From 2ababa9c5f85c90e083525e23ca7f185885326c6 Mon Sep 17 00:00:00 2001 From: Vebjorn Myklebust Date: Sun, 27 Aug 2023 21:29:53 +0200 Subject: [PATCH 1/7] simplelink: ti: devices: Add support for CC2340R5 Add initial lpf3 content to support cc2340r5. Currently, this includes files necessary to support power management and drivers. All files are added seperately from lpf2 content, which introduces a new folder structure in the TI HAL. Signed-off-by: Vebjorn Myklebust Signed-off-by: Lars Thalian Morstad Signed-off-by: Stoyan Bogdanov --- CMakeLists.txt | 1 + simplelink_lpf3/CMakeLists.txt | 31 + .../kernel/zephyr/dpl/ClockP_zephyr.c | 200 + .../kernel/zephyr/dpl/HwiP_zephyr.c | 184 + .../source/ti/devices/CMakeLists.txt | 1 + .../source/ti/devices/DeviceFamily.h | 260 + .../source/ti/devices/cc23x0r5/CMakeLists.txt | 45 + .../ti/devices/cc23x0r5/cmsis/cc23x0r5.h | 52 + .../cc23x0r5/cmsis/core/cmsis_compiler.h | 282 + .../devices/cc23x0r5/cmsis/core/cmsis_gcc.h | 2177 ++++++ .../cc23x0r5/cmsis/core/cmsis_iccarm.h | 969 +++ .../cc23x0r5/cmsis/core/cmsis_version.h | 39 + .../cc23x0r5/cmsis/core/core_cm0plus.h | 1087 +++ .../ti/devices/cc23x0r5/driverlib/adc.c | 401 + .../ti/devices/cc23x0r5/driverlib/adc.h | 661 ++ .../ti/devices/cc23x0r5/driverlib/aes.h | 692 ++ .../ti/devices/cc23x0r5/driverlib/aes_gcc.s | 231 + .../ti/devices/cc23x0r5/driverlib/aes_iar.s | 214 + .../devices/cc23x0r5/driverlib/aes_ticlang.s | 231 + .../ti/devices/cc23x0r5/driverlib/chipinfo.h | 143 + .../ti/devices/cc23x0r5/driverlib/ckmd.h | 642 ++ .../ti/devices/cc23x0r5/driverlib/copylist.h | 203 + .../ti/devices/cc23x0r5/driverlib/cpu.c | 97 + .../ti/devices/cc23x0r5/driverlib/cpu.h | 120 + .../ti/devices/cc23x0r5/driverlib/cpu_doc.h | 41 + .../ti/devices/cc23x0r5/driverlib/debug.c | 53 + .../ti/devices/cc23x0r5/driverlib/debug.h | 82 + .../ti/devices/cc23x0r5/driverlib/flash.h | 307 + .../ti/devices/cc23x0r5/driverlib/gpio.c | 38 + .../ti/devices/cc23x0r5/driverlib/gpio.h | 601 ++ .../ti/devices/cc23x0r5/driverlib/gpio_doc.h | 80 + .../ti/devices/cc23x0r5/driverlib/hapi.h | 487 ++ .../ti/devices/cc23x0r5/driverlib/i2c.c | 103 + .../ti/devices/cc23x0r5/driverlib/i2c.h | 844 ++ .../ti/devices/cc23x0r5/driverlib/interrupt.c | 380 + .../ti/devices/cc23x0r5/driverlib/interrupt.h | 410 + .../ti/devices/cc23x0r5/driverlib/lpcmp.c | 37 + .../ti/devices/cc23x0r5/driverlib/lpcmp.h | 383 + .../ti/devices/cc23x0r5/driverlib/lrfd.c | 118 + .../ti/devices/cc23x0r5/driverlib/lrfd.h | 154 + .../ti/devices/cc23x0r5/driverlib/pmctl.h | 219 + .../ti/devices/cc23x0r5/driverlib/setup.c | 70 + .../ti/devices/cc23x0r5/driverlib/setup.h | 106 + .../ti/devices/cc23x0r5/driverlib/setup_doc.h | 38 + .../ti/devices/cc23x0r5/driverlib/sha256sw.h | 362 + .../cc23x0r5/driverlib/sha2sw_common.h | 139 + .../cc23x0r5/driverlib/sha2sw_config.h | 127 + .../ti/devices/cc23x0r5/driverlib/spi.c | 227 + .../ti/devices/cc23x0r5/driverlib/spi.h | 678 ++ .../ti/devices/cc23x0r5/driverlib/sw_chacha.c | 151 + .../cc23x0r5/driverlib/sw_ecrypt-config.h | 277 + .../cc23x0r5/driverlib/sw_ecrypt-machine.h | 49 + .../cc23x0r5/driverlib/sw_ecrypt-portable.h | 278 + .../cc23x0r5/driverlib/sw_ecrypt-sync.h | 248 + .../cc23x0r5/driverlib/sw_poly1305-donna-32.h | 260 + .../cc23x0r5/driverlib/sw_poly1305-donna.c | 182 + .../cc23x0r5/driverlib/sw_poly1305-donna.h | 24 + .../ti/devices/cc23x0r5/driverlib/systick.c | 38 + .../ti/devices/cc23x0r5/driverlib/systick.h | 276 + .../devices/cc23x0r5/driverlib/systick_doc.h | 65 + .../ti/devices/cc23x0r5/driverlib/tempdiode.c | 323 + .../ti/devices/cc23x0r5/driverlib/tempdiode.h | 109 + .../ti/devices/cc23x0r5/driverlib/uart.c | 107 + .../ti/devices/cc23x0r5/driverlib/uart.h | 730 ++ .../ti/devices/cc23x0r5/driverlib/udma.c | 326 + .../ti/devices/cc23x0r5/driverlib/udma.h | 956 +++ .../source/ti/devices/cc23x0r5/inc/asmdefs.h | 149 + .../source/ti/devices/cc23x0r5/inc/hw_adc.h | 2714 +++++++ .../source/ti/devices/cc23x0r5/inc/hw_aes.h | 1341 ++++ .../source/ti/devices/cc23x0r5/inc/hw_bpu.h | 485 ++ .../source/ti/devices/cc23x0r5/inc/hw_ccfg.h | 236 + .../source/ti/devices/cc23x0r5/inc/hw_ckmd.h | 3564 +++++++++ .../ti/devices/cc23x0r5/inc/hw_clkctl.h | 823 ++ .../source/ti/devices/cc23x0r5/inc/hw_dbgss.h | 1082 +++ .../source/ti/devices/cc23x0r5/inc/hw_dcb.h | 272 + .../ti/devices/cc23x0r5/inc/hw_device.h | 114 + .../source/ti/devices/cc23x0r5/inc/hw_dma.h | 572 ++ .../ti/devices/cc23x0r5/inc/hw_evtsvt.h | 4678 +++++++++++ .../ti/devices/cc23x0r5/inc/hw_evtull.h | 291 + .../source/ti/devices/cc23x0r5/inc/hw_fcfg.h | 653 ++ .../source/ti/devices/cc23x0r5/inc/hw_flash.h | 1204 +++ .../source/ti/devices/cc23x0r5/inc/hw_gpio.h | 6737 ++++++++++++++++ .../source/ti/devices/cc23x0r5/inc/hw_i2c.h | 710 ++ .../source/ti/devices/cc23x0r5/inc/hw_ints.h | 105 + .../source/ti/devices/cc23x0r5/inc/hw_ioc.h | 4278 +++++++++++ .../source/ti/devices/cc23x0r5/inc/hw_lgpt.h | 3125 ++++++++ .../source/ti/devices/cc23x0r5/inc/hw_lgpt1.h | 316 + .../source/ti/devices/cc23x0r5/inc/hw_lgpt3.h | 407 + .../ti/devices/cc23x0r5/inc/hw_lrfddbell.h | 6818 +++++++++++++++++ .../ti/devices/cc23x0r5/inc/hw_lrfdrxf.h | 62 + .../ti/devices/cc23x0r5/inc/hw_lrfdtxf.h | 62 + .../ti/devices/cc23x0r5/inc/hw_memmap.h | 105 + .../devices/cc23x0r5/inc/hw_memmap_common.h | 51 + .../source/ti/devices/cc23x0r5/inc/hw_nvic.h | 397 + .../ti/devices/cc23x0r5/inc/hw_platform.h | 88 + .../source/ti/devices/cc23x0r5/inc/hw_pmctl.h | 754 ++ .../source/ti/devices/cc23x0r5/inc/hw_pmud.h | 930 +++ .../source/ti/devices/cc23x0r5/inc/hw_rtc.h | 520 ++ .../source/ti/devices/cc23x0r5/inc/hw_scb.h | 368 + .../source/ti/devices/cc23x0r5/inc/hw_scscs.h | 261 + .../source/ti/devices/cc23x0r5/inc/hw_spi.h | 1822 +++++ .../source/ti/devices/cc23x0r5/inc/hw_sys0.h | 832 ++ .../ti/devices/cc23x0r5/inc/hw_sysctl.h | 47 + .../ti/devices/cc23x0r5/inc/hw_systick.h | 158 + .../ti/devices/cc23x0r5/inc/hw_systim.h | 1436 ++++ .../source/ti/devices/cc23x0r5/inc/hw_types.h | 94 + .../source/ti/devices/cc23x0r5/inc/hw_uart.h | 1137 +++ .../source/ti/devices/cc23x0r5/inc/hw_vims.h | 604 ++ .../source/ti/drivers/BatteryMonitor.h | 546 ++ simplelink_lpf3/source/ti/drivers/Board.h | 99 + simplelink_lpf3/source/ti/drivers/Power.h | 961 +++ .../source/ti/drivers/Temperature.c | 79 + .../source/ti/drivers/Temperature.h | 550 ++ .../batterymonitor/BatMonSupportLPF3.c | 170 + .../batterymonitor/BatMonSupportLPF3.h | 193 + .../batterymonitor/BatteryMonitorLPF3.c | 484 ++ .../batterymonitor/BatteryMonitorLPF3.h | 76 + .../source/ti/drivers/dpl/ClockP.h | 328 + .../source/ti/drivers/dpl/DebugP.h | 170 + simplelink_lpf3/source/ti/drivers/dpl/HwiP.h | 294 + .../source/ti/drivers/power/PowerCC23X0.c | 1226 +++ .../source/ti/drivers/power/PowerCC23X0.h | 456 ++ .../ti/drivers/temperature/TemperatureLPF3.c | 663 ++ .../ti/drivers/temperature/TemperatureLPF3.h | 137 + .../source/ti/drivers/utils/List.c | 182 + .../source/ti/drivers/utils/List.h | 269 + .../source/ti/drivers/utils/Math.c | 50 + .../source/ti/drivers/utils/Math.h | 111 + 128 files changed, 76892 insertions(+) create mode 100644 simplelink_lpf3/CMakeLists.txt create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c create mode 100644 simplelink_lpf3/source/ti/devices/CMakeLists.txt create mode 100644 simplelink_lpf3/source/ti/devices/DeviceFamily.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/cc23x0r5.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_compiler.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_gcc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_iccarm.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_version.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/core_cm0plus.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_gcc.s create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_iar.s create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_ticlang.s create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/chipinfo.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/copylist.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu_doc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/flash.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio_doc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup_doc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha256sw.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_common.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_config.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_chacha.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-config.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-machine.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-portable.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-sync.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna-32.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick_doc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/asmdefs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_adc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_aes.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_bpu.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ckmd.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_clkctl.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dbgss.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dcb.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dma.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtsvt.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtull.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_flash.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_gpio.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_i2c.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ints.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ioc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt1.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt3.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap_common.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_nvic.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_platform.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmctl.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_rtc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scb.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scscs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sysctl.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systick.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systim.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_uart.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_vims.h create mode 100644 simplelink_lpf3/source/ti/drivers/BatteryMonitor.h create mode 100644 simplelink_lpf3/source/ti/drivers/Board.h create mode 100644 simplelink_lpf3/source/ti/drivers/Power.h create mode 100644 simplelink_lpf3/source/ti/drivers/Temperature.c create mode 100644 simplelink_lpf3/source/ti/drivers/Temperature.h create mode 100644 simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/ClockP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/DebugP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/HwiP.h create mode 100644 simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c create mode 100644 simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h create mode 100644 simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/utils/List.c create mode 100644 simplelink_lpf3/source/ti/drivers/utils/List.h create mode 100644 simplelink_lpf3/source/ti/drivers/utils/Math.c create mode 100644 simplelink_lpf3/source/ti/drivers/utils/Math.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 71592eef..1d923360 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1 +1,2 @@ add_subdirectory(simplelink) +add_subdirectory(simplelink_lpf3) diff --git a/simplelink_lpf3/CMakeLists.txt b/simplelink_lpf3/CMakeLists.txt new file mode 100644 index 00000000..0cb416bc --- /dev/null +++ b/simplelink_lpf3/CMakeLists.txt @@ -0,0 +1,31 @@ +add_subdirectory(source/ti/devices) + +if(CONFIG_HAS_CC23X0_SDK) + + if(CONFIG_SOC_CC2340R5) + zephyr_compile_definitions(DeviceFamily_CC23X0R5 ${COMPILER}) + endif() + + zephyr_include_directories( + . + source + ) + + zephyr_library() + zephyr_library_compile_definitions(${COMPILER}) + zephyr_library_sources( + # Utils + source/ti/drivers/utils/List.c + + # Drivers + source/ti/drivers/Temperature.c + source/ti/drivers/power/PowerCC23X0.c + source/ti/drivers/temperature/TemperatureLPF3.c + source/ti/drivers/batterymonitor/BatMonSupportLPF3.c + source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c + + # DPL + kernel/zephyr/dpl/ClockP_zephyr.c + kernel/zephyr/dpl/HwiP_zephyr.c + ) +endif() diff --git a/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c new file mode 100644 index 00000000..8fb7cd5c --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/* + * ClockP_STRUCT_SIZE in ClockP.h must be updated to match the size of this + * struct + */ +typedef struct _ClockP_Obj +{ + struct k_timer timer; + ClockP_Fxn clock_fxn; + uintptr_t arg; + uint32_t timeout; + uint32_t period; + bool active; +} ClockP_Obj; + +static ClockP_Params ClockP_defaultParams = { + .startFlag = false, + .period = 0, + .arg = 0, +}; + +static void expiry_fxn(struct k_timer *timer_id) +{ + ClockP_Obj *obj = (ClockP_Obj *)k_timer_user_data_get(timer_id); + + obj->clock_fxn(obj->arg); +} + +/* + * ======== ClockP_construct ======== + */ +ClockP_Handle ClockP_construct(ClockP_Struct *handle, ClockP_Fxn clockFxn, uint32_t timeout, ClockP_Params *params) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + if (handle == NULL) + { + return NULL; + } + + if (params == NULL) + { + params = &ClockP_defaultParams; + } + + obj->clock_fxn = clockFxn; + obj->arg = params->arg; + obj->period = params->period * ClockP_getSystemTickPeriod() / USEC_PER_MSEC; + obj->timeout = timeout; + obj->active = false; + + k_timer_init(&obj->timer, expiry_fxn, NULL); + k_timer_user_data_set(&obj->timer, obj); + + if (params->startFlag) + { + ClockP_start(obj); + } + + return ((ClockP_Handle)handle); +} + +/* + * ======== ClockP_getSystemTickPeriod ======== + */ +uint32_t ClockP_tickPeriod = (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC); +uint32_t ClockP_getSystemTickPeriod() +{ + return ClockP_tickPeriod; +} + +uint32_t ClockP_getSystemTicks() +{ + return (uint32_t)k_ms_to_ticks_ceil32(k_uptime_get_32()); +} + +/* + * ======== ClockP_Params_init ======== + */ +void ClockP_Params_init(ClockP_Params *params) +{ + params->arg = 0; + params->startFlag = false; + params->period = 0; +} + +/* + * ======== ClockP_setTimeout ======== + */ +void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + obj->timeout = timeout; +} + +/* + * ======== ClockP_start ======== + */ +void ClockP_start(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + int32_t timeout; + int32_t period; + + __ASSERT_NO_MSG(obj->timeout / CONFIG_SYS_CLOCK_TICKS_PER_SEC <= UINT32_MAX / USEC_PER_MSEC); + __ASSERT_NO_MSG(obj->period / CONFIG_SYS_CLOCK_TICKS_PER_SEC <= UINT32_MAX / USEC_PER_MSEC); + + /* Avoid overflow */ + if (obj->timeout > UINT32_MAX / USEC_PER_MSEC) + { + timeout = obj->timeout / CONFIG_SYS_CLOCK_TICKS_PER_SEC * USEC_PER_MSEC; + } + else if ((obj->timeout != 0) && (obj->timeout < CONFIG_SYS_CLOCK_TICKS_PER_SEC / USEC_PER_MSEC)) + { + /* For small timeouts we use 1 msec */ + timeout = 1; + } + else + { + timeout = obj->timeout * USEC_PER_MSEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC; + } + + if (obj->period > UINT32_MAX / USEC_PER_MSEC) + { + period = obj->period / CONFIG_SYS_CLOCK_TICKS_PER_SEC * USEC_PER_MSEC; + } + else if ((obj->period != 0) && (obj->period < CONFIG_SYS_CLOCK_TICKS_PER_SEC / USEC_PER_MSEC)) + { + period = 1; + } + else + { + period = obj->period * USEC_PER_MSEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC; + } + + k_timer_start(&obj->timer, K_MSEC(timeout), K_MSEC(period)); + + obj->active = true; +} + +/* + * ======== ClockP_stop ======== + */ +void ClockP_stop(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + k_timer_stop(&obj->timer); + obj->active = false; +} + +/* + * ======== ClockP_usleep ======== + */ +void ClockP_usleep(uint32_t usec) +{ + k_sleep(K_USEC(usec)); +} + +/* + * ======== ClockP_getTimeout ======== + */ +uint32_t ClockP_getTimeout(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + return k_timer_remaining_get(&obj->timer) * CONFIG_SYS_CLOCK_TICKS_PER_SEC / USEC_PER_MSEC; +} + +/* + * ======== ClockP_isActive ======== + */ +bool ClockP_isActive(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + return obj->active; +} + +void ClockP_destruct(ClockP_Struct *clockP) +{ + ClockP_Obj *obj = (ClockP_Obj *)clockP->data; + + obj->clock_fxn = NULL; + obj->arg = 0; + obj->period = 0; + obj->timeout = 0; + obj->active = false; + + k_timer_stop(&obj->timer); +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c new file mode 100644 index 00000000..74f9573a --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include + +#include + +/* + * IRQ_CONNECT requires we know the ISR signature and argument + * at build time; whereas SimpleLink plugs the interrupts + * at run time, so we create an ISR shim, and register that. + * The callback argument doesn't change after the ISR is registered. + */ +struct sl_isr_args +{ + HwiP_Fxn cb; + uintptr_t arg; +}; + +static void sl_isr(const void *isr_arg) +{ + HwiP_Fxn cb = ((struct sl_isr_args *)isr_arg)->cb; + uintptr_t arg = ((struct sl_isr_args *)isr_arg)->arg; + + /* Call the SimpleLink ISR Handler: */ + if (cb) + { + cb(arg); + } +} + +typedef struct _HwiP_Obj +{ + uint32_t intNum; + struct sl_isr_args *cb; +} HwiP_Obj; + +static struct sl_isr_args sl_IRQ03_cb = {NULL, 0}; +static struct sl_isr_args sl_IRQ16_cb = {NULL, 0}; + +/* + * ======== HwiP_construct ======== + */ +HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Obj *obj = (HwiP_Obj *)handle; + uintptr_t arg = 0; + uint8_t priority = INT_PRI_LEVEL3; /* default to lowest priority */ + + if (handle == NULL) + { + return NULL; + } + + if (params) + { + priority = params->priority & 0xFF; + arg = params->arg; + } + + /* + * Currently only support INT_CPUIRQ3 (Oscillator ISR) and INT_CPUIRQ16 + * (Batmon ISR) + */ + __ASSERT(INT_CPUIRQ3 == interruptNum || INT_CPUIRQ16 == interruptNum, + "Unexpected interruptNum: %d\r\n", + interruptNum); + + /* + * Priority expected is either: + * INT_PRI_LEVEL0 to INT_PRI_LEVEL3, + * or ~0 or 255 (meaning lowest priority) + * ~0 and 255 are meant to be the same as INT_PRI_LEVEL3. + */ + __ASSERT((INT_PRI_LEVEL0 == priority) || (INT_PRI_LEVEL3 == priority) || (INT_PRI_LEVEL2 == priority) || + (INT_PRI_LEVEL1 == priority) || (0xFF == priority), + "Unexpected priority level, got: 0x%x\r\n", + (unsigned int)priority); + + if (0xFF == priority) + { + priority = INT_PRI_LEVEL3; + } + + /* The priority for IRQ_CONNECT is encoded in the top 2 bits */ + priority = (priority >> 6); + + switch (interruptNum) + { + case INT_CPUIRQ3: + sl_IRQ03_cb.cb = hwiFxn; + sl_IRQ03_cb.arg = arg; + obj->cb = &sl_IRQ03_cb; + irq_connect_dynamic(INT_CPUIRQ3 - 16, priority, sl_isr, &sl_IRQ03_cb, 0); + break; + case INT_CPUIRQ16: + sl_IRQ16_cb.cb = hwiFxn; + sl_IRQ16_cb.arg = arg; + obj->cb = &sl_IRQ16_cb; + irq_connect_dynamic(INT_CPUIRQ16 - 16, priority, sl_isr, &sl_IRQ16_cb, 0); + break; + default: + return (NULL); + } + irq_enable(interruptNum - 16); + + obj->intNum = interruptNum; + + return (HwiP_Handle)handle; +} + +void HwiP_Params_init(HwiP_Params *params) +{ + params->arg = 0; + params->priority = ~0; +} + +/* Zephyr has no functions for clearing an interrupt, so use driverlib: */ +void HwiP_clearInterrupt(int interruptNum) +{ + IntClearPend((uint32_t)interruptNum); +} + +void HwiP_enableInterrupt(int interruptNum) +{ + irq_enable(interruptNum - 16); +} + +void HwiP_disableInterrupt(int interruptNum) +{ + irq_disable(interruptNum - 16); +} + +uintptr_t HwiP_disable(void) +{ + uintptr_t key; + + key = irq_lock(); + + return (key); +} + +void HwiP_restore(uintptr_t key) +{ + irq_unlock(key); +} + +void HwiP_post(int interruptNum) +{ + IntSetPend((uint32_t)interruptNum); +} + +void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP; + + uintptr_t key = HwiP_disable(); + + obj->cb->cb = fxn; + obj->cb->arg = arg; + + HwiP_restore(key); +} + +void HwiP_destruct(HwiP_Struct *hwiP) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP->data; + + int interruptNum = obj->intNum; + + irq_disable(interruptNum - 16); + + obj->cb->cb = NULL; + obj->cb->arg = (uintptr_t)NULL; + obj->cb = NULL; +} diff --git a/simplelink_lpf3/source/ti/devices/CMakeLists.txt b/simplelink_lpf3/source/ti/devices/CMakeLists.txt new file mode 100644 index 00000000..58b53e66 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory_ifdef(CONFIG_HAS_CC23X0_SDK cc23x0r5) \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/DeviceFamily.h b/simplelink_lpf3/source/ti/devices/DeviceFamily.h new file mode 100644 index 00000000..a9c1d955 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/DeviceFamily.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DeviceFamily.h + * + * @brief Infrastructure to select correct driverlib path and identify devices + * + * This module enables the selection of the correct driverlib path for the current + * device. It also facilitates the use of per-device conditional compilation + * to enable minor variations in drivers between devices. + * + * In order to use this functionality, DeviceFamily_XYZ must be defined as one of + * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines + * are set based on DeviceFamily_XYZ. + */ + +#ifndef ti_devices_DeviceFamily__include +#define ti_devices_DeviceFamily__include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * DeviceFamily_ID_XYZ values. + * + * DeviceFamily_ID may be used in the preprocessor for conditional compilation. + * DeviceFamily_ID is set to one of these values based on the top level + * DeviceFamily_XYZ define. + */ +#define DeviceFamily_ID_CC13X0 1 +#define DeviceFamily_ID_CC26X0 2 +#define DeviceFamily_ID_CC26X0R2 3 +#define DeviceFamily_ID_CC13X2 4 +#define DeviceFamily_ID_CC26X2 5 +#define DeviceFamily_ID_CC3200 6 +#define DeviceFamily_ID_CC3220 7 +#define DeviceFamily_ID_CC13X1 8 +#define DeviceFamily_ID_CC26X1 9 +#define DeviceFamily_ID_CC13X2X7 10 +#define DeviceFamily_ID_CC26X2X7 11 +#define DeviceFamily_ID_CC13X1_CC26X1 12 +#define DeviceFamily_ID_CC13X2_CC26X2 13 +#define DeviceFamily_ID_CC13X2X7_CC26X2X7 14 +#define DeviceFamily_ID_CC13X4_CC26X4 15 +#define DeviceFamily_ID_CC13X4 16 +#define DeviceFamily_ID_CC26X4 17 +#define DeviceFamily_ID_CC26X3 18 +#define DeviceFamily_ID_CC23X0R5 19 +#define DeviceFamily_ID_CC23X0R2 20 +#define DeviceFamily_ID_CC27XX 21 +#define DeviceFamily_ID_CC35XX 22 +#define DeviceFamily_ID_CC33XX 23 + +/* + * DeviceFamily_PARENT_XYZ values. + * + * DeviceFamily_PARENT may be used in the preprocessor for conditional + * compilation. DeviceFamily_PARENT is set to one of these values based + * on the top-level DeviceFamily_XYZ define. + */ +#define DeviceFamily_PARENT_CC13X0_CC26X0 1 +#define DeviceFamily_PARENT_CC13X2_CC26X2 2 +#define DeviceFamily_PARENT_CC13X1_CC26X1 3 +#define DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 4 +#define DeviceFamily_PARENT_CC32XX 5 +#define DeviceFamily_PARENT_CC23X0 6 +#define DeviceFamily_PARENT_CC27XX 7 +#define DeviceFamily_PARENT_CC35XX 8 + +/* + * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and + * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. + * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If + * multiple DeviceFamily_XYZ are defined, the first one encountered is used. + */ +#if defined(DeviceFamily_CC13X0) + #define DeviceFamily_ID DeviceFamily_ID_CC13X0 + #define DeviceFamily_DIRECTORY cc13x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC13X1) + #define DeviceFamily_ID DeviceFamily_ID_CC13X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC13X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X4) + #define DeviceFamily_ID DeviceFamily_ID_CC13X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC26X0) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0 + #define DeviceFamily_DIRECTORY cc26x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 + #define DeviceFamily_DIRECTORY cc26x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X1) + #define DeviceFamily_ID DeviceFamily_ID_CC26X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X3) + /* The CC2653 is very similar to CC26X4 from a software point of view, + * so we use the same directory and parent defines. + */ + #define DeviceFamily_ID DeviceFamily_ID_CC26X3 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC26X4) + #define DeviceFamily_ID DeviceFamily_ID_CC26X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC23X0R5) + #define DeviceFamily_ID DeviceFamily_ID_CC23X0R5 + #define DeviceFamily_DIRECTORY cc23x0r5 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC23X0 + +#elif defined(DeviceFamily_CC23X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC23X0R2 + #define DeviceFamily_DIRECTORY cc23x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC23X0 + +#elif defined(DeviceFamily_CC27XX) + #define DeviceFamily_ID DeviceFamily_ID_CC27XX + #define DeviceFamily_DIRECTORY cc27xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC27XX + +#elif defined(DeviceFamily_CC13X1_CC26X1) + #define DeviceFamily_ID DeviceFamily_ID_CC13X1_CC26X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC13X2_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2X7_CC26X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2X7_CC26X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X4_CC26X4) + #define DeviceFamily_ID DeviceFamily_ID_CC13X4_CC26X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC3200) + #define DeviceFamily_ID DeviceFamily_ID_CC3200 + #define DeviceFamily_DIRECTORY cc32xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC32XX + +#elif defined(DeviceFamily_CC3220) + #define DeviceFamily_ID DeviceFamily_ID_CC3220 + #define DeviceFamily_DIRECTORY cc32xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC32XX + +#elif defined(DeviceFamily_CC35XX) + #define DeviceFamily_ID DeviceFamily_ID_CC35XX + #define DeviceFamily_DIRECTORY cc35xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC35XX + +#elif defined(DeviceFamily_CC33XX) + #define DeviceFamily_ID DeviceFamily_ID_CC33XX + #define DeviceFamily_DIRECTORY cc33xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC35XX + +#else + #error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!" +#endif + +/* Ensure that only one DeviceFamily was specified */ +#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X1) + defined(DeviceFamily_CC13X2) + \ + defined(DeviceFamily_CC13X2X7) + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) + \ + defined(DeviceFamily_CC26X1) + defined(DeviceFamily_CC26X2) + defined(DeviceFamily_CC26X2X7) + \ + defined(DeviceFamily_CC26X3) + defined(DeviceFamily_CC26X4) + defined(DeviceFamily_CC13X4) + \ + defined(DeviceFamily_CC23X0R5) + defined(DeviceFamily_CC23X0R2) + defined(DeviceFamily_CC27XX) + \ + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) + defined(DeviceFamily_CC35XX) + \ + defined(DeviceFamily_CC33XX)) > 1 + #error More then one DeviceFamily has been defined! +#endif + +/*! + * @brief Macro to include correct driverlib path. + * + * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined + * first. + * + * @param x A token containing the path of the file to include based on + * the root device folder. The preceding forward slash must be + * omitted. For example: + * - #include DeviceFamily_constructPath(inc/hw_memmap.h) + * - #include DeviceFamily_constructPath(driverlib/uart.h) + * + * @return Returns an include path. + * + */ +#define DeviceFamily_constructPath(x) + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_DeviceFamily__include */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt new file mode 100644 index 00000000..f3893b95 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt @@ -0,0 +1,45 @@ +# Copyright (c) 2022-2024, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# All targets in this file are for Cortex-M0P + +zephyr_include_directories( + . + ) + +zephyr_library() + +zephyr_library_sources( + driverlib/gpio.c + driverlib/interrupt.c + driverlib/lrfd.c + driverlib/setup.c + driverlib/uart.c + ) diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/cc23x0r5.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/cc23x0r5.h new file mode 100644 index 00000000..8c46c4c2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/cc23x0r5.h @@ -0,0 +1,52 @@ +/****************************************************************************** +* Filename: cc23x0r5.h +* +* Description: Collection of architecture definitions for CC23x0R5 devices +* +// ##### LICENSE HEADER ##### +* +******************************************************************************/ +#ifndef __CC23X0R5_H__ +#define __CC23X0R5_H__ + +/* IRQ numbers */ +typedef enum IRQn +{ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + CPUIRQ0_IRQn = 0, /* 16 CPUIRQ0 configurable source */ + CPUIRQ1_IRQn = 1, /* 17 CPUIRQ1 configurable source */ + CPUIRQ2_IRQn = 2, /* 18 CPUIRQ2 configurable source */ + CPUIRQ3_IRQn = 3, /* 19 CPUIRQ3 configurable source */ + CPUIRQ4_IRQn = 4, /* 20 CPUIRQ4 configurable source */ + GPIO_COMB_IRQn = 5, /* 21 GPIO event interrupt */ + LRFD_IRQ0_IRQn = 6, /* 22 LRF interrupt 0 */ + LRFD_IRQ1_IRQn = 7, /* 23 LRF interrupt 1 */ + DMA_DONE_COMB_IRQn = 8, /* 24 uDMA done events */ + AES_COMB_IRQn = 9, /* 25 AES interrupt */ + SPI0_COMB_IRQn = 10, /* 26 SPI0 combined interrupt */ + UART0_COMB_IRQn = 11, /* 27 UART0 combined interrupt */ + I2C0_IRQ_IRQn = 12, /* 28 I2C0 combined interrupt */ + LGPT0_COMB_IRQn = 13, /* 29 LGPT0 interrupt */ + LGPT1_COMB_IRQn = 14, /* 30 LGPT1 interrupt */ + ADC_COMB_IRQn = 15, /* 31 ADC0 interrupt */ + CPUIRQ16_IRQn = 16, /* 32 CPUIRQ16 configurable source */ + LGPT2_COMB_IRQn = 17, /* 33 LGPT0 interrupt */ + LGPT3_COMB_IRQn = 18, /* 34 LGPT1 interrupt */ +} IRQn_Type; + +/* Architecture-specific constants */ +#define __SAUREGION_PRESENT 0x0000U /* SAU present */ +#define __DSP_PRESENT 0x0000U /* DSP extension present */ +#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0x0000U /* MPU present or not */ +#define __FPU_PRESENT 0x0000U /* FPU present or not */ +#define __VTOR_PRESENT 0x0001U /* VTOR present */ +#define __NVIC_PRIO_BITS 0x0002U /* 2 NVIC priority bits */ + +#include "core/core_cm0plus.h" + +#endif // #ifndef __CC23X0R5_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_compiler.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_compiler.h new file mode 100644 index 00000000..29e9b675 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_compiler.h @@ -0,0 +1,282 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) || defined(__clang__) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include "cmsis_ccs.h" + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_gcc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_gcc.h new file mode 100644 index 00000000..33aea6d9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] val Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] val Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_iccarm.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_iccarm.h new file mode 100644 index 00000000..58e8e360 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_iccarm.h @@ -0,0 +1,969 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2020 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_version.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_version.h new file mode 100644 index 00000000..2f048e45 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/core_cm0plus.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/core_cm0plus.h new file mode 100644 index 00000000..303c8a9f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/cmsis/core/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) || defined(__clang__) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE_CMSIS (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE_CMSIS (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE_CMSIS ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE_CMSIS ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.c new file mode 100644 index 00000000..14f61865 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.c @@ -0,0 +1,401 @@ +/****************************************************************************** + * Filename: adc.c + * + * Description: Driver for the ADC. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "adc.h" + +//***************************************************************************** +// +// Sets the clock-divider value, and sample duration +// +//***************************************************************************** +void ADCSetSampleDuration(uint32_t clkDiv, uint16_t clkCycles) +{ + uint32_t tempCtl; + + // Read current control register + tempCtl = HWREG(ADC_BASE + ADC_O_CTL0); + + /* Clear clk-div bits */ + tempCtl &= ~(ADC_CTL0_SCLKDIV_M); + + /* Set clk-div bits from argument */ + tempCtl |= (clkDiv & ADC_CTL0_SCLKDIV_M); + + /* Write back control register */ + HWREG(ADC_BASE + ADC_O_CTL0) = tempCtl; + + /* write sample-duration */ + HWREG(ADC_BASE + ADC_O_SCOMP0) = (clkCycles & ADC_SCOMP0_VAL_M); +} + +//***************************************************************************** +// +// Sets the ADC bit resolution +// +//***************************************************************************** +void ADCSetResolution(uint32_t resolution) +{ + uint32_t tempCtl; + + // Read current control register + tempCtl = HWREG(ADC_BASE + ADC_O_CTL2); + + /* Clear resolution bits */ + tempCtl &= ~(ADC_CTL2_RES_M); + + /* Set resolution bits from argument */ + tempCtl |= (resolution & ADC_CTL2_RES_M); + + /* Write back control register */ + HWREG(ADC_BASE + ADC_O_CTL2) = tempCtl; +} + +//***************************************************************************** +// +// Sets the ADC reference source and input channel +// +//***************************************************************************** +void ADCSetInput(uint32_t reference, uint8_t channel, uint32_t index) +{ + uint32_t tempCtl; + /* Set internal reference to disabled by default */ + uint32_t refCfg = ADC_REFCFG_REFEN_DIS; + + /* Read current control register */ + tempCtl = HWREG(ADC_BASE + ADC_O_MEMCTL0 + (4 * index)); + + /* Clear reference and channel bits */ + tempCtl &= ~(ADC_MEMCTL0_VRSEL_M | ADC_MEMCTL0_CHANSEL_M); + + /* Set channel */ + tempCtl |= (channel & ADC_MEMCTL0_CHANSEL_M); + + /* Set internal reference, if selected */ + if ((reference == ADC_FIXED_REFERENCE_1V4) || (reference == ADC_FIXED_REFERENCE_2V5)) + { + /* Enable internal reference, set bias current */ + refCfg = ADC_REFCFG_IBPROG_VAL0 | ADC_REFCFG_REFEN_EN; + + /* Set mem-ctrl register to use internal reference */ + tempCtl |= ADC_MEMCTL0_VRSEL_INTREF; + + /* Set internal reference voltage level */ + if (reference == ADC_FIXED_REFERENCE_1V4) + { + refCfg |= ADC_REFCFG_REFVSEL_V1P4; + } + else + { + refCfg |= ADC_REFCFG_REFVSEL_V2P5; + } + } + else if (reference == ADC_EXTERNAL_REFERENCE) + { + /* Set external reference */ + tempCtl |= ADC_MEMCTL0_VRSEL_EXTREF; + } + else + { + /* Neither internal, nor external reference pin selected. Set VDDS as reference */ + tempCtl |= ADC_MEMCTL0_VRSEL_VDDS; + } + + /* Write back control registers */ + HWREG(ADC_BASE + ADC_O_MEMCTL0 + (4 * index)) = tempCtl; + HWREG(ADC_BASE + ADC_O_REFCFG) = refCfg; +} + +//***************************************************************************** +// +// Triggers an ADC conversion +// +//***************************************************************************** +void ADCManualTrigger(void) +{ + uint32_t tempCtl; + + /* Enable conversion. This arms the peripheral and can now be triggered */ + HWREG(ADC_BASE + ADC_O_CTL0) |= ADC_CTL0_ENC_ON; + + /* Read current control register */ + tempCtl = HWREG(ADC_BASE + ADC_O_CTL1); + + /* Clear trigger-related fields */ + tempCtl &= ~(ADC_CTL1_SAMPMODE_M | ADC_CTL1_SC_M | ADC_CTL1_TRIGSRC_M); + + /* Set sampling-mode to automatic, and trigger source to software */ + tempCtl |= ADC_CTL1_SAMPMODE_AUTO | ADC_CTL1_TRIGSRC_SOFTWARE; + + /* Write back control register */ + HWREG(ADC_BASE + ADC_O_CTL1) = tempCtl; + + /* Trigger a conversion */ + HWREG(ADC_BASE + ADC_O_CTL1) |= ADC_CTL1_SC_START; +} + +//***************************************************************************** +// +// Set start and stop control registers +// +//***************************************************************************** +void ADCSetMemctlRange(uint32_t start, uint32_t stop) +{ + uint32_t tempCtl; + + /* Read current control register */ + tempCtl = HWREG(ADC_BASE + ADC_O_CTL2); + + /* Clear start and stop address bits */ + tempCtl &= ~(ADC_CTL2_ENDADD_M | ADC_CTL2_STARTADD_M); + + /* Set start and stop address bits */ + tempCtl |= (start << ADC_CTL2_STARTADD_S) & ADC_CTL2_STARTADD_M; + tempCtl |= (stop << ADC_CTL2_ENDADD_S) & ADC_CTL2_ENDADD_M; + + /* Write back control register */ + HWREG(ADC_BASE + ADC_O_CTL2) = tempCtl; +} + +//***************************************************************************** +// +// Set conversion sequence +// +//***************************************************************************** +void ADCSetSequence(uint32_t sequence) +{ + uint32_t tempCtl; + + /* Read current control register */ + tempCtl = HWREG(ADC_BASE + ADC_O_CTL1); + + /* Clear sequence bits */ + tempCtl &= ~(ADC_CTL1_CONSEQ_M); + + /* Set sequence bits */ + tempCtl |= sequence & ADC_CTL1_CONSEQ_M; + + /* Write back control register */ + HWREG(ADC_BASE + ADC_O_CTL1) = tempCtl; +} + +//***************************************************************************** +// +// Performs ADC value gain adjustment. +// +//***************************************************************************** +uint32_t ADCAdjustValueForGain(uint32_t adcValue, uint32_t bitResolution, uint16_t gain) +{ + uint32_t adcMaxCode; + uint32_t adjustedValue; + + /* Adjust value for gain and offset. Actual gain ratio is (gain/0x8000) */ + adjustedValue = ((adcValue * gain) + 0x4000) / 0x8000; + + /* Get threshold based on resolution */ + if (bitResolution == ADC_RESOLUTION_8_BIT) + { + adcMaxCode = 0xFF; + } + else if (bitResolution == ADC_RESOLUTION_10_BIT) + { + adcMaxCode = 0x3FF; + } + else /* Default to 12-bit */ + { + adcMaxCode = 0xFFF; + } + + /* Make sure no overflow occurs */ + if (adjustedValue > adcMaxCode) + { + adjustedValue = adcMaxCode; + } + + return (adjustedValue); +} + +//***************************************************************************** +// +// Convert ADC code to microvolts +// +//***************************************************************************** +uint32_t ADCValueToMicrovolts(uint32_t adcCode, uint32_t bitResolution, uint32_t referenceVoltageMicroVolt) +{ + uint32_t adcMaxCode; + uint32_t shift; + uint32_t microVolts; + + if (bitResolution == ADC_RESOLUTION_8_BIT) + { + adcMaxCode = 0xFF; + shift = 0; + } + else if (bitResolution == ADC_RESOLUTION_10_BIT) + { + adcMaxCode = 0x3FF; + shift = 2; + } + else /* Default to 12-bit */ + { + adcMaxCode = 0xFFF; + shift = 4; + } + + /* shift down voltage to avoid 32bit overflow */ + referenceVoltageMicroVolt >>= shift; + + /* Convert from code to microvolts */ + microVolts = (((adcCode * referenceVoltageMicroVolt) + (adcMaxCode >> 1)) / adcMaxCode); + + /* Shift result back up */ + microVolts <<= shift; + + return microVolts; +} + +//***************************************************************************** +// +// Get gain value for given reference source +// +//***************************************************************************** +uint16_t ADCGetAdjustmentGain(uint32_t reference) +{ + uint16_t gain; + + switch (reference) + { + /* 1.4V reference */ + case ADC_FIXED_REFERENCE_1V4: + + gain = fcfg->appTrims.cc23x0r5.adcGainWord1.adcGainIntref1P4V; + break; + + /* 2.5V reference */ + case ADC_FIXED_REFERENCE_2V5: + + gain = fcfg->appTrims.cc23x0r5.adcGainWord1.adcGainIntref2P5V; + break; + + /* External reference */ + case ADC_EXTERNAL_REFERENCE: + + gain = fcfg->appTrims.cc23x0r5.adcGainWord0.adcGainExtref; + break; + + /* VDDS reference */ + case ADC_VDDS_REFERENCE: + + gain = fcfg->appTrims.cc23x0r5.adcGainWord0.adcGainVdds; + break; + + default: + gain = 0x8000; + break; + } + + /* + * On an untrimmed device, the gain fields will read 0xFFFF. In this case, set the gain to unity (0x8000) + * The chance that an actual trimmed gain will be 0xFFFF is near zero. + */ + if (gain == 0xFFFF) + { + gain = 0x8000; + } + + return gain; +} + +//***************************************************************************** +// +// Set offset value in ADC peripheral +// +//***************************************************************************** +void ADCSetAdjustmentOffset(uint32_t reference) +{ + int8_t offset; + uint32_t tmute2_temp; + + switch (reference) + { + /* 1.4V reference */ + case ADC_FIXED_REFERENCE_1V4: + + offset = fcfg->appTrims.cc23x0r5.adcOffset.adcOffsetIntref1P4V; + break; + + /* 2.5V reference */ + case ADC_FIXED_REFERENCE_2V5: + + offset = fcfg->appTrims.cc23x0r5.adcOffset.adcOffsetIntref2P5V; + break; + + /* External reference */ + case ADC_EXTERNAL_REFERENCE: + + offset = fcfg->appTrims.cc23x0r5.adcOffset.adcOffsetExtref; + break; + + /* VDDS reference */ + case ADC_VDDS_REFERENCE: + + offset = fcfg->appTrims.cc23x0r5.adcOffset.adcOffsetVdds; + break; + + default: + offset = 0; + break; + } + + /* Read out current TMUTE2 register */ + tmute2_temp = HWREG(SYS0_BASE + SYS0_O_TMUTE2); + + /* Clear offset value in TMUTE2 */ + tmute2_temp &= ~(SYS0_TMUTE2_OFFSET_M); + + /* Sign-extend the offset value from 8-bit signed to 16-bit signed. Shift and mask, and place into tmute2_temp */ + tmute2_temp |= (((int16_t)offset) << SYS0_TMUTE2_OFFSET_S) & SYS0_TMUTE2_OFFSET_M; + + /* + * Unlock mutable registers to allow writing back tmute2. Register-write must follow within 32 clk-cycles, + * after which the mutable registers will be automatically locked. Key taken from hw_sys0.h + */ + HWREG(SYS0_BASE + SYS0_O_MUNLOCK) = 0xC5AF6927; + + /* Write back tmute2 register */ + HWREG(SYS0_BASE + SYS0_O_TMUTE2) = tmute2_temp; + + /* Lock the mutable registers by writing something other than the key */ + HWREG(SYS0_BASE + SYS0_O_MUNLOCK) = 0; +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h new file mode 100644 index 00000000..0c0bfea5 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h @@ -0,0 +1,661 @@ +/****************************************************************************** + * Filename: adc.h + * + * Description: Prototypes and defines for the ADC API. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include +#include "../inc/hw_adc.h" +#include "../inc/hw_fcfg.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_sys0.h" +#include "../inc/hw_types.h" + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +//***************************************************************************** +// +// Values +// +//***************************************************************************** + +//! \brief Set ADC clock to system clock divided by 1 +#define ADC_CLOCK_DIVIDER_1 ADC_CTL0_SCLKDIV_DIV_BY_1 + +//! \brief Set ADC clock to system clock divided by 2 +#define ADC_CLOCK_DIVIDER_2 ADC_CTL0_SCLKDIV_DIV_BY_2 + +//! \brief Set ADC clock to system clock divided by 4 +#define ADC_CLOCK_DIVIDER_4 ADC_CTL0_SCLKDIV_DIV_BY_4 + +//! \brief Set ADC clock to system clock divided by 8 +#define ADC_CLOCK_DIVIDER_8 ADC_CTL0_SCLKDIV_DIV_BY_8 + +//! \brief Set ADC clock to system clock divided by 16 +#define ADC_CLOCK_DIVIDER_16 ADC_CTL0_SCLKDIV_DIV_BY_16 + +//! \brief Set ADC clock to system clock divided by 24 +#define ADC_CLOCK_DIVIDER_24 ADC_CTL0_SCLKDIV_DIV_BY_24 + +//! \brief Set ADC clock to system clock divided by 32 +#define ADC_CLOCK_DIVIDER_32 ADC_CTL0_SCLKDIV_DIV_BY_32 + +//! \brief Set ADC clock to system clock divided by 48 +#define ADC_CLOCK_DIVIDER_48 ADC_CTL0_SCLKDIV_DIV_BY_48 + +//! \brief Set resolution of ADC conversion to 12 bit (unsigned) +#define ADC_RESOLUTION_12_BIT ADC_CTL2_RES_BIT_12 + +//! \brief Set resolution of ADC conversion to 10 bit (unsigned) +#define ADC_RESOLUTION_10_BIT ADC_CTL2_RES_BIT_10 + +//! \brief Set resolution of ADC conversion to 8 bit (unsigned) +#define ADC_RESOLUTION_8_BIT ADC_CTL2_RES_BIT_8 + +//! \brief Set ADC reference to internal fixed 1.4V +#define ADC_FIXED_REFERENCE_1V4 0 + +//! \brief Set ADC reference to internal fixed 2.5V +#define ADC_FIXED_REFERENCE_2V5 1 + +//! \brief Set ADC reference to external analog pin A1 +#define ADC_EXTERNAL_REFERENCE 2 + +//! \brief Set ADC reference to VDDS +#define ADC_VDDS_REFERENCE 3 + +//! \brief Set ADC conversion sequence to repeat control registers defined by start and stop address, +//! as set by \ref ADCSetMemctlRange +#define ADC_SEQUENCE_REPEATSEQUENCE ADC_CTL1_CONSEQ_REPEATSEQUENCE + +//! \brief Set ADC conversion sequence to repeat control register defined by start as set by \ref ADCSetMemctlRange +#define ADC_SEQUENCE_REPEATSINGLE ADC_CTL1_CONSEQ_REPEATSINGLE + +//! \brief Set ADC conversion sequence to a single pass of control registers defined by start and stop address, +//! as set by \ref ADCSetMemctlRange +#define ADC_SEQUENCE_SEQUENCE ADC_CTL1_CONSEQ_SEQUENCE + +//! \brief Set ADC conversion sequence to do a single conversion of control register defined by start, +//! as set by \ref ADCSetMemctlRange +#define ADC_SEQUENCE_SINGLE ADC_CTL1_CONSEQ_SINGLE + +//! \brief Result ready in memory result register 23 +#define ADC_INT_MEMRES_23 ADC_IMASK0_MEMRESIFG23 + +//! \brief Result ready in memory result register 22 +#define ADC_INT_MEMRES_22 ADC_IMASK0_MEMRESIFG22 + +//! \brief Result ready in memory result register 21 +#define ADC_INT_MEMRES_21 ADC_IMASK0_MEMRESIFG21 + +//! \brief Result ready in memory result register 20 +#define ADC_INT_MEMRES_20 ADC_IMASK0_MEMRESIFG20 + +//! \brief Result ready in memory result register 19 +#define ADC_INT_MEMRES_19 ADC_IMASK0_MEMRESIFG19 + +//! \brief Result ready in memory result register 18 +#define ADC_INT_MEMRES_18 ADC_IMASK0_MEMRESIFG18 + +//! \brief Result ready in memory result register 17 +#define ADC_INT_MEMRES_17 ADC_IMASK0_MEMRESIFG17 + +//! \brief Result ready in memory result register 16 +#define ADC_INT_MEMRES_16 ADC_IMASK0_MEMRESIFG16 + +//! \brief Result ready in memory result register 15 +#define ADC_INT_MEMRES_15 ADC_IMASK0_MEMRESIFG15 + +//! \brief Result ready in memory result register 14 +#define ADC_INT_MEMRES_14 ADC_IMASK0_MEMRESIFG14 + +//! \brief Result ready in memory result register 13 +#define ADC_INT_MEMRES_13 ADC_IMASK0_MEMRESIFG13 + +//! \brief Result ready in memory result register 12 +#define ADC_INT_MEMRES_12 ADC_IMASK0_MEMRESIFG12 + +//! \brief Result ready in memory result register 11 +#define ADC_INT_MEMRES_11 ADC_IMASK0_MEMRESIFG11 + +//! \brief Result ready in memory result register 10 +#define ADC_INT_MEMRES_10 ADC_IMASK0_MEMRESIFG10 + +//! \brief Result ready in memory result register 9 +#define ADC_INT_MEMRES_09 ADC_IMASK0_MEMRESIFG9 + +//! \brief Result ready in memory result register 8 +#define ADC_INT_MEMRES_08 ADC_IMASK0_MEMRESIFG8 + +//! \brief Result ready in memory result register 7 +#define ADC_INT_MEMRES_07 ADC_IMASK0_MEMRESIFG7 + +//! \brief Result ready in memory result register 6 +#define ADC_INT_MEMRES_06 ADC_IMASK0_MEMRESIFG6 + +//! \brief Result ready in memory result register 5 +#define ADC_INT_MEMRES_05 ADC_IMASK0_MEMRESIFG5 + +//! \brief Result ready in memory result register 4 +#define ADC_INT_MEMRES_04 ADC_IMASK0_MEMRESIFG4 + +//! \brief Result ready in memory result register 3 +#define ADC_INT_MEMRES_03 ADC_IMASK0_MEMRESIFG3 + +//! \brief Result ready in memory result register 2 +#define ADC_INT_MEMRES_02 ADC_IMASK0_MEMRESIFG2 + +//! \brief Result ready in memory result register 1 +#define ADC_INT_MEMRES_01 ADC_IMASK0_MEMRESIFG1 + +//! \brief Result ready in memory result register 0 +#define ADC_INT_MEMRES_00 ADC_IMASK0_MEMRESIFG0 + +//! \brief Ad-Hoc single conversion done +#define ADC_INT_ASCDONE ADC_IMASK0_ASCDONE + +//! \brief Conversion underflow +#define ADC_INT_UVIFG ADC_IMASK0_UVIFG + +//! \brief DMA transaction done +#define ADC_INT_DMADONE ADC_IMASK0_DMADONE + +//! \brief ADC result is inside window comparator range +#define ADC_INT_INIFG ADC_IMASK0_INIFG + +//! \brief ADC result is below window comparator range +#define ADC_INT_LOWIFG ADC_IMASK0_LOWIFG + +//! \brief ADC result is above window comparator range +#define ADC_INT_HIGHIFG ADC_IMASK0_HIGHIFG + +//! \brief Sequence conversion timeout overflow +#define ADC_INT_TOVIFG ADC_IMASK0_TOVIFG + +//! \brief Conversion overflow +#define ADC_INT_OVIFG ADC_IMASK0_OVIFG + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the clock-divider value, and sample duration +//! +//! This function sets the clock divider, which determines the ADC clock, +//! derived from the system clock, and sets the duration of a sample in +//! ADC-clock cycles +//! +//! \param clkDiv is the clock divider value +//! - \ref ADC_CLOCK_DIVIDER_1 +//! - \ref ADC_CLOCK_DIVIDER_2 +//! - \ref ADC_CLOCK_DIVIDER_4 +//! - \ref ADC_CLOCK_DIVIDER_8 +//! - \ref ADC_CLOCK_DIVIDER_16 +//! - \ref ADC_CLOCK_DIVIDER_24 +//! - \ref ADC_CLOCK_DIVIDER_32 +//! - \ref ADC_CLOCK_DIVIDER_48 +//! +//! \param clkCycles is the duration of a sample, in ADC-clock cycles. +//! Valid range of input is [0, 1023] +//! +//! \note +//! The numerical value of clkDiv is not the actual divider value. +//! See the list of possible arguments and which divider value they represent. +//! +//! \note +//! The minimum sampling time for the ADC is 250 ns. The clock-divider and sample +//! duration must be set accordingly to maintain this requirement. +//! +//! \return None +// +//***************************************************************************** +extern void ADCSetSampleDuration(uint32_t clkDiv, uint16_t clkCycles); + +//***************************************************************************** +// +//! \brief Sets the ADC bit resolution +//! +//! This function sets the resolution of the ADC conversion. +//! +//! \param resolution Bit resolution to be used in conversion +//! - \ref ADC_RESOLUTION_12_BIT +//! - \ref ADC_RESOLUTION_10_BIT +//! - \ref ADC_RESOLUTION_8_BIT +//! +//! \note +//! The resolution will affect how long a conversion will take. +//! - 12 bit: 14 clock cycles +//! - 10 bit: 12 clock cycles +//! - 8 bit: 9 clock cycles +//! +//! \return None +// +//***************************************************************************** +extern void ADCSetResolution(uint32_t resolution); + +//***************************************************************************** +// +//! \brief Sets the ADC reference source and input channel +//! +//! This function sets the ADC reference and input channel. The control register +//! index that the settings are applied to must also be passed as a parameter +//! +//! \param reference Reference source used in conversion +//! - \ref ADC_FIXED_REFERENCE_1V4 +//! - \ref ADC_FIXED_REFERENCE_2V5 +//! - \ref ADC_VDDS_REFERENCE +//! - \ref ADC_EXTERNAL_REFERENCE +//! +//! \param channel Internal channels that can be muxed to ADC. +//! Channels 0-11 correspond to analog pins 0-11. See device data for more information. +//! +//! \param index Index of which control register to write to. See device data for valid indexes. +//! +//! \return None +// +//***************************************************************************** +extern void ADCSetInput(uint32_t reference, uint8_t channel, uint32_t index); + +//***************************************************************************** +// +//! \brief Set start and stop control registers +//! +//! This function selects which control registers should be selected for +//! a conversion. Valid indexes are [0, 3]. For a single conversion, start and stop +//! should be set to the same. +//! +//! \param start the index of first control register used in sequence +//! \param stop the index of last control register used in sequence +//! +//! \return None +// +//***************************************************************************** +extern void ADCSetMemctlRange(uint32_t start, uint32_t stop); + +//***************************************************************************** +// +//! \brief Set conversion sequence +//! +//! This function sets the sequence for ADC conversions. The actual sequence is +//! defined by \ref ADCSetMemctlRange. For a single conversion, start and stop +//! should be set to the same. +//! +//! \param sequence +//! - \ref ADC_SEQUENCE_REPEATSEQUENCE +//! - \ref ADC_SEQUENCE_REPEATSINGLE +//! - \ref ADC_SEQUENCE_SEQUENCE +//! - \ref ADC_SEQUENCE_SINGLE +//! +//! \return None +// +//***************************************************************************** +extern void ADCSetSequence(uint32_t sequence); + +//***************************************************************************** +// +//! \brief Triggers an ADC conversion +//! +//! This function manually triggers an ADC conversion sequence, based on the +//! settings in the control registers in the start and stop range. See +//! \ref ADCSetMemctlRange and \ref ADCSetSequence +//! +//! \note It takes a minimum of 9 system-clock cycles for the BUSY-bit +//! in the STATUS register to go high after calling this function. +//! +//! \return None +// +//***************************************************************************** +extern void ADCManualTrigger(void); + +//***************************************************************************** +// +//! \brief Read conversion result from ADC +//! +//! This function blocks until a conversion is done, and returns data +//! from the given memory register. The index corresponds to the selected +//! control register used for the conversion +//! +//! \param index Index of which memory result register to read from +//! +//! \return Raw ADC conversion result +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCReadResult(uint32_t index) +{ + + while (HWREG(ADC_BASE + ADC_O_STA) & ADC_STA_BUSY_ACTIVE) {} + + /* Return data from result register */ + return HWREG(ADC_BASE + ADC_O_MEMRES0 + (4 * index)); +} + +//***************************************************************************** +// +//! \brief Check if ADC is busy +//! +//! This function returns whether the ADC is busy or not. +//! +//! \return ADC Busy status +//! true: ADC sampling or conversion is in progress. +//! false: No ADC sampling or conversion in progress. +//! +//! \note It takes a minimum of 9 system-clock cycles between writing to the +//! START-bit, and the BUSY-bit in the STATUS register going high +// +//***************************************************************************** +__STATIC_INLINE bool ADCIsBusy(void) +{ + + if (HWREG(ADC_BASE + ADC_O_STA) & ADC_STA_BUSY_ACTIVE) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +//! \brief Read conversion result from ADC +//! +//! This function returns data from the given memory register without blocking. +//! The index corresponds to the selected control register used for the conversion +//! +//! \param index Index of which memory result register to read from +//! +//! \return Raw ADC conversion result +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCReadResultNonBlocking(uint32_t index) +{ + /* Return data from result register */ + return HWREG(ADC_BASE + ADC_O_MEMRES0 + (4 * index)); +} + +//***************************************************************************** +// +//! \brief Convert ADC code to microvolts +//! +//! This function converts an adjusted ADC code to microvolts. Function arguments +//! also include bit resolution and reference voltage +//! +//! \param adcCode Raw adjusted adc code +//! \param bitResolution Bit resolution used in conversion +//! \param referenceVoltageMicroVolt Reference voltage (microvolts) +//! +//! \return ADC result in microvolts +// +//***************************************************************************** +extern uint32_t ADCValueToMicrovolts(uint32_t adcCode, uint32_t bitResolution, uint32_t referenceVoltageMicroVolt); + +//***************************************************************************** +// +//! \brief Enables individual ADC interrupt sources. +//! +//! This function enables the indicated ADC interrupt sources. +//! +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! - \ref ADC_INT_ASCDONE +//! - \ref ADC_INT_UVIFG +//! - \ref ADC_INT_DMADONE +//! - \ref ADC_INT_INIFG +//! - \ref ADC_INT_LOWIFG +//! - \ref ADC_INT_HIGHIFG +//! - \ref ADC_INT_TOVIFG +//! - \ref ADC_INT_OVIFG +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCEnableInterrupt(uint32_t intFlags) +{ + // Enable the specified interrupts. + HWREG(ADC_BASE + ADC_O_IMASK0) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual ADC interrupt sources. +//! +//! This function disables the indicated ADC interrupt sources. +//! +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! - \ref ADC_INT_ASCDONE +//! - \ref ADC_INT_UVIFG +//! - \ref ADC_INT_DMADONE +//! - \ref ADC_INT_INIFG +//! - \ref ADC_INT_LOWIFG +//! - \ref ADC_INT_HIGHIFG +//! - \ref ADC_INT_TOVIFG +//! - \ref ADC_INT_OVIFG +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCDisableInterrupt(uint32_t intFlags) +{ + // Disable the specified interrupts. + HWREG(ADC_BASE + ADC_O_IMASK0) &= ~(intFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current raw interrupt status. +//! +//! This function returns the raw interrupt status for the ADC +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! - \ref ADC_INT_ASCDONE +//! - \ref ADC_INT_UVIFG +//! - \ref ADC_INT_DMADONE +//! - \ref ADC_INT_INIFG +//! - \ref ADC_INT_LOWIFG +//! - \ref ADC_INT_HIGHIFG +//! - \ref ADC_INT_TOVIFG +//! - \ref ADC_INT_OVIFG +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCRawInterruptStatus(void) +{ + return (HWREG(ADC_BASE + ADC_O_RIS0)); +} + +//***************************************************************************** +// +//! \brief Gets the current masked interrupt status. +//! +//! This function returns the masked interrupt status for the ADC +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! - \ref ADC_INT_ASCDONE +//! - \ref ADC_INT_UVIFG +//! - \ref ADC_INT_DMADONE +//! - \ref ADC_INT_INIFG +//! - \ref ADC_INT_LOWIFG +//! - \ref ADC_INT_HIGHIFG +//! - \ref ADC_INT_TOVIFG +//! - \ref ADC_INT_OVIFG +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCMaskedInterruptStatus(void) +{ + return (HWREG(ADC_BASE + ADC_O_MIS0)); +} + +//***************************************************************************** +// +//! \brief Clears ADC interrupt sources. +//! +//! The specified ADC interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any +//! synchronizers) +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! - \ref ADC_INT_ASCDONE +//! - \ref ADC_INT_UVIFG +//! - \ref ADC_INT_DMADONE +//! - \ref ADC_INT_INIFG +//! - \ref ADC_INT_LOWIFG +//! - \ref ADC_INT_HIGHIFG +//! - \ref ADC_INT_TOVIFG +//! - \ref ADC_INT_OVIFG +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCClearInterrupt(uint32_t intFlags) +{ + // Clear the requested interrupt sources + HWREG(ADC_BASE + ADC_O_ICLR0) = intFlags; +} + +//***************************************************************************** +// +//! \brief Returns ADC gain value for given reference +//! +//! This returns a gain value that should be passed to \ref ADCAdjustValueForGain. +//! The gain is dependant on the reference source +//! +//! \param reference reference source used in conversion +//! - \ref ADC_FIXED_REFERENCE_1V4 +//! - \ref ADC_FIXED_REFERENCE_2V5 +//! - \ref ADC_VDDS_REFERENCE +//! - \ref ADC_EXTERNAL_REFERENCE +//! +//! \return Gain value +// +//***************************************************************************** +extern uint16_t ADCGetAdjustmentGain(uint32_t reference); + +//***************************************************************************** +// +//! \brief Write correct offset value to ADC-peripheral trim register +//! +//! The ADC peripheral relies on an offset trim value in \ref SYS0_O_TMUTE2. This value +//! needs to be set depending on which reference source is used in the conversion +//! +//! \param reference reference source used in conversion +//! - \ref ADC_FIXED_REFERENCE_1V4 +//! - \ref ADC_FIXED_REFERENCE_2V5 +//! - \ref ADC_VDDS_REFERENCE +//! - \ref ADC_EXTERNAL_REFERENCE +// +//***************************************************************************** +extern void ADCSetAdjustmentOffset(uint32_t reference); + +//***************************************************************************** +// +//! \brief Performs ADC value gain adjustment. +//! +//! This function takes a measured ADC value and compensates for the internal gain +//! in the ADC. +//! +//! \param adcValue +//! ADC unadjusted value +//! \param bitResolution +//! ADC bit resolution +//! \param gain +//! Gain adjustment value provided by \ref ADCGetAdjustmentGain() +//! +//! \return +//! ADC adjusted value +// +//***************************************************************************** +extern uint32_t ADCAdjustValueForGain(uint32_t adcValue, uint32_t bitResolution, uint16_t gain); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __ADC_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes.h new file mode 100644 index 00000000..288af016 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes.h @@ -0,0 +1,692 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*!**************************************************************************** + * @file aes.h + * + * @brief AES module header for CC23X0R5 devices + * + * @anchor ti_devices_cc23x0r5_aes_overview + * + * This module provides the low-level functions used to access the LAES128 + * crypto engine. + ******************************************************************************/ + +#ifndef __AES_H__ +#define __AES_H__ + +#include + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE 16U //!< Block size in number of bytes +#define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE / 4U) +#define AES_BLOCK_SIZE_MULTIPLE_MASK 0xFFFFFFF0U +#define AES_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_BLOCK_SIZE_MULTIPLE_MASK) +#define AES_NON_BLOCK_SIZE_MULTIPLE_MASK 0x0000000FU +#define AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_NON_BLOCK_SIZE_MULTIPLE_MASK) +#define AES_GET_NUM_BLOCKS(len) ((len) >> 4) +#define AES_BLOCKS_TO_BYTES(numBlocks) ((numBlocks) << 4) + +#define AES_DOUBLE_BLOCK_SIZE_MULTIPLE_MASK (size_t)(0xFFFFFFE0UL) + +#define AES_IV_LENGTH_BYTES AES_BLOCK_SIZE +#define AES_TAG_LENGTH_BYTES AES_BLOCK_SIZE + +#define AES_128_KEY_LENGTH_BYTES (128U / 8U) + +#define IS_WORD_ALIGNED(ptr) (((uintptr_t)(ptr) << 30) == 0U) + +#define AES_ICLR_ALL \ + ((uint32_t)AES_ICLR_AESDONE | (uint32_t)AES_ICLR_AESSTART | (uint32_t)AES_ICLR_CHADONE | (uint32_t)AES_ICLR_CHBDONE) + +typedef union +{ + uint32_t words[4]; + uint8_t bytes[16]; +} AES_BlockWordAligned; + +/*! @cond NODOC */ + +/*! + * @brief Process word-aligned data for CBC-MAC or CMAC + * + * @note \c input cannot be NULL. AUTOCFG.BUSHALT must be enabled. + * + * @param [in] input Pointer word-aligned input + * @param [in] numBlocks Number of 16-byte blocks of data to process + * + */ +void AESProcessAlignedBlocksCMAC(const uint32_t *input, uint32_t numBlocks); + +/*! + * @brief Process word-aligned data for CTR + * + * @note \c input and \c output cannot be NULL. AUTOCFG.BUSHALT must be enabled. + * + * @param [in] input Pointer word-aligned input + * @param [out] output Pointer word-aligned output + * @param [in] numBlocks Number of 16-byte blocks of data to process + * + */ +void AESProcessAlignedBlocksCTR(const uint32_t *input, uint32_t *output, uint32_t numBlocks); + +/*! + * @brief Process word-aligned data for ECB or CBC + * + * @note \c input and \c output cannot be NULL. AUTOCFG.BUSHALT must be enabled. + * + * @param [in] input Pointer word-aligned input + * @param [out] output Pointer word-aligned output + * @param [in] numBlocks Number of 16-byte blocks of data to process + * + */ +void AESProcessAlignedBlocksECB(const uint32_t *input, uint32_t *output, uint32_t numBlocks); + +/*! + * @brief Copy a 16-byte block of data + * + * Copies a 16-byte block of data from the memory location pointed to by + * \c src to the memory location pointed to by \c dst. If \c src and \c dst + * are both word-aligned, the memory contents will be copied in words for + * optimal performance. If either \c src or \c dst are not word-aligned, + * the memory contents will be copied byte-by-byte. + * + * @note \c src and \c dst cannot be NULL. + * + * @param [out] dst Pointer to the memory location to copy to + * @param [in] src Pointer to the memory location to copy from + * + */ +void AESCopyBlock(void *dst, const void *src); + +/*! + * @brief Write AES key + * + * Writes the given 128-bit key to the AES KEY0..KEY3 registers. + * + * @param [in] key Array containing the key material. + * + */ +__STATIC_INLINE void AESWriteKEY(const uint8_t key[16]) +{ + AESCopyBlock((void *)(AES_BASE + AES_O_KEY0), key); +} + +/*! + * @brief Write AES Buffer registers + * + * Writes the given values to the AES BUF0..BUF3 registers. + * + * @param [in] buf Array containing the values to be written to the + * buffer registers. + * + */ +__STATIC_INLINE void AESWriteBUF(const uint8_t buf[16]) +{ + AESCopyBlock((void *)(AES_BASE + AES_O_BUF0), buf); +} + +/*! + * @brief Write AES Buffer registers + * + * Writes the given values to the AES BUF0..BUF3 registers. + * + * @param [in] buf Word-aligned array containing the values to be written to the + * buffer registers. + * + */ +__STATIC_INLINE void AESWriteBUF32(const uint32_t buf[4]) +{ + HWREG(AES_BASE + AES_O_BUF0) = buf[0]; + HWREG(AES_BASE + AES_O_BUF1) = buf[1]; + HWREG(AES_BASE + AES_O_BUF2) = buf[2]; + HWREG(AES_BASE + AES_O_BUF3) = buf[3]; +} + +/*! + * @brief Read AES Buffer registers + * + * Reads the contents from the AES BUF0..BUF3 registers. + * + * @param [out] buf Array where the buffer contents will be written to. + * + */ +__STATIC_INLINE void AESReadBUF(uint8_t buf[16]) +{ + AESCopyBlock(buf, (const void *)(AES_BASE + AES_O_BUF0)); +} + +/*! + * @brief Read AES Buffer registers + * + * Reads the contents from the AES BUF0..BUF3 registers. + * + * @param [out] buf Word-aligned array where the buffer contents will be written to. + * + */ +__STATIC_INLINE void AESReadBUF32(uint32_t buf[4]) +{ + buf[0] = HWREG(AES_BASE + AES_O_BUF0); + buf[1] = HWREG(AES_BASE + AES_O_BUF1); + buf[2] = HWREG(AES_BASE + AES_O_BUF2); + buf[3] = HWREG(AES_BASE + AES_O_BUF3); +} + +/*! + * @brief Write AES Text Word XOR registers + * + * Writes the given values to the AES TXTX0..TXTX3 registers. + * + * @param [in] txtxor Array containing the values to be written to the + * TXTX registers. + * + */ +__STATIC_INLINE void AESWriteTXTXOR(const uint8_t txtxor[16]) +{ + AESCopyBlock((void *)(AES_BASE + AES_O_TXTX0), txtxor); +} + +/*! + * @brief Write AES Text Word XOR registers + * + * Writes the given values to the AES TXTX0..TXTX3 registers. + * + * @param [in] txtxor Word-aligned array containing the values to be written to the + * TXTX registers. + * + */ +__STATIC_INLINE void AESWriteTXTXOR32(const uint32_t txtxor[4]) +{ + HWREG(AES_BASE + AES_O_TXTX0) = txtxor[0]; + HWREG(AES_BASE + AES_O_TXTX1) = txtxor[1]; + HWREG(AES_BASE + AES_O_TXTX2) = txtxor[2]; + HWREG(AES_BASE + AES_O_TXTX3) = txtxor[3]; +} + +/*! + * @brief Read Text Word XOR Buffer Word registers + * + * Reads the contents from the AES TXTXBUF0..TXTXBUF0 registers. + * + * @param [out] txtxbuf Array where the TXTXBUF register contents will be + * written to. + * + */ +__STATIC_INLINE void AESReadTXTXBUF(uint8_t txtxbuf[16]) +{ + AESCopyBlock(txtxbuf, (const void *)(AES_BASE + AES_O_TXTXBUF0)); +} + +/*! + * @brief Write AES Text Word registers + * + * Writes the given values to the AES TXT0..TXT3 registers. + * + * @param [in] txt Array containing the values to be written to the + * TXT registers. + * + */ +__STATIC_INLINE void AESWriteTXT(const uint8_t txt[16]) +{ + AESCopyBlock((void *)(AES_BASE + AES_O_TXT0), txt); +} + +/*! + * @brief Write AES Text Word registers + * + * Writes the given values to the AES TXT0..TXT3 registers. + * + * @param [in] txt Word-aligned array containing the values to be written to the + * TXT registers. + * + */ +__STATIC_INLINE void AESWriteTXT32(const uint32_t txt[4]) +{ + HWREG(AES_BASE + AES_O_TXT0) = txt[0]; + HWREG(AES_BASE + AES_O_TXT1) = txt[1]; + HWREG(AES_BASE + AES_O_TXT2) = txt[2]; + HWREG(AES_BASE + AES_O_TXT3) = txt[3]; +} + +/*! + * @brief Read AES Text Word registers + * + * Reads the contents of the AES TXT0..TXT3 registers. + * + * @param [out] txt Array where the values from the TXT registers + * will be written to. + * + */ +__STATIC_INLINE void AESReadTXT(uint8_t txt[16]) +{ + AESCopyBlock(txt, (const void *)(AES_BASE + AES_O_TXT0)); +} + +/*! + * @brief Read AES Text Word registers + * + * Reads the contents of the AES TXT0..TXT3 registers. + * + * @param [out] txt Word-aligned array where the values from the TXT registers + * will be written to. + * + */ +__STATIC_INLINE void AESReadTXT32(uint32_t txt[4]) +{ + txt[0] = HWREG(AES_BASE + AES_O_TXT0); + txt[1] = HWREG(AES_BASE + AES_O_TXT1); + txt[2] = HWREG(AES_BASE + AES_O_TXT2); + txt[3] = HWREG(AES_BASE + AES_O_TXT3); +} + +/*! + * @brief Write AES Tag + * + * Writes the given Tag to the crypto engine. + * + * @param [in] tag Array containing the Tag. + * + */ +__STATIC_INLINE void AESWriteTag(const uint8_t tag[16]) +{ + AESWriteTXT(tag); +} + +/*! + * @brief Write AES Tag + * + * Writes the given Tag to the crypto engine. + * + * @param [in] tag Array containing the Tag. + * + */ +__STATIC_INLINE void AESWriteTag32(const uint32_t tag[4]) +{ + AESWriteTXT32(tag); +} + +/*! + * @brief Read AES Tag + * + * Reads the Tag from the crypto engine. + * + * @param [out] tag Array where the Tag will be written to. + * + */ +__STATIC_INLINE void AESReadTag(uint8_t tag[16]) +{ + AESReadTXT(tag); +} + +/*! + * @brief Read AES Tag + * + * Reads the Tag from the crypto engine. + * + * @param [out] tag Word-aligned array where the Tag will be written to. + * + */ +__STATIC_INLINE void AESReadTag32(uint32_t tag[4]) +{ + AESReadTXT32(tag); +} + +/*! + * @brief Set AES AutoCfg + * + * Sets the configuration for automatic HW updates to TXT and BUF. + * + * @param [in] autoCfg Specifies what configuration to be set. + * - @ref AES_AUTOCFG_CHBDONECLR_M + * - @ref AES_AUTOCFG_CHADONECLR_M + * - @ref AES_AUTOCFG_ECBSTARTCLR_M + * - @ref AES_AUTOCFG_ECBDONECLR_M + * - @ref AES_AUTOCFG_BUSHALT_M + * - @ref AES_AUTOCFG_CTRSIZE_M + * - @ref AES_AUTOCFG_CTRALIGN_M + * - @ref AES_AUTOCFG_CTRENDIAN_M + * - @ref AES_AUTOCFG_TRGTXT_M + * - @ref AES_AUTOCFG_AESSRC_M + * - @ref AES_AUTOCFG_TRGAES_M + * + */ +__STATIC_INLINE void AESSetAUTOCFG(uint32_t autoCfg) +{ + HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg; +} + +/*! + * @brief Clear the ECB trigger mask in AUTOCFG + * + * Clears the ECB trigger mask in AUTOCFG + * + */ +__STATIC_INLINE void AESClearAUTOCFGTrigger(void) +{ + /* Read the current AUTOCFG value */ + uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG); + + /* Clear the TRGECB bits */ + autoCfg &= (uint32_t)~AES_AUTOCFG_TRGAES_M; + + HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg; +} + +/*! + * @brief Clear the BUSHALT enable in AUTOCFG + * + * Clears the BUSHALT enable in AUTOCFG + * + */ +__STATIC_INLINE void AESClearAUTOCFGBusHalt(void) +{ + /* Read the current AUTOCFG value */ + uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG); + + /* Clear the BUSHALT bit */ + autoCfg &= (uint32_t)~AES_AUTOCFG_BUSHALT_M; + + HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg; +} + +/*! + * @brief Get AES Status + * + * Gets the state of the AES Accelerator. + * + * @return The state of the AES Accelerator: + * - @ref AES_STA_STATE_BUSY + * - @ref AES_STA_STATE_IDLE + */ +__STATIC_INLINE uint32_t AESGetStatus(void) +{ + return (HWREG(AES_BASE + AES_O_STA) & AES_STA_STATE_M); +} + +/*! + * @brief Set AES Trigger + * + * Sets the operations to be manually triggered. + * + * @param [in] triggerMask Specifies which operations to be triggered. + * - @ref AES_TRG_DMACHA + * - @ref AES_TRG_DMACHB + * - @ref AES_TRG_AESOP_TXTXBUF + * - @ref AES_TRG_AESOP_BUF + * - @ref AES_TRG_AESOP_TXT + * + */ +__STATIC_INLINE void AESSetTrigger(uint32_t triggerMask) +{ + HWREG(AES_BASE + AES_O_TRG) = triggerMask; +} + +/*! + * @brief Abort AES operation + * + * Aborts an ongoing AES operation. + * + * @note An abort will clear TXT, BUF, DMA, AUTOCFG registers. + * + */ +__STATIC_INLINE void AESAbort(void) +{ + HWREG(AES_BASE + AES_O_ABORT) = AES_ABORT_ABORTAES_SET; +} + +/*! + * @brief Clear AES TXT registers + * + * Clears the contents of TXT registers, if STATE = IDLE. + * Else, the contents remain unchanged. + * + */ +__STATIC_INLINE void AESClearTXT(void) +{ + HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M; +} + +/*! + * @brief Clear AES BUF registers + * + * Clears the contents of BUF registers, if STATE = IDLE. + * Else, the contents remain unchanged. + * + */ +__STATIC_INLINE void AESClearBUF(void) +{ + HWREG(AES_BASE + AES_O_CLR) = AES_CLR_BUF_M; +} + +/*! + * @brief Clear AES TXT & BUF registers + * + * Clears the contents of TXT and BUF registers, if STATE = IDLE. + * Else, the contents remain unchanged. + * + + */ +__STATIC_INLINE void AESClearTXTAndBUF(void) +{ + HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M | AES_CLR_BUF_M; +} + +/*! + * @brief Write AES IV + * + * Writes the given IV to the crypto engine. + * + * @param [in] iv Array containing the IV. + * + */ +__STATIC_INLINE void AESWriteIV(const uint8_t iv[16]) +{ + AESWriteTXT(iv); +} + +/*! + * @brief Write AES IV + * + * Writes the given IV to the crypto engine. + * + * @param [in] iv Word-aligned array containing the IV. + * + */ +__STATIC_INLINE void AESWriteIV32(const uint32_t iv[4]) +{ + AESWriteTXT32(iv); +} + +/*! + * @brief Clear AES IV + * + * Clears the IV in crypto engine. + * + */ +__STATIC_INLINE void AESClearIV(void) +{ + AESClearTXT(); +} + +/*! + * @brief Read AES IV + * + * Reads the IV from the crypto engine. + * + * @param [out] iv Array where the IV will be written to. + * + */ +__STATIC_INLINE void AESReadIV(uint8_t iv[16]) +{ + AESReadTXT(iv); +} + +/*! + * @brief Read AES IV + * + * Reads the IV from the crypto engine. + * + * @param [out] iv Word-aligned array where the IV will be written to. + * + */ +__STATIC_INLINE void AESReadIV32(uint32_t iv[4]) +{ + AESReadTXT32(iv); +} + +/*! + * @brief Get AES Raw Interrupt Status + * + * Gets the current Raw Interrupt Status + * + * @return The Raw Interrupt Status: + * - @ref AES_RIS_CHBDONE_M + * - @ref AES_RIS_CHADONE_M + * - @ref AES_RIS_ECBSTART_M + * - @ref AES_RIS_ECBDONE_M + */ +__STATIC_INLINE uint32_t AESGetRawInterruptStatus(void) +{ + return HWREG(AES_BASE + AES_O_RIS); +} + +/*! + * @brief Set AES Interrupt + * + * Sets one or more AES Interrupts. + * + * @param [in] intFlags Specifies which interrupt(s) to be set. + * - @ref AES_ISET_CHBDONE_M + * - @ref AES_ISET_CHADONE_M + * - @ref AES_ISET_ECBSTART_M + * - @ref AES_ISET_ECBDONE_M + * + + */ +__STATIC_INLINE void AESSetInterrupt(uint32_t intFlags) +{ + HWREG(AES_BASE + AES_O_ISET) = intFlags; +} + +/*! + * @brief Clear AES Interrupt + * + * Clears one or more AES Interrupts. + * + * @param [in] intFlags Specifies which interrupt(s) to be cleared. + * - @ref AES_ICLR_CHBDONE_M + * - @ref AES_ICLR_CHADONE_M + * - @ref AES_ICLR_AESSTART_M + * - @ref AES_ICLR_AESDONE_M + * + */ +__STATIC_INLINE void AESClearInterrupt(uint32_t intFlags) +{ + HWREG(AES_BASE + AES_O_ICLR) = intFlags; +} + +/*! + * @brief Get AES Masked Interrupt Status + * + * Gets the Masked Interrupt Status. + * + * @return The Masked Interrupt Status. + * - @ref AES_MIS_CHBDONE_M + * - @ref AES_MIS_CHADONE_M + * - @ref AES_MIS_ECBSTART_M + * - @ref AES_MIS_ECBDONE_M + */ +__STATIC_INLINE uint32_t AESGetMaskedInterruptStatus(void) +{ + return HWREG(AES_BASE + AES_O_MIS); +} + +/*! + * @brief Set AES IMASK + * + * Enables/disables interrupts. + * + * @param [in] intFlags Specifies which interrupts to be enabled/disabled. + * - @ref AES_IMASK_CHBDONE_M + * - @ref AES_IMASK_CHADONE_M + * - @ref AES_IMASK_ECBSTART_M + * - @ref AES_IMASK_ECBDONE_M + * + */ +__STATIC_INLINE void AESSetIMASK(uint32_t intFlags) +{ + HWREG(AES_BASE + AES_O_IMASK) = intFlags; +} + +/*! + * @brief Setup AES DMA + * + * Setup the DMA for the AES engine + * + * @param [in] dmaConfig Specifies the DMA configuration for done side-effects, + * addresses and triggers for DMA channel A & B. + * - @ref AES_DMA_DONEACT_M + * - @ref AES_DMA_ADRCHA_M + * - @ref AES_DMA_TRGCHA_M + * - @ref AES_DMA_ADRCHB_M + * - @ref AES_DMA_TRGCHB_M + * + */ +__STATIC_INLINE void AESSetupDMA(uint32_t dmaConfig) +{ + HWREG(AES_BASE + AES_O_DMA) = dmaConfig; +} + +/*! + * @brief Disable DMA + * + * Disables the DMA for the crypto engine + * + */ +__STATIC_INLINE void AESDisableDMA(void) +{ + HWREG(AES_BASE + AES_O_DMA) = AES_DMA_DONEACT_DIS | AES_DMA_TRGCHB_DIS | AES_DMA_TRGCHA_DIS; +} + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* __AES_H__ */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_gcc.s b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_gcc.s new file mode 100644 index 00000000..bf0367c8 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_gcc.s @@ -0,0 +1,231 @@ +//######################################################################################### +// Copyright (c) 2022 Texas Instruments Incorporated +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1) Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2) Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3) Neither the name of the copyright holder nor the names of its contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//######################################################################################### +// Filename: aes_gcc.s +// Description: Low level AES functions +// Language: GNU Assembly for ARM +// Processor: ARM Cortex M0 +// Compiler: GCC +//######################################################################################### + + .syntax unified + .file "aes_gcc.s" + +//----------------------------------------------------------------------------------------- +// Macros +//----------------------------------------------------------------------------------------- + + .macro .start_function name + .text + .align 2 + .thumb + .global \name + .thumb_func + .type \name, %function + .cfi_startproc + .endm + + .macro .end_function name + .cfi_endproc + .endm + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCMAC +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksCMAC + + input .req R0 + blocks .req R1 + buf0 .req R2 + +AESProcessAlignedBlocksCMAC: + PUSH {R4-R6} + +CMAC_WRITE_BLOCK: + LDM input!, {R3-R6} // Read input block (4 words) + LDR buf0, AES_BUF0_ADDR // buf0 = AES BUF0 register addr + STM buf0!, {R3-R6} // Write input block to AES BUF regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CMAC_WRITE_BLOCK + + POP {R4-R6} + BX LR + + .end_function AESProcessAlignedBlocksCMAC + + .unreq input + .unreq blocks + .unreq buf0 + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCTR +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksCTR + + input .req R0 + output .req R1 + blocks .req R2 + dst .req R3 + +AESProcessAlignedBlocksCTR: + + PUSH {R4-R7} + +CTR_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_TXTX0_ADDR // dst = AES TXTX0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CTR_PROCESS_BLOCK + + POP {R4-R7} + BX LR + + .end_function AESProcessAlignedBlocksCTR + + .unreq input + .unreq output + .unreq blocks + .unreq dst + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksECB +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksECB + + input .req R0 + output .req R1 + blocks .req R2 + dst .req R3 + +AESProcessAlignedBlocksECB: + + PUSH {R4-R7} + + LDM input!, {R4-R7} // Read first input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write first input block to AES TXTX regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BEQ ECB_READ_FINAL_OUTPUT + +ECB_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE ECB_PROCESS_BLOCK + +ECB_READ_FINAL_OUTPUT: + // Clear the AUTOCFG trigger mask to avoid triggering a spurious encryption + // upon reading the TXT3 register. + LDR R3, AES_AUTOCFG_ADDR // R3 = AES AUTOCFG register addr + LDR R4, [R3] // R4 = AES AUTOCFG register value + MOVS R5, #0xF // R5 = TRGECB_MASK + BICS R4, R4, R5 // R4 = AUTOCFG & ~TRGECB_MASK + STR R4, [R3] // Write modified AUTOCFG value + + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read final output block from TXT regs (4 words) + STM output!, {R4-R7} // Write final output block (4 words) + + POP {R4-R7} + BX LR + + .end_function AESProcessAlignedBlocksECB + + .unreq input + .unreq output + .unreq blocks + .unreq dst + +//----------------------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------------------- + .align 4 +AES_AUTOCFG_ADDR: + .word 0x400C002C // AES AUTOCFG register addr +AES_TXT0_ADDR: + .word 0x400C0070 // AES TXT0 register addr +AES_TXTX0_ADDR: + .word 0x400C0080 // AES TXTX0 register addr +AES_BUF0_ADDR: + .word 0x400C0090 // AES BUF0 register addr + + +//----------------------------------------------------------------------------------------- +// AESCopyBlock +//----------------------------------------------------------------------------------------- + .start_function AESCopyBlock + + dst .req R0 + src .req R1 + tmp .req R2 + len .req R3 + +AESCopyBlock: + + LSLS tmp, dst, #0x1e // dst << 30 + BNE UNALIGNED_COPY + LSLS tmp, src, #0x1e // src << 30 + BNE UNALIGNED_COPY + +WORD_ALIGNED_COPY: + PUSH {R4-R5} + LDM src!, {R2-R5} // Read src block (4 words) + STM dst!, {R2-R5} // dst block = src block + POP {R4-R5} + BX LR + +UNALIGNED_COPY: + MOVS len, #16 // len = 16 bytes +UNALIGNED_COPY_LOOP: + LDRB tmp, [src] // tmp = src[i] + STRB tmp, [dst] // dst[i] = src[i] + ADDS src, src, #1 // Increment src ptr by 1 + ADDS dst, dst, #1 // Increment dst ptr by 1 + SUBS len, #1 // Decrement len by 1 + BNE UNALIGNED_COPY_LOOP + BX LR + + .end_function AESCopyBlock + + .unreq dst + .unreq src + .unreq tmp + .unreq len diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_iar.s b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_iar.s new file mode 100644 index 00000000..466eeac9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_iar.s @@ -0,0 +1,214 @@ +//######################################################################################### +// Copyright (c) 2022 Texas Instruments Incorporated +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1) Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2) Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3) Neither the name of the copyright holder nor the names of its contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//######################################################################################### +// Filename: aes_iar.s +// Description: Low level AES functions +// Language: IAR Assembly for ARM +// Processor: ARM Cortex M0 +// Compiler: IAR +//######################################################################################### + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCMAC +//----------------------------------------------------------------------------------------- + SECTION .text:CODE(2) + THUMB + EXPORT AESProcessAlignedBlocksCMAC + + + #define input R0 + #define blocks R1 + #define buf0 R2 + +AESProcessAlignedBlocksCMAC: + PUSH {R4-R6} + +CMAC_WRITE_BLOCK: + LDM input!, {R3-R6} // Read input block (4 words) + LDR buf0, AES_BUF0_ADDR // buf0 = AES BUF0 register addr + STM buf0!, {R3-R6} // Write input block to AES BUF regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CMAC_WRITE_BLOCK + + POP {R4-R6} + BX LR + + #undef input + #undef blocks + #undef buf0 + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCTR +//----------------------------------------------------------------------------------------- + SECTION .text:CODE(2) + THUMB + EXPORT AESProcessAlignedBlocksCTR + + #define input R0 + #define output R1 + #define blocks R2 + #define dst R3 + +AESProcessAlignedBlocksCTR: + + PUSH {R4-R7} + +CTR_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_TXTX0_ADDR // dst = AES TXTX0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CTR_PROCESS_BLOCK + + POP {R4-R7} + BX LR + + #undef input + #undef output + #undef blocks + #undef dst + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksECB +//----------------------------------------------------------------------------------------- + SECTION .text:CODE(2) + THUMB + EXPORT AESProcessAlignedBlocksECB + + #define input R0 + #define output R1 + #define blocks R2 + #define dst R3 + +AESProcessAlignedBlocksECB: + + PUSH {R4-R7} + + LDM input!, {R4-R7} // Read first input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write first input block to AES TXTX regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BEQ ECB_READ_FINAL_OUTPUT + +ECB_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE ECB_PROCESS_BLOCK + +ECB_READ_FINAL_OUTPUT: + // Clear the AUTOCFG trigger mask to avoid triggering a spurious encryption + // upon reading the TXT3 register. + LDR R3, AES_AUTOCFG_ADDR // R3 = AES AUTOCFG register addr + LDR R4, [R3] // R4 = AES AUTOCFG register value + MOVS R5, #0xF // R5 = TRGECB_MASK + BICS R4, R4, R5 // R4 = AUTOCFG & ~TRGECB_MASK + STR R4, [R3] // Write modified AUTOCFG value + + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read final output block from TXT regs (4 words) + STM output!, {R4-R7} // Write final output block (4 words) + + POP {R4-R7} + BX LR + + #undef input + #undef output + #undef blocks + #undef dst + +//----------------------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------------------- + + SECTION .text:CONST(2) + DATA + ALIGNROM 2 + +AES_AUTOCFG_ADDR: + DC32 0x400C002C // AES AUTOCFG register addr +AES_TXT0_ADDR: + DC32 0x400C0070 // AES TXT0 register addr +AES_TXTX0_ADDR: + DC32 0x400C0080 // AES TXTX0 register addr +AES_BUF0_ADDR: + DC32 0x400C0090 // AES BUF0 register addr + + +//----------------------------------------------------------------------------------------- +// AESCopyBlock +//----------------------------------------------------------------------------------------- + SECTION .text:CODE(2) + THUMB + EXPORT AESCopyBlock + + #define dst R0 + #define src R1 + #define tmp R2 + #define len R3 + +AESCopyBlock: + + LSLS tmp, dst, #0x1e // dst << 30 + BNE UNALIGNED_COPY + LSLS tmp, src, #0x1e // src << 30 + BNE UNALIGNED_COPY + +WORD_ALIGNED_COPY: + PUSH {R4-R5} + LDM src!, {R2-R5} // Read src block (4 words) + STM dst!, {R2-R5} // dst block = src block + POP {R4-R5} + BX LR + +UNALIGNED_COPY: + MOVS len, #16 // len = 16 bytes +UNALIGNED_COPY_LOOP: + LDRB tmp, [src] // tmp = src[i] + STRB tmp, [dst] // dst[i] = src[i] + ADDS src, src, #1 // Increment src ptr by 1 + ADDS dst, dst, #1 // Increment dst ptr by 1 + SUBS len, #1 // Decrement len by 1 + BNE UNALIGNED_COPY_LOOP + BX LR + + #undef dst + #undef src + #undef tmp + #undef len + + END diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_ticlang.s b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_ticlang.s new file mode 100644 index 00000000..3e14687b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/aes_ticlang.s @@ -0,0 +1,231 @@ +//######################################################################################### +// Copyright (c) 2022 Texas Instruments Incorporated +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1) Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2) Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3) Neither the name of the copyright holder nor the names of its contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//######################################################################################### +// Filename: aes_ticlang.s +// Description: Low level AES functions +// Language: GNU Assembly for ARM +// Processor: ARM Cortex M0 +// Compiler: TI CLANG +//######################################################################################### + + .syntax unified + .file "aes_ticlang.s" + +//----------------------------------------------------------------------------------------- +// Macros +//----------------------------------------------------------------------------------------- + + .macro .start_function name + .text + .align 2 + .thumb + .global \name + .thumb_func + .type \name, %function + .cfi_startproc + .endm + + .macro .end_function name + .cfi_endproc + .endm + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCMAC +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksCMAC + + input .req R0 + blocks .req R1 + buf0 .req R2 + +AESProcessAlignedBlocksCMAC: + PUSH {R4-R6} + +CMAC_WRITE_BLOCK: + LDM input!, {R3-R6} // Read input block (4 words) + LDR buf0, AES_BUF0_ADDR // buf0 = AES BUF0 register addr + STM buf0!, {R3-R6} // Write input block to AES BUF regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CMAC_WRITE_BLOCK + + POP {R4-R6} + BX LR + + .end_function AESProcessAlignedBlocksCMAC + + .unreq input + .unreq blocks + .unreq buf0 + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksCTR +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksCTR + + input .req R0 + output .req R1 + blocks .req R2 + dst .req R3 + +AESProcessAlignedBlocksCTR: + + PUSH {R4-R7} + +CTR_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_TXTX0_ADDR // dst = AES TXTX0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE CTR_PROCESS_BLOCK + + POP {R4-R7} + BX LR + + .end_function AESProcessAlignedBlocksCTR + + .unreq input + .unreq output + .unreq blocks + .unreq dst + + +//----------------------------------------------------------------------------------------- +// AESProcessAlignedBlocksECB +//----------------------------------------------------------------------------------------- + .start_function AESProcessAlignedBlocksECB + + input .req R0 + output .req R1 + blocks .req R2 + dst .req R3 + +AESProcessAlignedBlocksECB: + + PUSH {R4-R7} + + LDM input!, {R4-R7} // Read first input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write first input block to AES TXTX regs + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BEQ ECB_READ_FINAL_OUTPUT + +ECB_PROCESS_BLOCK: + LDM input!, {R4-R7} // Read input block (4 words) + LDR dst, AES_BUF0_ADDR // dst = AES BUF0 register addr + STM dst!, {R4-R7} // Write input block to AES TXTX regs + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read output block from TXT regs (4 words) + STM output!, {R4-R7} // Write output block (4 words) + SUBS blocks, blocks, #0x1 // Decrement block cnt by 1 + BNE ECB_PROCESS_BLOCK + +ECB_READ_FINAL_OUTPUT: + // Clear the AUTOCFG trigger mask to avoid triggering a spurious encryption + // upon reading the TXT3 register. + LDR R3, AES_AUTOCFG_ADDR // R3 = AES AUTOCFG register addr + LDR R4, [R3] // R4 = AES AUTOCFG register value + MOVS R5, #0xF // R5 = TRGECB_MASK + BICS R4, R4, R5 // R4 = AUTOCFG & ~TRGECB_MASK + STR R4, [R3] // Write modified AUTOCFG value + + LDR dst, AES_TXT0_ADDR // dst = AES TXT0 register addr + LDM dst!, {R4-R7} // Read final output block from TXT regs (4 words) + STM output!, {R4-R7} // Write final output block (4 words) + + POP {R4-R7} + BX LR + + .end_function AESProcessAlignedBlocksECB + + .unreq input + .unreq output + .unreq blocks + .unreq dst + +//----------------------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------------------- + .align 4 +AES_AUTOCFG_ADDR: + .word 0x400C002C // AES AUTOCFG register addr +AES_TXT0_ADDR: + .word 0x400C0070 // AES TXT0 register addr +AES_TXTX0_ADDR: + .word 0x400C0080 // AES TXTX0 register addr +AES_BUF0_ADDR: + .word 0x400C0090 // AES BUF0 register addr + + +//----------------------------------------------------------------------------------------- +// AESCopyBlock +//----------------------------------------------------------------------------------------- + .start_function AESCopyBlock + + dst .req R0 + src .req R1 + tmp .req R2 + len .req R3 + +AESCopyBlock: + + LSLS tmp, dst, #0x1e // dst << 30 + BNE UNALIGNED_COPY + LSLS tmp, src, #0x1e // src << 30 + BNE UNALIGNED_COPY + +WORD_ALIGNED_COPY: + PUSH {R4-R5} + LDM src!, {R2-R5} // Read src block (4 words) + STM dst!, {R2-R5} // dst block = src block + POP {R4-R5} + BX LR + +UNALIGNED_COPY: + MOVS len, #16 // len = 16 bytes +UNALIGNED_COPY_LOOP: + LDRB tmp, [src] // tmp = src[i] + STRB tmp, [dst] // dst[i] = src[i] + ADDS src, src, #1 // Increment src ptr by 1 + ADDS dst, dst, #1 // Increment dst ptr by 1 + SUBS len, #1 // Decrement len by 1 + BNE UNALIGNED_COPY_LOOP + BX LR + + .end_function AESCopyBlock + + .unreq dst + .unreq src + .unreq tmp + .unreq len diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/chipinfo.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/chipinfo.h new file mode 100644 index 00000000..a64b3c34 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/chipinfo.h @@ -0,0 +1,143 @@ +/****************************************************************************** + * Filename: chipinfo.h + * + * Description: Collection of functions returning chip information. + * + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __CHIP_INFO_H__ +#define __CHIP_INFO_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup chipinfo_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_fcfg.h" +#include "../inc/hw_sys0.h" + +//***************************************************************************** +// +//! \brief Returns hardware version number +//! +//! The version number is set to 0 for the first market released chip +//! and thereafter incremented by 1 for each minor hardware change. +//! +//! \return Returns the hardware version number +// +//***************************************************************************** +__STATIC_INLINE uint32_t ChipInfoGetVersion(void) +{ + return (HWREG(SYS0_BASE + SYS0_O_DEVICEID) & SYS0_DEVICEID_VERSION_M) >> SYS0_DEVICEID_VERSION_S; +} + +//***************************************************************************** +// +//! \brief Chip type enumeration +// +//***************************************************************************** +typedef enum +{ + CHIP_TYPE_CC2340R = 0x2DDAU, //!< Chip type is CC2340R +} ChipType; + +//***************************************************************************** +// +//! \brief Returns chip type. +//! +//! \return +//! Returns \ref ChipType +// +//***************************************************************************** +__STATIC_INLINE ChipType ChipInfoGetChipType(void) +{ + return (ChipType)(fcfg->deviceInfo.partId.part); +} + +//***************************************************************************** +// +//! \brief Chip part ID enumeration +// +//***************************************************************************** +typedef enum +{ + CC2340R52E0RGER = 0x012DDAU, //!< Part ID is CC2340R52E0RGER + CC2340R52E0RKPR = 0x3B2DDAU, //!< Part ID is CC2340R52E0RKPR + CC2340R52E0WRHBRQ1 = 0x0F2DDAU, //!< Part ID is CC2340R52E0WRHBRQ1 +} ChipPartId; + +//***************************************************************************** +// +//! \brief Returns part ID. +//! +//! \return +//! Returns \ref ChipPartId +// +//***************************************************************************** +__STATIC_INLINE ChipPartId ChipInfoGetPartId(void) +{ + return (ChipPartId)(fcfg->deviceInfo.partId.val32 & 0x00FFFFFFU); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __CHIP_INFO_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h new file mode 100644 index 00000000..3433bbad --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h @@ -0,0 +1,642 @@ +/****************************************************************************** + * Filename: ckmd.h + * + * Description: Defines and prototypes for the CKMD module. + * + * Copyright (c) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __CKMD_H__ +#define __CKMD_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ckmd_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ckmd.h" +#include "../inc/hw_fcfg.h" + +//***************************************************************************** +// +//! \name LFOSC Temperature Coefficient Temperature Limits +//! +//! If the temperature in Celsius is within the range [ +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN, +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX ], inclusive, then the +//! temperature coefficient \ref CKMDGetLfoscMidTempCoefficientPpmPerC() shall +//! be used, otherwise \ref CKMDGetLfoscExtTempCoefficientPpmPerC(). +//! +//! If \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN is INT16_MIN, then there is no +//! lower limit for the above mentioned temperature range. +//! +//! If \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX is INT16_MAX, then there is no +//! upper limit for the above mentioned temperature range. +//! +//! \{ +// +//***************************************************************************** +#define CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN (INT16_MIN) +#define CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX (70) +//! \} + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets initial HFXT capacitor ramp trims +//! +//! This function sets the initial HFXT capacitor ramp trims. It will +//! overwrite the initial HFXT ramp trim values set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c capTrim must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q1CapTrim Initial Q1 capacitor trim. +//! \param q2CapTrim Initial Q2 capacitor trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialCapTrim(uint32_t q1CapTrim, uint32_t q2CapTrim) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~(CKMD_HFXTINIT_Q1CAP_M | CKMD_HFXTINIT_Q2CAP_M); + tmp |= (q1CapTrim << CKMD_HFXTINIT_Q1CAP_S) & CKMD_HFXTINIT_Q1CAP_M; + tmp |= (q2CapTrim << CKMD_HFXTINIT_Q2CAP_S) & CKMD_HFXTINIT_Q2CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets initial HFXT Q1 capacitor ramp trim +//! +//! This function sets the initial HFXT Q1 capacitor ramp trim. It will +//! overwrite the initial HFXT ramp trim value set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c q1Cap must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q1Cap Initial Q1 capacitor trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialQ1CapTrim(uint32_t q1Cap) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_Q1CAP_M; + tmp |= (q1Cap << CKMD_HFXTINIT_Q1CAP_S) & CKMD_HFXTINIT_Q1CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets initial HFXT Q2 capacitor ramp trim +//! +//! This function sets the initial HFXT Q2 capacitor ramp trim. It will +//! overwrite the initial HFXT ramp trim value set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c q2Cap must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q2Cap Initial Q2 capacitor trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialQ2CapTrim(uint32_t q2Cap) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_Q2CAP_M; + tmp |= (q2Cap << CKMD_HFXTINIT_Q2CAP_S) & CKMD_HFXTINIT_Q2CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets initial HFXT IREF ramp trim +//! +//! This function sets initial HFXT IREF ramp trim. It will overwrite the +//! initial HFXT ramp trim value set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c iref must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param iref Initial IREF trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialIrefTrim(uint32_t iref) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_IREF_M; + tmp |= (iref << CKMD_HFXTINIT_IREF_S) & CKMD_HFXTINIT_IREF_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets initial HFXT IDAC ramp trim +//! +//! This function sets the initial HFXT IDAC ramp trim. It will overwrite the +//! initial HFXT ramp trim value set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c idac must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param idac Initial IDAC trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialIdacTrim(uint32_t idac) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_IDAC_M; + tmp |= (idac << CKMD_HFXTINIT_IDAC_S) & CKMD_HFXTINIT_IDAC_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets initial HFXT amplitude threshold ramp trim +//! +//! This function sets the initial HFXT amplitude threshold ramp trim. It will +//! overwrite the initial HFXT ramp trim value set during startup. +//! +//! This trim value is used when initially turning on the HFXT. +//! +//! \note The value for \c amplitudeThreshold must be found experimentally based +//! on the chosen crystal and desired ramp behaviour. +//! +//! \param amplitudeThreshold Initial amplitude threshold trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetInitialAmplitudeThresholdTrim(uint32_t amplitudeThreshold) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & ~CKMD_HFXTINIT_AMPTHR_M; + tmp |= (amplitudeThreshold << CKMD_HFXTINIT_AMPTHR_S) & CKMD_HFXTINIT_AMPTHR_M; + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = tmp; +} + +//***************************************************************************** +// +//! \brief Gets initial HFXT Q1 capacitor ramp trim +//! +//! This function gets the initial HFXT Q1 capacitor ramp trim. +//! +//! \return Initial Q1 capacitor trim. +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetInitialQ1CapTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & CKMD_HFXTINIT_Q1CAP_M) >> CKMD_HFXTINIT_Q1CAP_S; +} + +//***************************************************************************** +// +//! \brief Gets initial HFXT Q2 capacitor ramp trim +//! +//! This function gets the initial HFXT Q2 capacitor ramp trim. +//! +//! \return Initial Q2 capacitor trim. +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetInitialQ2CapTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & CKMD_HFXTINIT_Q2CAP_M) >> CKMD_HFXTINIT_Q2CAP_S; +} + +//***************************************************************************** +// +//! \brief Gets initial HFXT IREF ramp trim +//! +//! This function gets the initial HFXT IREF ramp trim. +//! +//! \return Initial IREF trim. +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetInitialIrefTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & CKMD_HFXTINIT_IREF_M) >> CKMD_HFXTINIT_IREF_S; +} + +//***************************************************************************** +// +//! \brief Gets initial HFXT IDAC ramp trim +//! +//! This function gets the initial HFXT IDAC ramp trim. +//! +//! \return Initial IDAC trim. +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetInitialIdacTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & CKMD_HFXTINIT_IDAC_M) >> CKMD_HFXTINIT_IDAC_S; +} + +//***************************************************************************** +// +//! \brief Gets initial HFXT amplitude threshold ramp trim +//! +//! This function initial HFXT amplitude threshold ramp trim. +//! +//! \return Initial amplitude threshold trim. +//! +//! \sa CKMD_O_HFXTINIT for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetInitialAmplitudeThresholdTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTINIT) & CKMD_HFXTINIT_AMPTHR_M) >> CKMD_HFXTINIT_AMPTHR_S; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT capacitor ramp trims +//! +//! This function sets the target HFXT capacitor ramp trims. It will +//! overwrite the target HFXT ramp trim values set during startup. +//! +//! This trim value is used when target turning on the HFXT. +//! +//! \note The value for \c capTrim must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q1CapTrim Target Q1 capacitor trim. +//! \param q2CapTrim Target Q2 capacitor trim. +//! +//! \return None +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetCapTrim(uint32_t q1CapTrim, uint32_t q2CapTrim) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~(CKMD_HFXTTARG_Q1CAP_M | CKMD_HFXTTARG_Q2CAP_M); + tmp |= (q1CapTrim << CKMD_HFXTTARG_Q1CAP_S) & CKMD_HFXTTARG_Q1CAP_M; + tmp |= (q2CapTrim << CKMD_HFXTTARG_Q2CAP_S) & CKMD_HFXTTARG_Q2CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT Q1 capacitor ramp trim +//! +//! This function target HFXT Q1 capacitor ramp trim. It will overwrite the +//! target HFXT ramp trim value set during startup. +//! +//! This trim value is used after HFXT has ramped to change crystal performance. +//! +//! \note The value for \c q1Cap must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q1Cap Target Q1 capacitor trim. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetQ1CapTrim(uint32_t q1Cap) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~CKMD_HFXTTARG_Q1CAP_M; + tmp |= (q1Cap << CKMD_HFXTTARG_Q1CAP_S) & CKMD_HFXTTARG_Q1CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT Q2 capacitor ramp trim +//! +//! This function target HFXT Q2 capacitor ramp trim. It will overwrite the +//! target HFXT ramp trim value set during startup. +//! +//! This trim value is used after HFXT has ramped to change crystal performance. +//! +//! \note The value for \c q2Cap must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param q2Cap Target Q2 capacitor trim. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetQ2CapTrim(uint32_t q2Cap) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~CKMD_HFXTTARG_Q2CAP_M; + tmp |= (q2Cap << CKMD_HFXTTARG_Q2CAP_S) & CKMD_HFXTTARG_Q2CAP_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT IREF ramp trim +//! +//! This function target HFXT IREF ramp trim. It will overwrite the target +//! HFXT ramp trim value set during startup. +//! +//! This trim value is used after HFXT has ramped to change crystal performance. +//! +//! \note The value for \c iref must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param iref Target IREF trim. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetIrefTrim(uint32_t iref) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~CKMD_HFXTTARG_IREF_M; + tmp |= (iref << CKMD_HFXTTARG_IREF_S) & CKMD_HFXTTARG_IREF_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT IDAC ramp trim +//! +//! This function target HFXT IDAC ramp trim. It will overwrite the target +//! HFXT ramp trim value set during startup. +//! +//! This trim value is used after HFXT has ramped to change crystal performance. +//! +//! \note The value for \c idac must be found experimentally based on the +//! chosen crystal and desired ramp behaviour. +//! +//! \param idac Target IDAC trim. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetIdacTrim(uint32_t idac) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~CKMD_HFXTTARG_IDAC_M; + tmp |= (idac << CKMD_HFXTTARG_IDAC_S) & CKMD_HFXTTARG_IDAC_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Sets target HFXT amplitude threshold ramp trim +//! +//! This function target HFXT amplitude threshold ramp trim. It will overwrite +//! the target HFXT ramp trim value set during startup. +//! +//! This trim value is used after HFXT has ramped to change crystal performance. +//! +//! \note The value for \c amplitudeThreshold must be found experimentally based +//! on the chosen crystal and desired ramp behaviour. +//! +//! \param amplitudeThreshold Target amplitude threshold trim. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CKMDSetTargetAmplitudeThresholdTrim(uint32_t amplitudeThreshold) +{ + uint32_t tmp = HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & ~CKMD_HFXTTARG_AMPTHR_M; + tmp |= (amplitudeThreshold << CKMD_HFXTTARG_AMPTHR_S) & CKMD_HFXTTARG_AMPTHR_M; + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = tmp; +} + +//***************************************************************************** +// +//! \brief Gets target HFXT Q1 capacitor ramp trim +//! +//! This function gets the target HFXT Q1 capacitor ramp trim. +//! +//! \return Target Q1 capacitor trim. +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetTargetQ1CapTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & CKMD_HFXTTARG_Q1CAP_M) >> CKMD_HFXTTARG_Q1CAP_S; +} + +//***************************************************************************** +// +//! \brief Gets target HFXT Q2 capacitor ramp trim +//! +//! This function gets the target HFXT Q2 capacitor ramp trim. +//! +//! \return Target Q2 capacitor trim. +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetTargetQ2CapTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & CKMD_HFXTTARG_Q2CAP_M) >> CKMD_HFXTTARG_Q2CAP_S; +} + +//***************************************************************************** +// +//! \brief Gets target HFXT IREF ramp trim +//! +//! This function gets the target HFXT IREF ramp trim. +//! +//! \return Target IREF trim. +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetTargetIrefTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & CKMD_HFXTTARG_IREF_M) >> CKMD_HFXTTARG_IREF_S; +} + +//***************************************************************************** +// +//! \brief Gets target HFXT IDAC ramp trim +//! +//! This function gets the target HFXT IDAC ramp trim. +//! +//! \return Target IDAC trim. +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetTargetIdacTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & CKMD_HFXTTARG_IDAC_M) >> CKMD_HFXTTARG_IDAC_S; +} + +//***************************************************************************** +// +//! \brief Gets target HFXT amplitude threshold ramp trim +//! +//! This function target HFXT amplitude threshold ramp trim. +//! +//! \return Target amplitude threshold trim. +//! +//! \sa CKMD_O_HFXTTARG for trim range +// +//***************************************************************************** +__STATIC_INLINE uint32_t CKMDGetTargetAmplitudeThresholdTrim(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFXTTARG) & CKMD_HFXTTARG_AMPTHR_M) >> CKMD_HFXTTARG_AMPTHR_S; +} + +//***************************************************************************** +// +//! \brief Gets the worst case LFOSC frequency jump due to RTN. +//! +//! \return The absolute value of the worst case jump due to RTN in ppm. +// +//***************************************************************************** +__STATIC_INLINE uint_least16_t CKMDGetLfoscRtnPpm(void) +{ + uint8_t ppmRtn = 0x14; + if (fcfg->appTrims.revision >= 0x5) + { + ppmRtn = fcfg->appTrims.cc23x0r5.lfOscParams.ppmRtn; + } + return ppmRtn * 30; +} + +//***************************************************************************** +// +//! \brief Gets the the worst case LFOSC temperature coefficient in the "middle" +//! temperature range. +//! +//! This function can be used to determine the the worst case LFOSC temperature +//! coefficient in units of ppm/C in the temperature range [ +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN, +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX ]. +//! +//! \return The absolute value of worst case temperature coefficient in ppm/C. +// +//***************************************************************************** +__STATIC_INLINE uint_least16_t CKMDGetLfoscMidTempCoefficientPpmPerC(void) +{ + uint8_t ppmTempMid = 0x14; + if (fcfg->appTrims.revision >= 0x5) + { + ppmTempMid = fcfg->appTrims.cc23x0r5.lfOscParams.ppmTempMid; + } + return ppmTempMid * 13; +} + +//***************************************************************************** +// +//! \brief Gets the the worst case LFOSC temperature coefficient in the +//! "extended" temperature range. +//! +//! This function can be used to determine the the worst case LFOSC temperature +//! coefficient in units of ppm/C when the temperature is outside of the +//! temperature range [ +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN, +//! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX ]. +//! +//! \return The absolute value of worst case temperature coefficient in ppm/C. +// +//***************************************************************************** +__STATIC_INLINE uint_least16_t CKMDGetLfoscExtTempCoefficientPpmPerC(void) +{ + uint8_t ppmTempExt = 0x14; + if (fcfg->appTrims.revision >= 0x5) + { + ppmTempExt = fcfg->appTrims.cc23x0r5.lfOscParams.ppmTempExt; + } + return ppmTempExt * 35; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __CKMD_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/copylist.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/copylist.h new file mode 100644 index 00000000..c05a520a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/copylist.h @@ -0,0 +1,203 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + * \file copylist.h + * + * \brief Copy list format used to apply FCFG, CCFG, and standby wakeup + * configurations. + * + ******************************************************************************/ + +#ifndef __COPYLIST_H__ +#define __COPYLIST_H__ + +#include + +#include "hapi.h" + +#include "../inc/hw_types.h" + +//***************************************************************************** +// +//! \brief Copy list macro to end a copy list +//! +//! Processing of the copy list with CopyList_apply() will stop upon +//! encountering this entry. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! EOL |0000 |0000_0000|0000_0000_0000_0000_00|00 |0 |End-of-list +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_EOL 0U + +//***************************************************************************** +// +//! \brief Copy list macro to do nothing. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! NOP = WAIT(0)|0001 |0000_0000|0000_0000_0000_0000_00|00 |0 |No operation +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_NOP CopyList_WAIT(0U) + +//***************************************************************************** +// +//! \brief Copy list macro for waiting \c n iterations of a do-nothing loop +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! WAIT(N) |0001 |0000_0000|nnnn_nnnn_nnnn_nnnn_nn|00 |0 |Wait N/12 us +//! +//! \param[in] n Number of iterations to wait. Must be in range [1, 2^18 - 1]. +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_WAIT(n) (0x10000000U | (((uint32_t)n << 2U) & 0xFFFFCU)) + +//***************************************************************************** +// +//! \brief Copy list macro for copying a single literal to a specified address +//! +//! This macro copies a 32-bit literal to a specified \c address. This command +//! expects the next word in the copy list to be the literal it is supposed to +//! copy. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! CPY(A,1) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|01 |1 |Copy single literal word to full address A +//! +//! \param[in] address Address to copy the following literal to. The address +//! must be word-aligned. +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_COPY(address) ((uint32_t)address | 0x1U) + +//***************************************************************************** +// +//! \brief Copy list macro for copying multiple literals to a specified address +//! +//! This macro copies \c n 32-bit literal to a specified \c address. This +//! command expects the next \c n words in the copy list to be the literal it is +//! supposed to copy. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! CPY(A*,N) |aaaa |nnnn_nnnn|aaaa_aaaa_aaaa_aaaa_aa|00 |N |Copy N literal words to address A* +//! +//! The devices' address space is arranged such that bits 20:27 are not actually +//! needed to specify any valid address. +//! +//! \param[in] address Address to copy the following literals to. The address +//! must be word-aligned. +//! +//! \param[in] n Number of words to copy. Must be in range [1, 255] +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_COPY_MULTI(address, n) (((uint32_t)address & 0xF00FFFFCU) | (((uint32_t)n << 20U) & 0xFF00000U)) + +//***************************************************************************** +// +//! \brief Copy list macro for continuing copy list processing at a new address +//! +//! This macro continues processing the copy list at \c address. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! JMP(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|10 |0 |Jump to new list at full address A +//! +//! \param[in] address Address to continue processing the copy list at. The +//! address must be word-aligned. +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_JUMP(address) ((uint32_t)address | 0x2U) + +//***************************************************************************** +// +//! \brief Copy list macro to recurse to a new list +//! +//! Recurse into new list at \c address by invoking CopyList_apply(). Once this +//! list ends it will return back here and continue parsing this list. +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! CALL(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|11 |0 |Recurse to list at full address A +//! +//! \param[in] address Address to continue processing the copy list at. The +//! address must be word-aligned. +//! +//! \sa CopyList_apply() +// +//***************************************************************************** +#define CopyList_CALL(address) ((uint32_t)address | 0x3U) + +//***************************************************************************** +// +//! \brief Process copy list +//! Processes a copy list in a flexible CopyList format. Used by trims +//! in FCFG, for user-defined initialization in CCFG and may be used by +//! peripheral drivers to do HW reinitialization during wakeup from standby. +//! The copy list is processed as a sequence of 32b command words, followed by +//! zero or more literal words (LW): +//! +//! Command |31:28|27:20 |19:2 |1:0|LW|Description +//! -------------|-----|---------|----------------------|---|--|---------------- +//! EOL |0000 |0000_0000|0000_0000_0000_0000_00|00 |0 |End-of-list +//! WAIT(N) |0001 |0000_0000|nnnn_nnnn_nnnn_nnnn_nn|00 |0 |Wait N/12 us +//! NOP = WAIT(0)|0001 |0000_0000|0000_0000_0000_0000_00|00 |0 |No operation +//! CPY(A*,N) |aaaa |nnnn_nnnn|aaaa_aaaa_aaaa_aaaa_aa|00 |N |Copy N literal words to address A* +//! CPY(A,1) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|01 |1 |Copy single literal word to full address A +//! JMP(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|10 |0 |Jump to new list at full address A +//! CALL(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|11 |0 |Recurse to list at full address A +//! +//! A* is a reduced address space that covers all SRAM and peripheral space. +//! Bits 27:20 of this address will be assumed to be all zero. Full addresses +//! must have 32b alignment +//! +//! \param[in] list Pointer to the copy list +// +//***************************************************************************** +__STATIC_INLINE void CopyList_apply(const uint32_t *list) +{ + HapiApplyCopyList(list); +} + +#endif //__COPYLIST_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c new file mode 100644 index 00000000..e402609f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c @@ -0,0 +1,97 @@ +/****************************************************************************** + * Filename: cpu.c + * + * Description: Instruction wrappers for special CPU instructions needed by + * the drivers. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "cpu.h" + +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void CPUDelay(uint32_t count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void CPUDelay(uint32_t count) +{ + // Loop the specified number of times + __asm("CPUDelay:\n" + " subs r0, #1\n" + " bne.n CPUDelay\n" + " bx lr"); + #pragma diag_suppress = Pe940 +} + #pragma diag_default = Pe940 + +#elif defined(__TI_COMPILER_VERSION__) +// For CCS implement this function in pure assembly. This prevents the TI +// compiler from doing funny things with the optimizer. + +// Loop the specified number of times +__asm(" .sect \".text:CPUDelay\"\n" + " .clink\n" + " .thumbfunc CPUDelay\n" + " .thumb\n" + " .global CPUDelay\n" + "CPUDelay:\n" + " subs r0, #1\n" + " bne.n CPUDelay\n" + " bx lr\n"); + +#elif defined(__clang__) +void CPUDelay(uint32_t count) +{ + (void)count; // Linter does not see the use of r0 in asm. + // Loop the specified number of times + __asm(" subs r0, #1\n" + " bne.n CPUDelay\n" + " bx lr"); +} +#else +// GCC +void __attribute__((naked)) CPUDelay(uint32_t count) +{ + // Loop the specified number of times + __asm volatile(".syntax unified\n" + "%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r"(count)); +} +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h new file mode 100644 index 00000000..3681d8a1 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h @@ -0,0 +1,120 @@ +/****************************************************************************** + * Filename: cpu.h + * + * Description: Defines and prototypes for the CPU instruction wrapper + * functions. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup cpu_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Provide a small non-zero delay using a simple loop counter. +//! +//! This function provides means for generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \note It is not recommended using this function for long delays. +//! +//! Notice that interrupts can affect the delay if not manually disabled in advance. +//! +//! The delay depends on where code resides and the path for code fetching: +//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) +//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop +//! - Code in flash, cache disabled : 7 cycles per loop +//! - Code in SRAM : 6 cycles per loop +//! - Code in GPRAM : 3 cycles per loop +//! +//! \note If using an RTOS, consider using RTOS provided delay functions because +//! these will not block task scheduling and will potentially save power. +//! +//! Calculate delay count based on the wanted delay in microseconds (us): +//! - count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! +//! Example: 250 us delay with code in flash and with cache and prefetch enabled: +//! - count = 250 * 48 / 4 = 3000 +//! +//! \param count is the number of delay loop iterations to perform. Number must be greater than zero. +//! +//! \return None +// +//***************************************************************************** +extern void CPUDelay(uint32_t count); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __CPU_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu_doc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu_doc.h new file mode 100644 index 00000000..f62ae72c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * Filename: cpu_doc.h + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +//! \addtogroup cpu_api +//! @{ +//! \section sec_cpu Introduction +//! +//! The CPU API provides a set of functions performing very low-level control of the system CPU. +//! All functions in this API are written in assembler in order to either access special registers +//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: +//! One version for each supported compiler. +//! @} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.c new file mode 100644 index 00000000..e943a717 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.c @@ -0,0 +1,53 @@ +/****************************************************************************** + * Filename: debug.c + * + * Description: Driver for the Debug functionality (NB. This is a stub which + * should never be included in a release). + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "../inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +void __error__(char *pFilename, uint32_t line) +{ + (void)pFilename; + (void)line; + // Error catching. + // User can implement custom error handling for failing ASSERTs. + // Setting breakpoint here allows tracing of the failing ASSERT. + while (true) {} +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.h new file mode 100644 index 00000000..0b1b4b4a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/debug.h @@ -0,0 +1,82 @@ +/****************************************************************************** + * Filename: debug.h + * + * Description: Macros for assisting debug of the driver library. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup debug_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +extern void __error__(char *pFilename, uint32_t line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG + #define ASSERT(expr) \ + { \ + if (!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } + +#else + #define ASSERT(expr) +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __DEBUG_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/flash.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/flash.h new file mode 100644 index 00000000..f2bed7fc --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/flash.h @@ -0,0 +1,307 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "../inc/hw_types.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_fcfg.h" +#include "../inc/hw_vims.h" +#include "hapi.h" +#include "chipinfo.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// Values that can be returned from the API functions +//***************************************************************************** +#define FAPI_STATUS_SUCCESS 0x00000000 ///< Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 ///< FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 ///< FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH 0x00000003 ///< Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 ///< Flash program/erase operation failed +#define FAPI_STATUS_ADDRESS_ERROR 0x00000005 ///< Address range or alignment error +#define FAPI_STATUS_INVALID_KEY 0x00000010 ///< Invalid random jump protection key + +//***************************************************************************** +// +//! \brief Get size of a flash sector in number of bytes. +//! +//! This function will return the size of a flash sector in number of bytes. +//! +//! \return Returns size of a flash sector in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashGetSectorSize(void) +{ + return (FLASH_MAIN_SECTOR_SIZE); +} + +//***************************************************************************** +// +//! \brief Get the size of the flash. +//! +//! This function returns the size of the flash main bank in number of bytes. +//! +//! \return Returns the flash size in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashGetSize(void) +{ + // Return flash size in number of bytes + return (FLASH_MAIN_SIZE); +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine has detected an error. +//! +//! This function returns the status of the Flash State Machine indicating if +//! an error is detected or not. Primary use is to check if an Erase or +//! Program operation has failed. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAM while any part of the flash is being programmed or erased. +//! +//! \return Returns status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_ERROR +//! - \ref FAPI_STATUS_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashCheckFsmForError(void) +{ + if (HWREG(FLASH_BASE + FLASH_O_STATCMD) & FLASH_STATCMD_CMDPASS_M) + { + return (FAPI_STATUS_SUCCESS); + } + else + { + return (FAPI_STATUS_FSM_ERROR); + } +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine is ready. +//! +//! This function returns the status of the Flash State Machine indicating if +//! it is ready to accept a new command or not. Primary use is to check if an +//! Erase or Program operation has finished. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAMh while any part of the flash is being programmed or erased. +//! +//! \return Returns readiness status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_READY +//! - \ref FAPI_STATUS_FSM_BUSY +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashCheckFsmForReady(void) +{ + uint32_t reg = HWREG(FLASH_BASE + FLASH_O_STATCMD); + + if (((reg & FLASH_STATCMD_CMDINPROGRESS_M) == 0) || + (reg & FLASH_STATCMD_CMDDONE_M)) + { + return (FAPI_STATUS_FSM_READY); + } + else + { + return (FAPI_STATUS_FSM_BUSY); + } +} + +//***************************************************************************** +// +//! \brief Erase a flash sector. +//! +//! This function will erase the specified flash sector. The function will +//! not return until the flash sector has been erased or an error condition +//! occurred. If flash top sector is erased the function will program the +//! the device security data bytes with default values. The device security +//! data located in the customer configuration area of the flash top sector, +//! must have valid values at all times. These values affect the configuration +//! of the device during boot. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! \param sectorAddress is the starting address in flash of the sector to be +//! erased. +//! +//! \return Returns the status of the sector erase: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashEraseSector(uint32_t sectorAddress) +{ + // Store current configuration + uint32_t cchctrl = HWREG(VIMS_BASE + VIMS_O_CCHCTRL); + // Clear instruction cache + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = (VIMS_CCHCTRL_CCHMPEN_DIS | VIMS_CCHCTRL_CCHPFEN_DIS | VIMS_CCHCTRL_CCHEN_DIS); + + uint32_t retCode = HapiFlashSectorErase(FLASH_API_KEY, sectorAddress); + + // Restore configuration + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = cchctrl; + + return (retCode); +} + +/***************************************************************************** + * \brief Erase all unprotected sectors in the flash main bank + * + * This function will erase all unprotected main bank flash sectors. It will + * not return until the flash sectors has been erased or an error condition + * occurs. + * + * \warning Please note that code can not execute in flash while any part of + * the flash is being programmed or erased. The application must disable + * interrupts that have interrupt routines in flash. + * + * \return Returns the status of the sector erase: + * - \ref FAPI_STATUS_SUCCESS (0): Success + * - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. + *****************************************************************************/ +__STATIC_INLINE uint32_t FlashEraseBank(void) +{ + // Store current configuration + uint32_t cchctrl = HWREG(VIMS_BASE + VIMS_O_CCHCTRL); + + // Clear instruction cache + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = (VIMS_CCHCTRL_CCHMPEN_DIS | VIMS_CCHCTRL_CCHPFEN_DIS | VIMS_CCHCTRL_CCHEN_DIS); + + uint32_t retCode = HapiFlashBankErase(FLASH_API_KEY); + + // Restore configuration + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = cchctrl; + + return (retCode); +} + +//***************************************************************************** +// +//! \brief Programs unprotected flash sectors in the main bank. +//! +//! This function programs a sequence of bytes into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a byte can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! This function does not return until the data has been programmed or a +//! programming error occurs. +//! +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! The \c dataBuffer pointer can not point to flash. +//! +//! \param dataBuffer is a pointer to the data to be programmed. +//! \param address is the starting address in flash to be programmed. +//! \param count is the number of bytes to be programmed. +//! +//! \return Returns status of the flash programming: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +__STATIC_INLINE uint32_t FlashProgram(uint8_t *dataBuffer, uint32_t address, uint32_t count) +{ + // Store current configuration + uint32_t cchctrl = HWREG(VIMS_BASE + VIMS_O_CCHCTRL); + + // Clear instruction cache + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = (VIMS_CCHCTRL_CCHMPEN_DIS | VIMS_CCHCTRL_CCHPFEN_DIS | VIMS_CCHCTRL_CCHEN_DIS); + + uint32_t retCode = HapiFlashProgram(FLASH_API_KEY, dataBuffer, address, count); + + // Restore configuration + HWREG(VIMS_BASE + VIMS_O_CCHCTRL) = cchctrl; + + return (retCode); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __FLASH_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.c new file mode 100644 index 00000000..de61ca03 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.c @@ -0,0 +1,38 @@ +/****************************************************************************** + * Filename: gpio.c + * + * Description: Driver for the GPIO + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "gpio.h" + +// see gpio.h for implementation diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h new file mode 100644 index 00000000..595c859e --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h @@ -0,0 +1,601 @@ +/****************************************************************************** + * Filename: gpio.h + * + * Description: Defines and prototypes for the GPIO. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpio.h" +#include "debug.h" + +//***************************************************************************** +// +// Check for legal range of variable dioNumber +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG + #include "chipinfo.h" + +static bool dioNumberLegal(uint32_t dioNumber) +{ + // TODO: Implement properly + // Get number of GPIOs supported by platform. Number of DIOs is NUMDIO + 1. + // Actual number available may be less for some package types. + uint32_t numDio = 1 + ((HWREG(GPIO_BASE + GPIO_O_DESCEX) & GPIO_DESCEX_NUMDIO_M) >> GPIO_DESCEX_NUMDIO_S); + return (dioNumber < numDio); +} +#endif + +//***************************************************************************** +// +// The following values define the bit field for the GPIO DIOs. +// +//***************************************************************************** +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask + +//***************************************************************************** +// +// Define constants that shall be passed as the outputEnableValue parameter to +// GPIOSetOutputEnableDio() and will be returned from the function +// GPIOGetOutputEnableDio(). +// +//***************************************************************************** +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads a specific DIO. +//! +//! \param dioNumber specifies the DIO to read (0-31). +//! +//! \return Returns 0 or 1 reflecting the input value of the specified DIO. +//! +//! \sa \ref GPIOReadMultiDio(), \ref GPIOWriteDio(), \ref GPIOWriteMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOReadDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Return the input value from the specified DIO. + return ((HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber) & 1); +} + +//***************************************************************************** +// +//! \brief Reads the input value for the specified DIOs. +//! +//! This function returns the input value for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to read. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return Returns a bit vector reflecting the input value of the corresponding DIOs. +//! - 0 : Corresponding DIO is low. +//! - 1 : Corresponding DIO is high. +//! +//! \sa \ref GPIOReadDio(), \ref GPIOWriteDio(), \ref GPIOWriteMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOReadMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Return the input value from the specified DIOs. + return (HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask); +} + +//***************************************************************************** +// +//! \brief Writes a value to a specific DIO. +//! +//! \param dioNumber specifies the DIO to update (0-31). +//! \param value specifies the value to write +//! - 0 : Logic zero (low) +//! - 1 : Logic one (high) +//! +//! \return None +//! +//! \sa \ref GPIOWriteMultiDio(), \ref GPIOReadDio(), \ref GPIOReadMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOWriteDio(uint32_t dioNumber, uint32_t value) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((value == 0) || (value == 1)); + + // Write 0 or 1 to the byte indexed DOUT map + HWREGB( GPIO_BASE + GPIO_O_DOUT3_0 + dioNumber ) = value; +} + +//***************************************************************************** +// +//! \brief Writes masked data to the specified DIOs. +//! +//! Enables for writing multiple bits simultaneously. +//! The value to write must be shifted so it matches the corresponding dioMask bits. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs to write. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits. +//! +//! \return None +//! +//! \sa \ref GPIOWriteDio(), \ref GPIOReadDio(), \ref GPIOReadMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOWriteMultiDio(uint32_t dioMask, uint32_t bitVectoredValue) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = (HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask) | + (bitVectoredValue & dioMask); +} + +//***************************************************************************** +// +//! \brief Sets a specific DIO to 1 (high). +//! +//! \param dioNumber specifies the DIO to set (0-31). +//! +//! \return None +//! +//! \sa \ref GPIOSetMultiDio(), \ref GPIOClearDio(), \ref GPIOClearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOSetDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Set the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = (1 << dioNumber); +} + +//***************************************************************************** +// +//! \brief Sets the specified DIOs to 1 (high). +//! +//! \param dioMask is the bit-mask representation of the DIOs to set. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return None +//! +//! \sa \ref GPIOSetDio(), \ref GPIOClearDio(), \ref GPIOClearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOSetMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Set the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Clears a specific DIO to 0 (low). +//! +//! \param dioNumber specifies the DIO to clear (0-31). +//! +//! \return None +//! +//! \sa \ref GPIOClearMultiDio(), \ref GPIOSetDio(), \ref GPIOSetMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOClearDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Clear the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = (1 << dioNumber); +} + +//***************************************************************************** +// +//! \brief Clears the specified DIOs to 0 (low). +//! +//! \param dioMask is the bit-mask representation of the DIOs to clear. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return None +//! +//! \sa \ref GPIOClearDio(), \ref GPIOSetDio(), \ref GPIOSetMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOClearMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Clear the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Toggles a specific DIO. +//! +//! \param dioNumber specifies the DIO to toggle (0-31). +//! +//! \return None +//! +//! \sa \ref GPIOToggleMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOToggleDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Toggle the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = (1 << dioNumber); +} + +//***************************************************************************** +// +//! \brief Toggles the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs to toggle. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return None +//! +//! \sa \ref GPIOToggleDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOToggleMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Toggle the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Gets the output enable status of a specific DIO. +//! +//! This function returns the output enable status for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). +//! +//! \return Returns one of the enumerated data types (0 or 1): +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \sa \ref GPIOGetOutputEnableMultiDio(), \ref GPIOSetOutputEnableDio(), \ref GPIOSetOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOGetOutputEnableDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Return the output enable status for the specified DIO. + return ((HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber) & 1); +} + +//***************************************************************************** +// +//! \brief Gets the output enable setting of the specified DIOs. +//! +//! This function returns the output enable setting for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits. +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \sa \ref GPIOGetOutputEnableDio(), \ref GPIOSetOutputEnableDio(), \ref GPIOSetOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOGetOutputEnableMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Return the output enable value for the specified DIOs. + return (HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask); +} + +//***************************************************************************** +// +//! \brief Sets output enable of a specific DIO. +//! +//! This function sets the GPIO output enable bit for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to configure (0-31). +//! \param outputEnableValue specifies the output enable setting of the specified DIO: +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \return None +//! +//! \sa \ref GPIOSetOutputEnableMultiDio(), \ref GPIOGetOutputEnableDio(), \ref GPIOGetOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOSetOutputEnableDio(uint32_t dioNumber, uint32_t outputEnableValue) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((outputEnableValue == GPIO_OUTPUT_DISABLE) || (outputEnableValue == GPIO_OUTPUT_ENABLE)); + + // Update the output enable bit for the specified DIO. + if (outputEnableValue == GPIO_OUTPUT_ENABLE) + { + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) |= (1 << dioNumber); + } + else + { + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) &= ~(1 << dioNumber); + } +} + +//***************************************************************************** +// +//! \brief Configures the output enable setting for all specified DIOs. +//! +//! This function configures the output enable setting for the specified DIOs. +//! The output enable setting must be shifted so it matches the corresponding dioMask bits. +//! The DIOs can be configured as either an input or output under software control. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to configure the +//! output enable setting. The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits: +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \return None +//! +//! \sa \ref GPIOSetOutputEnableDio(), \ref GPIOGetOutputEnableDio(), \ref GPIOGetOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOSetOutputEnableMultiDio(uint32_t dioMask, uint32_t bitVectoredOutputEnable) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = (HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask) | + (bitVectoredOutputEnable & dioMask); +} + +//***************************************************************************** +// +//! \brief Gets the event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO to get the event status from (0-31). +//! +//! \return Returns the current event status on the specified DIO. +//! - 0 : Non-triggered event. +//! - 1 : Triggered event. +//! +//! \sa \ref GPIOGetEventMultiDio(), \ref GPIOClearEventDio(), \ref GPIOClearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOGetEventDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Return the event status for the specified DIO. + return ((HWREG( GPIO_BASE + GPIO_O_RIS ) >> dioNumber) & 1); +} + +//***************************************************************************** +// +//! \brief Gets the event status of the specified DIOs. +//! +//! This function returns the event status for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to get the +//! event status from (0-31). +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return Returns a bit vector with the current event status corresponding to the specified DIOs. +//! - 0 : Corresponding DIO has no triggered event. +//! - 1 : Corresponding DIO has a triggered event. +//! +//! \sa \ref GPIOGetEventDio(), \ref GPIOClearEventDio(), \ref GPIOClearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOGetEventMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Return the event status for the specified DIO. + return (HWREG( GPIO_BASE + GPIO_O_RIS ) & dioMask); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO on which to clear the event status (0-31). +//! +//! \return None +//! +//! \sa \ref GPIOClearEventMultiDio(), \ref GPIOGetEventDio(), \ref GPIOGetEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOClearEventDio(uint32_t dioNumber) +{ + // Check the arguments. + ASSERT(dioNumberLegal(dioNumber)); + + // Clear the event status for the specified DIO. + HWREG( GPIO_BASE + GPIO_O_ICLR ) = (1 << dioNumber); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status on the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to +//! clear the events status. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_25_MASK +//! +//! \return None +//! +//! \sa \ref GPIOClearEventDio(), \ref GPIOGetEventDio(), \ref GPIOGetEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOClearEventMultiDio(uint32_t dioMask) +{ + // Check the arguments. + ASSERT(dioMask & GPIO_DIO_ALL_MASK); + + // Clear the event status for the specified DIOs. + HWREG( GPIO_BASE + GPIO_O_ICLR ) = dioMask; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __GPIO_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio_doc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio_doc.h new file mode 100644 index 00000000..b4d7350f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio_doc.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * Filename: gpio_doc.h + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +//! \addtogroup gpio_api +//! @{ +//! \section sec_gpio Introduction +//! +//! The GPIO module allows software to control the pins of the device directly. +//! +//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC +//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the +//! System CPU can write these DIOs through the GPIO module. +//! +//! The IOC module can also be configured to generate events on edge detection and these events can be +//! read and cleared in the GPIO module by the System CPU. +//! +//! \section sec_gpio_api API +//! +//! The API functions can be grouped like this: +//! +//! Set and get direction of DIO (output enable): +//! - \ref GPIOSetOutputEnableDio() +//! - \ref GPIOSetOutputEnableMultiDio() +//! - \ref GPIOGetOutputEnableDio() +//! - \ref GPIOGetOutputEnableMultiDio() +//! +//! Write DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIOWriteDio() +//! - \ref GPIOWriteMultiDio() +//! +//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIOSetDio() +//! - \ref GPIOSetMultiDio() +//! - \ref GPIOClearDio() +//! - \ref GPIOClearMultiDio() +//! - \ref GPIOToggleDio() +//! - \ref GPIOToggleMultiDio() +//! +//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in +//! IOC): +//! - \ref GPIOReadDio() +//! - \ref GPIOReadMultiDio() +//! +//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input +//! enable in IOC): +//! - \ref GPIOGetEventDio() +//! - \ref GPIOGetEventMultiDio() +//! - \ref GPIOClearEventDio() +//! - \ref GPIOClearEventMultiDio() +//! +//! @} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h new file mode 100644 index 00000000..a7c178df --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h @@ -0,0 +1,487 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __HAPI_H__ +#define __HAPI_H__ + +#include +#include "sha256sw.h" + +/*! Magic value used to protect against inadvertent flash erasures/programming. + * (prevents corruption due to random jumps into the flash API, for example + * due to stack overflow or errant function pointers) + * Must be passed in key argument to all flash functions + */ +#define FLASH_API_KEY 0xB7E3A08F + +/*! Define HAPI table and the functions it points to */ +typedef struct +{ + // 0: Enter standby power state (from privileged thread mode with MSP as call stack) + void (*enterStandby)(const uint32_t *copyList); + // 1: [Utility] Calculate CRC32 over nBytes bytes at data + uint32_t (*crc32)(const uint8_t *data, uint32_t nBytes); + // 2: Apply copy list + void (*applyCopyList)(const uint32_t *list); + // 3: Erase (main) flash sector + uint32_t (*flashSectorErase)(uint32_t key, uint32_t sectorAddress); + // 4: Erase (main) flash bank + uint32_t (*flashBankErase)(uint32_t key); + // 5: Program (main) flash sector + uint32_t (*flashProgram)(uint32_t key, const uint8_t *dataBuffer, uint32_t address, uint32_t nBytes); + // 6: [Utility] Hamming weight of 32b word (number of bits set) + uint32_t (*countBits)(uint32_t word); + // 7: [Utility] Perform SECDED encoding on array of 64b words + void (*secdedEncode)(uint8_t *parity, const uint64_t *data, uint32_t nWords64); + // 8: [Utility] Perform SECDED detection/correction on array of 64b words and parity bytes + int32_t (*secdedDecode)(uint64_t *data, const uint8_t *parity, uint32_t nWords64); + // 9: Function to be called from boot code or bootloader to enter application properly + void (*enterApplication)(); + // 10: SHA256: hash single block of data and produce digest + int_fast16_t (*sha256SwHashData)(SHA256SW_Handle handle, + SHA2SW_HashType hashType, // Only SHA2SW_HASH_TYPE_256 supported + const void *data, + size_t length, + uint32_t digest[8]); + // 11: SHA256: initialize hash state + int_fast16_t (*sha256SwStart)(SHA256SW_Handle handle, + SHA2SW_HashType hashType // Only SHA2SW_HASH_TYPE_256 supported + ); + // 12: SHA256: update hash with data + int_fast16_t (*sha256SwAddData)(SHA256SW_Handle handle, const void *data, size_t length); + // 13: SHA256: finalize and produce digest + int_fast16_t (*sha256SwFinalize)(SHA256SW_Handle handle, uint32_t digest[8]); + // 14: [Utility] Reset device + void (*resetDevice)(void); + // 15: SHA256: Process Block + void (*sha256SwProcessBlock)(uint32_t digest[8], uint32_t Ws[16]); + // 16: SHA256: Round constants + const uint32_t (*sha256SW_K256)[64]; + // 17: SHA256: Initial constants + const uint32_t (*sha256SW_initialDigest256)[8]; + // 18: Busy loop that waits for nUs microseconds + void (*waitUs)(uint32_t nUs); + // 19: Count leading zeros + uint32_t (*clz)(uint32_t x); +} HARD_API_T; + +// Define address of HAPI table in ROM and macro for pointer to it +#define HAPI_TABLE_BASE_ADDR 0x0F00004C +#define HAPI_TABLE_POINTER ((const HARD_API_T *)HAPI_TABLE_BASE_ADDR) + +// ------------------------------------------------------------ +// Macros used in applications to actually call HAPI functions +// ------------------------------------------------------------ + +// void HapiEnterStandby(const uint32_t *copyList) +/***************************************************************************** + * \brief Enter standby power state + * Stores the full state of the CPU to MSP call stack so that it can get + * restored once we come back out of standby (at which point CPU is reset). + * When exiting standby the CPU will appear to return from this function. + * + * \param[in] copyList + * If non-null, the copy list to apply through ApplyCopyList() in the + * AsmExitStandby function while waiting for flash to become ready. + * + * \pre + * - Execution state is privileged and call stack being used is MSP + * - MSP call stack must reside in retained SRAM (obviously) + * - Interrupts have been turned off with CPSID but interrupts enabled in NVIC + * - Wakeup event(s) have been configured in AON event fabric + * - SCB.SCR.DSLP_EN=0 (if not, in debug standby exit will enter standby again) + * \warning + * The preconditions must be followed to the letter or bad things will happen + * \note + * Clobbers r0-r3 (normal per AAPCS) + *****************************************************************************/ +#define HapiEnterStandby(p) HAPI_TABLE_POINTER->enterStandby((p)) + +// uint32_t HapiCrc32(const uint8_t *data, uint32_t nBytes) +/***************************************************************************** + * \brief Calculate CRC32 over a data image + * CRC32 implementation that uses a 256-entry LUT + * + * \param[in] data + * Pointer to the image data + * \param[in] nBytes + * Size of image in bytes + * + * \return + * CRC-32 checksum of the image + *****************************************************************************/ +#define HapiCrc32(p, n) HAPI_TABLE_POINTER->crc32((p), (n)) + +// void HapiApplyCopyList(const uint32_t *list) +/***************************************************************************** + * \brief Process copy list + * Processes a copy list in a flexible CopyList format. Used by trims + * in FCFG, for user-defined initialization in CCFG and may be used by + * peripheral drivers to do HW reinitialization during wakeup from standby. + * The copy list is processed as a sequence of 32b command words, followed by + * zero or more literal words (LW): + * + * Command |31:28|27:20 |19:2 |1:0|LW|Description + * -------------|-----|---------|----------------------|---|--|------------------- + * EOL |0000 |0000_0000|0000_0000_0000_0000_00|00 |0 |End-of-list + * WAIT(N) |0001 |0000_0000|nnnn_nnnn_nnnn_nnnn_nn|00 |0 |Wait N/12 us + * NOP = WAIT(0)|0001 |0000_0000|0000_0000_0000_0000_00|00 |0 |No operation + * CPY(A*,N) |aaaa |nnnn_nnnn|aaaa_aaaa_aaaa_aaaa_aa|00 |N |Copy N literal words to address A* + * CPY(A,1) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|01 |1 |Copy single literal word to full address A + * JMP(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|10 |0 |Jump to new list at full address A + * CALL(A) |aaaa |aaaa_aaaa|aaaa_aaaa_aaaa_aaaa_aa|11 |0 |Recurse to list at full address A + * + * A* is a reduced address space that covers all SRAM and peripheral space. + * Bits 27:20 of this address will be assumed to be all zero. Full addresses + * must have 32b alignment + * + * \param[in] list + * Pointer to the copy list + *****************************************************************************/ +#define HapiApplyCopyList(p) HAPI_TABLE_POINTER->applyCopyList((p)) + +// uint32_t HapiFlashSectorErase(uint32_t key, uint32_t addr); +/***************************************************************************** + * \brief Erase a flash sector. + * + * Erase the flash sector that begins at address addr. Function will not return + * before erase operation completes or error occurs. Only main sectors and the + * CCFG sector is supported and are subject to flash write/erase restrictions. + * No default data is written back to CCFG after an erase. + * + * \warning No accesses to flash may occur during an erase operation. Interrupts + * must be disabled prior to calling or care taken that no reads to flash occur. + * DMA operations targeting flash must be suspended. + * + * \param key + * Magic number \ref FLASH_API_KEY (0xB7E3A08F) to protect against inadvertent + * flash erasures + * \param addr + * First address of a main sector or the CCFG sector + * + * \return + * Return code + * - \ref FAPI_STATUS_SUCCESS (0) + * - \ref FAPI_STATUS_ADDRESS_ERROR + * - \ref FAPI_STATUS_INVALID_KEY + * - \ref FAPI_STATUS_FSM_ERROR + *****************************************************************************/ +#define HapiFlashSectorErase(k, p) HAPI_TABLE_POINTER->flashSectorErase((k), (p)) + +// uint32_t HapiFlashBankErase(uint32_t key); +/****************************************************************************** + * \brief Erase all unprotected sectors in the flash main bank. + * + * Function will not return before mass erase operation completes or error occurs. + * + * \warning No accesses to flash may occur during an erase operation. Interrupts + * must be disabled prior to calling or care taken that no reads to flash occur. + * DMA operations targeting flash must be suspended. + * + * \param key + * Magic number \ref FLASH_API_KEY (0xB7E3A08F) to protect against inadvertent + * flash erasures + * + * \return + * Return code + * - \ref FAPI_STATUS_SUCCESS (0) + * - \ref FAPI_STATUS_INVALID_KEY + * - \ref FAPI_STATUS_FSM_ERROR + *****************************************************************************/ +#define HapiFlashBankErase(k) HAPI_TABLE_POINTER->flashBankErase((k)) + +// uint32_t HapiFlashProgram(uint32_t key, const uint8_t *data, uint32_t addr, uint32_t nBytes) +/****************************************************************************** + * \brief Program to flash (MAIN or CCFG) + * + * This function programs a sequence of bytes into the on-chip flash. + * Programming each location consists of the result of an AND operation + * of the new data and the existing data; in other words bits that contain + * 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed + * to 1. Therefore, a byte can be programmed multiple times as long as these + * rules are followed; if a program operation attempts to change a 0 bit to + * a 1 bit, that bit will not have its value changed. + * + * Programming may cross main sector boundaries. This function does not + * return until the data has been programmed or a programming error occurs. + * + * \note It is recommended to disable cache and line buffer before + * programming the flash and re-enable/clear cache and line buffer when the + * program operation completes. + * + * \warning Please note that code can not execute in flash while any part of + * the flash is being programmed or erased. The application must disable + * interrupts that have interrupt routines in flash. + * + * \warning The \c data pointer can not point to flash. + * + * \param key + * Magic number that must be \ref FLASH_API_KEY. The key protects against + * random jumps into the flash API + * \param data + * Pointer to the byte array of new data to be programmed + * \param addr + * First byte address in flash to be programmed + * \param nBytes + * Number of bytes to be programmed + * + * \return + * Return code + * - \ref FAPI_STATUS_SUCCESS (0) + * - \ref FAPI_STATUS_ADDRESS_ERROR + * - \ref FAPI_STATUS_INVALID_KEY + * - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH + * - \ref FAPI_STATUS_FSM_ERROR + *****************************************************************************/ +#define HapiFlashProgram(k, s, d, n) HAPI_TABLE_POINTER->flashProgram((k), (s), (d), (n)) + +// uint32_t HapiCountBits(uint32_t word) +/***************************************************************************** + * \brief Return Hamming weight (# bits that are set) of word + * + * \param[in] word + * 32-bit word to count bits for + * + * \return + * Number of bits set in word (0-32) + *****************************************************************************/ +#define HapiCountBits(w) HAPI_TABLE_POINTER->countBits((w)) + +// void HapiSecdedEncode(uint8_t *parity, const uint64_t *data, uint32_t nWords64) +/***************************************************************************** + * \brief Perform SECDED encoding over data array and produce parity array + * Uses the usual (72,64) SECDED generator matrix: + * DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD PPPPPPPP + * 66665555 55555544 44444444 33333333 33222222 22221111 11111100 00000000 00000000 + * 32109876 54321098 76543210 98765432 10987654 32109876 54321098 76543210 76543210 + * ------------------------------------------------------------------------------------- + * P7: 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 01111111 + * P6: 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111110 00000000 + * P5: 11111111 11111111 11111111 11111111 00000000 00000000 00000000 00000001 00000000 + * P4: 11111111 11111111 00000000 00000000 11111111 11111111 00000000 00000001 00000000 + * P3: 11111111 00000000 11111111 00000000 11111111 00000000 11111111 00000001 00000000 + * P2: 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110001 00000000 + * P1: 11001100 11001100 11001100 11001100 11001100 11001100 11001100 11001101 00000000 + * P0: 10101010 10101010 10101010 10101010 10101010 10101010 10101010 10101011 00000000 + * + * \param[out] parity + * Pointer to where to store parity bytes (one byte per 64b word of data) + * \param[in] data + * Pointer to the data (4B aligned) + * \param[in] nWords64 + * Number of 64b words of data / bytes of parity + *****************************************************************************/ +#define HapiSecdedEncode(p, d, n) HAPI_TABLE_POINTER->secdedEncode((p), (d), (n)) + +// int32_t HapiSecdedDecode(uint64_t *data, const uint8_t *parity, uint32_t nWords64) +/***************************************************************************** + * \brief Perform SECDED correction/detection over data array using parity array + * Uses the usual (72,64) SECDED generator matrix. + * + * \param[inout] data + * Pointer to the data (4B aligned) + * \param[in] parity + * Pointer to the parity bytes (one byte per 64b word of data) + * \param[in] nWords64 + * Number of 64b words of data / bytes of parity + * + * \return + * <0: uncorrectable error detected + * >=0: number of bits corrected + *****************************************************************************/ +#define HapiSecdedDecode(d, p, n) HAPI_TABLE_POINTER->secdedDecode((d), (p), (n)) + +// void BootEnterApplication(void) +/***************************************************************************** + * \brief Called from bootloader to transfer into application + * When called from a bootloader this function will apply application security + * restrictions and transfer to application (set up VTOR register, setup SP and + * jump to entry point as defined by application vector table in CCFG). The + * function will never return. + * + * When called from an application the function will return without doing + * anything. + *****************************************************************************/ +#define HapiEnterApplication() HAPI_TABLE_POINTER->enterApplication() + +// int_fast16_t HapiSha256SwHashData( +// SHA256SW_Handle handle, +// const void *data, +// size_t length, +// uint32_t digest[8] +// ) +/***************************************************************************** + * \brief Performs a complete SHA256 hash operation, producing a final + * digest for the data. + * + * This function wraps #HapiSha256SwStart(), #HapiSha256SwAddData(), and + * #HapiSha256SwFinalize(). + * + * There is no need to call #HapiSha256SwStart() prior to calling this function. + * + * The total length of data that can be hashed by this implementation + * is 512MiB (0x20000000 bytes.) + * + * \param[in] handle A #SHA256SW_Handle. + * + * \param[in] data Data (message) to hash. May point to zero. + * + * \param[in] length The number of bytes (pointed to by \c data parameter) + * to add to the hash. + * + * \param[out] digest Output location for the final digest. Must be + * able to hold 32 bytes of output and be 32-bit aligned. + * + * \retval #SHA2SW_STATUS_SUCCESS (0) The hash operation succeeded. + * \retval #SHA2SW_STATUS_ERROR The hash operation failed. + * \retval #SHA2SW_STATUS_UNSUPPORTED Requested Hash Type is unsupported. + * \retval #SHA2SW_STATUS_LENGTH_TOO_LARGE The requested length of data to hash + * is more than the implementation + * supports. + * \retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + *****************************************************************************/ +#define HapiSha256SwHashData(h, d, l, g) HAPI_TABLE_POINTER->sha256SwHashData((h), SHA2SW_HASH_TYPE_256, (d), (l), (g)) + +// int_fast16_t HapiSha256SwStart(SHA256SW_Handle handle) +/***************************************************************************** + * \brief Initialize a SHA256SW_Handle, preparing for hashing data. + * + * \param[in] handle A #SHA256SW_Handle. + * + * \retval #SHA2SW_STATUS_SUCCESS (0) The hash operation succeeded. + * \retval #SHA2SW_STATUS_UNSUPPORTED Requested Hash Type is unsupported. + * \retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * \sa #HapiSha256SwAddData() + * \sa #HapiSha256SwFinalize() + *****************************************************************************/ +#define HapiSha256SwStart(h) HAPI_TABLE_POINTER->sha256SwStart((h), SHA2SW_HASH_TYPE_256) + +// int_fast16_t HapiSha256SwAddData(SHA256SW_Handle handle, const void *data, size_t length) +/***************************************************************************** + * \brief Add data to a SHA256 operation. + * + * Adds data to a hash operation. The \c handle must have been + * initialized by a call to HapiSha256SwStart first. + * + * The total length of data that can be hashed by this implementation + * is 512MiB (0x20000000 bytes.) + * + * After passing in all data to be hashed, call #HapiSha256SwFinalize() + * to obtain the final digest. + * + * \pre handle was previously passed to #HapiSha256SwStart(). + * + * \param[in] handle A #SHA256SW_Handle. + * + * \param[in] data Data (message) to add to the hash. May point to zero. + * + * \param[in] length The number of bytes (pointed to by \c data parameter) + * to add to the hash. + * + * \retval #SHA2SW_STATUS_SUCCESS (0) The hash operation succeeded. + * \retval #SHA2SW_STATUS_LENGTH_TOO_LARGE The requested length of data to hash + * is more than the implementation + * supports. + * \retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * \sa #HapiSha256SwStart() + * \sa #HapiSha256SwFinalize() + *****************************************************************************/ +#define HapiSha256SwAddData(h, d, l) HAPI_TABLE_POINTER->sha256SwAddData((h), (d), (l)) + +// int_fast16_t HapiSha256SwFinalize(SHA256SW_Handle handle, uint32_t digest[8]); +/***************************************************************************** + * \brief Finalize a SHA256 operation, creating the final digest. + * + * After calling this function, \c handle should not be used again + * until it has been reinitialized via a call to #HapiSha256SwStart(). + * + * \pre handle was previously passed to #HapiSha256SwStart() and data to + * be hashed was passed to #HapiSha256SwAddData() + * + * \param[in] handle A #SHA256SW_Handle. + * + * \param[out] digest Output location for the final digest. Must be + * able to hold 32 bytes of output and be 32-bit aligned. + * + * \retval #SHA2SW_STATUS_SUCCESS (0) The hash operation succeeded. + * \retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * \sa #HapiSha256SwStart() + * \sa #HapiSha256SwAddData() + *****************************************************************************/ +#define HapiSha256SwFinalize(h, g) HAPI_TABLE_POINTER->sha256SwFinalize((h), (g)) + +// __noreturn void HapiResetDevice(void) +/***************************************************************************** + * \brief Perform system reset of the device + * + * This function will perform a system reset of the device equal to a pin + * reset. Software can determine that this was the cause of reset once + * rebooted. The function will never return. + *****************************************************************************/ +#define HapiResetDevice() HAPI_TABLE_POINTER->resetDevice() + +// HAPI entry used for internal purposes +#define HapiSha256SWProcessBlock(d, w) HAPI_TABLE_POINTER->pSHA256SWProcessBlock((d), (w)) + +// HAPI entry used for internal purposes +#define HapiSha256SW_K256 (*HAPI_TABLE_POINTER->sha256SW_K256) + +// HAPI entry used for internal purposes +#define HapiSha256SW_initialDigest256 (*HAPI_TABLE_POINTER->sha256SW_initialDigest256) + +// void HapiWaitUs(uint32_t nUs) +/***************************************************************************** + * \brief Wait function + * + * \param[in] nUs + * Number of microseconds to wait (min: 1 us, max: 2^24 us) + *****************************************************************************/ +#define HapiWaitUs(n) HAPI_TABLE_POINTER->waitUs((n)) + +// uint32_t HapiClz(uint32_t x) +/***************************************************************************** + * \brief Count leading zeros + * + * \param[in] x + * Value to count leading zeros for + * \return + * Number of leading zeroes (0 to 32) + *****************************************************************************/ +#define HapiClz(x) HAPI_TABLE_POINTER->clz((x)) + +#endif //__HAPI_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.c new file mode 100644 index 00000000..397e711c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.c @@ -0,0 +1,103 @@ +/****************************************************************************** + * Filename: i2c.c + * + * Description: Driver for I2C. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "i2c.h" + +//***************************************************************************** +// +// Initializes the I2C Controller module +// +//***************************************************************************** +void I2CControllerInitExpClk(uint32_t base, bool fast) +{ + uint32_t sclFreq; + uint32_t tpr; + + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Must enable the device before doing anything else. + I2CControllerEnable(base); + + // Get the desired SCL speed. + if (fast == true) + { + sclFreq = 400000; + } + else + { + sclFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + tpr = ((I2C_CLK_FREQ + (2 * 10 * sclFreq) - 1) / (2 * 10 * sclFreq)) - 1; + HWREG(base + I2C_O_CTPR) = tpr; +} + +//***************************************************************************** +// +// Gets the error status of the I2C Controller module +// +//***************************************************************************** +uint32_t I2CControllerError(uint32_t base) +{ + uint32_t err; + + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Get the raw error state. + err = HWREG(base + I2C_O_CSTA); + + // If the I2C controller is busy, then all the other status bits are invalid, + // and there is no error to report. + if (err & I2C_CSTA_BUSY_M) + { + return (I2C_CONTROLLER_ERR_NONE); + } + + // Check for errors. + if (err & (I2C_CSTA_ERR_M | I2C_CSTA_ARBLST_M)) + { + return (err & (I2C_CSTA_ARBLST_M | I2C_CSTA_DATACKN_M | I2C_CSTA_ADRACKN_M)); + } + else + { + return (I2C_CONTROLLER_ERR_NONE); + } +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.h new file mode 100644 index 00000000..8738a4cd --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/i2c.h @@ -0,0 +1,844 @@ +/****************************************************************************** + * Filename: i2c.h + * + * Description: Prototypes and defines for the I2C API. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_i2c.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// I2C Controller commands +// +//***************************************************************************** +#define I2C_CONTROLLER_CMD_SINGLE_SEND 0x00000007 +#define I2C_CONTROLLER_CMD_SINGLE_RECEIVE 0x00000007 +#define I2C_CONTROLLER_CMD_BURST_SEND_START 0x00000003 +#define I2C_CONTROLLER_CMD_BURST_SEND_CONT 0x00000001 +#define I2C_CONTROLLER_CMD_BURST_SEND_FINISH 0x00000005 +#define I2C_CONTROLLER_CMD_BURST_SEND_ERROR_STOP 0x00000004 +#define I2C_CONTROLLER_CMD_BURST_RECEIVE_START 0x0000000b +#define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT 0x00000009 +#define I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH 0x00000005 +#define I2C_CONTROLLER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000004 + +//***************************************************************************** +// +// I2C Controller error status +// +//***************************************************************************** +#define I2C_CONTROLLER_ERR_NONE 0 +#define I2C_CONTROLLER_ERR_ADDR_ACK 0x00000004 +#define I2C_CONTROLLER_ERR_DATA_ACK 0x00000008 +#define I2C_CONTROLLER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Target action requests +// +//***************************************************************************** +#define I2C_TARGET_ACT_NONE 0 +#define I2C_TARGET_ACT_RREQ 0x00000001 // Controller has sent data +#define I2C_TARGET_ACT_TREQ 0x00000002 // Controller has requested data +#define I2C_TARGET_ACT_RREQ_FBR 0x00000005 // Controller has sent first byte + +//***************************************************************************** +// +// I2C Target interrupts +// +//***************************************************************************** +#define I2C_TARGET_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_TARGET_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_TARGET_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// I2C module clock frequency +// +//***************************************************************************** +#define I2C_CLK_FREQ 48000000 // Clock supplied to I2C periph in Hz + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2C base address. +//! +//! This function determines if a I2C port base address is valid. +//! +//! \param base is the base address of the I2C port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool I2CBaseValid(uint32_t base) +{ + return (base == I2C0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Initializes the \I2C Controller module. +//! +//! This function initializes operation of the \I2C Controller module. Upon +//! successful initialization of the \I2C module, this function will have set the +//! bus speed for the controller, and will have enabled the \I2C Controller module. +//! +//! If the parameter \c fast is \c true, then the controller module will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! \param base is the base address of the \I2C module. +//! \param fast set up for fast data transfers. +//! +//! \return None +// +//***************************************************************************** +extern void I2CControllerInitExpClk(uint32_t base, bool fast); + +//***************************************************************************** +// +//! \brief Controls the state of the \I2C Controller module. +//! +//! This function is used to control the state of the Controller module send and +//! receive operations. +//! +//! \param base is the base address of the \I2C module. +//! \param cmd is the command to be issued by the \I2C Controller module +//! The parameter can be one of the following values: +//! - \ref I2C_CONTROLLER_CMD_SINGLE_SEND +//! - \ref I2C_CONTROLLER_CMD_SINGLE_RECEIVE +//! - \ref I2C_CONTROLLER_CMD_BURST_SEND_START +//! - \ref I2C_CONTROLLER_CMD_BURST_SEND_CONT +//! - \ref I2C_CONTROLLER_CMD_BURST_SEND_FINISH +//! - \ref I2C_CONTROLLER_CMD_BURST_SEND_ERROR_STOP +//! - \ref I2C_CONTROLLER_CMD_BURST_RECEIVE_START +//! - \ref I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT +//! - \ref I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH +//! - \ref I2C_CONTROLLER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerCommand(uint32_t base, uint32_t cmd) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT((cmd == I2C_CONTROLLER_CMD_SINGLE_SEND) || + // (cmd == I2C_CONTROLLER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND + (cmd == I2C_CONTROLLER_CMD_BURST_SEND_START) || (cmd == I2C_CONTROLLER_CMD_BURST_SEND_CONT) || + (cmd == I2C_CONTROLLER_CMD_BURST_SEND_FINISH) || (cmd == I2C_CONTROLLER_CMD_BURST_SEND_ERROR_STOP) || + (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_START) || (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT) || + (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH) || (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // Send the command. + HWREG(base + I2C_O_CCTL) = cmd; + + // Delay minimum four cycles in order to ensure that the I2C_O_CCTL + // register has been correctly updated before function exit + CPUDelay(2); +} + +//***************************************************************************** +// +//! \brief Sets the address that the \I2C Controller will place on the bus. +//! +//! This function will set the address that the \I2C Controller will place on the +//! bus when initiating a transaction. When the \c receive parameter is set +//! to \b true, the address will indicate that the \I2C Controller is initiating a +//! read from the target; otherwise the address will indicate that the \I2C +//! Controller is initiating a write to the target. +//! +//! \param base is the base address of the \I2C module. +//! \param targetAddr is a 7-bit target address +//! \param receive flag indicates the type of communication with the target. +//! - \c true : \I2C Controller is initiating a read from the target. +//! - \c false : \I2C Controller is initiating a write to the target. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerSetTargetAddr(uint32_t base, uint8_t targetAddr, bool receive) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT(!(targetAddr & 0x80)); + + // Set the address of the target with which the controller will communicate. + HWREG(base + I2C_O_CTA) = (targetAddr << 1) | receive; +} + +//***************************************************************************** +// +//! \brief Enables the \I2C Controller module. +//! +//! This will enable operation of the \I2C Controller module. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerEnable(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Enable the clock for the controller. + HWREG(base + I2C_O_CCR) |= I2C_CCR_CFE_M; + + // Enable the controller module. + HWREG(base + I2C_O_CCTL) = I2C_CCTL_RUN_EN; +} + +//***************************************************************************** +// +//! \brief Disables the \I2C controller module. +//! +//! This will disable operation of the \I2C controller module. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerDisable(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Disable the controller module. + HWREG(base + I2C_O_CCTL) = 0; + + // Disable the clock for the controller. + HWREG(base + I2C_O_CCR) &= ~I2C_CCR_CFE_M; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the \I2C Controller is busy. +//! +//! This function returns an indication of whether or not the \I2C Controller is +//! busy transmitting or receiving data. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return Returns status of \I2C Controller: +//! - \c true : \I2C Controller is busy. +//! - \c false : \I2C Controller is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool I2CControllerBusy(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Return the busy status. + if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSY_M) + { + return (true); + } + else + { + return (false); + } +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the \I2C bus is busy. +//! +//! This function returns an indication of whether or not the \I2C bus is busy. +//! This function can be used in a multi-controller environment to determine if +//! another controller is currently using the bus. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return Returns status of the \I2C bus: +//! - \c true : \I2C bus is busy. +//! - \c false : \I2C bus is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool I2CControllerBusBusy(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Return the bus busy status. + if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSBSY_M) + { + return (true); + } + else + { + return (false); + } +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the \I2C Controller. +//! +//! This function reads a byte of data from the \I2C Controller Data Register. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return Returns the byte received from by the \I2C Controller, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t I2CControllerGetData(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Read a byte. + return (HWREG(base + I2C_O_CDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the \I2C Controller. +//! +//! This function will place the supplied data into \I2C Controller Data Register. +//! +//! \param base is the base address of the \I2C module. +//! \param data is the data to be transmitted by the \I2C Controller +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerPutData(uint32_t base, uint8_t data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Write the byte. + HWREG(base + I2C_O_CDR) = data; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the \I2C Controller module. +//! +//! This function is used to obtain the error status of the Controller module send +//! and receive operations. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return Returns the error status of the Controller module: +//! - \ref I2C_CONTROLLER_ERR_NONE +//! - \ref I2C_CONTROLLER_ERR_ADDR_ACK +//! - \ref I2C_CONTROLLER_ERR_DATA_ACK +//! - \ref I2C_CONTROLLER_ERR_ARB_LOST +// +//***************************************************************************** +extern uint32_t I2CControllerError(uint32_t base); + +//***************************************************************************** +// +//! \brief Enables the \I2C Controller interrupt. +//! +//! Enables the \I2C Controller interrupt source. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerEnableInt(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Enable the controller interrupt. + HWREG(base + I2C_O_CIMR) = I2C_CIMR_IM; +} + +//***************************************************************************** +// +//! \brief Disables the \I2C Controller interrupt. +//! +//! Disables the \I2C Controller interrupt source. +//! +//! \param base is the base address of the \I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerDisableInt(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Disable the controller interrupt. + HWREG(base + I2C_O_CIMR) = 0; +} + +//***************************************************************************** +// +//! \brief Clears \I2C Controller interrupt sources. +//! +//! The \I2C Controller interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any +//! synchronizers) +//! +//! \param base is the base address of the \I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CControllerClearInt(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Clear the I2C controller interrupt source. + HWREG(base + I2C_O_CICR) = I2C_CICR_IC; +} + +//***************************************************************************** +// +//! \brief Gets the current \I2C Controller interrupt status. +//! +//! This returns the interrupt status for the \I2C Controller module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param base is the base address of the \I2C Controller module. +//! \param masked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status. +//! - \c true : Active. +//! - \c false : Not active. +// +//***************************************************************************** +__STATIC_INLINE bool I2CControllerIntStatus(uint32_t base, bool masked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if (masked) + { + return ((HWREG(base + I2C_O_CMIS)) ? true : false); + } + else + { + return ((HWREG(base + I2C_O_CRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! \brief Enables the \I2C Target module. +//! +//! This will enable operation of the \I2C Target module. +//! +//! \param base is the base address of the \I2C Target module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetEnable(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Enable the clock to the target module. + HWREG(base + I2C_O_CCR) |= I2C_CCR_TFE_M; + + // Enable the target. + HWREG(base + I2C_O_TCTL) = I2C_TCTL_DA_EN; +} + +//***************************************************************************** +// +//! \brief Initializes the \I2C Target module. +//! +//! This function initializes operation of the \I2C Target module. Upon +//! successful initialization of the \I2C module, this function will have set +//! the target address and have enabled the \I2C Target module. +//! +//! The parameter \c targetAddr is the value that will be compared against the +//! target address sent by an \I2C controller. +//! +//! \param base is the base address of the \I2C Target module. +//! \param targetAddr is the 7-bit target address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetInit(uint32_t base, uint8_t targetAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT(!(targetAddr & 0x80)); + + // Must enable the device before doing anything else. + I2CTargetEnable(base); + + // Set up the target address. + HWREG(base + I2C_O_TOAR) = targetAddr; +} + +//***************************************************************************** +// +//! \brief Sets the \I2C target address. +//! +//! This function writes the specified target address. +//! +//! \param base is the base address of the \I2C Target module. +//! \param targetAddr is the 7-bit target address +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetSetAddress(uint32_t base, uint8_t targetAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT(!(targetAddr & 0x80)); + + // Set up the primary target address. + HWREG(base + I2C_O_TOAR) = targetAddr; +} + +//***************************************************************************** +// +//! \brief Disables the \I2C target module. +//! +//! This will disable operation of the \I2C target module. +//! +//! \param base is the base address of the \I2C Target module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetDisable(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Disable the target. + HWREG(base + I2C_O_TCTL) = 0x0; + + // Disable the clock to the target module. + HWREG(base + I2C_O_CCR) &= ~I2C_CCR_TFE_M; +} + +//***************************************************************************** +// +//! \brief Gets the \I2C Target module status. +//! +//! This function will return the action requested from a controller, if any. +//! +//! \param base is the base address of the \I2C Target module. +//! +//! \return Returns the status of the \I2C Target module: +//! - \ref I2C_TARGET_ACT_NONE : No action has been requested of the \I2C Target module. +//! - \ref I2C_TARGET_ACT_RREQ : An \I2C controller has sent data to the \I2C Target module. +//! - \ref I2C_TARGET_ACT_TREQ : An \I2C controller has requested that the \I2C Target module send data. +//! - \ref I2C_TARGET_ACT_RREQ_FBR : An \I2C controller has sent data to the \I2C target +//! and the first byte following the target's own address has been received. +// +//***************************************************************************** +__STATIC_INLINE uint32_t I2CTargetStatus(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Return the target status. + return (HWREG(base + I2C_O_TSTA)); +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the \I2C Target. +//! +//! This function reads a byte of data from the \I2C Target Data Register. +//! +//! \param base is the base address of the \I2C Target module. +//! +//! \return Returns the byte received from by the \I2C Target, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t I2CTargetGetData(uint32_t base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Read a byte. + return (HWREG(base + I2C_O_TDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the \I2C Target. +//! +//! This function will place the supplied data into \I2C Target Data Register. +//! +//! \param base is the base address of the \I2C Target module. +//! \param data data to be transmitted from the \I2C Target. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetPutData(uint32_t base, uint8_t data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Write the byte. + HWREG(base + I2C_O_TDR) = data; +} + +//***************************************************************************** +// +//! \brief Enables individual \I2C Target interrupt sources. +//! +//! Enables the indicated \I2C Target interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param base is the base address of the \I2C module. +//! \param intFlags is the bit mask of the target interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_TARGET_INT_STOP +//! - \ref I2C_TARGET_INT_START +//! - \ref I2C_TARGET_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetEnableInt(uint32_t base, uint32_t intFlags) +{ + uint32_t val; + + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT(intFlags & (I2C_TARGET_INT_STOP | I2C_TARGET_INT_START | I2C_TARGET_INT_DATA)); + + // Enable the target interrupt. + val = HWREG(base + I2C_O_TIMR); + val |= intFlags; + HWREG(base + I2C_O_TIMR) = val; +} + +//***************************************************************************** +// +//! \brief Disables individual \I2C Target interrupt sources. +//! +//! Disables the indicated \I2C Target interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param base is the base address of the \I2C Target module. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_TARGET_INT_STOP +//! - \ref I2C_TARGET_INT_START +//! - \ref I2C_TARGET_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetDisableInt(uint32_t base, uint32_t intFlags) +{ + uint32_t val; + + // Check the arguments. + ASSERT(I2CBaseValid(base)); + ASSERT(intFlags & (I2C_TARGET_INT_STOP | I2C_TARGET_INT_START | I2C_TARGET_INT_DATA)); + + // Disable the target interrupt. + val = HWREG(base + I2C_O_TIMR); + val &= ~intFlags; + HWREG(base + I2C_O_TIMR) = val; +} + +//***************************************************************************** +// +//! \brief Clears \I2C Target interrupt sources. +//! +//! The specified \I2C Target interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any +//! synchronizers) +//! +//! \param base is the base address of the \I2C module. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_TARGET_INT_STOP +//! - \ref I2C_TARGET_INT_START +//! - \ref I2C_TARGET_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void I2CTargetClearInt(uint32_t base, uint32_t intFlags) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Clear the I2C target interrupt source. + HWREG(base + I2C_O_TICR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current \I2C Target interrupt status. +//! +//! This returns the interrupt status for the \I2C Target module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \param base is the base address of the \I2C Target module. +//! \param masked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref I2C_TARGET_INT_STOP +//! - \ref I2C_TARGET_INT_START +//! - \ref I2C_TARGET_INT_DATA +// +//***************************************************************************** +__STATIC_INLINE uint32_t I2CTargetIntStatus(uint32_t base, bool masked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if (masked) + { + return (HWREG(base + I2C_O_TMIS)); + } + else + { + return (HWREG(base + I2C_O_TRIS)); + } +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __I2C_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.c new file mode 100644 index 00000000..8fea4fed --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.c @@ -0,0 +1,380 @@ +/****************************************************************************** + * Filename: interrupt.c + * + * Description: Utility functions to interact with interrupts and the NVIC + * + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "interrupt.h" +#include "cpu.h" +#include "debug.h" + +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" + +//***************************************************************************** +// +//! \brief The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None +// +//***************************************************************************** +static void IntDefaultHandler(void) +{ + // Go into an infinite loop. + while (1) {} +} + +//***************************************************************************** +// +//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. +//! +//! Interrupt vector table is placed at ".ramVecs" defined in the linker file +//! provided by Texas Instruments. +//! +//! \note See \ti_code{interrupt.c} for compiler specific implementation! +// +//***************************************************************************** +#if defined(DOXYGEN) +// Dummy void pointer used as placeholder to generate Doxygen documentation. +void (*ramVectorTable[NUM_INTERRUPTS])(void); +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma data_alignment = 256 +static __no_init void (*ramVectorTable[NUM_INTERRUPTS])(void) @ ".ramVecs"; +#elif defined(__clang__) +static __attribute__((section(".ramVecs"), aligned(256))) void (*ramVectorTable[NUM_INTERRUPTS])(void); +#else +static __attribute__((section(".ramVecs"), aligned(256))) void (*ramVectorTable[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +// Registers a function to be called when an interrupt occurs. +// +//***************************************************************************** +void IntRegister(uint32_t intNum, void (*handler)(void)) +{ + uint32_t idx; + uint32_t tmpVtor; + + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Make sure that the RAM vector table is correctly aligned. + ASSERT(((uint32_t)ramVectorTable & 0x000000ff) == 0); + + // See if the RAM vector table has been initialized. + if (SCB->VTOR != (uint32_t)ramVectorTable) + { + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + tmpVtor = SCB->VTOR; + for (idx = 0; idx < NUM_INTERRUPTS; idx++) + { + ramVectorTable[idx] = (void (*)(void))HWREG((idx * 4) + tmpVtor); + } + + // Point NVIC at the RAM vector table. + SCB->VTOR = (uint32_t)ramVectorTable; + } + + // Save the interrupt handler. + ramVectorTable[intNum] = handler; +} + +//***************************************************************************** +// +// Unregisters the function to be called when an interrupt occurs. +// +//***************************************************************************** +void IntUnregister(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Reset the interrupt handler. + ramVectorTable[intNum] = IntDefaultHandler; +} + +//***************************************************************************** +// +// Sets the priority of an interrupt +// +//***************************************************************************** +void IntSetPriority(uint32_t intNum, uint8_t priority) +{ + // Check the arguments. + ASSERT((intNum >= 11) && (intNum < NUM_INTERRUPTS)); + ASSERT((intNum != 12) && (intNum != 13)); + ASSERT(priority <= INT_PRI_LEVEL3); + + uint32_t ipr; + uint32_t mask; + uint32_t shift; + uint32_t offset; + bool intNumWasEnabled; + uint32_t priorityRegIndex; + volatile uint32_t *address; + + // System exception priorities are set in the SHPR registers. + // Indexing starts at SHPR2 (8 <= intNum <= 11) + if (intNum < 16) + { + address = SCB->SHP; + priorityRegIndex = intNum - 8; + } + + // User interrupt (id >= 16) priorities are set in the IPR registers + // Indexing starts at IPR0 (16 <= intNum <= 19) + else + { + address = NVIC->IP; + priorityRegIndex = intNum - 16; + } + + offset = priorityRegIndex >> 2; + shift = (priorityRegIndex & 0x3) * 8; + mask = 0xff << shift; + + intNumWasEnabled = IntIsEnabled(intNum); + + // Disable the interrupt before changing it's priority + IntDisable(intNum); + + ipr = address[offset] & ~mask; + ipr |= (priority & INT_PRIORITY_MASK) << shift; + address[offset] = ipr; + + if (intNumWasEnabled) + { + // Re-enable the interrupt + IntEnable(intNum); + } +} + +//***************************************************************************** +// +// Gets the priority of an interrupt +// +//***************************************************************************** +int32_t IntGetPriority(uint32_t intNum) +{ + // Check the arguments. + ASSERT((intNum >= 11) && (intNum < NUM_INTERRUPTS)); + ASSERT((intNum != 12) && (intNum != 13)); + + uint32_t index = intNum >> 2; + + if (intNum < 16) + { + /* System exception priorities are set in the SHPR registers. + * Indexing starts at SHPR2 (8 <= intNum <= 11) + */ + return ((SCB->SHP[index - 2] >> (8 * (intNum & 3))) & INT_PRIORITY_MASK); + } + else + { + /* User interrupt (id >= 16) priorities are set in the IPR registers + * Indexing starts at IPR0 (16 <= intNum <= 19) + */ + return ((NVIC->IP[index - 4] >> (8 * (intNum & 3))) & INT_PRIORITY_MASK); + } +} + +//***************************************************************************** +// +// Checks whether an interrupt is enabled +// +//***************************************************************************** +bool IntIsEnabled(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + bool isEnabled = false; + + // Determine the interrupt to check. + if (intNum == INT_SYSTICK) + { + // Check the System Tick interrupt. + isEnabled = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk ? true : false; + } + else if ((intNum >= 16) && (intNum <= 47)) + { + // Check the general interrupt. + isEnabled = (NVIC->ISER[0] & (1 << (intNum - 16))) ? true : false; + } + + return isEnabled; +} + +//***************************************************************************** +// +// Enables an interrupt +// +//***************************************************************************** +void IntEnable(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if (intNum == INT_SYSTICK) + { + // Enable the System Tick interrupt. + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + } + else if ((intNum >= 16) && (intNum <= 47)) + { + // Enable the general interrupt. + NVIC->ISER[0] = 1 << (intNum - 16); + } +} + +//***************************************************************************** +// +// Disables an interrupt +// +//***************************************************************************** +void IntDisable(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if (intNum == INT_SYSTICK) + { + // Disable the System Tick interrupt. + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + } + else if ((intNum >= 16) && (intNum <= 47)) + { + // Disable the general interrupt. + NVIC->ICER[0] = 1 << (intNum - 16); + } +} + +//***************************************************************************** +// +// Pends an interrupt +// +//***************************************************************************** +void IntSetPend(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if ((intNum >= 16) && (intNum <= 47)) + { + // Pend the general interrupt. + NVIC->ISPR[0] = 1 << (intNum - 16); + } + else if (intNum == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk; + } + else if (intNum == INT_PENDSV) + { + // Pend the PendSV interrupt. + SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; + } + else if (intNum == INT_SYSTICK) + { + // Pend the SysTick interrupt. + SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk; + } +} + +//***************************************************************************** +// +// Query whether an interrupt is pending +// +//***************************************************************************** +bool IntGetPend(uint32_t intNum) +{ + uint32_t intPending; + + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + intPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (intNum < 16) + { + + return false; + } + + // Subtract lower 16 irq vectors + intNum -= 16; + + // Check if the interrupt is pending + intPending = NVIC->ISPR[0] & (1 << intNum); + + return intPending ? true : false; +} + +//***************************************************************************** +// +// Unpends an interrupt +// +//***************************************************************************** +void IntClearPend(uint32_t intNum) +{ + // Check the arguments. + ASSERT(intNum < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if (intNum == INT_PENDSV) + { + // Unpend the PendSV interrupt. + SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk; + } + else if (intNum == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; + } + else if ((intNum >= 16) && (intNum <= 47)) + { + // Unpend the general interrupt. + NVIC->ICPR[0] = 1 << (intNum - 16); + } +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.h new file mode 100644 index 00000000..7fc7aca0 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/interrupt.h @@ -0,0 +1,410 @@ +/****************************************************************************** + * Filename: interrupt.h + * + * Description: Defines and prototypes for the NVIC Interrupt Controller + * + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" + +#include "../cmsis/cc23x0r5.h" +#include "../cmsis/core/core_cm0plus.h" + +#include "cpu.h" + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Registers a function as an interrupt handler in the dynamic vector table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function writes a function pointer to the dynamic interrupt vector table +//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding +//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function +//! pointer is fetched from the dynamic vector table, and the System CPU will +//! execute the interrupt handler. +//! +//! \note The first call to this function (directly or indirectly via a peripheral +//! driver interrupt register function) copies the interrupt vector table from +//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function +//! is called. +//! +//! \param intNum specifies the index in the vector table to modify. +//! - System exceptions: +//! - INT_NMI_FAULT +//! - INT_HARD_FAULT +//! - INT_SVCALL +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_CPUIRQ0 +//! - INT_CPUIRQ1 +//! - INT_CPUIRQ2 +//! - INT_CPUIRQ3 +//! - INT_CPUIRQ4 +//! - INT_GPIO_COMB +//! - INT_LRFD_IRQ0 +//! - INT_LRFD_IRQ1 +//! - INT_DMA_DONE_COMB +//! - INT_AES_COMB +//! - INT_SPI0_COMB +//! - INT_UART0_COMB +//! - INT_I2C0_IRQ +//! - INT_LGPT0_COMB +//! - INT_LGPT1_COMB +//! - INT_ADC_COMB +//! - INT_CPUIRQ16 +//! - INT_LGPT2_COMB +//! - INT_LGPT3_COMB +//! +//! \param handler is a pointer to the function to register as interrupt handler. +//! +//! \return None. +//! +//! \sa \ref IntUnregister(), \ref IntEnable() +// +//***************************************************************************** +extern void IntRegister(uint32_t intNum, void (*handler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler in the dynamic vector table. +//! +//! This function removes an interrupt handler from the dynamic vector table and +//! replaces it with the default interrupt handler \ref IntDefaultHandler(). +//! +//! \note Remember to disable the interrupt before removing its interrupt handler +//! from the vector table. +//! +//! \param intNum specifies the index in the vector table to modify. +//! - See \ref IntRegister() for list of valid arguments. +//! +//! \return None. +//! +//! \sa \ref IntRegister(), \ref IntDisable() +// +//***************************************************************************** +extern void IntUnregister(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Sets the priority of an interrupt. +//! +//! This function sets the priority of an interrupt, including system exceptions. +//! When multiple interrupts are asserted simultaneously, the ones with the highest +//! priority are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities thus priority 0 is the highest +//! interrupt priority. +//! +//! \warning On Cortex M0+, changing interrupt priorities dynamically is not +//! supported. In order to change the priority of an interrupt, after it has +//! been enabled, the following steps must be followed: +//! - Disable the interrupt whose priority needs to be changed +//! - Change the priority +//! - Re-enable the interrupt +//! This is taken care of by the IntSetPriority function. +//! +//! \warning It is possible to lose an interrupt while its priority is being +//! changed, since that interrupt needs to be disabled to be able change its +//! priority. +//! +//! \warning This function does not support setting priority of interrupt +//! vectors one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param intNum specifies the index in the vector table to change priority for. +//! - System exceptions: +//! - INT_SVCALL +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_CPUIRQ0 +//! - INT_CPUIRQ1 +//! - INT_CPUIRQ2 +//! - INT_CPUIRQ3 +//! - INT_CPUIRQ4 +//! - INT_GPIO_COMB +//! - INT_LRFD_IRQ0 +//! - INT_LRFD_IRQ1 +//! - INT_DMA_DONE_COMB +//! - INT_AES_COMB +//! - INT_SPI0_COMB +//! - INT_UART0_COMB +//! - INT_I2C0_IRQ +//! - INT_LGPT0_COMB +//! - INT_LGPT1_COMB +//! - INT_ADC_COMB +//! - INT_CPUIRQ16 +//! - INT_LGPT2_COMB +//! - INT_LGPT3_COMB +//! +//! \param priority specifies the priority of the interrupt. +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 : Lowest priority. +//! +//! \return None +// +//***************************************************************************** +extern void IntSetPriority(uint32_t intNum, uint8_t priority); + +//***************************************************************************** +// +//! \brief Gets the priority of an interrupt. +//! +//! This function gets the priority of an interrupt. +//! +//! \warning This function does not support getting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param intNum specifies the index in the vector table to read priority of. +//! - See \ref IntSetPriority() for list of valid arguments. +//! +//! \return Returns the interrupt priority: +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 : Lowest priority. +// +//***************************************************************************** +extern int32_t IntGetPriority(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Check whether an interrupt is enabled. +//! +//! This function checks whether an interrupt is enabled in the NVIC. +//! +//! \param intNum specifies the index in the vector table to check. +//! +//! \return Whether the interrupt is enabled or not +//! +//! \sa \ref IntDisable() +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern bool IntIsEnabled(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Enables an interrupt or system exception. +//! +//! This function enables the specified interrupt in the interrupt controller. +//! +//! \note If a fault condition occurs while the corresponding system exception +//! is disabled, the fault is treated as a Hard Fault. +//! +//! \param intNum specifies the index in the vector table to enable. +//! +//! \return None +//! +//! \sa \ref IntDisable() +// +//***************************************************************************** +extern void IntEnable(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Disables an interrupt or system exception. +//! +//! This function disables the specified interrupt in the interrupt controller. +//! +//! \param intNum specifies the index in the vector table to disable. +//! - See \ref IntEnable() for list of valid arguments. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntDisable(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Pends an interrupt. +//! +//! This function pends the specified interrupt in the interrupt controller. +//! This causes the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. +//! +//! This interrupt controller automatically clears the pending interrupt once the +//! interrupt handler is executed. +//! +//! \param intNum specifies the index in the vector table to pend. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntSetPend(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Checks if an interrupt is pending. +//! +//! This function checks the interrupt controller to see if an interrupt is pending. +//! +//! The interrupt must be enabled in order for the corresponding interrupt handler +//! to be executed, so an interrupt can be pending waiting to be enabled or waiting +//! for an interrupt of higher priority to be done executing. +//! +//! \note This function does not support reading pending status for system exceptions +//! (vector table indexes <16). +//! +//! \param intNum specifies the index in the vector table to check pending +//! status for. +//! - See \ref IntSetPend() for list of valid arguments (except system exceptions). +//! +//! \return Returns: +//! - \c true : Specified interrupt is pending. +//! - \c false : Specified interrupt is not pending. +// +//***************************************************************************** +extern bool IntGetPend(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Unpends an interrupt. +//! +//! This function unpends the specified interrupt in the interrupt controller. +//! This causes any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \note It is not possible to unpend the NMI because it takes effect +//! immediately when being pended. +//! +//! \param intNum specifies the index in the vector table to unpend. +//! - See \ref IntSetPend() for list of valid arguments (except NMI). +//! +//! \return None +// +//***************************************************************************** +extern void IntClearPend(uint32_t intNum); + +//***************************************************************************** +// +//! \brief Enables the CPU interrupt. +//! +//! Allows the CPU to respond to interrupts. +//! +//! \return Returns: +//! - \c true : Interrupts were disabled and are now enabled. +//! - \c false : Interrupts were already enabled when the function was called. +// +//***************************************************************************** +__STATIC_INLINE bool IntEnableMaster(void) +{ + uint32_t interruptsDisabled = __get_PRIMASK(); + // Enable CPU interrupts. + __enable_irq(); + return (interruptsDisabled); +} + +//***************************************************************************** +// +//! \brief Disables the CPU interrupts with configurable priority. +//! +//! Prevents the CPU from receiving interrupts except NMI and hard fault. This +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the interrupt from the interrupt controller to the CPU. +//! +//! \return Returns: +//! - \c true : Interrupts were already disabled when the function was called. +//! - \c false : Interrupts were enabled and are now disabled. +// +//***************************************************************************** +__STATIC_INLINE bool IntDisableMaster(void) +{ + uint32_t interruptsDisabled = __get_PRIMASK(); + // Disable CPU interrupts. + __disable_irq(); + return (interruptsDisabled); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __INTERRUPT_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.c new file mode 100644 index 00000000..60655ba7 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.c @@ -0,0 +1,37 @@ +/****************************************************************************** + * Filename: lpcmp.c + * + * Description: Driver for the LPCMP peripheral. + * + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "lpcmp.h" diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.h new file mode 100644 index 00000000..260f33eb --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lpcmp.h @@ -0,0 +1,383 @@ +/****************************************************************************** + * Filename: lpcmp.h + * + * Description: Defines and prototypes for the LPCMP peripheral. + * + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __LPCMP_H__ +#define __LPCMP_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup lpcmp_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_sys0.h" + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +//***************************************************************************** +// +// Defines that can be passed to LPCMPSetDividerPath() to select the voltage +// divider path. +// +//***************************************************************************** +#define LPCMP_DIVISION_PATH_N SYS0_LPCMPCFG_DIVPATH_NSIDE //!< Apply voltage divider to the negative input +#define LPCMP_DIVISION_PATH_P SYS0_LPCMPCFG_DIVPATH_PSIDE //!< Apply voltage divider to the positive input + +//***************************************************************************** +// +// Defines that can be passed to LPCMPSetDividerRatio() to select which ratio +// should be used by the voltage divider. +// +//***************************************************************************** +#define LPCMP_DIVISION_FACTOR_1_1 SYS0_LPCMPCFG_DIV_VAL0 //!< Apply a 1/1 voltage division ratio +#define LPCMP_DIVISION_FACTOR_3_4 SYS0_LPCMPCFG_DIV_VAL1 //!< Apply a 3/4 voltage division ratio +#define LPCMP_DIVISION_FACTOR_1_2 SYS0_LPCMPCFG_DIV_VAL2 //!< Apply a 1/2 voltage division ratio +#define LPCMP_DIVISION_FACTOR_1_3 SYS0_LPCMPCFG_DIV_VAL3 //!< Apply a 1/3 voltage division ratio +#define LPCMP_DIVISION_FACTOR_1_4 SYS0_LPCMPCFG_DIV_VAL4 //!< Apply a 1/4 voltage division ratio + +//***************************************************************************** +// +// Defines that can be passed to LPCMPSetPolarity() to select which edge type +// should generate a LPCMP event. +// +//***************************************************************************** +#define LPCMP_POLARITY_FALL SYS0_LPCMPCFG_EDGCFG_FALL //!< Select falling edge for event generation +#define LPCMP_POLARITY_RISE SYS0_LPCMPCFG_EDGCFG_RISE //!< Select rising edge for event generation + +//***************************************************************************** +// +// Defines that can be passed to LPCMPNegativeInputSelect() to select which +// signal should be muxed to LPCMP negative input. +// +//***************************************************************************** +#define LPCMP_NEG_INPUT_VDDD SYS0_LPCMPCFG_NSEL_VDDD //!< Select VDDD as negative input +#define LPCMP_NEG_INPUT_VDDA SYS0_LPCMPCFG_NSEL_VDDA //!< Select VDDA as negative input +#define LPCMP_NEG_INPUT_A2 SYS0_LPCMPCFG_NSEL_VA_PAD_A2 //!< Select PAD_A2 as negative input +#define LPCMP_NEG_INPUT_A3 SYS0_LPCMPCFG_NSEL_VA_PAD_A3 //!< Select PAD_A3 as negative input +#define LPCMP_NEG_INPUT_OPEN SYS0_LPCMPCFG_NSEL_OPEN //!< Leave negative input floating + +//***************************************************************************** +// +// Defines that can be passed to LPCMPPositiveInputSelect() to select which +// signal should be muxed to LPCMP positive input. +// +//***************************************************************************** +#define LPCMP_POS_INPUT_A1 SYS0_LPCMPCFG_PSEL_VA_PAD_A1 //!< Select PAD_A1 as positive input +#define LPCMP_POS_INPUT_A2 SYS0_LPCMPCFG_PSEL_VA_PAD_A2 //!< Select PAD_A2 as positive input +#define LPCMP_POS_INPUT_A3 SYS0_LPCMPCFG_PSEL_VA_PAD_A3 //!< Select PAD_A3 as positive input +#define LPCMP_POS_INPUT_VDDA SYS0_LPCMPCFG_PSEL_VDDA //!< Selects VDDA as positive input +#define LPCMP_POS_INPUT_OPEN SYS0_LPCMPCFG_PSEL_OPEN //!< Leave negative positive floating + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables LPCMP. +//! +//! This function enables LPCMP and it must be called after having configured +//! the peripheral's inputs, voltage divider and event generation logic. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPEnable(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_EN; +} + +//***************************************************************************** +// +//! \brief Disables LPCMP. +//! +//! This function disables LPCMP after it has been enabled using \ref LPCMPEnable(). +// +//***************************************************************************** +__STATIC_INLINE void LPCMPDisable(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EN; +} + +//***************************************************************************** +// +//! \brief Enables LPCMP event generation. +//! +//! This function enables LPCMP event generation to the event fabric. +//! Polarity must be selected using \ref LPCMPSetPolarity() to determine on which +//! edge type of LPCMP output an event should be generated. LPCMP doesn't have a +//! dedicated interrupt line, therefore a configurable interrupt line must be +//! configured to propagate LPCMP events. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPEnableEvent(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_EVTEN; +} + +//***************************************************************************** +// +//! \brief Disables LPCMP event generation. +//! +//! This function disables LPCMP event generation to the event fabric. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPDisableEvent(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EVTEN; +} + +//***************************************************************************** +// +//! \brief Clear LPCMP event flag. +//! +//! This function clears LPCMP event flag and should be called from the ISR +//! registered to service LPCMP interrupts. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPClearEvent(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EVTIFG; +} + +//***************************************************************************** +// +//! \brief Enables LPCMP as wakeup source from standby. +//! +//! This function enables LPCMP as one of the sources that can wakeup the device +//! from standby. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPEnableWakeup(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_WUENSB; +} + +//***************************************************************************** +// +//! \brief Disables LPCMP as wakeup source from standby. +//! +//! This function disables LPCMP as one of the sources that can wakeup the device +//! from standby. +// +//***************************************************************************** +__STATIC_INLINE void LPCMPDisableWakeup(void) +{ + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_WUENSB; +} + +//***************************************************************************** +// +//! \brief Selects the negative input of LPCMP. +//! +//! This function selects one of the available sources as the negative input of +//! LPCMP. This function must be called before enabling LPCMP using \ref LPCMPEnable(). +//! +//! \param input +//! LPCMP negative input source: +//! - \ref LPCMP_NEG_INPUT_VDDD +//! - \ref LPCMP_NEG_INPUT_VDDA +//! - \ref LPCMP_NEG_INPUT_A2 +//! - \ref LPCMP_NEG_INPUT_A3 +//! - \ref LPCMP_NEG_INPUT_OPEN +// +//***************************************************************************** +__STATIC_INLINE void LPCMPSelectNegativeInput(uint32_t input) +{ + uint32_t lpcmpcfg; + + lpcmpcfg = HWREG(SYS0_BASE + SYS0_O_LPCMPCFG); + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) = (lpcmpcfg & ~SYS0_LPCMPCFG_NSEL_M) | (input & SYS0_LPCMPCFG_NSEL_M); +} + +//***************************************************************************** +// +//! \brief Verifies if the raw output of LPCMP is high. +//! +//! This function returns a boolean value indicating whether the raw output of +//! LPCMP is high or low +//! +//! \return status of LPCMP raw output: +//! - \c true : LPCMP raw output is high. +//! - \c false : LPCMP raw output is low. +// +//***************************************************************************** +__STATIC_INLINE bool LPCMPIsOutputHigh(void) +{ + if (HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) & SYS0_LPCMPCFG_COUT_HIGH) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +//! \brief Selects the positive input of LPCMP. +//! +//! This function selects one of the available sources as the positive input of +//! LPCMP. This function must be called before enabling LPCMP using \ref LPCMPEnable(). +//! +//! \param input +//! LPCMP positive input source: +//! - \ref LPCMP_POS_INPUT_A1 +//! - \ref LPCMP_POS_INPUT_A2 +//! - \ref LPCMP_POS_INPUT_A3 +//! - \ref LPCMP_POS_INPUT_VDDA +//! - \ref LPCMP_POS_INPUT_OPEN +// +//***************************************************************************** +__STATIC_INLINE void LPCMPSelectPositiveInput(uint32_t input) +{ + uint32_t lpcmpcfg; + + lpcmpcfg = HWREG(SYS0_BASE + SYS0_O_LPCMPCFG); + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) = (lpcmpcfg & ~SYS0_LPCMPCFG_PSEL_M) | (input & SYS0_LPCMPCFG_PSEL_M); +} + +//***************************************************************************** +// +//! \brief Selects the edge polarity of LPCMP output on which an event +//! is triggered. +//! +//! This function selects whether a rising or falling edge of LPCMP output +//! will trigger an event propagated through the event fabric. +//! +//! \param polarity +//! Edge polarity of LPCMP output on which the event is triggered: +//! - \ref LPCMP_POLARITY_RISE +//! - \ref LPCMP_POLARITY_FALL +// +//***************************************************************************** +__STATIC_INLINE void LPCMPSetPolarity(uint32_t polarity) +{ + if (polarity == LPCMP_POLARITY_FALL) + { + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_EDGCFG; + } + else + { + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_EDGCFG; + } +} + +//***************************************************************************** +// +//! \brief Selects the ratio used by LPCMP voltage divider +//! +//! This function selects the ratio used by LPCMP voltage divider to divide one +//! of the two comparator inputs. Use \ref LPCMPSetDividerPath() to select if +//! the ratio should be applied to the negative or positive input of LPCMP. +//! +//! \param divider +//! Divider ratio used by LPCMP voltage divider: +//! - \ref LPCMP_DIVISION_FACTOR_1_1 +//! - \ref LPCMP_DIVISION_FACTOR_3_4 +//! - \ref LPCMP_DIVISION_FACTOR_1_2 +//! - \ref LPCMP_DIVISION_FACTOR_1_3 +//! - \ref LPCMP_DIVISION_FACTOR_1_4 +// +//***************************************************************************** +__STATIC_INLINE void LPCMPSetDividerRatio(uint32_t divider) +{ + uint32_t lpcmpcfg; + + lpcmpcfg = HWREG(SYS0_BASE + SYS0_O_LPCMPCFG); + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) = (lpcmpcfg & ~SYS0_LPCMPCFG_DIV_M) | (divider & SYS0_LPCMPCFG_DIV_M); +} + +//***************************************************************************** +// +//! \brief Selects the input path on which the LPCMP voltage divider is applied +//! +//! This function selects the input path on which the LPCMP voltage divider is +//! applied. Use \ref LPCMPSetDividerRatio() to set the division ratio applied +//! by the LPCMP voltage divider on the selected path. +//! +//! \param path +//! Input path the LPCMP voltage divider is applied to: +//! - \ref LPCMP_DIVISION_PATH_N +//! - \ref LPCMP_DIVISION_PATH_P +// +//***************************************************************************** +__STATIC_INLINE void LPCMPSetDividerPath(uint32_t path) +{ + if (path == LPCMP_DIVISION_PATH_P) + { + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) |= SYS0_LPCMPCFG_DIVPATH; + } + else + { + HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) &= ~SYS0_LPCMPCFG_DIVPATH; + } +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __LPCMP_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c new file mode 100644 index 00000000..22ddc46c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c @@ -0,0 +1,118 @@ +/****************************************************************************** + * Filename: lrfd.c + * + * Description: Driver for LRFD + * + * Copyright (c) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "lrfd.h" + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_clkctl.h" +#include "../inc/hw_lrfddbell.h" + +#include "../driverlib/interrupt.h" + +static uint16_t lrfdClockDependencySets[LRFD_NUM_CLK_DEP]; +static bool lrfdClocked = false; + +//***************************************************************************** +// +// Set clock dependency on a set of modules in LRFD. +// +//***************************************************************************** +void LRFDSetClockDependency(uint16_t mask, uint8_t dependencySetId) +{ + if (dependencySetId < LRFD_NUM_CLK_DEP) + { + lrfdClockDependencySets[dependencySetId] |= mask; + } + LRFDApplyClockDependencies(); +} + +//***************************************************************************** +// +// Release clock dependency on a set of modules in LRFD. +// +//***************************************************************************** +void LRFDReleaseClockDependency(uint16_t mask, uint8_t dependencySetId) +{ + if (dependencySetId < LRFD_NUM_CLK_DEP) + { + lrfdClockDependencySets[dependencySetId] &= ~mask; + } + LRFDApplyClockDependencies(); +} + +//***************************************************************************** +// +// Apply the currently set clock dependencies. +// +//***************************************************************************** +void LRFDApplyClockDependencies(void) +{ + uint16_t clkctl = 0; + for (int i = 0; i < LRFD_NUM_CLK_DEP; i++) + { + clkctl |= lrfdClockDependencySets[i]; + } + + if (lrfdClocked) + { + /* BRIDGE bit should not be needed, as hardware will automatically enable the clock when + needed. The bit should be always be 0 in the HW, and is thus cleared. */ + HWREG(LRFDDBELL_BASE + LRFDDBELL_O_CLKCTL) = clkctl & ~LRFDDBELL_CLKCTL_BRIDGE_M; + + if (clkctl == 0) + { + /* Disable LRFD module clock */ + HWREG( CLKCTL_BASE + CLKCTL_O_CLKENCLR0 ) = CLKCTL_CLKENCLR0_LRFD; + lrfdClocked = false; + } + } + else + { + if (clkctl != 0) + { + /* Enable LRFD module clock */ + HWREG( CLKCTL_BASE + CLKCTL_O_CLKENSET0 ) = CLKCTL_CLKENSET0_LRFD; + lrfdClocked = true; + + /* BRIDGE bit should not be needed, as hardware will automatically enable the clock when + needed. The bit should be always be 0 in the HW, and is thus cleared. The bit can be + used in the input to indicate the need for the LRFD module clock to be enabled, but no + internal LRFD clocks. */ + HWREG(LRFDDBELL_BASE + LRFDDBELL_O_CLKCTL) = clkctl & ~LRFDDBELL_CLKCTL_BRIDGE_M; + } + } +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.h new file mode 100644 index 00000000..cd8ed857 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.h @@ -0,0 +1,154 @@ +/****************************************************************************** + * Filename: lrfd.h + * + * Description: Defines and prototypes for LRFD. + * + * Copyright (c) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __LRFD_H__ +#define __LRFD_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup lrfd_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "../inc/hw_lrfddbell.h" + +// Number of LRFD clock dependency sets +#define LRFD_NUM_CLK_DEP 2 +//! LRFD Clock dependency set to be used by the Power driver +#define LRFD_CLK_DEP_POWER 0 +//! LRFD Clock dependency set to be used by the RCL +#define LRFD_CLK_DEP_RCL 1 + +//***************************************************************************** +// +//! \brief Set clock dependency on a set of modules in LRFD. +//! +//! \warning This API uses internal state, and is not thread safe. +//! +//! This API supports multiple clock dependency sets. For any given LRFD module, +//! it will be clocked if any of the dependency sets has a dependency for that +//! LRFD module. +//! If any dependency set has a dependency on at least one LRFD module, the LRFD +//! module itself will be clocked, otherwise it will not be clocked. +//! +//! \param mask bitmask defining the set of LRFD modules to set clock dependency on. +//! - \ref LRFDDBELL_O_CLKCTL +//! \param dependencySetId ID for the clock dependency set to use. +//! - \ref LRFD_CLK_DEP_POWER +//! - \ref LRFD_CLK_DEP_RCL +//! +//! \sa LRFDReleaseClockDependency() +//! +//! \return None +// +//***************************************************************************** +extern void LRFDSetClockDependency(uint16_t mask, uint8_t dependencySetId); + +//***************************************************************************** +// +//! \brief Release clock dependency on a set of modules in LRFD. +//! +//! \warning This API uses internal state, and is not thread safe. +//! +//! This API supports multiple clock dependency sets. +//! See description of \ref LRFDSetClockDependency() +//! +//! \param mask bitmask defining the set of LRFD modules to release clock dependency from. +//! - \ref LRFDDBELL_O_CLKCTL +//! \param dependencySetId ID for the clock dependency set to use. +//! - \ref LRFD_CLK_DEP_POWER +//! - \ref LRFD_CLK_DEP_RCL +//! +//! \sa LRFDSetClockDependency() +//! +//! \return None +// +//***************************************************************************** +extern void LRFDReleaseClockDependency(uint16_t mask, uint8_t dependencySetId); + +//***************************************************************************** +// +//! \brief Apply the currently set clock dependencies. +//! +//! \warning This API uses internal state, and is not thread safe. +//! +//! \note The dependencies automatically being applied when setting and +//! releasing dependencies using \ref LRFDSetClockDependency() and +//! \ref LRFDReleaseClockDependency(). This API is mainly intended for when +//! the enabled clocks gets out of sync with the current dependencies. +//! For example, after the device wakes up from standby. +//! +//! This will update the LRFD clock control based on the currently set clock +//! dependencies. +//! If there is a clock dependency on any module in LRFD, the LRFD module itself +//! will be clocked, otherwise it will not be clocked. +//! +//! \return None +// +//***************************************************************************** +extern void LRFDApplyClockDependencies(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __LRFD_H__ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h new file mode 100644 index 00000000..dc614449 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h @@ -0,0 +1,219 @@ +/****************************************************************************** + * Filename: pmctl.h + * + * Description: Defines and prototypes for the PMCTL module. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __PMCTL_H__ +#define __PMCTL_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup pmctl_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_pmctl.h" + +#include "../cmsis/cc23x0r5.h" +#include "../cmsis/core/core_cm0plus.h" + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +//! \name PMCTLGetResetReason() return values +//@{ +//***************************************************************************** +//! Device woke up from shutdown due to an IO event +#define PMCTL_RESET_SHUTDOWN_IO (PMCTL_RSTSTA_SDDET | PMCTL_RSTSTA_IOWUSD) +//! Device woke up from shutdown due to an SWD event +#define PMCTL_RESET_SHUTDOWN_SWD PMCTL_RSTSTA_SDDET +//! Device reset because of a watchdog timeout. +#define PMCTL_RESET_WATCHDOG (PMCTL_RSTSTA_SYSSRC_WDTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset trggered by software writing to RSTCTL.SYSRST +#define PMCTL_RESET_SYSTEM (PMCTL_RSTSTA_SYSSRC_SYSRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by CPU reset event +#define PMCTL_RESET_CPU (PMCTL_RSTSTA_SYSSRC_CPURSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by CPU lockup event +#define PMCTL_RESET_LOCKUP (PMCTL_RSTSTA_SYSSRC_LOCKUPEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device woke up due to Serial Wire Debug event +#define PMCTL_RESET_SWD (PMCTL_RSTSTA_SYSSRC_SWDRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset due to LFXT clock loss +#define PMCTL_RESET_LFXT (PMCTL_RSTSTA_SYSSRC_LFLOSSEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device woke up from thermal shutdown after temperature drop +#define PMCTL_RESET_TSD (PMCTL_RSTSTA_TSDEV | PMCTL_RSTSTA_RESETSRC_PINRESET) +//! Device reset due to VDDR brownout event +#define PMCTL_RESET_VDDR PMCTL_RSTSTA_RESETSRC_VDDRLOSS +//! Device reset due to VDDS brownout event +#define PMCTL_RESET_VDDS PMCTL_RSTSTA_RESETSRC_VDDSLOSS +//! Device reset due to pin reset +#define PMCTL_RESET_PIN PMCTL_RSTSTA_RESETSRC_PINRESET +//! Device booted due to power on reset +#define PMCTL_RESET_POR PMCTL_RSTSTA_RESETSRC_PWRON +//@} + +//***************************************************************************** +//! \name PMCTLSetVoltageRegulator() inputs and PMCTLGetVoltageRegulator() return values +//@{ +//***************************************************************************** +//! DCDC voltage regulator +#define PMCTL_VOLTAGE_REGULATOR_DCDC PMCTL_VDDRCTL_SELECT_DCDC +//! GLDO voltage regulator +#define PMCTL_VOLTAGE_REGULATOR_GLDO PMCTL_VDDRCTL_SELECT_GLDO +//@} + +//***************************************************************************** +// +//! \brief Get the reason for the system reset. +//! +//! This function will return the reason the device reset. +//! +//! \return Returns the reset source. +//! - \ref PMCTL_RESET_SHUTDOWN_IO +//! - \ref PMCTL_RESET_SHUTDOWN_SWD +//! - \ref PMCTL_RESET_WATCHDOG +//! - \ref PMCTL_RESET_CPU +//! - \ref PMCTL_RESET_LOCKUP +//! - \ref PMCTL_RESET_TSD +//! - \ref PMCTL_RESET_SWD +//! - \ref PMCTL_RESET_LFXT +//! - \ref PMCTL_RESET_VDDR +//! - \ref PMCTL_RESET_VDDS +//! - \ref PMCTL_RESET_PIN +//! - \ref PMCTL_RESET_POR +// +//***************************************************************************** +__STATIC_INLINE uint32_t PMCTLGetResetReason(void) +{ + return HWREG(PMCTL_BASE + PMCTL_O_RSTSTA); +} + +//***************************************************************************** +// +//! \brief Issue a system reset. +//! +//! This function issues a system reset. This will cause the device to reboot. +//! After rebooting, #PMCTLGetResetReason() will return #PMCTL_RESET_SYSTEM. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void PMCTLResetSystem(void) +{ + // Disable interrupts + __disable_irq(); + + // Write reset register + HWREG(PMCTL_BASE + PMCTL_O_RSTCTL) |= PMCTL_RSTCTL_SYSRST_SET; + + // Should never return from this function + while (1) {} +} + +//***************************************************************************** +// +//! \brief Set the VDDR regulator +//! +//! This function sets the VDDR regulator to use in active, idle, and standby +//! modes. +//! +//! \param regulator The voltage regulator to switch to. +//! - \ref PMCTL_VOLTAGE_REGULATOR_DCDC +//! - \ref PMCTL_VOLTAGE_REGULATOR_GLDO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void PMCTLSetVoltageRegulator(uint32_t regulator) +{ + // Write to VDDR regulator register while preserving other configuration + // fields + uint32_t tmp = HWREG(PMCTL_BASE + PMCTL_O_VDDRCTL) & ~PMCTL_VDDRCTL_SELECT_M; + HWREG(PMCTL_BASE + PMCTL_O_VDDRCTL) = tmp | regulator; +} + +//***************************************************************************** +// +//! \brief Get the current VDDR regulator +//! +//! This function gets the VDDR regulator currently in use. +//! +//! \return Current voltage regulator +//! - PMCTL_VOLTAGE_REGULATOR_DCDC +//! - PMCTL_VOLTAGE_REGULATOR_GLDO +// +//***************************************************************************** +__STATIC_INLINE uint32_t PMCTLGetVoltageRegulator(void) +{ + return (HWREG(PMCTL_BASE + PMCTL_O_VDDRCTL) & PMCTL_VDDRCTL_SELECT_M); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __PMCTL_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.c new file mode 100644 index 00000000..77fd8151 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.c @@ -0,0 +1,70 @@ +/****************************************************************************** + * Filename: setup.c + * + * Description: Setup file for CC23x0R5 devices. + * + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +#include "../inc/hw_types.h" +#include "../inc/hw_ckmd.h" +#include "../inc/hw_fcfg.h" +#include "setup.h" + +void SetupTrimDevice(void) +{ + uint8_t trimState; + + // Read out the layout revision number + if (fcfg->appTrims.revision >= 4) + { + // Hard coded address for fcfg->appTrimsExt.cc23x0r5.ateFtRev.trimState + // to be independent of fcfg layout revision + trimState = HWREGB(0x4E00032F); + } + else + { + // Hard coded address for fcfg->appTrimsExt.cc23x0r5.ateFtRev.trimState + // to be independent of fcfg layout revision + trimState = HWREGB(0x4E0003AF); + } + + if (trimState > 0xFC) + { + // Override HFXT trims on state D and earlier devices. Without this + // override, HFXT startup will alternate between 20us and 1.5ms. + HWREG(CKMD_BASE + CKMD_O_HFXTINIT) = (0x23 << CKMD_HFXTINIT_Q1CAP_S) | (0x23 << CKMD_HFXTINIT_Q2CAP_S) | + (0x8 << CKMD_HFXTINIT_IREF_S) | (0x12 << CKMD_HFXTINIT_AMPTHR_S) | + (0x7F << CKMD_HFXTINIT_IDAC_S); + + HWREG(CKMD_BASE + CKMD_O_HFXTTARG) = (0x23 << CKMD_HFXTTARG_Q1CAP_S) | (0x23 << CKMD_HFXTTARG_Q2CAP_S) | + (0x3 << CKMD_HFXTTARG_IREF_S) | (0x12 << CKMD_HFXTTARG_AMPTHR_S) | + (0x7F << CKMD_HFXTTARG_IDAC_S) | (0x1 << CKMD_HFXTTARG_AMPHYST_S); + } +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.h new file mode 100644 index 00000000..d2794239 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup.h @@ -0,0 +1,106 @@ +/****************************************************************************** + * Filename: setup.h + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __SETUP_H__ +#define __SETUP_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. +//! +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. +//! +//! \return None +// +//***************************************************************************** +extern void SetupTrimDevice(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __SETUP_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup_doc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup_doc.h new file mode 100644 index 00000000..a30a0c10 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/setup_doc.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * Filename: setup_doc.h + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +//! \addtogroup setup_api +//! @{ +//! +//! This module contains functions for device setup which is not done in boot code. +//! +//! @} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha256sw.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha256sw.h new file mode 100644 index 00000000..f711a88d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha256sw.h @@ -0,0 +1,362 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +#ifndef SHA256SW_H_ +#define SHA256SW_H_ + +/** ============================================================================ + * @file sha256sw.h + */ +/*! + * @addtogroup sw_libraries_group + * @{ + * + * @addtogroup sha2sw_api + * @{ + * @brief SHA2 256/224 SW APIs. + * + * + * @anchor ti_SHA256_SW_LIBRARY_Overview + * # Overview # + * Provides top-level general purpose SHA2 256/224 APIs. SHA2 algorithm is + * implemented in SW with no HW acceleration. The implementation is highly + * optimized for speed and code size. These functions reside in ROM, and are + * exposed through HAPI, and also through the function prototypes and macros below. + * + * + * Availability of SHA2 224 depends on build configuration. + * See file @ref sha2sw_config.h. + * + * ## Limitations ## + * @li A maximum of 512MiB may be hashed by this implementation. (SHA2 + * standard supports 2 million Terabytes for 224/256) + * @li Input data may be 8-bit aligned. However, output digest must be + * 32-bit aligned. + * @li Intermediate values, input data, and final digest value may be + * left behind on the stack. + * + *
+ * @anchor ti_SHA256_SW_LIBRARY_Usage + * # Usage # + * + * There are two general ways to execute a SHA2 operation: + * + * - one-step, using #SHA256SWHashData() + * - multi-step, using #SHA256SWStart(), #SHA256SWAddData(), and + * #SHA256SWFinalize() + * + * The multi-step approach allows the hash to be extended by adding + * more data. + * + * All input data is to be in little-endian (LE) format and the resulting + * hash values produced by these APIs are in LE format. + * + * @anchor ti_SHA256_SW_LIBRARY_Synopsis + * ## Synopsis + * + * The following is a quick overview of one-step hashing. + * + * @anchor ti_SHA256_SW_LIBRARY_Synopsis_Code + * @code + * // Import SHA2 SW Driver definitions + * #include + * + * // Create an object and handle + * SHA256SW_Object sha256SWObject; + * SHA256SW_Handle sha256SWHandle = &sha256SWObject; + * + * // Allocate space for digest output + * uint32_t actualDigest[8]; + * + * result = SHA256SWHashData(sha256SWHandle, SHA2SW_HASH_TYPE_256, + * message, strlen(message), actualDigest); + * @endcode + * + *
+ * @anchor ti_SHA256_SW_LIBRARY_Examples + * # Examples + * @li @ref ti_SHA256_SW_LIBRARY_Example_hashData "Hashing data in one call" + * @li @ref ti_SHA256_SW_LIBRARY_Example_addData "Hashing data in multiple calls" + * + * @anchor ti_SHA256_SW_LIBRARY_Example_hashData + * ## Hashing data in one call + * + * @code + * SHA256SW_Object sha256SWObject; + * SHA256SW_Handle sha256SWHandle = &sha256SWObject; + * int_fast16_t sha2SWresult; + * uint32_t finalDigest[8]; + * int notsame; + * + * char message[] = + * "abcdefghijklmnabcdefghijklmnabcdefghijklmnabcdefghijklmn1234"; + * uint8_t expectedDigest[] = + * { 0x60, 0x06, 0x00, 0x24, 0x13, 0xe4, 0x27, 0x0d, + * 0x4d, 0xdb, 0x66, 0x93, 0x42, 0xa9, 0xe2, 0xdb, + * 0x66, 0x5e, 0xc8, 0x70, 0x73, 0xc4, 0x2e, 0xb5, + * 0x44, 0x99, 0x62, 0xf1, 0x2a, 0xb2, 0xe8, 0x60 }; + * + * sha2SWresult = SHA256SWHashData(sha256SWHandle, SHA2SW_HASH_TYPE_256, + * message, strlen(message), finalDigest); + * + * if (sha2SWresult != SHA2SW_STATUS_SUCCESS) + * { + * while(1); + * } + * + * // NOTE: If expectedDigest is a secret value, a timing constant comparison + * // routine shall be used instead of memcmp. + * notsame = memcmp(finalDigest, expectedDigest, sizeof(finalDigest)); + * + * if (notsame) + * { + * while(1); + * } + * @endcode + * + * + * @anchor ti_SHA256_SW_LIBRARY_Example_addData + * ## Hashing data in multiple calls + * + * @code + * SHA256SW_Object sha256SWObject; + * SHA256SW_Handle sha256SWHandle = &sha256SWObject; + * int_fast16_t sha2SWresult; + * uint32_t finalDigest[8]; + * int notsame; + * + * char message[] = + * "abcdefghijklmnabcdefghijklmnabcdefghijklmnabcdefghijklmn1234"; + * uint8_t expectedDigest[] = + * { 0x60, 0x06, 0x00, 0x24, 0x13, 0xe4, 0x27, 0x0d, + * 0x4d, 0xdb, 0x66, 0x93, 0x42, 0xa9, 0xe2, 0xdb, + * 0x66, 0x5e, 0xc8, 0x70, 0x73, 0xc4, 0x2e, 0xb5, + * 0x44, 0x99, 0x62, 0xf1, 0x2a, 0xb2, 0xe8, 0x60, }; + * + * + * sha2SWresult = SHA256SWStart(sha256SWHandle, SHA2SW_HASH_TYPE_256); + * + * if (sha2SWresult == SHA2SW_STATUS_SUCCESS) { + * sha2SWresult = SHA256SWAddData(sha256SWHandle, message, 20); + * } + * + * if (sha2SWresult == SHA2SW_STATUS_SUCCESS) { + * sha2SWresult = SHA256SWAddData(sha256SWHandle, &message[20], strlen(message) - 20); + * } + * + * if (sha2SWresult == SHA2SW_STATUS_SUCCESS) { + * sha2SWresult = SHA256SWFinalize(sha256SWHandle, finalDigest); + * } + * + * if (sha2SWresult != SHA2SW_STATUS_SUCCESS) + * { + * while(1); + * } + * + * // NOTE: If expectedDigest is a secret value, a timing constant comparison + * // routine shall be used instead of memcmp. + * notsame = memcmp(finalDigest, expectedDigest, sizeof(finalDigest)); + * + * if (notsame) + * { + * while(1); + * } + * @endcode + * + * + *
+ * @anchor ti_SHA256_SW_LIBRARY_configuration + * # Configuration + * + * See file @ref sha2sw_config.h for full configuration information. + * + * If #SHA2SW_VALIDATE_INPUTS is not defined then: + * @li the caller is responsible for ensuring all inputs are valid, and + * @li the module's functions will only return #SHA2SW_STATUS_SUCCESS + * + */ + +#include +#include + +#include "sha2sw_common.h" +#include "sha2sw_config.h" + +/*! + * @brief SHA256SW Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t bitsProcessed; // Only 2^32 bits (512 MiBytes) are supported + int8_t offsetWb; // Byte offset into Ws, used to load message + uint8_t reserved1; + uint8_t reserved2; + uint8_t reserved3; + uint32_t digest32[8]; // Holds intermediate/final digest + uint32_t Ws32[16]; // Message schedule, indexed by (s & 0xF), + // where s = 63 - t, and t is NIST 180-4's + // message schedule index +} SHA256SW_Object; + +/*! + * @brief A handle to a SHA256SW_Object. + */ +typedef SHA256SW_Object *SHA256SW_Handle; + +/* Include this file after the type definitions above, to break cyclic dependency between hapi.h and sha256sw.h */ +#include "hapi.h" + +/*! + * @brief Performs a complete hash operation, producing a final digest + * for the data. + * + * This function wraps #SHA256SWStart(), #SHA256SWAddData(), and + * #SHA256SWFinalize(). + * + * There is no need to call #SHA256SWStart() prior to calling this function. + * + * The total length of data that can be hashed by this implementation + * is 512MiB (0x20000000 bytes.) + * + * @param[in] handle A #SHA256SW_Handle. + * + * @param[in] hashType The type of hash (256 or 224) to perform. + * + * @param[in] data data (message) to hash. May point to zero. + * + * @param[in] length the number of bytes (pointed to by @c data parameter) + * to add to the hash. + * + * @param[out] digest Output location for the final digest. Must be + * able to hold 32 bytes of output and be 32-bit aligned. + * + * @retval #SHA2SW_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2SW_STATUS_ERROR The hash operation failed. + * @retval #SHA2SW_STATUS_UNSUPPORTED Requested Hash Type is unsupported. + * @retval #SHA2SW_STATUS_LENGTH_TOO_LARGE The requested length of data to hash + * is more than the implementation + * supports. + * @retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + */ +extern int_fast16_t SHA256SWHashData(SHA256SW_Handle handle, + SHA2SW_HashType hashType, + const void *data, + size_t length, + uint32_t digest[8]); + +#define SHA256SWHashData HAPI_TABLE_POINTER->sha256SwHashData + +/*! + * @brief Initialize a SHA256SW_Handle, preparing for hashing data. + * + * @param[in] handle A #SHA256SW_Handle. + * + * @param[in] hashType The type of hash (256 or 224) to perform. + * + * @retval #SHA2SW_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2SW_STATUS_UNSUPPORTED Requested Hash Type is unsupported. + * @retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * @sa #SHA256SWAddData() + * @sa #SHA256SWFinalize() + */ +extern int_fast16_t SHA256SWStart(SHA256SW_Handle handle, SHA2SW_HashType hashType); + +#define SHA256SWStart HAPI_TABLE_POINTER->sha256SwStart + +/*! + * @brief Add data to a SHA256/224 operation. + * + * Adds data to a hash operation. The @c handle must have been + * initialized by a call to SHA256SWStart first. + * + * The total length of data that can be hashed by this implementation + * is 512MiB (0x20000000 bytes.) + * + * After passing in all data to be hashed, call #SHA256SWFinalize() + * to obtain the final digest. + * + * @pre handle was previously passed to #SHA256SWStart(). + * + * @param[in] handle A #SHA256SW_Handle. + * + * @param[in] data data (message) to add to the hash. May point to zero. + * + * @param[in] length the number of bytes (pointed to by @c data parameter) + * to add to the hash. + * + * @retval #SHA2SW_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2SW_STATUS_LENGTH_TOO_LARGE The requested length of data to hash + * is more than the implementation + * supports. + * @retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * @sa #SHA256SWStart() + * @sa #SHA256SWFinalize() + */ +extern int_fast16_t SHA256SWAddData(SHA256SW_Handle handle, const void *data, size_t length); + +#define SHA256SWAddData HAPI_TABLE_POINTER->sha256SwAddData + +/*! + * @brief Finalize a SHA256/224 operation, creating the final digest. + * + * After calling this function, @c handle should not be used again + * until it has been reinitialized via a call to #SHA256SWStart(). + * + * @pre handle was previously passed to #SHA256SWStart() and data to + * be hashed was passed to #SHA256SWAddData() + * + * @param[in] handle A #SHA256SW_Handle. + * + * @param[out] digest Output location for the final digest. Must be + * able to hold 32 bytes of output and be 32-bit aligned. + * + * @retval #SHA2SW_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2SW_STATUS_NULL_INPUT One or more of the pointer inputs is + * NULL. + * + * @sa #SHA256SWStart() + * @sa #SHA256SWAddData() + */ +extern int_fast16_t SHA256SWFinalize(SHA256SW_Handle handle, uint32_t digest[8]); + +#define SHA256SWFinalize HAPI_TABLE_POINTER->sha256SwFinalize + +/*! @}*/ +/*! @}*/ + +#endif /* SHA256SW_H_ */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_common.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_common.h new file mode 100644 index 00000000..e22cbe78 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_common.h @@ -0,0 +1,139 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +#ifndef SHA2SW_COMMON_H_ +#define SHA2SW_COMMON_H_ + +/*! ============================================================================ + * @file sha2sw_common.h + * + * @brief Definitions common across all SHA2 SW modules. + * + * # Overview # + * Provides top-level general purpose SHA2 SW definitions such as + * error return codes and enumerations. + * + */ + +#include +#include + +#include "sha2sw_config.h" + +/*! + * @brief Enum for the hash types supported by the library. + */ +typedef enum +{ + SHA2SW_HASH_TYPE_256 = 0, +#if SHA2SW_SUPPORT_SHA2_224 == 1 + SHA2SW_HASH_TYPE_224 = 1, +#endif +#if SHA2SW_SUPPORT_SHA2_384 == 1 + SHA2SW_HASH_TYPE_384 = 2, +#endif + SHA2SW_HASH_TYPE_512 = 3 +} SHA2SW_HashType; + +/*! + * @brief Number of rounds used in the SHA2 224 and 256 algorithms. + */ +#define SHA2SW_224_OR_256_ROUNDS ((uint8_t)64u) + +/*! + * @brief Number of rounds used in the SHA2 384 and 512 algorithms. + */ +#define SHA2SW_384_OR_512_ROUNDS ((uint8_t)80u) + +/*! + * @brief Number of bytes in the block of the SHA2 224 and 256 algorithms. + */ +#define SHA2SW_224_OR_256_BLOCK_SIZE ((uint8_t)64u) + +/*! + * @brief Number of bytes in the block of the SHA2 384 and 512 algorithms. + */ +#define SHA2SW_384_OR_512_BLOCK_SIZE ((uint8_t)128u) + +/*! + * @brief The maximum number of bits this implementation + * supports in the input message/data. + */ +#define SHA2SW_MAX_MESSAGE_BIT_LENGTH ((uint32_t)0x20000000u) + +/*! + * @addtogroup sw_libraries_group + * @{ + * @addtogroup sha2sw_status_codes + * @{ + * @brief Status codes returned by the SHA2 SW module. + */ + +/*! + * @brief Successful status code. + * + * Functions return SHA2SW_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define SHA2SW_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return SHA2SW_STATUS_ERROR if the function was not executed + * successfully and no more specific error is applicable. + */ +#define SHA2SW_STATUS_ERROR ((int_fast16_t)-100) + +/*! + * @brief Requested operation is not supported. + * + * The library (as built) does not support a requested feature. + */ +#define SHA2SW_STATUS_UNSUPPORTED ((int_fast16_t)-102) + +/*! + * @brief Too many data bytes have been requested to be hashed. + * + * The library supports a maximum length of 512MiB to be hashed. + */ +#define SHA2SW_STATUS_LENGTH_TOO_LARGE ((int_fast16_t)-103) + +/*! + * @brief Input value was NULL. + * + * An input pointer was NULL. Operation not performed. + */ +#define SHA2SW_STATUS_NULL_INPUT ((int_fast16_t)-104) + +/*! @}*/ +/*! @}*/ + +#endif /* SHA2SW_COMMON_H_ */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_config.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_config.h new file mode 100644 index 00000000..63e4fbaa --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sha2sw_config.h @@ -0,0 +1,127 @@ +/****************************************************************************** + * Copyright (c) 2022-2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +#ifndef SHA2SW_CONFIG_H_ +#define SHA2SW_CONFIG_H_ + +/** ============================================================================ + * @file sha2sw_config.h + */ +/*! + * @addtogroup sw_libraries_group + * @{ + * @addtogroup sha2sw_config_options + * @{ + * @brief Build-time configuration options for the SHA2 SW module + */ +/*! + * @brief Include support for SHA2 224. + * + */ +#if !defined(SHA2SW_SUPPORT_SHA2_224) +// #define SHA2SW_SUPPORT_SHA2_224 (1) +#endif + +/*! + * @brief Include support for SHA2 384. + * + */ +#if !defined(SHA2SW_SUPPORT_SHA2_384) +// #define SHA2SW_SUPPORT_SHA2_384 (1) +#endif + +/*! + * @brief If defined, SHA2SW library will check inputs for invalid + * conditions. Otherwise, parameters will not be checked. + * + * If #SHA2SW_VALIDATE_INPUTS is not defined then: + * @li the caller is responsible for ensuring all inputs are valid, and + * @li the module's functions will only return #SHA2SW_STATUS_SUCCESS + * + * + * Not defining this value will reduce code size. + */ +#if !defined(SHA2SW_VALIDATE_INPUTS) + #define SHA2SW_VALIDATE_INPUTS (1) +#endif + +/*! + * @brief Use a faster implementation of the message schedule which is + * slightly larger in code size. + * + * Expected time savings of 2,600 cycles or more per input block. Code + * size cost for enabling may be as little as 8 bytes. + */ +#if !defined(SHA2SW_FAST_MESSAGE_SCHEDULE) + #define SHA2SW_FAST_MESSAGE_SCHEDULE (1) +#endif + +/*! + * @brief Use a faster implementation of the working variables a-h which is + * slightly larger in code size. + * + * Expected time savings of 750 cycles or more per input block. Code + * size cost for enabling may be as little as 24 bytes. + */ +#if !defined(SHA2SW_FAST_WORKING_VARS) + #define SHA2SW_FAST_WORKING_VARS (1) +#endif + +/*! + * @brief Use portions of the constants of the 512 algorithm to + * support the 256 and 224 algorithms. + * + * The initial hash values as well as the round constants (K) of + * 512/384 are extensions of the values used for 256/224. Thus, + * const data space can be saved by using the 512/384 constants + * for the 256/224 algorithm. However, the 256/224 algorithm must + * spend extra cycles to skip over unneeded constants. + * + * Expected savings of at least 288 bytes of const data at the cost + * of a few bytes of code space and small change in performance. + */ +#if !defined(SHA2SW_USE_512_CONST_FOR_256) +// #define SHA2SW_USE_512_CONST_FOR_256 (1) +#endif + +/*! + * @brief Use Arm(R) C Language Extensions + * + * Use ARM(R) CLE to directly access op codes which can improve + * code size and/or performance. + */ +#if !defined(SHA2SW_USE_ARMCLE) + #define SHA2SW_USE_ARMCLE (1) +#endif + +/*! @}*/ +/*! @}*/ + +#endif /* SHA2SW_CONFIG_H_ */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.c new file mode 100644 index 00000000..dcfa3662 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.c @@ -0,0 +1,227 @@ +/****************************************************************************** + * Filename: spi.c + * + * Description: Driver for the Serial Peripheral Interface (SPI). + * + * Copyright (c) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "spi.h" + +// DSAMPLE default value limits based bit rate +#define DSAMPLE_MED_BITRATE 4000000U +#define DSAMPLE_HIGH_BITRATE 8000000U + +// Maximum serial clock divider value +#define SCR_MAXIMUM 0x000003FFU + +//***************************************************************************** +// +// Configures the serial peripheral port +// +//***************************************************************************** +static void SPIConfig(uint32_t baseAddr, + uint32_t freq, + uint32_t format, + uint32_t mode, + uint32_t bitRate, + uint32_t dataSize, + uint32_t dsample) +{ + uint16_t scr; + uint32_t ratio; + + // Get existing settings + uint32_t reg = HWREG(baseAddr + SPI_O_CTL0); + // Create mask for settings to modify + uint32_t mask = (SPI_CTL0_DSS_M | SPI_CTL0_FRF_M | SPI_CTL0_SPO_M | SPI_CTL0_SPH_M); + + // Convert and mask data size to HW register format + dataSize = (SPI_CTL0_DSS_M & (dataSize - 1)); + + // Apply updated register + HWREG(baseAddr + SPI_O_CTL0) = (reg & ~mask) | format | dataSize; + + // Set controller/peripheral mode and MSB first for shift reg + HWREG(baseAddr + SPI_O_CTL1) = mode | SPI_CTL1_MSB_MSB; + + // Get existing settings + reg = HWREG(baseAddr + SPI_O_CLKCFG1); + + // Create a mask for settings to modify + mask = (SPI_CLKCFG1_DSAMPLE_M | SPI_CLKCFG1_SCR_M); + + // Calculate scr variable + ratio = freq / (2U * bitRate); + if ((ratio > 0U) && (ratio <= SCR_MAXIMUM)) + { + scr = (uint16_t)(ratio - 1U); + } + else + { + scr = 0U; + } + + // Set clock divider + HWREG(baseAddr + SPI_O_CLKCFG1) = (reg & ~mask) | dsample | scr; +} + +void SPIConfigSetExpClk(uint32_t base, + uint32_t spiClk, + uint32_t protocol, + uint32_t mode, + uint32_t bitRate, + uint32_t dataWidth) +{ + uint32_t dsample = 0U; + + ASSERT(SPIBaseValid(base)); + + if (bitRate >= DSAMPLE_MED_BITRATE) + { + dsample = 1U << SPI_CLKCFG1_DSAMPLE_S; + } + else if (bitRate >= DSAMPLE_HIGH_BITRATE) + { + dsample = 2U << SPI_CLKCFG1_DSAMPLE_S; + } + + SPIConfig(base, spiClk, protocol, mode, bitRate, dataWidth, dsample); +} + +//***************************************************************************** +// +// Puts a data element into the SPI transmit FIFO +// +//***************************************************************************** +int32_t SPIPutDataNonBlocking(uint32_t base, uint32_t data) +{ + ASSERT(SPIBaseValid(base)); + + // Check for space to write. + if (HWREG(base + SPI_O_STA) & SPI_STA_TNF_NOT_FULL) + { + // Write the data to the SPI TX FIFO. + HWREG(base + SPI_O_TXDATA) = data; + return (1); + } + else + { + return (0); + } +} + +//***************************************************************************** +// +// Puts a data element into the SPI transmit FIFO +// +//***************************************************************************** +void SPIPutData(uint32_t base, uint32_t data) +{ + ASSERT(SPIBaseValid(base)); + + // Check for space to write. + while (!(HWREG(base + SPI_O_STA) & SPI_STA_TNF_NOT_FULL)) {} + + // Write the data to the SPI TX FIFO. + HWREG(base + SPI_O_TXDATA) = data; +} + +//***************************************************************************** +// +// Gets a data element from the SPI receive FIFO +// +//***************************************************************************** +void SPIGetData(uint32_t base, uint32_t *data) +{ + ASSERT(SPIBaseValid(base)); + + // Wait until there is data to be read. + while (HWREG(base + SPI_O_STA) & SPI_STA_RFE_EMPTY) {} + + // Read data from SPI RX FIFO. + *data = HWREG(base + SPI_O_RXDATA); +} + +//***************************************************************************** +// +// Gets a data element from the SPI receive FIFO +// +//***************************************************************************** +int32_t SPIGetDataNonBlocking(uint32_t base, uint32_t *data) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Check for data to read + if (!(HWREG(base + SPI_O_STA) & SPI_STA_RFE_EMPTY)) + { + *data = HWREG(base + SPI_O_RXDATA); + return (1); + } + else + { + return (0); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the serial peripheral port +// +//***************************************************************************** +void SPIRegisterInt(uint32_t base, void (*pfnHandler)(void)) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Register the interrupt handler + IntRegister((uint32_t)INT_SPI0_COMB, pfnHandler); + + // Enable the synchronous serial port interrupt + IntEnable((uint32_t)INT_SPI0_COMB); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the serial peripheral port +// +//***************************************************************************** +void SPIUnregisterInt(uint32_t base) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Disable the interrupt + IntDisable((uint32_t)INT_SPI0_COMB); + + // Unregister the interrupt handler + IntUnregister((uint32_t)INT_SPI0_COMB); +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.h new file mode 100644 index 00000000..522f7df1 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/spi.h @@ -0,0 +1,678 @@ +/****************************************************************************** + * Filename: spi.h + * + * Description: Defines and prototypes for the Serial Peripheral Interface (SPI). + * + * Copyright (c) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __SPI_H__ +#define __SPI_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup spi_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_spi.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Values that can be passed to SPIEnableInt(), SPIDisableInt(), and SPIClearInt() +// as the intFlags parameter, and returned by SPIIntStatus(). +// +//***************************************************************************** +#define SPI_DMA_DONE_TX SPI_IMASK_DMATX //!< DMA Done 1 event for TX event mask +#define SPI_DMA_DONE_RX SPI_IMASK_DMARX //!< DMA Done 1 event for RX event mask +#define SPI_IDLE SPI_IMASK_IDLE //!< SPI Idle event mask +#define SPI_TXEMPTY SPI_IMASK_TXEMPTY //!< Transmit FIFO Empty event mask +#define SPI_TX SPI_IMASK_TX //!< Transmit FIFO event mask +#define SPI_RX \ + SPI_IMASK_RX //!< Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached +#define SPI_RTOUT SPI_IMASK_RTOUT //!< Enable SPI Receive Time-Out event mask +#define SPI_PER SPI_IMASK_PER //!< Parity error event mask +#define SPI_RXFIFO_OVF SPI_IMASK_RXOVF //!< RXFIFO overflow event mask + +//***************************************************************************** +// +// Values that are returned from SPIStatus +// +//***************************************************************************** +#define SPI_BUSY SPI_STA_BUSY_ACTIVE //!< Busy +#define SPI_RX_NOT_FULL SPI_STA_RNF_NOT_FULL //!< Receive FIFO not full +#define SPI_RX_EMPTY SPI_STA_RFE_EMPTY //!< Receive FIFO empty +#define SPI_TX_NOT_FULL SPI_STA_TNF_NOT_FULL //!< Transmit FIFO not full +#define SPI_TX_EMPTY SPI_STA_TFE_EMPTY //!< Transmit FIFO empty +#define SPI_STATUS_MASK 0x0000001F //!< Mask for bits above + +//***************************************************************************** +// +// Values that can be passed to SPIConfigSetExpClk +// +//***************************************************************************** +//! Motorola format 3-wire, polarity 0, phase 0 +#define SPI_FRF_MOTO_MODE_0 (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_LO | SPI_CTL0_SPH_FIRST) +//! Motorola format 3-wire, polarity 0, phase 1 +#define SPI_FRF_MOTO_MODE_1 (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_LO | SPI_CTL0_SPH_SECOND) +//! Motorola format 3-wire, polarity 1, phase 0 +#define SPI_FRF_MOTO_MODE_2 (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_HI | SPI_CTL0_SPH_FIRST) +//! Motorola format 3-wire, polarity 1, phase 1 +#define SPI_FRF_MOTO_MODE_3 (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_HI | SPI_CTL0_SPH_SECOND) +//! Motorola format 4-wire, polarity 0, phase 0 +#define SPI_FRF_MOTO_MODE_4 (SPI_CTL0_FRF_MOTOROLA_4WIRE | SPI_CTL0_SPO_LO | SPI_CTL0_SPH_FIRST) +//! Motorola format 4-wire, polarity 0, phase 1 +#define SPI_FRF_MOTO_MODE_5 (SPI_CTL0_FRF_MOTOROLA_4WIRE | SPI_CTL0_SPO_LO | SPI_CTL0_SPH_SECOND) +//! Motorola format 4-wire, polarity 1, phase 0 +#define SPI_FRF_MOTO_MODE_6 (SPI_CTL0_FRF_MOTOROLA_4WIRE | SPI_CTL0_SPO_HI | SPI_CTL0_SPH_FIRST) +//! Motorola format 4-wire, polarity 1, phase 1 +#define SPI_FRF_MOTO_MODE_7 (SPI_CTL0_FRF_MOTOROLA_4WIRE | SPI_CTL0_SPO_HI | SPI_CTL0_SPH_SECOND) + +#define SPI_FRF_TI SPI_CTL0_FRF_TI_SYNC //!< TI Sync frame format +#define SPI_FRF_NMW SPI_CTL0_FRF_MIRCOWIRE //!< MicroWire frame format + +#define SPI_MODE_CONTROLLER SPI_CTL1_MS_CONTROLLER //!< SPI controller +#define SPI_MODE_PERIPHERAL SPI_CTL1_MS_PERIPHERAL //!< SPI peripheral +#define SPI_MODE_PERIPHERAL_OD \ + SPI_CTL1_SOD_ENABLE //!< SPI peripheral with POCI + //!< output disabled + +//***************************************************************************** +// +// Values that can be passed to SPIEnableDMA() and SPIDisableDMA() +// +//***************************************************************************** +#define SPI_DMA_TX SPI_DMACR_TXEN //!< Enable DMA for transmit +#define SPI_DMA_RX SPI_DMACR_RXEN //!< Enable DMA for receive + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an SPI base address. +//! +//! This function determines if an SPI module base address is valid. +//! +//! \param base specifies the SPI module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool SPIBaseValid(uint32_t base) +{ + return (base == SPI0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the serial peripheral port. +//! +//! This function configures the serial peripheral port. It sets +//! the SPI protocol, mode of operation, bit rate, and data width. +//! +//! The \c protocol parameter defines the data frame format. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase   Motorola Protocol                  Mode
+//!   0       0           3-wire                SPI_FRF_MOTO_MODE_0
+//!   0       1           3-wire                SPI_FRF_MOTO_MODE_1
+//!   1       0           3-wire                SPI_FRF_MOTO_MODE_2
+//!   1       1           3-wire                SPI_FRF_MOTO_MODE_3
+//!   0       0           4-wire                SPI_FRF_MOTO_MODE_4
+//!   0       1           4-wire                SPI_FRF_MOTO_MODE_5
+//!   1       0           4-wire                SPI_FRF_MOTO_MODE_6
+//!   1       1           4-wire                SPI_FRF_MOTO_MODE_7
+//!
+//! +//! The \c mode parameter defines the operating mode of the SPI module. +//! The SPI module can operate as a controller or peripheral; if a peripheral, the SPI can be +//! configured to disable output on its serial output line. +//! +//! The \c bitRate parameter defines the bit rate for the SPI. +//! +//! The \c dataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 32, for controller mode, and 7 to 32, in peripheral mode. +//! +//! \note The peripheral clock is not necessarily the same as the processor clock. +//! The frequency of the peripheral clock is set by the system control. +//! +//! \param base specifies the SPI module base address. +//! \param spiClk is the rate of the clock supplied to the SPI module. +//! \param protocol specifies the data transfer protocol. +//! The parameter can be one of the following values: +//! - \ref SPI_FRF_MOTO_MODE_0 +//! - \ref SPI_FRF_MOTO_MODE_1 +//! - \ref SPI_FRF_MOTO_MODE_2 +//! - \ref SPI_FRF_MOTO_MODE_3 +//! - \ref SPI_FRF_MOTO_MODE_4 +//! - \ref SPI_FRF_MOTO_MODE_5 +//! - \ref SPI_FRF_MOTO_MODE_6 +//! - \ref SPI_FRF_MOTO_MODE_7 +//! - \ref SPI_FRF_TI +//! - \ref SPI_FRF_NMW. +//! \param mode specifies the mode of operation. +//! The parameter can be one of the following values: +//! - \ref SPI_MODE_CONTROLLER +//! - \ref SPI_MODE_PERIPHERAL +//! - \ref SPI_MODE_PERIPHERAL_OD +//! \param bitRate specifies the clock rate. +//! \param dataWidth specifies number of bits transferred per frame. +//! Must be a value between 4 and 16 for controller mode, and 7 to 16 in peripheral mode. +//! +//! \return None +// +//***************************************************************************** +extern void SPIConfigSetExpClk(uint32_t base, + uint32_t spiClk, + uint32_t protocol, + uint32_t mode, + uint32_t bitRate, + uint32_t dataWidth); + +//***************************************************************************** +// +//! \brief Enables the serial peripheral port. +//! +//! This function enables operation of the serial peripheral port. The +//! serial peripheral port must be configured before it is enabled. +//! +//! \param base specifies the SPI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIEnable(uint32_t base) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Read-modify-write the enable bit + HWREG(base + SPI_O_CTL1) |= SPI_CTL1_EN_EN; +} + +//***************************************************************************** +// +//! \brief Disables the serial peripheral port. +//! +//! This function disables operation of the serial peripheral port. +//! +//! \param base specifies the SPI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIDisable(uint32_t base) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Read-modify-write the enable bit + HWREG(base + SPI_O_CTL1) &= ~SPI_CTL1_EN_EN; +} + +//***************************************************************************** +// +//! \brief Puts a data element into the SPI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SPI module. +//! +//! \note The upper 32 - N bits of the \c data are discarded by the +//! hardware, where N is the data width as configured by \ref SPIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \c data are discarded. +//! +//! \param base specifies the SPI module base address. +//! \param data is the data to be transmitted over the SPI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SPIPutData(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! \brief Puts a data element into the SPI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SPI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of the \c data are discarded by the hardware, +//! where N is the data width as configured by \ref SPIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \c data are discarded. +//! +//! \param base specifies the SPI module base address. +//! \param data is the data to be transmitted over the SPI interface. +//! +//! \return Returns the number of elements written to the SPI transmit FIFO. +// +//***************************************************************************** +extern int32_t SPIPutDataNonBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SPI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified +//! SPI module and places that data into the location specified by the +//! \c data parameter. +//! +//! \note Only the lower N bits of the value written to \c data contain +//! valid data, where N is the data width as configured by +//! \ref SPIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \c data contain valid data. +//! +//! \param base specifies the SPI module base address. +//! \param data is a pointer to a storage location for data that was +//! received over the SPI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SPIGetData(uint32_t base, uint32_t *data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SPI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified SPI +//! module and places that data into the location specified by the \c data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \c data contain +//! valid data, where N is the data width as configured by +//! \ref SPIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \c data +//! contain valid data. +//! +//! \param base specifies the SPI module base address. +//! \param data is a pointer to a storage location for data that was +//! received over the SPI interface. +//! +//! \return Returns the number of elements read from the SPI receive FIFO. +// +//***************************************************************************** +extern int32_t SPIGetDataNonBlocking(uint32_t base, uint32_t *data); + +//***************************************************************************** +// +//! \brief Determines whether the SPI transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, then the transmit FIFO +//! is empty and all bits of the last transmitted word have left the hardware +//! shift register. +//! +//! \param base is the base address of the SPI port. +//! +//! \return Returns status of the SPI transmit buffer. +//! - \c true : SPI is transmitting. +//! - \c false : SPI transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool SPIBusy(uint32_t base) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + /* Determine if the SPI is busy. */ + return ((HWREG(base + SPI_O_STA) & SPI_STA_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Get the status of the SPI data buffers. +//! +//! This function is used to poll the status of the internal FIFOs in the SPI +//! module. The status of both TX and RX FIFO is returned. +//! +//! \param base specifies the SPI module base address. +//! +//! \return Returns the current status of the internal SPI data buffers. +//! The status is a bitwise OR'ed combination of: +//! - \ref SPI_BUSY : Busy +//! - \ref SPI_RX_NOT_FULL : Receive FIFO not full +//! - \ref SPI_RX_EMPTY : Receive FIFO empty +//! - \ref SPI_TX_NOT_FULL : Transmit FIFO not full +//! - \ref SPI_TX_EMPTY : Transmit FIFO empty +// +//***************************************************************************** +__STATIC_INLINE uint32_t SPIStatus(uint32_t base) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Return the status + return (HWREG(base + SPI_O_STA) & SPI_STATUS_MASK); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the +//! Serial Peripheral Interface in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific SPI interrupts must be enabled via \ref SPIEnableInt(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via \ref SPIClearInt(). +//! +//! \param base specifies the SPI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! serial peripheral port interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SPIRegisterInt(uint32_t base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the +//! Serial Peripheral Interface in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SPI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \param base specifies the SPI module base address. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SPIUnregisterInt(uint32_t base); + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! - \ref SPI_DMA_DONE_TX +//! - \ref SPI_DMA_DONE_RX +//! - \ref SPI_IDLE +//! - \ref SPI_TXEMPTY +//! - \ref SPI_TX +//! - \ref SPI_RX +//! - \ref SPI_RTOUT +//! - \ref SPI_PER +//! - \ref SPI_RXFIFO_OVF +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIEnableInt(uint32_t base, uint32_t intFlags) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Enable the specified interrupts + HWREG(base + SPI_O_IMASK) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! - \ref SPI_DMA_DONE_TX +//! - \ref SPI_DMA_DONE_RX +//! - \ref SPI_IDLE +//! - \ref SPI_TXEMPTY +//! - \ref SPI_TX +//! - \ref SPI_RX +//! - \ref SPI_RTOUT +//! - \ref SPI_PER +//! - \ref SPI_RXFIFO_OVF +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIDisableInt(uint32_t base, uint32_t intFlags) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Disable the specified interrupts + HWREG(base + SPI_O_IMASK) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Clears SPI interrupt sources. +//! +//! The specified SPI interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs), +//! (allowing cleared event to propagate through any synchronizers) +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter can consist of either or both of: +//! - \ref SPI_DMA_DONE_TX +//! - \ref SPI_DMA_DONE_RX +//! - \ref SPI_IDLE +//! - \ref SPI_TXEMPTY +//! - \ref SPI_TX +//! - \ref SPI_RX +//! - \ref SPI_RTOUT +//! - \ref SPI_PER +//! - \ref SPI_RXFIFO_OVF +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIClearInt(uint32_t base, uint32_t intFlags) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Clear the requested interrupt sources + HWREG(base + SPI_O_ICLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the SPI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param base specifies the SPI module base address. +//! \param isMasked selects either raw or masked interrupt. +//! \c false : Raw interrupt status is required. +//! \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref SPI_DMA_DONE_TX +//! - \ref SPI_DMA_DONE_RX +//! - \ref SPI_IDLE +//! - \ref SPI_TXEMPTY +//! - \ref SPI_TX +//! - \ref SPI_RX +//! - \ref SPI_RTOUT +//! - \ref SPI_PER +//! - \ref SPI_RXFIFO_OVF +// +//***************************************************************************** +__STATIC_INLINE uint32_t SPIIntStatus(uint32_t base, bool isMasked) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + /* Return either the interrupt status or the raw interrupt status as + requested. */ + if (isMasked) + { + return (HWREG(base + SPI_O_MIS)); + } + else + { + return (HWREG(base + SPI_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Enable SPI DMA operation. +//! +//! The specified SPI DMA features are enabled. The SPI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SPI. +//! +//! \param base is the base address of the SPI port. +//! \param dmaFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SPI_DMA_RX : Enable DMA for receive. +//! - \ref SPI_DMA_TX : Enable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIEnableDMA(uint32_t base, uint32_t dmaFlags) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Set the requested bits in the SPI DMA control register + HWREG(base + SPI_O_DMACR) |= dmaFlags; +} + +//***************************************************************************** +// +//! \brief Disable SPI DMA operation. +//! +//! This function is used to disable SPI DMA features that were enabled +//! by \ref SPIEnableDMA(). The specified SPI DMA features are disabled. +//! +//! \param base is the base address of the SPI port. +//! \param dmaFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SPI_DMA_RX : Disable DMA for receive. +//! - \ref SPI_DMA_TX : Disable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SPIDisableDMA(uint32_t base, uint32_t dmaFlags) +{ + // Check the arguments + ASSERT(SPIBaseValid(base)); + + // Clear the requested bits in the SPI DMA control register + HWREG(base + SPI_O_DMACR) &= ~dmaFlags; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __SPI_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_chacha.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_chacha.c new file mode 100644 index 00000000..484b6523 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_chacha.c @@ -0,0 +1,151 @@ +/****************************************************************************** + * Filename: sw_chacha.c + ******************************************************************************/ +/* +chacha-ref.c version 20080118 +D. J. Bernstein +Public domain. +*/ + +#define ECRYPT_LITTLE_ENDIAN + +#include "sw_ecrypt-sync.h" + +#define ROTATE(v, c) (ROTL32(v, c)) +#define XOR(v, w) ((v) ^ (w)) +#define PLUS(v, w) (U32V((v) + (w))) +#define PLUSONE(v) (PLUS((v), 1)) + +#define QUARTERROUND(a, b, c, d) \ + x[a] = PLUS(x[a], x[b]); \ + x[d] = ROTATE(XOR(x[d], x[a]), 16); \ + x[c] = PLUS(x[c], x[d]); \ + x[b] = ROTATE(XOR(x[b], x[c]), 12); \ + x[a] = PLUS(x[a], x[b]); \ + x[d] = ROTATE(XOR(x[d], x[a]), 8); \ + x[c] = PLUS(x[c], x[d]); \ + x[b] = ROTATE(XOR(x[b], x[c]), 7); + +static void salsa20_wordtobyte(u8 output[64], const u32 input[16]) +{ + u32 x[16]; + int i; + + for (i = 0; i < 16; ++i) + { + x[i] = input[i]; + } + for (i = 8; i > 0; i -= 2) + { + QUARTERROUND(0, 4, 8, 12) + QUARTERROUND(1, 5, 9, 13) + QUARTERROUND(2, 6, 10, 14) + QUARTERROUND(3, 7, 11, 15) + QUARTERROUND(0, 5, 10, 15) + QUARTERROUND(1, 6, 11, 12) + QUARTERROUND(2, 7, 8, 13) + QUARTERROUND(3, 4, 9, 14) + } + for (i = 0; i < 16; ++i) + { + x[i] = PLUS(x[i], input[i]); + } + for (i = 0; i < 16; ++i) + { + U32TO8_LITTLE(output + 4 * i, x[i]); + } +} + +void ECRYPT_init(void) +{ + return; +} + +static const char sigma[16] = "expand 32-byte k"; +static const char tau[16] = "expand 16-byte k"; + +void ECRYPT_keysetup(ECRYPT_ctx *x, const u8 *k, u32 kbits, u32 ivbits) +{ + const char *constants; + + x->input[4] = U8TO32_LITTLE(k + 0); + x->input[5] = U8TO32_LITTLE(k + 4); + x->input[6] = U8TO32_LITTLE(k + 8); + x->input[7] = U8TO32_LITTLE(k + 12); + if (kbits == 256) + { /* recommended */ + k += 16; + constants = sigma; + } + else + { /* kbits == 128 */ + constants = tau; + } + x->input[8] = U8TO32_LITTLE(k + 0); + x->input[9] = U8TO32_LITTLE(k + 4); + x->input[10] = U8TO32_LITTLE(k + 8); + x->input[11] = U8TO32_LITTLE(k + 12); + x->input[0] = U8TO32_LITTLE(constants + 0); + x->input[1] = U8TO32_LITTLE(constants + 4); + x->input[2] = U8TO32_LITTLE(constants + 8); + x->input[3] = U8TO32_LITTLE(constants + 12); +} + +void ECRYPT_ivsetup(ECRYPT_ctx *x, const u8 *iv) +{ + x->input[12] = 0; + x->input[13] = 0; + x->input[14] = U8TO32_LITTLE(iv + 0); + x->input[15] = U8TO32_LITTLE(iv + 4); +} + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *x, const u8 *m, u8 *c, u32 bytes) +{ + u8 output[64]; + int i; + + if (!bytes) + { + return; + } + for (;;) + { + salsa20_wordtobyte(output, x->input); + x->input[12] = PLUSONE(x->input[12]); + if (!x->input[12]) + { + x->input[13] = PLUSONE(x->input[13]); + /* stopping at 2^70 bytes per nonce is user's responsibility */ + } + if (bytes <= 64) + { + for (i = 0; i < bytes; ++i) + { + c[i] = m[i] ^ output[i]; + } + return; + } + for (i = 0; i < 64; ++i) + { + c[i] = m[i] ^ output[i]; + } + bytes -= 64; + c += 64; + m += 64; + } +} + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *x, const u8 *c, u8 *m, u32 bytes) +{ + ECRYPT_encrypt_bytes(x, c, m, bytes); +} + +void ECRYPT_keystream_bytes(ECRYPT_ctx *x, u8 *stream, u32 bytes) +{ + u32 i; + for (i = 0; i < bytes; ++i) + { + stream[i] = 0; + } + ECRYPT_encrypt_bytes(x, stream, stream, bytes); +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-config.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-config.h new file mode 100644 index 00000000..9c6e92d6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-config.h @@ -0,0 +1,277 @@ +/****************************************************************************** + * Filename: sw_ecrypt-config.h + ******************************************************************************/ +/* ecrypt-config.h */ + +/* *** Normally, it should not be necessary to edit this file. *** */ + +#ifndef ECRYPT_CONFIG +#define ECRYPT_CONFIG + +/* ------------------------------------------------------------------------- */ + +/* Guess the endianness of the target architecture. */ + +/* + * The LITTLE endian machines: + */ +#if (!defined(ECRYPT_LITTLE_ENDIAN)) + #if defined(__ultrix) /* Older MIPS */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(__alpha) /* Alpha */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(i386) /* x86 (gcc) */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(__i386) /* x86 (gcc) */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(_M_IX86) /* x86 (MSC, Borland) */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(_MSC_VER) /* x86 (surely MSC) */ + #define ECRYPT_LITTLE_ENDIAN + #elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ + #define ECRYPT_LITTLE_ENDIAN + + /* + * The BIG endian machines: + */ + #elif defined(sun) /* Newer Sparc's */ + #define ECRYPT_BIG_ENDIAN + #elif defined(__ppc__) /* PowerPC */ + #define ECRYPT_BIG_ENDIAN + + /* + * Finally machines with UNKNOWN endianness: + */ + #elif defined(_AIX) /* RS6000 */ + #define ECRYPT_UNKNOWN + #elif defined(__hpux) /* HP-PA */ + #define ECRYPT_UNKNOWN + #elif defined(__aux) /* 68K */ + #define ECRYPT_UNKNOWN + #elif defined(__dgux) /* 88K (but P6 in latest boxes) */ + #define ECRYPT_UNKNOWN + #elif defined(__sgi) /* Newer MIPS */ + #define ECRYPT_UNKNOWN + #else /* Any other processor */ + #define ECRYPT_UNKNOWN + #endif +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit + * integers. + * + * Note: to enable 64-bit types on 32-bit compilers, it might be + * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc + * -std=c99). + */ + +#include + +/* --- check char --- */ + +#if (UCHAR_MAX / 0xFU > 0xFU) + #ifndef I8T + #define I8T char + #define U8C(v) (v##U) + + #if (UCHAR_MAX == 0xFFU) + #define ECRYPT_I8T_IS_BYTE + #endif + + #endif + + #if (UCHAR_MAX / 0xFFU > 0xFFU) + #ifndef I16T + #define I16T char + #define U16C(v) (v##U) + #endif + + #if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) + #ifndef I32T + #define I32T char + #define U32C(v) (v##U) + #endif + + #if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) + #ifndef I64T + #define I64T char + #define U64C(v) (v##U) + #define ECRYPT_NATIVE64 + #endif + + #endif + #endif + #endif +#endif + +/* --- check short --- */ + +#if (USHRT_MAX / 0xFU > 0xFU) + #ifndef I8T + #define I8T short + #define U8C(v) (v##U) + + #if (USHRT_MAX == 0xFFU) + #define ECRYPT_I8T_IS_BYTE + #endif + + #endif + + #if (USHRT_MAX / 0xFFU > 0xFFU) + #ifndef I16T + #define I16T short + #define U16C(v) (v##U) + #endif + + #if (USHRT_MAX / 0xFFFFU > 0xFFFFU) + #ifndef I32T + #define I32T short + #define U32C(v) (v##U) + #endif + + #if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) + #ifndef I64T + #define I64T short + #define U64C(v) (v##U) + #define ECRYPT_NATIVE64 + #endif + + #endif + #endif + #endif +#endif + +/* --- check int --- */ + +#if (UINT_MAX / 0xFU > 0xFU) + #ifndef I8T + #define I8T int + #define U8C(v) (v##U) + + #if (ULONG_MAX == 0xFFU) + #define ECRYPT_I8T_IS_BYTE + #endif + + #endif + + #if (UINT_MAX / 0xFFU > 0xFFU) + #ifndef I16T + #define I16T int + #define U16C(v) (v##U) + #endif + + #if (UINT_MAX / 0xFFFFU > 0xFFFFU) + #ifndef I32T + #define I32T int + #define U32C(v) (v##U) + #endif + + #if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) + #ifndef I64T + #define I64T int + #define U64C(v) (v##U) + #define ECRYPT_NATIVE64 + #endif + + #endif + #endif + #endif +#endif + +/* --- check long --- */ + +#if (ULONG_MAX / 0xFUL > 0xFUL) + #ifndef I8T + #define I8T long + #define U8C(v) (v##UL) + + #if (ULONG_MAX == 0xFFUL) + #define ECRYPT_I8T_IS_BYTE + #endif + + #endif + + #if (ULONG_MAX / 0xFFUL > 0xFFUL) + #ifndef I16T + #define I16T long + #define U16C(v) (v##UL) + #endif + + #if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) + #ifndef I32T + #define I32T long + #define U32C(v) (v##UL) + #endif + + #if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) + #ifndef I64T + #define I64T long + #define U64C(v) (v##UL) + #define ECRYPT_NATIVE64 + #endif + + #endif + #endif + #endif +#endif + +/* --- check long long --- */ + +#ifdef ULLONG_MAX + + #if (ULLONG_MAX / 0xFULL > 0xFULL) + #ifndef I8T + #define I8T long long + #define U8C(v) (v##ULL) + + #if (ULLONG_MAX == 0xFFULL) + #define ECRYPT_I8T_IS_BYTE + #endif + + #endif + + #if (ULLONG_MAX / 0xFFULL > 0xFFULL) + #ifndef I16T + #define I16T long long + #define U16C(v) (v##ULL) + #endif + + #if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) + #ifndef I32T + #define I32T long long + #define U32C(v) (v##ULL) + #endif + + #if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) + #ifndef I64T + #define I64T long long + #define U64C(v) (v##ULL) + #endif + + #endif + #endif + #endif + #endif + +#endif + +/* --- check __int64 --- */ + +#ifdef _UI64_MAX + + #if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) + #ifndef I64T + #define I64T __int64 + #define U64C(v) (v##ui64) + #endif + + #endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-machine.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-machine.h new file mode 100644 index 00000000..c2a7e19e --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-machine.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * Filename: sw_ecrypt-machine.h + ******************************************************************************/ +/* ecrypt-machine.h */ + +/* + * This file is included by 'ecrypt-portable.h'. It allows to override + * the default macros for specific platforms. Please carefully check + * the machine code generated by your compiler (with optimisations + * turned on) before deciding to edit this file. + */ + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) + + #define ECRYPT_MACHINE_ROT + + #if (defined(WIN32) && defined(_MSC_VER)) + + #undef ROTL32 + #undef ROTR32 + #undef ROTL64 + #undef ROTR64 + + #include + + #define ROTL32(v, n) _lrotl(v, n) + #define ROTR32(v, n) _lrotr(v, n) + #define ROTL64(v, n) _rotl64(v, n) + #define ROTR64(v, n) _rotr64(v, n) + + #endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) + + #define ECRYPT_MACHINE_SWAP + +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ + +#endif + +/* ------------------------------------------------------------------------- */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-portable.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-portable.h new file mode 100644 index 00000000..192f146c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-portable.h @@ -0,0 +1,278 @@ +/****************************************************************************** + * Filename: sw_ecrypt-portable.h + ******************************************************************************/ +/* ecrypt-portable.h */ + +/* + * WARNING: the conversions defined below are implemented as macros, + * and should be used carefully. They should NOT be used with + * parameters which perform some action. E.g., the following two lines + * are not equivalent: + * + * 1) ++x; y = ROTL32(x, n); + * 2) y = ROTL32(++x, n); + */ + +/* + * *** Please do not edit this file. *** + * + * The default macros can be overridden for specific architectures by + * editing 'ecrypt-machine.h'. + */ + +#ifndef ECRYPT_PORTABLE +#define ECRYPT_PORTABLE + +#include "sw_ecrypt-config.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following types are defined (if available): + * + * u8: unsigned integer type, at least 8 bits + * u16: unsigned integer type, at least 16 bits + * u32: unsigned integer type, at least 32 bits + * u64: unsigned integer type, at least 64 bits + * + * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 + * + * The selection of minimum-width integer types is taken care of by + * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit + * compilers, it might be necessary to switch from ISO C90 mode to ISO + * C99 mode (e.g., gcc -std=c99). + */ + +#ifdef I8T +typedef signed I8T s8; +typedef unsigned I8T u8; +#endif + +#ifdef I16T +typedef signed I16T s16; +typedef unsigned I16T u16; +#endif + +#ifdef I32T +typedef signed I32T s32; +typedef unsigned I32T u32; +#endif + +#ifdef I64T +typedef signed I64T s64; +typedef unsigned I64T u64; +#endif + +/* + * The following macros are used to obtain exact-width results. + */ + +#define U8V(v) ((u8)(v)&U8C(0xFF)) +#define U16V(v) ((u16)(v)&U16C(0xFFFF)) +#define U32V(v) ((u32)(v)&U32C(0xFFFFFFFF)) +#define U64V(v) ((u64)(v)&U64C(0xFFFFFFFFFFFFFFFF)) + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return words with their bits rotated over n + * positions to the left/right. + */ + +#define ECRYPT_DEFAULT_ROT + +#define ROTL8(v, n) (U8V((v) << (n)) | ((v) >> (8 - (n)))) + +#define ROTL16(v, n) (U16V((v) << (n)) | ((v) >> (16 - (n)))) + +#define ROTL32(v, n) (U32V((v) << (n)) | ((v) >> (32 - (n)))) + +#define ROTL64(v, n) (U64V((v) << (n)) | ((v) >> (64 - (n)))) + +#define ROTR8(v, n) ROTL8(v, 8 - (n)) +#define ROTR16(v, n) ROTL16(v, 16 - (n)) +#define ROTR32(v, n) ROTL32(v, 32 - (n)) +#define ROTR64(v, n) ROTL64(v, 64 - (n)) + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return a word with bytes in reverse order. + */ + +#define ECRYPT_DEFAULT_SWAP + +#define SWAP16(v) ROTL16(v, 8) + +#define SWAP32(v) ((ROTL32(v, 8) & U32C(0x00FF00FF)) | (ROTL32(v, 24) & U32C(0xFF00FF00))) + +#ifdef ECRYPT_NATIVE64 + #define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ + (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | (ROTL64(v, 56) & U64C(0xFF000000FF000000))) +#else + #define SWAP64(v) (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) +#endif + +#include "sw_ecrypt-machine.h" + +#define ECRYPT_DEFAULT_WTOW + +#ifdef ECRYPT_LITTLE_ENDIAN + #define U16TO16_LITTLE(v) (v) + #define U32TO32_LITTLE(v) (v) + #define U64TO64_LITTLE(v) (v) + + #define U16TO16_BIG(v) SWAP16(v) + #define U32TO32_BIG(v) SWAP32(v) + #define U64TO64_BIG(v) SWAP64(v) +#endif + +#ifdef ECRYPT_BIG_ENDIAN + #define U16TO16_LITTLE(v) SWAP16(v) + #define U32TO32_LITTLE(v) SWAP32(v) + #define U64TO64_LITTLE(v) SWAP64(v) + + #define U16TO16_BIG(v) (v) + #define U32TO32_BIG(v) (v) + #define U64TO64_BIG(v) (v) +#endif + +#include "sw_ecrypt-machine.h" + +/* + * The following macros load words from an array of bytes with + * different types of endianness, and vice versa. + */ + +#define ECRYPT_DEFAULT_BTOW + +#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) + + #define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16 *)(p))[0]) + #define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32 *)(p))[0]) + #define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64 *)(p))[0]) + + #define U8TO16_BIG(p) U16TO16_BIG(((u16 *)(p))[0]) + #define U8TO32_BIG(p) U32TO32_BIG(((u32 *)(p))[0]) + #define U8TO64_BIG(p) U64TO64_BIG(((u64 *)(p))[0]) + + #define U16TO8_LITTLE(p, v) (((u16 *)(p))[0] = U16TO16_LITTLE(v)) + #define U32TO8_LITTLE(p, v) (((u32 *)(p))[0] = U32TO32_LITTLE(v)) + #define U64TO8_LITTLE(p, v) (((u64 *)(p))[0] = U64TO64_LITTLE(v)) + + #define U16TO8_BIG(p, v) (((u16 *)(p))[0] = U16TO16_BIG(v)) + #define U32TO8_BIG(p, v) (((u32 *)(p))[0] = U32TO32_BIG(v)) + #define U64TO8_BIG(p, v) (((u64 *)(p))[0] = U64TO64_BIG(v)) + +#else + + #define U8TO16_LITTLE(p) (((u16)((p)[0])) | ((u16)((p)[1]) << 8)) + + #define U8TO32_LITTLE(p) (((u32)((p)[0])) | ((u32)((p)[1]) << 8) | ((u32)((p)[2]) << 16) | ((u32)((p)[3]) << 24)) + + #ifdef ECRYPT_NATIVE64 + #define U8TO64_LITTLE(p) \ + (((u64)((p)[0])) | ((u64)((p)[1]) << 8) | ((u64)((p)[2]) << 16) | ((u64)((p)[3]) << 24) | \ + ((u64)((p)[4]) << 32) | ((u64)((p)[5]) << 40) | ((u64)((p)[6]) << 48) | ((u64)((p)[7]) << 56)) + #else + #define U8TO64_LITTLE(p) ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) + #endif + + #define U8TO16_BIG(p) (((u16)((p)[0]) << 8) | ((u16)((p)[1]))) + + #define U8TO32_BIG(p) (((u32)((p)[0]) << 24) | ((u32)((p)[1]) << 16) | ((u32)((p)[2]) << 8) | ((u32)((p)[3]))) + + #ifdef ECRYPT_NATIVE64 + #define U8TO64_BIG(p) \ + (((u64)((p)[0]) << 56) | ((u64)((p)[1]) << 48) | ((u64)((p)[2]) << 40) | ((u64)((p)[3]) << 32) | \ + ((u64)((p)[4]) << 24) | ((u64)((p)[5]) << 16) | ((u64)((p)[6]) << 8) | ((u64)((p)[7]))) + #else + #define U8TO64_BIG(p) (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) + #endif + + #define U16TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + + #define U32TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + } while (0) + + #ifdef ECRYPT_NATIVE64 + #define U64TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + (p)[4] = U8V((v) >> 32); \ + (p)[5] = U8V((v) >> 40); \ + (p)[6] = U8V((v) >> 48); \ + (p)[7] = U8V((v) >> 56); \ + } while (0) + #else + #define U64TO8_LITTLE(p, v) \ + do \ + { \ + U32TO8_LITTLE((p), U32V((v))); \ + U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ + } while (0) + #endif + + #define U16TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + + #define U32TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v) >> 24); \ + (p)[1] = U8V((v) >> 16); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v)); \ + } while (0) + + #ifdef ECRYPT_NATIVE64 + #define U64TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v) >> 56); \ + (p)[1] = U8V((v) >> 48); \ + (p)[2] = U8V((v) >> 40); \ + (p)[3] = U8V((v) >> 32); \ + (p)[4] = U8V((v) >> 24); \ + (p)[5] = U8V((v) >> 16); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v)); \ + } while (0) + #else + #define U64TO8_BIG(p, v) \ + do \ + { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v))); \ + } while (0) + #endif + +#endif + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-sync.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-sync.h new file mode 100644 index 00000000..0098b4c2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_ecrypt-sync.h @@ -0,0 +1,248 @@ +/****************************************************************************** + * Filename: sw_ecrypt-sync.h + ******************************************************************************/ +/* ecrypt-sync.h */ + +/* + * Header file for synchronous stream ciphers without authentication + * mechanism. + * + * *** Please only edit parts marked with "[edit]". *** + */ + +#ifndef ECRYPT_SYNC +#define ECRYPT_SYNC + +#include "sw_ecrypt-portable.h" + +/* ------------------------------------------------------------------------- */ + +/* Cipher parameters */ + +/* + * The name of your cipher. + */ +#define ECRYPT_NAME "ChaCha8" +#define ECRYPT_PROFILE "_____" + +/* + * Specify which key and IV sizes are supported by your cipher. A user + * should be able to enumerate the supported sizes by running the + * following code: + * + * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) + * { + * keysize = ECRYPT_KEYSIZE(i); + * + * ... + * } + * + * All sizes are in bits. + */ + +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ + +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ + +/* ------------------------------------------------------------------------- */ + +/* Data structures */ + +/* + * ECRYPT_ctx is the structure containing the representation of the + * internal state of your cipher. + */ + +typedef struct +{ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ +} ECRYPT_ctx; + +/* ------------------------------------------------------------------------- */ + +/* Mandatory functions */ + +/* + * Key and message independent initialization. This function will be + * called once when the program starts (e.g., to build expanded S-box + * tables). + */ +void ECRYPT_init(void); + +/* + * Key setup. It is the user's responsibility to select the values of + * keysize and ivsize from the set of supported values specified + * above. + */ +void ECRYPT_keysetup(ECRYPT_ctx *ctx, + const u8 *key, + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ + +/* + * IV setup. After having called ECRYPT_keysetup(), the user is + * allowed to call ECRYPT_ivsetup() different times in order to + * encrypt/decrypt different messages with the same key but different + * IV's. + */ +void ECRYPT_ivsetup(ECRYPT_ctx *ctx, const u8 *iv); + +/* + * Encryption/decryption of arbitrary length messages. + * + * For efficiency reasons, the API provides two types of + * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function + * (declared here) encrypts byte strings of arbitrary length, while + * the ECRYPT_encrypt_blocks() function (defined later) only accepts + * lengths which are multiples of ECRYPT_BLOCKLENGTH. + * + * The user is allowed to make multiple calls to + * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, + * but he is NOT allowed to make additional encryption calls once he + * has called ECRYPT_encrypt_bytes() (unless he starts a new message + * of course). For example, this sequence of calls is acceptable: + * + * ECRYPT_keysetup(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_bytes(); + * + * The following sequence is not: + * + * ECRYPT_keysetup(); + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * ECRYPT_encrypt_blocks(); + */ + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *ctx, const u8 *plaintext, u8 *ciphertext, u32 msglen); /* Message length in bytes. + */ + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *ctx, const u8 *ciphertext, u8 *plaintext, u32 msglen); /* Message length in bytes. + */ + +/* ------------------------------------------------------------------------- */ + +/* Optional features */ + +/* + * For testing purposes it can sometimes be useful to have a function + * which immediately generates keystream without having to provide it + * with a zero plaintext. If your cipher cannot provide this function + * (e.g., because it is not strictly a synchronous cipher), please + * reset the ECRYPT_GENERATES_KEYSTREAM flag. + */ + +#define ECRYPT_GENERATES_KEYSTREAM +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_bytes(ECRYPT_ctx *ctx, u8 *keystream, u32 length); /* Length of keystream in bytes. */ + +#endif + +/* ------------------------------------------------------------------------- */ + +/* Optional optimizations */ + +/* + * By default, the functions in this section are implemented using + * calls to functions declared above. However, you might want to + * implement them differently for performance reasons. + */ + +/* + * All-in-one encryption/decryption of (short) packets. + * + * The default definitions of these functions can be found in + * "ecrypt-sync.c". If you want to implement them differently, please + * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. + */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ + +void ECRYPT_encrypt_packet(ECRYPT_ctx *ctx, const u8 *iv, const u8 *plaintext, u8 *ciphertext, u32 msglen); + +void ECRYPT_decrypt_packet(ECRYPT_ctx *ctx, const u8 *iv, const u8 *ciphertext, u8 *plaintext, u32 msglen); + +/* + * Encryption/decryption of blocks. + * + * By default, these functions are defined as macros. If you want to + * provide a different implementation, please undef the + * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions + * declared below. + */ + +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ + +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS + + #define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, (blocks)*ECRYPT_BLOCKLENGTH) + + #define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, (blocks)*ECRYPT_BLOCKLENGTH) + + #ifdef ECRYPT_GENERATES_KEYSTREAM + + #define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, (blocks)*ECRYPT_BLOCKLENGTH) + + #endif + +#else + +void ECRYPT_encrypt_blocks(ECRYPT_ctx *ctx, const u8 *plaintext, u8 *ciphertext, u32 blocks); /* Message length in + blocks. */ + +void ECRYPT_decrypt_blocks(ECRYPT_ctx *ctx, const u8 *ciphertext, u8 *plaintext, u32 blocks); /* Message length in + blocks. */ + + #ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_blocks(ECRYPT_ctx *ctx, const u8 *keystream, u32 blocks); /* Keystream length in blocks. */ + + #endif + +#endif + +/* + * If your cipher can be implemented in different ways, you can use + * the ECRYPT_VARIANT parameter to allow the user to choose between + * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please + * only use this possibility if you really think it could make a + * significant difference and keep the number of variants + * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than + * 10). Note also that all variants should have exactly the same + * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). + */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ + +#ifndef ECRYPT_VARIANT + #define ECRYPT_VARIANT 1 +#endif + +#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) + #error this variant does not exist +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna-32.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna-32.h new file mode 100644 index 00000000..5c877218 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna-32.h @@ -0,0 +1,260 @@ +/****************************************************************************** + * Filename: sw_poly1305-donna-32.h + ******************************************************************************/ +/* + poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition +*/ + +#if defined(_MSC_VER) + #define POLY1305_NOINLINE __declspec(noinline) +#elif defined(__GNUC__) + #define POLY1305_NOINLINE __attribute__((noinline)) +#else + #define POLY1305_NOINLINE +#endif + +#define poly1305_block_size 16 + +/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ +typedef struct +{ + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; +} poly1305_state_internal_t; + +/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ +static unsigned long U8TO32(const unsigned char *p) +{ + return (((unsigned long)(p[0] & 0xff)) | ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | ((unsigned long)(p[3] & 0xff) << 24)); +} + +/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ +static void U32TO8(unsigned char *p, unsigned long v) +{ + p[0] = (v)&0xff; + p[1] = (v >> 8) & 0xff; + p[2] = (v >> 16) & 0xff; + p[3] = (v >> 24) & 0xff; +} + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]) +{ + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + + /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ + st->r[0] = (U8TO32(&key[0])) & 0x3ffffff; + st->r[1] = (U8TO32(&key[3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[9]) >> 6) & 0x3f03fff; + st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; + + /* h = 0 */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + + /* save pad for later */ + st->pad[0] = U8TO32(&key[16]); + st->pad[1] = U8TO32(&key[20]); + st->pad[2] = U8TO32(&key[24]); + st->pad[3] = U8TO32(&key[28]); + + st->leftover = 0; + st->final = 0; +} + +static void poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) +{ + const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ + unsigned long r0, r1, r2, r3, r4; + unsigned long s1, s2, s3, s4; + unsigned long h0, h1, h2, h3, h4; + unsigned long long d0, d1, d2, d3, d4; + unsigned long c; + + r0 = st->r[0]; + r1 = st->r[1]; + r2 = st->r[2]; + r3 = st->r[3]; + r4 = st->r[4]; + + s1 = r1 * 5; + s2 = r2 * 5; + s3 = r3 * 5; + s4 = r4 * 5; + + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + while (bytes >= poly1305_block_size) + { + /* h += m[i] */ + h0 += (U8TO32(m + 0)) & 0x3ffffff; + h1 += (U8TO32(m + 3) >> 2) & 0x3ffffff; + h2 += (U8TO32(m + 6) >> 4) & 0x3ffffff; + h3 += (U8TO32(m + 9) >> 6) & 0x3ffffff; + h4 += (U8TO32(m + 12) >> 8) | hibit; + + /* h *= r */ + d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); + d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); + d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); + d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); + d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); + + /* (partial) h %= p */ + c = (unsigned long)(d0 >> 26); + h0 = (unsigned long)d0 & 0x3ffffff; + d1 += c; + c = (unsigned long)(d1 >> 26); + h1 = (unsigned long)d1 & 0x3ffffff; + d2 += c; + c = (unsigned long)(d2 >> 26); + h2 = (unsigned long)d2 & 0x3ffffff; + d3 += c; + c = (unsigned long)(d3 >> 26); + h3 = (unsigned long)d3 & 0x3ffffff; + d4 += c; + c = (unsigned long)(d4 >> 26); + h4 = (unsigned long)d4 & 0x3ffffff; + h0 += c * 5; + c = (h0 >> 26); + h0 = h0 & 0x3ffffff; + h1 += c; + + m += poly1305_block_size; + bytes -= poly1305_block_size; + } + + st->h[0] = h0; + st->h[1] = h1; + st->h[2] = h2; + st->h[3] = h3; + st->h[4] = h4; +} + +POLY1305_NOINLINE void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) +{ + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + unsigned long h0, h1, h2, h3, h4, c; + unsigned long g0, g1, g2, g3, g4; + unsigned long long f; + unsigned long mask; + + /* process the remaining block */ + if (st->leftover) + { + size_t i = st->leftover; + st->buffer[i++] = 1; + for (; i < poly1305_block_size; i++) + { + st->buffer[i] = 0; + } + st->final = 1; + poly1305_blocks(st, st->buffer, poly1305_block_size); + } + + /* fully carry h */ + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + c = h1 >> 26; + h1 = h1 & 0x3ffffff; + h2 += c; + c = h2 >> 26; + h2 = h2 & 0x3ffffff; + h3 += c; + c = h3 >> 26; + h3 = h3 & 0x3ffffff; + h4 += c; + c = h4 >> 26; + h4 = h4 & 0x3ffffff; + h0 += c * 5; + c = h0 >> 26; + h0 = h0 & 0x3ffffff; + h1 += c; + + /* compute h + -p */ + g0 = h0 + 5; + c = g0 >> 26; + g0 &= 0x3ffffff; + g1 = h1 + c; + c = g1 >> 26; + g1 &= 0x3ffffff; + g2 = h2 + c; + c = g2 >> 26; + g2 &= 0x3ffffff; + g3 = h3 + c; + c = g3 >> 26; + g3 &= 0x3ffffff; + g4 = h4 + c - (1UL << 26); + + /* select h if h < p, or h + -p if h >= p */ + mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; + g0 &= mask; + g1 &= mask; + g2 &= mask; + g3 &= mask; + g4 &= mask; + mask = ~mask; + h0 = (h0 & mask) | g0; + h1 = (h1 & mask) | g1; + h2 = (h2 & mask) | g2; + h3 = (h3 & mask) | g3; + h4 = (h4 & mask) | g4; + + /* h = h % (2^128) */ + h0 = ((h0) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + + /* mac = (h + pad) % (2^128) */ + f = (unsigned long long)h0 + st->pad[0]; + h0 = (unsigned long)f; + f = (unsigned long long)h1 + st->pad[1] + (f >> 32); + h1 = (unsigned long)f; + f = (unsigned long long)h2 + st->pad[2] + (f >> 32); + h2 = (unsigned long)f; + f = (unsigned long long)h3 + st->pad[3] + (f >> 32); + h3 = (unsigned long)f; + + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); + U32TO8(mac + 12, h3); + + /* zero out the state */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + st->r[0] = 0; + st->r[1] = 0; + st->r[2] = 0; + st->r[3] = 0; + st->r[4] = 0; + st->pad[0] = 0; + st->pad[1] = 0; + st->pad[2] = 0; + st->pad[3] = 0; +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.c new file mode 100644 index 00000000..a1ec6948 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.c @@ -0,0 +1,182 @@ +/****************************************************************************** + * Filename: sw_poly1305-donna.c + ******************************************************************************/ + +#include "sw_poly1305-donna.h" + +#include "sw_poly1305-donna-32.h" + +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) +{ + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + size_t i; + + /* handle leftover */ + if (st->leftover) + { + size_t want = (poly1305_block_size - st->leftover); + if (want > bytes) + { + want = bytes; + } + for (i = 0; i < want; i++) + { + st->buffer[st->leftover + i] = m[i]; + } + bytes -= want; + m += want; + st->leftover += want; + if (st->leftover < poly1305_block_size) + { + return; + } + poly1305_blocks(st, st->buffer, poly1305_block_size); + st->leftover = 0; + } + + /* process full blocks */ + if (bytes >= poly1305_block_size) + { + size_t want = (bytes & ~(poly1305_block_size - 1)); + poly1305_blocks(st, m, want); + m += want; + bytes -= want; + } + + /* store leftover */ + if (bytes) + { + for (i = 0; i < bytes; i++) + { + st->buffer[st->leftover + i] = m[i]; + } + st->leftover += bytes; + } +} + +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) +{ + poly1305_context ctx; + poly1305_init(&ctx, key); + poly1305_update(&ctx, m, bytes); + poly1305_finish(&ctx, mac); +} + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) +{ + size_t i; + unsigned int dif = 0; + for (i = 0; i < 16; i++) + { + dif |= (mac1[i] ^ mac2[i]); + } + dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); + return (dif & 1); +} + +/* test a few basic operations */ +int poly1305_power_on_self_test(void) +{ + /* example from nacl */ + static const unsigned char nacl_key[32] = {0xee, 0xa6, 0xa7, 0x25, 0x1c, 0x1e, 0x72, 0x91, 0x6d, 0x11, 0xc2, + 0xcb, 0x21, 0x4d, 0x3c, 0x25, 0x25, 0x39, 0x12, 0x1d, 0x8e, 0x23, + 0x4e, 0x65, 0x2d, 0x65, 0x1f, 0xa4, 0xc8, 0xcf, 0xf8, 0x80}; + + static const unsigned char nacl_msg[131] = {0x8e, 0x99, 0x3b, 0x9f, 0x48, 0x68, 0x12, 0x73, 0xc2, 0x96, 0x50, 0xba, + 0x32, 0xfc, 0x76, 0xce, 0x48, 0x33, 0x2e, 0xa7, 0x16, 0x4d, 0x96, 0xa4, + 0x47, 0x6f, 0xb8, 0xc5, 0x31, 0xa1, 0x18, 0x6a, 0xc0, 0xdf, 0xc1, 0x7c, + 0x98, 0xdc, 0xe8, 0x7b, 0x4d, 0xa7, 0xf0, 0x11, 0xec, 0x48, 0xc9, 0x72, + 0x71, 0xd2, 0xc2, 0x0f, 0x9b, 0x92, 0x8f, 0xe2, 0x27, 0x0d, 0x6f, 0xb8, + 0x63, 0xd5, 0x17, 0x38, 0xb4, 0x8e, 0xee, 0xe3, 0x14, 0xa7, 0xcc, 0x8a, + 0xb9, 0x32, 0x16, 0x45, 0x48, 0xe5, 0x26, 0xae, 0x90, 0x22, 0x43, 0x68, + 0x51, 0x7a, 0xcf, 0xea, 0xbd, 0x6b, 0xb3, 0x73, 0x2b, 0xc0, 0xe9, 0xda, + 0x99, 0x83, 0x2b, 0x61, 0xca, 0x01, 0xb6, 0xde, 0x56, 0x24, 0x4a, 0x9e, + 0x88, 0xd5, 0xf9, 0xb3, 0x79, 0x73, 0xf6, 0x22, 0xa4, 0x3d, 0x14, 0xa6, + 0x59, 0x9b, 0x1f, 0x65, 0x4c, 0xb4, 0x5a, 0x74, 0xe3, 0x55, 0xa5}; + + static const unsigned char nacl_mac[16] = + {0xf3, 0xff, 0xc7, 0x70, 0x3f, 0x94, 0x00, 0xe5, 0x2a, 0x7d, 0xfb, 0x4b, 0x3d, 0x33, 0x05, 0xd9}; + + /* generates a final value of (2^130 - 2) == 3 */ + static const unsigned char wrap_key[32] = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + static const unsigned char wrap_msg[16] = + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + static const unsigned char wrap_mac[16] = + {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + /* + mac of the macs of messages of length 0 to 256, where the key and messages + have all their values set to the length + */ + static const unsigned char total_key[32] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0xff, 0xfe, 0xfd, + 0xfc, 0xfb, 0xfa, 0xf9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + static const unsigned char total_mac[16] = + {0x64, 0xaf, 0xe2, 0xe8, 0xd6, 0xad, 0x7b, 0xbd, 0xd2, 0x87, 0xf9, 0x7c, 0x44, 0x62, 0x3d, 0x39}; + + poly1305_context ctx; + poly1305_context total_ctx; + unsigned char all_key[32]; + unsigned char all_msg[256]; + unsigned char mac[16]; + size_t i, j; + int result = 1; + + for (i = 0; i < sizeof(mac); i++) + { + mac[i] = 0; + } + poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + { + mac[i] = 0; + } + poly1305_init(&ctx, nacl_key); + poly1305_update(&ctx, nacl_msg + 0, 32); + poly1305_update(&ctx, nacl_msg + 32, 64); + poly1305_update(&ctx, nacl_msg + 96, 16); + poly1305_update(&ctx, nacl_msg + 112, 8); + poly1305_update(&ctx, nacl_msg + 120, 4); + poly1305_update(&ctx, nacl_msg + 124, 2); + poly1305_update(&ctx, nacl_msg + 126, 1); + poly1305_update(&ctx, nacl_msg + 127, 1); + poly1305_update(&ctx, nacl_msg + 128, 1); + poly1305_update(&ctx, nacl_msg + 129, 1); + poly1305_update(&ctx, nacl_msg + 130, 1); + poly1305_finish(&ctx, mac); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + { + mac[i] = 0; + } + poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); + result &= poly1305_verify(wrap_mac, mac); + + poly1305_init(&total_ctx, total_key); + for (i = 0; i < 256; i++) + { + /* set key and message to 'i,i,i..' */ + for (j = 0; j < sizeof(all_key); j++) + { + all_key[j] = i; + } + for (j = 0; j < i; j++) + { + all_msg[j] = i; + } + poly1305_auth(mac, all_msg, i, all_key); + poly1305_update(&total_ctx, mac, 16); + } + poly1305_finish(&total_ctx, mac); + result &= poly1305_verify(total_mac, mac); + + return result; +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.h new file mode 100644 index 00000000..dbf2e89b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/sw_poly1305-donna.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * Filename: sw_poly1305-donna.h + ******************************************************************************/ + +#ifndef POLY1305_DONNA_H +#define POLY1305_DONNA_H + +#include + +typedef struct +{ + size_t aligner; + unsigned char opaque[136]; +} poly1305_context; + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); +void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); +int poly1305_power_on_self_test(void); + +#endif /* POLY1305_DONNA_H */ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.c new file mode 100644 index 00000000..62acafec --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.c @@ -0,0 +1,38 @@ +/****************************************************************************** + * Filename: systick.c + * + * Description: Driver for the SysTick timer + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "systick.h" + +// See systick.h for implementation diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.h new file mode 100644 index 00000000..271317a7 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick.h @@ -0,0 +1,276 @@ +/****************************************************************************** + * Filename: systick.h + * + * Description: Prototypes for the SysTick driver. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_systick.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// API Functions and Prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to \ref SysTickSetPeriod(). +//! If an immediate reload is required, the SYSTICK_O_CVR register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SysTickEnable(void) +{ + // Enable SysTick. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) |= (SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_ENABLE); +} + +//***************************************************************************** +// +//! \brief Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SysTickDisable(void) +{ + // Disable SysTick. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) &= ~(SYSTICK_CSR_ENABLE); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SysTickRegisterInt(void (*pfnHandler)(void)) +{ + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(INT_SYSTICK, pfnHandler); + + // Enable the SysTick interrupt. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) |= SYSTICK_CSR_TICKINT; +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SysTickUnregisterInt(void) +{ + // Disable the SysTick interrupt. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) &= ~(SYSTICK_CSR_TICKINT); + + // Unregister the interrupt handler. + IntUnregister(INT_SYSTICK); +} + +//***************************************************************************** +// +//! \brief Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically when the interrupt handler +//! is called. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SysTickEnableInt(void) +{ + // Enable the SysTick interrupt. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) |= SYSTICK_CSR_TICKINT; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SysTickDisableInt(void) +{ + // Disable the SysTick interrupt. + HWREG(SYSTICK_BASE + SYSTICK_O_CSR) &= ~(SYSTICK_CSR_TICKINT); +} + +//***************************************************************************** +// +//! \brief Sets the period of the SysTick counter. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload + +//! immediately. If an immediate reload is required, the SYSTICK_O_CVR +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \c period supplied here +//! on the next clock after the SysTick is enabled. +//! +//! \param period is the number of clock ticks in each period of the +//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SysTickSetPeriod(uint32_t period) +{ + // Check the arguments. + ASSERT((period > 0) && (period <= 16777216)); + + // Set the period of the SysTick counter. + HWREG(SYSTICK_BASE + SYSTICK_O_RVR) = period - 1; +} + +//***************************************************************************** +// +//! \brief Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +__STATIC_INLINE uint32_t SysTickGetPeriod(void) +{ + // Return the period of the SysTick counter. + return (HWREG(SYSTICK_BASE + SYSTICK_O_RVR) + 1); +} + +//***************************************************************************** +// +//! \brief Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the (period - 1) and zero, both included. +//! +//! \return Returns the current value of the SysTick counter +// +//***************************************************************************** +__STATIC_INLINE uint32_t SysTickGetValue(void) +{ + // Return the current value of the SysTick counter. + return (HWREG(SYSTICK_BASE + SYSTICK_O_CVR)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group +//! @} +//! @} +// +//***************************************************************************** + +#endif // __SYSTICK_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick_doc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick_doc.h new file mode 100644 index 00000000..32193a28 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/systick_doc.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * Filename: systick_doc.h + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ +//! \addtogroup systick_api +//! @{ +//! \section sec_systick Introduction +//! +//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, +//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. +//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on +//! the next clock edge, then decrements on subsequent clocks. +//! +//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the +//! SysTick counter stops. +//! +//! When the processor is halted for debugging, the counter does not decrement. +//! +//! \section sec_systick_api API +//! +//! The API functions can be grouped like this: +//! +//! Configuration and status: +//! - \ref SysTickSetPeriod() +//! - \ref SysTickGetPeriod() +//! - \ref SysTickGetValue() +//! +//! Enable and disable: +//! - \ref SysTickEnable() +//! - \ref SysTickDisable() +//! +//! Interrupt configuration: +//! - \ref SysTickRegisterInt() +//! - \ref SysTickUnregisterInt() +//! - \ref SysTickEnableInt() +//! - \ref SysTickDisableInt() +//! @} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c new file mode 100644 index 00000000..29381fbb --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c @@ -0,0 +1,323 @@ +/****************************************************************************** + * Filename: tempdiode.c + * + * Description: Driverlib for the high accuracy temperature diode + * + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include + +#include "adc.h" +#include "hapi.h" +#include "tempdiode.h" +#include "interrupt.h" + +#include "../inc/hw_clkctl.h" +#include "../inc/hw_fcfg.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_pmud.h" +#include "../inc/hw_sys0.h" +#include "../inc/hw_types.h" + +#ifdef __IAR_SYSTEMS_ICC__ +__ramfunc static uint32_t TempDiodeRamHWREG(uint32_t address, uint32_t data); +#elif (defined(__GNUC__) || defined(__clang__)) +static uint32_t TempDiodeRamHWREG(uint32_t address, uint32_t data) __attribute__((section(".TI.ramfunc"), noinline)); +#else + #error Unsupported Compiler +#endif + +static void enableADC(void); +static int32_t voltageToTemp(uint32_t microVolts); +static int64_t int_sqrt(uint64_t n); + +/* Temporary PMUD PREFSYS register definition. */ +#ifdef PMUD_O_PREFSYS + #error "PMUD_O_PREFSYS defined in DOC release! Remove definitition below." +#endif + +#define PMUD_O_PREFSYS 0x00000080U +#define PMUD_PREFSYS_TEST2 0x00000004U + +//***************************************************************************** +// +// Writes data to register while executing from RAM +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ +__ramfunc static uint32_t TempDiodeRamHWREG(uint32_t address, uint32_t data) +{ + HWREG(address) = data; + /* Wait at least 11 us before proceeding with any flash operations */ + HapiWaitUs(11); + return HWREG(address); +} +#elif (defined(__GNUC__) || defined(__clang__)) +static uint32_t TempDiodeRamHWREG(uint32_t address, uint32_t data) +{ + HWREG(address) = data; + /* Wait at least 11 us before proceeding with any flash operations */ + HapiWaitUs(11); + return HWREG(address); +} +#else + #error Unsupported Compiler +#endif + +//***************************************************************************** +// +// Enable and configure the ADC. Parameters are the same as used during +// trim-procedure. +// +//***************************************************************************** +static void enableADC(void) +{ + /* Enable ADC peripheral */ + HWREG(CLKCTL_BASE + CLKCTL_O_CLKENSET0) = CLKCTL_CLKENSET0_ADC0; + + /* Configure ADC CTL-register 0 */ + ADCSetMemctlRange(0, 0); + + /* Set maximum sampling duration for highest accuracy */ + ADCSetSampleDuration(ADC_CLOCK_DIVIDER_48, 1023); + + /* Use 12-bit resolution */ + ADCSetResolution(ADC_RESOLUTION_12_BIT); + + /* Use internal 1.4V reference, sample on internal channel 14 (VA_ATEST1) */ + ADCSetInput(ADC_FIXED_REFERENCE_1V4, ADC_MEMCTL0_CHANSEL_CHAN_14, 0); + + /* Adjust ADC to 1.4V reference */ + ADCSetAdjustmentOffset(ADC_FIXED_REFERENCE_1V4); + + /* Perform single conversion */ + ADCSetSequence(ADC_SEQUENCE_SINGLE); +} + +//***************************************************************************** +// +// Converts a voltage (uV) measured across the diode to temperature (degC), +// with 4 fractional bits. +// +//***************************************************************************** +static int32_t voltageToTemp(uint32_t microVolts) +{ + /* The tempsense diode voltage (mV) as a function of temperature (degC) can + * be modeled as mV(T) = a*T^2 + b*T + c, where the coefficients are: + * a = -0.000324 + * b = -1.432931 + * c = 833.729920 + * + * To improve the performance we find the delta between the curve fit, and + * the measured FCFG value. The FCFG temperature is not precisely 30 degC, + * but 28.3 degC instead. + * We calculate mV(28.3) = 792.918484 mV. + * + * The device-specific curve fit function then becomes + * mV(T) = a*T^2 + b*T + c + delta, where delta = (FCFG_value - mV(28.3)) + * + * mV(T) = -0.000324*T^2 - 1.432931*T + 833.729920 + FCFG_value - 792.918484 + * + * To bring all constants from floating-point to fixed-point integers we + * multiply the entire equation by a factor 2^24. This gives good enough + * resolution, and leaves a margin before overflowing 64 bit calculations. + * The shifted coefficients become as follows: + * + * aScaled = a * 2^24 = -5436 + * bScaled = b * 2^24 = -24040593 + * cScaled = c * 2^24 = 13987666953 + * mV(28.s)Scaled = 792.918484 * 2^24 = 13302964682 + * + */ + + int64_t aScaled = -5436LL; /* -0.000324 * 2^24 */ + int64_t bScaled = -24040593LL; /* -1.432931 * 2^24 */ + int64_t cScaled = 13987666953LL; /* 833.729920 * 2^24 */ + int64_t mV28Scaled = 13302964682LL; /* mV(28.3) * 2^24 */ + + /* To find the temperature T, we solve the equation + * 0 = p2*T^2 + p1*T + p0, using the quadratic formula, where + * p2 = aScaled + * p1 = bScaled + * p0 = cScaled + fcfg_valueScaled - mV(28.s)Scaled - inputVoltageScaled + * + * T = (-p1 - sqrt(p1*p1 - 4*p2*p0)) / (2*p2) + */ + + int64_t fcfgValue = fcfg->appTrims.cc23x0r5.auxDiodeCal30C.auxDiodeVoltage - + fcfg->appTrims.cc23x0r5.auxDiodeCal30C.auxDiodeGnd; + + /* The FCFG voltage value is already left-shifted by 4, so we only shift it + * 20 more. + */ + int64_t fcfgValueScaled = fcfgValue << 20; + + /* Convert input voltage (microvolts) to scaled millivolts */ + int64_t inputVoltageScaled = (((int64_t)microVolts << 24) + 500) / 1000; + + int64_t p2 = aScaled; + int64_t p1 = bScaled; + int64_t p0 = cScaled + fcfgValueScaled - mV28Scaled - inputVoltageScaled; + + /* Apply quadratic formula, but scale numerator by a factor 16 to get 4 + * fractional bits in the temperature result. + */ + int32_t temperature = ((-p1 - int_sqrt(p1 * p1 - (4 * p2 * p0))) << 4) / (2 * p2); + + return temperature; +} + +//***************************************************************************** +// +// Reads temperature from high accuracy temperature diode with 4 fractional bits +// +//***************************************************************************** +int32_t TempDiodeGetTemp(void) +{ + uint32_t diodeVoltage = 0; + bool intAlreadyDisabled; + + /* Unlock ATESTCFG register and connect VR_ATEST to VA_ATEST */ + HWREG(SYS0_BASE + SYS0_O_ATESTCFG) = 0x5A000000 | SYS0_ATESTCFG_VR2VA1 | SYS0_ATESTCFG_VR2VA0; + + /* Disable interrupts and keep track of whether interrupts were already + * disabled or not + */ + intAlreadyDisabled = IntDisableMaster(); + + /* Connect 1uA IREF to test bus. This is done via a function executing from + * RAM, while interrupts are disabled, to ensure that no flash-operations + * are active when the reference current is enabled. + */ + TempDiodeRamHWREG(PMUD_BASE + PMUD_O_PREFSYS, PMUD_PREFSYS_TEST2); + + /* If interrupts were already disabled, then they should be left disabled. + * If interrupts were already enabled, then they should be re-enabled here. + */ + if (intAlreadyDisabled == false) + { + IntEnableMaster(); + } + + enableADC(); + + /* Measure the high side of the diode */ + HWREG(SYS0_BASE + SYS0_O_TSENSCFG) = SYS0_TSENSCFG_SEL_VALUE; + + /* Do 4 ADC conversions for averaging */ + for (uint32_t i = 0; i < 4; i++) + { + ADCManualTrigger(); + CPUDelay(3); + diodeVoltage += ADCReadResult(0); + } + + /* Measure ground (low side of the diode) */ + HWREG(SYS0_BASE + SYS0_O_TSENSCFG) = SYS0_TSENSCFG_SEL_GND; + + /* Do 4 ADC conversions for averaging */ + for (uint32_t i = 0; i < 4; i++) + { + ADCManualTrigger(); + CPUDelay(3); + diodeVoltage -= ADCReadResult(0); + } + + /* Calculate an average of the 4 readings, rounded to the nearest integer */ + diodeVoltage = (diodeVoltage + 2) >> 2; + + /* Adjust ADC value to compensate for device/reference specific gain */ + uint16_t gain = ADCGetAdjustmentGain(ADC_FIXED_REFERENCE_1V4); + diodeVoltage = ADCAdjustValueForGain(diodeVoltage, ADC_RESOLUTION_12_BIT, gain); + + /* Convert raw reading to microvolts */ + diodeVoltage = ADCValueToMicrovolts(diodeVoltage, ADC_RESOLUTION_12_BIT, 1400000); + + /* Disable ADC */ + HWREG(CLKCTL_BASE + CLKCTL_O_CLKENCLR0) = CLKCTL_CLKENCLR0_ADC0; + + /* Reset ATB */ + HWREG(SYS0_BASE + SYS0_O_ATESTCFG) = 0x5A00000F; + + /* Disable temperature diode measurement */ + HWREG(SYS0_BASE + SYS0_O_TSENSCFG) &= ~SYS0_TSENSCFG_SEL_M; + + /* Disconnect all test reference signals */ + intAlreadyDisabled = IntDisableMaster(); + TempDiodeRamHWREG(PMUD_BASE + PMUD_O_PREFSYS, 0); + if (intAlreadyDisabled == false) + { + IntEnableMaster(); + } + + return voltageToTemp(diodeVoltage); +} + +//***************************************************************************** +// +// Compute the integer square root of a number n. Method taken from: +// https://en.wikipedia.org/wiki/Methods_of_computing_square_roots#Binary_numeral_system_(base_2) +// +//***************************************************************************** +static int64_t int_sqrt(uint64_t n) +{ + /* X_n+1 */ + int64_t x = n; + + /* c_n */ + int64_t c = 0; + + /* d_n which starts at the highest power of four <= n */ + int64_t d = 0x4000000000000000LL; + + while (d > n) + { + d >>= 2; + } + + /* for d_n ... d_0 */ + while (d != 0) + { + if (x >= (c + d)) + { /* if X_m+1 ≥ Y_m then a_m = 2^m */ + x -= c + d; /* X_m = X_m+1 - Y_m */ + c = (c >> 1) + d; /* c_m-1 = c_m/2 + d_m (a_m is 2^m) */ + } + else + { + c >>= 1; /* c_m-1 = c_m/2. (a_m is 0) */ + } + d >>= 2; /* d_m-1 = d_m/4 */ + } + + return c; /* c_-1 */ +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.h new file mode 100644 index 00000000..cf18b2e1 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * Filename: tempdiode.h + * + * Description: Defines and prototypes for reading the high accuracy temperature diode + * + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __tempdiode_H__ +#define __tempdiode_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup tempdiode_api +//! @{ +// +//***************************************************************************** + +#include + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads temperature from high accuracy temperature diode +//! +//! This function reads the temperature from the high-accuracy temperature diode +//! The returned result contains 4 fractional bits. For example: +//! 0x00000200 = +32.0000 degC +//! 0x0000020C = +32.7500 degC +//! 0xFFFFFEC3 = -19.8125 degC +//! +//! \warning This function uses the SoC ADC to measure the temperature. This +//! function must not be called while the ADC driver is active, or the SoC ADC +//! is open. +//! +//! \warning This function uses the internal test-bus (ATEST) to measure the +//! temperature. The test-bus must not be used when calling this function. +//! +//! \note Due to long and repeated ADC sampling, this function takes +//! roughly 8 milliseconds to execute. +//! +//! \return Ambient temperature in degrees Celcius, with 4 fractional bits +// +//***************************************************************************** +extern int32_t TempDiodeGetTemp(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __tempdiode_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c new file mode 100644 index 00000000..5638a3a6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c @@ -0,0 +1,107 @@ +/****************************************************************************** + * Filename: uart.c + * + * Description: Driver for the UART peripheral. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "uart.h" + +//***************************************************************************** +// +// Sets the configuration of a UART +// +//***************************************************************************** +void UARTConfigSetExpClk(uint32_t base, uint32_t UARTClkFreq, uint32_t baudFreq, uint32_t config) +{ + uint32_t div; + + // Check the arguments. + ASSERT(baudFreq != 0); + + // Stop the UART. + UARTDisable(base); + + // Compute the fractional baud rate divider. + div = (((UARTClkFreq * 8) / baudFreq) + 1) / 2; + + // Set the baud rate. + HWREG(base + UART_O_IBRD) = div / 64; + HWREG(base + UART_O_FBRD) = div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(base + UART_O_LCRH) = config; +} + +//***************************************************************************** +// +// Disables transmitting and receiving +// +//***************************************************************************** +void UARTDisable(uint32_t base) +{ + // Wait for end of TX. + while (HWREG(base + UART_O_FR) & UART_FR_BUSY) {} + + // Disable the FIFO. + HWREG(base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE); +} + +//***************************************************************************** +// +// Blocks until a character is available, and returns it +// +//***************************************************************************** +uint8_t UARTGetChar(uint32_t base) +{ + // Wait until a char is available. + while (HWREG(base + UART_O_FR) & UART_FR_RXFE) {} + + // Return the character. + return (HWREG(base + UART_O_DR)); +} + +//***************************************************************************** +// +// Blocks until there is space in the data register, and writes a byte to it +// +//***************************************************************************** +void UARTPutChar(uint32_t base, uint8_t data) +{ + // Wait until space is available. + while (HWREG(base + UART_O_FR) & UART_FR_TXFF) {} + + // Send the char. + HWREG(base + UART_O_DR) = data; +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h new file mode 100644 index 00000000..958d53f3 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h @@ -0,0 +1,730 @@ + +/****************************************************************************** + * Filename: uart.h + * + * Description: Defines and prototypes for the UART peripheral. + * + * Copyright (c) 2022-2024 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTEnableInt, UARTDisableInt, and UARTClearInt +// as the intFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_EOT (UART_IMSC_EOT) //!< End Of Transmission Interrupt Mask +#define UART_INT_OE (UART_IMSC_OE) //!< Overrun Error Interrupt Mask +#define UART_INT_BE (UART_IMSC_BE) //!< Break Error Interrupt Mask +#define UART_INT_PE (UART_IMSC_PE) //!< Parity Error Interrupt Mask +#define UART_INT_FE (UART_IMSC_FE) //!< Framing Error Interrupt Mask +#define UART_INT_RT (UART_IMSC_RT) //!< Receive Timeout Interrupt Mask +#define UART_INT_RX (UART_IMSC_RX) //!< Receive Interrupt Mask +#define UART_INT_TX (UART_IMSC_TX) //!< Transmit Interrupt Mask +#define UART_INT_CTS (UART_IMSC_CTSM) //!< CTS Modem Interrupt Mask +#define UART_INT_TXDMADONE (UART_IMSC_TXDMADONE) //!< Tx DMA done interrupt mask +#define UART_INT_RXDMADONE (UART_IMSC_RXDMADONE) //!< Rx DMA done interrupt mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the config parameter +// and returned by UARTConfigGetExpClk in the pconfig parameter. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 //!< Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 //!< 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 //!< 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 //!< 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 //!< 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 //!< Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 //!< One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 //!< Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 //!< Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 //!< No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 //!< Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 //!< Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 //!< Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 //!< Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTSetFifoLevel as the txLevel parameter +// +//***************************************************************************** +#define UART_FIFO_TX2_8 0x00000001 //!< Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 //!< Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 //!< Transmit interrupt at 3/4 Full + +//***************************************************************************** +// +// Values that can be passed to UARTSetFifoLevel as the rxLevel parameter +// +//***************************************************************************** +#define UART_FIFO_RX2_8 0x00000008 //!< Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 //!< Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 //!< Receive interrupt at 3/4 Full + +//***************************************************************************** +// +// Values that can be passed to UARTEnableDMA() and UARTDisableDMA(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 //!< Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 //!< Enable DMA for transmit +#define UART_DMA_RX 0x00000001 //!< Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTGetRxError(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the FIFO level at which interrupts are generated. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param base is the base address of the UART port. +//! \param txLevel is the transmit FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! \param rxLevel is the receive FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTSetFifoLevel(uint32_t base, uint32_t txLevel, uint32_t rxLevel) +{ + // Check the arguments. + ASSERT((txLevel == UART_FIFO_TX2_8) || (txLevel == UART_FIFO_TX4_8) || (txLevel == UART_FIFO_TX6_8)); + ASSERT((rxLevel == UART_FIFO_RX2_8) || (rxLevel == UART_FIFO_RX4_8) || (rxLevel == UART_FIFO_RX6_8)); + + // Set the FIFO interrupt levels. + HWREG(base + UART_O_IFLS) = txLevel | rxLevel; +} + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! This function configures the UART for operation in the specified data +//! format. +//! +//! \param base is the base address of the UART port. +//! \param UARTClkFreq is the rate of the clock supplied to the UART module. +//! \param baudFreq is the desired baud rate. +//! - Minimum baud rate: baudFreq >= ceil(UARTClkFreq / 1,048,559.875) +//! - Maximum baud rate: baudFreq <= floor(UARTClkFreq / 15.875) +//! \param config is the data format for the port. +//! The parameter is the bitwise OR of three values: +//! - Number of data bits +//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. +//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. +//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. +//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. +//! - Number of stop bits +//! - \ref UART_CONFIG_STOP_ONE : One stop bit. +//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. +//! - Parity +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigSetExpClk(uint32_t base, uint32_t UARTClkFreq, uint32_t baudFreq, uint32_t config); + +//***************************************************************************** +// +//! \brief Disables transmitting and receiving. +//! +//! This function waits until all data in the TX FIFO has been transmitted, +//! and then clears the UARTEN, TXE, and RXE bits, and disables the FIFO. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTDisable(uint32_t base); + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTEnableFifo(uint32_t base) +{ + // Enable the FIFO. + HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTDisableFIFO(uint32_t base) +{ + // Disable the FIFO. + HWREG(base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \param base is the base address of the UART port. +//! +//! \return Returns status of the receive FIFO. +//! - \c true : There is data in the receive FIFO. +//! - \c false : There is no data in the receive FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool UARTCharAvailable(uint32_t base) +{ + // Return the availability of characters. + return ((HWREG(base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \note The \ref UARTCharAvailable() function should be called before +//! attempting to call this function. +//! +//! \param[in] base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port +//! +//! \sa \ref UARTCharAvailable() +// +//***************************************************************************** +__STATIC_INLINE uint8_t UARTGetCharNonBlocking(uint32_t base) +{ + // Return a character from the data register + return (HWREGB(base + UART_O_DR)); +} + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \param base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port +// +//***************************************************************************** +extern uint8_t UARTGetChar(uint32_t base); + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \param base is the base address of the UART port. +//! +//! \return Returns status of the transmit FIFO. +//! - \c true : There is space available in the transmit FIFO. +//! - \c false : There is no space available in the transmit FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool UARTSpaceAvailable(uint32_t base) +{ + // Return the availability of space. + return ((HWREG(base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! This function writes the character \c data to the transmit FIFO for the +//! specified port. +//! +//! \note The \ref UARTSpaceAvailable() function should be called before +//! attempting to call this function. +//! +//! \param base is the base address of the UART port. +//! \param data is the character to be transmitted. +//! +//! \return None +//! +//! \sa \ref UARTSpaceAvailable() +// +//***************************************************************************** +__STATIC_INLINE void UARTPutCharNonBlocking(uint32_t base, uint8_t data) +{ + // Write this character to the transmit FIFO. + HWREG(base + UART_O_DR) = data; +} + +//***************************************************************************** +// +//! \brief Waits to send a character to the specified port. +//! +//! This function sends the character \c data to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \param base is the base address of the UART port. +//! \param data is the character to be transmitted. +//! +//! \return None +// +//***************************************************************************** +extern void UARTPutChar(uint32_t base, uint8_t data); + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \param base is the base address of the UART port. +//! +//! \return Returns status of UART transmitter. +//! - \c true : UART is transmitting. +//! - \c false : All transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool UARTBusy(uint32_t base) +{ + // Determine if the UART is busy. + return ((HWREG(base + UART_O_FR) & UART_FR_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param base is the base address of the UART port. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! - \ref UART_INT_TXDMADONE : TX DMA Done interrupt. +//! - \ref UART_INT_RXDMADONE : RX DMA Done interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTEnableInt(uint32_t base, uint32_t intFlags) +{ + // Enable the specified interrupts. + HWREG(base + UART_O_IMSC) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param base is the base address of the UART port. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! - \ref UART_INT_TXDMADONE : TX DMA Done interrupt. +//! - \ref UART_INT_RXDMADONE : RX DMA Done interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTDisableInt(uint32_t base, uint32_t intFlags) +{ + // Disable the specified interrupts. + HWREG(base + UART_O_IMSC) &= ~(intFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param base is the base address of the UART port. +//! \param masked selects either raw or masked interrupt. +//! - \c true : Masked interrupt status is required. +//! - \c false : Raw interrupt status is required. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! - \ref UART_INT_TXDMADONE : TX DMA Done interrupt. +//! - \ref UART_INT_RXDMADONE : RX DMA Done interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t UARTIntStatus(uint32_t base, bool masked) +{ + // Return either the interrupt status or the raw interrupt status as + // requested. + if (masked) + { + return (HWREG(base + UART_O_MIS)); + } + else + { + return (HWREG(base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any +//! synchronizers) +//! +//! \param base is the base address of the UART port. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! - \ref UART_INT_TXDMADONE : TX DMA Done interrupt. +//! - \ref UART_INT_RXDMADONE : RX DMA Done interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTClearInt(uint32_t base, uint32_t intFlags) +{ + // Clear the requested interrupt sources + HWREG(base + UART_O_ICR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Enable UART DMA operation. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \param base is the base address of the UART port. +//! \param dmaFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTEnableDMA(uint32_t base, uint32_t dmaFlags) +{ + // Set the requested bits in the UART DMA control register. + HWREG(base + UART_O_DMACTL) |= dmaFlags; +} + +//***************************************************************************** +// +//! \brief Disable UART DMA operation. +//! +//! This function is used to disable UART DMA features that were enabled +//! by \ref UARTEnableDMA(). The specified UART DMA features are disabled. +//! +//! \param base is the base address of the UART port. +//! \param dmaFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTDisableDMA(uint32_t base, uint32_t dmaFlags) +{ + // Clear the requested bits in the UART DMA control register. + HWREG(base + UART_O_DMACTL) &= ~dmaFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to \ref UARTGetChar() or \ref UARTGetCharNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \param base is the base address of the UART port. +//! +//! \return Returns a bitwise OR combination of the receiver error flags: +//! - \ref UART_RXERROR_FRAMING +//! - \ref UART_RXERROR_PARITY +//! - \ref UART_RXERROR_BREAK +//! - \ref UART_RXERROR_OVERRUN +// +//***************************************************************************** +__STATIC_INLINE uint32_t UARTGetRxError(uint32_t base) +{ + // Return the current value of the receive status register. + return (HWREG(base + UART_O_RSR_ECR) & 0x0000000F); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! This function is used to clear all receiver error conditions reported via +//! \ref UARTGetRxError(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTClearRxError(uint32_t base) +{ + // Any write to the Error Clear Register will clear all bits which are + // currently set. + HWREG(base + UART_O_RSR_ECR) = 0; +} + +//***************************************************************************** +// +//! \brief Enable CTS flow control +//! +//! Hardware flow control is disabled by default. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTEnableCTS(uint32_t base) +{ + HWREG(base + UART_O_CTL) |= (UART_CTL_CTSEN); +} + +//***************************************************************************** +// +//! \brief Enable RTS flow control +//! +//! Hardware flow control is disabled by default. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTEnableRTS(uint32_t base) +{ + HWREG(base + UART_O_CTL) |= (UART_CTL_RTSEN); +} + +//***************************************************************************** +// +//! \brief Disable CTS flow control +//! +//! Hardware flow control is disabled by default. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTDisableCTS(uint32_t base) +{ + HWREG(base + UART_O_CTL) &= ~(UART_CTL_CTSEN); +} + +//***************************************************************************** +// +//! \brief Disable RTS flow control +//! +//! Hardware flow control is disabled by default. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void UARTDisableRTS(uint32_t base) +{ + HWREG(base + UART_O_CTL) &= ~(UART_CTL_RTSEN); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __UART_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.c new file mode 100644 index 00000000..932b39bf --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.c @@ -0,0 +1,326 @@ +/****************************************************************************** + * Filename: udma.c + * + * Description: Driver for the uDMA controller + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "udma.h" + +//***************************************************************************** +// +// Enables attributes of a uDMA channel +// +//***************************************************************************** +void uDMAEnableChannelAttribute(uint32_t channelBitMask, uint32_t attr) +{ + // Check the arguments. + ASSERT((attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in attr. + if (attr & UDMA_ATTR_USEBURST) + { + HWREG(DMA_BASE + DMA_O_SETBURST) = channelBitMask; + } + + // Set the request mask bit for this channel, if set in attr. + if (attr & UDMA_ATTR_REQMASK) + { + HWREG(DMA_BASE + DMA_O_SETREQMASK) = channelBitMask; + } + + // Set the alternate control select bit for this channel, + // if set in attr. + if (attr & UDMA_ATTR_ALTSELECT) + { + HWREG(DMA_BASE + DMA_O_SETCHNLPRIALT) = channelBitMask; + } + + // Set the high priority bit for this channel, if set in attr. + if (attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(DMA_BASE + DMA_O_SETCHNLPRIORITY) = channelBitMask; + } +} + +//***************************************************************************** +// +// Disables attributes of a uDMA channel +// +//***************************************************************************** +void uDMADisableChannelAttribute(uint32_t channelBitMask, uint32_t attr) +{ + // Check the arguments. + ASSERT((attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in attr. + if (attr & UDMA_ATTR_USEBURST) + { + HWREG(DMA_BASE + DMA_O_CLEARBURST) = channelBitMask; + } + + // Clear the request mask bit for this channel, if set in attr. + if (attr & UDMA_ATTR_REQMASK) + { + HWREG(DMA_BASE + DMA_O_CLEARREQMASK) = channelBitMask; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if (attr & UDMA_ATTR_ALTSELECT) + { + HWREG(DMA_BASE + DMA_O_CLEARCHNLPRIALT) = channelBitMask; + } + + // Clear the high priority bit for this channel, if set in attr. + if (attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(DMA_BASE + DMA_O_CLEARCHNLPRIORITY) = channelBitMask; + } +} + +//***************************************************************************** +// +// Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t uDMAGetChannelAttribute(uint32_t channelBitMask) +{ + uint32_t attr = 0; + + // Check to see if useburst bit is set for this channel. + if (HWREG(DMA_BASE + DMA_O_SETBURST) & (channelBitMask)) + { + attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if (HWREG(DMA_BASE + DMA_O_SETCHNLPRIALT) & (channelBitMask)) + { + attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if (HWREG(DMA_BASE + DMA_O_SETCHNLPRIORITY) & (channelBitMask)) + { + attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if (HWREG(DMA_BASE + DMA_O_SETREQMASK) & (channelBitMask)) + { + attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return (attr); +} + +//***************************************************************************** +// +// Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void uDMASetChannelControl(volatile uDMAControlTableEntry *pChannelControlStruct, uint32_t control) +{ + // Check the arguments. + ASSERT(HWREG(DMA_BASE + DMA_O_CTRL) != 0); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pChannelControlStruct->control = ((pChannelControlStruct->control & + ~(UDMA_DST_INC_M | UDMA_SRC_INC_M | UDMA_SIZE_M | UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + control); +} + +//***************************************************************************** +// +// Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void uDMASetChannelTransfer(volatile uDMAControlTableEntry *pChannelControlStruct, + uint32_t mode, + void *pSrcAddr, + void *pDstAddr, + uint32_t transferSize) +{ + uint32_t controlTableAddr; + uint32_t control; + uint32_t incValue; + uint32_t bufferBytes; + uint32_t channelStructIndex; + + // Check the arguments. + ASSERT(HWREG(DMA_BASE + DMA_O_CTRL) != 0); + ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((transferSize != 0) && (transferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + controlTableAddr = HWREG(DMA_BASE + DMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + control = (pChannelControlStruct->control & ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Evaluate if the received table is a primary or alternate control table. + // To do this, calculate the index of the received control table among the + // entire control table array. This is the offset between the received table + // and the base address of the control table, divided by the size of the single + // control table block (16B). + channelStructIndex = (((uint32_t)pChannelControlStruct) - controlTableAddr) >> 4; + + // Adjust the mode if the alt control structure is selected. + if (channelStructIndex & UDMA_ALT_SELECT) + { + if ((mode == UDMA_MODE_MEM_SCATTER_GATHER) || (mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + control |= mode | ((transferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + incValue = (control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if (incValue != UDMA_SRC_INC_NONE) + { + incValue = incValue >> UDMA_SRC_INC_S; + bufferBytes = transferSize << incValue; + pSrcAddr = (void *)((uint32_t)pSrcAddr + bufferBytes - (1 << incValue)); + } + + // Load the source ending address into the control block. + pChannelControlStruct->pSrcEndAddr = pSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + incValue = control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if (incValue != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if ((mode == UDMA_MODE_MEM_SCATTER_GATHER) || (mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + if (channelStructIndex & UDMA_ALT_SELECT) + { + pDstAddr = (void *)&(pChannelControlStruct->spare); + } + else + { + pDstAddr = (void *)&pChannelControlStruct[UDMA_ALT_SELECT].spare; + } + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + incValue = incValue >> UDMA_DST_INC_S; + bufferBytes = transferSize << incValue; + pDstAddr = (void *)((uint32_t)pDstAddr + bufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pChannelControlStruct->pDstEndAddr = pDstAddr; + + // Write the new control word value. + pChannelControlStruct->control = control; +} + +//***************************************************************************** +// +// Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t uDMAGetChannelSize(volatile uDMAControlTableEntry const *pChannelControlStruct) +{ + uint32_t control; + + // Check the arguments. + ASSERT(HWREG(DMA_BASE + DMA_O_CTRL) != 0); + + // Get the current control word value and mask off all but the size field + // and the mode field. + control = (pChannelControlStruct->control & (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if (control == 0) + { + return (0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return ((control >> UDMA_XFER_SIZE_S) + 1); + } +} + +//***************************************************************************** +// +// Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t uDMAGetChannelMode(volatile uDMAControlTableEntry const *pChannelControlStruct) +{ + uint32_t control; + + // Check the arguments. + ASSERT(HWREG(DMA_BASE + DMA_O_CTRL) != 0); + + // Get the current control word value and mask off all but the mode field. + control = (pChannelControlStruct->control & UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return (control); +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.h new file mode 100644 index 00000000..7a8dcfd8 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/udma.h @@ -0,0 +1,956 @@ +/****************************************************************************** + * Filename: udma.h + * + * Description: Defines and prototypes for the uDMA controller. + * + * Copyright (c) 2022 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_dma.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! \brief A structure that defines an entry in the channel control table. +//! +//! These fields are used by the uDMA controller and normally it is not necessary for +//! software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + volatile void *pSrcEndAddr; //!< The ending source address of the data transfer. + volatile void *pDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t control; //!< The channel control mode. + volatile uint32_t spare; //!< An unused location. +} uDMAControlTableEntry; + +//***************************************************************************** +// +//! \brief A helper macro for building scatter-gather task table entries. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of uDMAControlTableEntry type, like this: +//! +/*! +\verbatim + uDMAControlTableEntry MyTaskList[] = + { + uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, + UDMA_SRC_INC_8, MySourceBuf, + UDMA_DST_INC_8, MyDestBuf, + UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), + uDMATaskStructEntry(Task2Count, ... ), + } +\endverbatim +*/ +//! \param transferCount is the count of items to transfer for this task. +//! It must be in the range 1-1024. +//! \param itemSize is the bit size of the items to transfer for this task. +//! It must be one of: +//! - \ref UDMA_SIZE_8 +//! - \ref UDMA_SIZE_16 +//! - \ref UDMA_SIZE_32 +//! \param srcIncrement is the bit size increment for source data. +//! It must be one of: +//! - \ref UDMA_SRC_INC_8 +//! - \ref UDMA_SRC_INC_16 +//! - \ref UDMA_SRC_INC_32 +//! - \ref UDMA_SRC_INC_NONE +//! \param pSrcAddr is the starting address of the data to transfer. +//! \param dstIncrement is the bit size increment for destination data. +//! It must be one of: +//! - \ref UDMA_DST_INC_8 +//! - \ref UDMA_DST_INC_16 +//! - \ref UDMA_DST_INC_32 +//! - \ref UDMA_DST_INC_NONE +//! \param pDstAddr is the starting address of the destination data. +//! \param arbSize is the arbitration size to use for the transfer task. +//! This is used to select the arbitration size in powers of 2, from 1 to 1024. +//! It must be one of: +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - ... +//! - \ref UDMA_ARB_1024 +//! \param mode is the transfer mode for this task. +//! Note that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! It must be one of: +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +//! +//! \return None (this is not a function) +// +//***************************************************************************** +#define uDMATaskStructEntry(transferCount, itemSize, srcIncrement, pSrcAddr, dstIncrement, pDstAddr, arbSize, mode) \ + { \ + (((srcIncrement) == UDMA_SRC_INC_NONE) \ + ? (pSrcAddr) \ + : ((void *)(&((uint8_t *)(pSrcAddr))[((transferCount) << ((srcIncrement) >> 26)) - 1]))), \ + (((dstIncrement) == UDMA_DST_INC_NONE) \ + ? (pDstAddr) \ + : ((void *)(&((uint8_t *)(pDstAddr))[((transferCount) << ((dstIncrement) >> 30)) - 1]))), \ + (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) | (((transferCount)-1) << 4) | \ + ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) || ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) \ + ? (mode) | UDMA_MODE_ALT_SELECT \ + : (mode)), \ + 0 \ + } + +//***************************************************************************** +// +// The hardware configured number of uDMA channels. +// +//***************************************************************************** +#define UDMA_NUM_CHANNELS 8 + +//***************************************************************************** +// +// The level of priority for the uDMA channels +// +//***************************************************************************** +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 + +//***************************************************************************** +// +// Flags that can be passed to uDMAEnableChannelAttribute(), +// uDMADisableChannelAttribute(), and returned from uDMAGetChannelAttribute(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMASetChannelTransfer() and returned +// from uDMAGetChannelMode(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER 0x00000006 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMASetChannelControl(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. On CC23x0 each uDMA channel is multiplexed between two different +// peripherals. The 1-to-1 mapping between UDMA channel and peripheral must be +// decided by the user and set in the event fabric registers EVTSVT.DMACH[x]SEL. +// The two valid peripherals for each channel are listed next to each channel's +// mask definition. +// +//***************************************************************************** +#define UDMA_CHANNEL_0_M 0x01 //!< UDMA channel 0 (SSI0_TX or UART0_RX) +#define UDMA_CHANNEL_1_M 0x02 //!< UDMA channel 1 (SSI0_RX or UART0_TX) +#define UDMA_CHANNEL_2_M 0x04 //!< UDMA channel 2 (LRFD or UART0_TX) +#define UDMA_CHANNEL_3_M 0x08 //!< UDMA channel 3 (ADC0 or UART0_RX) +#define UDMA_CHANNEL_4_M 0x10 //!< UDMA channel 4 (AES_A or LRFD) +#define UDMA_CHANNEL_5_M 0x20 //!< UDMA channel 5 (AES_B or ADC0) +#define UDMA_CHANNEL_6_M 0x40 //!< UDMA channel 6 (Software Event Channel 0) +#define UDMA_CHANNEL_7_M 0x80 //!< UDMA channel 7 (Software Event Channel 1) + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000008 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAEnable(void) +{ + // Set the master enable bit in the config register. + HWREG(DMA_BASE + DMA_O_CFG) = DMA_CFG_MASTERENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with \ref uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void uDMADisable(void) +{ + // Clear the master enable bit in the config register. + HWREG(DMA_BASE + DMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +__STATIC_INLINE uint32_t uDMAGetErrorStatus(void) +{ + // Return the uDMA error status. + return (HWREG(DMA_BASE + DMA_O_ERROR)); +} + +//***************************************************************************** +// +//! \brief Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAClearErrorStatus(void) +{ + // Clear the uDMA error interrupt. + HWREG(DMA_BASE + DMA_O_ERROR) = DMA_ERROR_STATUS; +} + +//***************************************************************************** +// +//! \brief Enables a uDMA channel for operation. +//! +//! This function enables the specified uDMA channels for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! \param channelBitMask is the bitmask of the channels to enable. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAEnableChannel(uint32_t channelBitMask) +{ + HWREG(DMA_BASE + DMA_O_SETCHANNELEN) = channelBitMask; +} + +//***************************************************************************** +// +//! \brief Disables a uDMA channel for operation. +//! +//! This function disables the specified uDMA channels. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! \ref uDMAEnableChannel(). +//! +//! \param channelBitMask is the bitmask of the channels to disable. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void uDMADisableChannel(uint32_t channelBitMask) +{ + HWREG(DMA_BASE + DMA_O_CLEARCHANNELEN) = channelBitMask; +} + +//***************************************************************************** +// +//! \brief Checks if a uDMA channel is enabled for operation. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. Note that if multiple +//! channels are specified in the bitmask, the return value will be true if at +//! least one channel is enabled. +//! +//! \param channelBitMask is the bitmask of the channel to check. +//! +//! \return Returns status of uDMA channel. +//! - \c true : Channel is enabled. +//! - \c false : Channel is disabled. +// +//***************************************************************************** +__STATIC_INLINE bool uDMAIsChannelEnabled(uint32_t channelBitMask) +{ + return ((HWREG(DMA_BASE + DMA_O_SETCHANNELEN) & (channelBitMask)) ? true : false); +} + +//***************************************************************************** +// +//! \brief Sets the base address for the channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! Setting the base address of the primary control table will automatically +//! set the address for the alternate control table as the next memory +//! location after the primary control table. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \note This register cannot be read when the controller is in the reset +//! state. +//! +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. The address must be an absolute address +//! in system memory space. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMASetControlBase(void *pControlTable) +{ + // Check the arguments. + ASSERT(((uint32_t)pControlTable & ~0x3FF) == (uint32_t)pControlTable); + ASSERT((uint32_t)pControlTable >= SRAM_BASE); + + // Program the base address into the register. + HWREG(DMA_BASE + DMA_O_CTRL) = (uint32_t)pControlTable; +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +__STATIC_INLINE void *uDMAGetControlBase(void) +{ + // Read the current value of the control base register, and return it to + // the caller. + return ((void *)HWREG(DMA_BASE + DMA_O_CTRL)); +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +__STATIC_INLINE void *uDMAGetControlAlternateBase(void) +{ + // Read the current value of the control base register, and return it to + // the caller. + return ((void *)HWREG(DMA_BASE + DMA_O_ALTCTRL)); +} + +//***************************************************************************** +// +//! \brief Requests a uDMA channel to start a transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! \note If the channel is a software channel and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \param channelBitMask is the bitmask of the channel on which to request a +//! uDMA transfer. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void uDMARequestChannel(uint32_t channelBitMask) +{ + // Set the bit for this channel in the software uDMA request register. + HWREG(DMA_BASE + DMA_O_SOFTREQ) = channelBitMask; +} + +//***************************************************************************** +// +//! \brief Enables attributes of a uDMA channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! \param channelBitMask is bitmask of the channel to configure. +//! \param attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAEnableChannelAttribute(uint32_t channelBitMask, uint32_t attr); + +//***************************************************************************** +// +//! \brief Disables attributes of an uDMA channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! \param channelBitMask is bitmask of the channel to configure. +//! \param attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMADisableChannelAttribute(uint32_t channelBitMask, uint32_t attr); + +//***************************************************************************** +// +//! \brief Gets the enabled attributes of a uDMA channel. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \param channelBitMask is the bitmask of the channel to configure. +//! +//! \return Returns the bitwise OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +extern uint32_t uDMAGetChannelAttribute(uint32_t channelBitMask); + +//***************************************************************************** +// +//! \brief Sets the control parameters for a uDMA channel control structure. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \param pChannelControlStruct is a pointer to the primary or alternate +//! control table of the uDMA channel to be set. +//! \param control is the bitwise OR of five values: +//! - Data size +//! - \ref UDMA_SIZE_8 : 8 bits. +//! - \ref UDMA_SIZE_16 : 16 bits. +//! - \ref UDMA_SIZE_32 : 32 bits. +//! - Source address increment +//! - \ref UDMA_SRC_INC_8 : 8 bits. +//! - \ref UDMA_SRC_INC_16 : 16 bits. +//! - \ref UDMA_SRC_INC_32 : 32 bits. +//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. +//! - Destination address increment +//! - \ref UDMA_DST_INC_8 : 8 bits. +//! - \ref UDMA_DST_INC_16 : 16 bits. +//! - \ref UDMA_DST_INC_32 : 32 bits. +//! - \ref UDMA_DST_INC_NONE : Non-incrementing. +//! - Arbitration size. Determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. In power of 2. +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - \ref UDMA_ARB_8 +//! - ... +//! - \ref UDMA_ARB_1024 +//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. +//! - \ref UDMA_NEXT_USEBURST +//! +//! \return None +// +//***************************************************************************** +extern void uDMASetChannelControl(volatile uDMAControlTableEntry *pChannelControlStruct, uint32_t control); + +//***************************************************************************** +// +//! \brief Sets the transfer parameters for a uDMA channel control structure. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! \ref uDMASetChannelControl() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \c pSrcAddr and \c pDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will recognize from the address of the +//! \c pChannelControlStruct if it's a primary or alternate control structure and +//! will set the scatter/gather mode as appropriate for it. +//! +//! The channel must also be enabled using \ref uDMAEnableChannel() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that \ref uDMAEnableChannel() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the \ref uDMAGetChannelMode() returns \ref UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The \ref uDMAGetChannelMode() function will return \ref UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \param pChannelControlStruct is a pointer to the primary or alternate +//! control table of the uDMA channel to be set. +//! \param mode is the type of uDMA transfer. +//! The parameter should be one of the following values: +//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. +//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. +//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. +//! \param pSrcAddr is the source address for the transfer. +//! \param pDstAddr is the destination address for the transfer. +//! \param transferSize is the number of data items to transfer (\b NOT bytes). +//! +//! \return None +// +//***************************************************************************** +extern void uDMASetChannelTransfer(volatile uDMAControlTableEntry *pChannelControlStruct, + uint32_t mode, + void *pSrcAddr, + void *pDstAddr, + uint32_t transferSize); + +//***************************************************************************** +// +//! \brief Gets the current transfer size for a uDMA channel control structure. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! \param pChannelControlStruct is a pointer to the primary or alternate +//! control table of the uDMA channel in use. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +extern uint32_t uDMAGetChannelSize(volatile uDMAControlTableEntry const *pChannelControlStruct); + +//***************************************************************************** +// +//! \brief Gets the transfer mode for a uDMA channel control structure. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \ref UDMA_MODE_STOP. +//! +//! \param pChannelControlStruct is a pointer to the primary or alternate +//! control table of the uDMA channel in use. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: +//! - \ref UDMA_MODE_STOP +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_PINGPONG +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +// +//***************************************************************************** +extern uint32_t uDMAGetChannelMode(volatile uDMAControlTableEntry const *pChannelControlStruct); + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! software channel is used. The interrupts for each peripheral channel are +//! handled through the individual peripheral interrupt handlers. +//! +//! \param intChannel specifies which uDMA interrupt is to be registered. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void uDMARegisterInt(uint32_t intChannel, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(pfnHandler); + ASSERT(intChannel == INT_DMA_DONE_COMB); + + // Register the interrupt handler. + IntRegister(intChannel, pfnHandler); + + // Enable the memory management fault. + IntEnable(intChannel); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. +//! +//! \param intChannel specifies which uDMA interrupt to unregister. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void uDMAUnregisterInt(uint32_t intChannel) +{ + // Check the arguments. + ASSERT(intChannel == INT_DMA_DONE_COMB); + + // Disable the interrupt. + IntDisable(intChannel); + + // Unregister the interrupt handler. + IntUnregister(intChannel); +} + +//***************************************************************************** +// +//! \brief Clears uDMA interrupt done status. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \c channelBitMask. There is one bit for each channel. If a a bit +//! is set in \c channelBitMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \param channelBitMask is a mask with one bit for each uDMA channel. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAClearInt(uint32_t channelBitMask) +{ + // Clear the requested bits in the uDMA interrupt status register. + HWREG(DMA_BASE + DMA_O_REQDONE) = channelBitMask; +} + +//***************************************************************************** +// +//! \brief Get the uDMA interrupt status. +//! +//! This function returns the interrupt status for the specified UDMA. This +//! function does not differentiate between software or hardware activated +//! interrupts. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t uDMAIntStatus(void) +{ + // Return the uDMA interrupt status register. + return (HWREG(DMA_BASE + DMA_O_REQDONE)); +} + +//***************************************************************************** +// +//! \brief Enable interrupt on software event driven uDMA transfers. +//! +//! \note The main purpose of this function is to prevent propagation of uDMA +//! status signals to a peripheral, if a peripheral and a software event is +//! sharing the uDMA channel. If it is desired to initiate a transfer by +//! writing to a register inside the uDMA (this means a software driven +//! channel), then the uDMA status signals propagation need to be blocked to +//! the hardware peripherals. +//! +//! \param intChannel identifies which uDMA interrupt to enable software +//! interrupts for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAEnableSwEventInt(uint32_t intChannel) +{ + // Check the arguments. + ASSERT(intChannel < UDMA_NUM_CHANNELS); + + // Enable the channel. + HWREG(DMA_BASE + DMA_O_DONEMASK) |= intChannel; +} + +//***************************************************************************** +// +//! \brief Disable interrupt on software event driven uDMA transfers. +//! +//! This register disables the blocking of the uDMA status signals propagation +//! to the hardware peripheral connected to the uDMA on the \c intChannel. +//! +//! \param intChannel identifies which uDMA interrupt to disable software +//! interrupts for. +//! +//! \return None +//! +//! \sa \ref uDMAEnableSwEventInt() +// +//***************************************************************************** +__STATIC_INLINE void uDMADisableSwEventInt(uint32_t intChannel) +{ + // Check the arguments. + ASSERT(intChannel < UDMA_NUM_CHANNELS); + + // Disable the SW channel. + HWREG(DMA_BASE + DMA_O_DONEMASK) &= ~intChannel; +} + +//***************************************************************************** +// +//! \brief Return the status of the uDMA module. +//! +//! \note This status register cannot be read when the controller is in the reset state. +//! +//! \return Current status of the uDMA module. +// +//***************************************************************************** +__STATIC_INLINE uint32_t uDMAGetStatus(void) +{ + // Read and return the status register. + return HWREG(DMA_BASE + DMA_O_STATUS); +} + +//***************************************************************************** +// +//! \brief Set the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To reset a channel +//! priority to the default value use \ref uDMAClearChannelPriority(). +//! +//! \param channelBitMask is bitmask of the uDMA channel to set the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMASetChannelPriority(uint32_t channelBitMask) +{ + // Set the channel priority to high. + HWREG(DMA_BASE + DMA_O_SETCHNLPRIORITY) = channelBitMask; +} + +//***************************************************************************** +// +//! \brief Get the priority of a uDMA channel. +//! +//! \param channelBitMask The bitmask of the uDMA channel to get the priority for. +//! +//! \return Returns one of: +//! - \ref UDMA_PRIORITY_HIGH +//! - \ref UDMA_PRIORITY_LOW +// +//***************************************************************************** +__STATIC_INLINE bool uDMAGetChannelPriority(uint32_t channelBitMask) +{ + // Return the channel priority. + return (HWREG(DMA_BASE + DMA_O_SETCHNLPRIORITY) & (channelBitMask) ? UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); +} + +//***************************************************************************** +// +//! \brief Clear the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To set a channel +//! priority to high use \ref uDMASetChannelPriority(). +//! +//! \param channelBitMask The bitmask of the uDMA channel to clear the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void uDMAClearChannelPriority(uint32_t channelBitMask) +{ + // Clear the channel priority. + HWREG(DMA_BASE + DMA_O_CLEARCHNLPRIORITY) = channelBitMask; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __UDMA_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/asmdefs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/asmdefs.h new file mode 100644 index 00000000..3e3b8bc2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/asmdefs.h @@ -0,0 +1,149 @@ +/****************************************************************************** +* Filename: asmdefs.h +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_adc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_adc.h new file mode 100644 index 00000000..8166732f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_adc.h @@ -0,0 +1,2714 @@ +/****************************************************************************** +* Filename: hw_adc_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADC component +// +//***************************************************************************** +// Interrupt mask +#define ADC_O_IMASK0 0x00000028U + +// Raw interrupt status +#define ADC_O_RIS0 0x00000030U + +// Masked interrupt status +#define ADC_O_MIS0 0x00000038U + +// Interrupt set +#define ADC_O_ISET0 0x00000040U + +// Interrupt clear +#define ADC_O_ICLR0 0x00000048U + +// Interrupt mask +#define ADC_O_IMASK1 0x00000058U + +// Raw interrupt status +#define ADC_O_RIS1 0x00000060U + +// Masked interrupt status +#define ADC_O_MIS1 0x00000068U + +// Interrupt set +#define ADC_O_ISET1 0x00000070U + +// Interrupt clear +#define ADC_O_ICLR1 0x00000078U + +// Interrupt mask +#define ADC_O_IMASK2 0x00000088U + +// Raw interrupt status +#define ADC_O_RIS2 0x00000090U + +// Masked interrupt status +#define ADC_O_MIS2 0x00000098U + +// Interrupt set +#define ADC_O_ISET2 0x000000A0U + +// Interrupt clear +#define ADC_O_ICLR2 0x000000A8U + +// Control Register 0 +#define ADC_O_CTL0 0x00000100U + +// Control Register 1 +#define ADC_O_CTL1 0x00000104U + +// Control Register 2 +#define ADC_O_CTL2 0x00000108U + +// Control Register 3 +#define ADC_O_CTL3 0x0000010CU + +// Sample Time Compare 0 Register +#define ADC_O_SCOMP0 0x00000114U + +// Sample Time Compare 1 Register +#define ADC_O_SCOMP1 0x00000118U + +// Reference Buffer Configuration Register +#define ADC_O_REFCFG 0x0000011CU + +// Window Comparator Low Threshold Register +#define ADC_O_WCLOW 0x00000148U + +// Window Comparator High Threshold Register +#define ADC_O_WCHIGH 0x00000150U + +// FIFO Data Register +#define ADC_O_FIFODATA 0x00000160U + +// ASC Result Register +#define ADC_O_ASCRES 0x00000170U + +// Conversion Memory Control Register 0 +#define ADC_O_MEMCTL0 0x00000180U + +// Conversion Memory Control Register 1 +#define ADC_O_MEMCTL1 0x00000184U + +// Conversion Memory Control Register 2 +#define ADC_O_MEMCTL2 0x00000188U + +// Conversion Memory Control Register 3 +#define ADC_O_MEMCTL3 0x0000018CU + +// Memory Result Register 0 +#define ADC_O_MEMRES0 0x00000280U + +// Memory Result Register 1 +#define ADC_O_MEMRES1 0x00000284U + +// Memory Result Register 2 +#define ADC_O_MEMRES2 0x00000288U + +// Memory Result Register 3 +#define ADC_O_MEMRES3 0x0000028CU + +// Status Register +#define ADC_O_STA 0x00000340U + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST0 0x00000E00U + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST2 0x00000E08U + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST3 0x00000E0CU + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST4 0x00000E10U + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST5 0x00000E14U + +// Internal. Only to be used through TI provided API. +#define ADC_O_TEST6 0x00000E18U + +// Internal. Only to be used through TI provided API. +#define ADC_O_DEBUG1 0x00000E20U + +// Internal. Only to be used through TI provided API. +#define ADC_O_DEBUG2 0x00000E24U + +// Internal. Only to be used through TI provided API. +#define ADC_O_DEBUG3 0x00000E28U + +// Internal. Only to be used through TI provided API. +#define ADC_O_DEBUG4 0x00000E2CU + +//***************************************************************************** +// +// Register: ADC_O_IMASK0 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// MEMRES3 conversion result interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_MEMRESIFG3 0x00000800U +#define ADC_IMASK0_MEMRESIFG3_M 0x00000800U +#define ADC_IMASK0_MEMRESIFG3_S 11U +#define ADC_IMASK0_MEMRESIFG3_EN 0x00000800U +#define ADC_IMASK0_MEMRESIFG3_DIS 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// MEMRES2 conversion result interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_MEMRESIFG2 0x00000400U +#define ADC_IMASK0_MEMRESIFG2_M 0x00000400U +#define ADC_IMASK0_MEMRESIFG2_S 10U +#define ADC_IMASK0_MEMRESIFG2_EN 0x00000400U +#define ADC_IMASK0_MEMRESIFG2_DIS 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// MEMRES1 conversion result interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_MEMRESIFG1 0x00000200U +#define ADC_IMASK0_MEMRESIFG1_M 0x00000200U +#define ADC_IMASK0_MEMRESIFG1_S 9U +#define ADC_IMASK0_MEMRESIFG1_EN 0x00000200U +#define ADC_IMASK0_MEMRESIFG1_DIS 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// MEMRES0 conversion result interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_MEMRESIFG0 0x00000100U +#define ADC_IMASK0_MEMRESIFG0_M 0x00000100U +#define ADC_IMASK0_MEMRESIFG0_S 8U +#define ADC_IMASK0_MEMRESIFG0_EN 0x00000100U +#define ADC_IMASK0_MEMRESIFG0_DIS 0x00000000U + +// Field: [7] ASCDONE +// +// Mask for ASC done raw interrupt flag. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_ASCDONE 0x00000080U +#define ADC_IMASK0_ASCDONE_M 0x00000080U +#define ADC_IMASK0_ASCDONE_S 7U +#define ADC_IMASK0_ASCDONE_EN 0x00000080U +#define ADC_IMASK0_ASCDONE_DIS 0x00000000U + +// Field: [6] UVIFG +// +// Conversion underflow interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_UVIFG 0x00000040U +#define ADC_IMASK0_UVIFG_M 0x00000040U +#define ADC_IMASK0_UVIFG_S 6U +#define ADC_IMASK0_UVIFG_EN 0x00000040U +#define ADC_IMASK0_UVIFG_DIS 0x00000000U + +// Field: [5] DMADONE +// +// DMA done interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_DMADONE 0x00000020U +#define ADC_IMASK0_DMADONE_M 0x00000020U +#define ADC_IMASK0_DMADONE_S 5U +#define ADC_IMASK0_DMADONE_EN 0x00000020U +#define ADC_IMASK0_DMADONE_DIS 0x00000000U + +// Field: [4] INIFG +// +// In-range comparator interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_INIFG 0x00000010U +#define ADC_IMASK0_INIFG_M 0x00000010U +#define ADC_IMASK0_INIFG_S 4U +#define ADC_IMASK0_INIFG_EN 0x00000010U +#define ADC_IMASK0_INIFG_DIS 0x00000000U + +// Field: [3] LOWIFG +// +// Low threshold compare interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_LOWIFG 0x00000008U +#define ADC_IMASK0_LOWIFG_M 0x00000008U +#define ADC_IMASK0_LOWIFG_S 3U +#define ADC_IMASK0_LOWIFG_EN 0x00000008U +#define ADC_IMASK0_LOWIFG_DIS 0x00000000U + +// Field: [2] HIGHIFG +// +// High threshold compare interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_HIGHIFG 0x00000004U +#define ADC_IMASK0_HIGHIFG_M 0x00000004U +#define ADC_IMASK0_HIGHIFG_S 2U +#define ADC_IMASK0_HIGHIFG_EN 0x00000004U +#define ADC_IMASK0_HIGHIFG_DIS 0x00000000U + +// Field: [1] TOVIFG +// +// Sequence conversion time overflow interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_TOVIFG 0x00000002U +#define ADC_IMASK0_TOVIFG_M 0x00000002U +#define ADC_IMASK0_TOVIFG_S 1U +#define ADC_IMASK0_TOVIFG_EN 0x00000002U +#define ADC_IMASK0_TOVIFG_DIS 0x00000000U + +// Field: [0] OVIFG +// +// Conversion overflow interrupt mask. +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define ADC_IMASK0_OVIFG 0x00000001U +#define ADC_IMASK0_OVIFG_M 0x00000001U +#define ADC_IMASK0_OVIFG_S 0U +#define ADC_IMASK0_OVIFG_EN 0x00000001U +#define ADC_IMASK0_OVIFG_DIS 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_RIS0 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Raw interrupt status for MEMRES3. +// This bit is set to 1 when MEMRES3 is loaded with a new +// conversion result. +// Reading MEMRES3 register will clear this bit, or when the +// corresponding bit in ICLR0 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS0_MEMRESIFG3 0x00000800U +#define ADC_RIS0_MEMRESIFG3_M 0x00000800U +#define ADC_RIS0_MEMRESIFG3_S 11U +#define ADC_RIS0_MEMRESIFG3_SET 0x00000800U +#define ADC_RIS0_MEMRESIFG3_CLR 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Raw interrupt status for MEMRES2. +// This bit is set to 1 when MEMRES2 is loaded with a new +// conversion result. +// Reading MEMRES2 register will clear this bit, or when the +// corresponding bit in ICLR0 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS0_MEMRESIFG2 0x00000400U +#define ADC_RIS0_MEMRESIFG2_M 0x00000400U +#define ADC_RIS0_MEMRESIFG2_S 10U +#define ADC_RIS0_MEMRESIFG2_SET 0x00000400U +#define ADC_RIS0_MEMRESIFG2_CLR 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Raw interrupt status for MEMRES1. +// This bit is set to 1 when MEMRES1 is loaded with a new +// conversion result. +// Reading MEMRES1 register will clear this bit, or when the +// corresponding bit in ICLR0 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS0_MEMRESIFG1 0x00000200U +#define ADC_RIS0_MEMRESIFG1_M 0x00000200U +#define ADC_RIS0_MEMRESIFG1_S 9U +#define ADC_RIS0_MEMRESIFG1_SET 0x00000200U +#define ADC_RIS0_MEMRESIFG1_CLR 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Raw interrupt status for MEMRES0. +// This bit is set to 1 when MEMRES0 is loaded with a new +// conversion result. +// Reading MEMRES0 register will clear this bit, or when the +// corresponding bit in ICLR0 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS0_MEMRESIFG0 0x00000100U +#define ADC_RIS0_MEMRESIFG0_M 0x00000100U +#define ADC_RIS0_MEMRESIFG0_S 8U +#define ADC_RIS0_MEMRESIFG0_SET 0x00000100U +#define ADC_RIS0_MEMRESIFG0_CLR 0x00000000U + +// Field: [7] ASCDONE +// +// Raw interrupt flag for ASC done. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_ASCDONE 0x00000080U +#define ADC_RIS0_ASCDONE_M 0x00000080U +#define ADC_RIS0_ASCDONE_S 7U +#define ADC_RIS0_ASCDONE_SET 0x00000080U +#define ADC_RIS0_ASCDONE_CLR 0x00000000U + +// Field: [6] UVIFG +// +// Raw interrupt flag for MEMRESx underflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_UVIFG 0x00000040U +#define ADC_RIS0_UVIFG_M 0x00000040U +#define ADC_RIS0_UVIFG_S 6U +#define ADC_RIS0_UVIFG_SET 0x00000040U +#define ADC_RIS0_UVIFG_CLR 0x00000000U + +// Field: [5] DMADONE +// +// Raw interrupt flag for DMADONE. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_DMADONE 0x00000020U +#define ADC_RIS0_DMADONE_M 0x00000020U +#define ADC_RIS0_DMADONE_S 5U +#define ADC_RIS0_DMADONE_SET 0x00000020U +#define ADC_RIS0_DMADONE_CLR 0x00000000U + +// Field: [4] INIFG +// +// Raw interrupt status for In-range comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_INIFG 0x00000010U +#define ADC_RIS0_INIFG_M 0x00000010U +#define ADC_RIS0_INIFG_S 4U +#define ADC_RIS0_INIFG_SET 0x00000010U +#define ADC_RIS0_INIFG_CLR 0x00000000U + +// Field: [3] LOWIFG +// +// Raw interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_LOWIFG 0x00000008U +#define ADC_RIS0_LOWIFG_M 0x00000008U +#define ADC_RIS0_LOWIFG_S 3U +#define ADC_RIS0_LOWIFG_SET 0x00000008U +#define ADC_RIS0_LOWIFG_CLR 0x00000000U + +// Field: [2] HIGHIFG +// +// Raw interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_HIGHIFG 0x00000004U +#define ADC_RIS0_HIGHIFG_M 0x00000004U +#define ADC_RIS0_HIGHIFG_S 2U +#define ADC_RIS0_HIGHIFG_SET 0x00000004U +#define ADC_RIS0_HIGHIFG_CLR 0x00000000U + +// Field: [1] TOVIFG +// +// Raw interrupt flag for sequence conversion trigger overflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_TOVIFG 0x00000002U +#define ADC_RIS0_TOVIFG_M 0x00000002U +#define ADC_RIS0_TOVIFG_S 1U +#define ADC_RIS0_TOVIFG_SET 0x00000002U +#define ADC_RIS0_TOVIFG_CLR 0x00000000U + +// Field: [0] OVIFG +// +// Raw interrupt flag for MEMRESx overflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS0_OVIFG 0x00000001U +#define ADC_RIS0_OVIFG_M 0x00000001U +#define ADC_RIS0_OVIFG_S 0U +#define ADC_RIS0_OVIFG_SET 0x00000001U +#define ADC_RIS0_OVIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MIS0 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Masked interrupt status for MEMRES3. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS0_MEMRESIFG3 0x00000800U +#define ADC_MIS0_MEMRESIFG3_M 0x00000800U +#define ADC_MIS0_MEMRESIFG3_S 11U +#define ADC_MIS0_MEMRESIFG3_SET 0x00000800U +#define ADC_MIS0_MEMRESIFG3_CLR 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Masked interrupt status for MEMRES2. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS0_MEMRESIFG2 0x00000400U +#define ADC_MIS0_MEMRESIFG2_M 0x00000400U +#define ADC_MIS0_MEMRESIFG2_S 10U +#define ADC_MIS0_MEMRESIFG2_SET 0x00000400U +#define ADC_MIS0_MEMRESIFG2_CLR 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Masked interrupt status for MEMRES1. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS0_MEMRESIFG1 0x00000200U +#define ADC_MIS0_MEMRESIFG1_M 0x00000200U +#define ADC_MIS0_MEMRESIFG1_S 9U +#define ADC_MIS0_MEMRESIFG1_SET 0x00000200U +#define ADC_MIS0_MEMRESIFG1_CLR 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Masked interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS0_MEMRESIFG0 0x00000100U +#define ADC_MIS0_MEMRESIFG0_M 0x00000100U +#define ADC_MIS0_MEMRESIFG0_S 8U +#define ADC_MIS0_MEMRESIFG0_SET 0x00000100U +#define ADC_MIS0_MEMRESIFG0_CLR 0x00000000U + +// Field: [7] ASCDONE +// +// Masked interrupt status for ASC done. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_ASCDONE 0x00000080U +#define ADC_MIS0_ASCDONE_M 0x00000080U +#define ADC_MIS0_ASCDONE_S 7U +#define ADC_MIS0_ASCDONE_SET 0x00000080U +#define ADC_MIS0_ASCDONE_CLR 0x00000000U + +// Field: [6] UVIFG +// +// Masked interrupt flag for MEMRESx underflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_UVIFG 0x00000040U +#define ADC_MIS0_UVIFG_M 0x00000040U +#define ADC_MIS0_UVIFG_S 6U +#define ADC_MIS0_UVIFG_SET 0x00000040U +#define ADC_MIS0_UVIFG_CLR 0x00000000U + +// Field: [5] DMADONE +// +// Masked interrupt flag for DMADONE. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_DMADONE 0x00000020U +#define ADC_MIS0_DMADONE_M 0x00000020U +#define ADC_MIS0_DMADONE_S 5U +#define ADC_MIS0_DMADONE_SET 0x00000020U +#define ADC_MIS0_DMADONE_CLR 0x00000000U + +// Field: [4] INIFG +// +// Mask INIFG in MIS0 register. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_INIFG 0x00000010U +#define ADC_MIS0_INIFG_M 0x00000010U +#define ADC_MIS0_INIFG_S 4U +#define ADC_MIS0_INIFG_SET 0x00000010U +#define ADC_MIS0_INIFG_CLR 0x00000000U + +// Field: [3] LOWIFG +// +// Masked interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_LOWIFG 0x00000008U +#define ADC_MIS0_LOWIFG_M 0x00000008U +#define ADC_MIS0_LOWIFG_S 3U +#define ADC_MIS0_LOWIFG_SET 0x00000008U +#define ADC_MIS0_LOWIFG_CLR 0x00000000U + +// Field: [2] HIGHIFG +// +// Masked interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_HIGHIFG 0x00000004U +#define ADC_MIS0_HIGHIFG_M 0x00000004U +#define ADC_MIS0_HIGHIFG_S 2U +#define ADC_MIS0_HIGHIFG_SET 0x00000004U +#define ADC_MIS0_HIGHIFG_CLR 0x00000000U + +// Field: [1] TOVIFG +// +// Masked interrupt flag for sequence conversion timeout overflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_TOVIFG 0x00000002U +#define ADC_MIS0_TOVIFG_M 0x00000002U +#define ADC_MIS0_TOVIFG_S 1U +#define ADC_MIS0_TOVIFG_SET 0x00000002U +#define ADC_MIS0_TOVIFG_CLR 0x00000000U + +// Field: [0] OVIFG +// +// Masked interrupt flag for MEMRESx overflow. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS0_OVIFG 0x00000001U +#define ADC_MIS0_OVIFG_M 0x00000001U +#define ADC_MIS0_OVIFG_S 0U +#define ADC_MIS0_OVIFG_SET 0x00000001U +#define ADC_MIS0_OVIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ISET0 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Set interrupt status for MEMRES3. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET0_MEMRESIFG3 0x00000800U +#define ADC_ISET0_MEMRESIFG3_M 0x00000800U +#define ADC_ISET0_MEMRESIFG3_S 11U +#define ADC_ISET0_MEMRESIFG3_SET 0x00000800U +#define ADC_ISET0_MEMRESIFG3_NO_EFFECT 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Set interrupt status for MEMRES2. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET0_MEMRESIFG2 0x00000400U +#define ADC_ISET0_MEMRESIFG2_M 0x00000400U +#define ADC_ISET0_MEMRESIFG2_S 10U +#define ADC_ISET0_MEMRESIFG2_SET 0x00000400U +#define ADC_ISET0_MEMRESIFG2_NO_EFFECT 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Set interrupt status for MEMRES1. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET0_MEMRESIFG1 0x00000200U +#define ADC_ISET0_MEMRESIFG1_M 0x00000200U +#define ADC_ISET0_MEMRESIFG1_S 9U +#define ADC_ISET0_MEMRESIFG1_SET 0x00000200U +#define ADC_ISET0_MEMRESIFG1_NO_EFFECT 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Set Interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET0_MEMRESIFG0 0x00000100U +#define ADC_ISET0_MEMRESIFG0_M 0x00000100U +#define ADC_ISET0_MEMRESIFG0_S 8U +#define ADC_ISET0_MEMRESIFG0_SET 0x00000100U +#define ADC_ISET0_MEMRESIFG0_NO_EFFECT 0x00000000U + +// Field: [7] ASCDONE +// +// Set interrupt for ASC done. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_ASCDONE 0x00000080U +#define ADC_ISET0_ASCDONE_M 0x00000080U +#define ADC_ISET0_ASCDONE_S 7U +#define ADC_ISET0_ASCDONE_SET 0x00000080U +#define ADC_ISET0_ASCDONE_NO_EFFECT 0x00000000U + +// Field: [6] UVIFG +// +// Set interrupt for MEMRESx underflow. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_UVIFG 0x00000040U +#define ADC_ISET0_UVIFG_M 0x00000040U +#define ADC_ISET0_UVIFG_S 6U +#define ADC_ISET0_UVIFG_SET 0x00000040U +#define ADC_ISET0_UVIFG_NO_EFFECT 0x00000000U + +// Field: [5] DMADONE +// +// Set interrupt for DMADONE. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_DMADONE 0x00000020U +#define ADC_ISET0_DMADONE_M 0x00000020U +#define ADC_ISET0_DMADONE_S 5U +#define ADC_ISET0_DMADONE_SET 0x00000020U +#define ADC_ISET0_DMADONE_NO_EFFECT 0x00000000U + +// Field: [4] INIFG +// +// Set INIFG interrupt register. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_INIFG 0x00000010U +#define ADC_ISET0_INIFG_M 0x00000010U +#define ADC_ISET0_INIFG_S 4U +#define ADC_ISET0_INIFG_SET 0x00000010U +#define ADC_ISET0_INIFG_NO_EFFECT 0x00000000U + +// Field: [3] LOWIFG +// +// Set interrupt for MEMRESx result register being below than the WCLOWx +// threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_LOWIFG 0x00000008U +#define ADC_ISET0_LOWIFG_M 0x00000008U +#define ADC_ISET0_LOWIFG_S 3U +#define ADC_ISET0_LOWIFG_SET 0x00000008U +#define ADC_ISET0_LOWIFG_NO_EFFECT 0x00000000U + +// Field: [2] HIGHIFG +// +// Set Interrupt for the MEMRESx result register being higher than the WCHIGHx +// threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_HIGHIFG 0x00000004U +#define ADC_ISET0_HIGHIFG_M 0x00000004U +#define ADC_ISET0_HIGHIFG_S 2U +#define ADC_ISET0_HIGHIFG_SET 0x00000004U +#define ADC_ISET0_HIGHIFG_NO_EFFECT 0x00000000U + +// Field: [1] TOVIFG +// +// Set interrupt for sequence conversion timeout overflow. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_TOVIFG 0x00000002U +#define ADC_ISET0_TOVIFG_M 0x00000002U +#define ADC_ISET0_TOVIFG_S 1U +#define ADC_ISET0_TOVIFG_SET 0x00000002U +#define ADC_ISET0_TOVIFG_NO_EFFECT 0x00000000U + +// Field: [0] OVIFG +// +// Set Interrupt for MEMRESx overflow. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET0_OVIFG 0x00000001U +#define ADC_ISET0_OVIFG_M 0x00000001U +#define ADC_ISET0_OVIFG_S 0U +#define ADC_ISET0_OVIFG_SET 0x00000001U +#define ADC_ISET0_OVIFG_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ICLR0 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Clear interrupt status for MEMRES3. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR0_MEMRESIFG3 0x00000800U +#define ADC_ICLR0_MEMRESIFG3_M 0x00000800U +#define ADC_ICLR0_MEMRESIFG3_S 11U +#define ADC_ICLR0_MEMRESIFG3_CLR 0x00000800U +#define ADC_ICLR0_MEMRESIFG3_NO_EFFECT 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Clear interrupt status for MEMRES2. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR0_MEMRESIFG2 0x00000400U +#define ADC_ICLR0_MEMRESIFG2_M 0x00000400U +#define ADC_ICLR0_MEMRESIFG2_S 10U +#define ADC_ICLR0_MEMRESIFG2_CLR 0x00000400U +#define ADC_ICLR0_MEMRESIFG2_NO_EFFECT 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Clear interrupt status for MEMRES1. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR0_MEMRESIFG1 0x00000200U +#define ADC_ICLR0_MEMRESIFG1_M 0x00000200U +#define ADC_ICLR0_MEMRESIFG1_S 9U +#define ADC_ICLR0_MEMRESIFG1_CLR 0x00000200U +#define ADC_ICLR0_MEMRESIFG1_NO_EFFECT 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Clear interrupt status for MEMRES0. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR0_MEMRESIFG0 0x00000100U +#define ADC_ICLR0_MEMRESIFG0_M 0x00000100U +#define ADC_ICLR0_MEMRESIFG0_S 8U +#define ADC_ICLR0_MEMRESIFG0_CLR 0x00000100U +#define ADC_ICLR0_MEMRESIFG0_NO_EFFECT 0x00000000U + +// Field: [7] ASCDONE +// +// Clear ASC done flag in RIS. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_ASCDONE 0x00000080U +#define ADC_ICLR0_ASCDONE_M 0x00000080U +#define ADC_ICLR0_ASCDONE_S 7U +#define ADC_ICLR0_ASCDONE_CLR 0x00000080U +#define ADC_ICLR0_ASCDONE_NO_EFFECT 0x00000000U + +// Field: [6] UVIFG +// +// Clear interrupt flag for MEMRESx underflow. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_UVIFG 0x00000040U +#define ADC_ICLR0_UVIFG_M 0x00000040U +#define ADC_ICLR0_UVIFG_S 6U +#define ADC_ICLR0_UVIFG_CLR 0x00000040U +#define ADC_ICLR0_UVIFG_NO_EFFECT 0x00000000U + +// Field: [5] DMADONE +// +// Clear interrupt flag for DMADONE. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_DMADONE 0x00000020U +#define ADC_ICLR0_DMADONE_M 0x00000020U +#define ADC_ICLR0_DMADONE_S 5U +#define ADC_ICLR0_DMADONE_CLR 0x00000020U +#define ADC_ICLR0_DMADONE_NO_EFFECT 0x00000000U + +// Field: [4] INIFG +// +// Clear INIFG in MIS0 register. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_INIFG 0x00000010U +#define ADC_ICLR0_INIFG_M 0x00000010U +#define ADC_ICLR0_INIFG_S 4U +#define ADC_ICLR0_INIFG_CLR 0x00000010U +#define ADC_ICLR0_INIFG_NO_EFFECT 0x00000000U + +// Field: [3] LOWIFG +// +// Clear interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_LOWIFG 0x00000008U +#define ADC_ICLR0_LOWIFG_M 0x00000008U +#define ADC_ICLR0_LOWIFG_S 3U +#define ADC_ICLR0_LOWIFG_CLR 0x00000008U +#define ADC_ICLR0_LOWIFG_NO_EFFECT 0x00000000U + +// Field: [2] HIGHIFG +// +// Clear interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_HIGHIFG 0x00000004U +#define ADC_ICLR0_HIGHIFG_M 0x00000004U +#define ADC_ICLR0_HIGHIFG_S 2U +#define ADC_ICLR0_HIGHIFG_CLR 0x00000004U +#define ADC_ICLR0_HIGHIFG_NO_EFFECT 0x00000000U + +// Field: [1] TOVIFG +// +// Clear interrupt flag for sequence conversion timeout overflow. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_TOVIFG 0x00000002U +#define ADC_ICLR0_TOVIFG_M 0x00000002U +#define ADC_ICLR0_TOVIFG_S 1U +#define ADC_ICLR0_TOVIFG_CLR 0x00000002U +#define ADC_ICLR0_TOVIFG_NO_EFFECT 0x00000000U + +// Field: [0] OVIFG +// +// Clear interrupt flag for MEMRESx overflow. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR0_OVIFG 0x00000001U +#define ADC_ICLR0_OVIFG_M 0x00000001U +#define ADC_ICLR0_OVIFG_S 0U +#define ADC_ICLR0_OVIFG_CLR 0x00000001U +#define ADC_ICLR0_OVIFG_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_IMASK1 +// +//***************************************************************************** +// Field: [8] MEMRESIFG0 +// +// MEMRES0 conversion result interrupt mask. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_IMASK1_MEMRESIFG0 0x00000100U +#define ADC_IMASK1_MEMRESIFG0_M 0x00000100U +#define ADC_IMASK1_MEMRESIFG0_S 8U +#define ADC_IMASK1_MEMRESIFG0_SET 0x00000100U +#define ADC_IMASK1_MEMRESIFG0_CLR 0x00000000U + +// Field: [4] INIFG +// +// In-range comparator interrupt mask. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_IMASK1_INIFG 0x00000010U +#define ADC_IMASK1_INIFG_M 0x00000010U +#define ADC_IMASK1_INIFG_S 4U +#define ADC_IMASK1_INIFG_SET 0x00000010U +#define ADC_IMASK1_INIFG_CLR 0x00000000U + +// Field: [3] LOWIFG +// +// Low threshold compare interrupt mask. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_IMASK1_LOWIFG 0x00000008U +#define ADC_IMASK1_LOWIFG_M 0x00000008U +#define ADC_IMASK1_LOWIFG_S 3U +#define ADC_IMASK1_LOWIFG_SET 0x00000008U +#define ADC_IMASK1_LOWIFG_CLR 0x00000000U + +// Field: [2] HIGHIFG +// +// High threshold compare interrupt mask. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_IMASK1_HIGHIFG 0x00000004U +#define ADC_IMASK1_HIGHIFG_M 0x00000004U +#define ADC_IMASK1_HIGHIFG_S 2U +#define ADC_IMASK1_HIGHIFG_SET 0x00000004U +#define ADC_IMASK1_HIGHIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_RIS1 +// +//***************************************************************************** +// Field: [8] MEMRESIFG0 +// +// Raw interrupt status for MEMRES0. +// This bit is set to 1 when MEMRES0 is loaded with a new +// conversion result. +// Reading MEMRES0 register will clear this bit, or when the +// corresponding bit in ICLR1 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS1_MEMRESIFG0 0x00000100U +#define ADC_RIS1_MEMRESIFG0_M 0x00000100U +#define ADC_RIS1_MEMRESIFG0_S 8U +#define ADC_RIS1_MEMRESIFG0_SET 0x00000100U +#define ADC_RIS1_MEMRESIFG0_CLR 0x00000000U + +// Field: [4] INIFG +// +// Raw interrupt status for In-range comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS1_INIFG 0x00000010U +#define ADC_RIS1_INIFG_M 0x00000010U +#define ADC_RIS1_INIFG_S 4U +#define ADC_RIS1_INIFG_SET 0x00000010U +#define ADC_RIS1_INIFG_CLR 0x00000000U + +// Field: [3] LOWIFG +// +// Raw interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS1_LOWIFG 0x00000008U +#define ADC_RIS1_LOWIFG_M 0x00000008U +#define ADC_RIS1_LOWIFG_S 3U +#define ADC_RIS1_LOWIFG_SET 0x00000008U +#define ADC_RIS1_LOWIFG_CLR 0x00000000U + +// Field: [2] HIGHIFG +// +// Raw interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_RIS1_HIGHIFG 0x00000004U +#define ADC_RIS1_HIGHIFG_M 0x00000004U +#define ADC_RIS1_HIGHIFG_S 2U +#define ADC_RIS1_HIGHIFG_SET 0x00000004U +#define ADC_RIS1_HIGHIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MIS1 +// +//***************************************************************************** +// Field: [8] MEMRESIFG0 +// +// Masked interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS1_MEMRESIFG0 0x00000100U +#define ADC_MIS1_MEMRESIFG0_M 0x00000100U +#define ADC_MIS1_MEMRESIFG0_S 8U +#define ADC_MIS1_MEMRESIFG0_SET 0x00000100U +#define ADC_MIS1_MEMRESIFG0_CLR 0x00000000U + +// Field: [4] INIFG +// +// Mask INIFG in MIS1 register. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS1_INIFG 0x00000010U +#define ADC_MIS1_INIFG_M 0x00000010U +#define ADC_MIS1_INIFG_S 4U +#define ADC_MIS1_INIFG_SET 0x00000010U +#define ADC_MIS1_INIFG_CLR 0x00000000U + +// Field: [3] LOWIFG +// +// Masked interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS1_LOWIFG 0x00000008U +#define ADC_MIS1_LOWIFG_M 0x00000008U +#define ADC_MIS1_LOWIFG_S 3U +#define ADC_MIS1_LOWIFG_SET 0x00000008U +#define ADC_MIS1_LOWIFG_CLR 0x00000000U + +// Field: [2] HIGHIFG +// +// Masked interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// CLR Interrupt is not pending. +#define ADC_MIS1_HIGHIFG 0x00000004U +#define ADC_MIS1_HIGHIFG_M 0x00000004U +#define ADC_MIS1_HIGHIFG_S 2U +#define ADC_MIS1_HIGHIFG_SET 0x00000004U +#define ADC_MIS1_HIGHIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ISET1 +// +//***************************************************************************** +// Field: [8] MEMRESIFG0 +// +// Set Interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET1_MEMRESIFG0 0x00000100U +#define ADC_ISET1_MEMRESIFG0_M 0x00000100U +#define ADC_ISET1_MEMRESIFG0_S 8U +#define ADC_ISET1_MEMRESIFG0_SET 0x00000100U +#define ADC_ISET1_MEMRESIFG0_NO_EFFECT 0x00000000U + +// Field: [4] INIFG +// +// Set INIFG interrupt register. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET1_INIFG 0x00000010U +#define ADC_ISET1_INIFG_M 0x00000010U +#define ADC_ISET1_INIFG_S 4U +#define ADC_ISET1_INIFG_SET 0x00000010U +#define ADC_ISET1_INIFG_NO_EFFECT 0x00000000U + +// Field: [3] LOWIFG +// +// Set interrupt for MEMRESx result register being below than the WCLOWx +// threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET1_LOWIFG 0x00000008U +#define ADC_ISET1_LOWIFG_M 0x00000008U +#define ADC_ISET1_LOWIFG_S 3U +#define ADC_ISET1_LOWIFG_SET 0x00000008U +#define ADC_ISET1_LOWIFG_NO_EFFECT 0x00000000U + +// Field: [2] HIGHIFG +// +// Set Interrupt for the MEMRESx result register being higher than the WCHIGHx +// threshold of the window comparator. +// ENUMs: +// SET Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ISET1_HIGHIFG 0x00000004U +#define ADC_ISET1_HIGHIFG_M 0x00000004U +#define ADC_ISET1_HIGHIFG_S 2U +#define ADC_ISET1_HIGHIFG_SET 0x00000004U +#define ADC_ISET1_HIGHIFG_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ICLR1 +// +//***************************************************************************** +// Field: [8] MEMRESIFG0 +// +// Clear interrupt status for MEMRES0. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR1_MEMRESIFG0 0x00000100U +#define ADC_ICLR1_MEMRESIFG0_M 0x00000100U +#define ADC_ICLR1_MEMRESIFG0_S 8U +#define ADC_ICLR1_MEMRESIFG0_CLR 0x00000100U +#define ADC_ICLR1_MEMRESIFG0_NO_EFFECT 0x00000000U + +// Field: [4] INIFG +// +// Clear INIFG in MIS1 register. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR1_INIFG 0x00000010U +#define ADC_ICLR1_INIFG_M 0x00000010U +#define ADC_ICLR1_INIFG_S 4U +#define ADC_ICLR1_INIFG_CLR 0x00000010U +#define ADC_ICLR1_INIFG_NO_EFFECT 0x00000000U + +// Field: [3] LOWIFG +// +// Clear interrupt flag for the MEMRESx result register being below than the +// WCLOWx threshold of the window comparator. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR1_LOWIFG 0x00000008U +#define ADC_ICLR1_LOWIFG_M 0x00000008U +#define ADC_ICLR1_LOWIFG_S 3U +#define ADC_ICLR1_LOWIFG_CLR 0x00000008U +#define ADC_ICLR1_LOWIFG_NO_EFFECT 0x00000000U + +// Field: [2] HIGHIFG +// +// Clear interrupt flag for the MEMRESx result register being higher than the +// WCHIGHx threshold of the window comparator. +// ENUMs: +// CLR Interrupt is pending. +// NO_EFFECT Interrupt is not pending. +#define ADC_ICLR1_HIGHIFG 0x00000004U +#define ADC_ICLR1_HIGHIFG_M 0x00000004U +#define ADC_ICLR1_HIGHIFG_S 2U +#define ADC_ICLR1_HIGHIFG_CLR 0x00000004U +#define ADC_ICLR1_HIGHIFG_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_IMASK2 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// MEMRES3 conversion result interrupt mask. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_IMASK2_MEMRESIFG3 0x00000800U +#define ADC_IMASK2_MEMRESIFG3_M 0x00000800U +#define ADC_IMASK2_MEMRESIFG3_S 11U +#define ADC_IMASK2_MEMRESIFG3_SET 0x00000800U +#define ADC_IMASK2_MEMRESIFG3_CLR 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// MEMRES2 conversion result interrupt mask. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_IMASK2_MEMRESIFG2 0x00000400U +#define ADC_IMASK2_MEMRESIFG2_M 0x00000400U +#define ADC_IMASK2_MEMRESIFG2_S 10U +#define ADC_IMASK2_MEMRESIFG2_SET 0x00000400U +#define ADC_IMASK2_MEMRESIFG2_CLR 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// MEMRES1 conversion result interrupt mask. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_IMASK2_MEMRESIFG1 0x00000200U +#define ADC_IMASK2_MEMRESIFG1_M 0x00000200U +#define ADC_IMASK2_MEMRESIFG1_S 9U +#define ADC_IMASK2_MEMRESIFG1_SET 0x00000200U +#define ADC_IMASK2_MEMRESIFG1_CLR 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// MEMRES0 conversion result interrupt mask. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_IMASK2_MEMRESIFG0 0x00000100U +#define ADC_IMASK2_MEMRESIFG0_M 0x00000100U +#define ADC_IMASK2_MEMRESIFG0_S 8U +#define ADC_IMASK2_MEMRESIFG0_SET 0x00000100U +#define ADC_IMASK2_MEMRESIFG0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_RIS2 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Raw interrupt status for MEMRES3. +// This bit is set to 1 when MEMRES3 is loaded with a new +// conversion result. +// Reading MEMRES3 register will clear this bit, or when the +// corresponding bit in ICLR2 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS2_MEMRESIFG3 0x00000800U +#define ADC_RIS2_MEMRESIFG3_M 0x00000800U +#define ADC_RIS2_MEMRESIFG3_S 11U +#define ADC_RIS2_MEMRESIFG3_SET 0x00000800U +#define ADC_RIS2_MEMRESIFG3_CLR 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Raw interrupt status for MEMRES2. +// This bit is set to 1 when MEMRES2 is loaded with a new +// conversion result. +// Reading MEMRES2 register will clear this bit, or when the +// corresponding bit in ICLR2 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS2_MEMRESIFG2 0x00000400U +#define ADC_RIS2_MEMRESIFG2_M 0x00000400U +#define ADC_RIS2_MEMRESIFG2_S 10U +#define ADC_RIS2_MEMRESIFG2_SET 0x00000400U +#define ADC_RIS2_MEMRESIFG2_CLR 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Raw interrupt status for MEMRES1. +// This bit is set to 1 when MEMRES1 is loaded with a new +// conversion result. +// Reading MEMRES1 register will clear this bit, or when the +// corresponding bit in ICLR2 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS2_MEMRESIFG1 0x00000200U +#define ADC_RIS2_MEMRESIFG1_M 0x00000200U +#define ADC_RIS2_MEMRESIFG1_S 9U +#define ADC_RIS2_MEMRESIFG1_SET 0x00000200U +#define ADC_RIS2_MEMRESIFG1_CLR 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Raw interrupt status for MEMRES0. +// This bit is set to 1 when MEMRES0 is loaded with a new +// conversion result. +// Reading MEMRES0 register will clear this bit, or when the +// corresponding bit in ICLR2 is set to 1 +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_RIS2_MEMRESIFG0 0x00000100U +#define ADC_RIS2_MEMRESIFG0_M 0x00000100U +#define ADC_RIS2_MEMRESIFG0_S 8U +#define ADC_RIS2_MEMRESIFG0_SET 0x00000100U +#define ADC_RIS2_MEMRESIFG0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MIS2 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Masked interrupt status for MEMRES3. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS2_MEMRESIFG3 0x00000800U +#define ADC_MIS2_MEMRESIFG3_M 0x00000800U +#define ADC_MIS2_MEMRESIFG3_S 11U +#define ADC_MIS2_MEMRESIFG3_SET 0x00000800U +#define ADC_MIS2_MEMRESIFG3_CLR 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Masked interrupt status for MEMRES2. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS2_MEMRESIFG2 0x00000400U +#define ADC_MIS2_MEMRESIFG2_M 0x00000400U +#define ADC_MIS2_MEMRESIFG2_S 10U +#define ADC_MIS2_MEMRESIFG2_SET 0x00000400U +#define ADC_MIS2_MEMRESIFG2_CLR 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Masked interrupt status for MEMRES1. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS2_MEMRESIFG1 0x00000200U +#define ADC_MIS2_MEMRESIFG1_M 0x00000200U +#define ADC_MIS2_MEMRESIFG1_S 9U +#define ADC_MIS2_MEMRESIFG1_SET 0x00000200U +#define ADC_MIS2_MEMRESIFG1_CLR 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Masked interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// CLR No new data ready. +#define ADC_MIS2_MEMRESIFG0 0x00000100U +#define ADC_MIS2_MEMRESIFG0_M 0x00000100U +#define ADC_MIS2_MEMRESIFG0_S 8U +#define ADC_MIS2_MEMRESIFG0_SET 0x00000100U +#define ADC_MIS2_MEMRESIFG0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ISET2 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Set interrupt status for MEMRES3. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET2_MEMRESIFG3 0x00000800U +#define ADC_ISET2_MEMRESIFG3_M 0x00000800U +#define ADC_ISET2_MEMRESIFG3_S 11U +#define ADC_ISET2_MEMRESIFG3_SET 0x00000800U +#define ADC_ISET2_MEMRESIFG3_NO_EFFECT 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Set interrupt status for MEMRES2. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET2_MEMRESIFG2 0x00000400U +#define ADC_ISET2_MEMRESIFG2_M 0x00000400U +#define ADC_ISET2_MEMRESIFG2_S 10U +#define ADC_ISET2_MEMRESIFG2_SET 0x00000400U +#define ADC_ISET2_MEMRESIFG2_NO_EFFECT 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Set interrupt status for MEMRES1. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET2_MEMRESIFG1 0x00000200U +#define ADC_ISET2_MEMRESIFG1_M 0x00000200U +#define ADC_ISET2_MEMRESIFG1_S 9U +#define ADC_ISET2_MEMRESIFG1_SET 0x00000200U +#define ADC_ISET2_MEMRESIFG1_NO_EFFECT 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Set Interrupt status for MEMRES0. +// ENUMs: +// SET A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ISET2_MEMRESIFG0 0x00000100U +#define ADC_ISET2_MEMRESIFG0_M 0x00000100U +#define ADC_ISET2_MEMRESIFG0_S 8U +#define ADC_ISET2_MEMRESIFG0_SET 0x00000100U +#define ADC_ISET2_MEMRESIFG0_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_ICLR2 +// +//***************************************************************************** +// Field: [11] MEMRESIFG3 +// +// Clear interrupt status for MEMRES3. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR2_MEMRESIFG3 0x00000800U +#define ADC_ICLR2_MEMRESIFG3_M 0x00000800U +#define ADC_ICLR2_MEMRESIFG3_S 11U +#define ADC_ICLR2_MEMRESIFG3_CLR 0x00000800U +#define ADC_ICLR2_MEMRESIFG3_NO_EFFECT 0x00000000U + +// Field: [10] MEMRESIFG2 +// +// Clear interrupt status for MEMRES2. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR2_MEMRESIFG2 0x00000400U +#define ADC_ICLR2_MEMRESIFG2_M 0x00000400U +#define ADC_ICLR2_MEMRESIFG2_S 10U +#define ADC_ICLR2_MEMRESIFG2_CLR 0x00000400U +#define ADC_ICLR2_MEMRESIFG2_NO_EFFECT 0x00000000U + +// Field: [9] MEMRESIFG1 +// +// Clear interrupt status for MEMRES1. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR2_MEMRESIFG1 0x00000200U +#define ADC_ICLR2_MEMRESIFG1_M 0x00000200U +#define ADC_ICLR2_MEMRESIFG1_S 9U +#define ADC_ICLR2_MEMRESIFG1_CLR 0x00000200U +#define ADC_ICLR2_MEMRESIFG1_NO_EFFECT 0x00000000U + +// Field: [8] MEMRESIFG0 +// +// Clear interrupt status for MEMRES0. +// ENUMs: +// CLR A new data is ready to be read. +// NO_EFFECT No new data ready. +#define ADC_ICLR2_MEMRESIFG0 0x00000100U +#define ADC_ICLR2_MEMRESIFG0_M 0x00000100U +#define ADC_ICLR2_MEMRESIFG0_S 8U +#define ADC_ICLR2_MEMRESIFG0_CLR 0x00000100U +#define ADC_ICLR2_MEMRESIFG0_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_CTL0 +// +//***************************************************************************** +// Field: [26:24] SCLKDIV +// +// Sample clock divider +// ENUMs: +// DIV_BY_48 Divide clock source by 48 +// DIV_BY_32 Divide clock source by 32 +// DIV_BY_24 Divide clock source by 24 +// DIV_BY_16 Divide clock source by 16 +// DIV_BY_8 Divide clock source by 8 +// DIV_BY_4 Divide clock source by 4 +// DIV_BY_2 Divide clock source by 2 +// DIV_BY_1 Do not divide clock source +#define ADC_CTL0_SCLKDIV_W 3U +#define ADC_CTL0_SCLKDIV_M 0x07000000U +#define ADC_CTL0_SCLKDIV_S 24U +#define ADC_CTL0_SCLKDIV_DIV_BY_48 0x07000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_32 0x06000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_24 0x05000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_16 0x04000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_8 0x03000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_4 0x02000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_2 0x01000000U +#define ADC_CTL0_SCLKDIV_DIV_BY_1 0x00000000U + +// Field: [16] PWRDN +// +// Power down policy +// ENUMs: +// MANUAL ADC remains powered on as long as it is enabled +// through software. +// AUTO ADC is powered down on completion of a conversion +// if there is no pending trigger +#define ADC_CTL0_PWRDN 0x00010000U +#define ADC_CTL0_PWRDN_M 0x00010000U +#define ADC_CTL0_PWRDN_S 16U +#define ADC_CTL0_PWRDN_MANUAL 0x00010000U +#define ADC_CTL0_PWRDN_AUTO 0x00000000U + +// Field: [0] ENC +// +// Enable conversion +// ENUMs: +// ON Conversion enabled. ADC sequencer waits for the +// programmed trigger (software or hardware). +// OFF Conversion disabled. ENC change from ON to OFF +// will abort single or repeat sequence on a +// MEMCTLx boundary. The current conversion will +// finish and result stored in corresponding +// MEMRESx. +#define ADC_CTL0_ENC 0x00000001U +#define ADC_CTL0_ENC_M 0x00000001U +#define ADC_CTL0_ENC_S 0U +#define ADC_CTL0_ENC_ON 0x00000001U +#define ADC_CTL0_ENC_OFF 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_CTL1 +// +//***************************************************************************** +// Field: [20] SAMPMODE +// +// Sample mode. This bit selects the source of the sampling signal. +// MANUAL option is not applicable when TRIGSRC is selected as hardware event +// trigger. +// ENUMs: +// MANUAL Software trigger is used as sample signal +// AUTO Sample timer high phase is used as sample signal +#define ADC_CTL1_SAMPMODE 0x00100000U +#define ADC_CTL1_SAMPMODE_M 0x00100000U +#define ADC_CTL1_SAMPMODE_S 20U +#define ADC_CTL1_SAMPMODE_MANUAL 0x00100000U +#define ADC_CTL1_SAMPMODE_AUTO 0x00000000U + +// Field: [17:16] CONSEQ +// +// Conversion sequence mode +// ENUMs: +// REPEATSEQUENCE ADC channel sequence pointed by STARTADD and +// ENDADD will be converted repeatedly +// REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be +// converted repeatedly +// SEQUENCE ADC channel sequence pointed by STARTADD and +// ENDADD will be converted once +// SINGLE ADC channel in MEMCTLx pointed by STARTADD will be +// converted once +#define ADC_CTL1_CONSEQ_W 2U +#define ADC_CTL1_CONSEQ_M 0x00030000U +#define ADC_CTL1_CONSEQ_S 16U +#define ADC_CTL1_CONSEQ_REPEATSEQUENCE 0x00030000U +#define ADC_CTL1_CONSEQ_REPEATSINGLE 0x00020000U +#define ADC_CTL1_CONSEQ_SEQUENCE 0x00010000U +#define ADC_CTL1_CONSEQ_SINGLE 0x00000000U + +// Field: [8] SC +// +// Start of conversion +// ENUMs: +// START When SAMPMODE is set to MANUAL, setting this bit +// will start the sample phase. Sample phase will +// last as long as this bit is set. +// When SAMPMODE is set to +// AUTO, setting this bit will trigger the timer +// based sample time. +// STOP When SAMPMODE is set to MANUAL, clearing this bit +// will end the sample phase and the conversion +// phase will start. +// When SAMPMODE is set to +// AUTO, writing 0 has no effect. +#define ADC_CTL1_SC 0x00000100U +#define ADC_CTL1_SC_M 0x00000100U +#define ADC_CTL1_SC_S 8U +#define ADC_CTL1_SC_START 0x00000100U +#define ADC_CTL1_SC_STOP 0x00000000U + +// Field: [0] TRIGSRC +// +// Sample trigger source +// ENUMs: +// EVENT Hardware event trigger +// SOFTWARE Software trigger +#define ADC_CTL1_TRIGSRC 0x00000001U +#define ADC_CTL1_TRIGSRC_M 0x00000001U +#define ADC_CTL1_TRIGSRC_S 0U +#define ADC_CTL1_TRIGSRC_EVENT 0x00000001U +#define ADC_CTL1_TRIGSRC_SOFTWARE 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_CTL2 +// +//***************************************************************************** +// Field: [28:24] ENDADD +// +// Sequence end address. These bits select which MEMCTLx is the last one for +// the sequence mode. +// The value of ENDADD is 0x00 to 0x03 corresponding to MEMRES0 to MEMRES3. +// ENUMs: +// ADDR_03 MEMCTL3 is selected as end address of sequence. +// ADDR_02 MEMCTL2 is selected as end address of sequence. +// ADDR_01 MEMCTL1 is selected as end address of sequence. +// ADDR_00 MEMCTL0 is selected as end address of sequence. +#define ADC_CTL2_ENDADD_W 5U +#define ADC_CTL2_ENDADD_M 0x1F000000U +#define ADC_CTL2_ENDADD_S 24U +#define ADC_CTL2_ENDADD_ADDR_03 0x03000000U +#define ADC_CTL2_ENDADD_ADDR_02 0x02000000U +#define ADC_CTL2_ENDADD_ADDR_01 0x01000000U +#define ADC_CTL2_ENDADD_ADDR_00 0x00000000U + +// Field: [20:16] STARTADD +// +// Sequencer start address. These bits select which MEMCTLx is used for single +// conversion or as first MEMCTL for sequence mode. +// The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. +// ENUMs: +// ADDR_03 MEMCTL3 is selected as start address of a sequence +// or for a single conversion. +// ADDR_02 MEMCTL2 is selected as start address of a sequence +// or for a single conversion. +// ADDR_01 MEMCTL1 is selected as start address of a sequence +// or for a single conversion. +// ADDR_00 MEMCTL0 is selected as start address of a sequence +// or for a single conversion. +#define ADC_CTL2_STARTADD_W 5U +#define ADC_CTL2_STARTADD_M 0x001F0000U +#define ADC_CTL2_STARTADD_S 16U +#define ADC_CTL2_STARTADD_ADDR_03 0x00030000U +#define ADC_CTL2_STARTADD_ADDR_02 0x00020000U +#define ADC_CTL2_STARTADD_ADDR_01 0x00010000U +#define ADC_CTL2_STARTADD_ADDR_00 0x00000000U + +// Field: [10] FIFOEN +// +// Enable FIFO based operation +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_CTL2_FIFOEN 0x00000400U +#define ADC_CTL2_FIFOEN_M 0x00000400U +#define ADC_CTL2_FIFOEN_S 10U +#define ADC_CTL2_FIFOEN_EN 0x00000400U +#define ADC_CTL2_FIFOEN_DIS 0x00000000U + +// Field: [8] DMAEN +// +// Enable DMA trigger for data transfer. +// Note: DMAEN bit is cleared by hardware based on DMA done signal at the end +// of data transfer. Software has to re-enable DMAEN bit for ADC to generate +// DMA triggers. +// ENUMs: +// EN DMA trigger enabled +// DIS DMA trigger not enabled +#define ADC_CTL2_DMAEN 0x00000100U +#define ADC_CTL2_DMAEN_M 0x00000100U +#define ADC_CTL2_DMAEN_S 8U +#define ADC_CTL2_DMAEN_EN 0x00000100U +#define ADC_CTL2_DMAEN_DIS 0x00000000U + +// Field: [2:1] RES +// +// Resolution. These bits define the resolutoin of ADC conversion result. +// Note : A value of 3 defaults to 12-bits resolution. +// ENUMs: +// BIT_8 8-bits resolution +// BIT_10 10-bits resolution +// BIT_12 12-bits resolution +#define ADC_CTL2_RES_W 2U +#define ADC_CTL2_RES_M 0x00000006U +#define ADC_CTL2_RES_S 1U +#define ADC_CTL2_RES_BIT_8 0x00000004U +#define ADC_CTL2_RES_BIT_10 0x00000002U +#define ADC_CTL2_RES_BIT_12 0x00000000U + +// Field: [0] DF +// +// Data read-back format. Data is always stored in binary unsigned format. +// ENUMs: +// SIGNED Digital result reads Signed Binary. (2s +// complement), left aligned. +// UNSIGNED Digital result reads as Binary Unsigned. +#define ADC_CTL2_DF 0x00000001U +#define ADC_CTL2_DF_M 0x00000001U +#define ADC_CTL2_DF_S 0U +#define ADC_CTL2_DF_SIGNED 0x00000001U +#define ADC_CTL2_DF_UNSIGNED 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_CTL3 +// +//***************************************************************************** +// Field: [13:12] ASCVRSEL +// +// Selects voltage reference for ASC operation. AREF- must be connected to +// on-board ground when external reference option is selected. +// Note: Writing value 0x3 defaults to INTREF. +// ENUMs: +// INTREF Internal reference +// EXTREF External reference from AREF+/AREF- pins +// VDDS VDDS reference +#define ADC_CTL3_ASCVRSEL_W 2U +#define ADC_CTL3_ASCVRSEL_M 0x00003000U +#define ADC_CTL3_ASCVRSEL_S 12U +#define ADC_CTL3_ASCVRSEL_INTREF 0x00002000U +#define ADC_CTL3_ASCVRSEL_EXTREF 0x00001000U +#define ADC_CTL3_ASCVRSEL_VDDS 0x00000000U + +// Field: [8] ASCSTIME +// +// ASC sample time compare value select. This is used to select between SCOMP0 +// and SCOMP1 registers for ASC operation. +// ENUMs: +// SEL_SCOMP1 Select SCOMP1 +// SEL_SCOMP0 Select SCOMP0 +#define ADC_CTL3_ASCSTIME 0x00000100U +#define ADC_CTL3_ASCSTIME_M 0x00000100U +#define ADC_CTL3_ASCSTIME_S 8U +#define ADC_CTL3_ASCSTIME_SEL_SCOMP1 0x00000100U +#define ADC_CTL3_ASCSTIME_SEL_SCOMP0 0x00000000U + +// Field: [4:0] ASCCHSEL +// +// ASC channel select +// ENUMs: +// CHAN_15 Selects channel 15 +// CHAN_14 Selects channel 14 +// CHAN_13 Selects channel 13 +// CHAN_12 Selects channel 12 +// CHAN_11 Selects channel 11 +// CHAN_10 Selects channel 10 +// CHAN_9 Selects channel 9 +// CHAN_8 Selects channel 8 +// CHAN_7 Selects channel 7 +// CHAN_6 Selects channel 6 +// CHAN_5 Selects channel 5 +// CHAN_4 Selects channel 4 +// CHAN_3 Selects channel 3 +// CHAN_2 Selects channel 2 +// CHAN_1 Selects channel 1 +// CHAN_0 Selects channel 0 +#define ADC_CTL3_ASCCHSEL_W 5U +#define ADC_CTL3_ASCCHSEL_M 0x0000001FU +#define ADC_CTL3_ASCCHSEL_S 0U +#define ADC_CTL3_ASCCHSEL_CHAN_15 0x0000000FU +#define ADC_CTL3_ASCCHSEL_CHAN_14 0x0000000EU +#define ADC_CTL3_ASCCHSEL_CHAN_13 0x0000000DU +#define ADC_CTL3_ASCCHSEL_CHAN_12 0x0000000CU +#define ADC_CTL3_ASCCHSEL_CHAN_11 0x0000000BU +#define ADC_CTL3_ASCCHSEL_CHAN_10 0x0000000AU +#define ADC_CTL3_ASCCHSEL_CHAN_9 0x00000009U +#define ADC_CTL3_ASCCHSEL_CHAN_8 0x00000008U +#define ADC_CTL3_ASCCHSEL_CHAN_7 0x00000007U +#define ADC_CTL3_ASCCHSEL_CHAN_6 0x00000006U +#define ADC_CTL3_ASCCHSEL_CHAN_5 0x00000005U +#define ADC_CTL3_ASCCHSEL_CHAN_4 0x00000004U +#define ADC_CTL3_ASCCHSEL_CHAN_3 0x00000003U +#define ADC_CTL3_ASCCHSEL_CHAN_2 0x00000002U +#define ADC_CTL3_ASCCHSEL_CHAN_1 0x00000001U +#define ADC_CTL3_ASCCHSEL_CHAN_0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_SCOMP0 +// +//***************************************************************************** +// Field: [9:0] VAL +// +// Specifies the number of sample clocks. +// When VAL = 0 or 1, number of sample clocks = Sample clock divide value. +// When VAL > 1, number of sample clocks = VAL x Sample clock divide value. +// Note: Sample clock divide value is not the value written to SCLKDIV but the +// actual divide value (SCLKDIV = 2 implies divide value is 4). +// Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. +#define ADC_SCOMP0_VAL_W 10U +#define ADC_SCOMP0_VAL_M 0x000003FFU +#define ADC_SCOMP0_VAL_S 0U + +//***************************************************************************** +// +// Register: ADC_O_SCOMP1 +// +//***************************************************************************** +// Field: [9:0] VAL +// +// Specifies the number of sample clocks. +// When VAL = 0 or 1, number of sample clocks = Sample clock divide value. +// When VAL > 1, number of sample clocks = VAL x Sample clock divide value. +// Note: Sample clock divide value is not the value written to SCLKDIV but the +// actual divide value (SCLKDIV = 2 implies divide value is 4). +// Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. +#define ADC_SCOMP1_VAL_W 10U +#define ADC_SCOMP1_VAL_M 0x000003FFU +#define ADC_SCOMP1_VAL_S 0U + +//***************************************************************************** +// +// Register: ADC_O_REFCFG +// +//***************************************************************************** +// Field: [4:3] IBPROG +// +// Configures reference buffer bias current output value +// ENUMs: +// VAL3 0.67uA +// VAL2 +// VAL1 0.5uA +// VAL0 +#define ADC_REFCFG_IBPROG_W 2U +#define ADC_REFCFG_IBPROG_M 0x00000018U +#define ADC_REFCFG_IBPROG_S 3U +#define ADC_REFCFG_IBPROG_VAL3 0x00000018U +#define ADC_REFCFG_IBPROG_VAL2 0x00000010U +#define ADC_REFCFG_IBPROG_VAL1 0x00000008U +#define ADC_REFCFG_IBPROG_VAL0 0x00000000U + +// Field: [2] SPARE +// +// Spare bit +#define ADC_REFCFG_SPARE 0x00000004U +#define ADC_REFCFG_SPARE_M 0x00000004U +#define ADC_REFCFG_SPARE_S 2U + +// Field: [1] REFVSEL +// +// Configures reference buffer output voltage +// ENUMs: +// V1P4 REFBUF generates 1.4V output +// V2P5 REFBUF generates 2.5V output +#define ADC_REFCFG_REFVSEL 0x00000002U +#define ADC_REFCFG_REFVSEL_M 0x00000002U +#define ADC_REFCFG_REFVSEL_S 1U +#define ADC_REFCFG_REFVSEL_V1P4 0x00000002U +#define ADC_REFCFG_REFVSEL_V2P5 0x00000000U + +// Field: [0] REFEN +// +// Reference buffer enable +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_REFCFG_REFEN 0x00000001U +#define ADC_REFCFG_REFEN_M 0x00000001U +#define ADC_REFCFG_REFEN_S 0U +#define ADC_REFCFG_REFEN_EN 0x00000001U +#define ADC_REFCFG_REFEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_WCLOW +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary format has to be used. +// The value based on the resolution has to be right aligned with the MSB on +// the left. +// For 10-bits and 8-bits resolution, unused bits have to be 0s. +// +// If DF = 1, 2s-complement format has to be used. +// The value based on the resolution has to be left aligned with the LSB on the +// right. +// For 10-bits and 8-bits resolution, unused bits have to be 0s. +#define ADC_WCLOW_DATA_W 16U +#define ADC_WCLOW_DATA_M 0x0000FFFFU +#define ADC_WCLOW_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_WCHIGH +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary format has to be used. +// The threshold value has to be right aligned, with the MSB on the left. +// For 10-bits and 8-bits resolution, unused bit have to be 0s. +// +// If DF = 1, 2s-complement format has to be used. +// The value based on the resolution has to be left aligned with the LSB on the +// right. +// For 10-bits and 8-bits resolution, unused bit have to be 0s. +#define ADC_WCHIGH_DATA_W 16U +#define ADC_WCHIGH_DATA_M 0x0000FFFFU +#define ADC_WCHIGH_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_FIFODATA +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Read from this data field returns the ADC sample from FIFO. +#define ADC_FIFODATA_DATA_W 32U +#define ADC_FIFODATA_DATA_M 0xFFFFFFFFU +#define ADC_FIFODATA_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_ASCRES +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Result of ADC ad-hoc single conversion. +// If DF = 0, unsigned binary: +// The conversion result is right aligned. In 10 and 8 bit modes, the unused +// MSB bits are forced to 0. +// If DF = 1, 2s-complement format: +// The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB +// bits are forced to 0. +// The data is stored in the right-justified format and is converted to the +// left-justified 2s-complement format during read back. +#define ADC_ASCRES_DATA_W 16U +#define ADC_ASCRES_DATA_M 0x0000FFFFU +#define ADC_ASCRES_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_MEMCTL0 +// +//***************************************************************************** +// Field: [28] WINCOMP +// +// Enable window comparator. +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_MEMCTL0_WINCOMP 0x10000000U +#define ADC_MEMCTL0_WINCOMP_M 0x10000000U +#define ADC_MEMCTL0_WINCOMP_S 28U +#define ADC_MEMCTL0_WINCOMP_EN 0x10000000U +#define ADC_MEMCTL0_WINCOMP_DIS 0x00000000U + +// Field: [24] TRG +// +// Trigger policy. Indicates if a trigger will be needed to step to the next +// MEMCTL in the sequence or to perform next conversion in the case of repeat +// single channel conversions. +// ENUMs: +// TRIGGER_NEXT Next conversion requires a trigger +// AUTO_NEXT Next conversion is automatic +#define ADC_MEMCTL0_TRG 0x01000000U +#define ADC_MEMCTL0_TRG_M 0x01000000U +#define ADC_MEMCTL0_TRG_S 24U +#define ADC_MEMCTL0_TRG_TRIGGER_NEXT 0x01000000U +#define ADC_MEMCTL0_TRG_AUTO_NEXT 0x00000000U + +// Field: [12] STIME +// +// Selects the source of sample timer period between SCOMP0 and SCOMP1. +// ENUMs: +// SEL_SCOMP1 Select SCOMP1 +// SEL_SCOMP0 Select SCOMP0 +#define ADC_MEMCTL0_STIME 0x00001000U +#define ADC_MEMCTL0_STIME_M 0x00001000U +#define ADC_MEMCTL0_STIME_S 12U +#define ADC_MEMCTL0_STIME_SEL_SCOMP1 0x00001000U +#define ADC_MEMCTL0_STIME_SEL_SCOMP0 0x00000000U + +// Field: [9:8] VRSEL +// +// Voltage reference selection. AREF- must be connected to on-board ground when +// external reference option is selected. +// Note: Writing value 0x3 defaults to INTREF. +// ENUMs: +// INTREF Internal reference +// EXTREF External reference from AREF+/AREF- pins +// VDDS VDDS reference +#define ADC_MEMCTL0_VRSEL_W 2U +#define ADC_MEMCTL0_VRSEL_M 0x00000300U +#define ADC_MEMCTL0_VRSEL_S 8U +#define ADC_MEMCTL0_VRSEL_INTREF 0x00000200U +#define ADC_MEMCTL0_VRSEL_EXTREF 0x00000100U +#define ADC_MEMCTL0_VRSEL_VDDS 0x00000000U + +// Field: [4:0] CHANSEL +// +// Input channel select. +// ENUMs: +// CHAN_15 Selects channel 15 +// CHAN_14 Selects channel 14 +// CHAN_13 Selects channel 13 +// CHAN_12 Selects channel 12 +// CHAN_11 Selects channel 11 +// CHAN_10 Selects channel 10 +// CHAN_9 Selects channel 9 +// CHAN_8 Selects channel 8 +// CHAN_7 Selects channel 7 +// CHAN_6 Selects channel 6 +// CHAN_5 Selects channel 5 +// CHAN_4 Selects channel 4 +// CHAN_3 Selects channel 3 +// CHAN_2 Selects channel 2 +// CHAN_1 Selects channel 1 +// CHAN_0 Selects channel 0 +#define ADC_MEMCTL0_CHANSEL_W 5U +#define ADC_MEMCTL0_CHANSEL_M 0x0000001FU +#define ADC_MEMCTL0_CHANSEL_S 0U +#define ADC_MEMCTL0_CHANSEL_CHAN_15 0x0000000FU +#define ADC_MEMCTL0_CHANSEL_CHAN_14 0x0000000EU +#define ADC_MEMCTL0_CHANSEL_CHAN_13 0x0000000DU +#define ADC_MEMCTL0_CHANSEL_CHAN_12 0x0000000CU +#define ADC_MEMCTL0_CHANSEL_CHAN_11 0x0000000BU +#define ADC_MEMCTL0_CHANSEL_CHAN_10 0x0000000AU +#define ADC_MEMCTL0_CHANSEL_CHAN_9 0x00000009U +#define ADC_MEMCTL0_CHANSEL_CHAN_8 0x00000008U +#define ADC_MEMCTL0_CHANSEL_CHAN_7 0x00000007U +#define ADC_MEMCTL0_CHANSEL_CHAN_6 0x00000006U +#define ADC_MEMCTL0_CHANSEL_CHAN_5 0x00000005U +#define ADC_MEMCTL0_CHANSEL_CHAN_4 0x00000004U +#define ADC_MEMCTL0_CHANSEL_CHAN_3 0x00000003U +#define ADC_MEMCTL0_CHANSEL_CHAN_2 0x00000002U +#define ADC_MEMCTL0_CHANSEL_CHAN_1 0x00000001U +#define ADC_MEMCTL0_CHANSEL_CHAN_0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MEMCTL1 +// +//***************************************************************************** +// Field: [28] WINCOMP +// +// Enable window comparator. +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_MEMCTL1_WINCOMP 0x10000000U +#define ADC_MEMCTL1_WINCOMP_M 0x10000000U +#define ADC_MEMCTL1_WINCOMP_S 28U +#define ADC_MEMCTL1_WINCOMP_EN 0x10000000U +#define ADC_MEMCTL1_WINCOMP_DIS 0x00000000U + +// Field: [24] TRG +// +// Trigger policy. Indicates if a trigger will be needed to step to the next +// MEMCTL in the sequence or to perform next conversion in the case of repeat +// single channel conversions. +// ENUMs: +// TRIGGER_NEXT Next conversion requires a trigger +// AUTO_NEXT Next conversion is automatic +#define ADC_MEMCTL1_TRG 0x01000000U +#define ADC_MEMCTL1_TRG_M 0x01000000U +#define ADC_MEMCTL1_TRG_S 24U +#define ADC_MEMCTL1_TRG_TRIGGER_NEXT 0x01000000U +#define ADC_MEMCTL1_TRG_AUTO_NEXT 0x00000000U + +// Field: [12] STIME +// +// Selects the source of sample timer period between SCOMP0 and SCOMP1. +// ENUMs: +// SEL_SCOMP1 Select SCOMP1 +// SEL_SCOMP0 Select SCOMP0 +#define ADC_MEMCTL1_STIME 0x00001000U +#define ADC_MEMCTL1_STIME_M 0x00001000U +#define ADC_MEMCTL1_STIME_S 12U +#define ADC_MEMCTL1_STIME_SEL_SCOMP1 0x00001000U +#define ADC_MEMCTL1_STIME_SEL_SCOMP0 0x00000000U + +// Field: [9:8] VRSEL +// +// Voltage reference selection. AREF- must be connected to on-board ground when +// external reference option is selected. +// Note: Writing value 0x3 defaults to INTREF. +// ENUMs: +// INTREF Internal reference +// EXTREF External reference from AREF+/AREF- pins +// VDDS VDDS reference +#define ADC_MEMCTL1_VRSEL_W 2U +#define ADC_MEMCTL1_VRSEL_M 0x00000300U +#define ADC_MEMCTL1_VRSEL_S 8U +#define ADC_MEMCTL1_VRSEL_INTREF 0x00000200U +#define ADC_MEMCTL1_VRSEL_EXTREF 0x00000100U +#define ADC_MEMCTL1_VRSEL_VDDS 0x00000000U + +// Field: [4:0] CHANSEL +// +// Input channel select. +// ENUMs: +// CHAN_15 Selects channel 15 +// CHAN_14 Selects channel 14 +// CHAN_13 Selects channel 13 +// CHAN_12 Selects channel 12 +// CHAN_11 Selects channel 11 +// CHAN_10 Selects channel 10 +// CHAN_9 Selects channel 9 +// CHAN_8 Selects channel 8 +// CHAN_7 Selects channel 7 +// CHAN_6 Selects channel 6 +// CHAN_5 Selects channel 5 +// CHAN_4 Selects channel 4 +// CHAN_3 Selects channel 3 +// CHAN_2 Selects channel 2 +// CHAN_1 Selects channel 1 +// CHAN_0 Selects channel 0 +#define ADC_MEMCTL1_CHANSEL_W 5U +#define ADC_MEMCTL1_CHANSEL_M 0x0000001FU +#define ADC_MEMCTL1_CHANSEL_S 0U +#define ADC_MEMCTL1_CHANSEL_CHAN_15 0x0000000FU +#define ADC_MEMCTL1_CHANSEL_CHAN_14 0x0000000EU +#define ADC_MEMCTL1_CHANSEL_CHAN_13 0x0000000DU +#define ADC_MEMCTL1_CHANSEL_CHAN_12 0x0000000CU +#define ADC_MEMCTL1_CHANSEL_CHAN_11 0x0000000BU +#define ADC_MEMCTL1_CHANSEL_CHAN_10 0x0000000AU +#define ADC_MEMCTL1_CHANSEL_CHAN_9 0x00000009U +#define ADC_MEMCTL1_CHANSEL_CHAN_8 0x00000008U +#define ADC_MEMCTL1_CHANSEL_CHAN_7 0x00000007U +#define ADC_MEMCTL1_CHANSEL_CHAN_6 0x00000006U +#define ADC_MEMCTL1_CHANSEL_CHAN_5 0x00000005U +#define ADC_MEMCTL1_CHANSEL_CHAN_4 0x00000004U +#define ADC_MEMCTL1_CHANSEL_CHAN_3 0x00000003U +#define ADC_MEMCTL1_CHANSEL_CHAN_2 0x00000002U +#define ADC_MEMCTL1_CHANSEL_CHAN_1 0x00000001U +#define ADC_MEMCTL1_CHANSEL_CHAN_0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MEMCTL2 +// +//***************************************************************************** +// Field: [28] WINCOMP +// +// Enable window comparator. +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_MEMCTL2_WINCOMP 0x10000000U +#define ADC_MEMCTL2_WINCOMP_M 0x10000000U +#define ADC_MEMCTL2_WINCOMP_S 28U +#define ADC_MEMCTL2_WINCOMP_EN 0x10000000U +#define ADC_MEMCTL2_WINCOMP_DIS 0x00000000U + +// Field: [24] TRG +// +// Trigger policy. Indicates if a trigger will be needed to step to the next +// MEMCTL in the sequence or to perform next conversion in the case of repeat +// single channel conversions. +// ENUMs: +// TRIGGER_NEXT Next conversion requires a trigger +// AUTO_NEXT Next conversion is automatic +#define ADC_MEMCTL2_TRG 0x01000000U +#define ADC_MEMCTL2_TRG_M 0x01000000U +#define ADC_MEMCTL2_TRG_S 24U +#define ADC_MEMCTL2_TRG_TRIGGER_NEXT 0x01000000U +#define ADC_MEMCTL2_TRG_AUTO_NEXT 0x00000000U + +// Field: [12] STIME +// +// Selects the source of sample timer period between SCOMP0 and SCOMP1. +// ENUMs: +// SEL_SCOMP1 Select SCOMP1 +// SEL_SCOMP0 Select SCOMP0 +#define ADC_MEMCTL2_STIME 0x00001000U +#define ADC_MEMCTL2_STIME_M 0x00001000U +#define ADC_MEMCTL2_STIME_S 12U +#define ADC_MEMCTL2_STIME_SEL_SCOMP1 0x00001000U +#define ADC_MEMCTL2_STIME_SEL_SCOMP0 0x00000000U + +// Field: [9:8] VRSEL +// +// Voltage reference selection. AREF- must be connected to on-board ground when +// external reference option is selected. +// Note: Writing value 0x3 defaults to INTREF. +// ENUMs: +// INTREF Internal reference +// EXTREF External reference from AREF+/AREF- pins +// VDDS VDDS reference +#define ADC_MEMCTL2_VRSEL_W 2U +#define ADC_MEMCTL2_VRSEL_M 0x00000300U +#define ADC_MEMCTL2_VRSEL_S 8U +#define ADC_MEMCTL2_VRSEL_INTREF 0x00000200U +#define ADC_MEMCTL2_VRSEL_EXTREF 0x00000100U +#define ADC_MEMCTL2_VRSEL_VDDS 0x00000000U + +// Field: [4:0] CHANSEL +// +// Input channel select. +// ENUMs: +// CHAN_15 Selects channel 15 +// CHAN_14 Selects channel 14 +// CHAN_13 Selects channel 13 +// CHAN_12 Selects channel 12 +// CHAN_11 Selects channel 11 +// CHAN_10 Selects channel 10 +// CHAN_9 Selects channel 9 +// CHAN_8 Selects channel 8 +// CHAN_7 Selects channel 7 +// CHAN_6 Selects channel 6 +// CHAN_5 Selects channel 5 +// CHAN_4 Selects channel 4 +// CHAN_3 Selects channel 3 +// CHAN_2 Selects channel 2 +// CHAN_1 Selects channel 1 +// CHAN_0 Selects channel 0 +#define ADC_MEMCTL2_CHANSEL_W 5U +#define ADC_MEMCTL2_CHANSEL_M 0x0000001FU +#define ADC_MEMCTL2_CHANSEL_S 0U +#define ADC_MEMCTL2_CHANSEL_CHAN_15 0x0000000FU +#define ADC_MEMCTL2_CHANSEL_CHAN_14 0x0000000EU +#define ADC_MEMCTL2_CHANSEL_CHAN_13 0x0000000DU +#define ADC_MEMCTL2_CHANSEL_CHAN_12 0x0000000CU +#define ADC_MEMCTL2_CHANSEL_CHAN_11 0x0000000BU +#define ADC_MEMCTL2_CHANSEL_CHAN_10 0x0000000AU +#define ADC_MEMCTL2_CHANSEL_CHAN_9 0x00000009U +#define ADC_MEMCTL2_CHANSEL_CHAN_8 0x00000008U +#define ADC_MEMCTL2_CHANSEL_CHAN_7 0x00000007U +#define ADC_MEMCTL2_CHANSEL_CHAN_6 0x00000006U +#define ADC_MEMCTL2_CHANSEL_CHAN_5 0x00000005U +#define ADC_MEMCTL2_CHANSEL_CHAN_4 0x00000004U +#define ADC_MEMCTL2_CHANSEL_CHAN_3 0x00000003U +#define ADC_MEMCTL2_CHANSEL_CHAN_2 0x00000002U +#define ADC_MEMCTL2_CHANSEL_CHAN_1 0x00000001U +#define ADC_MEMCTL2_CHANSEL_CHAN_0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MEMCTL3 +// +//***************************************************************************** +// Field: [28] WINCOMP +// +// Enable window comparator. +// ENUMs: +// EN Enable +// DIS Disable +#define ADC_MEMCTL3_WINCOMP 0x10000000U +#define ADC_MEMCTL3_WINCOMP_M 0x10000000U +#define ADC_MEMCTL3_WINCOMP_S 28U +#define ADC_MEMCTL3_WINCOMP_EN 0x10000000U +#define ADC_MEMCTL3_WINCOMP_DIS 0x00000000U + +// Field: [24] TRG +// +// Trigger policy. Indicates if a trigger will be needed to step to the next +// MEMCTL in the sequence or to perform next conversion in the case of repeat +// single channel conversions. +// ENUMs: +// TRIGGER_NEXT Next conversion requires a trigger +// AUTO_NEXT Next conversion is automatic +#define ADC_MEMCTL3_TRG 0x01000000U +#define ADC_MEMCTL3_TRG_M 0x01000000U +#define ADC_MEMCTL3_TRG_S 24U +#define ADC_MEMCTL3_TRG_TRIGGER_NEXT 0x01000000U +#define ADC_MEMCTL3_TRG_AUTO_NEXT 0x00000000U + +// Field: [12] STIME +// +// Selects the source of sample timer period between SCOMP0 and SCOMP1. +// ENUMs: +// SEL_SCOMP1 Select SCOMP1 +// SEL_SCOMP0 Select SCOMP0 +#define ADC_MEMCTL3_STIME 0x00001000U +#define ADC_MEMCTL3_STIME_M 0x00001000U +#define ADC_MEMCTL3_STIME_S 12U +#define ADC_MEMCTL3_STIME_SEL_SCOMP1 0x00001000U +#define ADC_MEMCTL3_STIME_SEL_SCOMP0 0x00000000U + +// Field: [9:8] VRSEL +// +// Voltage reference selection. AREF- must be connected to on-board ground when +// external reference option is selected. +// Note: Writing value 0x3 defaults to INTREF. +// ENUMs: +// INTREF Internal reference +// EXTREF External reference from AREF+/AREF- pins +// VDDS VDDS reference +#define ADC_MEMCTL3_VRSEL_W 2U +#define ADC_MEMCTL3_VRSEL_M 0x00000300U +#define ADC_MEMCTL3_VRSEL_S 8U +#define ADC_MEMCTL3_VRSEL_INTREF 0x00000200U +#define ADC_MEMCTL3_VRSEL_EXTREF 0x00000100U +#define ADC_MEMCTL3_VRSEL_VDDS 0x00000000U + +// Field: [4:0] CHANSEL +// +// Input channel select. +// ENUMs: +// CHAN_15 Selects channel 15 +// CHAN_14 Selects channel 14 +// CHAN_13 Selects channel 13 +// CHAN_12 Selects channel 12 +// CHAN_11 Selects channel 11 +// CHAN_10 Selects channel 10 +// CHAN_9 Selects channel 9 +// CHAN_8 Selects channel 8 +// CHAN_7 Selects channel 7 +// CHAN_6 Selects channel 6 +// CHAN_5 Selects channel 5 +// CHAN_4 Selects channel 4 +// CHAN_3 Selects channel 3 +// CHAN_2 Selects channel 2 +// CHAN_1 Selects channel 1 +// CHAN_0 Selects channel 0 +#define ADC_MEMCTL3_CHANSEL_W 5U +#define ADC_MEMCTL3_CHANSEL_M 0x0000001FU +#define ADC_MEMCTL3_CHANSEL_S 0U +#define ADC_MEMCTL3_CHANSEL_CHAN_15 0x0000000FU +#define ADC_MEMCTL3_CHANSEL_CHAN_14 0x0000000EU +#define ADC_MEMCTL3_CHANSEL_CHAN_13 0x0000000DU +#define ADC_MEMCTL3_CHANSEL_CHAN_12 0x0000000CU +#define ADC_MEMCTL3_CHANSEL_CHAN_11 0x0000000BU +#define ADC_MEMCTL3_CHANSEL_CHAN_10 0x0000000AU +#define ADC_MEMCTL3_CHANSEL_CHAN_9 0x00000009U +#define ADC_MEMCTL3_CHANSEL_CHAN_8 0x00000008U +#define ADC_MEMCTL3_CHANSEL_CHAN_7 0x00000007U +#define ADC_MEMCTL3_CHANSEL_CHAN_6 0x00000006U +#define ADC_MEMCTL3_CHANSEL_CHAN_5 0x00000005U +#define ADC_MEMCTL3_CHANSEL_CHAN_4 0x00000004U +#define ADC_MEMCTL3_CHANSEL_CHAN_3 0x00000003U +#define ADC_MEMCTL3_CHANSEL_CHAN_2 0x00000002U +#define ADC_MEMCTL3_CHANSEL_CHAN_1 0x00000001U +#define ADC_MEMCTL3_CHANSEL_CHAN_0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_MEMRES0 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary: +// The conversion results are right aligned. In 10 and 8 bit modes, the unused +// MSB bits are forced to 0. +// If DF = 1, 2s-complement format: +// The conversion results are left aligned. In 10 and 8 bit modes, the unused +// LSB bits are forced to 0. +// The data is stored in the right-justified format and is converted to the +// left-justified 2s-complement format during read back. +// +#define ADC_MEMRES0_DATA_W 16U +#define ADC_MEMRES0_DATA_M 0x0000FFFFU +#define ADC_MEMRES0_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_MEMRES1 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary: +// The conversion results are right aligned. In 10 and 8 bit modes, the unused +// MSB bits are forced to 0. +// If DF = 1, 2s-complement format: +// The conversion results are left aligned. In 10 and 8 bit modes, the unused +// LSB bits are forced to 0. +// The data is stored in the right-justified format and is converted to the +// left-justified 2s-complement format during read back. +// +#define ADC_MEMRES1_DATA_W 16U +#define ADC_MEMRES1_DATA_M 0x0000FFFFU +#define ADC_MEMRES1_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_MEMRES2 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary: +// The conversion results are right aligned. In 10 and 8 bit modes, the unused +// MSB bits are forced to 0. +// If DF = 1, 2s-complement format: +// The conversion results are left aligned. In 10 and 8 bit modes, the unused +// LSB bits are forced to 0. +// The data is stored in the right-justified format and is converted to the +// left-justified 2s-complement format during read back. +// +#define ADC_MEMRES2_DATA_W 16U +#define ADC_MEMRES2_DATA_M 0x0000FFFFU +#define ADC_MEMRES2_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_MEMRES3 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// If DF = 0, unsigned binary: +// The conversion results are right aligned. In 10 and 8 bit modes, the unused +// MSB bits are forced to 0. +// If DF = 1, 2s-complement format: +// The conversion results are left aligned. In 10 and 8 bit modes, the unused +// LSB bits are forced to 0. +// The data is stored in the right-justified format and is converted to the +// left-justified 2s-complement format during read back. +// +#define ADC_MEMRES3_DATA_W 16U +#define ADC_MEMRES3_DATA_M 0x0000FFFFU +#define ADC_MEMRES3_DATA_S 0U + +//***************************************************************************** +// +// Register: ADC_O_STA +// +//***************************************************************************** +// Field: [2] ASCACT +// +// ASC active +// ENUMs: +// ACTIVE ASC active +// IDLE Idle or done +#define ADC_STA_ASCACT 0x00000004U +#define ADC_STA_ASCACT_M 0x00000004U +#define ADC_STA_ASCACT_S 2U +#define ADC_STA_ASCACT_ACTIVE 0x00000004U +#define ADC_STA_ASCACT_IDLE 0x00000000U + +// Field: [0] BUSY +// +// Busy. This bit indicates that an active ADC sample or conversion operation +// is in progress. +// ENUMs: +// ACTIVE ADC sampling or conversion is in progress. +// IDLE No ADC sampling or conversion in progress. +#define ADC_STA_BUSY 0x00000001U +#define ADC_STA_BUSY_M 0x00000001U +#define ADC_STA_BUSY_S 0U +#define ADC_STA_BUSY_ACTIVE 0x00000001U +#define ADC_STA_BUSY_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_TEST0 +// +//***************************************************************************** +// Field: [30] ATEST0_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADC_TEST0_ATEST0_EN 0x40000000U +#define ADC_TEST0_ATEST0_EN_M 0x40000000U +#define ADC_TEST0_ATEST0_EN_S 30U +#define ADC_TEST0_ATEST0_EN_EN 0x40000000U +#define ADC_TEST0_ATEST0_EN_DIS 0x00000000U + +// Field: [29] ATEST1_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADC_TEST0_ATEST1_EN 0x20000000U +#define ADC_TEST0_ATEST1_EN_M 0x20000000U +#define ADC_TEST0_ATEST1_EN_S 29U +#define ADC_TEST0_ATEST1_EN_EN 0x20000000U +#define ADC_TEST0_ATEST1_EN_DIS 0x00000000U + +// Field: [12:8] ATEST1_MUXSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL16 Internal. Only to be used through TI provided API. +// VAL8 Internal. Only to be used through TI provided API. +// VAL4 Internal. Only to be used through TI provided API. +// VAL2 Internal. Only to be used through TI provided API. +// VAL1 Internal. Only to be used through TI provided API. +#define ADC_TEST0_ATEST1_MUXSEL_W 5U +#define ADC_TEST0_ATEST1_MUXSEL_M 0x00001F00U +#define ADC_TEST0_ATEST1_MUXSEL_S 8U +#define ADC_TEST0_ATEST1_MUXSEL_VAL16 0x00001000U +#define ADC_TEST0_ATEST1_MUXSEL_VAL8 0x00000800U +#define ADC_TEST0_ATEST1_MUXSEL_VAL4 0x00000400U +#define ADC_TEST0_ATEST1_MUXSEL_VAL2 0x00000200U +#define ADC_TEST0_ATEST1_MUXSEL_VAL1 0x00000100U + +// Field: [4:0] ATEST0_MUXSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL16 Internal. Only to be used through TI provided API. +// VAL8 Internal. Only to be used through TI provided API. +// VAL4 Internal. Only to be used through TI provided API. +// VAL2 Internal. Only to be used through TI provided API. +// VAL1 Internal. Only to be used through TI provided API. +#define ADC_TEST0_ATEST0_MUXSEL_W 5U +#define ADC_TEST0_ATEST0_MUXSEL_M 0x0000001FU +#define ADC_TEST0_ATEST0_MUXSEL_S 0U +#define ADC_TEST0_ATEST0_MUXSEL_VAL16 0x00000010U +#define ADC_TEST0_ATEST0_MUXSEL_VAL8 0x00000008U +#define ADC_TEST0_ATEST0_MUXSEL_VAL4 0x00000004U +#define ADC_TEST0_ATEST0_MUXSEL_VAL2 0x00000002U +#define ADC_TEST0_ATEST0_MUXSEL_VAL1 0x00000001U + +//***************************************************************************** +// +// Register: ADC_O_TEST2 +// +//***************************************************************************** +// Field: [31] CDAC_OVST_EN +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST2_CDAC_OVST_EN 0x80000000U +#define ADC_TEST2_CDAC_OVST_EN_M 0x80000000U +#define ADC_TEST2_CDAC_OVST_EN_S 31U + +// Field: [24] LATCH_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST2_LATCH_TRIM_EN 0x01000000U +#define ADC_TEST2_LATCH_TRIM_EN_M 0x01000000U +#define ADC_TEST2_LATCH_TRIM_EN_S 24U + +// Field: [20] COMP_GAIN_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST2_COMP_GAIN_TRIM 0x00100000U +#define ADC_TEST2_COMP_GAIN_TRIM_M 0x00100000U +#define ADC_TEST2_COMP_GAIN_TRIM_S 20U + +// Field: [8] MUX_TEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST2_MUX_TEST_SEL 0x00000100U +#define ADC_TEST2_MUX_TEST_SEL_M 0x00000100U +#define ADC_TEST2_MUX_TEST_SEL_S 8U + +//***************************************************************************** +// +// Register: ADC_O_TEST3 +// +//***************************************************************************** +// Field: [31:0] CAL_ACUML +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST3_CAL_ACUML_W 32U +#define ADC_TEST3_CAL_ACUML_M 0xFFFFFFFFU +#define ADC_TEST3_CAL_ACUML_S 0U + +//***************************************************************************** +// +// Register: ADC_O_TEST4 +// +//***************************************************************************** +// Field: [31] HW_STEP_SEL_DIS +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST4_HW_STEP_SEL_DIS 0x80000000U +#define ADC_TEST4_HW_STEP_SEL_DIS_M 0x80000000U +#define ADC_TEST4_HW_STEP_SEL_DIS_S 31U + +// Field: [24] CAL_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST4_CAL_MODE_EN 0x01000000U +#define ADC_TEST4_CAL_MODE_EN_M 0x01000000U +#define ADC_TEST4_CAL_MODE_EN_S 24U + +// Field: [21:16] CAL_STEP_SEL +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST4_CAL_STEP_SEL_W 6U +#define ADC_TEST4_CAL_STEP_SEL_M 0x003F0000U +#define ADC_TEST4_CAL_STEP_SEL_S 16U + +//***************************************************************************** +// +// Register: ADC_O_TEST5 +// +//***************************************************************************** +// Field: [9:0] CAL_CAP_CTL +// +// Internal. Only to be used through TI provided API. +#define ADC_TEST5_CAL_CAP_CTL_W 10U +#define ADC_TEST5_CAL_CAP_CTL_M 0x000003FFU +#define ADC_TEST5_CAL_CAP_CTL_S 0U + +//***************************************************************************** +// +// Register: ADC_O_TEST6 +// +//***************************************************************************** +// Field: [3:0] ATESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL8 Internal. Only to be used through TI provided API. +// VAL4 Internal. Only to be used through TI provided API. +// VAL2 Internal. Only to be used through TI provided API. +// VAL1 Internal. Only to be used through TI provided API. +// VAL0 Internal. Only to be used through TI provided API. +#define ADC_TEST6_ATESTSEL_W 4U +#define ADC_TEST6_ATESTSEL_M 0x0000000FU +#define ADC_TEST6_ATESTSEL_S 0U +#define ADC_TEST6_ATESTSEL_VAL8 0x00000008U +#define ADC_TEST6_ATESTSEL_VAL4 0x00000004U +#define ADC_TEST6_ATESTSEL_VAL2 0x00000002U +#define ADC_TEST6_ATESTSEL_VAL1 0x00000001U +#define ADC_TEST6_ATESTSEL_VAL0 0x00000000U + +//***************************************************************************** +// +// Register: ADC_O_DEBUG1 +// +//***************************************************************************** +// Field: [31:0] CTRL +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG1_CTRL_W 32U +#define ADC_DEBUG1_CTRL_M 0xFFFFFFFFU +#define ADC_DEBUG1_CTRL_S 0U + +//***************************************************************************** +// +// Register: ADC_O_DEBUG2 +// +//***************************************************************************** +// Field: [29:28] VTOI_CTRL +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG2_VTOI_CTRL_W 2U +#define ADC_DEBUG2_VTOI_CTRL_M 0x30000000U +#define ADC_DEBUG2_VTOI_CTRL_S 28U + +// Field: [24] VTOI_TESTMODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG2_VTOI_TESTMODE_EN 0x01000000U +#define ADC_DEBUG2_VTOI_TESTMODE_EN_M 0x01000000U +#define ADC_DEBUG2_VTOI_TESTMODE_EN_S 24U + +//***************************************************************************** +// +// Register: ADC_O_DEBUG3 +// +//***************************************************************************** +// Field: [5] DEC1_DIS +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG3_DEC1_DIS 0x00000020U +#define ADC_DEBUG3_DEC1_DIS_M 0x00000020U +#define ADC_DEBUG3_DEC1_DIS_S 5U + +// Field: [4] DEC0_DIS +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG3_DEC0_DIS 0x00000010U +#define ADC_DEBUG3_DEC0_DIS_M 0x00000010U +#define ADC_DEBUG3_DEC0_DIS_S 4U + +// Field: [0] BOOST_ENZ +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG3_BOOST_ENZ 0x00000001U +#define ADC_DEBUG3_BOOST_ENZ_M 0x00000001U +#define ADC_DEBUG3_BOOST_ENZ_S 0U + +//***************************************************************************** +// +// Register: ADC_O_DEBUG4 +// +//***************************************************************************** +// Field: [15:0] ADC_CTRL0 +// +// Internal. Only to be used through TI provided API. +#define ADC_DEBUG4_ADC_CTRL0_W 16U +#define ADC_DEBUG4_ADC_CTRL0_M 0x0000FFFFU +#define ADC_DEBUG4_ADC_CTRL0_S 0U + + +#endif // __ADC__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_aes.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_aes.h new file mode 100644 index 00000000..730920d3 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_aes.h @@ -0,0 +1,1341 @@ +/****************************************************************************** +* Filename: hw_aes_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AES component +// +//***************************************************************************** +// Description Register. +#define AES_O_DESC 0x00000000U + +// Trigger +#define AES_O_TRG 0x00000010U + +// Abort +#define AES_O_ABORT 0x00000014U + +// Clear +#define AES_O_CLR 0x00000018U + +// Status +#define AES_O_STA 0x0000001CU + +// Direct Memory Access +#define AES_O_DMA 0x00000020U + +// DMA Channel A data transfer +#define AES_O_DMACHA 0x00000024U + +// DMA Channel B data transfer +#define AES_O_DMACHB 0x00000028U + +// Automatic Configuration +#define AES_O_AUTOCFG 0x0000002CU + +// Key Word 0 +#define AES_O_KEY0 0x00000050U + +// Key Word 1 +#define AES_O_KEY1 0x00000054U + +// Key Word 2 +#define AES_O_KEY2 0x00000058U + +// Key Word 3 +#define AES_O_KEY3 0x0000005CU + +// Text Word 0 +#define AES_O_TXT0 0x00000070U + +// Text Word 1 +#define AES_O_TXT1 0x00000074U + +// Text Word 2 +#define AES_O_TXT2 0x00000078U + +// Text Word 3 +#define AES_O_TXT3 0x0000007CU + +// Text Word 0 XOR +#define AES_O_TXTX0 0x00000080U + +// Text Word 1 XOR +#define AES_O_TXTX1 0x00000084U + +// Text Word 2 XOR +#define AES_O_TXTX2 0x00000088U + +// Text Word 3 XOR +#define AES_O_TXTX3 0x0000008CU + +// Buffer Word 0 +#define AES_O_BUF0 0x00000090U + +// Buffer Word 1 +#define AES_O_BUF1 0x00000094U + +// Buffer Word 2 +#define AES_O_BUF2 0x00000098U + +// Buffer Word 3 +#define AES_O_BUF3 0x0000009CU + +// Text Word 0 XOR Buffer Word 0 +#define AES_O_TXTXBUF0 0x000000A0U + +// Text Word 1 XOR Buffer Word 1 +#define AES_O_TXTXBUF1 0x000000A4U + +// Text Word 2 XOR Buffer Word 2 +#define AES_O_TXTXBUF2 0x000000A8U + +// Text Word 3 XOR Buffer Word3 +#define AES_O_TXTXBUF3 0x000000ACU + +// Interrupt Mask register +#define AES_O_IMASK 0x00000104U + +// Raw Interrupt Status register +#define AES_O_RIS 0x00000108U + +// Masked Interrupt Status register +#define AES_O_MIS 0x0000010CU + +// Interrupt Set register +#define AES_O_ISET 0x00000110U + +// Interrupt Clear register +#define AES_O_ICLR 0x00000114U + +// Interrupt Mask Set register +#define AES_O_IMSET 0x00000118U + +// Interrupt Mask Clear register +#define AES_O_IMCLR 0x0000011CU + +//***************************************************************************** +// +// Register: AES_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module Identifier +// This register is used to uniquely identify this IP. +#define AES_DESC_MODID_W 16U +#define AES_DESC_MODID_M 0xFFFF0000U +#define AES_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset +// Standard IP MMRs are the set from aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist. +// +// 0x1-0xF: Standard IP MMRs begin at offset of 64*STDIPOFF from the base IP +// address. +#define AES_DESC_STDIPOFF_W 4U +#define AES_DESC_STDIPOFF_M 0x0000F000U +#define AES_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number +// If multiple instances of IP exist in the device, this field can +// identify the instance number (0-15). +#define AES_DESC_INSTIDX_W 4U +#define AES_DESC_INSTIDX_M 0x00000F00U +#define AES_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15) +#define AES_DESC_MAJREV_W 4U +#define AES_DESC_MAJREV_M 0x000000F0U +#define AES_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor Revision of IP(0-15) +#define AES_DESC_MINREV_W 4U +#define AES_DESC_MINREV_M 0x0000000FU +#define AES_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: AES_O_TRG +// +//***************************************************************************** +// Field: [3] DMACHA +// +// Manually trigger channel A request +// ENUMs: +// SET Triggers channel A request +// NOEFF Writing 0 has no effect +#define AES_TRG_DMACHA 0x00000008U +#define AES_TRG_DMACHA_M 0x00000008U +#define AES_TRG_DMACHA_S 3U +#define AES_TRG_DMACHA_SET 0x00000008U +#define AES_TRG_DMACHA_NOEFF 0x00000000U + +// Field: [2] DMACHB +// +// Manually trigger channel B request +// ENUMs: +// SET Triggers channel B request +// NOEFF Writing 0 has no effect +#define AES_TRG_DMACHB 0x00000004U +#define AES_TRG_DMACHB_M 0x00000004U +#define AES_TRG_DMACHB_S 2U +#define AES_TRG_DMACHB_SET 0x00000004U +#define AES_TRG_DMACHB_NOEFF 0x00000000U + +// Field: [1:0] AESOP +// +// AES Operation +// +// Write an enumerated value to this field when STA.STATE = IDLE to manually +// trigger an AES operation. If condition is not met, the trigger is ignored. +// Non-enumerated values are ignored. +// Enumerated value indicates source of AES operation +// ENUMs: +// TXTXBUF TXT = AES(KEY, TXT XOR BUF) +// BUF TXT = AES(KEY,BUF) +// TXT TXT = AES(KEY,TXT) +#define AES_TRG_AESOP_W 2U +#define AES_TRG_AESOP_M 0x00000003U +#define AES_TRG_AESOP_S 0U +#define AES_TRG_AESOP_TXTXBUF 0x00000003U +#define AES_TRG_AESOP_BUF 0x00000002U +#define AES_TRG_AESOP_TXT 0x00000001U + +//***************************************************************************** +// +// Register: AES_O_ABORT +// +//***************************************************************************** +// Field: [0] ABORTAES +// +// Abort AES operation +// +// Abort an ongoing AES operation. An abort will clear TXT, BUF, DMA, AUTOCFG +// registers +// ENUMs: +// SET Aborts an ongoing AES operation +// NOEFF Writing 0 has no effect +#define AES_ABORT_ABORTAES 0x00000001U +#define AES_ABORT_ABORTAES_M 0x00000001U +#define AES_ABORT_ABORTAES_S 0U +#define AES_ABORT_ABORTAES_SET 0x00000001U +#define AES_ABORT_ABORTAES_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_CLR +// +//***************************************************************************** +// Field: [1] TXT +// +// Clear TXT +// ENUMs: +// CLR Clears TXT +// NOEFF Writing 0 has no effect +#define AES_CLR_TXT 0x00000002U +#define AES_CLR_TXT_M 0x00000002U +#define AES_CLR_TXT_S 1U +#define AES_CLR_TXT_CLR 0x00000002U +#define AES_CLR_TXT_NOEFF 0x00000000U + +// Field: [0] BUF +// +// Clear BUF +// ENUMs: +// CLR Clears BUF +// NOEFF Writing 0 has no effect +#define AES_CLR_BUF 0x00000001U +#define AES_CLR_BUF_M 0x00000001U +#define AES_CLR_BUF_S 0U +#define AES_CLR_BUF_CLR 0x00000001U +#define AES_CLR_BUF_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_STA +// +//***************************************************************************** +// Field: [1] BUFSTA +// +// BUF Status +// +// Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGAES +// = WRBUF3. +// If AUTOCFG.TRGAES != WRBUF3, then STA.BUFSTA will hold the value 0. +// Note : Useful for CBC-MAC +// ENUMs: +// FULL Data stored in BUF is not yet consumed by the AES +// engine. Next block of data cannot be written +// into BUF until STA.STATE = IDLE. +// EMPTY Data stored in BUF is already consumed by the AES +// engine and next block of data can be written in +// BUF. +#define AES_STA_BUFSTA 0x00000002U +#define AES_STA_BUFSTA_M 0x00000002U +#define AES_STA_BUFSTA_S 1U +#define AES_STA_BUFSTA_FULL 0x00000002U +#define AES_STA_BUFSTA_EMPTY 0x00000000U + +// Field: [0] STATE +// +// State +// +// Field gives the state of the AES engine. +// ENUMs: +// BUSY AES operation active +// IDLE AES engine is IDLE +#define AES_STA_STATE 0x00000001U +#define AES_STA_STATE_M 0x00000001U +#define AES_STA_STATE_S 0U +#define AES_STA_STATE_BUSY 0x00000001U +#define AES_STA_STATE_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_DMA +// +//***************************************************************************** +// Field: [19:16] DONEACT +// +// Done Action +// +// This field determines the side effects of DMA done. It is allowed to +// configure this field with an OR-combination of supported enums, with the +// exception that GATE_TRGAES_ON_CHA and GATE_TRGAES_ON_CHA_DEL must be +// mutually exclusive +// ENUMs: +// CLR_TXT_ON_CHB DMA channel B done event clears TXT0 thru TXT3 if +// STA.STATE = IDLE. Event is ignored if condition +// is not met. +// CLR_TXT_ON_CHA DMA channel A done event clears TXT0 thru TXT3 if +// STA.STATE = IDLE. Event is ignored if condition +// is not met. +// GATE_TRGAES_ON_CHA_DEL Delayed gating of triggers defined in +// AUTOCFG.TRGAES +// Due to the pipelining +// of BUF writes, in certain modes, DMA CHA Done +// appears before the last but one AES operation +// has completed. Setting this bit, will gate the +// triggers defined in AUTOCFG.TRGAES only after +// the last write by CHA is consumed by AES FSM. +// Used in ECB,CBC,CBC-MAC modes (having multiple +// blocks encryption/decryption) to avoid spurious +// AES operation triggered on last read by CHB. +// For single mode operation, +// DMA.GATE_TRGAES_ON_CHA must be used. +// GATE_TRGAES_ON_CHA Triggers defined in AUTOCFG.TRGAES are gated when +// RIS.CHADONE = SET +// DIS DMA done has no side effect +#define AES_DMA_DONEACT_W 4U +#define AES_DMA_DONEACT_M 0x000F0000U +#define AES_DMA_DONEACT_S 16U +#define AES_DMA_DONEACT_CLR_TXT_ON_CHB 0x00080000U +#define AES_DMA_DONEACT_CLR_TXT_ON_CHA 0x00040000U +#define AES_DMA_DONEACT_GATE_TRGAES_ON_CHA_DEL 0x00020000U +#define AES_DMA_DONEACT_GATE_TRGAES_ON_CHA 0x00010000U +#define AES_DMA_DONEACT_DIS 0x00000000U + +// Field: [13:12] ADRCHB +// +// Channel B Read Write Address +// +// The DMA accesses DMACHB to read or write contents of TXT and BUF as a +// response to a burst request. This field specifes the start address of the +// first DMA transfer that follows the burst request. The internal address gets +// incremented automatically for subsequent accesses. The DMA can transfer +// 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer +// before re-arbitration. +// ENUMs: +// TXTXBUF0 Start address is TXTXBUF0 +// BUF0 Start address is BUF0 +// TXTX0 Start address is TXTX0 +// TXT0 Start address is TXT0 +#define AES_DMA_ADRCHB_W 2U +#define AES_DMA_ADRCHB_M 0x00003000U +#define AES_DMA_ADRCHB_S 12U +#define AES_DMA_ADRCHB_TXTXBUF0 0x00003000U +#define AES_DMA_ADRCHB_BUF0 0x00002000U +#define AES_DMA_ADRCHB_TXTX0 0x00001000U +#define AES_DMA_ADRCHB_TXT0 0x00000000U + +// Field: [10:8] TRGCHB +// +// Channel B Trigger +// +// Select the condition that triggers DMA channel B request. Non-enumerated +// values are not supported and ignored. +// ENUMs: +// RDTXT3 Reads of TXT3, or TXTXBUF3 trigger request +// WRTXT3 Writes to TXT3, TXTX3, or TXTXBUF3 trigger request +// AESDONE Completion of AES operation triggers request +// AESSTART Start of AES operation triggers request +// DIS DMA requests are disabled +#define AES_DMA_TRGCHB_W 3U +#define AES_DMA_TRGCHB_M 0x00000700U +#define AES_DMA_TRGCHB_S 8U +#define AES_DMA_TRGCHB_RDTXT3 0x00000400U +#define AES_DMA_TRGCHB_WRTXT3 0x00000300U +#define AES_DMA_TRGCHB_AESDONE 0x00000200U +#define AES_DMA_TRGCHB_AESSTART 0x00000100U +#define AES_DMA_TRGCHB_DIS 0x00000000U + +// Field: [5:4] ADRCHA +// +// Channel A Read Write Address +// +// The DMA accesses DMACHA to read or write contents of TXT and BUF as a +// response to a burst request. This field specifes the start address of the +// first DMA transfer that follows the burst request. The internal address gets +// incremented automatically for subsequent accesses. The DMA can transfer +// 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer +// before re-arbitration. +// ENUMs: +// TXTXBUF0 Start address is TXTXBUF0 +// BUF0 Start address is BUF0 +// TXTX0 Start address is TXTX0 +// TXT0 Start address is TXT0 +#define AES_DMA_ADRCHA_W 2U +#define AES_DMA_ADRCHA_M 0x00000030U +#define AES_DMA_ADRCHA_S 4U +#define AES_DMA_ADRCHA_TXTXBUF0 0x00000030U +#define AES_DMA_ADRCHA_BUF0 0x00000020U +#define AES_DMA_ADRCHA_TXTX0 0x00000010U +#define AES_DMA_ADRCHA_TXT0 0x00000000U + +// Field: [2:0] TRGCHA +// +// Channel A Trigger +// +// Select the condition that triggers DMA channel A request. Non-enumerated +// values are not supported and ignored. +// ENUMs: +// RDTXT3 Reads of TXT3 or TXTXBUF3 trigger request +// WRTXT3 Writes to TXT3 or TXTX3 trigger request +// AESDONE Completion of AES operation triggers request +// AESSTART Start of AES operation triggers request +// DIS DMA requests are disabled +#define AES_DMA_TRGCHA_W 3U +#define AES_DMA_TRGCHA_M 0x00000007U +#define AES_DMA_TRGCHA_S 0U +#define AES_DMA_TRGCHA_RDTXT3 0x00000004U +#define AES_DMA_TRGCHA_WRTXT3 0x00000003U +#define AES_DMA_TRGCHA_AESDONE 0x00000002U +#define AES_DMA_TRGCHA_AESSTART 0x00000001U +#define AES_DMA_TRGCHA_DIS 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_DMACHA +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value transferred through DMA Channel A +#define AES_DMACHA_VAL_W 32U +#define AES_DMACHA_VAL_M 0xFFFFFFFFU +#define AES_DMACHA_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_DMACHB +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value transferred through DMA Channel B +#define AES_DMACHB_VAL_W 32U +#define AES_DMACHB_VAL_M 0xFFFFFFFFU +#define AES_DMACHB_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_AUTOCFG +// +//***************************************************************************** +// Field: [28] CHBDNCLR +// +// This field enable auto-clear of RIS.CHBDONE interrupt on read/write of +// TXT3/BUF3/TXTX3/TXTXBUF3 . +// +// ENUMs: +// EN Enable auto-clear of RIS.CHBDONE interrupt +// DIS Disable auto-clear of RIS.CHBDONE interrupt +#define AES_AUTOCFG_CHBDNCLR 0x10000000U +#define AES_AUTOCFG_CHBDNCLR_M 0x10000000U +#define AES_AUTOCFG_CHBDNCLR_S 28U +#define AES_AUTOCFG_CHBDNCLR_EN 0x10000000U +#define AES_AUTOCFG_CHBDNCLR_DIS 0x00000000U + +// Field: [27] CHADNCLR +// +// This field enables auto-clear of RIS.CHADONE interrupt on read/write of +// TXT3/BUF3/TXTX3/TXTXBUF3 . +// +// ENUMs: +// EN Enable auto-clear of RIS.CHADONE interrupt +// DIS Disable auto-clear of RIS.CHADONE interrupt +#define AES_AUTOCFG_CHADNCLR 0x08000000U +#define AES_AUTOCFG_CHADNCLR_M 0x08000000U +#define AES_AUTOCFG_CHADNCLR_S 27U +#define AES_AUTOCFG_CHADNCLR_EN 0x08000000U +#define AES_AUTOCFG_CHADNCLR_DIS 0x00000000U + +// Field: [26] CLRAESST +// +// Clear AES Start +// +// This field enables auto-clear of RIS.AESSTART interrupt on read/write of +// TXT3/BUF3/TXTX3/TXTXBUF3 . +// ENUMs: +// EN Enable auto-clear of RIS.AESSTART interrupt +// DIS Disable auto-clear of RIS.AESSTART interrupt +#define AES_AUTOCFG_CLRAESST 0x04000000U +#define AES_AUTOCFG_CLRAESST_M 0x04000000U +#define AES_AUTOCFG_CLRAESST_S 26U +#define AES_AUTOCFG_CLRAESST_EN 0x04000000U +#define AES_AUTOCFG_CLRAESST_DIS 0x00000000U + +// Field: [25] CLRAESDN +// +// Clear AES Done +// +// This field enables auto-clear of RIS.AESDONE interrupt on read/write of +// TXT3/BUF3/TXTX3/TXTXBUF3 . +// +// ENUMs: +// EN Enable auto-clear of RIS.AESDONE interrupt +// DIS Disable auto-clear of RIS.AESDONE interrupt +#define AES_AUTOCFG_CLRAESDN 0x02000000U +#define AES_AUTOCFG_CLRAESDN_M 0x02000000U +#define AES_AUTOCFG_CLRAESDN_S 25U +#define AES_AUTOCFG_CLRAESDN_EN 0x02000000U +#define AES_AUTOCFG_CLRAESDN_DIS 0x00000000U + +// Field: [24] BUSHALT +// +// Bus Halt +// +// This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF +// when STA.STATE = BUSY. +// ENUMs: +// EN Enable bus halt +// +// When STA.STATE = BUSY, +// access to KEY, TXT, TXTX, TXTXBUF halt the bus +// until STA.STATE = IDLE. +// When STA.STATE = BUSY and +// if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE +// != DISABLE, access to BUF halts the bus until +// STA.STATE = IDLE. +// DIS Disable bus halt +// +// When STA.STATE = BUSY, +// writes to KEY, TXT, TXTX are ignored, reads +// from TXT, TXTXBUF return zero. +// When STA.STATE = BUSY and +// if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE +// != DISABLE, writes to BUF are ignored, reads +// return zero. +#define AES_AUTOCFG_BUSHALT 0x01000000U +#define AES_AUTOCFG_BUSHALT_M 0x01000000U +#define AES_AUTOCFG_BUSHALT_S 24U +#define AES_AUTOCFG_BUSHALT_EN 0x01000000U +#define AES_AUTOCFG_BUSHALT_DIS 0x00000000U + +// Field: [21:19] CTRSIZE +// +// Counter Size +// +// Configures size of counter as either 8,16,32,64 or 128 +// Non-enumerated values are not supported and ignored +// ENUMs: +// CTR128 Configures counter size as 128-bit +// CTR64 Configures counter size as 64-bit +// CTR32 Configures counter size as 32-bit +// CTR16 Configures counter size as 16-bit +// CTR8 Configures counter size as 8-bit +// DIS Disable CTR operation +#define AES_AUTOCFG_CTRSIZE_W 3U +#define AES_AUTOCFG_CTRSIZE_M 0x00380000U +#define AES_AUTOCFG_CTRSIZE_S 19U +#define AES_AUTOCFG_CTRSIZE_CTR128 0x00280000U +#define AES_AUTOCFG_CTRSIZE_CTR64 0x00200000U +#define AES_AUTOCFG_CTRSIZE_CTR32 0x00180000U +#define AES_AUTOCFG_CTRSIZE_CTR16 0x00100000U +#define AES_AUTOCFG_CTRSIZE_CTR8 0x00080000U +#define AES_AUTOCFG_CTRSIZE_DIS 0x00000000U + +// Field: [18] CTRALIGN +// +// Counter Alignment +// +// Specifies alignment of counter +// ENUMs: +// RIGHTALIGN Indicates right aligned counter +// Not applicable when +// counter size is 128-bit +// For 128-bit counter, all +// octets will be considered +// +// If right aligned, octet +// 8-15 will be considered based on endianness and +// counter size +// LEFTALIGN Indicates Left Aligned Counter +// Not applicable for +// 128-bit counter size. +// For 128-bit counter, all +// octets will be considered +// +// When left aligned,,octet +// 0-7 will be considered , based on counter size +// and endianness +#define AES_AUTOCFG_CTRALIGN 0x00040000U +#define AES_AUTOCFG_CTRALIGN_M 0x00040000U +#define AES_AUTOCFG_CTRALIGN_S 18U +#define AES_AUTOCFG_CTRALIGN_RIGHTALIGN 0x00040000U +#define AES_AUTOCFG_CTRALIGN_LEFTALIGN 0x00000000U + +// Field: [17] CTRENDN +// +// Counter Endianness +// +// Specifies Endianness of counter +// ENUMs: +// BIGENDIAN Specifies Big Endian Counter +// Carry will flow from +// octet 'n' to octet 'n-1' +// LITTLEENDIAN Specifies Little Endian Counter +// Carry will flow from +// octet 'n' to octet 'n+1' +#define AES_AUTOCFG_CTRENDN 0x00020000U +#define AES_AUTOCFG_CTRENDN_M 0x00020000U +#define AES_AUTOCFG_CTRENDN_S 17U +#define AES_AUTOCFG_CTRENDN_BIGENDIAN 0x00020000U +#define AES_AUTOCFG_CTRENDN_LITTLEENDIAN 0x00000000U + +// Field: [9:8] TRGTXT +// +// Trigger for TXT +// +// This field determines if and when hardware automatically XORs BUF into TXT. +// Non-enumerated values are not supported and ignored. It is allowed to +// configure this field with an OR-combination of supported enums. +// ENUMs: +// RDTXTXBUF3 Hardware XORs content of BUF into TXT upon read of +// TXTXBUF3 +// RDTXT3 Hardware XORs content of BUF into TXT upon read of +// TXT3 +// DIS No hardware update of TXT +#define AES_AUTOCFG_TRGTXT_W 2U +#define AES_AUTOCFG_TRGTXT_M 0x00000300U +#define AES_AUTOCFG_TRGTXT_S 8U +#define AES_AUTOCFG_TRGTXT_RDTXTXBUF3 0x00000200U +#define AES_AUTOCFG_TRGTXT_RDTXT3 0x00000100U +#define AES_AUTOCFG_TRGTXT_DIS 0x00000000U + +// Field: [5:4] AESSRC +// +// AES Source +// +// This field specifies the data source to hardware-triggered AES operations. +// Non-enumerated values are not supported and ignored. +// ENUMs: +// TXTXBUF TXT = AES(KEY, TXT XOR BUF) +// BUF TXT = AES(KEY,BUF) +// TXT TXT = AES(KEY,TXT) +#define AES_AUTOCFG_AESSRC_W 2U +#define AES_AUTOCFG_AESSRC_M 0x00000030U +#define AES_AUTOCFG_AESSRC_S 4U +#define AES_AUTOCFG_AESSRC_TXTXBUF 0x00000030U +#define AES_AUTOCFG_AESSRC_BUF 0x00000020U +#define AES_AUTOCFG_AESSRC_TXT 0x00000010U + +// Field: [3:0] TRGAES +// +// Trigger Electronic Codebook +// +// This field specifies one or more actions that indirectly trigger AES +// operation. +// It is allowed to configure this field with an OR-combination of supported +// enums. +// ENUMs: +// WRBUF3S Write to BUF3 will schedule to trigger single +// action once STA.STATE is or becomes IDLE. +// Subsequent writes do not trigger action unless +// this setting is written again to this field. +// WRBUF3 All writes to BUF3 will schedule to trigger action +// once STA.STATE is or becomes IDLE, only when +// AUTOCFG.CTRSIZE = DIS +// RDTXT3 All reads of TXT3 or TXTXBUF3 trigger action, only +// when STA.STATE = IDLE +// WRTXT3 All writes to TXT3 or TXTX3 trigger action, only +// when STA.STATE = IDLE +// DIS No user action indirectly triggers AES operation +#define AES_AUTOCFG_TRGAES_W 4U +#define AES_AUTOCFG_TRGAES_M 0x0000000FU +#define AES_AUTOCFG_TRGAES_S 0U +#define AES_AUTOCFG_TRGAES_WRBUF3S 0x00000008U +#define AES_AUTOCFG_TRGAES_WRBUF3 0x00000004U +#define AES_AUTOCFG_TRGAES_RDTXT3 0x00000002U +#define AES_AUTOCFG_TRGAES_WRTXT3 0x00000001U +#define AES_AUTOCFG_TRGAES_DIS 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_KEY0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of KEY[31:0] +#define AES_KEY0_VAL_W 32U +#define AES_KEY0_VAL_M 0xFFFFFFFFU +#define AES_KEY0_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_KEY1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of KEY[63:32] +#define AES_KEY1_VAL_W 32U +#define AES_KEY1_VAL_M 0xFFFFFFFFU +#define AES_KEY1_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_KEY2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of KEY[95:64] +#define AES_KEY2_VAL_W 32U +#define AES_KEY2_VAL_M 0xFFFFFFFFU +#define AES_KEY2_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_KEY3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of KEY[127:96] +#define AES_KEY3_VAL_W 32U +#define AES_KEY3_VAL_M 0xFFFFFFFFU +#define AES_KEY3_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXT0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of TXT[31:0] +#define AES_TXT0_VAL_W 32U +#define AES_TXT0_VAL_M 0xFFFFFFFFU +#define AES_TXT0_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXT1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of TXT[63:32] +#define AES_TXT1_VAL_W 32U +#define AES_TXT1_VAL_M 0xFFFFFFFFU +#define AES_TXT1_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXT2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of TXT[95:64] +#define AES_TXT2_VAL_W 32U +#define AES_TXT2_VAL_M 0xFFFFFFFFU +#define AES_TXT2_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXT3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of TXT[127:96] +// +// AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES +// operation. +#define AES_TXT3_VAL_W 32U +#define AES_TXT3_VAL_M 0xFFFFFFFFU +#define AES_TXT3_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTX0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value in TXT0 will be TXT0.VAL = VAL XOR TXT0.VAL +#define AES_TXTX0_VAL_W 32U +#define AES_TXTX0_VAL_M 0xFFFFFFFFU +#define AES_TXTX0_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTX1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value in TXT1 will be TXT1.VAL = VAL XOR TXT1.VAL +#define AES_TXTX1_VAL_W 32U +#define AES_TXTX1_VAL_M 0xFFFFFFFFU +#define AES_TXTX1_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTX2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value in TXT2 will be TXT2.VAL = VAL XOR TXT2.VAL +#define AES_TXTX2_VAL_W 32U +#define AES_TXTX2_VAL_M 0xFFFFFFFFU +#define AES_TXTX2_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTX3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value in TXT3 will be TXT3.VAL = VAL XOR TXT3.VAL +#define AES_TXTX3_VAL_W 32U +#define AES_TXTX3_VAL_M 0xFFFFFFFFU +#define AES_TXTX3_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_BUF0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of BUF[31:0] +#define AES_BUF0_VAL_W 32U +#define AES_BUF0_VAL_M 0xFFFFFFFFU +#define AES_BUF0_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_BUF1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of BUF[63:32] +#define AES_BUF1_VAL_W 32U +#define AES_BUF1_VAL_M 0xFFFFFFFFU +#define AES_BUF1_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_BUF2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of BUF[95:64] +#define AES_BUF2_VAL_W 32U +#define AES_BUF2_VAL_M 0xFFFFFFFFU +#define AES_BUF2_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_BUF3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value of BUF[127:96] +#define AES_BUF3_VAL_W 32U +#define AES_BUF3_VAL_M 0xFFFFFFFFU +#define AES_BUF3_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTXBUF0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value read will be TXT0.VAL XOR BUF0.VAL +#define AES_TXTXBUF0_VAL_W 32U +#define AES_TXTXBUF0_VAL_M 0xFFFFFFFFU +#define AES_TXTXBUF0_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTXBUF1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value read will be TXT1.VAL XOR BUF1.VAL +#define AES_TXTXBUF1_VAL_W 32U +#define AES_TXTXBUF1_VAL_M 0xFFFFFFFFU +#define AES_TXTXBUF1_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTXBUF2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value read will be TXT2.VAL XOR BUF2.VAL +#define AES_TXTXBUF2_VAL_W 32U +#define AES_TXTXBUF2_VAL_M 0xFFFFFFFFU +#define AES_TXTXBUF2_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_TXTXBUF3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Value read will be TXT3.VAL XOR BUF3.VAL +#define AES_TXTXBUF3_VAL_W 32U +#define AES_TXTXBUF3_VAL_M 0xFFFFFFFFU +#define AES_TXTXBUF3_VAL_S 0U + +//***************************************************************************** +// +// Register: AES_O_IMASK +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// DMA Channel B Done interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define AES_IMASK_CHBDONE 0x00000008U +#define AES_IMASK_CHBDONE_M 0x00000008U +#define AES_IMASK_CHBDONE_S 3U +#define AES_IMASK_CHBDONE_EN 0x00000008U +#define AES_IMASK_CHBDONE_DIS 0x00000000U + +// Field: [2] CHADONE +// +// DMA Channel A Done interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define AES_IMASK_CHADONE 0x00000004U +#define AES_IMASK_CHADONE_M 0x00000004U +#define AES_IMASK_CHADONE_S 2U +#define AES_IMASK_CHADONE_EN 0x00000004U +#define AES_IMASK_CHADONE_DIS 0x00000000U + +// Field: [1] AESSTART +// +// AES Start interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define AES_IMASK_AESSTART 0x00000002U +#define AES_IMASK_AESSTART_M 0x00000002U +#define AES_IMASK_AESSTART_S 1U +#define AES_IMASK_AESSTART_EN 0x00000002U +#define AES_IMASK_AESSTART_DIS 0x00000000U + +// Field: [0] AESDONE +// +// AES Done interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define AES_IMASK_AESDONE 0x00000001U +#define AES_IMASK_AESDONE_M 0x00000001U +#define AES_IMASK_AESDONE_S 0U +#define AES_IMASK_AESDONE_EN 0x00000001U +#define AES_IMASK_AESDONE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_RIS +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Raw Interrupt Status for DMA Channel B Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_RIS_CHBDONE 0x00000008U +#define AES_RIS_CHBDONE_M 0x00000008U +#define AES_RIS_CHBDONE_S 3U +#define AES_RIS_CHBDONE_SET 0x00000008U +#define AES_RIS_CHBDONE_CLR 0x00000000U + +// Field: [2] CHADONE +// +// Raw Interrupt Status for DMA Channel A Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_RIS_CHADONE 0x00000004U +#define AES_RIS_CHADONE_M 0x00000004U +#define AES_RIS_CHADONE_S 2U +#define AES_RIS_CHADONE_SET 0x00000004U +#define AES_RIS_CHADONE_CLR 0x00000000U + +// Field: [1] AESSTART +// +// Raw Interrupt Status for AES Start +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_RIS_AESSTART 0x00000002U +#define AES_RIS_AESSTART_M 0x00000002U +#define AES_RIS_AESSTART_S 1U +#define AES_RIS_AESSTART_SET 0x00000002U +#define AES_RIS_AESSTART_CLR 0x00000000U + +// Field: [0] AESDONE +// +// Raw Interrupt Status for AES Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_RIS_AESDONE 0x00000001U +#define AES_RIS_AESDONE_M 0x00000001U +#define AES_RIS_AESDONE_S 0U +#define AES_RIS_AESDONE_SET 0x00000001U +#define AES_RIS_AESDONE_CLR 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_MIS +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Masked Interrupt Status for DMA Channel B Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_MIS_CHBDONE 0x00000008U +#define AES_MIS_CHBDONE_M 0x00000008U +#define AES_MIS_CHBDONE_S 3U +#define AES_MIS_CHBDONE_SET 0x00000008U +#define AES_MIS_CHBDONE_CLR 0x00000000U + +// Field: [2] CHADONE +// +// Masked Interrupt Status for DMA Channel A Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_MIS_CHADONE 0x00000004U +#define AES_MIS_CHADONE_M 0x00000004U +#define AES_MIS_CHADONE_S 2U +#define AES_MIS_CHADONE_SET 0x00000004U +#define AES_MIS_CHADONE_CLR 0x00000000U + +// Field: [1] AESSTART +// +// Masked Interrupt Status for AES Start +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_MIS_AESSTART 0x00000002U +#define AES_MIS_AESSTART_M 0x00000002U +#define AES_MIS_AESSTART_S 1U +#define AES_MIS_AESSTART_SET 0x00000002U +#define AES_MIS_AESSTART_CLR 0x00000000U + +// Field: [0] AESDONE +// +// Masked Interrupt Status for AES Done +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define AES_MIS_AESDONE 0x00000001U +#define AES_MIS_AESDONE_M 0x00000001U +#define AES_MIS_AESDONE_S 0U +#define AES_MIS_AESDONE_SET 0x00000001U +#define AES_MIS_AESDONE_CLR 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_ISET +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Set DMA Channel B Done interrupt +// ENUMs: +// SET Set interrupt +// NOEFF Writing 0 has no effect +#define AES_ISET_CHBDONE 0x00000008U +#define AES_ISET_CHBDONE_M 0x00000008U +#define AES_ISET_CHBDONE_S 3U +#define AES_ISET_CHBDONE_SET 0x00000008U +#define AES_ISET_CHBDONE_NOEFF 0x00000000U + +// Field: [2] CHADONE +// +// Set DMA Channel A Done interrupt +// ENUMs: +// SET Set interrupt +// NOEFF Writing 0 has no effect +#define AES_ISET_CHADONE 0x00000004U +#define AES_ISET_CHADONE_M 0x00000004U +#define AES_ISET_CHADONE_S 2U +#define AES_ISET_CHADONE_SET 0x00000004U +#define AES_ISET_CHADONE_NOEFF 0x00000000U + +// Field: [1] AESSTART +// +// Set AES Start interrupt +// ENUMs: +// SET Set interrupt +// NOEFF Writing 0 has no effect +#define AES_ISET_AESSTART 0x00000002U +#define AES_ISET_AESSTART_M 0x00000002U +#define AES_ISET_AESSTART_S 1U +#define AES_ISET_AESSTART_SET 0x00000002U +#define AES_ISET_AESSTART_NOEFF 0x00000000U + +// Field: [0] AESDONE +// +// Set AES Done interrupt +// ENUMs: +// SET Set interrupt +// NOEFF Writing 0 has no effect +#define AES_ISET_AESDONE 0x00000001U +#define AES_ISET_AESDONE_M 0x00000001U +#define AES_ISET_AESDONE_S 0U +#define AES_ISET_AESDONE_SET 0x00000001U +#define AES_ISET_AESDONE_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_ICLR +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Clear DMA Channel B Done interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing 0 has no effect +#define AES_ICLR_CHBDONE 0x00000008U +#define AES_ICLR_CHBDONE_M 0x00000008U +#define AES_ICLR_CHBDONE_S 3U +#define AES_ICLR_CHBDONE_CLR 0x00000008U +#define AES_ICLR_CHBDONE_NOEFF 0x00000000U + +// Field: [2] CHADONE +// +// Clear DMA Channel A Done interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing 0 has no effect +#define AES_ICLR_CHADONE 0x00000004U +#define AES_ICLR_CHADONE_M 0x00000004U +#define AES_ICLR_CHADONE_S 2U +#define AES_ICLR_CHADONE_CLR 0x00000004U +#define AES_ICLR_CHADONE_NOEFF 0x00000000U + +// Field: [1] AESSTART +// +// Clear AES Start interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing 0 has no effect +#define AES_ICLR_AESSTART 0x00000002U +#define AES_ICLR_AESSTART_M 0x00000002U +#define AES_ICLR_AESSTART_S 1U +#define AES_ICLR_AESSTART_CLR 0x00000002U +#define AES_ICLR_AESSTART_NOEFF 0x00000000U + +// Field: [0] AESDONE +// +// Clear AES Done interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing 0 has no effect +#define AES_ICLR_AESDONE 0x00000001U +#define AES_ICLR_AESDONE_M 0x00000001U +#define AES_ICLR_AESDONE_S 0U +#define AES_ICLR_AESDONE_CLR 0x00000001U +#define AES_ICLR_AESDONE_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_IMSET +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Set DMA Channel B Done interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMSET_CHBDONE 0x00000008U +#define AES_IMSET_CHBDONE_M 0x00000008U +#define AES_IMSET_CHBDONE_S 3U +#define AES_IMSET_CHBDONE_SET 0x00000008U +#define AES_IMSET_CHBDONE_NOEFF 0x00000000U + +// Field: [2] CHADONE +// +// Set DMA Channel A Done interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMSET_CHADONE 0x00000004U +#define AES_IMSET_CHADONE_M 0x00000004U +#define AES_IMSET_CHADONE_S 2U +#define AES_IMSET_CHADONE_SET 0x00000004U +#define AES_IMSET_CHADONE_NOEFF 0x00000000U + +// Field: [1] AESSTART +// +// Set AES Start interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMSET_AESSTART 0x00000002U +#define AES_IMSET_AESSTART_M 0x00000002U +#define AES_IMSET_AESSTART_S 1U +#define AES_IMSET_AESSTART_SET 0x00000002U +#define AES_IMSET_AESSTART_NOEFF 0x00000000U + +// Field: [0] AESDONE +// +// Set AES Done interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMSET_AESDONE 0x00000001U +#define AES_IMSET_AESDONE_M 0x00000001U +#define AES_IMSET_AESDONE_S 0U +#define AES_IMSET_AESDONE_SET 0x00000001U +#define AES_IMSET_AESDONE_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: AES_O_IMCLR +// +//***************************************************************************** +// Field: [3] CHBDONE +// +// Clear DMA Channel B Done interrupt mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMCLR_CHBDONE 0x00000008U +#define AES_IMCLR_CHBDONE_M 0x00000008U +#define AES_IMCLR_CHBDONE_S 3U +#define AES_IMCLR_CHBDONE_CLR 0x00000008U +#define AES_IMCLR_CHBDONE_NOEFF 0x00000000U + +// Field: [2] CHADONE +// +// Clear DMA Channel A Done interrupt mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMCLR_CHADONE 0x00000004U +#define AES_IMCLR_CHADONE_M 0x00000004U +#define AES_IMCLR_CHADONE_S 2U +#define AES_IMCLR_CHADONE_CLR 0x00000004U +#define AES_IMCLR_CHADONE_NOEFF 0x00000000U + +// Field: [1] AESSTART +// +// Clear AES Start interrupt mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMCLR_AESSTART 0x00000002U +#define AES_IMCLR_AESSTART_M 0x00000002U +#define AES_IMCLR_AESSTART_S 1U +#define AES_IMCLR_AESSTART_CLR 0x00000002U +#define AES_IMCLR_AESSTART_NOEFF 0x00000000U + +// Field: [0] AESDONE +// +// Clear AES Done interrupt mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define AES_IMCLR_AESDONE 0x00000001U +#define AES_IMCLR_AESDONE_M 0x00000001U +#define AES_IMCLR_AESDONE_S 0U +#define AES_IMCLR_AESDONE_CLR 0x00000001U +#define AES_IMCLR_AESDONE_NOEFF 0x00000000U + + +#endif // __AES__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_bpu.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_bpu.h new file mode 100644 index 00000000..69f86c79 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_bpu.h @@ -0,0 +1,485 @@ +/****************************************************************************** +* Filename: hw_bpu_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_BPU_H__ +#define __HW_BPU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// BPU component +// +//***************************************************************************** +// Breakpoint Control Register +#define BPU_O_BP_CTRL 0x00000000U + +// Breakpoint Comparator Register 0 +#define BPU_O_BP_COMP0 0x00000008U + +// Breakpoint Comparator Register 1 +#define BPU_O_BP_COMP1 0x0000000CU + +// Breakpoint Comparator Register 2 +#define BPU_O_BP_COMP2 0x00000010U + +// Breakpoint Comparator Register 3 +#define BPU_O_BP_COMP3 0x00000014U + +// Peripheral ID Register 4 +#define BPU_O_PIDR4 0x00000FD0U + +// Peripheral ID Register 5 +#define BPU_O_PIDR5 0x00000FD4U + +// Peripheral ID Register 6 +#define BPU_O_PIDR6 0x00000FD8U + +// Peripheral ID Register 7 +#define BPU_O_PIDR7 0x00000FDCU + +// Peripheral ID Register 0 +#define BPU_O_PIDR0 0x00000FE0U + +// Peripheral ID Register 1 +#define BPU_O_PIDR1 0x00000FE4U + +// Peripheral ID Register 2 +#define BPU_O_PIDR2 0x00000FE8U + +// Peripheral ID Register 3 +#define BPU_O_PIDR3 0x00000FECU + +// Component ID Register 0 +#define BPU_O_CIDR0 0x00000FF0U + +// Component ID Register 1 +#define BPU_O_CIDR1 0x00000FF4U + +// Component ID Register 2 +#define BPU_O_CIDR2 0x00000FF8U + +// Component ID Register 3 +#define BPU_O_CIDR3 0x00000FFCU + +//***************************************************************************** +// +// Register: BPU_O_BP_CTRL +// +//***************************************************************************** +// Field: [7:4] NUM_CODE +// +// Number of comparators. +#define BPU_BP_CTRL_NUM_CODE_W 4U +#define BPU_BP_CTRL_NUM_CODE_M 0x000000F0U +#define BPU_BP_CTRL_NUM_CODE_S 4U + +// Field: [1] KEY +// +// Key field. To write to the Breakpoint Control Register, you must write a 1 +// to this write-only bit. This bit reads as zero. +#define BPU_BP_CTRL_KEY 0x00000002U +#define BPU_BP_CTRL_KEY_M 0x00000002U +#define BPU_BP_CTRL_KEY_S 1U + +// Field: [0] ENABLE +// +// Breakpoint unit enable bit. DBGRESETn clears the ENABLE bit. +// ENUMs: +// BKPT_EN Breakpoint unit enabled +// BKPT_DIS Breakpoint unit disabled +#define BPU_BP_CTRL_ENABLE 0x00000001U +#define BPU_BP_CTRL_ENABLE_M 0x00000001U +#define BPU_BP_CTRL_ENABLE_S 0U +#define BPU_BP_CTRL_ENABLE_BKPT_EN 0x00000001U +#define BPU_BP_CTRL_ENABLE_BKPT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: BPU_O_BP_COMP0 +// +//***************************************************************************** +// Field: [31:30] BP_MATCH +// +// This selects what happens when the COMP address is matched +// ENUMs: +// BKPT_COMP_BOTH set breakpoint on both lower and upper halfwords +// BKPT_COMP_HI set breakpoint on upper halfword, lower is +// unaffected +// BKPT_COMP_LOW set breakpoint on lower halfword, upper is +// unaffected +// BKPT_COMP_NONE no breakpoint generated +#define BPU_BP_COMP0_BP_MATCH_W 2U +#define BPU_BP_COMP0_BP_MATCH_M 0xC0000000U +#define BPU_BP_COMP0_BP_MATCH_S 30U +#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U +#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_HI 0x80000000U +#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_LOW 0x40000000U +#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_NONE 0x00000000U + +// Field: [28:2] COMP +// +// Comparison address, UNKNOWN on reset. +#define BPU_BP_COMP0_COMP_W 27U +#define BPU_BP_COMP0_COMP_M 0x1FFFFFFCU +#define BPU_BP_COMP0_COMP_S 2U + +// Field: [0] ENABLE +// +// Compare enable for Breakpoint Comparator Register 0. The ENABLE bit of +// BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE +// bit. +// ENUMs: +// BKPT_COMP_DIS Breakpoint Comparator Register 0 compare enabled +// BKPT_COMP_EN Breakpoint Comparator Register 0 compare disabled +#define BPU_BP_COMP0_ENABLE 0x00000001U +#define BPU_BP_COMP0_ENABLE_M 0x00000001U +#define BPU_BP_COMP0_ENABLE_S 0U +#define BPU_BP_COMP0_ENABLE_BKPT_COMP_DIS 0x00000001U +#define BPU_BP_COMP0_ENABLE_BKPT_COMP_EN 0x00000000U + +//***************************************************************************** +// +// Register: BPU_O_BP_COMP1 +// +//***************************************************************************** +// Field: [31:30] BP_MATCH +// +// This selects what happens when the COMP address is matched +// ENUMs: +// BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords +// BKPT_COMP_HI Set breakpoint on upper halfword, lower is +// unaffected +// BKPT_COMP_LOW Set breakpoint on lower halfword, upper is +// unaffected +// BKPT_COMP_NONE No breakpoint generated +#define BPU_BP_COMP1_BP_MATCH_W 2U +#define BPU_BP_COMP1_BP_MATCH_M 0xC0000000U +#define BPU_BP_COMP1_BP_MATCH_S 30U +#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U +#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_HI 0x80000000U +#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_LOW 0x40000000U +#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_NONE 0x00000000U + +// Field: [28:2] COMP +// +// Comparison address. Although it is architecturally Unpredictable whether +// breakpoint matches on the address of the second halfword of a 32-bit +// instruction to generates a debug event, in this processor it is predictable +// and a debug event is generated. +#define BPU_BP_COMP1_COMP_W 27U +#define BPU_BP_COMP1_COMP_M 0x1FFFFFFCU +#define BPU_BP_COMP1_COMP_S 2U + +// Field: [0] ENABLE +// +// Comparison address, UNKNOWN on reset. +// ENUMs: +// BKPT_COMP_DIS Breakpoint Comparator Register 1 compare enabled +// BKPT_COMP_EN Breakpoint Comparator Register 1 compare disabled +#define BPU_BP_COMP1_ENABLE 0x00000001U +#define BPU_BP_COMP1_ENABLE_M 0x00000001U +#define BPU_BP_COMP1_ENABLE_S 0U +#define BPU_BP_COMP1_ENABLE_BKPT_COMP_DIS 0x00000001U +#define BPU_BP_COMP1_ENABLE_BKPT_COMP_EN 0x00000000U + +//***************************************************************************** +// +// Register: BPU_O_BP_COMP2 +// +//***************************************************************************** +// Field: [31:30] BP_MATCH +// +// This selects what happens when the COMP address is matched +// ENUMs: +// BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords +// BKPT_COMP_HI Set breakpoint on upper halfword, lower is +// unaffected +// BKPT_COMP_LOW Set breakpoint on lower halfword, upper is +// unaffected +// BKPT_COMP_NONE No breakpoint matching +#define BPU_BP_COMP2_BP_MATCH_W 2U +#define BPU_BP_COMP2_BP_MATCH_M 0xC0000000U +#define BPU_BP_COMP2_BP_MATCH_S 30U +#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U +#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_HI 0x80000000U +#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_LOW 0x40000000U +#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_NONE 0x00000000U + +// Field: [28:2] COMP +// +// Comparison address, UNKNOWN on reset. +#define BPU_BP_COMP2_COMP_W 27U +#define BPU_BP_COMP2_COMP_M 0x1FFFFFFCU +#define BPU_BP_COMP2_COMP_S 2U + +// Field: [0] ENABLE +// +// Compare enable for Breakpoint Comparator Register 2. The ENABLE bit of +// BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE +// bit. +// ENUMs: +// BKPT_COMP_DIS Breakpoint Comparator Register 2 compare enabled +// BKPT_COMP_EN Breakpoint Comparator Register 2 compare disabled +#define BPU_BP_COMP2_ENABLE 0x00000001U +#define BPU_BP_COMP2_ENABLE_M 0x00000001U +#define BPU_BP_COMP2_ENABLE_S 0U +#define BPU_BP_COMP2_ENABLE_BKPT_COMP_DIS 0x00000001U +#define BPU_BP_COMP2_ENABLE_BKPT_COMP_EN 0x00000000U + +//***************************************************************************** +// +// Register: BPU_O_BP_COMP3 +// +//***************************************************************************** +// Field: [31:30] BP_MATCH +// +// This selects what happens when the COMP address is matched +// ENUMs: +// BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords +// BKPT_COMP_HI Set breakpoint on upper halfword, lower is +// unaffected +// BKPT_COMP_LOW Set breakpoint on lower halfword, upper is +// unaffected +// BKPT_COMP_NONE No breakpoint generated +#define BPU_BP_COMP3_BP_MATCH_W 2U +#define BPU_BP_COMP3_BP_MATCH_M 0xC0000000U +#define BPU_BP_COMP3_BP_MATCH_S 30U +#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U +#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_HI 0x80000000U +#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_LOW 0x40000000U +#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_NONE 0x00000000U + +// Field: [28:2] COMP +// +// Comparison address, UNKNOWN on reset. +#define BPU_BP_COMP3_COMP_W 27U +#define BPU_BP_COMP3_COMP_M 0x1FFFFFFCU +#define BPU_BP_COMP3_COMP_S 2U + +// Field: [0] ENABLE +// +// Compare enable for Breakpoint Comparator Register 3. The ENABLE bit of +// BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE +// bit. +// ENUMs: +// BKPT_COMP_DIS Breakpoint Comparator Register 3 compare enabled +// BKPT_COMP_EN Breakpoint Comparator Register 3 compare disabled +#define BPU_BP_COMP3_ENABLE 0x00000001U +#define BPU_BP_COMP3_ENABLE_M 0x00000001U +#define BPU_BP_COMP3_ENABLE_S 0U +#define BPU_BP_COMP3_ENABLE_BKPT_COMP_DIS 0x00000001U +#define BPU_BP_COMP3_ENABLE_BKPT_COMP_EN 0x00000000U + +//***************************************************************************** +// +// Register: BPU_O_PIDR4 +// +//***************************************************************************** +// Field: [7:4] SIZE +// +// This is a 4-bit value that indicates the total contiguous size of the memory +// window used by this component in powers of 2 from the standard 4KB. If a +// component only requires the standard 4KB then this should read as 0x0, 4KB +// only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. +#define BPU_PIDR4_SIZE_W 4U +#define BPU_PIDR4_SIZE_M 0x000000F0U +#define BPU_PIDR4_SIZE_S 4U + +// Field: [3:0] DES_2 +// +// Number of JEDEC continuation codes. Indicates the designer of the component +// (along with the identity code) +#define BPU_PIDR4_DES_2_W 4U +#define BPU_PIDR4_DES_2_M 0x0000000FU +#define BPU_PIDR4_DES_2_S 0U + +//***************************************************************************** +// +// Register: BPU_O_PIDR5 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: BPU_O_PIDR6 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: BPU_O_PIDR7 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: BPU_O_PIDR0 +// +//***************************************************************************** +// Field: [7:0] PART_0 +// +// Bits [7:0] of the component's part number. This is selected by the designer +// of the component. +#define BPU_PIDR0_PART_0_W 8U +#define BPU_PIDR0_PART_0_M 0x000000FFU +#define BPU_PIDR0_PART_0_S 0U + +//***************************************************************************** +// +// Register: BPU_O_PIDR1 +// +//***************************************************************************** +// Field: [7:4] DES_0 +// +// Bits [3:0] of the JEDEC identity code indicating the designer of the +// component (along with the continuation code) +#define BPU_PIDR1_DES_0_W 4U +#define BPU_PIDR1_DES_0_M 0x000000F0U +#define BPU_PIDR1_DES_0_S 4U + +// Field: [3:0] PART_1 +// +// Bits [11:8] of the component's part number. This is selected by the designer +// of the component. +#define BPU_PIDR1_PART_1_W 4U +#define BPU_PIDR1_PART_1_M 0x0000000FU +#define BPU_PIDR1_PART_1_S 0U + +//***************************************************************************** +// +// Register: BPU_O_PIDR2 +// +//***************************************************************************** +// Field: [7:4] REVISION +// +// The Revision field is an incremental value starting at 0x0 for the first +// design of this component. This only increases by 1 for both major and minor +// revisions and is simply used as a look-up to establish the exact major/minor +// revision. +#define BPU_PIDR2_REVISION_W 4U +#define BPU_PIDR2_REVISION_M 0x000000F0U +#define BPU_PIDR2_REVISION_S 4U + +// Field: [3] JEDEC +// +// Always set. Indicates that a JEDEC assigned value is used +#define BPU_PIDR2_JEDEC 0x00000008U +#define BPU_PIDR2_JEDEC_M 0x00000008U +#define BPU_PIDR2_JEDEC_S 3U + +// Field: [2:0] DES_1 +// +// Bits [6:4] of the JEDEC identity code indicating the designer of the +// component (along with the continuation code) +#define BPU_PIDR2_DES_1_W 3U +#define BPU_PIDR2_DES_1_M 0x00000007U +#define BPU_PIDR2_DES_1_S 0U + +//***************************************************************************** +// +// Register: BPU_O_PIDR3 +// +//***************************************************************************** +// Field: [7:4] REVAND +// +// This field indicates minor errata fixes specific to this design, for example +// metal fixes after implementation. In most cases this field is zero. It is +// recommended that component designers ensure this field can be changed by a +// metal fix if required, for example by driving it from registers that reset +// to zero. +#define BPU_PIDR3_REVAND_W 4U +#define BPU_PIDR3_REVAND_M 0x000000F0U +#define BPU_PIDR3_REVAND_S 4U + +// Field: [3:0] CMOD +// +// Where the component is reusable IP, this value indicates if the customer has +// modified the behavior of the component. In most cases this field is zero. +#define BPU_PIDR3_CMOD_W 4U +#define BPU_PIDR3_CMOD_M 0x0000000FU +#define BPU_PIDR3_CMOD_S 0U + +//***************************************************************************** +// +// Register: BPU_O_CIDR0 +// +//***************************************************************************** +// Field: [7:0] PRMBL_0 +// +// Contains bits [7:0] of the component identification +#define BPU_CIDR0_PRMBL_0_W 8U +#define BPU_CIDR0_PRMBL_0_M 0x000000FFU +#define BPU_CIDR0_PRMBL_0_S 0U + +//***************************************************************************** +// +// Register: BPU_O_CIDR1 +// +//***************************************************************************** +// Field: [7:4] CLASS +// +// Class of the component. E.g. ROM table, CoreSight component etc. Constitutes +// bits [15:12] of the component identification. +#define BPU_CIDR1_CLASS_W 4U +#define BPU_CIDR1_CLASS_M 0x000000F0U +#define BPU_CIDR1_CLASS_S 4U + +// Field: [3:0] PRMBL_1 +// +// Contains bits [11:8] of the component identification +#define BPU_CIDR1_PRMBL_1_W 4U +#define BPU_CIDR1_PRMBL_1_M 0x0000000FU +#define BPU_CIDR1_PRMBL_1_S 0U + +//***************************************************************************** +// +// Register: BPU_O_CIDR2 +// +//***************************************************************************** +// Field: [7:0] PRMBL_2 +// +// Contains bits [23:16] of the component identification +#define BPU_CIDR2_PRMBL_2_W 8U +#define BPU_CIDR2_PRMBL_2_M 0x000000FFU +#define BPU_CIDR2_PRMBL_2_S 0U + +//***************************************************************************** +// +// Register: BPU_O_CIDR3 +// +//***************************************************************************** +// Field: [7:0] PRMBL_3 +// +// Contains bits [31:24] of the component identification +#define BPU_CIDR3_PRMBL_3_W 8U +#define BPU_CIDR3_PRMBL_3_M 0x000000FFU +#define BPU_CIDR3_PRMBL_3_S 0U + + +#endif // __BPU__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h new file mode 100644 index 00000000..217aa5f6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h @@ -0,0 +1,236 @@ +/****************************************************************************** +* Copyright (c) 2021-2023 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +****************************************************************************** +* \file hw_ccfg.h +* +* \brief Customer Configuration (CCFG) header file. +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +#include +#include "hw_device.h" + +/*! CCFG sector data structure definition + * This structure should be allocated at the base of CCFG section defined in + * the linker file. + */ +typedef struct { + + // Bootloader/application configuration + struct { // [0]: length 16B + // Pointer to user bootloader vector table + void* pBldrVtor; + #define CCFG_BC_PBLDR_USE_FCFG ((void*)0xFFFFFFF0) + #define XCFG_BC_PBLDR_FORBID ((void*)0xFFFFFFFC) + #define XCFG_BC_PBLDR_UNDEF ((void*)0xFFFFFFFF) + #define CCFG_BC_PBLDR_VALID(x) ((x) < CCFG_BC_PBLDR_USE_FCFG) + // Parameter passed to bootloader + union { + uint32_t val32; + #define CCFG_BC_BLDRCFG_UNDEF 0xFFFFFFFF + // Serial ROM bootloader parameters (also used in FCFG.h) + struct serialRomBldrParam_struct { + uint32_t bldrEnabled : 1; + #define XCFG_BC_BLDR_DIS 0 + #define XCFG_BC_BLDR_EN 1 + uint32_t pinTriggerEnabled : 1; + #define XCFG_BC_PINTRIG_DIS 0 + #define XCFG_BC_PINTRIG_EN 1 + uint32_t pinTriggerLevel : 1; + #define XCFG_BC_PINTRIG_LEVEL_LO 0 + #define XCFG_BC_PINTRIG_LEVEL_HI 1 + uint32_t res0 : 13; + uint32_t pinTriggerDio : 6; + uint32_t res1 : 2; + uint32_t serialIoCfgIndex : 3; + #define XCFG_BC_IOCFGIND_DEFAULT 0 + uint32_t res2 : 5; + } serialRomBldrParamStruct; + } bldrParam; + // Pointer to application VTOR table + void* pAppVtor; + #define CCFG_BC_PAPP_NONE ((void*)0xFFFFFFFF) + uint32_t crc32; + } bootCfg; + + + // Paperspin options [16]: length 8 B + // Defines peripheral/feature availability and accessible memory. Allows + // customer to target a paperspin device features on a superset device + // AND-combined with FCFG.hwOpts. + uint32_t hwOpts[2]; + + + // Device permissions [24]: length 4 B + // This is maximally-restrictive combined with similar field in FCFG + struct { + #define CCFG_PERMISSION_ALLOW 0xA + #define CCFG_PERMISSION_FORBID 0x0 + // (all other value other than ALLOW are interpreted as FORBID) + uint32_t allowReturnToFactory : 4; + uint32_t allowFakeStby : 4; + uint32_t allowToolsClientMode : 4; + uint32_t allowChipErase : 4; + uint32_t allowFlashProgram : 4; + uint32_t allowFlashVerify : 4; + uint32_t allowEnergyTrace : 4; + uint32_t allowDebugPort : 4; + } permissions; + + + // Miscellaneous fields [28]: length 4B + struct { + // SACI timeout is infinite when 0, else (2^saciTimeoutExp)*64 ms + // Fcfg timeout applied instead if CCfg.saciTimeoutOverride==0 + uint32_t saciTimeoutExp : 3; + #define XCFG_MISC_SACITOEXP_8SEC 7 + #define XCFG_MISC_SACITOEXP_1SEC 4 + #define XCFG_MISC_SACITOEXP_INFINITE 0 + uint32_t saciTimeoutOverride : 1; + uint32_t res0 : 28; + } misc; + + + // Flash protection [32]: length 32 B + // This is maximally-restrictive combined with similar field in FCFG + struct { + struct { + // Sticky-0 bits written to VIMS.WEPRA (sectors 0-31, 1/bit) + uint32_t mainSectors0_31; + union { + // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) + uint32_t mainSectors32_255; + // Dummy symbol to allow code to remain the same across devices + uint32_t mainSectors256_511; + }; + // Sticky-0 bit written to VIMS.WEPRAUX + union { + uint32_t auxSectors; + struct { + uint32_t ccfgSector : 1; + uint32_t fcfgSector : 1; + uint32_t engrSector : 1; + uint32_t res1 : 29; + }; + }; + } writeEraseProt; + uint32_t res; + struct { + // Set bits (sectors 0-31, 1/bit) define what a chip erase command can optionally retain + uint32_t mainSectors0_31; + union { + // Set bits (sectors 32-255, 8/bit) define what a chip erase command can optionally retain + uint32_t mainSectors32_255; + // Dummy field to allow code to remain same across devices + uint32_t mainSectors256_511; + }; + } chipEraseRetain; + // Reserved for future flash increases + uint32_t res0[2]; + } flashProt; + + + // Optional HW initialization copy-list [64]: length x B + // Copy list applied before user application is entered. May be used by customer/SYSCFG to + // initialize hardware right before application is entered. + // Also used to pad out CCFG to correct size + uint32_t hwInitCopyList[(FLASH_1T_SECTOR_SIZE / 4) - 61]; + // Simple macros to assist in initializing copy lists + // NOTE: Addresses to CPYLIST_CPY must fulfill ((a&0x0FF00003)==0). + // The memory map ensures this for SRAM and peripherals. + // There is no check as ELF only supports {symbol + const offset} + #define CPYLST_EOL 0 + #define CPYLST_NOP 0x10000000 + #define CPYLST_WAIT(x) ( 0x10000000 + (((x)<<2)&0x000FFFFC) ) + #define CPYLST_CPY(a, n) ( ((uint32_t)(a)) + (((n)<<20)&0x0FF00000) ) + #define CPYLST_CPYFULLADDR(a) (((uint32_t)(a)) + 1) + #define CPYLST_JUMP(a) (((uint32_t)(a)) + 2) + #define CPYLST_CALL(a) (((uint32_t)(a)) + 3) + + + // CRC across hwOpts through hwInitCopyList + // [End-180]: length 4B + uint32_t crc32; + + + // User record (programmable also through separate SACI command), no dependencies in boot code + // User record size is fixed at 128 B. Last word assumed to be CRC over first 124 B (optional) + #define CCFG_USER_RECORD_SIZE 128 + union { // [End-176]: length 128B + // Generic 32b record layout + uint32_t val32[(CCFG_USER_RECORD_SIZE/4)]; + // Generic 8b record layout + uint8_t val8[CCFG_USER_RECORD_SIZE]; + // CRC field in last word + struct { + uint32_t res0[CCFG_USER_RECORD_SIZE/4-1]; + uint32_t crc32; + }; + } userRecord; + + // Debug configuration and password + struct { // [End-48]: length 48B + // Debug authorization requirements + uint8_t authorization; + #define CCFG_DBGAUTH_REQPWD 0xA5 + #define CCFG_DBGAUTH_DBGOPEN 0x5A + #define CCFG_DBGAUTH_DBGFORBID 0x00 + // (and any other value) + // Allow debugging of bootloader + uint8_t allowBldr; + #define CCFG_DBGBLDR_ALLOW 0xA5 + #define CCFG_DBGBLDR_FORBID 0x00 + // (and any other value) + uint8_t res0[2]; + // 64b password ID value (may be used to calculate or look up debug password) + uint8_t pwdId[8]; + // SHA256 hash of debug password + uint8_t pwdHash[32]; + // CRC32 of previous fields in debugCfg + uint32_t crc32; + } debugCfg; + +} ccfg_t; + + +/*! Typedef of substruct as it is also used in hw_fcfg.h and in the ROM bootloader itself */ +typedef struct serialRomBldrParam_struct serialRomBldrParam_t; + + +/*! \brief Extern declaration of the CCFG struct. + * This extern declaration can be used to access CCFG fields from other parts + * of the code base. + * This extern assumes that the ccfg_t struct allocated in the system is called + * "ccfg". + */ +extern const ccfg_t ccfg; + +#endif // __HW_CCFG_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ckmd.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ckmd.h new file mode 100644 index 00000000..44bd28eb --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ckmd.h @@ -0,0 +1,3564 @@ +/****************************************************************************** +* Filename: hw_ckmd_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_CKMD_H__ +#define __HW_CKMD_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CKMD component +// +//***************************************************************************** +// Description Register. +#define CKMD_O_DESC 0x00000000U + +// Interrupt mask. +#define CKMD_O_IMASK 0x00000044U + +// Raw interrupt status. +#define CKMD_O_RIS 0x00000048U + +// Masked interrupt status. +#define CKMD_O_MIS 0x0000004CU + +// Interrupt set register. +#define CKMD_O_ISET 0x00000050U + +// Interrupt clear register. +#define CKMD_O_ICLR 0x00000054U + +// Interrupt mask set register. +#define CKMD_O_IMSET 0x00000058U + +// Interrupt mask clear register. +#define CKMD_O_IMCLR 0x0000005CU + +// Internal. Only to be used through TI provided API. +#define CKMD_O_HFOSCCTL 0x00000080U + +// High frequency crystal control +#define CKMD_O_HFXTCTL 0x00000084U + +// Low frequency oscillator control +#define CKMD_O_LFOSCCTL 0x0000008CU + +// Low frequency crystal control +#define CKMD_O_LFXTCTL 0x00000090U + +// Low frequency clock qualification control +#define CKMD_O_LFQUALCTL 0x00000094U + +// Low frequency time increment control +#define CKMD_O_LFINCCTL 0x00000098U + +// Low frequency time increment override control +#define CKMD_O_LFINCOVR 0x0000009CU + +// Internal. Only to be used through TI provided API. +#define CKMD_O_AMPADCCTL 0x000000A0U + +// High frequency tracking loop control +#define CKMD_O_HFTRACKCTL 0x000000A4U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_LDOCTL 0x000000A8U + +// Nanoamp-bias control +#define CKMD_O_NABIASCTL 0x000000ACU + +// Low-frequency clock-monitor control +#define CKMD_O_LFMONCTL 0x000000B0U + +// Low frequency clock selection +#define CKMD_O_LFCLKSEL 0x000000C0U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCCLKSEL 0x000000C4U + +// ADC clock selection +#define CKMD_O_ADCCLKSEL 0x000000C8U + +// Low-frequency clock status +#define CKMD_O_LFCLKSTAT 0x000000E0U + +// HFXT status information +#define CKMD_O_HFXTSTAT 0x000000E4U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_AMPADCSTAT 0x000000E8U + +// HFOSC tracking loop status information +#define CKMD_O_TRACKSTAT 0x000000ECU + +// HFXT Amplitude Compensation Status +#define CKMD_O_AMPSTAT 0x000000F0U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_ATBCTL0 0x00000100U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_ATBCTL1 0x00000104U + +// Digital test bus mux control +#define CKMD_O_DTBCTL 0x00000108U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TRIM0 0x00000110U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TRIM1 0x00000114U + +// Initial values for HFXT ramping +#define CKMD_O_HFXTINIT 0x00000118U + +// Target values for HFXT ramping +#define CKMD_O_HFXTTARG 0x0000011CU + +// Alternative target values for HFXT configuration +#define CKMD_O_HFXTDYN 0x00000120U + +// Amplitude Compensation Configuration 0 +#define CKMD_O_AMPCFG0 0x00000124U + +// Amplitude Compensation Configuration 1 +#define CKMD_O_AMPCFG1 0x00000128U + +// Configuration Register for the Tracking Loop +#define CKMD_O_LOOPCFG 0x0000012CU + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCCTL 0x00000200U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCSTAT 0x00000204U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCRESULT 0x00000208U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCSATCFG 0x0000020CU + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCTRIGSRC 0x00000210U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCTRIGCNT 0x00000214U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCTRIGCNTLOAD 0x00000218U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCTRIGCNTCFG 0x0000021CU + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCPRECTL 0x00000220U + +// Internal. Only to be used through TI provided API. +#define CKMD_O_TDCPRECNTR 0x00000224U + +// WDT counter value register +#define CKMD_O_WDTCNT 0x00000300U + +// WDT test mode register +#define CKMD_O_WDTTEST 0x00000304U + +// WDT lock register +#define CKMD_O_WDTLOCK 0x00000308U + +//***************************************************************************** +// +// Register: CKMD_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define CKMD_DESC_MODID_W 16U +#define CKMD_DESC_MODID_M 0xFFFF0000U +#define CKMD_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// 0: Standard IP MMRs do not exist +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +// +// NOTE: This IP does not have DTB as part of the Standard IP MMRs. It uses +// DTBCTL instead. +#define CKMD_DESC_STDIPOFF_W 4U +#define CKMD_DESC_STDIPOFF_M 0x0000F000U +#define CKMD_DESC_STDIPOFF_S 12U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define CKMD_DESC_MAJREV_W 4U +#define CKMD_DESC_MAJREV_M 0x000000F0U +#define CKMD_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define CKMD_DESC_MINREV_W 4U +#define CKMD_DESC_MINREV_M 0x0000000FU +#define CKMD_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_IMASK +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_IMASK_LFTICK 0x00020000U +#define CKMD_IMASK_LFTICK_M 0x00020000U +#define CKMD_IMASK_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_IMASK_LFGEARRSTRT 0x00010000U +#define CKMD_IMASK_LFGEARRSTRT_M 0x00010000U +#define CKMD_IMASK_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_IMASK_AMPSETTLED 0x00008000U +#define CKMD_IMASK_AMPSETTLED_M 0x00008000U +#define CKMD_IMASK_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_IMASK_AMPCTRLATTARG 0x00004000U +#define CKMD_IMASK_AMPCTRLATTARG_M 0x00004000U +#define CKMD_IMASK_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_IMASK_PRELFEDGE 0x00002000U +#define CKMD_IMASK_PRELFEDGE_M 0x00002000U +#define CKMD_IMASK_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_IMASK_LFCLKLOSS 0x00001000U +#define CKMD_IMASK_LFCLKLOSS_M 0x00001000U +#define CKMD_IMASK_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_IMASK_LFCLKOOR 0x00000800U +#define CKMD_IMASK_LFCLKOOR_M 0x00000800U +#define CKMD_IMASK_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_IMASK_LFCLKGOOD 0x00000400U +#define CKMD_IMASK_LFCLKGOOD_M 0x00000400U +#define CKMD_IMASK_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_IMASK_LFINCUPD 0x00000200U +#define CKMD_IMASK_LFINCUPD_M 0x00000200U +#define CKMD_IMASK_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_IMASK_TDCDONE 0x00000100U +#define CKMD_IMASK_TDCDONE_M 0x00000100U +#define CKMD_IMASK_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_IMASK_ADCPEAKUPD 0x00000080U +#define CKMD_IMASK_ADCPEAKUPD_M 0x00000080U +#define CKMD_IMASK_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_IMASK_ADCBIASUPD 0x00000040U +#define CKMD_IMASK_ADCBIASUPD_M 0x00000040U +#define CKMD_IMASK_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_IMASK_ADCCOMPUPD 0x00000020U +#define CKMD_IMASK_ADCCOMPUPD_M 0x00000020U +#define CKMD_IMASK_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_IMASK_TRACKREFOOR 0x00000010U +#define CKMD_IMASK_TRACKREFOOR_M 0x00000010U +#define CKMD_IMASK_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_IMASK_TRACKREFLOSS 0x00000008U +#define CKMD_IMASK_TRACKREFLOSS_M 0x00000008U +#define CKMD_IMASK_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_IMASK_HFXTAMPGOOD 0x00000004U +#define CKMD_IMASK_HFXTAMPGOOD_M 0x00000004U +#define CKMD_IMASK_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_IMASK_HFXTFAULT 0x00000002U +#define CKMD_IMASK_HFXTFAULT_M 0x00000002U +#define CKMD_IMASK_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_IMASK_HFXTGOOD 0x00000001U +#define CKMD_IMASK_HFXTGOOD_M 0x00000001U +#define CKMD_IMASK_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_RIS +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_RIS_LFTICK 0x00020000U +#define CKMD_RIS_LFTICK_M 0x00020000U +#define CKMD_RIS_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_RIS_LFGEARRSTRT 0x00010000U +#define CKMD_RIS_LFGEARRSTRT_M 0x00010000U +#define CKMD_RIS_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_RIS_AMPSETTLED 0x00008000U +#define CKMD_RIS_AMPSETTLED_M 0x00008000U +#define CKMD_RIS_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_RIS_AMPCTRLATTARG 0x00004000U +#define CKMD_RIS_AMPCTRLATTARG_M 0x00004000U +#define CKMD_RIS_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_RIS_PRELFEDGE 0x00002000U +#define CKMD_RIS_PRELFEDGE_M 0x00002000U +#define CKMD_RIS_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_RIS_LFCLKLOSS 0x00001000U +#define CKMD_RIS_LFCLKLOSS_M 0x00001000U +#define CKMD_RIS_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_RIS_LFCLKOOR 0x00000800U +#define CKMD_RIS_LFCLKOOR_M 0x00000800U +#define CKMD_RIS_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_RIS_LFCLKGOOD 0x00000400U +#define CKMD_RIS_LFCLKGOOD_M 0x00000400U +#define CKMD_RIS_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_RIS_LFINCUPD 0x00000200U +#define CKMD_RIS_LFINCUPD_M 0x00000200U +#define CKMD_RIS_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_RIS_TDCDONE 0x00000100U +#define CKMD_RIS_TDCDONE_M 0x00000100U +#define CKMD_RIS_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_RIS_ADCPEAKUPD 0x00000080U +#define CKMD_RIS_ADCPEAKUPD_M 0x00000080U +#define CKMD_RIS_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_RIS_ADCBIASUPD 0x00000040U +#define CKMD_RIS_ADCBIASUPD_M 0x00000040U +#define CKMD_RIS_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_RIS_ADCCOMPUPD 0x00000020U +#define CKMD_RIS_ADCCOMPUPD_M 0x00000020U +#define CKMD_RIS_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_RIS_TRACKREFOOR 0x00000010U +#define CKMD_RIS_TRACKREFOOR_M 0x00000010U +#define CKMD_RIS_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_RIS_TRACKREFLOSS 0x00000008U +#define CKMD_RIS_TRACKREFLOSS_M 0x00000008U +#define CKMD_RIS_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_RIS_HFXTAMPGOOD 0x00000004U +#define CKMD_RIS_HFXTAMPGOOD_M 0x00000004U +#define CKMD_RIS_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_RIS_HFXTFAULT 0x00000002U +#define CKMD_RIS_HFXTFAULT_M 0x00000002U +#define CKMD_RIS_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_RIS_HFXTGOOD 0x00000001U +#define CKMD_RIS_HFXTGOOD_M 0x00000001U +#define CKMD_RIS_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_MIS +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_MIS_LFTICK 0x00020000U +#define CKMD_MIS_LFTICK_M 0x00020000U +#define CKMD_MIS_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_MIS_LFGEARRSTRT 0x00010000U +#define CKMD_MIS_LFGEARRSTRT_M 0x00010000U +#define CKMD_MIS_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_MIS_AMPSETTLED 0x00008000U +#define CKMD_MIS_AMPSETTLED_M 0x00008000U +#define CKMD_MIS_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_MIS_AMPCTRLATTARG 0x00004000U +#define CKMD_MIS_AMPCTRLATTARG_M 0x00004000U +#define CKMD_MIS_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_MIS_PRELFEDGE 0x00002000U +#define CKMD_MIS_PRELFEDGE_M 0x00002000U +#define CKMD_MIS_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_MIS_LFCLKLOSS 0x00001000U +#define CKMD_MIS_LFCLKLOSS_M 0x00001000U +#define CKMD_MIS_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_MIS_LFCLKOOR 0x00000800U +#define CKMD_MIS_LFCLKOOR_M 0x00000800U +#define CKMD_MIS_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_MIS_LFCLKGOOD 0x00000400U +#define CKMD_MIS_LFCLKGOOD_M 0x00000400U +#define CKMD_MIS_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_MIS_LFINCUPD 0x00000200U +#define CKMD_MIS_LFINCUPD_M 0x00000200U +#define CKMD_MIS_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_MIS_TDCDONE 0x00000100U +#define CKMD_MIS_TDCDONE_M 0x00000100U +#define CKMD_MIS_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_MIS_ADCPEAKUPD 0x00000080U +#define CKMD_MIS_ADCPEAKUPD_M 0x00000080U +#define CKMD_MIS_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_MIS_ADCBIASUPD 0x00000040U +#define CKMD_MIS_ADCBIASUPD_M 0x00000040U +#define CKMD_MIS_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_MIS_ADCCOMPUPD 0x00000020U +#define CKMD_MIS_ADCCOMPUPD_M 0x00000020U +#define CKMD_MIS_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_MIS_TRACKREFOOR 0x00000010U +#define CKMD_MIS_TRACKREFOOR_M 0x00000010U +#define CKMD_MIS_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_MIS_TRACKREFLOSS 0x00000008U +#define CKMD_MIS_TRACKREFLOSS_M 0x00000008U +#define CKMD_MIS_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_MIS_HFXTAMPGOOD 0x00000004U +#define CKMD_MIS_HFXTAMPGOOD_M 0x00000004U +#define CKMD_MIS_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_MIS_HFXTFAULT 0x00000002U +#define CKMD_MIS_HFXTFAULT_M 0x00000002U +#define CKMD_MIS_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_MIS_HFXTGOOD 0x00000001U +#define CKMD_MIS_HFXTGOOD_M 0x00000001U +#define CKMD_MIS_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_ISET +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_ISET_LFTICK 0x00020000U +#define CKMD_ISET_LFTICK_M 0x00020000U +#define CKMD_ISET_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_ISET_LFGEARRSTRT 0x00010000U +#define CKMD_ISET_LFGEARRSTRT_M 0x00010000U +#define CKMD_ISET_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_ISET_AMPSETTLED 0x00008000U +#define CKMD_ISET_AMPSETTLED_M 0x00008000U +#define CKMD_ISET_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG.Q1CAP, +// HFXTTARG.Q2CAP and HFXTTARG.IREF or HFXTDYN.Q1CAP, HFXTDYN.Q2CAP and +// HFXTDYN.IREF are reached. +#define CKMD_ISET_AMPCTRLATTARG 0x00004000U +#define CKMD_ISET_AMPCTRLATTARG_M 0x00004000U +#define CKMD_ISET_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_ISET_PRELFEDGE 0x00002000U +#define CKMD_ISET_PRELFEDGE_M 0x00002000U +#define CKMD_ISET_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_ISET_LFCLKLOSS 0x00001000U +#define CKMD_ISET_LFCLKLOSS_M 0x00001000U +#define CKMD_ISET_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_ISET_LFCLKOOR 0x00000800U +#define CKMD_ISET_LFCLKOOR_M 0x00000800U +#define CKMD_ISET_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_ISET_LFCLKGOOD 0x00000400U +#define CKMD_ISET_LFCLKGOOD_M 0x00000400U +#define CKMD_ISET_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_ISET_LFINCUPD 0x00000200U +#define CKMD_ISET_LFINCUPD_M 0x00000200U +#define CKMD_ISET_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_ISET_TDCDONE 0x00000100U +#define CKMD_ISET_TDCDONE_M 0x00000100U +#define CKMD_ISET_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_ISET_ADCPEAKUPD 0x00000080U +#define CKMD_ISET_ADCPEAKUPD_M 0x00000080U +#define CKMD_ISET_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_ISET_ADCBIASUPD 0x00000040U +#define CKMD_ISET_ADCBIASUPD_M 0x00000040U +#define CKMD_ISET_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_ISET_ADCCOMPUPD 0x00000020U +#define CKMD_ISET_ADCCOMPUPD_M 0x00000020U +#define CKMD_ISET_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_ISET_TRACKREFOOR 0x00000010U +#define CKMD_ISET_TRACKREFOOR_M 0x00000010U +#define CKMD_ISET_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_ISET_TRACKREFLOSS 0x00000008U +#define CKMD_ISET_TRACKREFLOSS_M 0x00000008U +#define CKMD_ISET_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_ISET_HFXTAMPGOOD 0x00000004U +#define CKMD_ISET_HFXTAMPGOOD_M 0x00000004U +#define CKMD_ISET_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_ISET_HFXTFAULT 0x00000002U +#define CKMD_ISET_HFXTFAULT_M 0x00000002U +#define CKMD_ISET_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_ISET_HFXTGOOD 0x00000001U +#define CKMD_ISET_HFXTGOOD_M 0x00000001U +#define CKMD_ISET_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_ICLR +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_ICLR_LFTICK 0x00020000U +#define CKMD_ICLR_LFTICK_M 0x00020000U +#define CKMD_ICLR_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_ICLR_LFGEARRSTRT 0x00010000U +#define CKMD_ICLR_LFGEARRSTRT_M 0x00010000U +#define CKMD_ICLR_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_ICLR_AMPSETTLED 0x00008000U +#define CKMD_ICLR_AMPSETTLED_M 0x00008000U +#define CKMD_ICLR_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_ICLR_AMPCTRLATTARG 0x00004000U +#define CKMD_ICLR_AMPCTRLATTARG_M 0x00004000U +#define CKMD_ICLR_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_ICLR_PRELFEDGE 0x00002000U +#define CKMD_ICLR_PRELFEDGE_M 0x00002000U +#define CKMD_ICLR_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_ICLR_LFCLKLOSS 0x00001000U +#define CKMD_ICLR_LFCLKLOSS_M 0x00001000U +#define CKMD_ICLR_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_ICLR_LFCLKOOR 0x00000800U +#define CKMD_ICLR_LFCLKOOR_M 0x00000800U +#define CKMD_ICLR_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_ICLR_LFCLKGOOD 0x00000400U +#define CKMD_ICLR_LFCLKGOOD_M 0x00000400U +#define CKMD_ICLR_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_ICLR_LFINCUPD 0x00000200U +#define CKMD_ICLR_LFINCUPD_M 0x00000200U +#define CKMD_ICLR_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_ICLR_TDCDONE 0x00000100U +#define CKMD_ICLR_TDCDONE_M 0x00000100U +#define CKMD_ICLR_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_ICLR_ADCPEAKUPD 0x00000080U +#define CKMD_ICLR_ADCPEAKUPD_M 0x00000080U +#define CKMD_ICLR_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_ICLR_ADCBIASUPD 0x00000040U +#define CKMD_ICLR_ADCBIASUPD_M 0x00000040U +#define CKMD_ICLR_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_ICLR_ADCCOMPUPD 0x00000020U +#define CKMD_ICLR_ADCCOMPUPD_M 0x00000020U +#define CKMD_ICLR_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_ICLR_TRACKREFOOR 0x00000010U +#define CKMD_ICLR_TRACKREFOOR_M 0x00000010U +#define CKMD_ICLR_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_ICLR_TRACKREFLOSS 0x00000008U +#define CKMD_ICLR_TRACKREFLOSS_M 0x00000008U +#define CKMD_ICLR_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_ICLR_HFXTAMPGOOD 0x00000004U +#define CKMD_ICLR_HFXTAMPGOOD_M 0x00000004U +#define CKMD_ICLR_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_ICLR_HFXTFAULT 0x00000002U +#define CKMD_ICLR_HFXTFAULT_M 0x00000002U +#define CKMD_ICLR_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_ICLR_HFXTGOOD 0x00000001U +#define CKMD_ICLR_HFXTGOOD_M 0x00000001U +#define CKMD_ICLR_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_IMSET +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_IMSET_LFTICK 0x00020000U +#define CKMD_IMSET_LFTICK_M 0x00020000U +#define CKMD_IMSET_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_IMSET_LFGEARRSTRT 0x00010000U +#define CKMD_IMSET_LFGEARRSTRT_M 0x00010000U +#define CKMD_IMSET_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_IMSET_AMPSETTLED 0x00008000U +#define CKMD_IMSET_AMPSETTLED_M 0x00008000U +#define CKMD_IMSET_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_IMSET_AMPCTRLATTARG 0x00004000U +#define CKMD_IMSET_AMPCTRLATTARG_M 0x00004000U +#define CKMD_IMSET_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_IMSET_PRELFEDGE 0x00002000U +#define CKMD_IMSET_PRELFEDGE_M 0x00002000U +#define CKMD_IMSET_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_IMSET_LFCLKLOSS 0x00001000U +#define CKMD_IMSET_LFCLKLOSS_M 0x00001000U +#define CKMD_IMSET_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_IMSET_LFCLKOOR 0x00000800U +#define CKMD_IMSET_LFCLKOOR_M 0x00000800U +#define CKMD_IMSET_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_IMSET_LFCLKGOOD 0x00000400U +#define CKMD_IMSET_LFCLKGOOD_M 0x00000400U +#define CKMD_IMSET_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_IMSET_LFINCUPD 0x00000200U +#define CKMD_IMSET_LFINCUPD_M 0x00000200U +#define CKMD_IMSET_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_IMSET_TDCDONE 0x00000100U +#define CKMD_IMSET_TDCDONE_M 0x00000100U +#define CKMD_IMSET_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_IMSET_ADCPEAKUPD 0x00000080U +#define CKMD_IMSET_ADCPEAKUPD_M 0x00000080U +#define CKMD_IMSET_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_IMSET_ADCBIASUPD 0x00000040U +#define CKMD_IMSET_ADCBIASUPD_M 0x00000040U +#define CKMD_IMSET_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_IMSET_ADCCOMPUPD 0x00000020U +#define CKMD_IMSET_ADCCOMPUPD_M 0x00000020U +#define CKMD_IMSET_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_IMSET_TRACKREFOOR 0x00000010U +#define CKMD_IMSET_TRACKREFOOR_M 0x00000010U +#define CKMD_IMSET_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_IMSET_TRACKREFLOSS 0x00000008U +#define CKMD_IMSET_TRACKREFLOSS_M 0x00000008U +#define CKMD_IMSET_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_IMSET_HFXTAMPGOOD 0x00000004U +#define CKMD_IMSET_HFXTAMPGOOD_M 0x00000004U +#define CKMD_IMSET_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_IMSET_HFXTFAULT 0x00000002U +#define CKMD_IMSET_HFXTFAULT_M 0x00000002U +#define CKMD_IMSET_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_IMSET_HFXTGOOD 0x00000001U +#define CKMD_IMSET_HFXTGOOD_M 0x00000001U +#define CKMD_IMSET_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_IMCLR +// +//***************************************************************************** +// Field: [17] LFTICK +// +// 32kHz TICK to RTC and WDT. +// +// Either derived from selected LFCLK or generated from CLKULL in absence of +// LFCLK. +#define CKMD_IMCLR_LFTICK 0x00020000U +#define CKMD_IMCLR_LFTICK_M 0x00020000U +#define CKMD_IMCLR_LFTICK_S 17U + +// Field: [16] LFGEARRSTRT +// +// LFINC filter gearing restart. +// +// Indicates that the LFINC filter restarted gearing. Subsequent LFINC +// estimates may have higher variation. +#define CKMD_IMCLR_LFGEARRSTRT 0x00010000U +#define CKMD_IMCLR_LFGEARRSTRT_M 0x00010000U +#define CKMD_IMCLR_LFGEARRSTRT_S 16U + +// Field: [15] AMPSETTLED +// +// HFXT Amplitude compensation - settled +// +// Indicates that the amplitude compensation FSM has reached the SETTLED or +// TCXOMODE state, +// and the controls configured in HFXTTARG or HFXTDYN are reached. +#define CKMD_IMCLR_AMPSETTLED 0x00008000U +#define CKMD_IMCLR_AMPSETTLED_M 0x00008000U +#define CKMD_IMCLR_AMPSETTLED_S 15U + +// Field: [14] AMPCTRLATTARG +// +// HFXT Amplitude compensation - controls at target +// +// Indicates that the control values configured in HFXTTARG or HFXTDYN are +// reached. +// Applies to Q1CAP, Q2CAP and IREF. +#define CKMD_IMCLR_AMPCTRLATTARG 0x00004000U +#define CKMD_IMCLR_AMPCTRLATTARG_M 0x00004000U +#define CKMD_IMCLR_AMPCTRLATTARG_S 14U + +// Field: [13] PRELFEDGE +// +// Pre-LF clock edge detect. +// +// Indicates that a positive edge occured on the selected pre-LF clock +// LFCLKSEL.PRE. +// Can be used by software to confirm that a LF clock source is running and +// within the expected frequency, +// before selecting it as the main LF clock source. +#define CKMD_IMCLR_PRELFEDGE 0x00002000U +#define CKMD_IMCLR_PRELFEDGE_M 0x00002000U +#define CKMD_IMCLR_PRELFEDGE_S 13U + +// Field: [12] LFCLKLOSS +// +// LF clock is lost. +// +// Indicates that no LF clock edge occured for ~49us (~1.6 times nominal +// period). +// The system will automatically fall-back to generating LFTICK based on +// CLKULL, +// to avoid timing corruption. +// Note that this signal is NOT related to the analog LF clock-loss detector +// which can reset the device during STANDBY. +#define CKMD_IMCLR_LFCLKLOSS 0x00001000U +#define CKMD_IMCLR_LFCLKLOSS_M 0x00001000U +#define CKMD_IMCLR_LFCLKLOSS_S 12U + +// Field: [11] LFCLKOOR +// +// LF clock period out-of-range. +// +// Indicates that a LF clock period was measured to be out-of-range, +// according to LFQUALCTL.MAXERR. +#define CKMD_IMCLR_LFCLKOOR 0x00000800U +#define CKMD_IMCLR_LFCLKOOR_M 0x00000800U +#define CKMD_IMCLR_LFCLKOOR_S 11U + +// Field: [10] LFCLKGOOD +// +// LF clock good. +// +// Indicates that the LF clock is good, according to the configuration in +// LFQUALCTL. +#define CKMD_IMCLR_LFCLKGOOD 0x00000400U +#define CKMD_IMCLR_LFCLKGOOD_M 0x00000400U +#define CKMD_IMCLR_LFCLKGOOD_S 10U + +// Field: [9] LFINCUPD +// +// LFINC updated. +// +// Indicates that a new LFINC measurement value is available in +// LFCLKSTAT.LFINC. +#define CKMD_IMCLR_LFINCUPD 0x00000200U +#define CKMD_IMCLR_LFINCUPD_M 0x00000200U +#define CKMD_IMCLR_LFINCUPD_S 9U + +// Field: [8] TDCDONE +// +// TDC done event. +// +// Indicates that the TDC measurement is done. +#define CKMD_IMCLR_TDCDONE 0x00000100U +#define CKMD_IMCLR_TDCDONE_M 0x00000100U +#define CKMD_IMCLR_TDCDONE_S 8U + +// Field: [7] ADCPEAKUPD +// +// HFXT-ADC PEAK measurement update event. +// +// Indicates that the HFXT-ADC PEAK measurement is done. +#define CKMD_IMCLR_ADCPEAKUPD 0x00000080U +#define CKMD_IMCLR_ADCPEAKUPD_M 0x00000080U +#define CKMD_IMCLR_ADCPEAKUPD_S 7U + +// Field: [6] ADCBIASUPD +// +// HFXT-ADC BIAS measurement update event. +// +// Indicates that the HFXT-ADC BIAS measurement is done. +#define CKMD_IMCLR_ADCBIASUPD 0x00000040U +#define CKMD_IMCLR_ADCBIASUPD_M 0x00000040U +#define CKMD_IMCLR_ADCBIASUPD_S 6U + +// Field: [5] ADCCOMPUPD +// +// HFXT-ADC comparison update event. +// +// Indicates that the HFXT-ADC comparison is done. +#define CKMD_IMCLR_ADCCOMPUPD 0x00000020U +#define CKMD_IMCLR_ADCCOMPUPD_M 0x00000020U +#define CKMD_IMCLR_ADCCOMPUPD_S 5U + +// Field: [4] TRACKREFOOR +// +// Out-of-range indication from the tracking loop. +// +// Indicates that the selected reference clock frequency of the tracking loop +// is out-of-range. +#define CKMD_IMCLR_TRACKREFOOR 0x00000010U +#define CKMD_IMCLR_TRACKREFOOR_M 0x00000010U +#define CKMD_IMCLR_TRACKREFOOR_S 4U + +// Field: [3] TRACKREFLOSS +// +// Clock loss indication from the tracking loop. +// +// Indicates that the selected reference clock of the tracking loop is lost. +#define CKMD_IMCLR_TRACKREFLOSS 0x00000008U +#define CKMD_IMCLR_TRACKREFLOSS_M 0x00000008U +#define CKMD_IMCLR_TRACKREFLOSS_S 3U + +// Field: [2] HFXTAMPGOOD +// +// HFXT amplitude good indication. +#define CKMD_IMCLR_HFXTAMPGOOD 0x00000004U +#define CKMD_IMCLR_HFXTAMPGOOD_M 0x00000004U +#define CKMD_IMCLR_HFXTAMPGOOD_S 2U + +// Field: [1] HFXTFAULT +// +// HFXT fault indication. +// +// Indicates that HFXT did not start correctly, or its frequency is too low. +// HFXT will not recover from this fault and has to be restarted. +// This is only a one-time check at HFXT startup. +#define CKMD_IMCLR_HFXTFAULT 0x00000002U +#define CKMD_IMCLR_HFXTFAULT_M 0x00000002U +#define CKMD_IMCLR_HFXTFAULT_S 1U + +// Field: [0] HFXTGOOD +// +// HFXT good indication. +// +// Indicates that HFXT started correctly. The frequency is not necessarily good +// enough for radio operation. +// This is only a one-time check at HFXT startup. +#define CKMD_IMCLR_HFXTGOOD 0x00000001U +#define CKMD_IMCLR_HFXTGOOD_M 0x00000001U +#define CKMD_IMCLR_HFXTGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFOSCCTL +// +//***************************************************************************** +// Field: [31:24] PW +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFOSCCTL_PW_W 8U +#define CKMD_HFOSCCTL_PW_M 0xFF000000U +#define CKMD_HFOSCCTL_PW_S 24U + +// Field: [8] CLKSVTOVR +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HFXT Internal. Only to be used through TI provided API. +// HFOSC Internal. Only to be used through TI provided API. +#define CKMD_HFOSCCTL_CLKSVTOVR 0x00000100U +#define CKMD_HFOSCCTL_CLKSVTOVR_M 0x00000100U +#define CKMD_HFOSCCTL_CLKSVTOVR_S 8U +#define CKMD_HFOSCCTL_CLKSVTOVR_HFXT 0x00000100U +#define CKMD_HFOSCCTL_CLKSVTOVR_HFOSC 0x00000000U + +// Field: [1] FORCEOFF +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFOSCCTL_FORCEOFF 0x00000002U +#define CKMD_HFOSCCTL_FORCEOFF_M 0x00000002U +#define CKMD_HFOSCCTL_FORCEOFF_S 1U + +// Field: [0] QUALBYP +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFOSCCTL_QUALBYP 0x00000001U +#define CKMD_HFOSCCTL_QUALBYP_M 0x00000001U +#define CKMD_HFOSCCTL_QUALBYP_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFXTCTL +// +//***************************************************************************** +// Field: [31] AMPOVR +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_AMPOVR 0x80000000U +#define CKMD_HFXTCTL_AMPOVR_M 0x80000000U +#define CKMD_HFXTCTL_AMPOVR_S 31U + +// Field: [26] BIASEN +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_BIASEN 0x04000000U +#define CKMD_HFXTCTL_BIASEN_M 0x04000000U +#define CKMD_HFXTCTL_BIASEN_S 26U + +// Field: [25] LPBUFEN +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_LPBUFEN 0x02000000U +#define CKMD_HFXTCTL_LPBUFEN_M 0x02000000U +#define CKMD_HFXTCTL_LPBUFEN_S 25U + +// Field: [24] INJECT +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_INJECT 0x01000000U +#define CKMD_HFXTCTL_INJECT_M 0x01000000U +#define CKMD_HFXTCTL_INJECT_S 24U + +// Field: [23] QUALBYP +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_QUALBYP 0x00800000U +#define CKMD_HFXTCTL_QUALBYP_M 0x00800000U +#define CKMD_HFXTCTL_QUALBYP_S 23U + +// Field: [19:8] QUALDLY +// +// Skip potentially unstable clock cycles after enabling HFXT. +// Number of cycles skipped is 8*QUALDLY. +#define CKMD_HFXTCTL_QUALDLY_W 12U +#define CKMD_HFXTCTL_QUALDLY_M 0x000FFF00U +#define CKMD_HFXTCTL_QUALDLY_S 8U + +// Field: [7] TCXOMODE +// +// Temperature compensated crystal oscillator mode. +// +// Set this bit if a TXCO is connected. +#define CKMD_HFXTCTL_TCXOMODE 0x00000080U +#define CKMD_HFXTCTL_TCXOMODE_M 0x00000080U +#define CKMD_HFXTCTL_TCXOMODE_S 7U + +// Field: [6] TCXOTYPE +// +// Type of temperature compensated crystal used. +// +// Only has effect if TCXOMODE is set. +// ENUMs: +// CMOS Use with CMOS TCXO +// CLIPPEDSINE Use with clipped-sine TCXO +#define CKMD_HFXTCTL_TCXOTYPE 0x00000040U +#define CKMD_HFXTCTL_TCXOTYPE_M 0x00000040U +#define CKMD_HFXTCTL_TCXOTYPE_S 6U +#define CKMD_HFXTCTL_TCXOTYPE_CMOS 0x00000040U +#define CKMD_HFXTCTL_TCXOTYPE_CLIPPEDSINE 0x00000000U + +// Field: [2] AUTOEN +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_AUTOEN 0x00000004U +#define CKMD_HFXTCTL_AUTOEN_M 0x00000004U +#define CKMD_HFXTCTL_AUTOEN_S 2U + +// Field: [1] HPBUFEN +// +// High performance clock buffer enable. +// +// This bit controls the clock output for the RF PLL. +// It is required for radio operation. +#define CKMD_HFXTCTL_HPBUFEN 0x00000002U +#define CKMD_HFXTCTL_HPBUFEN_M 0x00000002U +#define CKMD_HFXTCTL_HPBUFEN_S 1U + +// Field: [0] EN +// +// Internal. Only to be used through TI provided API. +#define CKMD_HFXTCTL_EN 0x00000001U +#define CKMD_HFXTCTL_EN_M 0x00000001U +#define CKMD_HFXTCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFOSCCTL +// +//***************************************************************************** +// Field: [0] EN +// +// LFOSC enable +#define CKMD_LFOSCCTL_EN 0x00000001U +#define CKMD_LFOSCCTL_EN_M 0x00000001U +#define CKMD_LFOSCCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFXTCTL +// +//***************************************************************************** +// Field: [14:13] LEAKCOMP +// +// Leakage compensation control +// ENUMs: +// OFF No leakage compensation +// HALF Half leakage compensation +// FULL Full leakage compensation +#define CKMD_LFXTCTL_LEAKCOMP_W 2U +#define CKMD_LFXTCTL_LEAKCOMP_M 0x00006000U +#define CKMD_LFXTCTL_LEAKCOMP_S 13U +#define CKMD_LFXTCTL_LEAKCOMP_OFF 0x00006000U +#define CKMD_LFXTCTL_LEAKCOMP_HALF 0x00002000U +#define CKMD_LFXTCTL_LEAKCOMP_FULL 0x00000000U + +// Field: [12] BUFBIAS +// +// Control the BIAS current of the input amp in LP buffer +// ENUMs: +// MAX Maximum bias current: 50nA +// MIN Minimum bias current: 25nA +#define CKMD_LFXTCTL_BUFBIAS 0x00001000U +#define CKMD_LFXTCTL_BUFBIAS_M 0x00001000U +#define CKMD_LFXTCTL_BUFBIAS_S 12U +#define CKMD_LFXTCTL_BUFBIAS_MAX 0x00001000U +#define CKMD_LFXTCTL_BUFBIAS_MIN 0x00000000U + +// Field: [11:8] AMPBIAS +// +// Adjust current mirror ratio into oscillator core. This value is depending on +// crystal and is set by FW. This field uses a 2's complement encoding. +#define CKMD_LFXTCTL_AMPBIAS_W 4U +#define CKMD_LFXTCTL_AMPBIAS_M 0x00000F00U +#define CKMD_LFXTCTL_AMPBIAS_S 8U + +// Field: [7:6] BIASBOOST +// +// Boost oscillator amplitude +// +// This value depends on the crystal and needs to be configured by Firmware. +#define CKMD_LFXTCTL_BIASBOOST_W 2U +#define CKMD_LFXTCTL_BIASBOOST_M 0x000000C0U +#define CKMD_LFXTCTL_BIASBOOST_S 6U + +// Field: [5:4] REGBIAS +// +// Regulation loop bias resistor value +// +// This value depends on the crystal and needs to be configured by Firmware. +#define CKMD_LFXTCTL_REGBIAS_W 2U +#define CKMD_LFXTCTL_REGBIAS_M 0x00000030U +#define CKMD_LFXTCTL_REGBIAS_S 4U + +// Field: [2] HPBUFEN +// +// Control the buffer used. In normal operation, low-power buffer is used in +// all device modes. The high-performance buffer is only used for test +// purposes. +#define CKMD_LFXTCTL_HPBUFEN 0x00000004U +#define CKMD_LFXTCTL_HPBUFEN_M 0x00000004U +#define CKMD_LFXTCTL_HPBUFEN_S 2U + +// Field: [1] AMPREGMODE +// +// Amplitude regulation mode +// ENUMs: +// LOOPDIS Amplitude control loop disabled +// LOOPEN Amplitude control loop enabled +#define CKMD_LFXTCTL_AMPREGMODE 0x00000002U +#define CKMD_LFXTCTL_AMPREGMODE_M 0x00000002U +#define CKMD_LFXTCTL_AMPREGMODE_S 1U +#define CKMD_LFXTCTL_AMPREGMODE_LOOPDIS 0x00000002U +#define CKMD_LFXTCTL_AMPREGMODE_LOOPEN 0x00000000U + +// Field: [0] EN +// +// LFXT enable +#define CKMD_LFXTCTL_EN 0x00000001U +#define CKMD_LFXTCTL_EN_M 0x00000001U +#define CKMD_LFXTCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFQUALCTL +// +//***************************************************************************** +// Field: [13:8] MAXERR +// +// Maximum LFCLK period error. +// +// Value given in microseconds, 3 integer bits + 3 fractional bits. +#define CKMD_LFQUALCTL_MAXERR_W 6U +#define CKMD_LFQUALCTL_MAXERR_M 0x00003F00U +#define CKMD_LFQUALCTL_MAXERR_S 8U + +// Field: [7:0] CONSEC +// +// Number of consecutive times the LFCLK period error has to be +// smaller than MAXERR to be considered "good". +// Setting this value to 0 will bypass clock qualification, +// and the "good" indicator will always be 1. +#define CKMD_LFQUALCTL_CONSEC_W 8U +#define CKMD_LFQUALCTL_CONSEC_M 0x000000FFU +#define CKMD_LFQUALCTL_CONSEC_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFINCCTL +// +//***************************************************************************** +// Field: [31] PREVENTSTBY +// +// Controls if the LFINC filter prevents STANBY entry until settled. +// ENUMs: +// ON Enable. Prevent STANDBY entry. +// OFF Disable. Do not prevent STANDBY entry. +#define CKMD_LFINCCTL_PREVENTSTBY 0x80000000U +#define CKMD_LFINCCTL_PREVENTSTBY_M 0x80000000U +#define CKMD_LFINCCTL_PREVENTSTBY_S 31U +#define CKMD_LFINCCTL_PREVENTSTBY_ON 0x80000000U +#define CKMD_LFINCCTL_PREVENTSTBY_OFF 0x00000000U + +// Field: [29:8] INT +// +// Integral part of the LFINC filter. +// +// This value is updated by Hardware to reflect the current state of the +// filter. +// It can also be written to change the current state. +#define CKMD_LFINCCTL_INT_W 22U +#define CKMD_LFINCCTL_INT_M 0x3FFFFF00U +#define CKMD_LFINCCTL_INT_S 8U + +// Field: [7] STOPGEAR +// +// Controls the final gear of the LFINC filter. +// ENUMs: +// HIGH Highest final gear. Best dynamic frequency +// tracking, but higher variation in filter value. +// LOW Lowest final gear. Best settling, but less dynamic +// frequency tracking. +#define CKMD_LFINCCTL_STOPGEAR 0x00000080U +#define CKMD_LFINCCTL_STOPGEAR_M 0x00000080U +#define CKMD_LFINCCTL_STOPGEAR_S 7U +#define CKMD_LFINCCTL_STOPGEAR_HIGH 0x00000080U +#define CKMD_LFINCCTL_STOPGEAR_LOW 0x00000000U + +// Field: [6:5] ERRTHR +// +// Controls the threshold for gearing restart of the LFINC filter. +// +// Only effective if GEARRSTRT is not ONETHR or TWOTHR. +// ENUMs: +// SMALL Restart gearing on small error. Potentially more +// false restarts, faster response on small +// frequency shifts. +// MIDSMALL Middle value towards SMALL. +// MIDLARGE Middle value towards LARGE. +// LARGE Restart gearing on large error. Fewer false +// restarts, slower response on small frequency +// shifts. +#define CKMD_LFINCCTL_ERRTHR_W 2U +#define CKMD_LFINCCTL_ERRTHR_M 0x00000060U +#define CKMD_LFINCCTL_ERRTHR_S 5U +#define CKMD_LFINCCTL_ERRTHR_SMALL 0x00000060U +#define CKMD_LFINCCTL_ERRTHR_MIDSMALL 0x00000040U +#define CKMD_LFINCCTL_ERRTHR_MIDLARGE 0x00000020U +#define CKMD_LFINCCTL_ERRTHR_LARGE 0x00000000U + +// Field: [4:3] GEARRSTRT +// +// Controls gearing restart of the LFINC filter. +// ENUMs: +// TWOTHR Restart gearing when the error accumulator crosses +// the threshold twice in a row. +// ONETHR Restart gearing when the error accumulator crosses +// the threshold once. +// NEVER Never restart gearing. Very stable filter value, +// but very slow response on frequency changes. +#define CKMD_LFINCCTL_GEARRSTRT_W 2U +#define CKMD_LFINCCTL_GEARRSTRT_M 0x00000018U +#define CKMD_LFINCCTL_GEARRSTRT_S 3U +#define CKMD_LFINCCTL_GEARRSTRT_TWOTHR 0x00000010U +#define CKMD_LFINCCTL_GEARRSTRT_ONETHR 0x00000008U +#define CKMD_LFINCCTL_GEARRSTRT_NEVER 0x00000000U + +// Field: [2] SOFTRSTRT +// +// Use a higher gear after re-enabling / wakeup. +// +// The filter will require 16-24 LFCLK periods to settle (depending on +// STOPGEAR), but may respond faster to frequency changes during STANDBY. +// ENUMs: +// ON Use soft gearing restarts +// OFF Don't use soft gearing restarts +#define CKMD_LFINCCTL_SOFTRSTRT 0x00000004U +#define CKMD_LFINCCTL_SOFTRSTRT_M 0x00000004U +#define CKMD_LFINCCTL_SOFTRSTRT_S 2U +#define CKMD_LFINCCTL_SOFTRSTRT_ON 0x00000004U +#define CKMD_LFINCCTL_SOFTRSTRT_OFF 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_LFINCOVR +// +//***************************************************************************** +// Field: [31] OVERRIDE +// +// Override LF increment +// +// Use the value provided in LFINC instead of the value calculated by Hardware. +#define CKMD_LFINCOVR_OVERRIDE 0x80000000U +#define CKMD_LFINCOVR_OVERRIDE_M 0x80000000U +#define CKMD_LFINCOVR_OVERRIDE_S 31U + +// Field: [21:0] LFINC +// +// LF increment value +// +// This value is used when OVERRIDE is set to 1. +// Otherwise the value is calculated automatically. +#define CKMD_LFINCOVR_LFINC_W 22U +#define CKMD_LFINCOVR_LFINC_M 0x003FFFFFU +#define CKMD_LFINCOVR_LFINC_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_AMPADCCTL +// +//***************************************************************************** +// Field: [31] SWOVR +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_SWOVR 0x80000000U +#define CKMD_AMPADCCTL_SWOVR_M 0x80000000U +#define CKMD_AMPADCCTL_SWOVR_S 31U + +// Field: [17] PEAKDETEN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ENABLE Internal. Only to be used through TI provided API. +// DISABLE Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_PEAKDETEN 0x00020000U +#define CKMD_AMPADCCTL_PEAKDETEN_M 0x00020000U +#define CKMD_AMPADCCTL_PEAKDETEN_S 17U +#define CKMD_AMPADCCTL_PEAKDETEN_ENABLE 0x00020000U +#define CKMD_AMPADCCTL_PEAKDETEN_DISABLE 0x00000000U + +// Field: [16] ADCEN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ENABLE Internal. Only to be used through TI provided API. +// DISABLE Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_ADCEN 0x00010000U +#define CKMD_AMPADCCTL_ADCEN_M 0x00010000U +#define CKMD_AMPADCCTL_ADCEN_S 16U +#define CKMD_AMPADCCTL_ADCEN_ENABLE 0x00010000U +#define CKMD_AMPADCCTL_ADCEN_DISABLE 0x00000000U + +// Field: [14:8] COMPVAL +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_COMPVAL_W 7U +#define CKMD_AMPADCCTL_COMPVAL_M 0x00007F00U +#define CKMD_AMPADCCTL_COMPVAL_S 8U + +// Field: [4] SRCSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// PEAK Internal. Only to be used through TI provided API. +// BIAS Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_SRCSEL 0x00000010U +#define CKMD_AMPADCCTL_SRCSEL_M 0x00000010U +#define CKMD_AMPADCCTL_SRCSEL_S 4U +#define CKMD_AMPADCCTL_SRCSEL_PEAK 0x00000010U +#define CKMD_AMPADCCTL_SRCSEL_BIAS 0x00000000U + +// Field: [1] COMPSTRT +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_COMPSTRT 0x00000002U +#define CKMD_AMPADCCTL_COMPSTRT_M 0x00000002U +#define CKMD_AMPADCCTL_COMPSTRT_S 1U + +// Field: [0] SARSTRT +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCCTL_SARSTRT 0x00000001U +#define CKMD_AMPADCCTL_SARSTRT_M 0x00000001U +#define CKMD_AMPADCCTL_SARSTRT_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFTRACKCTL +// +//***************************************************************************** +// Field: [31] EN +// +// Enable tracking loop. +#define CKMD_HFTRACKCTL_EN 0x80000000U +#define CKMD_HFTRACKCTL_EN_M 0x80000000U +#define CKMD_HFTRACKCTL_EN_S 31U + +// Field: [30] DSMBYP +// +// Bypass Delta-Sigma-Modulation of fine trim. +#define CKMD_HFTRACKCTL_DSMBYP 0x40000000U +#define CKMD_HFTRACKCTL_DSMBYP_M 0x40000000U +#define CKMD_HFTRACKCTL_DSMBYP_S 30U + +// Field: [27:26] REFCLK +// +// Select the reference clock for the tracking loop. +// Change only while the tracking loop is disabled. +// ENUMs: +// GPI Select GPI as reference clock. +// LRF Select LRF reference clock. +// HFXT Select HFXT as reference clock. +#define CKMD_HFTRACKCTL_REFCLK_W 2U +#define CKMD_HFTRACKCTL_REFCLK_M 0x0C000000U +#define CKMD_HFTRACKCTL_REFCLK_S 26U +#define CKMD_HFTRACKCTL_REFCLK_GPI 0x08000000U +#define CKMD_HFTRACKCTL_REFCLK_LRF 0x04000000U +#define CKMD_HFTRACKCTL_REFCLK_HFXT 0x00000000U + +// Field: [25:0] RATIO +// +// Reference clock ratio. +// +// RATIO = 24MHz / (2*reference-frequency) * 2^24 +// Commonly used reference clock frequencies are provided as enumerations. +// ENUMs: +// REF4M Use for 4MHz reference clock +// REF8M Use for 8MHz reference clock +// REF48M Use for 48MHz reference clock +#define CKMD_HFTRACKCTL_RATIO_W 26U +#define CKMD_HFTRACKCTL_RATIO_M 0x03FFFFFFU +#define CKMD_HFTRACKCTL_RATIO_S 0U +#define CKMD_HFTRACKCTL_RATIO_REF4M 0x03000000U +#define CKMD_HFTRACKCTL_RATIO_REF8M 0x01800000U +#define CKMD_HFTRACKCTL_RATIO_REF48M 0x00400000U + +//***************************************************************************** +// +// Register: CKMD_O_LDOCTL +// +//***************************************************************************** +// Field: [31] SWOVR +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_SWOVR 0x80000000U +#define CKMD_LDOCTL_SWOVR_M 0x80000000U +#define CKMD_LDOCTL_SWOVR_S 31U + +// Field: [4] HFXTLVLEN +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_HFXTLVLEN 0x00000010U +#define CKMD_LDOCTL_HFXTLVLEN_M 0x00000010U +#define CKMD_LDOCTL_HFXTLVLEN_S 4U + +// Field: [3] STARTCTL +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_STARTCTL 0x00000008U +#define CKMD_LDOCTL_STARTCTL_M 0x00000008U +#define CKMD_LDOCTL_STARTCTL_S 3U + +// Field: [2] START +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_START 0x00000004U +#define CKMD_LDOCTL_START_M 0x00000004U +#define CKMD_LDOCTL_START_S 2U + +// Field: [1] BYPASS +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_BYPASS 0x00000002U +#define CKMD_LDOCTL_BYPASS_M 0x00000002U +#define CKMD_LDOCTL_BYPASS_S 1U + +// Field: [0] EN +// +// Internal. Only to be used through TI provided API. +#define CKMD_LDOCTL_EN 0x00000001U +#define CKMD_LDOCTL_EN_M 0x00000001U +#define CKMD_LDOCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_NABIASCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Enable nanoamp-bias +#define CKMD_NABIASCTL_EN 0x00000001U +#define CKMD_NABIASCTL_EN_M 0x00000001U +#define CKMD_NABIASCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFMONCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Enable LFMONITOR. +// Enable only after a LF clock source has been selected, enabled and is +// stable. +// If LFMONITOR detects a clock loss, the system will be reset. +#define CKMD_LFMONCTL_EN 0x00000001U +#define CKMD_LFMONCTL_EN_M 0x00000001U +#define CKMD_LFMONCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LFCLKSEL +// +//***************************************************************************** +// Field: [3:2] PRE +// +// Select low frequency clock source for the PRELFCLK interrupt. +// +// Can be used by Software to confirm that the clock is running and it's +// frequency is good, before selecting it in MAIN. +// ENUMs: +// EXTLF External LF clock through GPI. +// LFXT Low frequency crystal oscillator +// LFOSC Low frequency on-chip oscillator +// NONE No clock. Output will be tied low. +#define CKMD_LFCLKSEL_PRE_W 2U +#define CKMD_LFCLKSEL_PRE_M 0x0000000CU +#define CKMD_LFCLKSEL_PRE_S 2U +#define CKMD_LFCLKSEL_PRE_EXTLF 0x0000000CU +#define CKMD_LFCLKSEL_PRE_LFXT 0x00000008U +#define CKMD_LFCLKSEL_PRE_LFOSC 0x00000004U +#define CKMD_LFCLKSEL_PRE_NONE 0x00000000U + +// Field: [1:0] MAIN +// +// Select the main low frequency clock source. +// +// If running, this clock will be used to generate LFTICK and as CLKULL during +// STANDBY. +// If not running, LFTICK will be generated from HFOSC and STANDBY entry will +// be prevented. +// ENUMs: +// EXTLF External LF clock through GPI. +// LFXT Low frequency crystal oscillator +// LFOSC Low frequency on-chip oscillator +// FAKE No LF clock selected. LFTICK will be generated +// from HFOSC, STANDBY entry will be prevented. +#define CKMD_LFCLKSEL_MAIN_W 2U +#define CKMD_LFCLKSEL_MAIN_M 0x00000003U +#define CKMD_LFCLKSEL_MAIN_S 0U +#define CKMD_LFCLKSEL_MAIN_EXTLF 0x00000003U +#define CKMD_LFCLKSEL_MAIN_LFXT 0x00000002U +#define CKMD_LFCLKSEL_MAIN_LFOSC 0x00000001U +#define CKMD_LFCLKSEL_MAIN_FAKE 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCCLKSEL +// +//***************************************************************************** +// Field: [1:0] REFCLK +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// GPI Internal. Only to be used through TI provided API. +// CLKULL Internal. Only to be used through TI provided API. +// CLKSVT Internal. Only to be used through TI provided API. +// NONE Internal. Only to be used through TI provided API. +#define CKMD_TDCCLKSEL_REFCLK_W 2U +#define CKMD_TDCCLKSEL_REFCLK_M 0x00000003U +#define CKMD_TDCCLKSEL_REFCLK_S 0U +#define CKMD_TDCCLKSEL_REFCLK_GPI 0x00000003U +#define CKMD_TDCCLKSEL_REFCLK_CLKULL 0x00000002U +#define CKMD_TDCCLKSEL_REFCLK_CLKSVT 0x00000001U +#define CKMD_TDCCLKSEL_REFCLK_NONE 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_ADCCLKSEL +// +//***************************************************************************** +// Field: [1:0] SRC +// +// Select ADC clock source +// +// Change only while ADC is disabled. +// ENUMs: +// HFXT 48MHz HFXT +// CLKSVT 48MHz CLKSVT +#define CKMD_ADCCLKSEL_SRC_W 2U +#define CKMD_ADCCLKSEL_SRC_M 0x00000003U +#define CKMD_ADCCLKSEL_SRC_S 0U +#define CKMD_ADCCLKSEL_SRC_HFXT 0x00000001U +#define CKMD_ADCCLKSEL_SRC_CLKSVT 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_LFCLKSTAT +// +//***************************************************************************** +// Field: [31] GOOD +// +// Low frequency clock good +// +// Note: This is only a coarse frequency check based on LFQUALCTL. The clock +// may not be accurate enough for timing purposes. +#define CKMD_LFCLKSTAT_GOOD 0x80000000U +#define CKMD_LFCLKSTAT_GOOD_M 0x80000000U +#define CKMD_LFCLKSTAT_GOOD_S 31U + +// Field: [25] FLTSETTLED +// +// LFINC filter is running and settled. +#define CKMD_LFCLKSTAT_FLTSETTLED 0x02000000U +#define CKMD_LFCLKSTAT_FLTSETTLED_M 0x02000000U +#define CKMD_LFCLKSTAT_FLTSETTLED_S 25U + +// Field: [24] LFTICKSRC +// +// Source of LFTICK. +// ENUMs: +// FAKE LFTICK generated from CLKULL (LFCLK not available) +// LFCLK LFTICK generated from the selected LFCLK +#define CKMD_LFCLKSTAT_LFTICKSRC 0x01000000U +#define CKMD_LFCLKSTAT_LFTICKSRC_M 0x01000000U +#define CKMD_LFCLKSTAT_LFTICKSRC_S 24U +#define CKMD_LFCLKSTAT_LFTICKSRC_FAKE 0x01000000U +#define CKMD_LFCLKSTAT_LFTICKSRC_LFCLK 0x00000000U + +// Field: [23:22] LFINCSRC +// +// Source of LFINC used by the RTC. +// +// This value depends on LFINCOVR.OVERRIDE, LF clock availability, HF tracking +// loop status and the device state (ACTIVE/STANDBY). +// ENUMs: +// FAKE Using FAKE LFTICKs with corresponding LFINC value. +// OVERRIDE Using override value from LFINCOVR.LFINC +// AVG Using filtered / average value. +// This value is updated by +// hardware and can be read and updated in +// LFINCCTL.INT. +// MEAS Using measured value. +// This value is updated by +// hardware and can be read from LFINC. +#define CKMD_LFCLKSTAT_LFINCSRC_W 2U +#define CKMD_LFCLKSTAT_LFINCSRC_M 0x00C00000U +#define CKMD_LFCLKSTAT_LFINCSRC_S 22U +#define CKMD_LFCLKSTAT_LFINCSRC_FAKE 0x00C00000U +#define CKMD_LFCLKSTAT_LFINCSRC_OVERRIDE 0x00800000U +#define CKMD_LFCLKSTAT_LFINCSRC_AVG 0x00400000U +#define CKMD_LFCLKSTAT_LFINCSRC_MEAS 0x00000000U + +// Field: [21:0] LFINC +// +// Measured value of LFINC. +// +// Given in microseconds with 16 fractional bits. +// This value is calculated by Hardware. +// It is the LFCLK period according to CLKULL cycles. +#define CKMD_LFCLKSTAT_LFINC_W 22U +#define CKMD_LFCLKSTAT_LFINC_M 0x003FFFFFU +#define CKMD_LFCLKSTAT_LFINC_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFXTSTAT +// +//***************************************************************************** +// Field: [30:16] STARTUPTIME +// +// HFXT startup time +// +// Can be used by software to plan starting HFXT ahead in time. +// Measured whenever HFXT is enabled in CLKULL periods (24MHz), from HFXTCTL.EN +// until the clock is good for radio operation (amplitude compensation is +// settled). +#define CKMD_HFXTSTAT_STARTUPTIME_W 15U +#define CKMD_HFXTSTAT_STARTUPTIME_M 0x7FFF0000U +#define CKMD_HFXTSTAT_STARTUPTIME_S 16U + +// Field: [1] FAULT +// +// HFXT clock fault +// +// Indicates a lower than expected HFXT frequency. +// HFXT will not recover from this fault, disabling and re-enabling HFXT is +// required. +#define CKMD_HFXTSTAT_FAULT 0x00000002U +#define CKMD_HFXTSTAT_FAULT_M 0x00000002U +#define CKMD_HFXTSTAT_FAULT_S 1U + +// Field: [0] GOOD +// +// HFXT clock available. +// +// The frequency is not necessarily good enough for radio operation. +#define CKMD_HFXTSTAT_GOOD 0x00000001U +#define CKMD_HFXTSTAT_GOOD_M 0x00000001U +#define CKMD_HFXTSTAT_GOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_AMPADCSTAT +// +//***************************************************************************** +// Field: [24] COMPOUT +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCSTAT_COMPOUT 0x01000000U +#define CKMD_AMPADCSTAT_COMPOUT_M 0x01000000U +#define CKMD_AMPADCSTAT_COMPOUT_S 24U + +// Field: [22:16] PEAKRAW +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCSTAT_PEAKRAW_W 7U +#define CKMD_AMPADCSTAT_PEAKRAW_M 0x007F0000U +#define CKMD_AMPADCSTAT_PEAKRAW_S 16U + +// Field: [15:8] PEAK +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCSTAT_PEAK_W 8U +#define CKMD_AMPADCSTAT_PEAK_M 0x0000FF00U +#define CKMD_AMPADCSTAT_PEAK_S 8U + +// Field: [6:0] BIAS +// +// Internal. Only to be used through TI provided API. +#define CKMD_AMPADCSTAT_BIAS_W 7U +#define CKMD_AMPADCSTAT_BIAS_M 0x0000007FU +#define CKMD_AMPADCSTAT_BIAS_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TRACKSTAT +// +//***************************************************************************** +// Field: [31] LOOPERRVLD +// +// Current HFOSC tracking error valid +// +// This bit is one if the tracking loop is running and the error value is +// valid. +#define CKMD_TRACKSTAT_LOOPERRVLD 0x80000000U +#define CKMD_TRACKSTAT_LOOPERRVLD_M 0x80000000U +#define CKMD_TRACKSTAT_LOOPERRVLD_S 31U + +// Field: [29:16] LOOPERR +// +// Current HFOSC tracking error +#define CKMD_TRACKSTAT_LOOPERR_W 14U +#define CKMD_TRACKSTAT_LOOPERR_M 0x3FFF0000U +#define CKMD_TRACKSTAT_LOOPERR_S 16U + +// Field: [12:0] FINETRIM +// +// Current HFOSC Fine-trim value +// +// This field uses the internal fractional representation (sign, 4 integer +// bits, 8 fractional bits). +// The actual trim value applied to the oscillator is delta-sigma modulated 5 +// bits non-signed +// (inverted sign bit + integer bits). +#define CKMD_TRACKSTAT_FINETRIM_W 13U +#define CKMD_TRACKSTAT_FINETRIM_M 0x00001FFFU +#define CKMD_TRACKSTAT_FINETRIM_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_AMPSTAT +// +//***************************************************************************** +// Field: [28:25] STATE +// +// Current AMPCOMP FSM state. +// ENUMs: +// SETTLED Settled state +// UPDATEUP Amplitude up correction +// TXCOMODE TCXO settled state +// SHUTDN0 First shutdown state +// INJWAIT Post injection settle wait +// UPDATEDN Amplitude down correction +// RAMP0 Initial amplitude ramping with HFXTINIT values +// RAMP1 Transition to HFXTTARG values +// INJECT Injecting HFOSC for fast startup +// SHUTDN1 Second shutdown state +// LDOSTART Starting LDO +// IDLE FSM in idle state +#define CKMD_AMPSTAT_STATE_W 4U +#define CKMD_AMPSTAT_STATE_M 0x1E000000U +#define CKMD_AMPSTAT_STATE_S 25U +#define CKMD_AMPSTAT_STATE_SETTLED 0x1E000000U +#define CKMD_AMPSTAT_STATE_UPDATEUP 0x1C000000U +#define CKMD_AMPSTAT_STATE_TXCOMODE 0x18000000U +#define CKMD_AMPSTAT_STATE_SHUTDN0 0x14000000U +#define CKMD_AMPSTAT_STATE_INJWAIT 0x0E000000U +#define CKMD_AMPSTAT_STATE_UPDATEDN 0x0C000000U +#define CKMD_AMPSTAT_STATE_RAMP0 0x0A000000U +#define CKMD_AMPSTAT_STATE_RAMP1 0x08000000U +#define CKMD_AMPSTAT_STATE_INJECT 0x06000000U +#define CKMD_AMPSTAT_STATE_SHUTDN1 0x04000000U +#define CKMD_AMPSTAT_STATE_LDOSTART 0x02000000U +#define CKMD_AMPSTAT_STATE_IDLE 0x00000000U + +// Field: [24:18] IDAC +// +// Current IDAC control value. +#define CKMD_AMPSTAT_IDAC_W 7U +#define CKMD_AMPSTAT_IDAC_M 0x01FC0000U +#define CKMD_AMPSTAT_IDAC_S 18U + +// Field: [17:14] IREF +// +// Current IREF control value. +#define CKMD_AMPSTAT_IREF_W 4U +#define CKMD_AMPSTAT_IREF_M 0x0003C000U +#define CKMD_AMPSTAT_IREF_S 14U + +// Field: [13:8] Q2CAP +// +// Current Q2CAP control value. +#define CKMD_AMPSTAT_Q2CAP_W 6U +#define CKMD_AMPSTAT_Q2CAP_M 0x00003F00U +#define CKMD_AMPSTAT_Q2CAP_S 8U + +// Field: [7:2] Q1CAP +// +// Current Q1CAP control value. +#define CKMD_AMPSTAT_Q1CAP_W 6U +#define CKMD_AMPSTAT_Q1CAP_M 0x000000FCU +#define CKMD_AMPSTAT_Q1CAP_S 2U + +// Field: [1] CTRLATTARGET +// +// HFXT control values match target values. +// +// This applies to IREF, Q1CAP, Q2CAP values. +#define CKMD_AMPSTAT_CTRLATTARGET 0x00000002U +#define CKMD_AMPSTAT_CTRLATTARGET_M 0x00000002U +#define CKMD_AMPSTAT_CTRLATTARGET_S 1U + +// Field: [0] AMPGOOD +// +// HFXT amplitude good +#define CKMD_AMPSTAT_AMPGOOD 0x00000001U +#define CKMD_AMPSTAT_AMPGOOD_M 0x00000001U +#define CKMD_AMPSTAT_AMPGOOD_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_ATBCTL0 +// +//***************************************************************************** +// Field: [18:0] SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// LFXTTESTCLK Internal. Only to be used through TI provided API. +// LFOSCTESTCLK Internal. Only to be used through TI provided API. +// HFXTTESTCLK Internal. Only to be used through TI provided API. +// HFOSCTESTCLK Internal. Only to be used through TI provided API. +// LFMONVTEST Internal. Only to be used through TI provided API. +// LFOSCVDDL Internal. Only to be used through TI provided API. +// HFOSCIBIAS Internal. Only to be used through TI provided API. +// HFOSCVDDL Internal. Only to be used through TI provided API. +// HFOSCVREF Internal. Only to be used through TI provided API. +// NABIASITEST Internal. Only to be used through TI provided API. +// ADCDACOUT Internal. Only to be used through TI provided API. +// ADCCOMPIN Internal. Only to be used through TI provided API. +// ADCCOMPOUT Internal. Only to be used through TI provided API. +// LFXTANA Internal. Only to be used through TI provided API. +// LDOITEST Internal. Only to be used through TI provided API. +// VDDCKM Internal. Only to be used through TI provided API. +// HFXTANA Internal. Only to be used through TI provided API. +// OFF Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL0_SEL_W 19U +#define CKMD_ATBCTL0_SEL_M 0x0007FFFFU +#define CKMD_ATBCTL0_SEL_S 0U +#define CKMD_ATBCTL0_SEL_LFXTTESTCLK 0x00070000U +#define CKMD_ATBCTL0_SEL_LFOSCTESTCLK 0x00050000U +#define CKMD_ATBCTL0_SEL_HFXTTESTCLK 0x00030000U +#define CKMD_ATBCTL0_SEL_HFOSCTESTCLK 0x00010000U +#define CKMD_ATBCTL0_SEL_LFMONVTEST 0x00001000U +#define CKMD_ATBCTL0_SEL_LFOSCVDDL 0x00000800U +#define CKMD_ATBCTL0_SEL_HFOSCIBIAS 0x00000400U +#define CKMD_ATBCTL0_SEL_HFOSCVDDL 0x00000200U +#define CKMD_ATBCTL0_SEL_HFOSCVREF 0x00000100U +#define CKMD_ATBCTL0_SEL_NABIASITEST 0x00000080U +#define CKMD_ATBCTL0_SEL_ADCDACOUT 0x00000040U +#define CKMD_ATBCTL0_SEL_ADCCOMPIN 0x00000020U +#define CKMD_ATBCTL0_SEL_ADCCOMPOUT 0x00000010U +#define CKMD_ATBCTL0_SEL_LFXTANA 0x00000008U +#define CKMD_ATBCTL0_SEL_LDOITEST 0x00000004U +#define CKMD_ATBCTL0_SEL_VDDCKM 0x00000002U +#define CKMD_ATBCTL0_SEL_HFXTANA 0x00000001U +#define CKMD_ATBCTL0_SEL_OFF 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_ATBCTL1 +// +//***************************************************************************** +// Field: [14:13] LFOSC +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BOTH Internal. Only to be used through TI provided API. +// VDDLOCAL Internal. Only to be used through TI provided API. +// TESTCLK Internal. Only to be used through TI provided API. +// OFF Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_LFOSC_W 2U +#define CKMD_ATBCTL1_LFOSC_M 0x00006000U +#define CKMD_ATBCTL1_LFOSC_S 13U +#define CKMD_ATBCTL1_LFOSC_BOTH 0x00006000U +#define CKMD_ATBCTL1_LFOSC_VDDLOCAL 0x00004000U +#define CKMD_ATBCTL1_LFOSC_TESTCLK 0x00002000U +#define CKMD_ATBCTL1_LFOSC_OFF 0x00000000U + +// Field: [12] NABIAS +// +// Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_NABIAS 0x00001000U +#define CKMD_ATBCTL1_NABIAS_M 0x00001000U +#define CKMD_ATBCTL1_NABIAS_S 12U + +// Field: [10] LFXT +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TESTCLK Internal. Only to be used through TI provided API. +// OFF Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_LFXT 0x00000400U +#define CKMD_ATBCTL1_LFXT_M 0x00000400U +#define CKMD_ATBCTL1_LFXT_S 10U +#define CKMD_ATBCTL1_LFXT_TESTCLK 0x00000400U +#define CKMD_ATBCTL1_LFXT_OFF 0x00000000U + +// Field: [9:8] LFMON +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TEST2 Internal. Only to be used through TI provided API. +// TEST1 Internal. Only to be used through TI provided API. +// OFF Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_LFMON_W 2U +#define CKMD_ATBCTL1_LFMON_M 0x00000300U +#define CKMD_ATBCTL1_LFMON_S 8U +#define CKMD_ATBCTL1_LFMON_TEST2 0x00000200U +#define CKMD_ATBCTL1_LFMON_TEST1 0x00000100U +#define CKMD_ATBCTL1_LFMON_OFF 0x00000000U + +// Field: [7] HFXT +// +// Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_HFXT 0x00000080U +#define CKMD_ATBCTL1_HFXT_M 0x00000080U +#define CKMD_ATBCTL1_HFXT_S 7U + +// Field: [0] HFOSC +// +// Internal. Only to be used through TI provided API. +#define CKMD_ATBCTL1_HFOSC 0x00000001U +#define CKMD_ATBCTL1_HFOSC_M 0x00000001U +#define CKMD_ATBCTL1_HFOSC_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_DTBCTL +// +//***************************************************************************** +// Field: [22:18] DSEL2 +// +// Internal. Only to be used through TI provided API. +#define CKMD_DTBCTL_DSEL2_W 5U +#define CKMD_DTBCTL_DSEL2_M 0x007C0000U +#define CKMD_DTBCTL_DSEL2_S 18U + +// Field: [17:13] DSEL1 +// +// Internal. Only to be used through TI provided API. +#define CKMD_DTBCTL_DSEL1_W 5U +#define CKMD_DTBCTL_DSEL1_M 0x0003E000U +#define CKMD_DTBCTL_DSEL1_S 13U + +// Field: [12:8] DSEL0 +// +// Internal. Only to be used through TI provided API. +#define CKMD_DTBCTL_DSEL0_W 5U +#define CKMD_DTBCTL_DSEL0_M 0x00001F00U +#define CKMD_DTBCTL_DSEL0_S 8U + +// Field: [7:4] CLKSEL +// +// Select clock to output on DTB[0] +// ENUMs: +// LFXT Select LFXT +// LFOSC Select LFOSC +// HFXT Select HFXT +// HFXTBY8 Select HFXT divided by 8 +// HFOSC Select HFOSC after qualification +// LFCLK Select LFCLK (selected by LFCLKSEL.MAIN) +// TRACKREF Select tracking loop reference clock +// CLKADC Select CLKADC (48 MHz) +// CLKSVT Select CLKSVT (48 MHz) +// CLKULL Select CLKULL (24 MHz during ACTIVE, 32kHz during +// STANDBY) +#define CKMD_DTBCTL_CLKSEL_W 4U +#define CKMD_DTBCTL_CLKSEL_M 0x000000F0U +#define CKMD_DTBCTL_CLKSEL_S 4U +#define CKMD_DTBCTL_CLKSEL_LFXT 0x000000F0U +#define CKMD_DTBCTL_CLKSEL_LFOSC 0x000000E0U +#define CKMD_DTBCTL_CLKSEL_HFXT 0x000000D0U +#define CKMD_DTBCTL_CLKSEL_HFXTBY8 0x000000C0U +#define CKMD_DTBCTL_CLKSEL_HFOSC 0x000000A0U +#define CKMD_DTBCTL_CLKSEL_LFCLK 0x00000070U +#define CKMD_DTBCTL_CLKSEL_TRACKREF 0x00000040U +#define CKMD_DTBCTL_CLKSEL_CLKADC 0x00000020U +#define CKMD_DTBCTL_CLKSEL_CLKSVT 0x00000010U +#define CKMD_DTBCTL_CLKSEL_CLKULL 0x00000000U + +// Field: [0] EN +// +// Enable DTB output +#define CKMD_DTBCTL_EN 0x00000001U +#define CKMD_DTBCTL_EN_M 0x00000001U +#define CKMD_DTBCTL_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TRIM0 +// +//***************************************************************************** +// Field: [8:5] HFOSC_CAP +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM0_HFOSC_CAP_W 4U +#define CKMD_TRIM0_HFOSC_CAP_M 0x000001E0U +#define CKMD_TRIM0_HFOSC_CAP_S 5U + +// Field: [4:0] HFOSC_COARSE +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM0_HFOSC_COARSE_W 5U +#define CKMD_TRIM0_HFOSC_COARSE_M 0x0000001FU +#define CKMD_TRIM0_HFOSC_COARSE_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TRIM1 +// +//***************************************************************************** +// Field: [31:30] HFXTSLICER +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_HFXTSLICER_W 2U +#define CKMD_TRIM1_HFXTSLICER_M 0xC0000000U +#define CKMD_TRIM1_HFXTSLICER_S 30U + +// Field: [29:28] PEAKIBIAS +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_PEAKIBIAS_W 2U +#define CKMD_TRIM1_PEAKIBIAS_M 0x30000000U +#define CKMD_TRIM1_PEAKIBIAS_S 28U + +// Field: [27] NABIAS_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_NABIAS_UDIGLDO 0x08000000U +#define CKMD_TRIM1_NABIAS_UDIGLDO_M 0x08000000U +#define CKMD_TRIM1_NABIAS_UDIGLDO_S 27U + +// Field: [26:24] LDOBW +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_LDOBW_W 3U +#define CKMD_TRIM1_LDOBW_M 0x07000000U +#define CKMD_TRIM1_LDOBW_S 24U + +// Field: [23:20] LDOFB +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_LDOFB_W 4U +#define CKMD_TRIM1_LDOFB_M 0x00F00000U +#define CKMD_TRIM1_LDOFB_S 20U + +// Field: [19:16] LFDLY +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_LFDLY_W 4U +#define CKMD_TRIM1_LFDLY_M 0x000F0000U +#define CKMD_TRIM1_LFDLY_S 16U + +// Field: [15] NABIAS_LFOSC +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_NABIAS_LFOSC 0x00008000U +#define CKMD_TRIM1_NABIAS_LFOSC_M 0x00008000U +#define CKMD_TRIM1_NABIAS_LFOSC_S 15U + +// Field: [14:8] NABIAS_RES +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_NABIAS_RES_W 7U +#define CKMD_TRIM1_NABIAS_RES_M 0x00007F00U +#define CKMD_TRIM1_NABIAS_RES_S 8U + +// Field: [7:0] LFOSC_CAP +// +// Internal. Only to be used through TI provided API. +#define CKMD_TRIM1_LFOSC_CAP_W 8U +#define CKMD_TRIM1_LFOSC_CAP_M 0x000000FFU +#define CKMD_TRIM1_LFOSC_CAP_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFXTINIT +// +//***************************************************************************** +// Field: [29:23] AMPTHR +// +// Amplitude threshold during HFXT ramping +#define CKMD_HFXTINIT_AMPTHR_W 7U +#define CKMD_HFXTINIT_AMPTHR_M 0x3F800000U +#define CKMD_HFXTINIT_AMPTHR_S 23U + +// Field: [22:16] IDAC +// +// Initial HFXT IDAC current +#define CKMD_HFXTINIT_IDAC_W 7U +#define CKMD_HFXTINIT_IDAC_M 0x007F0000U +#define CKMD_HFXTINIT_IDAC_S 16U + +// Field: [15:12] IREF +// +// Initial HFXT IREF current +#define CKMD_HFXTINIT_IREF_W 4U +#define CKMD_HFXTINIT_IREF_M 0x0000F000U +#define CKMD_HFXTINIT_IREF_S 12U + +// Field: [11:6] Q2CAP +// +// Initial HFXT Q2 cap trim +#define CKMD_HFXTINIT_Q2CAP_W 6U +#define CKMD_HFXTINIT_Q2CAP_M 0x00000FC0U +#define CKMD_HFXTINIT_Q2CAP_S 6U + +// Field: [5:0] Q1CAP +// +// Initial HFXT Q1 cap trim +#define CKMD_HFXTINIT_Q1CAP_W 6U +#define CKMD_HFXTINIT_Q1CAP_M 0x0000003FU +#define CKMD_HFXTINIT_Q1CAP_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFXTTARG +// +//***************************************************************************** +// Field: [31:30] AMPHYST +// +// ADC hysteresis used during IDAC updates. +// +// Every AMPCFG1.INTERVAL, IDAC will be regulated +// - up as long as ADC < AMPTHR +// - down as long as ADC > AMPTHR+AMPHYST +#define CKMD_HFXTTARG_AMPHYST_W 2U +#define CKMD_HFXTTARG_AMPHYST_M 0xC0000000U +#define CKMD_HFXTTARG_AMPHYST_S 30U + +// Field: [29:23] AMPTHR +// +// Minimum HFXT amplitude +#define CKMD_HFXTTARG_AMPTHR_W 7U +#define CKMD_HFXTTARG_AMPTHR_M 0x3F800000U +#define CKMD_HFXTTARG_AMPTHR_S 23U + +// Field: [22:16] IDAC +// +// Minimum IDAC current +#define CKMD_HFXTTARG_IDAC_W 7U +#define CKMD_HFXTTARG_IDAC_M 0x007F0000U +#define CKMD_HFXTTARG_IDAC_S 16U + +// Field: [15:12] IREF +// +// Target HFXT IREF current +#define CKMD_HFXTTARG_IREF_W 4U +#define CKMD_HFXTTARG_IREF_M 0x0000F000U +#define CKMD_HFXTTARG_IREF_S 12U + +// Field: [11:6] Q2CAP +// +// Target HFXT Q2 cap trim +#define CKMD_HFXTTARG_Q2CAP_W 6U +#define CKMD_HFXTTARG_Q2CAP_M 0x00000FC0U +#define CKMD_HFXTTARG_Q2CAP_S 6U + +// Field: [5:0] Q1CAP +// +// Target HFXT Q1 cap trim +#define CKMD_HFXTTARG_Q1CAP_W 6U +#define CKMD_HFXTTARG_Q1CAP_M 0x0000003FU +#define CKMD_HFXTTARG_Q1CAP_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_HFXTDYN +// +//***************************************************************************** +// Field: [31] SEL +// +// Select the dynamic configuration. +// +// Amplitude ramping will always happen using the values in HFXTINIT, and +// HFXTTARG. +// Afterwards, this bit can be used to select between HFXTTARG and HFXTDYN. +// Hardware will ensure a smooth transition of analog control signals. +// ENUMs: +// DYNAMIC Select configuration in HFXTDYN. +// TARGET Select configuration in HFXTTARG. +#define CKMD_HFXTDYN_SEL 0x80000000U +#define CKMD_HFXTDYN_SEL_M 0x80000000U +#define CKMD_HFXTDYN_SEL_S 31U +#define CKMD_HFXTDYN_SEL_DYNAMIC 0x80000000U +#define CKMD_HFXTDYN_SEL_TARGET 0x00000000U + +// Field: [29:23] AMPTHR +// +// Minimum HFXT amplitude +#define CKMD_HFXTDYN_AMPTHR_W 7U +#define CKMD_HFXTDYN_AMPTHR_M 0x3F800000U +#define CKMD_HFXTDYN_AMPTHR_S 23U + +// Field: [22:16] IDAC +// +// Minimum IDAC current +#define CKMD_HFXTDYN_IDAC_W 7U +#define CKMD_HFXTDYN_IDAC_M 0x007F0000U +#define CKMD_HFXTDYN_IDAC_S 16U + +// Field: [15:12] IREF +// +// Target HFXT IREF current +#define CKMD_HFXTDYN_IREF_W 4U +#define CKMD_HFXTDYN_IREF_M 0x0000F000U +#define CKMD_HFXTDYN_IREF_S 12U + +// Field: [11:6] Q2CAP +// +// Target HFXT Q2 cap trim +#define CKMD_HFXTDYN_Q2CAP_W 6U +#define CKMD_HFXTDYN_Q2CAP_M 0x00000FC0U +#define CKMD_HFXTDYN_Q2CAP_S 6U + +// Field: [5:0] Q1CAP +// +// Target HFXT Q1 cap trim +#define CKMD_HFXTDYN_Q1CAP_W 6U +#define CKMD_HFXTDYN_Q1CAP_M 0x0000003FU +#define CKMD_HFXTDYN_Q1CAP_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_AMPCFG0 +// +//***************************************************************************** +// Field: [31:28] Q2DLY +// +// Q2CAP change delay. +// +// Number of clock cycles to wait before changing Q2CAP by one step. +// Clock frequency defined in FSMRATE. +#define CKMD_AMPCFG0_Q2DLY_W 4U +#define CKMD_AMPCFG0_Q2DLY_M 0xF0000000U +#define CKMD_AMPCFG0_Q2DLY_S 28U + +// Field: [27:24] Q1DLY +// +// Q1CAP change delay. +// +// Number of clock cycles to wait before changing Q1CAP by one step. +// Clock frequency defined in FSMRATE. +#define CKMD_AMPCFG0_Q1DLY_W 4U +#define CKMD_AMPCFG0_Q1DLY_M 0x0F000000U +#define CKMD_AMPCFG0_Q1DLY_S 24U + +// Field: [23:20] ADCDLY +// +// ADC and PEAKDET startup time. +// +// Number of clock cycles to wait after enabling the PEAKDET and ADC before the +// first measurement. +// Clock frequency defined in FSMRATE. +#define CKMD_AMPCFG0_ADCDLY_W 4U +#define CKMD_AMPCFG0_ADCDLY_M 0x00F00000U +#define CKMD_AMPCFG0_ADCDLY_S 20U + +// Field: [19:15] LDOSTART +// +// LDO startup time. +// +// Number of clock cycles to bypass the LDO resistors for faster startup. +// Clock frequency defined in FSMRATE. +#define CKMD_AMPCFG0_LDOSTART_W 5U +#define CKMD_AMPCFG0_LDOSTART_M 0x000F8000U +#define CKMD_AMPCFG0_LDOSTART_S 15U + +// Field: [14:10] INJWAIT +// +// Inject HFOSC for faster HFXT startup. +// +// This value specifies the number of clock cycles to wait after injection is +// done. +// The clock speed is defined in FSMRATE. +#define CKMD_AMPCFG0_INJWAIT_W 5U +#define CKMD_AMPCFG0_INJWAIT_M 0x00007C00U +#define CKMD_AMPCFG0_INJWAIT_S 10U + +// Field: [9:5] INJTIME +// +// Inject HFOSC for faster HFXT startup. +// +// This value specifies the number of clock cycles the injection is enabled. +// The clock speed is defined in FSMRATE. +// Set to 0 to disable injection. +#define CKMD_AMPCFG0_INJTIME_W 5U +#define CKMD_AMPCFG0_INJTIME_M 0x000003E0U +#define CKMD_AMPCFG0_INJTIME_S 5U + +// Field: [4:0] FSMRATE +// +// Update rate for the AMPCOMP update rate. +// Also affects the clock rate for the Amplitude ADC. +// +// The update rate is 6MHz / (FSMRATE+1). +// ENUMs: +// _250K 250 kHz +// _500K 500 kHz +// _1M 1 MHz +// _2M 2 MHz +// _3M 3 MHz +// _6M 6 MHz +#define CKMD_AMPCFG0_FSMRATE_W 5U +#define CKMD_AMPCFG0_FSMRATE_M 0x0000001FU +#define CKMD_AMPCFG0_FSMRATE_S 0U +#define CKMD_AMPCFG0_FSMRATE__250K 0x00000017U +#define CKMD_AMPCFG0_FSMRATE__500K 0x0000000BU +#define CKMD_AMPCFG0_FSMRATE__1M 0x00000005U +#define CKMD_AMPCFG0_FSMRATE__2M 0x00000002U +#define CKMD_AMPCFG0_FSMRATE__3M 0x00000001U +#define CKMD_AMPCFG0_FSMRATE__6M 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_AMPCFG1 +// +//***************************************************************************** +// Field: [31:28] IDACDLY +// +// IDAC change delay. +// +// Time to wait before changing IDAC by one step. +// This time needs to be long enough for the crystal to settle. +// The number of clock cycles to wait is IDACDLY<<4 + 15. +// Clock frequency defined in AMPCFG0.FSMRATE. +#define CKMD_AMPCFG1_IDACDLY_W 4U +#define CKMD_AMPCFG1_IDACDLY_M 0xF0000000U +#define CKMD_AMPCFG1_IDACDLY_S 28U + +// Field: [27:24] IREFDLY +// +// IREF change delay. +// +// Number of clock cycles to wait before changing IREF by one step. +// Clock frequency defined in AMPCFG0.FSMRATE. +#define CKMD_AMPCFG1_IREFDLY_W 4U +#define CKMD_AMPCFG1_IREFDLY_M 0x0F000000U +#define CKMD_AMPCFG1_IREFDLY_S 24U + +// Field: [23:12] BIASLT +// +// Lifetime of the amplitude ADC bias value. +// This value specifies the number of adjustment intervals, +// until the ADC bias value has to be measured again. +// Set to 0 to disable automatic bias measurements. +#define CKMD_AMPCFG1_BIASLT_W 12U +#define CKMD_AMPCFG1_BIASLT_M 0x00FFF000U +#define CKMD_AMPCFG1_BIASLT_S 12U + +// Field: [11:0] INTERVAL +// +// Interval for amplitude adjustments. +// Set to 0 to disable periodic adjustments. +// +// This value specifies the number of clock cycles between adjustments. +// The clock speed is defined in AMPCFG0.FSMRATE. +#define CKMD_AMPCFG1_INTERVAL_W 12U +#define CKMD_AMPCFG1_INTERVAL_M 0x00000FFFU +#define CKMD_AMPCFG1_INTERVAL_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_LOOPCFG +// +//***************************************************************************** +// Field: [31:26] FINETRIM_INIT +// +// Initial value for the resistor fine trim +#define CKMD_LOOPCFG_FINETRIM_INIT_W 6U +#define CKMD_LOOPCFG_FINETRIM_INIT_M 0xFC000000U +#define CKMD_LOOPCFG_FINETRIM_INIT_S 26U + +// Field: [25:21] BOOST_TARGET +// +// Number of error-updates using BOOST values, before using KI/KP +#define CKMD_LOOPCFG_BOOST_TARGET_W 5U +#define CKMD_LOOPCFG_BOOST_TARGET_M 0x03E00000U +#define CKMD_LOOPCFG_BOOST_TARGET_S 21U + +// Field: [20:18] KP_BOOST +// +// Proportional loop coefficient during BOOST +#define CKMD_LOOPCFG_KP_BOOST_W 3U +#define CKMD_LOOPCFG_KP_BOOST_M 0x001C0000U +#define CKMD_LOOPCFG_KP_BOOST_S 18U + +// Field: [17:15] KI_BOOST +// +// Integral loop coefficient during BOOST +#define CKMD_LOOPCFG_KI_BOOST_W 3U +#define CKMD_LOOPCFG_KI_BOOST_M 0x00038000U +#define CKMD_LOOPCFG_KI_BOOST_S 15U + +// Field: [14:10] SETTLED_TARGET +// +// Number of updates before HFOSC is considered "settled" +#define CKMD_LOOPCFG_SETTLED_TARGET_W 5U +#define CKMD_LOOPCFG_SETTLED_TARGET_M 0x00007C00U +#define CKMD_LOOPCFG_SETTLED_TARGET_S 10U + +// Field: [9:6] OOR_LIMIT +// +// Out-of-range threshold +#define CKMD_LOOPCFG_OOR_LIMIT_W 4U +#define CKMD_LOOPCFG_OOR_LIMIT_M 0x000003C0U +#define CKMD_LOOPCFG_OOR_LIMIT_S 6U + +// Field: [5:3] KP +// +// Proportional loop coefficient +#define CKMD_LOOPCFG_KP_W 3U +#define CKMD_LOOPCFG_KP_M 0x00000038U +#define CKMD_LOOPCFG_KP_S 3U + +// Field: [2:0] KI +// +// Integral loop coefficient +#define CKMD_LOOPCFG_KI_W 3U +#define CKMD_LOOPCFG_KI_M 0x00000007U +#define CKMD_LOOPCFG_KI_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TDCCTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ABORT Internal. Only to be used through TI provided API. +// RUN Internal. Only to be used through TI provided API. +// RUN_SYNC_START Internal. Only to be used through TI provided API. +// CLR_RESULT Internal. Only to be used through TI provided API. +#define CKMD_TDCCTL_CMD_W 2U +#define CKMD_TDCCTL_CMD_M 0x00000003U +#define CKMD_TDCCTL_CMD_S 0U +#define CKMD_TDCCTL_CMD_ABORT 0x00000003U +#define CKMD_TDCCTL_CMD_RUN 0x00000002U +#define CKMD_TDCCTL_CMD_RUN_SYNC_START 0x00000001U +#define CKMD_TDCCTL_CMD_CLR_RESULT 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCSTAT +// +//***************************************************************************** +// Field: [9] STOP_BF +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCSTAT_STOP_BF 0x00000200U +#define CKMD_TDCSTAT_STOP_BF_M 0x00000200U +#define CKMD_TDCSTAT_STOP_BF_S 9U + +// Field: [8] START_BF +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCSTAT_START_BF 0x00000100U +#define CKMD_TDCSTAT_START_BF_M 0x00000100U +#define CKMD_TDCSTAT_START_BF_S 8U + +// Field: [7] SAT +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCSTAT_SAT 0x00000080U +#define CKMD_TDCSTAT_SAT_M 0x00000080U +#define CKMD_TDCSTAT_SAT_S 7U + +// Field: [6] DONE +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCSTAT_DONE 0x00000040U +#define CKMD_TDCSTAT_DONE_M 0x00000040U +#define CKMD_TDCSTAT_DONE_S 6U + +// Field: [5:0] STATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// FORCE_STOP Internal. Only to be used through TI provided API. +// START_FALL Internal. Only to be used through TI provided API. +// WAIT_CLR_CNT_DONE Internal. Only to be used through TI provided API. +// POR Internal. Only to be used through TI provided API. +// GET_RESULT Internal. Only to be used through TI provided API. +// WAIT_STOP_CNTDWN Internal. Only to be used through TI provided API. +// WAIT_STOP Internal. Only to be used through TI provided API. +// CLR_CNT Internal. Only to be used through TI provided API. +// IDLE Internal. Only to be used through TI provided API. +// WAIT_START_STOP_CNT_EN Internal. Only to be used through TI provided API. +// WAIT_START Internal. Only to be used through TI provided API. +#define CKMD_TDCSTAT_STATE_W 6U +#define CKMD_TDCSTAT_STATE_M 0x0000003FU +#define CKMD_TDCSTAT_STATE_S 0U +#define CKMD_TDCSTAT_STATE_FORCE_STOP 0x0000002EU +#define CKMD_TDCSTAT_STATE_START_FALL 0x0000001EU +#define CKMD_TDCSTAT_STATE_WAIT_CLR_CNT_DONE 0x00000016U +#define CKMD_TDCSTAT_STATE_POR 0x0000000FU +#define CKMD_TDCSTAT_STATE_GET_RESULT 0x0000000EU +#define CKMD_TDCSTAT_STATE_WAIT_STOP_CNTDWN 0x0000000CU +#define CKMD_TDCSTAT_STATE_WAIT_STOP 0x00000008U +#define CKMD_TDCSTAT_STATE_CLR_CNT 0x00000007U +#define CKMD_TDCSTAT_STATE_IDLE 0x00000006U +#define CKMD_TDCSTAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004U +#define CKMD_TDCSTAT_STATE_WAIT_START 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCRESULT +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCRESULT_VALUE_W 32U +#define CKMD_TDCRESULT_VALUE_M 0xFFFFFFFFU +#define CKMD_TDCRESULT_VALUE_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TDCSATCFG +// +//***************************************************************************** +// Field: [4:0] LIMIT +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// R30 Internal. Only to be used through TI provided API. +// R29 Internal. Only to be used through TI provided API. +// R28 Internal. Only to be used through TI provided API. +// R27 Internal. Only to be used through TI provided API. +// R26 Internal. Only to be used through TI provided API. +// R25 Internal. Only to be used through TI provided API. +// R24 Internal. Only to be used through TI provided API. +// R23 Internal. Only to be used through TI provided API. +// R22 Internal. Only to be used through TI provided API. +// R21 Internal. Only to be used through TI provided API. +// R20 Internal. Only to be used through TI provided API. +// R19 Internal. Only to be used through TI provided API. +// R18 Internal. Only to be used through TI provided API. +// R17 Internal. Only to be used through TI provided API. +// R16 Internal. Only to be used through TI provided API. +// R15 Internal. Only to be used through TI provided API. +// R14 Internal. Only to be used through TI provided API. +// R13 Internal. Only to be used through TI provided API. +// R12 Internal. Only to be used through TI provided API. +// NONE Internal. Only to be used through TI provided API. +#define CKMD_TDCSATCFG_LIMIT_W 5U +#define CKMD_TDCSATCFG_LIMIT_M 0x0000001FU +#define CKMD_TDCSATCFG_LIMIT_S 0U +#define CKMD_TDCSATCFG_LIMIT_R30 0x00000015U +#define CKMD_TDCSATCFG_LIMIT_R29 0x00000014U +#define CKMD_TDCSATCFG_LIMIT_R28 0x00000013U +#define CKMD_TDCSATCFG_LIMIT_R27 0x00000012U +#define CKMD_TDCSATCFG_LIMIT_R26 0x00000011U +#define CKMD_TDCSATCFG_LIMIT_R25 0x00000010U +#define CKMD_TDCSATCFG_LIMIT_R24 0x0000000FU +#define CKMD_TDCSATCFG_LIMIT_R23 0x0000000EU +#define CKMD_TDCSATCFG_LIMIT_R22 0x0000000DU +#define CKMD_TDCSATCFG_LIMIT_R21 0x0000000CU +#define CKMD_TDCSATCFG_LIMIT_R20 0x0000000BU +#define CKMD_TDCSATCFG_LIMIT_R19 0x0000000AU +#define CKMD_TDCSATCFG_LIMIT_R18 0x00000009U +#define CKMD_TDCSATCFG_LIMIT_R17 0x00000008U +#define CKMD_TDCSATCFG_LIMIT_R16 0x00000007U +#define CKMD_TDCSATCFG_LIMIT_R15 0x00000006U +#define CKMD_TDCSATCFG_LIMIT_R14 0x00000005U +#define CKMD_TDCSATCFG_LIMIT_R13 0x00000004U +#define CKMD_TDCSATCFG_LIMIT_R12 0x00000003U +#define CKMD_TDCSATCFG_LIMIT_NONE 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCTRIGSRC +// +//***************************************************************************** +// Field: [15] STOP_POL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// LOW Internal. Only to be used through TI provided API. +// HIGH Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGSRC_STOP_POL 0x00008000U +#define CKMD_TDCTRIGSRC_STOP_POL_M 0x00008000U +#define CKMD_TDCTRIGSRC_STOP_POL_S 15U +#define CKMD_TDCTRIGSRC_STOP_POL_LOW 0x00008000U +#define CKMD_TDCTRIGSRC_STOP_POL_HIGH 0x00000000U + +// Field: [12:8] STOP_SRC +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TDC_PRE Internal. Only to be used through TI provided API. +// DTB15 Internal. Only to be used through TI provided API. +// DTB14 Internal. Only to be used through TI provided API. +// DTB13 Internal. Only to be used through TI provided API. +// DTB12 Internal. Only to be used through TI provided API. +// DTB11 Internal. Only to be used through TI provided API. +// DTB10 Internal. Only to be used through TI provided API. +// DTB9 Internal. Only to be used through TI provided API. +// DTB8 Internal. Only to be used through TI provided API. +// DTB7 Internal. Only to be used through TI provided API. +// DTB6 Internal. Only to be used through TI provided API. +// DTB5 Internal. Only to be used through TI provided API. +// DTB4 Internal. Only to be used through TI provided API. +// DTB3 Internal. Only to be used through TI provided API. +// DTB2 Internal. Only to be used through TI provided API. +// DTB1 Internal. Only to be used through TI provided API. +// DTB0 Internal. Only to be used through TI provided API. +// GPI Internal. Only to be used through TI provided API. +// LFCLK_DLY Internal. Only to be used through TI provided API. +// LFXT Internal. Only to be used through TI provided API. +// LFOSC Internal. Only to be used through TI provided API. +// LFTICK Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGSRC_STOP_SRC_W 5U +#define CKMD_TDCTRIGSRC_STOP_SRC_M 0x00001F00U +#define CKMD_TDCTRIGSRC_STOP_SRC_S 8U +#define CKMD_TDCTRIGSRC_STOP_SRC_TDC_PRE 0x00001F00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB15 0x00001400U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB14 0x00001300U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB13 0x00001200U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB12 0x00001100U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB11 0x00001000U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB10 0x00000F00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB9 0x00000E00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB8 0x00000D00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB7 0x00000C00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB6 0x00000B00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB5 0x00000A00U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB4 0x00000900U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB3 0x00000800U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB2 0x00000700U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB1 0x00000600U +#define CKMD_TDCTRIGSRC_STOP_SRC_DTB0 0x00000500U +#define CKMD_TDCTRIGSRC_STOP_SRC_GPI 0x00000400U +#define CKMD_TDCTRIGSRC_STOP_SRC_LFCLK_DLY 0x00000300U +#define CKMD_TDCTRIGSRC_STOP_SRC_LFXT 0x00000200U +#define CKMD_TDCTRIGSRC_STOP_SRC_LFOSC 0x00000100U +#define CKMD_TDCTRIGSRC_STOP_SRC_LFTICK 0x00000000U + +// Field: [7] START_POL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// LOW Internal. Only to be used through TI provided API. +// HIGH Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGSRC_START_POL 0x00000080U +#define CKMD_TDCTRIGSRC_START_POL_M 0x00000080U +#define CKMD_TDCTRIGSRC_START_POL_S 7U +#define CKMD_TDCTRIGSRC_START_POL_LOW 0x00000080U +#define CKMD_TDCTRIGSRC_START_POL_HIGH 0x00000000U + +// Field: [4:0] START_SRC +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TDC_PRE Internal. Only to be used through TI provided API. +// DTB15 Internal. Only to be used through TI provided API. +// DTB14 Internal. Only to be used through TI provided API. +// DTB13 Internal. Only to be used through TI provided API. +// DTB12 Internal. Only to be used through TI provided API. +// DTB11 Internal. Only to be used through TI provided API. +// DTB10 Internal. Only to be used through TI provided API. +// DTB9 Internal. Only to be used through TI provided API. +// DTB8 Internal. Only to be used through TI provided API. +// DTB7 Internal. Only to be used through TI provided API. +// DTB6 Internal. Only to be used through TI provided API. +// DTB5 Internal. Only to be used through TI provided API. +// DTB4 Internal. Only to be used through TI provided API. +// DTB3 Internal. Only to be used through TI provided API. +// DTB2 Internal. Only to be used through TI provided API. +// DTB1 Internal. Only to be used through TI provided API. +// DTB0 Internal. Only to be used through TI provided API. +// GPI Internal. Only to be used through TI provided API. +// LFCLK_DLY Internal. Only to be used through TI provided API. +// LFXT Internal. Only to be used through TI provided API. +// LFOSC Internal. Only to be used through TI provided API. +// LFTICK Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGSRC_START_SRC_W 5U +#define CKMD_TDCTRIGSRC_START_SRC_M 0x0000001FU +#define CKMD_TDCTRIGSRC_START_SRC_S 0U +#define CKMD_TDCTRIGSRC_START_SRC_TDC_PRE 0x0000001FU +#define CKMD_TDCTRIGSRC_START_SRC_DTB15 0x00000014U +#define CKMD_TDCTRIGSRC_START_SRC_DTB14 0x00000013U +#define CKMD_TDCTRIGSRC_START_SRC_DTB13 0x00000012U +#define CKMD_TDCTRIGSRC_START_SRC_DTB12 0x00000011U +#define CKMD_TDCTRIGSRC_START_SRC_DTB11 0x00000010U +#define CKMD_TDCTRIGSRC_START_SRC_DTB10 0x0000000FU +#define CKMD_TDCTRIGSRC_START_SRC_DTB9 0x0000000EU +#define CKMD_TDCTRIGSRC_START_SRC_DTB8 0x0000000DU +#define CKMD_TDCTRIGSRC_START_SRC_DTB7 0x0000000CU +#define CKMD_TDCTRIGSRC_START_SRC_DTB6 0x0000000BU +#define CKMD_TDCTRIGSRC_START_SRC_DTB5 0x0000000AU +#define CKMD_TDCTRIGSRC_START_SRC_DTB4 0x00000009U +#define CKMD_TDCTRIGSRC_START_SRC_DTB3 0x00000008U +#define CKMD_TDCTRIGSRC_START_SRC_DTB2 0x00000007U +#define CKMD_TDCTRIGSRC_START_SRC_DTB1 0x00000006U +#define CKMD_TDCTRIGSRC_START_SRC_DTB0 0x00000005U +#define CKMD_TDCTRIGSRC_START_SRC_GPI 0x00000004U +#define CKMD_TDCTRIGSRC_START_SRC_LFCLK_DLY 0x00000003U +#define CKMD_TDCTRIGSRC_START_SRC_LFXT 0x00000002U +#define CKMD_TDCTRIGSRC_START_SRC_LFOSC 0x00000001U +#define CKMD_TDCTRIGSRC_START_SRC_LFTICK 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCTRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGCNT_CNT_W 16U +#define CKMD_TDCTRIGCNT_CNT_M 0x0000FFFFU +#define CKMD_TDCTRIGCNT_CNT_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TDCTRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGCNTLOAD_CNT_W 16U +#define CKMD_TDCTRIGCNTLOAD_CNT_M 0x0000FFFFU +#define CKMD_TDCTRIGCNTLOAD_CNT_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TDCTRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCTRIGCNTCFG_EN 0x00000001U +#define CKMD_TDCTRIGCNTCFG_EN_M 0x00000001U +#define CKMD_TDCTRIGCNTCFG_EN_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_TDCPRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCPRECTL_RESET_N 0x00000080U +#define CKMD_TDCPRECTL_RESET_N_M 0x00000080U +#define CKMD_TDCPRECTL_RESET_N_S 7U + +// Field: [6] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV64 Internal. Only to be used through TI provided API. +// DIV16 Internal. Only to be used through TI provided API. +#define CKMD_TDCPRECTL_RATIO 0x00000040U +#define CKMD_TDCPRECTL_RATIO_M 0x00000040U +#define CKMD_TDCPRECTL_RATIO_S 6U +#define CKMD_TDCPRECTL_RATIO_DIV64 0x00000040U +#define CKMD_TDCPRECTL_RATIO_DIV16 0x00000000U + +// Field: [4:0] SRC +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HFXT Internal. Only to be used through TI provided API. +// HFOSC Internal. Only to be used through TI provided API. +// DTB15 Internal. Only to be used through TI provided API. +// DTB14 Internal. Only to be used through TI provided API. +// DTB13 Internal. Only to be used through TI provided API. +// DTB12 Internal. Only to be used through TI provided API. +// DTB11 Internal. Only to be used through TI provided API. +// DTB10 Internal. Only to be used through TI provided API. +// DTB9 Internal. Only to be used through TI provided API. +// DTB8 Internal. Only to be used through TI provided API. +// DTB7 Internal. Only to be used through TI provided API. +// DTB6 Internal. Only to be used through TI provided API. +// DTB5 Internal. Only to be used through TI provided API. +// DTB4 Internal. Only to be used through TI provided API. +// DTB3 Internal. Only to be used through TI provided API. +// DTB2 Internal. Only to be used through TI provided API. +// DTB1 Internal. Only to be used through TI provided API. +// DTB0 Internal. Only to be used through TI provided API. +// GPI Internal. Only to be used through TI provided API. +// LFCLK_DLY Internal. Only to be used through TI provided API. +// LFXT Internal. Only to be used through TI provided API. +// LFOSC Internal. Only to be used through TI provided API. +// LFTICK Internal. Only to be used through TI provided API. +#define CKMD_TDCPRECTL_SRC_W 5U +#define CKMD_TDCPRECTL_SRC_M 0x0000001FU +#define CKMD_TDCPRECTL_SRC_S 0U +#define CKMD_TDCPRECTL_SRC_HFXT 0x00000016U +#define CKMD_TDCPRECTL_SRC_HFOSC 0x00000015U +#define CKMD_TDCPRECTL_SRC_DTB15 0x00000014U +#define CKMD_TDCPRECTL_SRC_DTB14 0x00000013U +#define CKMD_TDCPRECTL_SRC_DTB13 0x00000012U +#define CKMD_TDCPRECTL_SRC_DTB12 0x00000011U +#define CKMD_TDCPRECTL_SRC_DTB11 0x00000010U +#define CKMD_TDCPRECTL_SRC_DTB10 0x0000000FU +#define CKMD_TDCPRECTL_SRC_DTB9 0x0000000EU +#define CKMD_TDCPRECTL_SRC_DTB8 0x0000000DU +#define CKMD_TDCPRECTL_SRC_DTB7 0x0000000CU +#define CKMD_TDCPRECTL_SRC_DTB6 0x0000000BU +#define CKMD_TDCPRECTL_SRC_DTB5 0x0000000AU +#define CKMD_TDCPRECTL_SRC_DTB4 0x00000009U +#define CKMD_TDCPRECTL_SRC_DTB3 0x00000008U +#define CKMD_TDCPRECTL_SRC_DTB2 0x00000007U +#define CKMD_TDCPRECTL_SRC_DTB1 0x00000006U +#define CKMD_TDCPRECTL_SRC_DTB0 0x00000005U +#define CKMD_TDCPRECTL_SRC_GPI 0x00000004U +#define CKMD_TDCPRECTL_SRC_LFCLK_DLY 0x00000003U +#define CKMD_TDCPRECTL_SRC_LFXT 0x00000002U +#define CKMD_TDCPRECTL_SRC_LFOSC 0x00000001U +#define CKMD_TDCPRECTL_SRC_LFTICK 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_TDCPRECNTR +// +//***************************************************************************** +// Field: [16] CAPT +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCPRECNTR_CAPT 0x00010000U +#define CKMD_TDCPRECNTR_CAPT_M 0x00010000U +#define CKMD_TDCPRECNTR_CAPT_S 16U + +// Field: [15:0] CNT +// +// Internal. Only to be used through TI provided API. +#define CKMD_TDCPRECNTR_CNT_W 16U +#define CKMD_TDCPRECNTR_CNT_M 0x0000FFFFU +#define CKMD_TDCPRECNTR_CNT_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_WDTCNT +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Counter value. +// +// A write to this field immediately starts (or restarts) the counter. It will +// count down from the written value. +// If the counter reaches 0, a reset will be generated. +// A write value of 0 immediately generates a reset. +// +// This field is only writable if not locked. See WDTLOCK register. +// Writing this field will automatically activate the lock. +// +// A read returns the current value of the counter. +#define CKMD_WDTCNT_VAL_W 32U +#define CKMD_WDTCNT_VAL_M 0xFFFFFFFFU +#define CKMD_WDTCNT_VAL_S 0U + +//***************************************************************************** +// +// Register: CKMD_O_WDTTEST +// +//***************************************************************************** +// Field: [0] STALLEN +// +// WDT stall enable +// +// This field is only writable if not locked. See WDTLOCK register. +// ENUMs: +// EN ENABLE +// +// WDT stops counting while +// the CPU is stopped by a debugger. +// DIS DISABLE +// +// WDT continues counting +// while the CPU is stopped by a debugger. +#define CKMD_WDTTEST_STALLEN 0x00000001U +#define CKMD_WDTTEST_STALLEN_M 0x00000001U +#define CKMD_WDTTEST_STALLEN_S 0U +#define CKMD_WDTTEST_STALLEN_EN 0x00000001U +#define CKMD_WDTTEST_STALLEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: CKMD_O_WDTLOCK +// +//***************************************************************************** +// Field: [31:0] STAT +// +// A write with value 0x1ACCE551 unlocks the watchdog registers for write +// access. +// A write with any other value locks the watchdog registers for write access. +// Writing the WDTCNT register will also lock the watchdog registers. +// +// A read of this field returns the state of the lock (0=unlocked, 1=locked). +#define CKMD_WDTLOCK_STAT_W 32U +#define CKMD_WDTLOCK_STAT_M 0xFFFFFFFFU +#define CKMD_WDTLOCK_STAT_S 0U + + +#endif // __CKMD__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_clkctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_clkctl.h new file mode 100644 index 00000000..463ca573 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_clkctl.h @@ -0,0 +1,823 @@ +/****************************************************************************** +* Filename: hw_clkctl_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_CLKCTL_H__ +#define __HW_CLKCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CLKCTL component +// +//***************************************************************************** +// Description Register. +#define CLKCTL_O_DESC 0x00000000U + +// Extended Description Register 0. +#define CLKCTL_O_DESCEX0 0x00000004U + +// Extended Description Register 1. +#define CLKCTL_O_DESCEX1 0x00000008U + +// Clock Configuration Register 0. +#define CLKCTL_O_CLKCFG0 0x0000000CU + +// Clock Configuration Register 1. +#define CLKCTL_O_CLKCFG1 0x00000010U + +// Clock Enable Set Register 0. +#define CLKCTL_O_CLKENSET0 0x00000014U + +// Clock Enable Set Register 1. +#define CLKCTL_O_CLKENSET1 0x00000018U + +// Clock Enable Clear Register 0. +#define CLKCTL_O_CLKENCLR0 0x00000020U + +// Clock Enable Clear Register 1. +#define CLKCTL_O_CLKENCLR1 0x00000024U + +// Internal. Only to be used through TI provided API. +#define CLKCTL_O_STBYPTR 0x0000003CU + +// IDLE Configuration Register. +#define CLKCTL_O_IDLECFG 0x00000048U + +//***************************************************************************** +// +// Register: CLKCTL_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define CLKCTL_DESC_MODID_W 16U +#define CLKCTL_DESC_MODID_M 0xFFFF0000U +#define CLKCTL_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define CLKCTL_DESC_STDIPOFF_W 4U +#define CLKCTL_DESC_STDIPOFF_M 0x0000F000U +#define CLKCTL_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define CLKCTL_DESC_INSTIDX_W 4U +#define CLKCTL_DESC_INSTIDX_M 0x00000F00U +#define CLKCTL_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP 0-15 +#define CLKCTL_DESC_MAJREV_W 4U +#define CLKCTL_DESC_MAJREV_M 0x000000F0U +#define CLKCTL_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP 0-15. +#define CLKCTL_DESC_MINREV_W 4U +#define CLKCTL_DESC_MINREV_M 0x0000000FU +#define CLKCTL_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: CLKCTL_O_DESCEX0 +// +//***************************************************************************** +// Field: [30] LGPT3 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LGPT3 0x40000000U +#define CLKCTL_DESCEX0_LGPT3_M 0x40000000U +#define CLKCTL_DESCEX0_LGPT3_S 30U +#define CLKCTL_DESCEX0_LGPT3_IP_AVAIL 0x40000000U +#define CLKCTL_DESCEX0_LGPT3_IP_UNAVAIL 0x00000000U + +// Field: [29] LGPT2 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LGPT2 0x20000000U +#define CLKCTL_DESCEX0_LGPT2_M 0x20000000U +#define CLKCTL_DESCEX0_LGPT2_S 29U +#define CLKCTL_DESCEX0_LGPT2_IP_AVAIL 0x20000000U +#define CLKCTL_DESCEX0_LGPT2_IP_UNAVAIL 0x00000000U + +// Field: [28] LGPT1 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LGPT1 0x10000000U +#define CLKCTL_DESCEX0_LGPT1_M 0x10000000U +#define CLKCTL_DESCEX0_LGPT1_S 28U +#define CLKCTL_DESCEX0_LGPT1_IP_AVAIL 0x10000000U +#define CLKCTL_DESCEX0_LGPT1_IP_UNAVAIL 0x00000000U + +// Field: [27] LGPT0 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LGPT0 0x08000000U +#define CLKCTL_DESCEX0_LGPT0_M 0x08000000U +#define CLKCTL_DESCEX0_LGPT0_S 27U +#define CLKCTL_DESCEX0_LGPT0_IP_AVAIL 0x08000000U +#define CLKCTL_DESCEX0_LGPT0_IP_UNAVAIL 0x00000000U + +// Field: [17] DMA +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_DMA 0x00020000U +#define CLKCTL_DESCEX0_DMA_M 0x00020000U +#define CLKCTL_DESCEX0_DMA_S 17U +#define CLKCTL_DESCEX0_DMA_IP_AVAIL 0x00020000U +#define CLKCTL_DESCEX0_DMA_IP_UNAVAIL 0x00000000U + +// Field: [16] LAES +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LAES 0x00010000U +#define CLKCTL_DESCEX0_LAES_M 0x00010000U +#define CLKCTL_DESCEX0_LAES_S 16U +#define CLKCTL_DESCEX0_LAES_IP_AVAIL 0x00010000U +#define CLKCTL_DESCEX0_LAES_IP_UNAVAIL 0x00000000U + +// Field: [14] ADC0 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_ADC0 0x00004000U +#define CLKCTL_DESCEX0_ADC0_M 0x00004000U +#define CLKCTL_DESCEX0_ADC0_S 14U +#define CLKCTL_DESCEX0_ADC0_IP_AVAIL 0x00004000U +#define CLKCTL_DESCEX0_ADC0_IP_UNAVAIL 0x00000000U + +// Field: [10] SPI0 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_SPI0 0x00000400U +#define CLKCTL_DESCEX0_SPI0_M 0x00000400U +#define CLKCTL_DESCEX0_SPI0_S 10U +#define CLKCTL_DESCEX0_SPI0_IP_AVAIL 0x00000400U +#define CLKCTL_DESCEX0_SPI0_IP_UNAVAIL 0x00000000U + +// Field: [6] I2C0 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_I2C0 0x00000040U +#define CLKCTL_DESCEX0_I2C0_M 0x00000040U +#define CLKCTL_DESCEX0_I2C0_S 6U +#define CLKCTL_DESCEX0_I2C0_IP_AVAIL 0x00000040U +#define CLKCTL_DESCEX0_I2C0_IP_UNAVAIL 0x00000000U + +// Field: [2] UART0 +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_UART0 0x00000004U +#define CLKCTL_DESCEX0_UART0_M 0x00000004U +#define CLKCTL_DESCEX0_UART0_S 2U +#define CLKCTL_DESCEX0_UART0_IP_AVAIL 0x00000004U +#define CLKCTL_DESCEX0_UART0_IP_UNAVAIL 0x00000000U + +// Field: [1] LRFD +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_LRFD 0x00000002U +#define CLKCTL_DESCEX0_LRFD_M 0x00000002U +#define CLKCTL_DESCEX0_LRFD_S 1U +#define CLKCTL_DESCEX0_LRFD_IP_AVAIL 0x00000002U +#define CLKCTL_DESCEX0_LRFD_IP_UNAVAIL 0x00000000U + +// Field: [0] GPIO +// +// IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define CLKCTL_DESCEX0_GPIO 0x00000001U +#define CLKCTL_DESCEX0_GPIO_M 0x00000001U +#define CLKCTL_DESCEX0_GPIO_S 0U +#define CLKCTL_DESCEX0_GPIO_IP_AVAIL 0x00000001U +#define CLKCTL_DESCEX0_GPIO_IP_UNAVAIL 0x00000000U + +//***************************************************************************** +// +// Register: CLKCTL_O_DESCEX1 +// +//***************************************************************************** +// Field: [31:30] FLASHSZ +// +// System flash availability +// ENUMs: +// SZ3 Flash size set to level 3 (Max size) +// SZ2 Flash size set to level 2 +// SZ1 Flash size set to level 1 +// SZ0 Flash size set to level 0 (Min size) +#define CLKCTL_DESCEX1_FLASHSZ_W 2U +#define CLKCTL_DESCEX1_FLASHSZ_M 0xC0000000U +#define CLKCTL_DESCEX1_FLASHSZ_S 30U +#define CLKCTL_DESCEX1_FLASHSZ_SZ3 0xC0000000U +#define CLKCTL_DESCEX1_FLASHSZ_SZ2 0x80000000U +#define CLKCTL_DESCEX1_FLASHSZ_SZ1 0x40000000U +#define CLKCTL_DESCEX1_FLASHSZ_SZ0 0x00000000U + +// Field: [29:28] SRAMSZ +// +// System SRAM availability +// ENUMs: +// SZ3 SRAM size set to level 3 (Max size) +// SZ2 SRAM size set to level 2 +// SZ1 SRAM size set to level 1 +// SZ0 SRAM size set to level 0 (Min size) +#define CLKCTL_DESCEX1_SRAMSZ_W 2U +#define CLKCTL_DESCEX1_SRAMSZ_M 0x30000000U +#define CLKCTL_DESCEX1_SRAMSZ_S 28U +#define CLKCTL_DESCEX1_SRAMSZ_SZ3 0x30000000U +#define CLKCTL_DESCEX1_SRAMSZ_SZ2 0x20000000U +#define CLKCTL_DESCEX1_SRAMSZ_SZ1 0x10000000U +#define CLKCTL_DESCEX1_SRAMSZ_SZ0 0x00000000U + +// Field: [15:8] ROPT +// +// System radio feature availability +// ENUMs: +// MAX All features available +#define CLKCTL_DESCEX1_ROPT_W 8U +#define CLKCTL_DESCEX1_ROPT_M 0x0000FF00U +#define CLKCTL_DESCEX1_ROPT_S 8U +#define CLKCTL_DESCEX1_ROPT_MAX 0x0000FF00U + +//***************************************************************************** +// +// Register: CLKCTL_O_CLKCFG0 +// +//***************************************************************************** +// Field: [30] LGPT3 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LGPT3 0x40000000U +#define CLKCTL_CLKCFG0_LGPT3_M 0x40000000U +#define CLKCTL_CLKCFG0_LGPT3_S 30U +#define CLKCTL_CLKCFG0_LGPT3_CLK_EN 0x40000000U +#define CLKCTL_CLKCFG0_LGPT3_CLK_DIS 0x00000000U + +// Field: [29] LGPT2 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LGPT2 0x20000000U +#define CLKCTL_CLKCFG0_LGPT2_M 0x20000000U +#define CLKCTL_CLKCFG0_LGPT2_S 29U +#define CLKCTL_CLKCFG0_LGPT2_CLK_EN 0x20000000U +#define CLKCTL_CLKCFG0_LGPT2_CLK_DIS 0x00000000U + +// Field: [28] LGPT1 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LGPT1 0x10000000U +#define CLKCTL_CLKCFG0_LGPT1_M 0x10000000U +#define CLKCTL_CLKCFG0_LGPT1_S 28U +#define CLKCTL_CLKCFG0_LGPT1_CLK_EN 0x10000000U +#define CLKCTL_CLKCFG0_LGPT1_CLK_DIS 0x00000000U + +// Field: [27] LGPT0 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LGPT0 0x08000000U +#define CLKCTL_CLKCFG0_LGPT0_M 0x08000000U +#define CLKCTL_CLKCFG0_LGPT0_S 27U +#define CLKCTL_CLKCFG0_LGPT0_CLK_EN 0x08000000U +#define CLKCTL_CLKCFG0_LGPT0_CLK_DIS 0x00000000U + +// Field: [17] DMA +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_DMA 0x00020000U +#define CLKCTL_CLKCFG0_DMA_M 0x00020000U +#define CLKCTL_CLKCFG0_DMA_S 17U +#define CLKCTL_CLKCFG0_DMA_CLK_EN 0x00020000U +#define CLKCTL_CLKCFG0_DMA_CLK_DIS 0x00000000U + +// Field: [16] LAES +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LAES 0x00010000U +#define CLKCTL_CLKCFG0_LAES_M 0x00010000U +#define CLKCTL_CLKCFG0_LAES_S 16U +#define CLKCTL_CLKCFG0_LAES_CLK_EN 0x00010000U +#define CLKCTL_CLKCFG0_LAES_CLK_DIS 0x00000000U + +// Field: [14] ADC0 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_ADC0 0x00004000U +#define CLKCTL_CLKCFG0_ADC0_M 0x00004000U +#define CLKCTL_CLKCFG0_ADC0_S 14U +#define CLKCTL_CLKCFG0_ADC0_CLK_EN 0x00004000U +#define CLKCTL_CLKCFG0_ADC0_CLK_DIS 0x00000000U + +// Field: [10] SPI0 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_SPI0 0x00000400U +#define CLKCTL_CLKCFG0_SPI0_M 0x00000400U +#define CLKCTL_CLKCFG0_SPI0_S 10U +#define CLKCTL_CLKCFG0_SPI0_CLK_EN 0x00000400U +#define CLKCTL_CLKCFG0_SPI0_CLK_DIS 0x00000000U + +// Field: [6] I2C0 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_I2C0 0x00000040U +#define CLKCTL_CLKCFG0_I2C0_M 0x00000040U +#define CLKCTL_CLKCFG0_I2C0_S 6U +#define CLKCTL_CLKCFG0_I2C0_CLK_EN 0x00000040U +#define CLKCTL_CLKCFG0_I2C0_CLK_DIS 0x00000000U + +// Field: [2] UART0 +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_UART0 0x00000004U +#define CLKCTL_CLKCFG0_UART0_M 0x00000004U +#define CLKCTL_CLKCFG0_UART0_S 2U +#define CLKCTL_CLKCFG0_UART0_CLK_EN 0x00000004U +#define CLKCTL_CLKCFG0_UART0_CLK_DIS 0x00000000U + +// Field: [1] LRFD +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_LRFD 0x00000002U +#define CLKCTL_CLKCFG0_LRFD_M 0x00000002U +#define CLKCTL_CLKCFG0_LRFD_S 1U +#define CLKCTL_CLKCFG0_LRFD_CLK_EN 0x00000002U +#define CLKCTL_CLKCFG0_LRFD_CLK_DIS 0x00000000U + +// Field: [0] GPIO +// +// IP clock configuration +// ENUMs: +// CLK_EN Clock is enabled +// CLK_DIS Clock is disabled +#define CLKCTL_CLKCFG0_GPIO 0x00000001U +#define CLKCTL_CLKCFG0_GPIO_M 0x00000001U +#define CLKCTL_CLKCFG0_GPIO_S 0U +#define CLKCTL_CLKCFG0_GPIO_CLK_EN 0x00000001U +#define CLKCTL_CLKCFG0_GPIO_CLK_DIS 0x00000000U + +//***************************************************************************** +// +// Register: CLKCTL_O_CLKCFG1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CLKCTL_O_CLKENSET0 +// +//***************************************************************************** +// Field: [30] LGPT3 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LGPT3 0x40000000U +#define CLKCTL_CLKENSET0_LGPT3_M 0x40000000U +#define CLKCTL_CLKENSET0_LGPT3_S 30U +#define CLKCTL_CLKENSET0_LGPT3_CLK_SET 0x40000000U +#define CLKCTL_CLKENSET0_LGPT3_CLK_UNCHGD 0x00000000U + +// Field: [29] LGPT2 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LGPT2 0x20000000U +#define CLKCTL_CLKENSET0_LGPT2_M 0x20000000U +#define CLKCTL_CLKENSET0_LGPT2_S 29U +#define CLKCTL_CLKENSET0_LGPT2_CLK_SET 0x20000000U +#define CLKCTL_CLKENSET0_LGPT2_CLK_UNCHGD 0x00000000U + +// Field: [28] LGPT1 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LGPT1 0x10000000U +#define CLKCTL_CLKENSET0_LGPT1_M 0x10000000U +#define CLKCTL_CLKENSET0_LGPT1_S 28U +#define CLKCTL_CLKENSET0_LGPT1_CLK_SET 0x10000000U +#define CLKCTL_CLKENSET0_LGPT1_CLK_UNCHGD 0x00000000U + +// Field: [27] LGPT0 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LGPT0 0x08000000U +#define CLKCTL_CLKENSET0_LGPT0_M 0x08000000U +#define CLKCTL_CLKENSET0_LGPT0_S 27U +#define CLKCTL_CLKENSET0_LGPT0_CLK_SET 0x08000000U +#define CLKCTL_CLKENSET0_LGPT0_CLK_UNCHGD 0x00000000U + +// Field: [17] DMA +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_DMA 0x00020000U +#define CLKCTL_CLKENSET0_DMA_M 0x00020000U +#define CLKCTL_CLKENSET0_DMA_S 17U +#define CLKCTL_CLKENSET0_DMA_CLK_SET 0x00020000U +#define CLKCTL_CLKENSET0_DMA_CLK_UNCHGD 0x00000000U + +// Field: [16] LAES +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LAES 0x00010000U +#define CLKCTL_CLKENSET0_LAES_M 0x00010000U +#define CLKCTL_CLKENSET0_LAES_S 16U +#define CLKCTL_CLKENSET0_LAES_CLK_SET 0x00010000U +#define CLKCTL_CLKENSET0_LAES_CLK_UNCHGD 0x00000000U + +// Field: [14] ADC0 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_ADC0 0x00004000U +#define CLKCTL_CLKENSET0_ADC0_M 0x00004000U +#define CLKCTL_CLKENSET0_ADC0_S 14U +#define CLKCTL_CLKENSET0_ADC0_CLK_SET 0x00004000U +#define CLKCTL_CLKENSET0_ADC0_CLK_UNCHGD 0x00000000U + +// Field: [10] SPI0 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_SPI0 0x00000400U +#define CLKCTL_CLKENSET0_SPI0_M 0x00000400U +#define CLKCTL_CLKENSET0_SPI0_S 10U +#define CLKCTL_CLKENSET0_SPI0_CLK_SET 0x00000400U +#define CLKCTL_CLKENSET0_SPI0_CLK_UNCHGD 0x00000000U + +// Field: [6] I2C0 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_I2C0 0x00000040U +#define CLKCTL_CLKENSET0_I2C0_M 0x00000040U +#define CLKCTL_CLKENSET0_I2C0_S 6U +#define CLKCTL_CLKENSET0_I2C0_CLK_SET 0x00000040U +#define CLKCTL_CLKENSET0_I2C0_CLK_UNCHGD 0x00000000U + +// Field: [2] UART0 +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_UART0 0x00000004U +#define CLKCTL_CLKENSET0_UART0_M 0x00000004U +#define CLKCTL_CLKENSET0_UART0_S 2U +#define CLKCTL_CLKENSET0_UART0_CLK_SET 0x00000004U +#define CLKCTL_CLKENSET0_UART0_CLK_UNCHGD 0x00000000U + +// Field: [1] LRFD +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_LRFD 0x00000002U +#define CLKCTL_CLKENSET0_LRFD_M 0x00000002U +#define CLKCTL_CLKENSET0_LRFD_S 1U +#define CLKCTL_CLKENSET0_LRFD_CLK_SET 0x00000002U +#define CLKCTL_CLKENSET0_LRFD_CLK_UNCHGD 0x00000000U + +// Field: [0] GPIO +// +// Configure IP clock enable +// ENUMs: +// CLK_SET Set IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENSET0_GPIO 0x00000001U +#define CLKCTL_CLKENSET0_GPIO_M 0x00000001U +#define CLKCTL_CLKENSET0_GPIO_S 0U +#define CLKCTL_CLKENSET0_GPIO_CLK_SET 0x00000001U +#define CLKCTL_CLKENSET0_GPIO_CLK_UNCHGD 0x00000000U + +//***************************************************************************** +// +// Register: CLKCTL_O_CLKENSET1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CLKCTL_O_CLKENCLR0 +// +//***************************************************************************** +// Field: [30] LGPT3 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LGPT3 0x40000000U +#define CLKCTL_CLKENCLR0_LGPT3_M 0x40000000U +#define CLKCTL_CLKENCLR0_LGPT3_S 30U +#define CLKCTL_CLKENCLR0_LGPT3_CLK_CLR 0x40000000U +#define CLKCTL_CLKENCLR0_LGPT3_CLK_UNCHGD 0x00000000U + +// Field: [29] LGPT2 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LGPT2 0x20000000U +#define CLKCTL_CLKENCLR0_LGPT2_M 0x20000000U +#define CLKCTL_CLKENCLR0_LGPT2_S 29U +#define CLKCTL_CLKENCLR0_LGPT2_CLK_CLR 0x20000000U +#define CLKCTL_CLKENCLR0_LGPT2_CLK_UNCHGD 0x00000000U + +// Field: [28] LGPT1 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LGPT1 0x10000000U +#define CLKCTL_CLKENCLR0_LGPT1_M 0x10000000U +#define CLKCTL_CLKENCLR0_LGPT1_S 28U +#define CLKCTL_CLKENCLR0_LGPT1_CLK_CLR 0x10000000U +#define CLKCTL_CLKENCLR0_LGPT1_CLK_UNCHGD 0x00000000U + +// Field: [27] LGPT0 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LGPT0 0x08000000U +#define CLKCTL_CLKENCLR0_LGPT0_M 0x08000000U +#define CLKCTL_CLKENCLR0_LGPT0_S 27U +#define CLKCTL_CLKENCLR0_LGPT0_CLK_CLR 0x08000000U +#define CLKCTL_CLKENCLR0_LGPT0_CLK_UNCHGD 0x00000000U + +// Field: [17] DMA +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_DMA 0x00020000U +#define CLKCTL_CLKENCLR0_DMA_M 0x00020000U +#define CLKCTL_CLKENCLR0_DMA_S 17U +#define CLKCTL_CLKENCLR0_DMA_CLK_CLR 0x00020000U +#define CLKCTL_CLKENCLR0_DMA_CLK_UNCHGD 0x00000000U + +// Field: [16] LAES +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LAES 0x00010000U +#define CLKCTL_CLKENCLR0_LAES_M 0x00010000U +#define CLKCTL_CLKENCLR0_LAES_S 16U +#define CLKCTL_CLKENCLR0_LAES_CLK_CLR 0x00010000U +#define CLKCTL_CLKENCLR0_LAES_CLK_UNCHGD 0x00000000U + +// Field: [14] ADC0 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_ADC0 0x00004000U +#define CLKCTL_CLKENCLR0_ADC0_M 0x00004000U +#define CLKCTL_CLKENCLR0_ADC0_S 14U +#define CLKCTL_CLKENCLR0_ADC0_CLK_CLR 0x00004000U +#define CLKCTL_CLKENCLR0_ADC0_CLK_UNCHGD 0x00000000U + +// Field: [10] SPI0 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_SPI0 0x00000400U +#define CLKCTL_CLKENCLR0_SPI0_M 0x00000400U +#define CLKCTL_CLKENCLR0_SPI0_S 10U +#define CLKCTL_CLKENCLR0_SPI0_CLK_CLR 0x00000400U +#define CLKCTL_CLKENCLR0_SPI0_CLK_UNCHGD 0x00000000U + +// Field: [6] I2C0 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_I2C0 0x00000040U +#define CLKCTL_CLKENCLR0_I2C0_M 0x00000040U +#define CLKCTL_CLKENCLR0_I2C0_S 6U +#define CLKCTL_CLKENCLR0_I2C0_CLK_CLR 0x00000040U +#define CLKCTL_CLKENCLR0_I2C0_CLK_UNCHGD 0x00000000U + +// Field: [2] UART0 +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_UART0 0x00000004U +#define CLKCTL_CLKENCLR0_UART0_M 0x00000004U +#define CLKCTL_CLKENCLR0_UART0_S 2U +#define CLKCTL_CLKENCLR0_UART0_CLK_CLR 0x00000004U +#define CLKCTL_CLKENCLR0_UART0_CLK_UNCHGD 0x00000000U + +// Field: [1] LRFD +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_LRFD 0x00000002U +#define CLKCTL_CLKENCLR0_LRFD_M 0x00000002U +#define CLKCTL_CLKENCLR0_LRFD_S 1U +#define CLKCTL_CLKENCLR0_LRFD_CLK_CLR 0x00000002U +#define CLKCTL_CLKENCLR0_LRFD_CLK_UNCHGD 0x00000000U + +// Field: [0] GPIO +// +// Configure IP clock enable +// ENUMs: +// CLK_CLR Clear IP clock enable +// CLK_UNCHGD IP clock enable is unchanged +#define CLKCTL_CLKENCLR0_GPIO 0x00000001U +#define CLKCTL_CLKENCLR0_GPIO_M 0x00000001U +#define CLKCTL_CLKENCLR0_GPIO_S 0U +#define CLKCTL_CLKENCLR0_GPIO_CLK_CLR 0x00000001U +#define CLKCTL_CLKENCLR0_GPIO_CLK_UNCHGD 0x00000000U + +//***************************************************************************** +// +// Register: CLKCTL_O_CLKENCLR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CLKCTL_O_STBYPTR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN Internal. Only to be used through TI provided API. +#define CLKCTL_STBYPTR_VAL_W 32U +#define CLKCTL_STBYPTR_VAL_M 0xFFFFFFFFU +#define CLKCTL_STBYPTR_VAL_S 0U +#define CLKCTL_STBYPTR_VAL_MIN 0x00000000U + +//***************************************************************************** +// +// Register: CLKCTL_O_IDLECFG +// +//***************************************************************************** +// Field: [0] MODE +// +// Flash LDO configuration in SLEEP/IDLE mode. +// ENUMs: +// LDO_OFF Flash LDO is off in SLEEP/IDLE mode. +// Decreases power +// consumption in SLEEP/IDLE mode, but gives +// longer wake up time. +// +// Note: NVM clock is turned +// off independent of DMA status. Therefore SW +// must ensure that DMA never access NVM in this +// mode. +// LDO_ON Flash LDO is on in SLEEP/IDLE mode. +// Gives fast wake up time +// from SLEEP/IDLE mode, but increased power +// consumption. +#define CLKCTL_IDLECFG_MODE 0x00000001U +#define CLKCTL_IDLECFG_MODE_M 0x00000001U +#define CLKCTL_IDLECFG_MODE_S 0U +#define CLKCTL_IDLECFG_MODE_LDO_OFF 0x00000001U +#define CLKCTL_IDLECFG_MODE_LDO_ON 0x00000000U + + +#endif // __CLKCTL__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dbgss.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dbgss.h new file mode 100644 index 00000000..a662a919 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dbgss.h @@ -0,0 +1,1082 @@ +/****************************************************************************** +* Filename: hw_dbgss_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_DBGSS_H__ +#define __HW_DBGSS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DBGSS component +// +//***************************************************************************** +// Module Description +#define DBGSS_O_DESC 0x00000000U + +// Interrupt mask +#define DBGSS_O_IMASK 0x00000044U + +// Raw interrupt status +#define DBGSS_O_RIS 0x0000004CU + +// Masked interrupt status +#define DBGSS_O_MIS 0x00000054U + +// Interrupt set +#define DBGSS_O_ISET 0x0000005CU + +// Interrupt clear +#define DBGSS_O_ICLR 0x00000064U + +// Set Interupt Mask in IMASK +#define DBGSS_O_IMSET 0x0000006CU + +// Clear Interupt Mask in IMASK +#define DBGSS_O_IMCLR 0x00000074U + +// Transmit data register +#define DBGSS_O_TXD 0x00000100U + +// Transmit control register +#define DBGSS_O_TXCTL 0x00000104U + +// Receive data register +#define DBGSS_O_RXD 0x00000108U + +// Receive control register +#define DBGSS_O_RXCTL 0x0000010CU + +// Transmit Data Peek Register +#define DBGSS_O_TXDPEEK 0x00000110U + +// Receive Data Peek Register +#define DBGSS_O_RXDPEEK 0x00000114U + +// Special enable authorization register +#define DBGSS_O_SPECIAL_AUTH 0x00000200U + +// Special enable authorization set register +#define DBGSS_O_SPECIAL_AUTH_SET 0x00000204U + +// Special enable authorization clear register +#define DBGSS_O_SPECIAL_AUTH_CLR 0x00000208U + +// Application authorization register +#define DBGSS_O_APP_AUTH 0x00000210U + +// Application authorization set register +#define DBGSS_O_APP_AUTH_SET 0x00000214U + +// Application authorization clear register +#define DBGSS_O_APP_AUTH_CLR 0x00000218U + +// Debug control register +#define DBGSS_O_DBGCTL 0x0000021CU + +//***************************************************************************** +// +// Register: DBGSS_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODULEID +// +// Module identifier used to uniquely identify this IP. +// ENUMs: +// MAX Maximum possible value +// MIN Minimum value +#define DBGSS_DESC_MODULEID_W 16U +#define DBGSS_DESC_MODULEID_M 0xFFFF0000U +#define DBGSS_DESC_MODULEID_S 16U +#define DBGSS_DESC_MODULEID_MAX 0xFFFF0000U +#define DBGSS_DESC_MODULEID_MIN 0x00000000U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +// +// 0: STDIP MMRs do not exist +// 0x1-0xF: These MMRs begin at offset 64*STDIPOFF from IP base address +// ENUMs: +// MAX Maximum possible value +// MIN Minimum Value +#define DBGSS_DESC_STDIPOFF_W 4U +#define DBGSS_DESC_STDIPOFF_M 0x0000F000U +#define DBGSS_DESC_STDIPOFF_S 12U +#define DBGSS_DESC_STDIPOFF_MAX 0x0000F000U +#define DBGSS_DESC_STDIPOFF_MIN 0x00000000U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +// ENUMs: +// MAX Maximum possible value +// MIN Minimum Value +#define DBGSS_DESC_INSTIDX_W 4U +#define DBGSS_DESC_INSTIDX_M 0x00000F00U +#define DBGSS_DESC_INSTIDX_S 8U +#define DBGSS_DESC_INSTIDX_MAX 0x00000F00U +#define DBGSS_DESC_INSTIDX_MIN 0x00000000U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +// ENUMs: +// MAX Maximum possible value +// MIN Minimum Value +#define DBGSS_DESC_MAJREV_W 4U +#define DBGSS_DESC_MAJREV_M 0x000000F0U +#define DBGSS_DESC_MAJREV_S 4U +#define DBGSS_DESC_MAJREV_MAX 0x000000F0U +#define DBGSS_DESC_MAJREV_MIN 0x00000000U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +// ENUMs: +// MAX Maximum possible value +// MIN Minimum Value +#define DBGSS_DESC_MINREV_W 4U +#define DBGSS_DESC_MINREV_M 0x0000000FU +#define DBGSS_DESC_MINREV_S 0U +#define DBGSS_DESC_MINREV_MAX 0x0000000FU +#define DBGSS_DESC_MINREV_MIN 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_IMASK +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// PWRDWNIFG interrupt mask +// ENUMs: +// SET Interrupt will request an interrupt service +// routine and corresponding bit in MIS will be +// set +// CLR Interrupt is masked out +#define DBGSS_IMASK_PWRDWNIFG 0x00000008U +#define DBGSS_IMASK_PWRDWNIFG_M 0x00000008U +#define DBGSS_IMASK_PWRDWNIFG_S 3U +#define DBGSS_IMASK_PWRDWNIFG_SET 0x00000008U +#define DBGSS_IMASK_PWRDWNIFG_CLR 0x00000000U + +// Field: [2] PWRUPIFG +// +// PWRUPIFG interrupt mask +// ENUMs: +// SET Interrupt will request an interrupt service +// routine and corresponding bit in MIS will be +// set +// CLR Interrupt is masked out +#define DBGSS_IMASK_PWRUPIFG 0x00000004U +#define DBGSS_IMASK_PWRUPIFG_M 0x00000004U +#define DBGSS_IMASK_PWRUPIFG_S 2U +#define DBGSS_IMASK_PWRUPIFG_SET 0x00000004U +#define DBGSS_IMASK_PWRUPIFG_CLR 0x00000000U + +// Field: [1] RXIFG +// +// RXIFG interrupt mask +// ENUMs: +// SET Interrupt will request an interrupt service +// routine and corresponding bit in MIS will be +// set +// CLR Interrupt is masked out +#define DBGSS_IMASK_RXIFG 0x00000002U +#define DBGSS_IMASK_RXIFG_M 0x00000002U +#define DBGSS_IMASK_RXIFG_S 1U +#define DBGSS_IMASK_RXIFG_SET 0x00000002U +#define DBGSS_IMASK_RXIFG_CLR 0x00000000U + +// Field: [0] TXIFG +// +// TXIFG interrupt mask +// ENUMs: +// EN Enable Interrupt Mask +// DIS Disable Interrupt Mask +#define DBGSS_IMASK_TXIFG 0x00000001U +#define DBGSS_IMASK_TXIFG_M 0x00000001U +#define DBGSS_IMASK_TXIFG_S 0U +#define DBGSS_IMASK_TXIFG_EN 0x00000001U +#define DBGSS_IMASK_TXIFG_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_RIS +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Raw interrupt status for PWRDWNIFG +// ENUMs: +// SET PWRDWNIFG occurred +// CLR PWRDWNIFG did not occur +#define DBGSS_RIS_PWRDWNIFG 0x00000008U +#define DBGSS_RIS_PWRDWNIFG_M 0x00000008U +#define DBGSS_RIS_PWRDWNIFG_S 3U +#define DBGSS_RIS_PWRDWNIFG_SET 0x00000008U +#define DBGSS_RIS_PWRDWNIFG_CLR 0x00000000U + +// Field: [2] PWRUPIFG +// +// Raw interrupt status for PWRUPIFG +// ENUMs: +// SET PWRUPIFG occurred +// CLR PWRUPIFG did not occur +#define DBGSS_RIS_PWRUPIFG 0x00000004U +#define DBGSS_RIS_PWRUPIFG_M 0x00000004U +#define DBGSS_RIS_PWRUPIFG_S 2U +#define DBGSS_RIS_PWRUPIFG_SET 0x00000004U +#define DBGSS_RIS_PWRUPIFG_CLR 0x00000000U + +// Field: [1] RXIFG +// +// Raw interrupt status for RXIFG +// ENUMs: +// SET RXIFG occurred +// CLR RXIFG did not occur +#define DBGSS_RIS_RXIFG 0x00000002U +#define DBGSS_RIS_RXIFG_M 0x00000002U +#define DBGSS_RIS_RXIFG_S 1U +#define DBGSS_RIS_RXIFG_SET 0x00000002U +#define DBGSS_RIS_RXIFG_CLR 0x00000000U + +// Field: [0] TXIFG +// +// Raw interrupt status for TXIFG +// ENUMs: +// SET TXIFG occurred +// CLR TXIFG did not occur +#define DBGSS_RIS_TXIFG 0x00000001U +#define DBGSS_RIS_TXIFG_M 0x00000001U +#define DBGSS_RIS_TXIFG_S 0U +#define DBGSS_RIS_TXIFG_SET 0x00000001U +#define DBGSS_RIS_TXIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_MIS +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Masked interrupt status for PWRDWNIFG +// ENUMs: +// SET PWRDWNIFG requests an interrupt service routine +// CLR PWRDWNIFG did not request an interrupt service +// routine +#define DBGSS_MIS_PWRDWNIFG 0x00000008U +#define DBGSS_MIS_PWRDWNIFG_M 0x00000008U +#define DBGSS_MIS_PWRDWNIFG_S 3U +#define DBGSS_MIS_PWRDWNIFG_SET 0x00000008U +#define DBGSS_MIS_PWRDWNIFG_CLR 0x00000000U + +// Field: [2] PWRUPIFG +// +// Masked interrupt status for PWRUPIFG +// ENUMs: +// SET PWRUPIFG requests an interrupt service routine +// CLR PWRUPIFG did not request an interrupt service +// routine +#define DBGSS_MIS_PWRUPIFG 0x00000004U +#define DBGSS_MIS_PWRUPIFG_M 0x00000004U +#define DBGSS_MIS_PWRUPIFG_S 2U +#define DBGSS_MIS_PWRUPIFG_SET 0x00000004U +#define DBGSS_MIS_PWRUPIFG_CLR 0x00000000U + +// Field: [1] RXIFG +// +// Masked interrupt status for RXIFG +// ENUMs: +// SET RXIFG requests an interrupt service routine +// CLR RXIFG did not request an interrupt service routine +#define DBGSS_MIS_RXIFG 0x00000002U +#define DBGSS_MIS_RXIFG_M 0x00000002U +#define DBGSS_MIS_RXIFG_S 1U +#define DBGSS_MIS_RXIFG_SET 0x00000002U +#define DBGSS_MIS_RXIFG_CLR 0x00000000U + +// Field: [0] TXIFG +// +// Masked interrupt status for TXIFG +// ENUMs: +// SET TXIFG requests an interrupt service routine +// CLR TXIFG did not request an interrupt service routine +#define DBGSS_MIS_TXIFG 0x00000001U +#define DBGSS_MIS_TXIFG_M 0x00000001U +#define DBGSS_MIS_TXIFG_S 0U +#define DBGSS_MIS_TXIFG_SET 0x00000001U +#define DBGSS_MIS_TXIFG_CLR 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_ISET +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Sets PWRDWNIFG in RIS register +// ENUMs: +// SET Set interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ISET_PWRDWNIFG 0x00000008U +#define DBGSS_ISET_PWRDWNIFG_M 0x00000008U +#define DBGSS_ISET_PWRDWNIFG_S 3U +#define DBGSS_ISET_PWRDWNIFG_SET 0x00000008U +#define DBGSS_ISET_PWRDWNIFG_NOEFF 0x00000000U + +// Field: [2] PWRUPIFG +// +// Sets PWRUPIFG in RIS register +// ENUMs: +// SET Set interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ISET_PWRUPIFG 0x00000004U +#define DBGSS_ISET_PWRUPIFG_M 0x00000004U +#define DBGSS_ISET_PWRUPIFG_S 2U +#define DBGSS_ISET_PWRUPIFG_SET 0x00000004U +#define DBGSS_ISET_PWRUPIFG_NOEFF 0x00000000U + +// Field: [1] RXIFG +// +// Sets RXIFG in RIS register +// ENUMs: +// SET Set interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ISET_RXIFG 0x00000002U +#define DBGSS_ISET_RXIFG_M 0x00000002U +#define DBGSS_ISET_RXIFG_S 1U +#define DBGSS_ISET_RXIFG_SET 0x00000002U +#define DBGSS_ISET_RXIFG_NOEFF 0x00000000U + +// Field: [0] TXIFG +// +// Sets TXIFG in RIS register +// ENUMs: +// SET Set interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ISET_TXIFG 0x00000001U +#define DBGSS_ISET_TXIFG_M 0x00000001U +#define DBGSS_ISET_TXIFG_S 0U +#define DBGSS_ISET_TXIFG_SET 0x00000001U +#define DBGSS_ISET_TXIFG_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_ICLR +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Clears PWRDWNIFG interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ICLR_PWRDWNIFG 0x00000008U +#define DBGSS_ICLR_PWRDWNIFG_M 0x00000008U +#define DBGSS_ICLR_PWRDWNIFG_S 3U +#define DBGSS_ICLR_PWRDWNIFG_CLR 0x00000008U +#define DBGSS_ICLR_PWRDWNIFG_NOEFF 0x00000000U + +// Field: [2] PWRUPIFG +// +// Clears PWRUPIFG interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ICLR_PWRUPIFG 0x00000004U +#define DBGSS_ICLR_PWRUPIFG_M 0x00000004U +#define DBGSS_ICLR_PWRUPIFG_S 2U +#define DBGSS_ICLR_PWRUPIFG_CLR 0x00000004U +#define DBGSS_ICLR_PWRUPIFG_NOEFF 0x00000000U + +// Field: [1] RXIFG +// +// Clears RXIFG interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ICLR_RXIFG 0x00000002U +#define DBGSS_ICLR_RXIFG_M 0x00000002U +#define DBGSS_ICLR_RXIFG_S 1U +#define DBGSS_ICLR_RXIFG_CLR 0x00000002U +#define DBGSS_ICLR_RXIFG_NOEFF 0x00000000U + +// Field: [0] TXIFG +// +// Clears TXIFG interrupt +// ENUMs: +// CLR Clear interrupt +// NOEFF Writing a 0 has no effect +#define DBGSS_ICLR_TXIFG 0x00000001U +#define DBGSS_ICLR_TXIFG_M 0x00000001U +#define DBGSS_ICLR_TXIFG_S 0U +#define DBGSS_ICLR_TXIFG_CLR 0x00000001U +#define DBGSS_ICLR_TXIFG_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_IMSET +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Set PWRDWNIFG interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing a 0 has no effect +#define DBGSS_IMSET_PWRDWNIFG 0x00000008U +#define DBGSS_IMSET_PWRDWNIFG_M 0x00000008U +#define DBGSS_IMSET_PWRDWNIFG_S 3U +#define DBGSS_IMSET_PWRDWNIFG_SET 0x00000008U +#define DBGSS_IMSET_PWRDWNIFG_NOEFF 0x00000000U + +// Field: [2] PWRUPIFG +// +// Set PWRUPIFG interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing a 0 has no effect +#define DBGSS_IMSET_PWRUPIFG 0x00000004U +#define DBGSS_IMSET_PWRUPIFG_M 0x00000004U +#define DBGSS_IMSET_PWRUPIFG_S 2U +#define DBGSS_IMSET_PWRUPIFG_SET 0x00000004U +#define DBGSS_IMSET_PWRUPIFG_NOEFF 0x00000000U + +// Field: [1] RXIFG +// +// Set RXIFG interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing a 0 has no effect +#define DBGSS_IMSET_RXIFG 0x00000002U +#define DBGSS_IMSET_RXIFG_M 0x00000002U +#define DBGSS_IMSET_RXIFG_S 1U +#define DBGSS_IMSET_RXIFG_SET 0x00000002U +#define DBGSS_IMSET_RXIFG_NOEFF 0x00000000U + +// Field: [0] TXIFG +// +// Set TXIFG interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing a 0 has no effect +#define DBGSS_IMSET_TXIFG 0x00000001U +#define DBGSS_IMSET_TXIFG_M 0x00000001U +#define DBGSS_IMSET_TXIFG_S 0U +#define DBGSS_IMSET_TXIFG_SET 0x00000001U +#define DBGSS_IMSET_TXIFG_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_IMCLR +// +//***************************************************************************** +// Field: [3] PWRDWNIFG +// +// Clears PWRDWNIFG interrupt mask +// ENUMs: +// CLR IMASK bit corresponding to PWRDWNIFG is cleared +// NO_EFFECT Writing a 0 has no effect +#define DBGSS_IMCLR_PWRDWNIFG 0x00000008U +#define DBGSS_IMCLR_PWRDWNIFG_M 0x00000008U +#define DBGSS_IMCLR_PWRDWNIFG_S 3U +#define DBGSS_IMCLR_PWRDWNIFG_CLR 0x00000008U +#define DBGSS_IMCLR_PWRDWNIFG_NO_EFFECT 0x00000000U + +// Field: [2] PWRUPIFG +// +// Clears PWRUPIFG interrupt mask +// ENUMs: +// CLR IMASK bit corresponding to PWRUPIFG is cleared +// NO_EFFECT Writing a 0 has no effect +#define DBGSS_IMCLR_PWRUPIFG 0x00000004U +#define DBGSS_IMCLR_PWRUPIFG_M 0x00000004U +#define DBGSS_IMCLR_PWRUPIFG_S 2U +#define DBGSS_IMCLR_PWRUPIFG_CLR 0x00000004U +#define DBGSS_IMCLR_PWRUPIFG_NO_EFFECT 0x00000000U + +// Field: [1] RXIFG +// +// Clears RXIFG interrupt mask +// ENUMs: +// CLR IMASK bit corresponding to RXIFG is cleared +// NO_EFFECT Writing a 0 has no effect +#define DBGSS_IMCLR_RXIFG 0x00000002U +#define DBGSS_IMCLR_RXIFG_M 0x00000002U +#define DBGSS_IMCLR_RXIFG_S 1U +#define DBGSS_IMCLR_RXIFG_CLR 0x00000002U +#define DBGSS_IMCLR_RXIFG_NO_EFFECT 0x00000000U + +// Field: [0] TXIFG +// +// Clears TXIFG interrupt mask +// ENUMs: +// CLR IMASK bit corresponding to TXIFG is cleared +// NO_EFFECT Writing a 0 has no effect +#define DBGSS_IMCLR_TXIFG 0x00000001U +#define DBGSS_IMCLR_TXIFG_M 0x00000001U +#define DBGSS_IMCLR_TXIFG_S 0U +#define DBGSS_IMCLR_TXIFG_CLR 0x00000001U +#define DBGSS_IMCLR_TXIFG_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_TXD +// +//***************************************************************************** +// Field: [31:0] VAL +// +// SACI command/parameter word. Valid value when TXCTL.TXDSTA=1. TXCTL.TXDSTA +// gets automatically cleared upon read. +#define DBGSS_TXD_VAL_W 32U +#define DBGSS_TXD_VAL_M 0xFFFFFFFFU +#define DBGSS_TXD_VAL_S 0U + +//***************************************************************************** +// +// Register: DBGSS_O_TXCTL +// +//***************************************************************************** +// Field: [7:1] FLAGS +// +// Software defined flags that are used by the SACI protocol (host to device). +#define DBGSS_TXCTL_FLAGS_W 7U +#define DBGSS_TXCTL_FLAGS_M 0x000000FEU +#define DBGSS_TXCTL_FLAGS_S 1U + +// Field: [0] TXDSTA +// +// Indicates whether the host has written a word to the TXD register, which can +// be read by the device: +// TXDSTA is automatically set upon write to TXD register in SECAP and +// automatically gets cleared upon read from TXD +// ENUMs: +// FULL The TXD register contains a new SACI parameter +// word from the host, which can be read by the +// device. +// EMPTY The TXD register does not contain a new SACI +// parameter word from the host, and should not be +// read by the device. +#define DBGSS_TXCTL_TXDSTA 0x00000001U +#define DBGSS_TXCTL_TXDSTA_M 0x00000001U +#define DBGSS_TXCTL_TXDSTA_S 0U +#define DBGSS_TXCTL_TXDSTA_FULL 0x00000001U +#define DBGSS_TXCTL_TXDSTA_EMPTY 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_RXD +// +//***************************************************************************** +// Field: [31:0] VAL +// +// SACI command response word. RXCTL.RXDSTA automatically set upon write. +// RXCTL.RXDSTA automatically cleared upon read (flush operation). +#define DBGSS_RXD_VAL_W 32U +#define DBGSS_RXD_VAL_M 0xFFFFFFFFU +#define DBGSS_RXD_VAL_S 0U + +//***************************************************************************** +// +// Register: DBGSS_O_RXCTL +// +//***************************************************************************** +// Field: [7:1] FLAGS +// +// Software defined flags that are used by the SACI protocol (device to host). +#define DBGSS_RXCTL_FLAGS_W 7U +#define DBGSS_RXCTL_FLAGS_M 0x000000FEU +#define DBGSS_RXCTL_FLAGS_S 1U + +// Field: [0] RXDSTA +// +// Indicates whether the device has written a word to the RXD register, which +// can be read by the host: +// RXDSTA is automatically set upon write to RXD and automatically cleared upon +// read from RXD register of SECAP or RXD. +// ENUMs: +// FULL The RXD register contains a new SACI response word +// from the device, which can be read by the host. +// EMPTY The RXD register does not contain a new SACI +// response word from the device, and should not +// be read by the host. +#define DBGSS_RXCTL_RXDSTA 0x00000001U +#define DBGSS_RXCTL_RXDSTA_M 0x00000001U +#define DBGSS_RXCTL_RXDSTA_S 0U +#define DBGSS_RXCTL_RXDSTA_FULL 0x00000001U +#define DBGSS_RXCTL_RXDSTA_EMPTY 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_TXDPEEK +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Transmit Data Peek Register. SACI command parameter word. TXCTL.TXDSTA not +// affected by read of TXDPEEK +#define DBGSS_TXDPEEK_VAL_W 32U +#define DBGSS_TXDPEEK_VAL_M 0xFFFFFFFFU +#define DBGSS_TXDPEEK_VAL_S 0U + +//***************************************************************************** +// +// Register: DBGSS_O_RXDPEEK +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Receive Data Peek Register. SACI command response word. RXCTL.RXDSTA not +// affected by read of RXDPEEK +#define DBGSS_RXDPEEK_VAL_W 32U +#define DBGSS_RXDPEEK_VAL_M 0xFFFFFFFFU +#define DBGSS_RXDPEEK_VAL_S 0U + +//***************************************************************************** +// +// Register: DBGSS_O_SPECIAL_AUTH +// +//***************************************************************************** +// Field: [6] DBGDIS +// +// Indicates status of DBGDIS. +// ENUMs: +// DIS Disables debugging capability +// EN Enables debugging capability. +#define DBGSS_SPECIAL_AUTH_DBGDIS 0x00000040U +#define DBGSS_SPECIAL_AUTH_DBGDIS_M 0x00000040U +#define DBGSS_SPECIAL_AUTH_DBGDIS_S 6U +#define DBGSS_SPECIAL_AUTH_DBGDIS_DIS 0x00000040U +#define DBGSS_SPECIAL_AUTH_DBGDIS_EN 0x00000000U + +// Field: [5] AHBAPEN +// +// Indicates status of AHBAPEN +// ENUMs: +// EN Enable AHB-AP +// DIS Disable AHB-AP +#define DBGSS_SPECIAL_AUTH_AHBAPEN 0x00000020U +#define DBGSS_SPECIAL_AUTH_AHBAPEN_M 0x00000020U +#define DBGSS_SPECIAL_AUTH_AHBAPEN_S 5U +#define DBGSS_SPECIAL_AUTH_AHBAPEN_EN 0x00000020U +#define DBGSS_SPECIAL_AUTH_AHBAPEN_DIS 0x00000000U + +// Field: [4] CFGAPEN +// +// Indicates status of CFGAPEN +// ENUMs: +// EN Enable CFG-AP +// DIS Disable CFG-AP +#define DBGSS_SPECIAL_AUTH_CFGAPEN 0x00000010U +#define DBGSS_SPECIAL_AUTH_CFGAPEN_M 0x00000010U +#define DBGSS_SPECIAL_AUTH_CFGAPEN_S 4U +#define DBGSS_SPECIAL_AUTH_CFGAPEN_EN 0x00000010U +#define DBGSS_SPECIAL_AUTH_CFGAPEN_DIS 0x00000000U + +// Field: [2] DFTAPEN +// +// Indicates status of DFTAPEN +// ENUMs: +// EN Enable DFT-TAP +// DIS Disable DFT-TAP +#define DBGSS_SPECIAL_AUTH_DFTAPEN 0x00000004U +#define DBGSS_SPECIAL_AUTH_DFTAPEN_M 0x00000004U +#define DBGSS_SPECIAL_AUTH_DFTAPEN_S 2U +#define DBGSS_SPECIAL_AUTH_DFTAPEN_EN 0x00000004U +#define DBGSS_SPECIAL_AUTH_DFTAPEN_DIS 0x00000000U + +// Field: [0] SECAPEN +// +// Indicates status of SECAP +// ENUMs: +// EN Enable SEC-AP +// DIS Disable SEC-AP +#define DBGSS_SPECIAL_AUTH_SECAPEN 0x00000001U +#define DBGSS_SPECIAL_AUTH_SECAPEN_M 0x00000001U +#define DBGSS_SPECIAL_AUTH_SECAPEN_S 0U +#define DBGSS_SPECIAL_AUTH_SECAPEN_EN 0x00000001U +#define DBGSS_SPECIAL_AUTH_SECAPEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_SPECIAL_AUTH_SET +// +//***************************************************************************** +// Field: [31:24] KEY +// +// This field must be configured with 0xA5 in order to access this register. +// ENUMs: +// _to_unlock_w_ This field must be written with 0xA5 to be able to +// set any of the enable bits +#define DBGSS_SPECIAL_AUTH_SET_KEY_W 8U +#define DBGSS_SPECIAL_AUTH_SET_KEY_M 0xFF000000U +#define DBGSS_SPECIAL_AUTH_SET_KEY_S 24U +#define DBGSS_SPECIAL_AUTH_SET_KEY__TO_UNLOCK_W_ 0xA5000000U + +// Field: [6] DBGDIS +// +// This bit sets DBGDIS in SPECIAL_AUTH register. +// ENUMs: +// SET SET DBGDIS +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_SET_DBGDIS 0x00000040U +#define DBGSS_SPECIAL_AUTH_SET_DBGDIS_M 0x00000040U +#define DBGSS_SPECIAL_AUTH_SET_DBGDIS_S 6U +#define DBGSS_SPECIAL_AUTH_SET_DBGDIS_SET 0x00000040U +#define DBGSS_SPECIAL_AUTH_SET_DBGDIS_NOEFF 0x00000000U + +// Field: [5] AHBAPEN +// +// This bit sets AHBAPEN in SPECIAL_AUTH register. +// ENUMs: +// SET SET AHB-AP +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_SET_AHBAPEN 0x00000020U +#define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_M 0x00000020U +#define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_S 5U +#define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_SET 0x00000020U +#define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_NOEFF 0x00000000U + +// Field: [4] CFGAPEN +// +// This bit sets CFGAPEN in SPECIAL_AUTH register. +// ENUMs: +// SET Set CFGAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_SET_CFGAPEN 0x00000010U +#define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_M 0x00000010U +#define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_S 4U +#define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_SET 0x00000010U +#define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_NOEFF 0x00000000U + +// Field: [2] DFTAPEN +// +// This bit sets DFTAPEN in SPECIAL_AUTH register. +// ENUMs: +// SET Set DFTAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_SET_DFTAPEN 0x00000004U +#define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_M 0x00000004U +#define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_S 2U +#define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_SET 0x00000004U +#define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_NOEFF 0x00000000U + +// Field: [0] SECAPEN +// +// This bit sets SECAPEN bit in SPECIAL_AUTH register. +// ENUMs: +// SET Set SECAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_SET_SECAPEN 0x00000001U +#define DBGSS_SPECIAL_AUTH_SET_SECAPEN_M 0x00000001U +#define DBGSS_SPECIAL_AUTH_SET_SECAPEN_S 0U +#define DBGSS_SPECIAL_AUTH_SET_SECAPEN_SET 0x00000001U +#define DBGSS_SPECIAL_AUTH_SET_SECAPEN_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_SPECIAL_AUTH_CLR +// +//***************************************************************************** +// Field: [31:24] KEY +// +// This field must be configured with 0x22 in order to access this register. +// ENUMs: +// _to_unlock_w_ This field must be written with 0x22 to be able to +// clear any of the enable bits +#define DBGSS_SPECIAL_AUTH_CLR_KEY_W 8U +#define DBGSS_SPECIAL_AUTH_CLR_KEY_M 0xFF000000U +#define DBGSS_SPECIAL_AUTH_CLR_KEY_S 24U +#define DBGSS_SPECIAL_AUTH_CLR_KEY__TO_UNLOCK_W_ 0x22000000U + +// Field: [6] DBGDIS +// +// This bit clears DBGDIS in SPECIAL_AUTH register. +// ENUMs: +// CLR Clear DBGDIS +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_CLR_DBGDIS 0x00000040U +#define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_M 0x00000040U +#define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_S 6U +#define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_CLR 0x00000040U +#define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_NOEFF 0x00000000U + +// Field: [5] AHBAPEN +// +// This bit clears AHBAPEN in SPECIAL_AUTH register. +// ENUMs: +// CLR Clear AHBAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN 0x00000020U +#define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_M 0x00000020U +#define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_S 5U +#define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_CLR 0x00000020U +#define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_NOEFF 0x00000000U + +// Field: [4] CFGAPEN +// +// This bit clears CFGAPEN in SPECIAL_AUTH register. +// ENUMs: +// CLR Clear CFGAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN 0x00000010U +#define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_M 0x00000010U +#define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_S 4U +#define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_CLR 0x00000010U +#define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_NOEFF 0x00000000U + +// Field: [2] DFTAPEN +// +// This bit clears DFTAPEN in SPECIAL_AUTH register. +// ENUMs: +// CLR Clear DFTAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN 0x00000004U +#define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_M 0x00000004U +#define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_S 2U +#define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_CLR 0x00000004U +#define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_NOEFF 0x00000000U + +// Field: [0] SECAPEN +// +// This bit clears SECAPEN in SPECIAL_AUTH register. +// ENUMs: +// CLR Clear SECAPEN +// NOEFF Writing 0 has no effect +#define DBGSS_SPECIAL_AUTH_CLR_SECAPEN 0x00000001U +#define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_M 0x00000001U +#define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_S 0U +#define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_CLR 0x00000001U +#define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_APP_AUTH +// +//***************************************************************************** +// Field: [1] NIDEN +// +// Controls non-invasive debug enable. +// ENUMs: +// EN Non-invasive debug enabled +// DIS Non-invasive debug disabled +#define DBGSS_APP_AUTH_NIDEN 0x00000002U +#define DBGSS_APP_AUTH_NIDEN_M 0x00000002U +#define DBGSS_APP_AUTH_NIDEN_S 1U +#define DBGSS_APP_AUTH_NIDEN_EN 0x00000002U +#define DBGSS_APP_AUTH_NIDEN_DIS 0x00000000U + +// Field: [0] DBGEN +// +// Controls invasive debug enable. +// ENUMs: +// EN Invasive debug enabled +// DIS Invasive debug disabled +#define DBGSS_APP_AUTH_DBGEN 0x00000001U +#define DBGSS_APP_AUTH_DBGEN_M 0x00000001U +#define DBGSS_APP_AUTH_DBGEN_S 0U +#define DBGSS_APP_AUTH_DBGEN_EN 0x00000001U +#define DBGSS_APP_AUTH_DBGEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_APP_AUTH_SET +// +//***************************************************************************** +// Field: [31:24] KEY +// +// This field must be configured with 0x39 in order to access this register. +// ENUMs: +// _to_unlock_w_ Write this value 0x39 to unlock writing to the +// APP_AUTH_SET register +#define DBGSS_APP_AUTH_SET_KEY_W 8U +#define DBGSS_APP_AUTH_SET_KEY_M 0xFF000000U +#define DBGSS_APP_AUTH_SET_KEY_S 24U +#define DBGSS_APP_AUTH_SET_KEY__TO_UNLOCK_W_ 0x39000000U + +// Field: [1] NIDEN +// +// Sets NIDEN bit in [APP_AUTH ]register. +// ENUMs: +// SET Sets NIDEN +// NOEFF Writing 0 has no effect +#define DBGSS_APP_AUTH_SET_NIDEN 0x00000002U +#define DBGSS_APP_AUTH_SET_NIDEN_M 0x00000002U +#define DBGSS_APP_AUTH_SET_NIDEN_S 1U +#define DBGSS_APP_AUTH_SET_NIDEN_SET 0x00000002U +#define DBGSS_APP_AUTH_SET_NIDEN_NOEFF 0x00000000U + +// Field: [0] DBGEN +// +// Sets DBGEN bit in APP_AUTH register. +// ENUMs: +// SET Sets DBGEN +// NOEFF Writing 0 has no effect +#define DBGSS_APP_AUTH_SET_DBGEN 0x00000001U +#define DBGSS_APP_AUTH_SET_DBGEN_M 0x00000001U +#define DBGSS_APP_AUTH_SET_DBGEN_S 0U +#define DBGSS_APP_AUTH_SET_DBGEN_SET 0x00000001U +#define DBGSS_APP_AUTH_SET_DBGEN_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_APP_AUTH_CLR +// +//***************************************************************************** +// Field: [31:24] KEY +// +// This field must be configured with 0x7D in order to access this register. +// ENUMs: +// _to_unlock_w_ Write this value 0x7D to unlock writing to the +// APP_AUTH_CLR register +#define DBGSS_APP_AUTH_CLR_KEY_W 8U +#define DBGSS_APP_AUTH_CLR_KEY_M 0xFF000000U +#define DBGSS_APP_AUTH_CLR_KEY_S 24U +#define DBGSS_APP_AUTH_CLR_KEY__TO_UNLOCK_W_ 0x7D000000U + +// Field: [1] NIDEN +// +// Clears NIDEN bit in APP_AUTH register. +// ENUMs: +// CLR Clears NIDEN +// NOEFF Writing 0 has no effect +#define DBGSS_APP_AUTH_CLR_NIDEN 0x00000002U +#define DBGSS_APP_AUTH_CLR_NIDEN_M 0x00000002U +#define DBGSS_APP_AUTH_CLR_NIDEN_S 1U +#define DBGSS_APP_AUTH_CLR_NIDEN_CLR 0x00000002U +#define DBGSS_APP_AUTH_CLR_NIDEN_NOEFF 0x00000000U + +// Field: [0] DBGEN +// +// Clears DBGEN bit in APP_AUTH register. +// ENUMs: +// CLR Clears DBGEN +// NOEFF Writing 0 has no effect +#define DBGSS_APP_AUTH_CLR_DBGEN 0x00000001U +#define DBGSS_APP_AUTH_CLR_DBGEN_M 0x00000001U +#define DBGSS_APP_AUTH_CLR_DBGEN_S 0U +#define DBGSS_APP_AUTH_CLR_DBGEN_CLR 0x00000001U +#define DBGSS_APP_AUTH_CLR_DBGEN_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: DBGSS_O_DBGCTL +// +//***************************************************************************** +// Field: [5] SWDCEN +// +// This bit is used to enable connection between SWD pads and IceMelter (wakeup +// circuit used for detecting debug probe) +// ENUMs: +// EN Connection enabled +// DIS Connection disabled +#define DBGSS_DBGCTL_SWDCEN 0x00000020U +#define DBGSS_DBGCTL_SWDCEN_M 0x00000020U +#define DBGSS_DBGCTL_SWDCEN_S 5U +#define DBGSS_DBGCTL_SWDCEN_EN 0x00000020U +#define DBGSS_DBGCTL_SWDCEN_DIS 0x00000000U + +// Field: [4] DBGPWRUPACK +// +// This bit field specifies the status of dbgpwrupack from pmctl. +// ENUMs: +// EN dbgpwrupreq is acknowledged. +// DIS dbgpwrupreq is not acknowledged +#define DBGSS_DBGCTL_DBGPWRUPACK 0x00000010U +#define DBGSS_DBGCTL_DBGPWRUPACK_M 0x00000010U +#define DBGSS_DBGCTL_DBGPWRUPACK_S 4U +#define DBGSS_DBGCTL_DBGPWRUPACK_EN 0x00000010U +#define DBGSS_DBGCTL_DBGPWRUPACK_DIS 0x00000000U + +// Field: [3] SYSPWRUPACK +// +// This bit field specify the status of syspwrupack from pmctl. +// ENUMs: +// EN syspwrupreq is acknowledged +// DIS syspwrupreq is not acknowledged +#define DBGSS_DBGCTL_SYSPWRUPACK 0x00000008U +#define DBGSS_DBGCTL_SYSPWRUPACK_M 0x00000008U +#define DBGSS_DBGCTL_SYSPWRUPACK_S 3U +#define DBGSS_DBGCTL_SYSPWRUPACK_EN 0x00000008U +#define DBGSS_DBGCTL_SYSPWRUPACK_DIS 0x00000000U + +// Field: [2] JTAGSEL +// +// This bit field specifies the status of JTAG MODE for TEST TAP. +// ENUMs: +// EN TEST TAP enabled +// DIS TEST TAP disabled +#define DBGSS_DBGCTL_JTAGSEL 0x00000004U +#define DBGSS_DBGCTL_JTAGSEL_M 0x00000004U +#define DBGSS_DBGCTL_JTAGSEL_S 2U +#define DBGSS_DBGCTL_JTAGSEL_EN 0x00000004U +#define DBGSS_DBGCTL_JTAGSEL_DIS 0x00000000U + +// Field: [1] SWDSEL +// +// This bit field specifies the status of SWD MODE for connection. +// ENUMs: +// EN debug connection enabled. +// DIS debug connection disabled. +#define DBGSS_DBGCTL_SWDSEL 0x00000002U +#define DBGSS_DBGCTL_SWDSEL_M 0x00000002U +#define DBGSS_DBGCTL_SWDSEL_S 1U +#define DBGSS_DBGCTL_SWDSEL_EN 0x00000002U +#define DBGSS_DBGCTL_SWDSEL_DIS 0x00000000U + +// Field: [0] SWDOVR +// +// This bit is used for connecting to IO pads to SWCLK/IO on SW-DP through a +// software request and establish SWD connection without IceMelter trigger for +// debug purpose. +// ENUMs: +// DBGENA Force 1 or debug enable mode in which SWD +// connection is established bypassing IceMelter +// sequence +// TRNSPRT Transparent mode in which SWD connection is +// established via IceMelter Sequence. +#define DBGSS_DBGCTL_SWDOVR 0x00000001U +#define DBGSS_DBGCTL_SWDOVR_M 0x00000001U +#define DBGSS_DBGCTL_SWDOVR_S 0U +#define DBGSS_DBGCTL_SWDOVR_DBGENA 0x00000001U +#define DBGSS_DBGCTL_SWDOVR_TRNSPRT 0x00000000U + + +#endif // __DBGSS__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dcb.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dcb.h new file mode 100644 index 00000000..bfccc5b8 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dcb.h @@ -0,0 +1,272 @@ +/****************************************************************************** +* Filename: hw_dcb_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_DCB_H__ +#define __HW_DCB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DCB component +// +//***************************************************************************** +// Debug Fault Status Register +#define DCB_O_DFSR 0x00000000U + +// Debug Halting Control and Status Register +#define DCB_O_DHCSR 0x000000C0U + +// Debug Core Register Selector Register +#define DCB_O_DCRSR 0x000000C4U + +// Debug Core Register Data Register +#define DCB_O_DCRDR 0x000000C8U + +// Debug Exception and Monitor Control Register +#define DCB_O_DEMCR 0x000000CCU + +//***************************************************************************** +// +// Register: DCB_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag +// 0x0:No edbgrq external debug request occurred +// 0x1:Edbgrq has halted the core +#define DCB_DFSR_EXTERNAL 0x00000010U +#define DCB_DFSR_EXTERNAL_M 0x00000010U +#define DCB_DFSR_EXTERNAL_S 4U + +// Field: [3] VCATCH +// +// Vector catch flag. When the VCATCH flag is set, a flag in the Debug +// Exception and Monitor Control Register is also set to indicate the type of +// vector catch. +// 0x0:No vector catch occurred +// 0x1:Vector catch occurred +#define DCB_DFSR_VCATCH 0x00000008U +#define DCB_DFSR_VCATCH_M 0x00000008U +#define DCB_DFSR_VCATCH_S 3U + +// Field: [2] DWTRAP +// +// Data Watchpoint (DW) flag. +// 0x0:No dw match +// 0x1:Dw match +#define DCB_DFSR_DWTRAP 0x00000004U +#define DCB_DFSR_DWTRAP_M 0x00000004U +#define DCB_DFSR_DWTRAP_S 2U + +// Field: [1] BKPT +// +// The BKPT flag is set by the execution of the BKPT instruction or on an +// instruction whose address triggered the breakpoint comparator match. When +// the processor has halted, the return PC points to the address of the +// breakpointed instruction. +// 0x0:No bkpt instruction or hardware breakpoint match +// 0x1:Bkpt instruction or hardware breakpoint match +#define DCB_DFSR_BKPT 0x00000002U +#define DCB_DFSR_BKPT_M 0x00000002U +#define DCB_DFSR_BKPT_S 1U + +// Field: [0] HALTED +// +// Halt request flag +// 0x0:No halt request +// 0x1:Halt requested by dap access to c_halt or halted with c_step asserted +#define DCB_DFSR_HALTED 0x00000001U +#define DCB_DFSR_HALTED_M 0x00000001U +#define DCB_DFSR_HALTED_S 0U + +//***************************************************************************** +// +// Register: DCB_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is currently reset and held in +// reset. +#define DCB_DHCSR_S_RESET_ST 0x02000000U +#define DCB_DHCSR_S_RESET_ST_M 0x02000000U +#define DCB_DHCSR_S_RESET_ST_S 25U + +// Field: [24] S_RETIRE_ST +// +// Core has retired at least part of an instruction since last read. This is a +// sticky bit that clears on read. +#define DCB_DHCSR_S_RETIRE_ST 0x01000000U +#define DCB_DHCSR_S_RETIRE_ST_M 0x01000000U +#define DCB_DHCSR_S_RETIRE_ST_S 24U + +// Field: [17] S_HALT +// +// The core is halted in debug state only if S_HALT is set. +#define DCB_DHCSR_S_HALT 0x00020000U +#define DCB_DHCSR_S_HALT_M 0x00020000U +#define DCB_DHCSR_S_HALT_S 17U + +// Field: [16] S_REGRDY +// +// Register Read/Write to the Debug Core Register Selector Register is +// available. Set in response to a successful register access. +#define DCB_DHCSR_S_REGRDY 0x00010000U +#define DCB_DHCSR_S_REGRDY_M 0x00010000U +#define DCB_DHCSR_S_REGRDY_S 16U + +// Field: [3] C_MASKINTS +// +// When this bit is set and debug is enabled, external interrupts, SysTick, and +// PendSV are masked. Does not affect NMI, Hard Fault or SVCall. When C_DEBUGEN +// = 0, this bit has no effect. +#define DCB_DHCSR_C_MASKINTS 0x00000008U +#define DCB_DHCSR_C_MASKINTS_M 0x00000008U +#define DCB_DHCSR_C_MASKINTS_S 3U + +// Field: [2] C_STEP +// +// Causes a debug event on any instruction or exception being executed, +// resulting in the core single stepping. +#define DCB_DHCSR_C_STEP 0x00000004U +#define DCB_DHCSR_C_STEP_M 0x00000004U +#define DCB_DHCSR_C_STEP_S 2U + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core triggers a debug +// event, for example, on a breakpoint. This bit clears on core reset. When +// C_DEBUGEN = 0, this bit has no effect. +#define DCB_DHCSR_C_HALT 0x00000002U +#define DCB_DHCSR_C_HALT_M 0x00000002U +#define DCB_DHCSR_C_HALT_S 1U + +// Field: [0] C_DEBUGEN +// +// Enables or disable debug +// ENUMs: +// DBG_EN Debug enabled +// DBG_DIS Debug disabled +#define DCB_DHCSR_C_DEBUGEN 0x00000001U +#define DCB_DHCSR_C_DEBUGEN_M 0x00000001U +#define DCB_DHCSR_C_DEBUGEN_S 0U +#define DCB_DHCSR_C_DEBUGEN_DBG_EN 0x00000001U +#define DCB_DHCSR_C_DEBUGEN_DBG_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DCB_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWnR +// +// Register Write-not-Read +// 0x0:Read +// 0x1:Write +#define DCB_DCRSR_REGWNR 0x00010000U +#define DCB_DCRSR_REGWNR_M 0x00010000U +#define DCB_DCRSR_REGWNR_S 16U + +// Field: [4:0] REGSEL +// +// Select processor register +// 0x00:R0 +// 0x01:R1 +// 0x02:R2 +// 0x03:R3 +// 0x04:R4 +// 0x05:R5 +// 0x06:R6 +// 0x07:R7 +// 0x08:R8 +// 0x09:R9 +// 0x0a:R10 +// 0x0b:R11 +// 0x0c:R12 +// 0x0d:Current sp +// 0x0e:Lr +// 0x0f:Debug Return Address +// 0x10:Xpsr flags, execution number, and state information +// 0x11:Msp (main sp) +// 0x12:Psp (process sp) +// 0x14:Control (dcrdr[25:24]), primask (dcrdr[0]) +#define DCB_DCRSR_REGSEL_W 5U +#define DCB_DCRSR_REGSEL_M 0x0000001FU +#define DCB_DCRSR_REGSEL_S 0U + +//***************************************************************************** +// +// Register: DCB_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DBGTMP +// +// Data temporary cache, for reading and writing registers. +#define DCB_DCRDR_DBGTMP_W 32U +#define DCB_DCRDR_DBGTMP_M 0xFFFFFFFFU +#define DCB_DCRDR_DBGTMP_S 0U + +//***************************************************************************** +// +// Register: DCB_O_DEMCR +// +//***************************************************************************** +// Field: [24] DWTENA +// +// Global enable or disable for the DW unit +// 0x0:Dw unit disabled. watchpoint cannot halt the core. the dw pcsr reads as +// oxffffffff. +// 0x1:Dw unit enabled +#define DCB_DEMCR_DWTENA 0x01000000U +#define DCB_DEMCR_DWTENA_M 0x01000000U +#define DCB_DEMCR_DWTENA_S 24U + +// Field: [10] VC_HARDERR +// +// Debug trap on a Hard Fault +#define DCB_DEMCR_VC_HARDERR 0x00000400U +#define DCB_DEMCR_VC_HARDERR_M 0x00000400U +#define DCB_DEMCR_VC_HARDERR_S 10U + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if HRESETn is asserted +#define DCB_DEMCR_VC_CORERESET 0x00000001U +#define DCB_DEMCR_VC_CORERESET_M 0x00000001U +#define DCB_DEMCR_VC_CORERESET_S 0U + + +#endif // __DCB__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h new file mode 100644 index 00000000..c9fdc25b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h @@ -0,0 +1,114 @@ +/****************************************************************************** +* Copyright (c) 2021-2023 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ +#ifndef __HW_DEVICE_H__ +#define __HW_DEVICE_H__ + +#include "hw_memmap.h" +#include "hw_platform.h" + +//***************************************************************************** +// +// Address, offset and size definitions +// +//***************************************************************************** + +// --- ROM definitions --- +/// Size of the call stack used in ROM, in number of bytes +#define BOOT_CSTACK_SIZE (1024-CCFG_USER_RECORD_SIZE) + +// --- FLASH definitions --- +/// Size of a 1T flash sector, in number of bytes +#define FLASH_1T_SECTOR_SIZE 2048 +/// Flash word width in number of bits +#define FLASH_DATAWIDTH_BITS 128 +/// Size of a 2T flash sector, in number of bytes +#define FLASH_2T_SECTOR_SIZE (FLASH_1T_SECTOR_SIZE/2) +/// Size of a MAIN flash sector, in number of bytes +#define FLASH_MAIN_SECTOR_SIZE FLASH_1T_SECTOR_SIZE + +// --- Factory Configuration (FCFG) definitions --- +/// Size of generalTrims section in FCFG, in number of 32-bit words +#define FCFG_GENERALTRIMS_SIZE ((FLASH_2T_SECTOR_SIZE / 4) - 104) + +// --- Customer Configuration (CCFG) definitions --- +/*! Macro for default CCFG configuration. All fields can be overwritten by + * setting the field to another value further down in the struct definition + * within a C file. + */ +#define CCFG_DEFAULT_VALUES \ + .bootCfg = { \ + .pBldrVtor = XCFG_BC_PBLDR_UNDEF, \ + .bldrParam = { 0x00000000 }, \ + .pAppVtor = CCFG_BC_PAPP_NONE, \ + .crc32 = 0x0BAD0BAD \ + }, \ + .hwOpts[0] = 0xFFFFFFFF, \ + .hwOpts[1] = 0xFFFFFFFF, \ + .permissions = { \ + .allowReturnToFactory = CCFG_PERMISSION_ALLOW, \ + .allowFakeStby = CCFG_PERMISSION_ALLOW, \ + .allowToolsClientMode = CCFG_PERMISSION_ALLOW, \ + .allowChipErase = CCFG_PERMISSION_ALLOW, \ + .allowFlashProgram = CCFG_PERMISSION_ALLOW, \ + .allowFlashVerify = CCFG_PERMISSION_ALLOW, \ + .allowEnergyTrace = CCFG_PERMISSION_ALLOW, \ + .allowDebugPort = CCFG_PERMISSION_ALLOW, \ + }, \ + .misc = { \ + .saciTimeoutOverride = 0 \ + }, \ + .flashProt = { \ + .writeEraseProt = { \ + .mainSectors0_31 = 0xFFFFFFFF, \ + .mainSectors32_255 = 0xFFFFFFFF, \ + .auxSectors = 0xFFFFFFFF, \ + }, \ + .res = 0xFFFFFFFF, \ + .chipEraseRetain = { \ + .mainSectors0_31 = 0, \ + .mainSectors32_255 = 0, \ + } \ + }, \ + .hwInitCopyList = { CPYLST_EOL }, \ + .crc32 = 0x0BAD0BAD, \ + .userRecord.crc32 = 0x0BAD0BAD, \ + .debugCfg = { \ + .authorization = CCFG_DBGAUTH_DBGOPEN, \ + .allowBldr = CCFG_DBGBLDR_ALLOW, \ + .pwdId = {1, 1, 2, 3, 5, 8, 13, 21 }, \ + .pwdHash = { /* SHA256 of "Open Sesame!" */ \ + 0x6D, 0xD7, 0xE4, 0x36, 0xEB, 0xF4, 0x31, 0xDF, \ + 0x95, 0xAE, 0x15, 0xEE, 0x03, 0xBA, 0x8E, 0xE4, \ + 0xC4, 0xC6, 0x3F, 0xD8, 0x45, 0x3F, 0x67, 0x5E, \ + 0x74, 0xD7, 0xC2, 0x01, 0x2C, 0x90, 0x58, 0xE5, \ + }, \ + .crc32 = 0x0BAD0BAD, \ + } +#endif // __HW_DEVICE_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dma.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dma.h new file mode 100644 index 00000000..0f79ccc8 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_dma.h @@ -0,0 +1,572 @@ +/****************************************************************************** +* Filename: hw_dma_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_DMA_H__ +#define __HW_DMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DMA component +// +//***************************************************************************** +// Status Register. +#define DMA_O_STATUS 0x00000000U + +// Configuration Register. +#define DMA_O_CFG 0x00000004U + +// Channel Control Data Base Pointer Register. +#define DMA_O_CTRL 0x00000008U + +// Channel Alternate Control Data Base Pointer Register. +#define DMA_O_ALTCTRL 0x0000000CU + +// Channel Wait On Request Status Register. +#define DMA_O_WAITONREQ 0x00000010U + +// Channel Software Request Register. +#define DMA_O_SOFTREQ 0x00000014U + +// Channel Set UseBurst Register. +#define DMA_O_SETBURST 0x00000018U + +// Channel Clear UseBurst Register. +#define DMA_O_CLEARBURST 0x0000001CU + +// Channel Set Request Mask Register. +#define DMA_O_SETREQMASK 0x00000020U + +// Clear Channel Request Mask Register. +#define DMA_O_CLEARREQMASK 0x00000024U + +// Set Channel Enable Register. +#define DMA_O_SETCHANNELEN 0x00000028U + +// Clear Channel Enable Register. +#define DMA_O_CLEARCHANNELEN 0x0000002CU + +// Channel Set Primary-Alternate Register. +#define DMA_O_SETCHNLPRIALT 0x00000030U + +// Channel Clear Primary-Alternate Register. +#define DMA_O_CLEARCHNLPRIALT 0x00000034U + +// Set Channel Priority Register. +#define DMA_O_SETCHNLPRIORITY 0x00000038U + +// Clear Channel Priority Register. +#define DMA_O_CLEARCHNLPRIORITY 0x0000003CU + +// Error Status and Clear Register. +#define DMA_O_ERROR 0x0000004CU + +// Channel Request Done Register. +#define DMA_O_REQDONE 0x00000504U + +// Channel Request Done Mask Register. +#define DMA_O_DONEMASK 0x00000520U + +//***************************************************************************** +// +// Register: DMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define DMA_STATUS_TEST_W 4U +#define DMA_STATUS_TEST_M 0xF0000000U +#define DMA_STATUS_TEST_S 28U + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define DMA_STATUS_TOTALCHANNELS_W 5U +#define DMA_STATUS_TOTALCHANNELS_M 0x001F0000U +#define DMA_STATUS_TOTALCHANNELS_S 16U + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define DMA_STATUS_STATE_W 4U +#define DMA_STATUS_STATE_M 0x000000F0U +#define DMA_STATUS_STATE_S 4U + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// ENUMs: +// EN Controller is enabled +// DIS Controller is disabled +#define DMA_STATUS_MASTERENABLE 0x00000001U +#define DMA_STATUS_MASTERENABLE_M 0x00000001U +#define DMA_STATUS_MASTERENABLE_S 0U +#define DMA_STATUS_MASTERENABLE_EN 0x00000001U +#define DMA_STATUS_MASTERENABLE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define DMA_CFG_PRTOCTRL_W 3U +#define DMA_CFG_PRTOCTRL_M 0x000000E0U +#define DMA_CFG_PRTOCTRL_S 5U + +// Field: [0] MASTERENABLE +// +// Enables the controller. +// ENUMs: +// EN Enables the controller +// DIS Disables the controller +#define DMA_CFG_MASTERENABLE 0x00000001U +#define DMA_CFG_MASTERENABLE_M 0x00000001U +#define DMA_CFG_MASTERENABLE_S 0U +#define DMA_CFG_MASTERENABLE_EN 0x00000001U +#define DMA_CFG_MASTERENABLE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: DMA_O_CTRL +// +//***************************************************************************** +// Field: [31:8] BASEPTR +// +// This register point to the base address for the primary data structures of +// each uDMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when uDMA is in usage +#define DMA_CTRL_BASEPTR_W 24U +#define DMA_CTRL_BASEPTR_M 0xFFFFFF00U +#define DMA_CTRL_BASEPTR_S 8U + +//***************************************************************************** +// +// Register: DMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define DMA_ALTCTRL_BASEPTR_W 32U +#define DMA_ALTCTRL_BASEPTR_M 0xFFFFFFFFU +#define DMA_ALTCTRL_BASEPTR_S 0U + +//***************************************************************************** +// +// Register: DMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [7:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define DMA_WAITONREQ_CHNLSTATUS_W 8U +#define DMA_WAITONREQ_CHNLSTATUS_M 0x000000FFU +#define DMA_WAITONREQ_CHNLSTATUS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define DMA_SOFTREQ_CHNLS_W 8U +#define DMA_SOFTREQ_CHNLS_M 0x000000FFU +#define DMA_SOFTREQ_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SETBURST +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel Ch. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_SETBURST_CHNLS_W 8U +#define DMA_SETBURST_CHNLS_M 0x000000FFU +#define DMA_SETBURST_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect. +#define DMA_CLEARBURST_CHNLS_W 8U +#define DMA_CLEARBURST_CHNLS_M 0x000000FFU +#define DMA_CLEARBURST_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [Ch] and uDMA single +// request channel [Ch] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_SETREQMASK_CHNLS_W 8U +#define DMA_SETREQMASK_CHNLS_M 0x000000FFU +#define DMA_SETREQMASK_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Set the appropriate bit to enable uDMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel Ch from +// generating requests. +// Bit [Ch] = 1: Enables channel [Ch] to generate uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect. +#define DMA_CLEARREQMASK_CHNLS_W 8U +#define DMA_CLEARREQMASK_CHNLS_M 0x000000FFU +#define DMA_CLEARREQMASK_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Returns the enable status of the channels, or enable the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_SETCHANNELEN_CHNLS_W 8U +#define DMA_SETCHANNELEN_CHNLS_M 0x000000FFU +#define DMA_SETCHANNELEN_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_CLEARCHANNELEN_CHNLS_W 8U +#define DMA_CLEARCHANNELEN_CHNLS_M 0x000000FFU +#define DMA_CLEARCHANNELEN_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_SETCHNLPRIALT_CHNLS_W 8U +#define DMA_SETCHNLPRIALT_CHNLS_M 0x000000FFU +#define DMA_SETCHNLPRIALT_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_CLEARCHNLPRIALT_CHNLS_W 8U +#define DMA_CLEARCHNLPRIALT_CHNLS_M 0x000000FFU +#define DMA_CLEARCHNLPRIALT_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_SETCHNLPRIORITY_CHNLS_W 8U +#define DMA_SETCHNLPRIORITY_CHNLS_M 0x000000FFU +#define DMA_SETCHNLPRIORITY_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define DMA_CLEARCHNLPRIORITY_CHNLS_W 8U +#define DMA_CLEARCHNLPRIORITY_CHNLS_M 0x000000FFU +#define DMA_CLEARCHNLPRIORITY_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define DMA_ERROR_STATUS 0x00000001U +#define DMA_ERROR_STATUS_M 0x00000001U +#define DMA_ERROR_STATUS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_REQDONE +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define DMA_REQDONE_CHNLS_W 8U +#define DMA_REQDONE_CHNLS_M 0x000000FFU +#define DMA_REQDONE_CHNLS_S 0U + +//***************************************************************************** +// +// Register: DMA_O_DONEMASK +// +//***************************************************************************** +// Field: [7:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active state to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define DMA_DONEMASK_CHNLS_W 8U +#define DMA_DONEMASK_CHNLS_M 0x000000FFU +#define DMA_DONEMASK_CHNLS_S 0U + + +#endif // __DMA__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtsvt.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtsvt.h new file mode 100644 index 00000000..326084c2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtsvt.h @@ -0,0 +1,4678 @@ +/****************************************************************************** +* Filename: hw_evtsvt_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_EVTSVT_H__ +#define __HW_EVTSVT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVTSVT component +// +//***************************************************************************** +// Description +#define EVTSVT_O_DESC 0x00000000U + +// Extended Description +#define EVTSVT_O_DESCEX 0x00000004U + +// Digital test bus control +#define EVTSVT_O_DTB 0x00000064U + +// Output Selection for CPU NMI Exception +#define EVTSVT_O_NMISEL 0x00000400U + +// Output Selection for CPU Interrupt CPUIRQ0 +#define EVTSVT_O_CPUIRQ0SEL 0x00000404U + +// Output Selection for CPU Interrupt CPUIRQ1 +#define EVTSVT_O_CPUIRQ1SEL 0x00000408U + +// Output Selection for CPU Interrupt CPUIRQ2 +#define EVTSVT_O_CPUIRQ2SEL 0x0000040CU + +// Output Selection for CPU Interrupt CPUIRQ3 +#define EVTSVT_O_CPUIRQ3SEL 0x00000410U + +// Output Selection for CPU Interrupt CPUIRQ4 +#define EVTSVT_O_CPUIRQ4SEL 0x00000414U + +// Output Selection for CPU Interrupt CPUIRQ5 +#define EVTSVT_O_CPUIRQ5SEL 0x00000418U + +// Output Selection for CPU Interrupt CPUIRQ6 +#define EVTSVT_O_CPUIRQ6SEL 0x0000041CU + +// Output Selection for CPU Interrupt CPUIRQ7 +#define EVTSVT_O_CPUIRQ7SEL 0x00000420U + +// Output Selection for CPU Interrupt CPUIRQ8 +#define EVTSVT_O_CPUIRQ8SEL 0x00000424U + +// Output Selection for CPU Interrupt CPUIRQ9 +#define EVTSVT_O_CPUIRQ9SEL 0x00000428U + +// Output Selection for CPU Interrupt CPUIRQ10 +#define EVTSVT_O_CPUIRQ10SEL 0x0000042CU + +// Output Selection for CPU Interrupt CPUIRQ11 +#define EVTSVT_O_CPUIRQ11SEL 0x00000430U + +// Output Selection for CPU Interrupt CPUIRQ12 +#define EVTSVT_O_CPUIRQ12SEL 0x00000434U + +// Output Selection for CPU Interrupt CPUIRQ13 +#define EVTSVT_O_CPUIRQ13SEL 0x00000438U + +// Output Selection for CPU Interrupt CPUIRQ14 +#define EVTSVT_O_CPUIRQ14SEL 0x0000043CU + +// Output Selection for CPU Interrupt CPUIRQ15 +#define EVTSVT_O_CPUIRQ15SEL 0x00000440U + +// Output Selection for CPU Interrupt CPUIRQ16 +#define EVTSVT_O_CPUIRQ16SEL 0x00000444U + +// Output Selection for CPU Interrupt CPUIRQ17 +#define EVTSVT_O_CPUIRQ17SEL 0x00000448U + +// Output Selection for CPU Interrupt CPUIRQ18 +#define EVTSVT_O_CPUIRQ18SEL 0x0000044CU + +// Output Selection for SYSTIMC0 +#define EVTSVT_O_SYSTIMC0SEL 0x00000450U + +// Output Selection for SYSTIMC1 +#define EVTSVT_O_SYSTIMC1SEL 0x00000454U + +// Output Selection for SYSTIMC2 +#define EVTSVT_O_SYSTIMC2SEL 0x00000458U + +// Output Selection for SYSTIMC3 +#define EVTSVT_O_SYSTIMC3SEL 0x0000045CU + +// Output Selection for SYSTIMC4 +#define EVTSVT_O_SYSTIMC4SEL 0x00000460U + +// Output Selection for ADCTRG +#define EVTSVT_O_ADCTRGSEL 0x00000464U + +// Output Selection for LGPTSYNC +#define EVTSVT_O_LGPTSYNCSEL 0x00000468U + +// Output Selection for LGPT0IN0 +#define EVTSVT_O_LGPT0IN0SEL 0x0000046CU + +// Output Selection for LGPT0IN1 +#define EVTSVT_O_LGPT0IN1SEL 0x00000470U + +// Output Selection for LGPT0IN2 +#define EVTSVT_O_LGPT0IN2SEL 0x00000474U + +// Output Selection for LGPT0TEN +#define EVTSVT_O_LGPT0TENSEL 0x00000478U + +// Output Selection for LGPT1IN0 +#define EVTSVT_O_LGPT1IN0SEL 0x0000047CU + +// Output Selection for LGPT1IN1 +#define EVTSVT_O_LGPT1IN1SEL 0x00000480U + +// Output Selection for LGPT1IN2 +#define EVTSVT_O_LGPT1IN2SEL 0x00000484U + +// Output Selection for LGPT1TEN +#define EVTSVT_O_LGPT1TENSEL 0x00000488U + +// Output Selection for LGPT2IN0 +#define EVTSVT_O_LGPT2IN0SEL 0x0000048CU + +// Output Selection for LGPT2IN1 +#define EVTSVT_O_LGPT2IN1SEL 0x00000490U + +// Output Selection for LGPT2IN2 +#define EVTSVT_O_LGPT2IN2SEL 0x00000494U + +// Output Selection for LGPT2TEN +#define EVTSVT_O_LGPT2TENSEL 0x00000498U + +// Output Selection for LGPT3IN0 +#define EVTSVT_O_LGPT3IN0SEL 0x0000049CU + +// Output Selection for LGPT3IN1 +#define EVTSVT_O_LGPT3IN1SEL 0x000004A0U + +// Output Selection for LGPT3IN2 +#define EVTSVT_O_LGPT3IN2SEL 0x000004A4U + +// Output Selection for LGPT3TEN +#define EVTSVT_O_LGPT3TENSEL 0x000004A8U + +// Output Selection for LRFDIN0 +#define EVTSVT_O_LRFDIN0SEL 0x000004ACU + +// Output Selection for LRFDIN1 +#define EVTSVT_O_LRFDIN1SEL 0x000004B0U + +// Output Selection for LRFDIN2 +#define EVTSVT_O_LRFDIN2SEL 0x000004B4U + +// Output Selection for DMA CH0 +#define EVTSVT_O_DMACH0SEL 0x00000C00U + +// Output Selection for DMA CH1 +#define EVTSVT_O_DMACH1SEL 0x00000C04U + +// Output Selection for DMA CH2 +#define EVTSVT_O_DMACH2SEL 0x00000C08U + +// Output Selection for DMA CH3 +#define EVTSVT_O_DMACH3SEL 0x00000C0CU + +// Output Selection for DMA CH4 +#define EVTSVT_O_DMACH4SEL 0x00000C10U + +// Output Selection for DMA CH5 +#define EVTSVT_O_DMACH5SEL 0x00000C14U + +// Output Selection for DMA CH6 +#define EVTSVT_O_DMACH6SEL 0x00000C18U + +// Output Selection for DMA CH7 +#define EVTSVT_O_DMACH7SEL 0x00000C1CU + +//***************************************************************************** +// +// Register: EVTSVT_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define EVTSVT_DESC_MODID_W 16U +#define EVTSVT_DESC_MODID_M 0xFFFF0000U +#define EVTSVT_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// 0: Standard IP MMRs do not exist +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define EVTSVT_DESC_STDIPOFF_W 4U +#define EVTSVT_DESC_STDIPOFF_M 0x0000F000U +#define EVTSVT_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define EVTSVT_DESC_INSTIDX_W 4U +#define EVTSVT_DESC_INSTIDX_M 0x00000F00U +#define EVTSVT_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define EVTSVT_DESC_MAJREV_W 4U +#define EVTSVT_DESC_MAJREV_M 0x000000F0U +#define EVTSVT_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define EVTSVT_DESC_MINREV_W 4U +#define EVTSVT_DESC_MINREV_M 0x0000000FU +#define EVTSVT_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: EVTSVT_O_DESCEX +// +//***************************************************************************** +// Field: [31:22] IDMA +// +// Number of DMA input channels +#define EVTSVT_DESCEX_IDMA_W 10U +#define EVTSVT_DESCEX_IDMA_M 0xFFC00000U +#define EVTSVT_DESCEX_IDMA_S 22U + +// Field: [21:17] NDMA +// +// Number of DMA output channels +#define EVTSVT_DESCEX_NDMA_W 5U +#define EVTSVT_DESCEX_NDMA_M 0x003E0000U +#define EVTSVT_DESCEX_NDMA_S 17U + +// Field: [16] PD +// +// Power Domain. +// 0 : SVT +// 1 : ULL +#define EVTSVT_DESCEX_PD 0x00010000U +#define EVTSVT_DESCEX_PD_M 0x00010000U +#define EVTSVT_DESCEX_PD_S 16U + +// Field: [15:8] NSUB +// +// Number of Subscribers +#define EVTSVT_DESCEX_NSUB_W 8U +#define EVTSVT_DESCEX_NSUB_M 0x0000FF00U +#define EVTSVT_DESCEX_NSUB_S 8U + +// Field: [7:0] NPUB +// +// Number of Publishers +#define EVTSVT_DESCEX_NPUB_W 8U +#define EVTSVT_DESCEX_NPUB_M 0x000000FFU +#define EVTSVT_DESCEX_NPUB_S 0U + +//***************************************************************************** +// +// Register: EVTSVT_O_DTB +// +//***************************************************************************** +// Field: [1:0] SEL +// +// Digital test bus selection mux control. +// Non-zero select values output a 16 bit selected group of signals per value. +// ENUMs: +// DIS All 16 observation signals are set to zero. +#define EVTSVT_DTB_SEL_W 2U +#define EVTSVT_DTB_SEL_M 0x00000003U +#define EVTSVT_DTB_SEL_S 0U +#define EVTSVT_DTB_SEL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_NMISEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_NMI_SEL Selects an AON_NMI source, controlled by +// EVTULL:NMISEL +// NONE Always inactive +#define EVTSVT_NMISEL_PUBID_W 6U +#define EVTSVT_NMISEL_PUBID_M 0x0000003FU +#define EVTSVT_NMISEL_PUBID_S 0U +#define EVTSVT_NMISEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_NMISEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_NMISEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_NMISEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_NMISEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_NMISEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_NMISEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_NMISEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_NMISEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_NMISEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_NMISEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_NMISEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_NMISEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_NMISEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_NMISEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_NMISEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_NMISEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_NMISEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_NMISEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_NMISEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_NMISEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_NMISEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_NMISEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_NMISEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_NMISEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_NMISEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_NMISEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_NMISEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_NMISEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_NMISEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_NMISEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_NMISEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_NMISEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_NMISEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_NMISEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_NMISEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_NMISEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_NMISEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_NMISEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_NMISEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_NMISEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_NMISEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_NMISEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_NMISEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_NMISEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_NMISEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_NMISEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_NMISEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_NMISEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_NMISEL_PUBID_AON_NMI_SEL 0x00000001U +#define EVTSVT_NMISEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ0SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ0SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ0SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_CPUIRQ0SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ0SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ0SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ0SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ0SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ0SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_CPUIRQ0SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ0SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ0SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_CPUIRQ0SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ0SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ1SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ1SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ1SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_CPUIRQ1SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ1SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ1SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ1SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ1SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_CPUIRQ1SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ1SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ1SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_CPUIRQ1SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ1SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ2SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ2SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ2SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ2SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ2SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ2SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ2SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ2SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ2SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ2SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ2SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ2SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ2SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ2SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ2SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ2SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ2SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ2SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ2SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ3SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ3SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ3SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ3SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ3SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ3SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ3SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ3SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ3SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ3SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ3SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ3SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ3SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ3SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ3SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ3SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ3SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ3SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ3SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ3SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ4SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ4SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ4SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ4SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ4SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ4SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ4SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ4SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ4SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ4SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ4SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ4SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ4SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ4SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ4SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ4SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ4SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ4SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ4SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ4SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ5SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +#define EVTSVT_CPUIRQ5SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ5SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ5SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ5SEL_PUBID_GPIO_COMB 0x00000009U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ6SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +#define EVTSVT_CPUIRQ6SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ6SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ6SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ6SEL_PUBID_LRFD_IRQ0 0x0000000CU + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ7SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +#define EVTSVT_CPUIRQ7SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ7SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ7SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ7SEL_PUBID_LRFD_IRQ1 0x0000000DU + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ8SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +#define EVTSVT_CPUIRQ8SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ8SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ8SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ8SEL_PUBID_DMA_DONE_COMB 0x00000014U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ9SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +#define EVTSVT_CPUIRQ9SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ9SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ9SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ9SEL_PUBID_AES_COMB 0x00000016U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ10SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +#define EVTSVT_CPUIRQ10SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ10SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ10SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ10SEL_PUBID_SPI0_COMB 0x0000000FU + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ11SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVTSVT_CPUIRQ11SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ11SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ11SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ11SEL_PUBID_UART0_COMB 0x00000017U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ12SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +#define EVTSVT_CPUIRQ12SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ12SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ12SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ12SEL_PUBID_I2C0_IRQ 0x00000018U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ13SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +#define EVTSVT_CPUIRQ13SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ13SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ13SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ13SEL_PUBID_LGPT0_COMB 0x00000012U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ14SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +#define EVTSVT_CPUIRQ14SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ14SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ14SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ14SEL_PUBID_LGPT1_COMB 0x00000013U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ15SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +#define EVTSVT_CPUIRQ15SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ15SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ15SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ15SEL_PUBID_ADC_COMB 0x00000010U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ16SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_CPUIRQ16SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ16SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ16SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_CPUIRQ16SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_CPUIRQ16SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_CPUIRQ16SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_CPUIRQ16SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_CPUIRQ16SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_CPUIRQ16SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_CPUIRQ16SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_CPUIRQ16SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_CPUIRQ16SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_CPUIRQ16SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_CPUIRQ16SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_CPUIRQ16SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_CPUIRQ16SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ17SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +#define EVTSVT_CPUIRQ17SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ17SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ17SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ17SEL_PUBID_LGPT2_COMB 0x00000031U + +//***************************************************************************** +// +// Register: EVTSVT_O_CPUIRQ18SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +#define EVTSVT_CPUIRQ18SEL_PUBID_W 6U +#define EVTSVT_CPUIRQ18SEL_PUBID_M 0x0000003FU +#define EVTSVT_CPUIRQ18SEL_PUBID_S 0U +#define EVTSVT_CPUIRQ18SEL_PUBID_LGPT3_COMB 0x00000037U + +//***************************************************************************** +// +// Register: EVTSVT_O_SYSTIMC0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +#define EVTSVT_SYSTIMC0SEL_PUBID_W 6U +#define EVTSVT_SYSTIMC0SEL_PUBID_M 0x0000003FU +#define EVTSVT_SYSTIMC0SEL_PUBID_S 0U +#define EVTSVT_SYSTIMC0SEL_PUBID_AON_RTC_COMB 0x00000004U + +//***************************************************************************** +// +// Register: EVTSVT_O_SYSTIMC1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_SYSTIMC1SEL_PUBID_W 6U +#define EVTSVT_SYSTIMC1SEL_PUBID_M 0x0000003FU +#define EVTSVT_SYSTIMC1SEL_PUBID_S 0U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_SYSTIMC1SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_SYSTIMC1SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_SYSTIMC1SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_SYSTIMC1SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_SYSTIMC1SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_SYSTIMC1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_SYSTIMC1SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_SYSTIMC1SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_SYSTIMC1SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_SYSTIMC1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_SYSTIMC1SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_SYSTIMC1SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_SYSTIMC1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_SYSTIMC2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +#define EVTSVT_SYSTIMC2SEL_PUBID_W 6U +#define EVTSVT_SYSTIMC2SEL_PUBID_M 0x0000003FU +#define EVTSVT_SYSTIMC2SEL_PUBID_S 0U +#define EVTSVT_SYSTIMC2SEL_PUBID_LRFD_EVT0 0x0000002AU + +//***************************************************************************** +// +// Register: EVTSVT_O_SYSTIMC3SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +#define EVTSVT_SYSTIMC3SEL_PUBID_W 6U +#define EVTSVT_SYSTIMC3SEL_PUBID_M 0x0000003FU +#define EVTSVT_SYSTIMC3SEL_PUBID_S 0U +#define EVTSVT_SYSTIMC3SEL_PUBID_LRFD_EVT1 0x0000002BU + +//***************************************************************************** +// +// Register: EVTSVT_O_SYSTIMC4SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +#define EVTSVT_SYSTIMC4SEL_PUBID_W 6U +#define EVTSVT_SYSTIMC4SEL_PUBID_M 0x0000003FU +#define EVTSVT_SYSTIMC4SEL_PUBID_S 0U +#define EVTSVT_SYSTIMC4SEL_PUBID_LRFD_EVT2 0x0000002CU + +//***************************************************************************** +// +// Register: EVTSVT_O_ADCTRGSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_ADCTRGSEL_PUBID_W 6U +#define EVTSVT_ADCTRGSEL_PUBID_M 0x0000003FU +#define EVTSVT_ADCTRGSEL_PUBID_S 0U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_ADCTRGSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_ADCTRGSEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_ADCTRGSEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_ADCTRGSEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_ADCTRGSEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_ADCTRGSEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_ADCTRGSEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_ADCTRGSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_ADCTRGSEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_ADCTRGSEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_ADCTRGSEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_ADCTRGSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_ADCTRGSEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_ADCTRGSEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_ADCTRGSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_ADCTRGSEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_ADCTRGSEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_ADCTRGSEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_ADCTRGSEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_ADCTRGSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPTSYNCSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_LGPTSYNCSEL_PUBID_W 6U +#define EVTSVT_LGPTSYNCSEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPTSYNCSEL_PUBID_S 0U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPTSYNCSEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_LGPTSYNCSEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_LGPTSYNCSEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_LGPTSYNCSEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_LGPTSYNCSEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_LGPTSYNCSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPTSYNCSEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_LGPTSYNCSEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_LGPTSYNCSEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_LGPTSYNCSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPTSYNCSEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_LGPTSYNCSEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_LGPTSYNCSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT0IN0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_LGPT0IN0SEL_PUBID_W 6U +#define EVTSVT_LGPT0IN0SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT0IN0SEL_PUBID_S 0U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT0IN0SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_LGPT0IN0SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_LGPT0IN0SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_LGPT0IN0SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_LGPT0IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_LGPT0IN0SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT0IN0SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_LGPT0IN0SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_LGPT0IN0SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_LGPT0IN0SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT0IN0SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_LGPT0IN0SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_LGPT0IN0SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT0IN1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT0IN1SEL_PUBID_W 6U +#define EVTSVT_LGPT0IN1SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT0IN1SEL_PUBID_S 0U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT0IN1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT0IN1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT0IN1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT0IN2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT0IN2SEL_PUBID_W 6U +#define EVTSVT_LGPT0IN2SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT0IN2SEL_PUBID_S 0U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT0IN2SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT0IN2SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT0IN2SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT0TENSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT0TENSEL_PUBID_W 6U +#define EVTSVT_LGPT0TENSEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT0TENSEL_PUBID_S 0U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT0TENSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT0TENSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT0TENSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT1IN0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_LGPT1IN0SEL_PUBID_W 6U +#define EVTSVT_LGPT1IN0SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT1IN0SEL_PUBID_S 0U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT1IN0SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_LGPT1IN0SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_LGPT1IN0SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_LGPT1IN0SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_LGPT1IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_LGPT1IN0SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT1IN0SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_LGPT1IN0SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_LGPT1IN0SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_LGPT1IN0SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT1IN0SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_LGPT1IN0SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_LGPT1IN0SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT1IN1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT1IN1SEL_PUBID_W 6U +#define EVTSVT_LGPT1IN1SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT1IN1SEL_PUBID_S 0U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT1IN1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT1IN1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT1IN1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT1IN2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT1IN2SEL_PUBID_W 6U +#define EVTSVT_LGPT1IN2SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT1IN2SEL_PUBID_S 0U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT1IN2SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT1IN2SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT1IN2SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT1TENSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT1TENSEL_PUBID_W 6U +#define EVTSVT_LGPT1TENSEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT1TENSEL_PUBID_S 0U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT1TENSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT1TENSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT1TENSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT2IN0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_LGPT2IN0SEL_PUBID_W 6U +#define EVTSVT_LGPT2IN0SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT2IN0SEL_PUBID_S 0U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT2IN0SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_LGPT2IN0SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_LGPT2IN0SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_LGPT2IN0SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_LGPT2IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_LGPT2IN0SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT2IN0SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_LGPT2IN0SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_LGPT2IN0SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_LGPT2IN0SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT2IN0SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_LGPT2IN0SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_LGPT2IN0SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT2IN1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT2IN1SEL_PUBID_W 6U +#define EVTSVT_LGPT2IN1SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT2IN1SEL_PUBID_S 0U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT2IN1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT2IN1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT2IN1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT2IN2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT2IN2SEL_PUBID_W 6U +#define EVTSVT_LGPT2IN2SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT2IN2SEL_PUBID_S 0U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT2IN2SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT2IN2SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT2IN2SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT2TENSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT2TENSEL_PUBID_W 6U +#define EVTSVT_LGPT2TENSEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT2TENSEL_PUBID_S 0U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT2TENSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT2TENSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT2TENSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT3IN0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_LGPT3IN0SEL_PUBID_W 6U +#define EVTSVT_LGPT3IN0SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT3IN0SEL_PUBID_S 0U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT3IN0SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_LGPT3IN0SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_LGPT3IN0SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_LGPT3IN0SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_LGPT3IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_LGPT3IN0SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT3IN0SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_LGPT3IN0SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_LGPT3IN0SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_LGPT3IN0SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT3IN0SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_LGPT3IN0SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_LGPT3IN0SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT3IN1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT3IN1SEL_PUBID_W 6U +#define EVTSVT_LGPT3IN1SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT3IN1SEL_PUBID_S 0U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT3IN1SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT3IN1SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT3IN1SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT3IN2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT3IN2SEL_PUBID_W 6U +#define EVTSVT_LGPT3IN2SEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT3IN2SEL_PUBID_S 0U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT3IN2SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT3IN2SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT3IN2SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LGPT3TENSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// NONE Always inactive +#define EVTSVT_LGPT3TENSEL_PUBID_W 6U +#define EVTSVT_LGPT3TENSEL_PUBID_M 0x0000003FU +#define EVTSVT_LGPT3TENSEL_PUBID_S 0U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_LGPT3TENSEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_LGPT3TENSEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_LGPT3TENSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_LRFDIN0SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +#define EVTSVT_LRFDIN0SEL_PUBID_W 6U +#define EVTSVT_LRFDIN0SEL_PUBID_M 0x0000003FU +#define EVTSVT_LRFDIN0SEL_PUBID_S 0U +#define EVTSVT_LRFDIN0SEL_PUBID_SYSTIM2 0x0000001DU + +//***************************************************************************** +// +// Register: EVTSVT_O_LRFDIN1SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +#define EVTSVT_LRFDIN1SEL_PUBID_W 6U +#define EVTSVT_LRFDIN1SEL_PUBID_M 0x0000003FU +#define EVTSVT_LRFDIN1SEL_PUBID_S 0U +#define EVTSVT_LRFDIN1SEL_PUBID_SYSTIM3 0x0000001EU + +//***************************************************************************** +// +// Register: EVTSVT_O_LRFDIN2SEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read only selection value +// ENUMs: +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +#define EVTSVT_LRFDIN2SEL_PUBID_W 6U +#define EVTSVT_LRFDIN2SEL_PUBID_M 0x0000003FU +#define EVTSVT_LRFDIN2SEL_PUBID_S 0U +#define EVTSVT_LRFDIN2SEL_PUBID_SYSTIM4 0x0000001FU + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH0SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// UART0RXTRG Selects uart0rxtrg as channel source +// SPI0TXTRG Selects spi0txtrg as channel source +#define EVTSVT_DMACH0SEL_IPID_W 3U +#define EVTSVT_DMACH0SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH0SEL_IPID_S 0U +#define EVTSVT_DMACH0SEL_IPID_UART0RXTRG 0x00000007U +#define EVTSVT_DMACH0SEL_IPID_SPI0TXTRG 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH1SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// UART0TXTRG Selects uart0txtrg as channel source +// SPI0RXTRG Selects spi0rxtrg as channel source +#define EVTSVT_DMACH1SEL_IPID_W 3U +#define EVTSVT_DMACH1SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH1SEL_IPID_S 0U +#define EVTSVT_DMACH1SEL_IPID_UART0TXTRG 0x00000006U +#define EVTSVT_DMACH1SEL_IPID_SPI0RXTRG 0x00000001U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH2SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// UART0TXTRG Selects uart0txtrg as channel source +// RSVD Reserved value. Should not be programmed. +#define EVTSVT_DMACH2SEL_IPID_W 3U +#define EVTSVT_DMACH2SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH2SEL_IPID_S 0U +#define EVTSVT_DMACH2SEL_IPID_UART0TXTRG 0x00000006U +#define EVTSVT_DMACH2SEL_IPID_RSVD 0x00000002U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH3SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// UART0RXTRG Selects uart0rxtrg as channel source +// ADC0TRG Selects adc0trg as channel source +#define EVTSVT_DMACH3SEL_IPID_W 3U +#define EVTSVT_DMACH3SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH3SEL_IPID_S 0U +#define EVTSVT_DMACH3SEL_IPID_UART0RXTRG 0x00000007U +#define EVTSVT_DMACH3SEL_IPID_ADC0TRG 0x00000005U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH4SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LAESTRGA Selects laestrga as channel source +// RSVD Reserved value. Should not be programmed. +#define EVTSVT_DMACH4SEL_IPID_W 3U +#define EVTSVT_DMACH4SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH4SEL_IPID_S 0U +#define EVTSVT_DMACH4SEL_IPID_LAESTRGA 0x00000003U +#define EVTSVT_DMACH4SEL_IPID_RSVD 0x00000002U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH5SEL +// +//***************************************************************************** +// Field: [2:0] IPID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ADC0TRG Selects adc0trg as channel source +// LAESTRGB Selects laestrgb as channel source +#define EVTSVT_DMACH5SEL_IPID_W 3U +#define EVTSVT_DMACH5SEL_IPID_M 0x00000007U +#define EVTSVT_DMACH5SEL_IPID_S 0U +#define EVTSVT_DMACH5SEL_IPID_ADC0TRG 0x00000005U +#define EVTSVT_DMACH5SEL_IPID_LAESTRGB 0x00000004U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH6SEL +// +//***************************************************************************** +// Field: [16] EDGDETDIS +// +// Edge detect disable. +// 0: Enabled. +// 1: Disabled +#define EVTSVT_DMACH6SEL_EDGDETDIS 0x00010000U +#define EVTSVT_DMACH6SEL_EDGDETDIS_M 0x00010000U +#define EVTSVT_DMACH6SEL_EDGDETDIS_S 16U + +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_DMACH6SEL_PUBID_W 6U +#define EVTSVT_DMACH6SEL_PUBID_M 0x0000003FU +#define EVTSVT_DMACH6SEL_PUBID_S 0U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_DMACH6SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_DMACH6SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_DMACH6SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_DMACH6SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_DMACH6SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_DMACH6SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_DMACH6SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_DMACH6SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_DMACH6SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_DMACH6SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_DMACH6SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_DMACH6SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_DMACH6SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_DMACH6SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_DMACH6SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_DMACH6SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_DMACH6SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_DMACH6SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_DMACH6SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_DMACH6SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_DMACH6SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_DMACH6SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_DMACH6SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_DMACH6SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_DMACH6SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_DMACH6SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_DMACH6SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_DMACH6SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_DMACH6SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_DMACH6SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_DMACH6SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_DMACH6SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_DMACH6SEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTSVT_O_DMACH7SEL +// +//***************************************************************************** +// Field: [16] EDGDETDIS +// +// Edge detect disable. +// 0: Enabled. +// 1: Disabled +#define EVTSVT_DMACH7SEL_EDGDETDIS 0x00010000U +#define EVTSVT_DMACH7SEL_EDGDETDIS_M 0x00010000U +#define EVTSVT_DMACH7SEL_EDGDETDIS_S 16U + +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// LGPT3_ADC LGPT3 ADC trigger event, controlled by +// LGPT3:ADCTRG setting +// LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA +// setting +// LGPT3_COMB LGPT3 combined interrupt, interrupt flags are +// found here LGPT3:MIS +// LGPT3C2 LGPT3 compare/capture output event 2, controlled +// by LGPT3:C2CFG setting +// LGPT3C1 LGPT3 compare/capture output event 1, controlled +// by LGPT3:C1CFG setting +// LGPT3C0 LGPT3 compare/capture output event 0, controlled +// by LGPT3:C0CFG setting +// LGPT2_ADC LGPT2 ADC trigger event, controlled by +// LGPT2:ADCTRG setting +// LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA +// setting +// LGPT2_COMB LGPT2 combined interrupt, interrupt flags are +// found here LGPT2:MIS +// LGPT2C2 LGPT0 compare/capture output event 2, controlled +// by LGPT2:C2CFG setting +// LGPT2C1 LGPT2 compare/capture output event 1, controlled +// by LGPT2:C1CFG setting +// LGPT2C0 LGPT2 compare/capture output event 0, controlled +// by LGPT2:C0CFG setting +// LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC2 +// LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC1 +// LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by +// LRFDDBELL:SYSTIMOEV.SRC0 +// LGPT1_ADC LGPT1 ADC trigger event, controlled by +// LGPT1:ADCTRG setting +// LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA +// setting +// LGPT1C2 LGPT1 compare/capture output event 2, controlled +// by LGPT1:C2CFG setting +// LGPT1C1 LGPT1 compare/capture output event 1, controlled +// by LGPT1:C1CFG setting +// LGPT1C0 LGPT1 compare/capture output event 0, controlled +// by LGPT1:C0CFG setting +// LGPT0_ADC LGPT0 ADC trigger event, controlled by +// LGPT0:ADCTRG setting +// LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA +// setting +// LGPT0C2 LGPT0 compare/capture output event 2, controlled +// by LGPT0:C2CFG setting +// LGPT0C1 LGPT0 compare/capture output event 1, controlled +// by LGPT0:C1CFG setting +// LGPT0C0 LGPT0 compare/capture output event 0, controlled +// by LGPT0:C0CFG setting +// SYSTIM4 SYSTIM Channel 4 event, event flag is +// SYSTIM:MIS.EVT4 +// SYSTIM3 SYSTIM Channel 3 event, event flag is +// SYSTIM:MIS.EVT3 +// SYSTIM2 SYSTIM Channel 2 event, event flag is +// SYSTIM:MIS.EVT2 +// SYSTIM1 SYSTIM Channel 1 event, event flag is +// SYSTIM:MIS.EVT1 +// SYSTIM0 SYSTIM Channel 0 event, event flag is +// SYSTIM:MIS.EVT0 +// SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK +// signal to SVT clock +// SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT +// I2C0_IRQ Interrupt event from I2C0, interrupt flags can be +// found here I2C0:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// AES_COMB AES accelerator combined interrupt request, +// interrupt flags can be found here AES:MIS +// DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS +// DMA_DONE_COMB DMA combined done interrupt, corresponding flags +// can be found here DMA:REQDONE +// LGPT1_COMB LGPT1 combined interrupt, interrupt flags are +// found here LGPT1:MIS +// LGPT0_COMB LGPT0 combined interrupt, interrupt flags are +// found here LGPT0:MIS +// ADC_EVT ADC general published event, interrupt flags can +// be found here ADC:MIS1 +// ADC_COMB ADC combined interrupt request, interrupt flags +// can be found here ADC:MIS0 +// SPI0_COMB SPI0 combined interrupt request, interrupt flags +// can be found here SPI0:MIS +// LRFD_IRQ2 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS2 +// LRFD_IRQ1 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS1 +// LRFD_IRQ0 LRFD combined event, interrupt flags can be found +// here LRFDDBELL:MIS0 +// FLASH_IRQ NoWrapper Flash interrupt indicating that the +// flash operation has completed, interrupt flags +// can be found here FLASH:MIS +// GPIO_EVT GPIO generic published event, controlled by +// GPIO:EVTCFG +// GPIO_COMB GPIO combined wake up interrupt, interrupt flags +// can be found here GPIO:MIS +// SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are +// found here SYSTIM:MIS +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTSVT_DMACH7SEL_PUBID_W 6U +#define EVTSVT_DMACH7SEL_PUBID_M 0x0000003FU +#define EVTSVT_DMACH7SEL_PUBID_S 0U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3_ADC 0x00000039U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3_DMA 0x00000038U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3_COMB 0x00000037U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3C2 0x00000036U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3C1 0x00000035U +#define EVTSVT_DMACH7SEL_PUBID_LGPT3C0 0x00000034U +#define EVTSVT_DMACH7SEL_PUBID_LGPT2_ADC 0x00000033U +#define EVTSVT_DMACH7SEL_PUBID_LGPT2_DMA 0x00000032U +#define EVTSVT_DMACH7SEL_PUBID_LGPT2_COMB 0x00000031U +#define EVTSVT_DMACH7SEL_PUBID_LGPT2C2 0x00000030U +#define EVTSVT_DMACH7SEL_PUBID_LGPT2C1 0x0000002FU +#define EVTSVT_DMACH7SEL_PUBID_LGPT2C0 0x0000002EU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT2 0x0000002CU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT1 0x0000002BU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT0 0x0000002AU +#define EVTSVT_DMACH7SEL_PUBID_LGPT1_ADC 0x00000029U +#define EVTSVT_DMACH7SEL_PUBID_LGPT1_DMA 0x00000028U +#define EVTSVT_DMACH7SEL_PUBID_LGPT1C2 0x00000027U +#define EVTSVT_DMACH7SEL_PUBID_LGPT1C1 0x00000026U +#define EVTSVT_DMACH7SEL_PUBID_LGPT1C0 0x00000025U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0_ADC 0x00000024U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0_DMA 0x00000023U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0C2 0x00000022U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0C1 0x00000021U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0C0 0x00000020U +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM4 0x0000001FU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM3 0x0000001EU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM2 0x0000001DU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM1 0x0000001CU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM0 0x0000001BU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM_LT 0x0000001AU +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM_HB 0x00000019U +#define EVTSVT_DMACH7SEL_PUBID_I2C0_IRQ 0x00000018U +#define EVTSVT_DMACH7SEL_PUBID_UART0_COMB 0x00000017U +#define EVTSVT_DMACH7SEL_PUBID_AES_COMB 0x00000016U +#define EVTSVT_DMACH7SEL_PUBID_DMA_ERR 0x00000015U +#define EVTSVT_DMACH7SEL_PUBID_DMA_DONE_COMB 0x00000014U +#define EVTSVT_DMACH7SEL_PUBID_LGPT1_COMB 0x00000013U +#define EVTSVT_DMACH7SEL_PUBID_LGPT0_COMB 0x00000012U +#define EVTSVT_DMACH7SEL_PUBID_ADC_EVT 0x00000011U +#define EVTSVT_DMACH7SEL_PUBID_ADC_COMB 0x00000010U +#define EVTSVT_DMACH7SEL_PUBID_SPI0_COMB 0x0000000FU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ2 0x0000000EU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ1 0x0000000DU +#define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ0 0x0000000CU +#define EVTSVT_DMACH7SEL_PUBID_FLASH_IRQ 0x0000000BU +#define EVTSVT_DMACH7SEL_PUBID_GPIO_EVT 0x0000000AU +#define EVTSVT_DMACH7SEL_PUBID_GPIO_COMB 0x00000009U +#define EVTSVT_DMACH7SEL_PUBID_SYSTIM_COMB 0x00000008U +#define EVTSVT_DMACH7SEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTSVT_DMACH7SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTSVT_DMACH7SEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTSVT_DMACH7SEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTSVT_DMACH7SEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTSVT_DMACH7SEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTSVT_DMACH7SEL_PUBID_NONE 0x00000000U + + +#endif // __EVTSVT__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtull.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtull.h new file mode 100644 index 00000000..61bb093f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_evtull.h @@ -0,0 +1,291 @@ +/****************************************************************************** +* Filename: hw_evtull_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_EVTULL_H__ +#define __HW_EVTULL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVTULL component +// +//***************************************************************************** +// Description +#define EVTULL_O_DESC 0x00000000U + +// Extended Description +#define EVTULL_O_DESCEX 0x00000004U + +// Digital test bus control register +#define EVTULL_O_DTB 0x00000064U + +// Output Selection for CPU NMI Exception +#define EVTULL_O_NMISEL 0x00000400U + +// Output Selection for RTCCPT +#define EVTULL_O_RTCCPTSEL 0x00000404U + +// WAKEUP Mask +#define EVTULL_O_WKUPMASK 0x00000800U + +//***************************************************************************** +// +// Register: EVTULL_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define EVTULL_DESC_MODID_W 16U +#define EVTULL_DESC_MODID_M 0xFFFF0000U +#define EVTULL_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// 0: Standard IP MMRs do not exist +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define EVTULL_DESC_STDIPOFF_W 4U +#define EVTULL_DESC_STDIPOFF_M 0x0000F000U +#define EVTULL_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define EVTULL_DESC_INSTIDX_W 4U +#define EVTULL_DESC_INSTIDX_M 0x00000F00U +#define EVTULL_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define EVTULL_DESC_MAJREV_W 4U +#define EVTULL_DESC_MAJREV_M 0x000000F0U +#define EVTULL_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define EVTULL_DESC_MINREV_W 4U +#define EVTULL_DESC_MINREV_M 0x0000000FU +#define EVTULL_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: EVTULL_O_DESCEX +// +//***************************************************************************** +// Field: [31:22] IDMA +// +// Number of DMA input channels +#define EVTULL_DESCEX_IDMA_W 10U +#define EVTULL_DESCEX_IDMA_M 0xFFC00000U +#define EVTULL_DESCEX_IDMA_S 22U + +// Field: [21:17] NDMA +// +// Number of DMA output channels +#define EVTULL_DESCEX_NDMA_W 5U +#define EVTULL_DESCEX_NDMA_M 0x003E0000U +#define EVTULL_DESCEX_NDMA_S 17U + +// Field: [16] PD +// +// Power Domain. +// 0 : SVT +// 1 : ULL +#define EVTULL_DESCEX_PD 0x00010000U +#define EVTULL_DESCEX_PD_M 0x00010000U +#define EVTULL_DESCEX_PD_S 16U + +// Field: [15:8] NSUB +// +// Number of Subscribers +#define EVTULL_DESCEX_NSUB_W 8U +#define EVTULL_DESCEX_NSUB_M 0x0000FF00U +#define EVTULL_DESCEX_NSUB_S 8U + +// Field: [7:0] NPUB +// +// Number of Publishers +#define EVTULL_DESCEX_NPUB_W 8U +#define EVTULL_DESCEX_NPUB_M 0x000000FFU +#define EVTULL_DESCEX_NPUB_S 0U + +//***************************************************************************** +// +// Register: EVTULL_O_DTB +// +//***************************************************************************** +// Field: [0] SEL +// +// Digital test bus selection mux control +// +// Non-zero select values output a 16 bit selected group of signals +// per value. +// ENUMs: +// DIS All 16 observation signals are set to zero. +#define EVTULL_DTB_SEL 0x00000001U +#define EVTULL_DTB_SEL_M 0x00000001U +#define EVTULL_DTB_SEL_S 0U +#define EVTULL_DTB_SEL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: EVTULL_O_NMISEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTULL_NMISEL_PUBID_W 6U +#define EVTULL_NMISEL_PUBID_M 0x0000003FU +#define EVTULL_NMISEL_PUBID_S 0U +#define EVTULL_NMISEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTULL_NMISEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTULL_NMISEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTULL_NMISEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTULL_NMISEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTULL_NMISEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTULL_NMISEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTULL_O_RTCCPTSEL +// +//***************************************************************************** +// Field: [5:0] PUBID +// +// Read/write selection value. +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// AON_IOC_COMB IOC synchronous combined event, controlled by +// IOC:EVTCFG +// AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG +// AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be +// found here DBGSS:MIS +// AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting +// AON_CKM_COMB CKMD combined interrupt request, interrupt flags +// can be found here CKMD:MIS +// AON_PMU_COMB PMU combined interrupt request for BATMON, +// interrupt flags can be found here PMUD:EVENT +// NONE Always inactive +#define EVTULL_RTCCPTSEL_PUBID_W 6U +#define EVTULL_RTCCPTSEL_PUBID_M 0x0000003FU +#define EVTULL_RTCCPTSEL_PUBID_S 0U +#define EVTULL_RTCCPTSEL_PUBID_AON_IOC_COMB 0x00000007U +#define EVTULL_RTCCPTSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U +#define EVTULL_RTCCPTSEL_PUBID_AON_DBG_COMB 0x00000005U +#define EVTULL_RTCCPTSEL_PUBID_AON_RTC_COMB 0x00000004U +#define EVTULL_RTCCPTSEL_PUBID_AON_CKM_COMB 0x00000003U +#define EVTULL_RTCCPTSEL_PUBID_AON_PMU_COMB 0x00000002U +#define EVTULL_RTCCPTSEL_PUBID_NONE 0x00000000U + +//***************************************************************************** +// +// Register: EVTULL_O_WKUPMASK +// +//***************************************************************************** +// Field: [7] AON_IOC_COMB +// +// Wake-up mask for AON_IOC_COMB. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_IOC_COMB 0x00000080U +#define EVTULL_WKUPMASK_AON_IOC_COMB_M 0x00000080U +#define EVTULL_WKUPMASK_AON_IOC_COMB_S 7U + +// Field: [6] AON_LPMCMP_IRQ +// +// Wake-up mask for AON_LPMCMP_IRQ. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_LPMCMP_IRQ 0x00000040U +#define EVTULL_WKUPMASK_AON_LPMCMP_IRQ_M 0x00000040U +#define EVTULL_WKUPMASK_AON_LPMCMP_IRQ_S 6U + +// Field: [5] AON_DBG_COMB +// +// Wake-up mask for AON_DBG_COMB. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_DBG_COMB 0x00000020U +#define EVTULL_WKUPMASK_AON_DBG_COMB_M 0x00000020U +#define EVTULL_WKUPMASK_AON_DBG_COMB_S 5U + +// Field: [4] AON_RTC_COMB +// +// Wake-up mask for AON_RTC_COMB. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_RTC_COMB 0x00000010U +#define EVTULL_WKUPMASK_AON_RTC_COMB_M 0x00000010U +#define EVTULL_WKUPMASK_AON_RTC_COMB_S 4U + +// Field: [3] AON_CKM_COMB +// +// Wake-up mask for AON_CKM_COMB. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_CKM_COMB 0x00000008U +#define EVTULL_WKUPMASK_AON_CKM_COMB_M 0x00000008U +#define EVTULL_WKUPMASK_AON_CKM_COMB_S 3U + +// Field: [2] AON_PMU_COMB +// +// Wake-up mask for AON_PMU_COMB. +// 0 - Wakeup Disabled +// 1 - Wakeup Enabled +#define EVTULL_WKUPMASK_AON_PMU_COMB 0x00000004U +#define EVTULL_WKUPMASK_AON_PMU_COMB_M 0x00000004U +#define EVTULL_WKUPMASK_AON_PMU_COMB_S 2U + + +#endif // __EVTULL__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h new file mode 100644 index 00000000..aea73249 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h @@ -0,0 +1,653 @@ +/****************************************************************************** +* Copyright (c) 2021-2023 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +****************************************************************************** +* \file hw_fcfg.h +* +* \brief Factory Configuration (FCFG) header file. +******************************************************************************/ +#ifndef __HW_FCFG_H__ +#define __HW_FCFG_H__ + +#include +#include "hw_device.h" +#include "hw_ccfg.h" + +// *** Define datatypes used in FCFG *** + +// \note Struct written to avoid automatic padding. Packing directives not needed +// \note Bitfields: lsb->msb, packing of similar base types, no word boundary crossing +typedef struct { + // Critical Trim (done early in boot sequence or requires special handling) + struct { // [0]: length 64 B + // SRAM repair information (* hardcoded into ASM to be at offset 0, do not move! *) + struct { // length 28B + // Value SRAMREP_MAGICWORD tells SRAM repair in ASM that criticalTrim is valid + uint32_t magicWord; + // Number of bits to shift through SRAM repair chain (first 4b are read back) + uint8_t numBits; + // Data to shift through SRAM repair chain (MSB first, max 184b) + uint8_t data[23]; + } sramRepair; + // HFOSC trim (CKMD.TRIM0) + struct { // length: 4B + union { + uint16_t val16; + struct { + uint16_t coarse : 5; + uint16_t cap : 4; + uint16_t bias : 5; + uint16_t res0 : 2; + }; + } initial; + union { + uint16_t val16; + struct { + uint16_t coarse : 5; + uint16_t cap : 4; + uint16_t bias : 5; + uint16_t res0 : 2; + }; + } final; + } hfoscTrim; + // Flash trims + struct { // length 16 B + // Flash 1T wait states (default: 2 WS trimmed) + struct { // length: 2B + uint8_t initial; + uint8_t final; + } flws1t; + // Flash 2T wait states (default: 5 WS untrimmed, 2 WS trimmed) + struct { // length: 2B + uint8_t initial; + uint8_t final; + } flws2t; + uint32_t ptrmc0; + uint32_t b0trmc1; + uint32_t b0trmc0; + } flashTrim; + // PMU trim: GLDO/BIAS/BGAP/DigLDO + struct { // length 8B + union { + uint32_t val32; + struct { + uint32_t vref : 4; + uint32_t vbg : 6; + uint32_t vddsbod : 5; + uint32_t bgtrimen : 1; // Latch vddsbod (0 initially, set to 1 in later trim steps) + uint32_t iref : 5; + uint32_t tsense : 2; + uint32_t spare : 1; + uint32_t vddrokhyst : 1; + uint32_t dissahyst : 1; + uint32_t gldocompdis: 1; + uint32_t gldodisana : 1; + uint32_t res0 : 4; + }; + } timmute0; + union { + uint32_t val32; + struct { + uint32_t vddr : 5; + uint32_t vddrsl : 5; + uint32_t iptat : 2; + uint32_t bod : 4; + uint32_t udig : 4; + uint32_t dig : 4; + uint32_t coarse : 4; + uint32_t delta : 3; + uint32_t res0 : 1; + }; + } timmute1; + } pmuTrim; + // Systick reload value that determines minimum time for each trim step in clock cycles + uint8_t sysTickRvrTrimStep; + // Flag to control whether BOD reset is disabled during VDDR/BGAP trim stepping + uint8_t disableBodDuringTrim : 1; + // Settling delay after VDDR/BGAP = enableBodDelaySteps*sysTickRvrTrimStep+1 clock cycles + uint8_t enableBodDelaySteps : 5; + uint8_t res0 : 2; + // Flash verify waitstates + uint8_t flashVerifyWaitStates : 4; + uint8_t res2 : 4; + // Padding to get record size to multiple of 16 B + uint8_t res1[1]; + // CRC32 integrity check critical trim + uint32_t crc32; + } criticalTrim; + + // Paperspin options [64]: length 8 B + // Defines peripheral/feature availability and accessible memory + uint32_t hwOpts[2]; + + + // Device permissions [72]: length 4 B + // This is maximally-restrictive combined with similar field in CCFG + struct { + #define FCFG_PERMISSION_ALLOW 0xA + #define FCFG_PERMISSION_FORBID 0x0 + // (all other value other than ALLOW are interpreted as FORBID) + uint32_t allowReturnToFactory : 4; + uint32_t allowFakeStby : 4; + uint32_t allowToolsClientMode : 4; + uint32_t allowChipErase : 4; + uint32_t allowFlashProgram : 4; + uint32_t allowFlashVerify : 4; + uint32_t allowEnergyTrace : 4; + uint32_t allowDebugPort : 4; + } permissions; + + + // Miscellaneous fields + // [76]: length 4B + struct { + // SACI timeout is infinite when 0, else (2^saciTimeoutExp)*64 ms + // Ccfg timeout applied instead if CCfg.saciTimeoutOverride==1 + uint32_t saciTimeoutExp : 3; + #define XCFG_MISC_SACITOEXP_8SEC 7 + #define XCFG_MISC_SACITOEXP_1SEC 4 + #define XCFG_MISC_SACITOEXP_INFINITE 0 + uint32_t res0 : 29; + } misc; + + + // Device information + struct { // [80]: length 48B + // 64b device-unique UUID (non-sequential across parts) + uint8_t uuid[8]; + // 48b device-unique BLE address + uint8_t bleAddr[6]; + // Padding + uint8_t res0[2]; + // 64b device-unique IEEE MAC address + uint8_t macAddr[8]; + // 128b die identifier (lot #, wafer #, die X/Y, date, etc) + uint8_t dieId[16]; + // Padding (previously devId but this HW-defined value is now readable through an MMR) + uint32_t res1; + // 32b PARTID (Part/Variant/majRev/minorRev) + union { + uint32_t val32; + struct { + // Random bit pattern to uniquely identify part (with devId) + uint32_t part : 16; + // Random bit pattern to uniquely identify package/memory variant + uint32_t variant : 8; + // Minor revision for orderable part (starts at 0) + uint32_t minorRev : 4; + // Major revision for orderable part: PCB/SW change (starts at 1) + uint32_t majorRev : 3; + // 0: partId not yet valid; 1: partId valid + uint32_t partIdValid : 1; + }; + } partId; + } deviceInfo; + + + // Flash protection [128]: length 16 B + // This is maximally-restrictive combined with similar field in CCFG + struct { + struct { + // Sticky-0 bits written to VIMS.WEPRA (sectors 0-31, 1/bit) + uint32_t mainSectors0_31; + union { + // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) + uint32_t mainSectors32_255; + // Dummy symbol to allow code to remain the same across devices + uint32_t mainSectors256_511; + }; + // Sticky-0 bit written to VIMS.WEPRAUX + union { + uint32_t auxSectors; + struct { + uint32_t ccfgSector : 1; + uint32_t fcfgSector : 1; + uint32_t engrSector : 1; + uint32_t res1 : 29; + }; + }; + } writeEraseProt; + uint32_t res; + } flashProt; + + // ******************************************************* + // *** General Trims (copy list format) *** + // ******************************************************* + // [144]: (152 words in 128b flash, 40 words in 64b flash) + uint32_t generalTrims[FCFG_GENERALTRIMS_SIZE]; + // Simple macros to assist in initializing copy lists + // NOTE: Addresses to CPYLIST_CPY must fulfill (a & 0x0FF00003) == 3. + // The memory map ensures this for SRAM and peripherals. + // There is no check as ELF only supports {symbol + const offset} + #define CPYLST_EOL 0 + #define CPYLST_NOP 0x10000000 + #define CPYLST_WAIT(x) ( 0x10000000 + (((x)<<2)&0x000FFFFC) ) + #define CPYLST_CPY(a, n) ( ((uint32_t)(a)) + (((n)<<20)&0x0FF00000) ) + #define CPYLST_CPYFULLADDR(a) (((uint32_t)(a)) + 1) + #define CPYLST_JUMP(a) (((uint32_t)(a)) + 2) + #define CPYLST_CALL(a) (((uint32_t)(a)) + 3) + + + // ******************************************************* + // *** Extended Application Trims *** + // ******************************************************* + // Extended application trims. + // [End-272]: length 64B + struct appTrimsExt_struct { + struct appTrimsExtCc23x0r5_s { // length: 64B + // Unused space + uint8_t res[40]; + struct { // length: 4B + // Measured value on 1.8V for ODP core NMOS IDSAT + uint16_t odpNmos; + // Measured value on 1.8V for ODP core PMOS IDSAT + uint16_t odpPmos; + } odpVal1p8v; + struct { // length: 4B + // Measured value on 1.2V for ODP core NMOS IDSAT + uint16_t odpNmos; + // Measured value on 1.2V for ODP core PMOS IDSAT + uint16_t odpPmos; + } odpVal1p2v; + // Value for the FWT MP production program revision + struct { // length: 4B + uint32_t revBranch : 4; + uint32_t revPatch : 8; + uint32_t revMinor : 8; + uint32_t revMajor : 6; + uint32_t variantCode : 6; + } tfwMp; + // Value for the FWT FT production program revision + struct { // length: 4B + uint32_t revBranch : 4; + uint32_t revPatch : 8; + uint32_t revMinor : 8; + uint32_t revMajor : 6; + uint32_t variantCode : 6; + } tfwFt; + // Value for the MP production test program revision + struct { // length 4B + uint32_t mp1Rev : 8; + uint32_t mp2Rev : 8; + uint32_t mp3Rev : 8; + uint32_t res : 8; + } ateMpRev; + // Value for the FT production test program revision + struct { // length 4B + uint32_t ft1Rev : 8; + uint32_t ft2Rev : 8; + uint32_t ft3Rev : 8; + uint32_t trimState : 8; + } ateFtRev; + } cc23x0r5; + } appTrimsExt; + + + // ******************************************************* + // *** Application Trims *** + // ******************************************************* + // Application trims (individual fields are not referenced + // by ROM). Note that the Application Trims section is + // copied to SRAM by the SACI command SC_MODE_REQ_TOOLS_CLIENT. + // [End-208]: length 128B for non BLE High devices + // [End-256]: length 128B for BLE High devices + struct appTrims_struct { + // Revision of appTrims (defines layout) + uint8_t revision; + // Offset range to copy to SRAM in tools client mode to appTrims-n*16B. + uint8_t nToolsClientOffset; + // Pad to 32b alignment + uint8_t res[2]; + + // Different device-specific application trim records + struct appTrimsCc23x0r5_s { // length: 124B + // Trim value for LRFDRFE:PA0.TRIM + struct { // length: 2B + uint16_t trim : 5; + uint16_t zero : 11; + } pa0; + // Trim value for LRFDRFE:ATSTREFH.IREFTRIM + struct { // length: 2B + uint16_t zero0 : 10; + uint16_t irefTrim : 5; + uint16_t zero1 : 1; + } atstRefH; + // Trim value for LRFDRFE:LNA.TRIM + struct { // length: 2B + uint16_t zero0 : 4; + uint16_t trim : 4; + uint16_t zero1 : 8; + } lna; + // Trim value for LRFDRFE:IFAMPRFLDO.TRIM + struct { // length: 2B + uint16_t zero : 9; + uint16_t trim : 7; + } ifampRfLdo; + // Trim value for LRFDRFE:DIVLDO.VOUTTRIM + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t voutTrim : 7; + uint16_t zero1 : 1; + } divLdo; + // Trim value for LRFDRFE:TDCLDO.VOUTTRIM + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t voutTrim : 7; + uint16_t zero1 : 1; + } tdcLdo; + // Trim values for LRFDRFE:DCOLDO0 + struct { // length: 2B + uint16_t zero0 : 4; + uint16_t firstTrim : 4; + uint16_t secondTrim : 6; + uint16_t zero1 : 2; + } dcoLdo0; + // Trim value for LRFDRFE:IFADCALDO.TRIMOUT + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t trimout : 6; + uint16_t zero1 : 2; + } ifadcAldo; + // Trim value for LRFDRFE:IFADCDLDO.TRIMOUT + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t trimout : 6; + uint16_t zero1 : 2; + } ifadcDldo; + // Trim value for LRFDRFE:DCO.TAILRESTRIM + struct { // length: 2B + uint16_t zero0 : 3; + uint16_t tailresTrim : 4; + uint16_t zero1 : 9; + } dco; + // Trim value for LRFDRFE:IFADCQUANT.QUANTTHR + struct { // length: 2B + uint16_t quantThr : 3; + uint16_t zero : 13; + } ifadcQuant; + // Trim values for LRFDRFE:IFADC0 + struct { // length: 2B + uint16_t zero0 : 2; + uint16_t aafcap : 2; + uint16_t int2Adj : 4; + uint16_t zero1 : 2; + uint16_t ditheren : 2; + uint16_t dithertrim : 3; + uint16_t zero2 : 1; + } ifadc0; + // Trim value for LRFDRFE:IFADC1.TRIM + struct { // length: 2B + uint16_t zero0 : 9; + uint16_t trim : 6; + uint16_t nrz : 1; + } ifadc1; + // Trim values for LRFDRFE:IFADCLF + struct { // length: 2B + uint16_t int3 : 4; + uint16_t ff1 : 4; + uint16_t ff2 : 4; + uint16_t ff3 : 4; + } ifadclf; + // Trim value for LRFDRFE:IFADCQUANT.QUANTTHR high-bandwidth + struct { // length: 2B + uint16_t quantThr : 3; + uint16_t zero : 13; + } ifadcQuantWbw; + // Trim values for LRFDRFE:IFADC0 high-bandwidth + struct { // length: 2B + uint16_t zero0 : 2; + uint16_t aafcap : 2; + uint16_t int2Adj : 4; + uint16_t zero1 : 2; + uint16_t ditheren : 2; + uint16_t dithertrim : 3; + uint16_t zero2 : 1; + } ifadc0Wbw; + // Trim value for LRFDRFE:IFADC1.TRIM high-bandwidth + struct { // length: 2B + uint16_t zero0 : 9; + uint16_t trim : 6; + uint16_t nrz : 1; + } ifadc1Wbw; + // Trim values for LRFDRFE:IFADCLF high-bandwidth + struct { // length: 2B + uint16_t int3 : 4; + uint16_t ff1 : 4; + uint16_t ff2 : 4; + uint16_t ff3 : 4; + } ifadclfWbw; + // Trim values for RTRIM, synth LDO and HFXT Peak Detector + struct { + // RTRIM Min Offset. + // Value represents the positive offset in RTRIM at -40 vs 25C. The calculated trim + // adjustment will be added to nominal trim when temperature crosses -40 +TTHRL x 2^k. + uint32_t rtrimMinOffset : 2; + // RTRIM Max Offset. + // Value represents the positive offset in RTRIM at 125C vs 25C. The calculated trim adjustment + // will be added to nominal trim when temperature crosses 125 - TTHRH x 2^k. + uint32_t rtrimMaxOffset : 2; + // DIVLDO Min Offset. + // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at -40 as + // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature + // crosses -40 + TTHRL x 2^k. + uint32_t divLdoMinOffset : 2; + // DIVLDO Max Offset. + // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at 125C as + // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature + // crosses 125 - TTHRH x 2^k. + uint32_t divLdoMaxOffset : 2; + // TDCLDO Min Offset. + // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at -40 as + // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature + // crosses -40 + TTHRL x 2^k. + uint32_t tdcLdoMinOffset : 2; + // TDCLDO Max Offset. + // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at 125C as + // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature + // crosses 125 - TTHRH x 2^k. + uint32_t tdcLdoMaxOffset : 2; + // Temperature Threshold Low. + // Value sets the temperature threshold for correction as -40C + x * 2^k, where k is TBD. + // At temperatures below the threshold, a nominal trim value will be adjusted. + uint32_t tThrl : 2; + // Temperature Threshold High. + // Value sets the temperature threshold for correction as -40C + x * 2^k, where k is TBD. + // At temperatures above the threshold, a nominal trim value will be adjusted. + uint32_t tThrh : 2; + // Peak detector variation measured in production + uint32_t hfxtPdError : 8; + // Reserved + uint32_t res : 8; + } lrfdrfeExtTrim1; + // Trim values for adjusting AGC and RSSI + struct { + // RSSI offset temperature compensation. + // The COMP is added to RSSIOFFSET before programming RSSI offset to HW register. + // Use for all PHYs. + // Max compensation at 125C is -6 to +5.5 dB. Max compensation at -40C is -3.5 to 4 dB. + // Add to LRFDRFE:RSSIOFFSET. + // Formula: COMP = (temp-25)*signed(RSSITCOMP)/128 + uint32_t rssiTcomp : 4; + // AGC magn target temperature compensation. + // The COMP is added to MAGN target before programming HW register (SPARE). + // Use for PHYs using the generic AGC. + // Max compensation at 125C is -6 to +5.5 dB. Max compensation at -40C is -3.5 to 4 dB. + // Add to LRFDRFE:SPARE. + // Formula: COMP = (temp-25)*signed(magnTcomp)/128 + uint32_t magnTcomp : 4; + // Fab dependent offset to add to AGC magnitude target (SPARE). + // Use for PHYs using the generic AGC. Add to LRFDRFE:SPARE. + // Formula: COMP = signed(magnOffset) + uint32_t magnOffset : 4; + // Reserved + uint32_t rfu : 4; + // AGC threshold temperature compensation. + // The COMP is added to AGC threshold before programming HW register (SPARE). + // Use for PHYs with fast AGC (high gain / low gain type). + // Formula: COMP = (temp-25)*signed(agcThrTcomp)/128 + uint32_t agcThrTcomp : 4; + // Fab dependent offset to add to AGC threshold target. + // Use for PHYs with fast AGC (high gain / low gain type). + // Add to LRFDRFE:SPARE. + // Formula: COMP = signed(agcThrOffset) + uint32_t agcThrOffset : 4; + // Adjust the low gain setting with this signed number. + // Use for PHYs with fast AGC (high gain / low gain type). + // Add to LRFDRFE:SPARE0[3:0], check for overflow/underflow. + // Formula: COMP = signed(lowGainOffset) + uint32_t lowGainOffset : 4; + // Adjust the high gain setting with this signed number. + // Use for PHYs with fast AGC (high gain / low gain type). + // Add to LRFDRFE:SPARE0[7:4], check for overflow/underflow. + // Formula: COMP = signed(lowGainOffset) + uint32_t highGainOffset : 4; + } lrfdrfeExtTrim0; + // Trim values for front end 0 + struct { // length: 2B + // RSSI measured for front end 0 in production test. + // Value is read by RF Core FW during RF Core initialization + uint16_t offset : 8; + uint16_t trimCompleteN : 1; + uint16_t zero : 7; + } fend0Rssi; + // Trim values for synth divider 0 + struct { // length: 2B + // Trim value for IQ mismatch compensation. + // Value is read by RF Core FW during RF Core initialization + uint16_t iqmc : 16; + } syntDiv0; + // Unused space + uint8_t res1[2]; + // Trim values for LRFDRFE:IFAMP.AAFCAP + struct { // length: 1B + uint8_t zero : 4; + uint8_t aafcap : 4; + } ifamprfldo; + // Trim values for LRFDRFE:IFAMP.AAFCAP high-bandwidth + struct { // length: 1B + uint8_t zero : 4; + uint8_t aafcap : 4; + } ifamprfldoWbw; + // Trim value for AUX Diode voltage at 30C + struct { // length: 4B + uint16_t auxDiodeGnd; + uint16_t auxDiodeVoltage; + } auxDiodeCal30C; + // Trim value for AUX Diode voltage at 125C + struct { // length: 4B + uint16_t auxDiodeGnd; + uint16_t auxDiodeVoltage; + } auxDiodeCal125C; + // Values for LFOSC performance + struct { // length: 4B + uint32_t ppmRtn : 8; + uint32_t ppmTempMid : 8; + uint32_t ppmTempExt : 8; + uint32_t res : 8; + } lfOscParams; + // Unused space + uint8_t res2[16]; + // ADC offset for four modes + struct { // length: 4B + uint32_t adcOffsetVdds : 8; + uint32_t adcOffsetExtref : 8; + uint32_t adcOffsetIntref2P5V : 8; + uint32_t adcOffsetIntref1P4V : 8; + } adcOffset; + // ADC gain for VDDS and Extref modes + struct { // length: 4B + uint32_t adcGainVdds : 16; + uint32_t adcGainExtref : 16; + } adcGainWord0; + // ADC gain for Intref 2.5V and Intref 1.4V modes + struct { // length: 4B + uint32_t adcGainIntref2P5V : 16; + uint32_t adcGainIntref1P4V : 16; + } adcGainWord1; + // Unused space + uint8_t res3[28]; + // Measured I2V resistor error values + struct { // length: 4B + uint32_t i2v20k : 8; + uint32_t i2v50k : 8; + uint32_t i2v100k : 8; + uint32_t i2v1m : 8; + } i2vCompact; + } cc23x0r5; + } appTrims; + + // Bootloader configuration + struct { // [End-80]: length 8B + // Pointer to default bootloader VTOR table + void *pBldrVtor; + #define XCFG_BC_PBLDR_FORBID ((void*)0xFFFFFFFC) + #define XCFG_BC_PBLDR_UNDEF ((void*)0xFFFFFFFF) + #define FCFG_BC_PBLDR_VALID(x) ((x) < XCFG_BC_PBLDR_FORBID) + // Parameter passed to bootloader + union { + uint32_t val32; + // Serial ROM bootloader parameters (defined in CCFG.h) + serialRomBldrParam_t params; + } bldrParam; + } bootCfg; + + + // Reserved/padding to get 16 B alignment + // [End-72] length: 4B + uint32_t res1; + + + // CRC across hwOpts through res1 (after criticalTrim to here) + // [End-68]: length 4B + uint32_t crc32; + + // Lifecycle management + struct { // [End-64]: length 16B + // 128b field updated incrementally (32b at a time) as lifecycle increments + uint32_t states[4]; + // SET => 32b word has a value within a Hamming distance <=1 of (FCFG_SET32) + // UNSET => all others (2T erased state is random) + #define FCFG_SET32 0x41008002 + #define FCFG_UNSET32 0x41FFFFFF + // Lifecycle BDAY1ST: FA unlock key integrity check fails + // Other lifecycles: FA unlock key integrity check OK + states words as below + #define FCFG_LC_TESTPT {FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32} + #define FCFG_LC_TESTFT {FCFG_SET32, FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32} + #define FCFG_LC_ENGRDEV {FCFG_SET32, FCFG_SET32, FCFG_UNSET32, FCFG_UNSET32} + #define FCFG_LC_PRODDEV {FCFG_SET32, FCFG_SET32, FCFG_SET32, FCFG_UNSET32} + #define FCFG_LC_RETEST {FCFG_SET32, FCFG_SET32, FCFG_SET32, FCFG_SET32} + } lifecycle; +} fcfg_t; + +/* \brief Define to access FCFG struct pointer from application code. + * This definition can be used to access member elements with the `->` + * operator. + */ +#define fcfg ((const fcfg_t *)FCFG_BASE) + +#endif // __HW_FCFG_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_flash.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_flash.h new file mode 100644 index 00000000..2e3905d0 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_flash.h @@ -0,0 +1,1204 @@ +/****************************************************************************** +* Filename: hw_flash_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// Interrupt Mask Register +#define FLASH_O_IMASK 0x00000028U + +// Raw Interrupt Status Register +#define FLASH_O_RIS 0x00000030U + +// Masked Interrupt Status Register +#define FLASH_O_MIS 0x00000038U + +// Interrupt Set Register +#define FLASH_O_ISET 0x00000040U + +// Interrupt Clear Register +#define FLASH_O_ICLR 0x00000048U + +// Hardware Version Description Register +#define FLASH_O_DESC 0x000000FCU + +// Command Execute Register +#define FLASH_O_CMDEXEC 0x00000100U + +// Command Type Register +#define FLASH_O_CMDTYPE 0x00000104U + +// Command Control Register +#define FLASH_O_CMDCTL 0x00000108U + +// Command Address Register +#define FLASH_O_CMDADDR 0x00000120U + +// Command Program Byte Enable Register +#define FLASH_O_CMDBYTEN 0x00000124U + +// Command Data Register 0 +#define FLASH_O_CMDDATA0 0x00000130U + +// Command Data Register 1 +#define FLASH_O_CMDDATA1 0x00000134U + +// Command Data Register 2 +#define FLASH_O_CMDDATA2 0x00000138U + +// Command Data Register Bits 127:96 +#define FLASH_O_CMDDATA3 0x0000013CU + +// Command Write Erase Protect A Register +#define FLASH_O_CMDWEPROTA 0x000001D0U + +// Command Write Erase Protect B Register +#define FLASH_O_CMDWEPROTB 0x000001D4U + +// Command Write Erase Protect Non-Main Register +#define FLASH_O_CMDWEPROTNM 0x00000210U + +// Command Write Erase Protect Trim Register +#define FLASH_O_CMDWEPROTTR 0x00000214U + +// Command Write Erase Protect Engr Register +#define FLASH_O_CMDWEPROTEN 0x00000218U + +// Command Configuration Register +#define FLASH_O_CFGCMD 0x000003B0U + +// Pulse Counter Configuration Register +#define FLASH_O_CFGPCNT 0x000003B4U + +// Command Status Register +#define FLASH_O_STATCMD 0x000003D0U + +// Address Status Register +#define FLASH_O_STATADDR 0x000003D4U + +// Pulse Count Status Register +#define FLASH_O_STATPCNT 0x000003D8U + +// Mode Status Register +#define FLASH_O_STATMODE 0x000003DCU + +// Global Information Register 0 +#define FLASH_O_GBLINFO0 0x000003F0U + +// Global Information Register 1 +#define FLASH_O_GBLINFO1 0x000003F4U + +// Global Information Register 2 +#define FLASH_O_GBLINFO2 0x000003F8U + +// Bank Information Register 0 for Bank 0 +#define FLASH_O_BANK0INFO0 0x00000400U + +// Bank Information Register 1 for Bank 0 +#define FLASH_O_BANK0INFO1 0x00000404U + +//***************************************************************************** +// +// Register: FLASH_O_IMASK +// +//***************************************************************************** +// Field: [0] DONE +// +// Interrupt mask for DONE: +// 0: Interrupt is disabled in MIS register +// 1: Interrupt is enabled in MIS register +// ENUMs: +// ENABLED Interrupt will request an interrupt service +// routine and corresponding bit in IPSTANDARD.MIS +// will be set +// DISABLED Interrupt is masked out +#define FLASH_IMASK_DONE 0x00000001U +#define FLASH_IMASK_DONE_M 0x00000001U +#define FLASH_IMASK_DONE_S 0U +#define FLASH_IMASK_DONE_ENABLED 0x00000001U +#define FLASH_IMASK_DONE_DISABLED 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_RIS +// +//***************************************************************************** +// Field: [0] DONE +// +// Flash wrapper operation completed. +// This interrupt bit is set by firmware or the corresponding bit in the ISET +// register. +// It is cleared by the corresponding bit in in the ICLR register or reading +// the IIDX register when this interrupt is the highest priority. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define FLASH_RIS_DONE 0x00000001U +#define FLASH_RIS_DONE_M 0x00000001U +#define FLASH_RIS_DONE_S 0U +#define FLASH_RIS_DONE_SET 0x00000001U +#define FLASH_RIS_DONE_CLR 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_MIS +// +//***************************************************************************** +// Field: [0] DONE +// +// Flash wrapper operation completed. +// This masked interrupt bit reflects the bitwise AND of the corresponding RIS +// and IMASK bits. +// ENUMs: +// SET Masked interrupt occurred +// CLR Masked interrupt did not occur +#define FLASH_MIS_DONE 0x00000001U +#define FLASH_MIS_DONE_M 0x00000001U +#define FLASH_MIS_DONE_S 0U +#define FLASH_MIS_DONE_SET 0x00000001U +#define FLASH_MIS_DONE_CLR 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_ISET +// +//***************************************************************************** +// Field: [0] DONE +// +// 0: No effect +// 1: Set the DONE interrupt in the RIS register +// ENUMs: +// SET Set IPSTANDARD.RIS bit +// NO_EFFECT Writing a 0 has no effect +#define FLASH_ISET_DONE 0x00000001U +#define FLASH_ISET_DONE_M 0x00000001U +#define FLASH_ISET_DONE_S 0U +#define FLASH_ISET_DONE_SET 0x00000001U +#define FLASH_ISET_DONE_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_ICLR +// +//***************************************************************************** +// Field: [0] DONE +// +// 0: No effect +// 1: Clear the DONE interrupt in the RIS register +// ENUMs: +// CLR Clear IPSTANDARD.RIS bit +// NO_EFFECT Writing a 0 has no effect +#define FLASH_ICLR_DONE 0x00000001U +#define FLASH_ICLR_DONE_M 0x00000001U +#define FLASH_ICLR_DONE_S 0U +#define FLASH_ICLR_DONE_CLR 0x00000001U +#define FLASH_ICLR_DONE_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODULEID +// +// Module ID +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define FLASH_DESC_MODULEID_W 16U +#define FLASH_DESC_MODULEID_M 0xFFFF0000U +#define FLASH_DESC_MODULEID_S 16U +#define FLASH_DESC_MODULEID_MAXIMUM 0xFFFF0000U +#define FLASH_DESC_MODULEID_MINIMUM 0x00000000U + +// Field: [15:12] FEATUREVER +// +// Feature set +// ENUMs: +// MAXIMUM Maximum Value +// MINIMUM Minimum Value +#define FLASH_DESC_FEATUREVER_W 4U +#define FLASH_DESC_FEATUREVER_M 0x0000F000U +#define FLASH_DESC_FEATUREVER_S 12U +#define FLASH_DESC_FEATUREVER_MAXIMUM 0x0000F000U +#define FLASH_DESC_FEATUREVER_MINIMUM 0x00000000U + +// Field: [11:8] INSTNUM +// +// Instance number +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define FLASH_DESC_INSTNUM_W 4U +#define FLASH_DESC_INSTNUM_M 0x00000F00U +#define FLASH_DESC_INSTNUM_S 8U +#define FLASH_DESC_INSTNUM_MAXIMUM 0x00000F00U +#define FLASH_DESC_INSTNUM_MINIMUM 0x00000000U + +// Field: [7:4] MAJREV +// +// Major Revision +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define FLASH_DESC_MAJREV_W 4U +#define FLASH_DESC_MAJREV_M 0x000000F0U +#define FLASH_DESC_MAJREV_S 4U +#define FLASH_DESC_MAJREV_MAXIMUM 0x000000F0U +#define FLASH_DESC_MAJREV_MINIMUM 0x00000000U + +// Field: [3:0] MINREV +// +// Minor Revision +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define FLASH_DESC_MINREV_W 4U +#define FLASH_DESC_MINREV_M 0x0000000FU +#define FLASH_DESC_MINREV_S 0U +#define FLASH_DESC_MINREV_MAXIMUM 0x0000000FU +#define FLASH_DESC_MINREV_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDEXEC +// +//***************************************************************************** +// Field: [0] VAL +// +// Command Execute value +// Initiates execution of the command specified in the CMDTYPE register. +// ENUMs: +// EXECUTE Command will execute or is executing in flash +// wrapper +// NOEXECUTE Command will not execute or is not executing in +// flash wrapper +#define FLASH_CMDEXEC_VAL 0x00000001U +#define FLASH_CMDEXEC_VAL_M 0x00000001U +#define FLASH_CMDEXEC_VAL_S 0U +#define FLASH_CMDEXEC_VAL_EXECUTE 0x00000001U +#define FLASH_CMDEXEC_VAL_NOEXECUTE 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDTYPE +// +//***************************************************************************** +// Field: [6:4] SIZE +// +// Command size +// ENUMs: +// BANK Operate on an entire flash bank +// SECTOR Operate on a flash sector +// EIGHTWORD Operate on 8 flash words +// FOURWORD Operate on 4 flash words +// TWOWORD Operate on 2 flash words +// ONEWORD Operate on 1 flash word +#define FLASH_CMDTYPE_SIZE_W 3U +#define FLASH_CMDTYPE_SIZE_M 0x00000070U +#define FLASH_CMDTYPE_SIZE_S 4U +#define FLASH_CMDTYPE_SIZE_BANK 0x00000050U +#define FLASH_CMDTYPE_SIZE_SECTOR 0x00000040U +#define FLASH_CMDTYPE_SIZE_EIGHTWORD 0x00000030U +#define FLASH_CMDTYPE_SIZE_FOURWORD 0x00000020U +#define FLASH_CMDTYPE_SIZE_TWOWORD 0x00000010U +#define FLASH_CMDTYPE_SIZE_ONEWORD 0x00000000U + +// Field: [2:0] COMMAND +// +// Command type +// ENUMs: +// BLANKVERIFY Blank Verify - Check whether a flash word is in +// the erased state. +// This command may only be +// used with CMDTYPE.SIZE = ONEWORD +// CLEARSTATUS Clear Status - Clear status bits in FW_SMSTAT +// only. +// MODECHANGE Mode Change - Perform a mode change only, no other +// operation. +// ERASE Erase +// PROGRAM Program +// NOOP No Operation +#define FLASH_CMDTYPE_COMMAND_W 3U +#define FLASH_CMDTYPE_COMMAND_M 0x00000007U +#define FLASH_CMDTYPE_COMMAND_S 0U +#define FLASH_CMDTYPE_COMMAND_BLANKVERIFY 0x00000006U +#define FLASH_CMDTYPE_COMMAND_CLEARSTATUS 0x00000005U +#define FLASH_CMDTYPE_COMMAND_MODECHANGE 0x00000004U +#define FLASH_CMDTYPE_COMMAND_ERASE 0x00000002U +#define FLASH_CMDTYPE_COMMAND_PROGRAM 0x00000001U +#define FLASH_CMDTYPE_COMMAND_NOOP 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDCTL +// +//***************************************************************************** +// Field: [21] DATAVEREN +// +// Enable invalid data verify. +// This checks for 0->1 transitions in the memory when +// a program operation is initiated. If such a transition is found, the +// program will +// fail with an error without executing the program. +// ENUMs: +// ENABLE Enable +// DISABLE Disable +#define FLASH_CMDCTL_DATAVEREN 0x00200000U +#define FLASH_CMDCTL_DATAVEREN_M 0x00200000U +#define FLASH_CMDCTL_DATAVEREN_S 21U +#define FLASH_CMDCTL_DATAVEREN_ENABLE 0x00200000U +#define FLASH_CMDCTL_DATAVEREN_DISABLE 0x00000000U + +// Field: [20] SSERASEDIS +// +// Disable Stair-Step Erase. If set, the default VHV trim voltage setting will +// be used +// for all erase pulses. +// By default, this bit is reset, meaning that the VHV voltage will be stepped +// during +// successive erase pulses. The step count, step voltage, begin and end +// voltages +// are all hard-wired. +// ENUMs: +// DISABLE Disable +// ENABLE Enable +#define FLASH_CMDCTL_SSERASEDIS 0x00100000U +#define FLASH_CMDCTL_SSERASEDIS_M 0x00100000U +#define FLASH_CMDCTL_SSERASEDIS_S 20U +#define FLASH_CMDCTL_SSERASEDIS_DISABLE 0x00100000U +#define FLASH_CMDCTL_SSERASEDIS_ENABLE 0x00000000U + +// Field: [16] ADDRXLATEOVR +// +// Override hardware address translation of address in CMDADDR from a +// system address to a bank address and bank ID. Use data written to +// CMDADDR directly as the bank address. Use the value written to +// CMDCTL.BANKSEL directly as the bank ID. Use the value written to +// CMDCTL.REGIONSEL directly as the region ID. +// ENUMs: +// OVERRIDE Override +// NOOVERRIDE Do not override +#define FLASH_CMDCTL_ADDRXLATEOVR 0x00010000U +#define FLASH_CMDCTL_ADDRXLATEOVR_M 0x00010000U +#define FLASH_CMDCTL_ADDRXLATEOVR_S 16U +#define FLASH_CMDCTL_ADDRXLATEOVR_OVERRIDE 0x00010000U +#define FLASH_CMDCTL_ADDRXLATEOVR_NOOVERRIDE 0x00000000U + +// Field: [12:9] REGIONSEL +// +// Bank Region +// A specific region ID can be written to this field to indicate to which +// region an +// operation is to be applied if CMDCTL.ADDRXLATEOVR is set. +// ENUMs: +// ENGR Engr Region +// TRIM Trim Region +// NONMAIN Non-Main Region +// MAIN Main Region +#define FLASH_CMDCTL_REGIONSEL_W 4U +#define FLASH_CMDCTL_REGIONSEL_M 0x00001E00U +#define FLASH_CMDCTL_REGIONSEL_S 9U +#define FLASH_CMDCTL_REGIONSEL_ENGR 0x00001000U +#define FLASH_CMDCTL_REGIONSEL_TRIM 0x00000800U +#define FLASH_CMDCTL_REGIONSEL_NONMAIN 0x00000400U +#define FLASH_CMDCTL_REGIONSEL_MAIN 0x00000200U + +// Field: [3:0] MODESEL +// +// Mode +// This field is only used for the Mode Change command type. Otherwise, bank +// and pump modes are set automaticlly through the NW hardware. +// ENUMs: +// ERASEBNK Erase Bank +// PGMMW Program Multiple Word +// ERASESECT Erase Sector +// ERASEVER Erase Verify Mode +// PGMSW Program Single Word +// PGMVER Program Verify Mode +// RDMARG1B Read Margin 1B Mode +// RDMARG0B Read Margin 0B Mode +// RDMARG1 Read Margin 1 Mode +// RDMARG0 Read Margin 0 Mode +// READ Read Mode +#define FLASH_CMDCTL_MODESEL_W 4U +#define FLASH_CMDCTL_MODESEL_M 0x0000000FU +#define FLASH_CMDCTL_MODESEL_S 0U +#define FLASH_CMDCTL_MODESEL_ERASEBNK 0x0000000FU +#define FLASH_CMDCTL_MODESEL_PGMMW 0x0000000EU +#define FLASH_CMDCTL_MODESEL_ERASESECT 0x0000000CU +#define FLASH_CMDCTL_MODESEL_ERASEVER 0x0000000BU +#define FLASH_CMDCTL_MODESEL_PGMSW 0x0000000AU +#define FLASH_CMDCTL_MODESEL_PGMVER 0x00000009U +#define FLASH_CMDCTL_MODESEL_RDMARG1B 0x00000007U +#define FLASH_CMDCTL_MODESEL_RDMARG0B 0x00000006U +#define FLASH_CMDCTL_MODESEL_RDMARG1 0x00000004U +#define FLASH_CMDCTL_MODESEL_RDMARG0 0x00000002U +#define FLASH_CMDCTL_MODESEL_READ 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDADDR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Address value +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDADDR_VAL_W 32U +#define FLASH_CMDADDR_VAL_M 0xFFFFFFFFU +#define FLASH_CMDADDR_VAL_S 0U +#define FLASH_CMDADDR_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDADDR_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDBYTEN +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Command Byte Enable value. +// A 1-bit per flash word byte value is placed in this register. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDBYTEN_VAL_W 16U +#define FLASH_CMDBYTEN_VAL_M 0x0000FFFFU +#define FLASH_CMDBYTEN_VAL_S 0U +#define FLASH_CMDBYTEN_VAL_MAXIMUM 0x0003FFFFU +#define FLASH_CMDBYTEN_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDDATA0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// A 32-bit data value is placed in this field. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDDATA0_VAL_W 32U +#define FLASH_CMDDATA0_VAL_M 0xFFFFFFFFU +#define FLASH_CMDDATA0_VAL_S 0U +#define FLASH_CMDDATA0_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDDATA0_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDDATA1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// A 32-bit data value is placed in this field. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDDATA1_VAL_W 32U +#define FLASH_CMDDATA1_VAL_M 0xFFFFFFFFU +#define FLASH_CMDDATA1_VAL_S 0U +#define FLASH_CMDDATA1_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDDATA1_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDDATA2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// A 32-bit data value is placed in this field. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDDATA2_VAL_W 32U +#define FLASH_CMDDATA2_VAL_M 0xFFFFFFFFU +#define FLASH_CMDDATA2_VAL_S 0U +#define FLASH_CMDDATA2_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDDATA2_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDDATA3 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// A 32-bit data value is placed in this field. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDDATA3_VAL_W 32U +#define FLASH_CMDDATA3_VAL_M 0xFFFFFFFFU +#define FLASH_CMDDATA3_VAL_S 0U +#define FLASH_CMDDATA3_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDDATA3_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDWEPROTA +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Each bit protects 1 sector. +// +// bit [0]: When 1, sector 0 of the flash memory will be protected from program +// and erase. +// bit [1]: When 1, sector 1 of the flash memory will be protected from program +// and erase. +// : +// : +// bit [31]: When 1, sector 31 of the flash memory will be protected from +// program +// and erase. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDWEPROTA_VAL_W 32U +#define FLASH_CMDWEPROTA_VAL_M 0xFFFFFFFFU +#define FLASH_CMDWEPROTA_VAL_S 0U +#define FLASH_CMDWEPROTA_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDWEPROTA_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDWEPROTB +// +//***************************************************************************** +// Field: [27:0] VAL +// +// Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 +// sectors +// in the flash will be protected from program and erase. A maximum of 256 +// sectors can be protected with this register. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDWEPROTB_VAL_W 28U +#define FLASH_CMDWEPROTB_VAL_M 0x0FFFFFFFU +#define FLASH_CMDWEPROTB_VAL_S 0U +#define FLASH_CMDWEPROTB_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDWEPROTB_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDWEPROTNM +// +//***************************************************************************** +// Field: [0] VAL +// +// Each bit protects 1 sector. +// +// bit [0]: When 1, sector 0 of the non-main region will be protected from +// program +// and erase. +// bit [1]: When 1, sector 1 of the non-main region will be protected from +// program +// and erase. +// : +// : +// bit [31]: When 1, sector 31 of the non-main will be protected from program +// and erase. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDWEPROTNM_VAL 0x00000001U +#define FLASH_CMDWEPROTNM_VAL_M 0x00000001U +#define FLASH_CMDWEPROTNM_VAL_S 0U +#define FLASH_CMDWEPROTNM_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDWEPROTNM_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDWEPROTTR +// +//***************************************************************************** +// Field: [0] VAL +// +// Each bit protects 1 sector. +// +// bit [0]: When 1, sector 0 of the engr region will be protected from program +// and erase. +// bit [1]: When 1, sector 1 of the engr region will be protected from program +// and erase. +// : +// : +// bit [31]: When 1, sector 31 of the engr region will be protected from +// program +// and erase. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDWEPROTTR_VAL 0x00000001U +#define FLASH_CMDWEPROTTR_VAL_M 0x00000001U +#define FLASH_CMDWEPROTTR_VAL_S 0U +#define FLASH_CMDWEPROTTR_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDWEPROTTR_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CMDWEPROTEN +// +//***************************************************************************** +// Field: [0] VAL +// +// Each bit protects 1 sector. +// +// bit [0]: When 1, sector 0 of the engr region will be protected from program +// and erase. +// bit [1]: When 1, sector 1 of the engr region will be protected from program +// and erase. +// : +// : +// bit [31]: When 1, sector 31 of the engr region will be protected from +// program +// and erase. +// ENUMs: +// MAXIMUM Maximum value of VAL +// MINIMUM Minimum value of VAL +#define FLASH_CMDWEPROTEN_VAL 0x00000001U +#define FLASH_CMDWEPROTEN_VAL_M 0x00000001U +#define FLASH_CMDWEPROTEN_VAL_S 0U +#define FLASH_CMDWEPROTEN_VAL_MAXIMUM 0xFFFFFFFFU +#define FLASH_CMDWEPROTEN_VAL_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CFGCMD +// +//***************************************************************************** +// Field: [3:0] WAITSTATE +// +// Wait State setting for verify reads +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define FLASH_CFGCMD_WAITSTATE_W 4U +#define FLASH_CFGCMD_WAITSTATE_M 0x0000000FU +#define FLASH_CFGCMD_WAITSTATE_S 0U +#define FLASH_CFGCMD_WAITSTATE_MAXIMUM 0x0000000FU +#define FLASH_CFGCMD_WAITSTATE_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_CFGPCNT +// +//***************************************************************************** +// Field: [11:4] MAXPCNTVAL +// +// Override maximum pulse counter with this value. +// If MAXPCNTOVR = 0, then this field is ignored. +// If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used +// to override the max pulse count for both program and erase. Full max value +// will be {4'h0, MAXPCNTVAL} . +// If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used +// to override the max pulse count for program only. Full max value will be +// {4'h0, MAXPCNTVAL}. +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define FLASH_CFGPCNT_MAXPCNTVAL_W 8U +#define FLASH_CFGPCNT_MAXPCNTVAL_M 0x00000FF0U +#define FLASH_CFGPCNT_MAXPCNTVAL_S 4U +#define FLASH_CFGPCNT_MAXPCNTVAL_MAXIMUM 0x00000FF0U +#define FLASH_CFGPCNT_MAXPCNTVAL_MINIMUM 0x00000000U + +// Field: [0] MAXPCNTOVR +// +// Override hard-wired maximum pulse count. If MAXERSPCNTOVR +// is not set, then setting this value alone will override the max pulse count +// for +// both program and erase. If MAXERSPCNTOVR is set, then this bit will only +// control the max pulse count setting for program. +// By default, this bit is 0, and a hard-wired max pulse count is used. +// ENUMs: +// OVERRIDE Use value from MAXPCNTVAL field as maximum puse +// count +// DEFAULT Use hard-wired (default) value for maximum pulse +// count +#define FLASH_CFGPCNT_MAXPCNTOVR 0x00000001U +#define FLASH_CFGPCNT_MAXPCNTOVR_M 0x00000001U +#define FLASH_CFGPCNT_MAXPCNTOVR_S 0U +#define FLASH_CFGPCNT_MAXPCNTOVR_OVERRIDE 0x00000001U +#define FLASH_CFGPCNT_MAXPCNTOVR_DEFAULT 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_STATCMD +// +//***************************************************************************** +// Field: [12] FAILMISC +// +// Command failed due to error other than write/erase protect violation or +// verify +// error. This is an extra bit in case a new failure mechanism is added which +// requires a status bit. +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILMISC 0x00001000U +#define FLASH_STATCMD_FAILMISC_M 0x00001000U +#define FLASH_STATCMD_FAILMISC_S 12U +#define FLASH_STATCMD_FAILMISC_STATFAIL 0x00001000U +#define FLASH_STATCMD_FAILMISC_STATNOFAIL 0x00000000U + +// Field: [8] FAILINVDATA +// +// Program command failed because an attempt was made to program a stored +// 0 value to a 1. +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILINVDATA 0x00000100U +#define FLASH_STATCMD_FAILINVDATA_M 0x00000100U +#define FLASH_STATCMD_FAILINVDATA_S 8U +#define FLASH_STATCMD_FAILINVDATA_STATFAIL 0x00000100U +#define FLASH_STATCMD_FAILINVDATA_STATNOFAIL 0x00000000U + +// Field: [7] FAILMODE +// +// Command failed because a bank has been set to a mode other than READ. +// Program and Erase commands cannot be initiated unless all banks are in READ +// mode. +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILMODE 0x00000080U +#define FLASH_STATCMD_FAILMODE_M 0x00000080U +#define FLASH_STATCMD_FAILMODE_S 7U +#define FLASH_STATCMD_FAILMODE_STATFAIL 0x00000080U +#define FLASH_STATCMD_FAILMODE_STATNOFAIL 0x00000000U + +// Field: [6] FAILILLADDR +// +// Command failed due to the use of an illegal address +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILILLADDR 0x00000040U +#define FLASH_STATCMD_FAILILLADDR_M 0x00000040U +#define FLASH_STATCMD_FAILILLADDR_S 6U +#define FLASH_STATCMD_FAILILLADDR_STATFAIL 0x00000040U +#define FLASH_STATCMD_FAILILLADDR_STATNOFAIL 0x00000000U + +// Field: [5] FAILVERIFY +// +// Command failed due to verify error +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILVERIFY 0x00000020U +#define FLASH_STATCMD_FAILVERIFY_M 0x00000020U +#define FLASH_STATCMD_FAILVERIFY_S 5U +#define FLASH_STATCMD_FAILVERIFY_STATFAIL 0x00000020U +#define FLASH_STATCMD_FAILVERIFY_STATNOFAIL 0x00000000U + +// Field: [4] FAILWEPROT +// +// Command failed due to Write/Erase Protect Sector Violation +// ENUMs: +// STATFAIL Fail +// STATNOFAIL No Fail +#define FLASH_STATCMD_FAILWEPROT 0x00000010U +#define FLASH_STATCMD_FAILWEPROT_M 0x00000010U +#define FLASH_STATCMD_FAILWEPROT_S 4U +#define FLASH_STATCMD_FAILWEPROT_STATFAIL 0x00000010U +#define FLASH_STATCMD_FAILWEPROT_STATNOFAIL 0x00000000U + +// Field: [2] CMDINPROGRESS +// +// Command In Progress +// ENUMs: +// STATINPROGRESS In Progress +// STATCOMPLETE Complete +#define FLASH_STATCMD_CMDINPROGRESS 0x00000004U +#define FLASH_STATCMD_CMDINPROGRESS_M 0x00000004U +#define FLASH_STATCMD_CMDINPROGRESS_S 2U +#define FLASH_STATCMD_CMDINPROGRESS_STATINPROGRESS 0x00000004U +#define FLASH_STATCMD_CMDINPROGRESS_STATCOMPLETE 0x00000000U + +// Field: [1] CMDPASS +// +// Command Pass - valid when CMD_DONE field is 1 +// ENUMs: +// STATPASS Pass +// STATFAIL Fail +#define FLASH_STATCMD_CMDPASS 0x00000002U +#define FLASH_STATCMD_CMDPASS_M 0x00000002U +#define FLASH_STATCMD_CMDPASS_S 1U +#define FLASH_STATCMD_CMDPASS_STATPASS 0x00000002U +#define FLASH_STATCMD_CMDPASS_STATFAIL 0x00000000U + +// Field: [0] CMDDONE +// +// Command Done +// ENUMs: +// STATDONE Done +// STATNOTDONE Not Done +#define FLASH_STATCMD_CMDDONE 0x00000001U +#define FLASH_STATCMD_CMDDONE_M 0x00000001U +#define FLASH_STATCMD_CMDDONE_S 0U +#define FLASH_STATCMD_CMDDONE_STATDONE 0x00000001U +#define FLASH_STATCMD_CMDDONE_STATNOTDONE 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_STATADDR +// +//***************************************************************************** +// Field: [25:21] BANKID +// +// Current Bank ID +// A bank indicator is stored in this register which represents the current +// bank on +// which the state machine is operating. There is 1 bit per bank. +// ENUMs: +// BANK4 Bank 4 +// BANK3 Bank 3 +// BANK2 Bank 2 +// BANK1 Bank 1 +// BANK0 Bank 0 +#define FLASH_STATADDR_BANKID_W 5U +#define FLASH_STATADDR_BANKID_M 0x03E00000U +#define FLASH_STATADDR_BANKID_S 21U +#define FLASH_STATADDR_BANKID_BANK4 0x02000000U +#define FLASH_STATADDR_BANKID_BANK3 0x01000000U +#define FLASH_STATADDR_BANKID_BANK2 0x00800000U +#define FLASH_STATADDR_BANKID_BANK1 0x00400000U +#define FLASH_STATADDR_BANKID_BANK0 0x00200000U + +// Field: [20:16] REGIONID +// +// Current Region ID +// A region indicator is stored in this register which represents the current +// flash +// region on which the state machine is operating. +// ENUMs: +// ENGR Engr Region +// TRIM Trim Region +// NONMAIN Non-Main Region +// MAIN Main Region +#define FLASH_STATADDR_REGIONID_W 5U +#define FLASH_STATADDR_REGIONID_M 0x001F0000U +#define FLASH_STATADDR_REGIONID_S 16U +#define FLASH_STATADDR_REGIONID_ENGR 0x00080000U +#define FLASH_STATADDR_REGIONID_TRIM 0x00040000U +#define FLASH_STATADDR_REGIONID_NONMAIN 0x00020000U +#define FLASH_STATADDR_REGIONID_MAIN 0x00010000U + +// Field: [15:0] BANKADDR +// +// Current Bank Address +// A bank offset address is stored in this register. +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define FLASH_STATADDR_BANKADDR_W 16U +#define FLASH_STATADDR_BANKADDR_M 0x0000FFFFU +#define FLASH_STATADDR_BANKADDR_S 0U +#define FLASH_STATADDR_BANKADDR_MAXIMUM 0x0000FFFFU +#define FLASH_STATADDR_BANKADDR_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_STATPCNT +// +//***************************************************************************** +// Field: [11:0] PULSECNT +// +// Current Pulse Counter Value +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define FLASH_STATPCNT_PULSECNT_W 12U +#define FLASH_STATPCNT_PULSECNT_M 0x00000FFFU +#define FLASH_STATPCNT_PULSECNT_S 0U +#define FLASH_STATPCNT_PULSECNT_MAXIMUM 0x00000FFFU +#define FLASH_STATPCNT_PULSECNT_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: FLASH_O_STATMODE +// +//***************************************************************************** +// Field: [17] BANK1TRDY +// +// Bank 1T Ready. +// Bank(s) are ready for 1T access. This is accomplished when the bank and +// pump +// have been trimmed. +// ENUMs: +// TRUE Ready +// FALSE Not ready +#define FLASH_STATMODE_BANK1TRDY 0x00020000U +#define FLASH_STATMODE_BANK1TRDY_M 0x00020000U +#define FLASH_STATMODE_BANK1TRDY_S 17U +#define FLASH_STATMODE_BANK1TRDY_TRUE 0x00020000U +#define FLASH_STATMODE_BANK1TRDY_FALSE 0x00000000U + +// Field: [16] BANK2TRDY +// +// Bank 2T Ready. +// Bank(s) are ready for 2T access. This is accomplished when the pump has +// fully driven power rails to the bank(s). +// ENUMs: +// TRUE Ready +// FALSE Not ready +#define FLASH_STATMODE_BANK2TRDY 0x00010000U +#define FLASH_STATMODE_BANK2TRDY_M 0x00010000U +#define FLASH_STATMODE_BANK2TRDY_S 16U +#define FLASH_STATMODE_BANK2TRDY_TRUE 0x00010000U +#define FLASH_STATMODE_BANK2TRDY_FALSE 0x00000000U + +// Field: [11:8] BANKMODE +// +// Indicates mode of bank(s) that are not in READ mode +// ENUMs: +// ERASEBNK Erase Bank +// PGMMW Program Multiple Word +// ERASESECT Erase Sector +// ERASEVER Erase Verify Mode +// PGMSW Program Single Word +// PGMVER Program Verify Mode +// RDMARG1B Read Margin 1B Mode +// RDMARG0B Read Margin 0B Mode +// RDMARG1 Read Margin 1 Mode +// RDMARG0 Read Margin 0 Mode +// READ Read Mode +#define FLASH_STATMODE_BANKMODE_W 4U +#define FLASH_STATMODE_BANKMODE_M 0x00000F00U +#define FLASH_STATMODE_BANKMODE_S 8U +#define FLASH_STATMODE_BANKMODE_ERASEBNK 0x00000F00U +#define FLASH_STATMODE_BANKMODE_PGMMW 0x00000E00U +#define FLASH_STATMODE_BANKMODE_ERASESECT 0x00000C00U +#define FLASH_STATMODE_BANKMODE_ERASEVER 0x00000B00U +#define FLASH_STATMODE_BANKMODE_PGMSW 0x00000A00U +#define FLASH_STATMODE_BANKMODE_PGMVER 0x00000900U +#define FLASH_STATMODE_BANKMODE_RDMARG1B 0x00000700U +#define FLASH_STATMODE_BANKMODE_RDMARG0B 0x00000600U +#define FLASH_STATMODE_BANKMODE_RDMARG1 0x00000400U +#define FLASH_STATMODE_BANKMODE_RDMARG0 0x00000200U +#define FLASH_STATMODE_BANKMODE_READ 0x00000000U + +// Field: [0] BANKNOTINRD +// +// Bank not in read mode. +// Indicates which banks are not in READ mode. There is 1 bit per bank. +// ENUMs: +// BANK4 Bank 4 +// BANK3 Bank 3 +// BANK2 Bank 2 +// BANK1 Bank 1 +// BANK0 Bank 0 +#define FLASH_STATMODE_BANKNOTINRD 0x00000001U +#define FLASH_STATMODE_BANKNOTINRD_M 0x00000001U +#define FLASH_STATMODE_BANKNOTINRD_S 0U +#define FLASH_STATMODE_BANKNOTINRD_BANK4 0x00000010U +#define FLASH_STATMODE_BANKNOTINRD_BANK3 0x00000008U +#define FLASH_STATMODE_BANKNOTINRD_BANK2 0x00000004U +#define FLASH_STATMODE_BANKNOTINRD_BANK1 0x00000002U +#define FLASH_STATMODE_BANKNOTINRD_BANK0 0x00000001U + +//***************************************************************************** +// +// Register: FLASH_O_GBLINFO0 +// +//***************************************************************************** +// Field: [18:16] NUMBANKS +// +// Number of banks instantiated +// Minimum: 1 +// Maximum: 5 +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define FLASH_GBLINFO0_NUMBANKS_W 3U +#define FLASH_GBLINFO0_NUMBANKS_M 0x00070000U +#define FLASH_GBLINFO0_NUMBANKS_S 16U +#define FLASH_GBLINFO0_NUMBANKS_MAXIMUM 0x00050000U +#define FLASH_GBLINFO0_NUMBANKS_MINIMUM 0x00010000U + +// Field: [15:0] SECTORSIZE +// +// Sector size in bytes +// ENUMs: +// TWOKB Sector size is TWOKB +// ONEKB Sector size is ONEKB +#define FLASH_GBLINFO0_SECTORSIZE_W 16U +#define FLASH_GBLINFO0_SECTORSIZE_M 0x0000FFFFU +#define FLASH_GBLINFO0_SECTORSIZE_S 0U +#define FLASH_GBLINFO0_SECTORSIZE_TWOKB 0x00000800U +#define FLASH_GBLINFO0_SECTORSIZE_ONEKB 0x00000400U + +//***************************************************************************** +// +// Register: FLASH_O_GBLINFO1 +// +//***************************************************************************** +// Field: [18:16] REDWIDTH +// +// Redundant data width in bits +// ENUMs: +// W4BIT Redundant data width is 4 bits +// W2BIT Redundant data width is 2 bits +// W0BIT Redundant data width is 0. Redundancy/Repair not +// present. +#define FLASH_GBLINFO1_REDWIDTH_W 3U +#define FLASH_GBLINFO1_REDWIDTH_M 0x00070000U +#define FLASH_GBLINFO1_REDWIDTH_S 16U +#define FLASH_GBLINFO1_REDWIDTH_W4BIT 0x00040000U +#define FLASH_GBLINFO1_REDWIDTH_W2BIT 0x00020000U +#define FLASH_GBLINFO1_REDWIDTH_W0BIT 0x00000000U + +// Field: [12:8] ECCWIDTH +// +// ECC data width in bits +// ENUMs: +// W16BIT ECC data width is 16 bits +// W8BIT ECC data width is 8 bits +// W0BIT ECC data width is 0. ECC not used. +#define FLASH_GBLINFO1_ECCWIDTH_W 5U +#define FLASH_GBLINFO1_ECCWIDTH_M 0x00001F00U +#define FLASH_GBLINFO1_ECCWIDTH_S 8U +#define FLASH_GBLINFO1_ECCWIDTH_W16BIT 0x00001000U +#define FLASH_GBLINFO1_ECCWIDTH_W8BIT 0x00000800U +#define FLASH_GBLINFO1_ECCWIDTH_W0BIT 0x00000000U + +// Field: [7:0] DATAWIDTH +// +// Data width in bits +// ENUMs: +// W128BIT Data width is 128 bits +// W64BIT Data width is 64 bits +#define FLASH_GBLINFO1_DATAWIDTH_W 8U +#define FLASH_GBLINFO1_DATAWIDTH_M 0x000000FFU +#define FLASH_GBLINFO1_DATAWIDTH_S 0U +#define FLASH_GBLINFO1_DATAWIDTH_W128BIT 0x00000080U +#define FLASH_GBLINFO1_DATAWIDTH_W64BIT 0x00000040U + +//***************************************************************************** +// +// Register: FLASH_O_GBLINFO2 +// +//***************************************************************************** +// Field: [3:0] DATAREGISTERS +// +// Number of data registers present. +// ENUMs: +// MAXIMUM Maximum value of DATAREGISTERS +// MINIMUM Minimum value of DATAREGISTERS +#define FLASH_GBLINFO2_DATAREGISTERS_W 4U +#define FLASH_GBLINFO2_DATAREGISTERS_M 0x0000000FU +#define FLASH_GBLINFO2_DATAREGISTERS_S 0U +#define FLASH_GBLINFO2_DATAREGISTERS_MAXIMUM 0x00000008U +#define FLASH_GBLINFO2_DATAREGISTERS_MINIMUM 0x00000001U + +//***************************************************************************** +// +// Register: FLASH_O_BANK0INFO0 +// +//***************************************************************************** +// Field: [11:0] MAINSIZE +// +// Main region size in sectors +// Minimum: 0x8 (8) +// Maximum: 0x200 (512) +// ENUMs: +// MAXSECTORS Maximum value of MAINSIZE +// MINSECTORS Minimum value of MAINSIZE +#define FLASH_BANK0INFO0_MAINSIZE_W 12U +#define FLASH_BANK0INFO0_MAINSIZE_M 0x00000FFFU +#define FLASH_BANK0INFO0_MAINSIZE_S 0U +#define FLASH_BANK0INFO0_MAINSIZE_MAXSECTORS 0x00000200U +#define FLASH_BANK0INFO0_MAINSIZE_MINSECTORS 0x00000008U + +//***************************************************************************** +// +// Register: FLASH_O_BANK0INFO1 +// +//***************************************************************************** +// Field: [23:16] ENGRSIZE +// +// Engr region size in sectors +// Minimum: 0x0 (0) +// Maximum: 0x10 (16) +// ENUMs: +// MAXSECTORS Maximum value of ENGRSIZE +// MINSECTORS Minimum value of ENGRSIZE +#define FLASH_BANK0INFO1_ENGRSIZE_W 8U +#define FLASH_BANK0INFO1_ENGRSIZE_M 0x00FF0000U +#define FLASH_BANK0INFO1_ENGRSIZE_S 16U +#define FLASH_BANK0INFO1_ENGRSIZE_MAXSECTORS 0x00200000U +#define FLASH_BANK0INFO1_ENGRSIZE_MINSECTORS 0x00000000U + +// Field: [15:8] TRIMSIZE +// +// Trim region size in sectors +// Minimum: 0x0 (0) +// Maximum: 0x10 (16) +// ENUMs: +// MAXSECTORS Maximum value of TRIMSIZE +// MINSECTORS Minimum value of TRIMSIZE +#define FLASH_BANK0INFO1_TRIMSIZE_W 8U +#define FLASH_BANK0INFO1_TRIMSIZE_M 0x0000FF00U +#define FLASH_BANK0INFO1_TRIMSIZE_S 8U +#define FLASH_BANK0INFO1_TRIMSIZE_MAXSECTORS 0x00002000U +#define FLASH_BANK0INFO1_TRIMSIZE_MINSECTORS 0x00000000U + +// Field: [7:0] NONMAINSIZE +// +// Non-main region size in sectors +// Minimum: 0x0 (0) +// Maximum: 0x10 (16) +// ENUMs: +// MAXSECTORS Maximum value of NONMAINSIZE +// MINSECTORS Minimum value of NONMAINSIZE +#define FLASH_BANK0INFO1_NONMAINSIZE_W 8U +#define FLASH_BANK0INFO1_NONMAINSIZE_M 0x000000FFU +#define FLASH_BANK0INFO1_NONMAINSIZE_S 0U +#define FLASH_BANK0INFO1_NONMAINSIZE_MAXSECTORS 0x00000020U +#define FLASH_BANK0INFO1_NONMAINSIZE_MINSECTORS 0x00000000U + + +#endif // __FLASH__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_gpio.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_gpio.h new file mode 100644 index 00000000..7adefe23 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_gpio.h @@ -0,0 +1,6737 @@ +/****************************************************************************** +* Filename: hw_gpio_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Module Description +#define GPIO_O_DESC 0x00000000U + +// Module Description Extended +#define GPIO_O_DESCEX 0x00000004U + +// Interrupt Mask +#define GPIO_O_IMASK 0x00000044U + +// Raw interrupt status +#define GPIO_O_RIS 0x0000004CU + +// Masked interrupt status +#define GPIO_O_MIS 0x00000054U + +// Interrupt set +#define GPIO_O_ISET 0x0000005CU + +// Interrupt clear +#define GPIO_O_ICLR 0x00000064U + +// Interrupt mask set +#define GPIO_O_IMSET 0x0000006CU + +// Interrupt mask clear +#define GPIO_O_IMCLR 0x00000074U + +// Alias for Data out 3 to 0 +#define GPIO_O_DOUT3_0 0x00000100U + +// Alias for Data out 7 to 4 +#define GPIO_O_DOUT7_4 0x00000104U + +// Alias for Data out 11 to 8 +#define GPIO_O_DOUT11_8 0x00000108U + +// Alias for Data out 15 to 12 +#define GPIO_O_DOUT15_12 0x0000010CU + +// Alias for Data out 19 to 16 +#define GPIO_O_DOUT19_16 0x00000110U + +// Alias for Data out 23 to 20 +#define GPIO_O_DOUT23_20 0x00000114U + +// Alias for Data out 27 to 24 +#define GPIO_O_DOUT27_24 0x00000118U + +// Data out 31 to 0 +#define GPIO_O_DOUT31_0 0x00000200U + +// Data out set 31 to 0 +#define GPIO_O_DOUTSET31_0 0x00000210U + +// Data out clear 31 to 0 +#define GPIO_O_DOUTCLR31_0 0x00000220U + +// Data out toggle 31 to 0 +#define GPIO_O_DOUTTGL31_0 0x00000230U + +// Alias for Data out toggle 3 to 0 +#define GPIO_O_DOUTTGL3_0 0x00000300U + +// Alias for Data out toggle 7 to 4 +#define GPIO_O_DOUTTGL7_4 0x00000304U + +// Alias for Data out toggle 11 to 8 +#define GPIO_O_DOUTTGL11_8 0x00000308U + +// Alias for Data out toggle 15 to 12 +#define GPIO_O_DOUTTGL15_12 0x0000030CU + +// Alias for Data out toggle 19 to 16 +#define GPIO_O_DOUTTGL19_16 0x00000310U + +// Alias for Data out toggle 23 to 20 +#define GPIO_O_DOUTTGL23_20 0x00000314U + +// Alias for Data out toggle 27 to 24 +#define GPIO_O_DOUTTGL27_24 0x00000318U + +// Alias for Data out enable 3 to 0 +#define GPIO_O_DOE3_0 0x00000400U + +// Alias for Data out enable 7 to 4 +#define GPIO_O_DOE7_4 0x00000404U + +// Alias for Data out enable 11 to 8 +#define GPIO_O_DOE11_8 0x00000408U + +// Alias for Data out enable 15 to 12 +#define GPIO_O_DOE15_12 0x0000040CU + +// Alias for Data out enable 19 to 16 +#define GPIO_O_DOE19_16 0x00000410U + +// Alias for Data out enable 23 to 20 +#define GPIO_O_DOE23_20 0x00000414U + +// Alias for Data out enable 27 to 24 +#define GPIO_O_DOE27_24 0x00000418U + +// Data out enable 31 to 0 +#define GPIO_O_DOE31_0 0x00000500U + +// Data out enable set 31 to 0 +#define GPIO_O_DOESET31_0 0x00000510U + +// Data out enable clear 31 to 0 +#define GPIO_O_DOECLR31_0 0x00000520U + +// Data out enable toggle 31 to 0 +#define GPIO_O_DOETGL31_0 0x00000530U + +// Alias for Data input 3 to 0 +#define GPIO_O_DIN3_0 0x00000600U + +// Alias for Data input 7 to 4 +#define GPIO_O_DIN7_4 0x00000604U + +// Alias for Data input 11 to 8 +#define GPIO_O_DIN11_8 0x00000608U + +// Alias for Data input 15 to 12 +#define GPIO_O_DIN15_12 0x0000060CU + +// Alias for Data input 19 to 16 +#define GPIO_O_DIN19_16 0x00000610U + +// Alias for Data input 23 to 20 +#define GPIO_O_DIN23_20 0x00000614U + +// Alias for Data input 27 to 24 +#define GPIO_O_DIN27_24 0x00000618U + +// Data input 31 to 0 +#define GPIO_O_DIN31_0 0x00000700U + +// Event configuration +#define GPIO_O_EVTCFG 0x00000800U + +//***************************************************************************** +// +// Register: GPIO_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define GPIO_DESC_MODID_W 16U +#define GPIO_DESC_MODID_M 0xFFFF0000U +#define GPIO_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set from aggregated +// IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define GPIO_DESC_STDIPOFF_W 4U +#define GPIO_DESC_STDIPOFF_M 0x0000F000U +#define GPIO_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define GPIO_DESC_INSTIDX_W 4U +#define GPIO_DESC_INSTIDX_M 0x00000F00U +#define GPIO_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define GPIO_DESC_MAJREV_W 4U +#define GPIO_DESC_MAJREV_M 0x000000F0U +#define GPIO_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define GPIO_DESC_MINREV_W 4U +#define GPIO_DESC_MINREV_M 0x0000000FU +#define GPIO_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: GPIO_O_DESCEX +// +//***************************************************************************** +// Field: [5:0] NUMDIO +// +// This provides the total number of DIOs supported by GPIO. The number of DIOs +// supprted is NUMDIO + 1 +#define GPIO_DESCEX_NUMDIO_W 6U +#define GPIO_DESCEX_NUMDIO_M 0x0000003FU +#define GPIO_DESCEX_NUMDIO_S 0U + +//***************************************************************************** +// +// Register: GPIO_O_IMASK +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Interrupt mask for DIO25 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO25 0x02000000U +#define GPIO_IMASK_DIO25_M 0x02000000U +#define GPIO_IMASK_DIO25_S 25U +#define GPIO_IMASK_DIO25_SET 0x02000000U +#define GPIO_IMASK_DIO25_CLR 0x00000000U + +// Field: [24] DIO24 +// +// Interrupt mask for DIO24 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO24 0x01000000U +#define GPIO_IMASK_DIO24_M 0x01000000U +#define GPIO_IMASK_DIO24_S 24U +#define GPIO_IMASK_DIO24_SET 0x01000000U +#define GPIO_IMASK_DIO24_CLR 0x00000000U + +// Field: [23] DIO23 +// +// Interrupt mask for DIO23 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO23 0x00800000U +#define GPIO_IMASK_DIO23_M 0x00800000U +#define GPIO_IMASK_DIO23_S 23U +#define GPIO_IMASK_DIO23_SET 0x00800000U +#define GPIO_IMASK_DIO23_CLR 0x00000000U + +// Field: [22] DIO22 +// +// Interrupt mask for DIO22 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO22 0x00400000U +#define GPIO_IMASK_DIO22_M 0x00400000U +#define GPIO_IMASK_DIO22_S 22U +#define GPIO_IMASK_DIO22_SET 0x00400000U +#define GPIO_IMASK_DIO22_CLR 0x00000000U + +// Field: [21] DIO21 +// +// Interrupt mask for DIO21 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO21 0x00200000U +#define GPIO_IMASK_DIO21_M 0x00200000U +#define GPIO_IMASK_DIO21_S 21U +#define GPIO_IMASK_DIO21_SET 0x00200000U +#define GPIO_IMASK_DIO21_CLR 0x00000000U + +// Field: [20] DIO20 +// +// Interrupt mask for DIO20 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO20 0x00100000U +#define GPIO_IMASK_DIO20_M 0x00100000U +#define GPIO_IMASK_DIO20_S 20U +#define GPIO_IMASK_DIO20_SET 0x00100000U +#define GPIO_IMASK_DIO20_CLR 0x00000000U + +// Field: [19] DIO19 +// +// Interrupt mask for DIO19 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO19 0x00080000U +#define GPIO_IMASK_DIO19_M 0x00080000U +#define GPIO_IMASK_DIO19_S 19U +#define GPIO_IMASK_DIO19_SET 0x00080000U +#define GPIO_IMASK_DIO19_CLR 0x00000000U + +// Field: [18] DIO18 +// +// Interrupt mask for DIO18 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO18 0x00040000U +#define GPIO_IMASK_DIO18_M 0x00040000U +#define GPIO_IMASK_DIO18_S 18U +#define GPIO_IMASK_DIO18_SET 0x00040000U +#define GPIO_IMASK_DIO18_CLR 0x00000000U + +// Field: [17] DIO17 +// +// Interrupt mask for DIO17 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO17 0x00020000U +#define GPIO_IMASK_DIO17_M 0x00020000U +#define GPIO_IMASK_DIO17_S 17U +#define GPIO_IMASK_DIO17_SET 0x00020000U +#define GPIO_IMASK_DIO17_CLR 0x00000000U + +// Field: [16] DIO16 +// +// Interrupt mask for DIO16 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO16 0x00010000U +#define GPIO_IMASK_DIO16_M 0x00010000U +#define GPIO_IMASK_DIO16_S 16U +#define GPIO_IMASK_DIO16_SET 0x00010000U +#define GPIO_IMASK_DIO16_CLR 0x00000000U + +// Field: [15] DIO15 +// +// Interrupt mask for DIO15 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO15 0x00008000U +#define GPIO_IMASK_DIO15_M 0x00008000U +#define GPIO_IMASK_DIO15_S 15U +#define GPIO_IMASK_DIO15_SET 0x00008000U +#define GPIO_IMASK_DIO15_CLR 0x00000000U + +// Field: [14] DIO14 +// +// Interrupt mask for DIO14 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO14 0x00004000U +#define GPIO_IMASK_DIO14_M 0x00004000U +#define GPIO_IMASK_DIO14_S 14U +#define GPIO_IMASK_DIO14_SET 0x00004000U +#define GPIO_IMASK_DIO14_CLR 0x00000000U + +// Field: [13] DIO13 +// +// Interrupt mask for DIO13 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO13 0x00002000U +#define GPIO_IMASK_DIO13_M 0x00002000U +#define GPIO_IMASK_DIO13_S 13U +#define GPIO_IMASK_DIO13_SET 0x00002000U +#define GPIO_IMASK_DIO13_CLR 0x00000000U + +// Field: [12] DIO12 +// +// Interrupt mask for DIO12 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO12 0x00001000U +#define GPIO_IMASK_DIO12_M 0x00001000U +#define GPIO_IMASK_DIO12_S 12U +#define GPIO_IMASK_DIO12_SET 0x00001000U +#define GPIO_IMASK_DIO12_CLR 0x00000000U + +// Field: [11] DIO11 +// +// Interrupt mask for DIO11 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO11 0x00000800U +#define GPIO_IMASK_DIO11_M 0x00000800U +#define GPIO_IMASK_DIO11_S 11U +#define GPIO_IMASK_DIO11_SET 0x00000800U +#define GPIO_IMASK_DIO11_CLR 0x00000000U + +// Field: [10] DIO10 +// +// Interrupt mask for DIO10 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO10 0x00000400U +#define GPIO_IMASK_DIO10_M 0x00000400U +#define GPIO_IMASK_DIO10_S 10U +#define GPIO_IMASK_DIO10_SET 0x00000400U +#define GPIO_IMASK_DIO10_CLR 0x00000000U + +// Field: [9] DIO9 +// +// Interrupt mask for DIO9 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO9 0x00000200U +#define GPIO_IMASK_DIO9_M 0x00000200U +#define GPIO_IMASK_DIO9_S 9U +#define GPIO_IMASK_DIO9_SET 0x00000200U +#define GPIO_IMASK_DIO9_CLR 0x00000000U + +// Field: [8] DIO8 +// +// Interrupt mask for DIO8 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO8 0x00000100U +#define GPIO_IMASK_DIO8_M 0x00000100U +#define GPIO_IMASK_DIO8_S 8U +#define GPIO_IMASK_DIO8_SET 0x00000100U +#define GPIO_IMASK_DIO8_CLR 0x00000000U + +// Field: [7] DIO7 +// +// Interrupt mask for DIO7 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO7 0x00000080U +#define GPIO_IMASK_DIO7_M 0x00000080U +#define GPIO_IMASK_DIO7_S 7U +#define GPIO_IMASK_DIO7_SET 0x00000080U +#define GPIO_IMASK_DIO7_CLR 0x00000000U + +// Field: [6] DIO6 +// +// Interrupt mask for DIO6 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO6 0x00000040U +#define GPIO_IMASK_DIO6_M 0x00000040U +#define GPIO_IMASK_DIO6_S 6U +#define GPIO_IMASK_DIO6_SET 0x00000040U +#define GPIO_IMASK_DIO6_CLR 0x00000000U + +// Field: [5] DIO5 +// +// Interrupt mask for DIO5 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO5 0x00000020U +#define GPIO_IMASK_DIO5_M 0x00000020U +#define GPIO_IMASK_DIO5_S 5U +#define GPIO_IMASK_DIO5_SET 0x00000020U +#define GPIO_IMASK_DIO5_CLR 0x00000000U + +// Field: [4] DIO4 +// +// Interrupt mask for DIO4 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO4 0x00000010U +#define GPIO_IMASK_DIO4_M 0x00000010U +#define GPIO_IMASK_DIO4_S 4U +#define GPIO_IMASK_DIO4_SET 0x00000010U +#define GPIO_IMASK_DIO4_CLR 0x00000000U + +// Field: [3] DIO3 +// +// Interrupt mask for DIO3 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO3 0x00000008U +#define GPIO_IMASK_DIO3_M 0x00000008U +#define GPIO_IMASK_DIO3_S 3U +#define GPIO_IMASK_DIO3_SET 0x00000008U +#define GPIO_IMASK_DIO3_CLR 0x00000000U + +// Field: [2] DIO2 +// +// Interrupt mask for DIO2 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO2 0x00000004U +#define GPIO_IMASK_DIO2_M 0x00000004U +#define GPIO_IMASK_DIO2_S 2U +#define GPIO_IMASK_DIO2_SET 0x00000004U +#define GPIO_IMASK_DIO2_CLR 0x00000000U + +// Field: [1] DIO1 +// +// Interrupt mask for DIO1 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO1 0x00000002U +#define GPIO_IMASK_DIO1_M 0x00000002U +#define GPIO_IMASK_DIO1_S 1U +#define GPIO_IMASK_DIO1_SET 0x00000002U +#define GPIO_IMASK_DIO1_CLR 0x00000000U + +// Field: [0] DIO0 +// +// Interrupt mask for DIO0 +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define GPIO_IMASK_DIO0 0x00000001U +#define GPIO_IMASK_DIO0_M 0x00000001U +#define GPIO_IMASK_DIO0_S 0U +#define GPIO_IMASK_DIO0_SET 0x00000001U +#define GPIO_IMASK_DIO0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_RIS +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Raw interrupt flag for DIO25 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO25 0x02000000U +#define GPIO_RIS_DIO25_M 0x02000000U +#define GPIO_RIS_DIO25_S 25U +#define GPIO_RIS_DIO25_SET 0x02000000U +#define GPIO_RIS_DIO25_CLR 0x00000000U + +// Field: [24] DIO24 +// +// Raw interrupt flag for DIO24 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO24 0x01000000U +#define GPIO_RIS_DIO24_M 0x01000000U +#define GPIO_RIS_DIO24_S 24U +#define GPIO_RIS_DIO24_SET 0x01000000U +#define GPIO_RIS_DIO24_CLR 0x00000000U + +// Field: [23] DIO23 +// +// Raw interrupt flag for DIO23 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO23 0x00800000U +#define GPIO_RIS_DIO23_M 0x00800000U +#define GPIO_RIS_DIO23_S 23U +#define GPIO_RIS_DIO23_SET 0x00800000U +#define GPIO_RIS_DIO23_CLR 0x00000000U + +// Field: [22] DIO22 +// +// Raw interrupt flag for DIO22 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO22 0x00400000U +#define GPIO_RIS_DIO22_M 0x00400000U +#define GPIO_RIS_DIO22_S 22U +#define GPIO_RIS_DIO22_SET 0x00400000U +#define GPIO_RIS_DIO22_CLR 0x00000000U + +// Field: [21] DIO21 +// +// Raw interrupt flag for DIO21 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO21 0x00200000U +#define GPIO_RIS_DIO21_M 0x00200000U +#define GPIO_RIS_DIO21_S 21U +#define GPIO_RIS_DIO21_SET 0x00200000U +#define GPIO_RIS_DIO21_CLR 0x00000000U + +// Field: [20] DIO20 +// +// Raw interrupt flag for DIO20 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO20 0x00100000U +#define GPIO_RIS_DIO20_M 0x00100000U +#define GPIO_RIS_DIO20_S 20U +#define GPIO_RIS_DIO20_SET 0x00100000U +#define GPIO_RIS_DIO20_CLR 0x00000000U + +// Field: [19] DIO19 +// +// Raw interrupt flag for DIO19 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO19 0x00080000U +#define GPIO_RIS_DIO19_M 0x00080000U +#define GPIO_RIS_DIO19_S 19U +#define GPIO_RIS_DIO19_SET 0x00080000U +#define GPIO_RIS_DIO19_CLR 0x00000000U + +// Field: [18] DIO18 +// +// Raw interrupt flag for DIO18 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO18 0x00040000U +#define GPIO_RIS_DIO18_M 0x00040000U +#define GPIO_RIS_DIO18_S 18U +#define GPIO_RIS_DIO18_SET 0x00040000U +#define GPIO_RIS_DIO18_CLR 0x00000000U + +// Field: [17] DIO17 +// +// Raw interrupt flag for DIO17 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO17 0x00020000U +#define GPIO_RIS_DIO17_M 0x00020000U +#define GPIO_RIS_DIO17_S 17U +#define GPIO_RIS_DIO17_SET 0x00020000U +#define GPIO_RIS_DIO17_CLR 0x00000000U + +// Field: [16] DIO16 +// +// Raw interrupt flag for DIO16 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO16 0x00010000U +#define GPIO_RIS_DIO16_M 0x00010000U +#define GPIO_RIS_DIO16_S 16U +#define GPIO_RIS_DIO16_SET 0x00010000U +#define GPIO_RIS_DIO16_CLR 0x00000000U + +// Field: [15] DIO15 +// +// Raw interrupt flag for DIO15 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO15 0x00008000U +#define GPIO_RIS_DIO15_M 0x00008000U +#define GPIO_RIS_DIO15_S 15U +#define GPIO_RIS_DIO15_SET 0x00008000U +#define GPIO_RIS_DIO15_CLR 0x00000000U + +// Field: [14] DIO14 +// +// Raw interrupt flag for DIO14 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO14 0x00004000U +#define GPIO_RIS_DIO14_M 0x00004000U +#define GPIO_RIS_DIO14_S 14U +#define GPIO_RIS_DIO14_SET 0x00004000U +#define GPIO_RIS_DIO14_CLR 0x00000000U + +// Field: [13] DIO13 +// +// Raw interrupt flag for DIO13 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO13 0x00002000U +#define GPIO_RIS_DIO13_M 0x00002000U +#define GPIO_RIS_DIO13_S 13U +#define GPIO_RIS_DIO13_SET 0x00002000U +#define GPIO_RIS_DIO13_CLR 0x00000000U + +// Field: [12] DIO12 +// +// Raw interrupt flag for DIO12 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO12 0x00001000U +#define GPIO_RIS_DIO12_M 0x00001000U +#define GPIO_RIS_DIO12_S 12U +#define GPIO_RIS_DIO12_SET 0x00001000U +#define GPIO_RIS_DIO12_CLR 0x00000000U + +// Field: [11] DIO11 +// +// Raw interrupt flag for DIO11 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO11 0x00000800U +#define GPIO_RIS_DIO11_M 0x00000800U +#define GPIO_RIS_DIO11_S 11U +#define GPIO_RIS_DIO11_SET 0x00000800U +#define GPIO_RIS_DIO11_CLR 0x00000000U + +// Field: [10] DIO10 +// +// Raw interrupt flag for DIO10 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO10 0x00000400U +#define GPIO_RIS_DIO10_M 0x00000400U +#define GPIO_RIS_DIO10_S 10U +#define GPIO_RIS_DIO10_SET 0x00000400U +#define GPIO_RIS_DIO10_CLR 0x00000000U + +// Field: [9] DIO9 +// +// Raw interrupt flag for DIO9 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO9 0x00000200U +#define GPIO_RIS_DIO9_M 0x00000200U +#define GPIO_RIS_DIO9_S 9U +#define GPIO_RIS_DIO9_SET 0x00000200U +#define GPIO_RIS_DIO9_CLR 0x00000000U + +// Field: [8] DIO8 +// +// Raw interrupt flag for DIO8 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO8 0x00000100U +#define GPIO_RIS_DIO8_M 0x00000100U +#define GPIO_RIS_DIO8_S 8U +#define GPIO_RIS_DIO8_SET 0x00000100U +#define GPIO_RIS_DIO8_CLR 0x00000000U + +// Field: [7] DIO7 +// +// Raw interrupt flag for DIO7 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO7 0x00000080U +#define GPIO_RIS_DIO7_M 0x00000080U +#define GPIO_RIS_DIO7_S 7U +#define GPIO_RIS_DIO7_SET 0x00000080U +#define GPIO_RIS_DIO7_CLR 0x00000000U + +// Field: [6] DIO6 +// +// Raw interrupt flag for DIO6 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO6 0x00000040U +#define GPIO_RIS_DIO6_M 0x00000040U +#define GPIO_RIS_DIO6_S 6U +#define GPIO_RIS_DIO6_SET 0x00000040U +#define GPIO_RIS_DIO6_CLR 0x00000000U + +// Field: [5] DIO5 +// +// Raw interrupt flag for DIO5 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO5 0x00000020U +#define GPIO_RIS_DIO5_M 0x00000020U +#define GPIO_RIS_DIO5_S 5U +#define GPIO_RIS_DIO5_SET 0x00000020U +#define GPIO_RIS_DIO5_CLR 0x00000000U + +// Field: [4] DIO4 +// +// Raw interrupt flag for DIO4 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO4 0x00000010U +#define GPIO_RIS_DIO4_M 0x00000010U +#define GPIO_RIS_DIO4_S 4U +#define GPIO_RIS_DIO4_SET 0x00000010U +#define GPIO_RIS_DIO4_CLR 0x00000000U + +// Field: [3] DIO3 +// +// Raw interrupt flag for DIO3 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO3 0x00000008U +#define GPIO_RIS_DIO3_M 0x00000008U +#define GPIO_RIS_DIO3_S 3U +#define GPIO_RIS_DIO3_SET 0x00000008U +#define GPIO_RIS_DIO3_CLR 0x00000000U + +// Field: [2] DIO2 +// +// Raw interrupt flag for DIO2 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO2 0x00000004U +#define GPIO_RIS_DIO2_M 0x00000004U +#define GPIO_RIS_DIO2_S 2U +#define GPIO_RIS_DIO2_SET 0x00000004U +#define GPIO_RIS_DIO2_CLR 0x00000000U + +// Field: [1] DIO1 +// +// Raw interrupt flag for DIO1 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO1 0x00000002U +#define GPIO_RIS_DIO1_M 0x00000002U +#define GPIO_RIS_DIO1_S 1U +#define GPIO_RIS_DIO1_SET 0x00000002U +#define GPIO_RIS_DIO1_CLR 0x00000000U + +// Field: [0] DIO0 +// +// Raw interrupt flag for DIO0 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_RIS_DIO0 0x00000001U +#define GPIO_RIS_DIO0_M 0x00000001U +#define GPIO_RIS_DIO0_S 0U +#define GPIO_RIS_DIO0_SET 0x00000001U +#define GPIO_RIS_DIO0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_MIS +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Masked interrupt flag for DIO25 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO25 0x02000000U +#define GPIO_MIS_DIO25_M 0x02000000U +#define GPIO_MIS_DIO25_S 25U +#define GPIO_MIS_DIO25_SET 0x02000000U +#define GPIO_MIS_DIO25_CLR 0x00000000U + +// Field: [24] DIO24 +// +// Masked interrupt flag for DIO24 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO24 0x01000000U +#define GPIO_MIS_DIO24_M 0x01000000U +#define GPIO_MIS_DIO24_S 24U +#define GPIO_MIS_DIO24_SET 0x01000000U +#define GPIO_MIS_DIO24_CLR 0x00000000U + +// Field: [23] DIO23 +// +// Masked interrupt flag for DIO23 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO23 0x00800000U +#define GPIO_MIS_DIO23_M 0x00800000U +#define GPIO_MIS_DIO23_S 23U +#define GPIO_MIS_DIO23_SET 0x00800000U +#define GPIO_MIS_DIO23_CLR 0x00000000U + +// Field: [22] DIO22 +// +// Masked interrupt flag for DIO22 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO22 0x00400000U +#define GPIO_MIS_DIO22_M 0x00400000U +#define GPIO_MIS_DIO22_S 22U +#define GPIO_MIS_DIO22_SET 0x00400000U +#define GPIO_MIS_DIO22_CLR 0x00000000U + +// Field: [21] DIO21 +// +// Masked interrupt flag for DIO21 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO21 0x00200000U +#define GPIO_MIS_DIO21_M 0x00200000U +#define GPIO_MIS_DIO21_S 21U +#define GPIO_MIS_DIO21_SET 0x00200000U +#define GPIO_MIS_DIO21_CLR 0x00000000U + +// Field: [20] DIO20 +// +// Masked interrupt flag for DIO20 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO20 0x00100000U +#define GPIO_MIS_DIO20_M 0x00100000U +#define GPIO_MIS_DIO20_S 20U +#define GPIO_MIS_DIO20_SET 0x00100000U +#define GPIO_MIS_DIO20_CLR 0x00000000U + +// Field: [19] DIO19 +// +// Masked interrupt flag for DIO19 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO19 0x00080000U +#define GPIO_MIS_DIO19_M 0x00080000U +#define GPIO_MIS_DIO19_S 19U +#define GPIO_MIS_DIO19_SET 0x00080000U +#define GPIO_MIS_DIO19_CLR 0x00000000U + +// Field: [18] DIO18 +// +// Masked interrupt flag for DIO18 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO18 0x00040000U +#define GPIO_MIS_DIO18_M 0x00040000U +#define GPIO_MIS_DIO18_S 18U +#define GPIO_MIS_DIO18_SET 0x00040000U +#define GPIO_MIS_DIO18_CLR 0x00000000U + +// Field: [17] DIO17 +// +// Masked interrupt flag for DIO17 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO17 0x00020000U +#define GPIO_MIS_DIO17_M 0x00020000U +#define GPIO_MIS_DIO17_S 17U +#define GPIO_MIS_DIO17_SET 0x00020000U +#define GPIO_MIS_DIO17_CLR 0x00000000U + +// Field: [16] DIO16 +// +// Masked interrupt flag for DIO16 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO16 0x00010000U +#define GPIO_MIS_DIO16_M 0x00010000U +#define GPIO_MIS_DIO16_S 16U +#define GPIO_MIS_DIO16_SET 0x00010000U +#define GPIO_MIS_DIO16_CLR 0x00000000U + +// Field: [15] DIO15 +// +// Masked interrupt flag for DIO15 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO15 0x00008000U +#define GPIO_MIS_DIO15_M 0x00008000U +#define GPIO_MIS_DIO15_S 15U +#define GPIO_MIS_DIO15_SET 0x00008000U +#define GPIO_MIS_DIO15_CLR 0x00000000U + +// Field: [14] DIO14 +// +// Masked interrupt flag for DIO14 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO14 0x00004000U +#define GPIO_MIS_DIO14_M 0x00004000U +#define GPIO_MIS_DIO14_S 14U +#define GPIO_MIS_DIO14_SET 0x00004000U +#define GPIO_MIS_DIO14_CLR 0x00000000U + +// Field: [13] DIO13 +// +// Masked interrupt flag for DIO13 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO13 0x00002000U +#define GPIO_MIS_DIO13_M 0x00002000U +#define GPIO_MIS_DIO13_S 13U +#define GPIO_MIS_DIO13_SET 0x00002000U +#define GPIO_MIS_DIO13_CLR 0x00000000U + +// Field: [12] DIO12 +// +// Masked interrupt flag for DIO12 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO12 0x00001000U +#define GPIO_MIS_DIO12_M 0x00001000U +#define GPIO_MIS_DIO12_S 12U +#define GPIO_MIS_DIO12_SET 0x00001000U +#define GPIO_MIS_DIO12_CLR 0x00000000U + +// Field: [11] DIO11 +// +// Masked interrupt flag for DIO11 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO11 0x00000800U +#define GPIO_MIS_DIO11_M 0x00000800U +#define GPIO_MIS_DIO11_S 11U +#define GPIO_MIS_DIO11_SET 0x00000800U +#define GPIO_MIS_DIO11_CLR 0x00000000U + +// Field: [10] DIO10 +// +// Masked interrupt flag for DIO10 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO10 0x00000400U +#define GPIO_MIS_DIO10_M 0x00000400U +#define GPIO_MIS_DIO10_S 10U +#define GPIO_MIS_DIO10_SET 0x00000400U +#define GPIO_MIS_DIO10_CLR 0x00000000U + +// Field: [9] DIO9 +// +// Masked interrupt flag for DIO9 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO9 0x00000200U +#define GPIO_MIS_DIO9_M 0x00000200U +#define GPIO_MIS_DIO9_S 9U +#define GPIO_MIS_DIO9_SET 0x00000200U +#define GPIO_MIS_DIO9_CLR 0x00000000U + +// Field: [8] DIO8 +// +// Masked interrupt flag for DIO8 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO8 0x00000100U +#define GPIO_MIS_DIO8_M 0x00000100U +#define GPIO_MIS_DIO8_S 8U +#define GPIO_MIS_DIO8_SET 0x00000100U +#define GPIO_MIS_DIO8_CLR 0x00000000U + +// Field: [7] DIO7 +// +// Masked interrupt flag for DIO7 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO7 0x00000080U +#define GPIO_MIS_DIO7_M 0x00000080U +#define GPIO_MIS_DIO7_S 7U +#define GPIO_MIS_DIO7_SET 0x00000080U +#define GPIO_MIS_DIO7_CLR 0x00000000U + +// Field: [6] DIO6 +// +// Masked interrupt flag for DIO6 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO6 0x00000040U +#define GPIO_MIS_DIO6_M 0x00000040U +#define GPIO_MIS_DIO6_S 6U +#define GPIO_MIS_DIO6_SET 0x00000040U +#define GPIO_MIS_DIO6_CLR 0x00000000U + +// Field: [5] DIO5 +// +// Masked interrupt flag for DIO5 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO5 0x00000020U +#define GPIO_MIS_DIO5_M 0x00000020U +#define GPIO_MIS_DIO5_S 5U +#define GPIO_MIS_DIO5_SET 0x00000020U +#define GPIO_MIS_DIO5_CLR 0x00000000U + +// Field: [4] DIO4 +// +// Masked interrupt flag for DIO4 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO4 0x00000010U +#define GPIO_MIS_DIO4_M 0x00000010U +#define GPIO_MIS_DIO4_S 4U +#define GPIO_MIS_DIO4_SET 0x00000010U +#define GPIO_MIS_DIO4_CLR 0x00000000U + +// Field: [3] DIO3 +// +// Masked interrupt flag for DIO3 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO3 0x00000008U +#define GPIO_MIS_DIO3_M 0x00000008U +#define GPIO_MIS_DIO3_S 3U +#define GPIO_MIS_DIO3_SET 0x00000008U +#define GPIO_MIS_DIO3_CLR 0x00000000U + +// Field: [2] DIO2 +// +// Masked interrupt flag for DIO2 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO2 0x00000004U +#define GPIO_MIS_DIO2_M 0x00000004U +#define GPIO_MIS_DIO2_S 2U +#define GPIO_MIS_DIO2_SET 0x00000004U +#define GPIO_MIS_DIO2_CLR 0x00000000U + +// Field: [1] DIO1 +// +// Masked interrupt flag for DIO1 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO1 0x00000002U +#define GPIO_MIS_DIO1_M 0x00000002U +#define GPIO_MIS_DIO1_S 1U +#define GPIO_MIS_DIO1_SET 0x00000002U +#define GPIO_MIS_DIO1_CLR 0x00000000U + +// Field: [0] DIO0 +// +// Masked interrupt flag for DIO0 +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define GPIO_MIS_DIO0 0x00000001U +#define GPIO_MIS_DIO0_M 0x00000001U +#define GPIO_MIS_DIO0_S 0U +#define GPIO_MIS_DIO0_SET 0x00000001U +#define GPIO_MIS_DIO0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_ISET +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Set DIO25 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO25 0x02000000U +#define GPIO_ISET_DIO25_M 0x02000000U +#define GPIO_ISET_DIO25_S 25U +#define GPIO_ISET_DIO25_SET 0x02000000U +#define GPIO_ISET_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Set DIO24 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO24 0x01000000U +#define GPIO_ISET_DIO24_M 0x01000000U +#define GPIO_ISET_DIO24_S 24U +#define GPIO_ISET_DIO24_SET 0x01000000U +#define GPIO_ISET_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Set DIO23 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO23 0x00800000U +#define GPIO_ISET_DIO23_M 0x00800000U +#define GPIO_ISET_DIO23_S 23U +#define GPIO_ISET_DIO23_SET 0x00800000U +#define GPIO_ISET_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Set DIO22 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO22 0x00400000U +#define GPIO_ISET_DIO22_M 0x00400000U +#define GPIO_ISET_DIO22_S 22U +#define GPIO_ISET_DIO22_SET 0x00400000U +#define GPIO_ISET_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Set DIO21 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO21 0x00200000U +#define GPIO_ISET_DIO21_M 0x00200000U +#define GPIO_ISET_DIO21_S 21U +#define GPIO_ISET_DIO21_SET 0x00200000U +#define GPIO_ISET_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Set DIO20 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO20 0x00100000U +#define GPIO_ISET_DIO20_M 0x00100000U +#define GPIO_ISET_DIO20_S 20U +#define GPIO_ISET_DIO20_SET 0x00100000U +#define GPIO_ISET_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Set DIO19 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO19 0x00080000U +#define GPIO_ISET_DIO19_M 0x00080000U +#define GPIO_ISET_DIO19_S 19U +#define GPIO_ISET_DIO19_SET 0x00080000U +#define GPIO_ISET_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Set DIO18 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO18 0x00040000U +#define GPIO_ISET_DIO18_M 0x00040000U +#define GPIO_ISET_DIO18_S 18U +#define GPIO_ISET_DIO18_SET 0x00040000U +#define GPIO_ISET_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Set DIO17 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO17 0x00020000U +#define GPIO_ISET_DIO17_M 0x00020000U +#define GPIO_ISET_DIO17_S 17U +#define GPIO_ISET_DIO17_SET 0x00020000U +#define GPIO_ISET_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Set DIO16 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO16 0x00010000U +#define GPIO_ISET_DIO16_M 0x00010000U +#define GPIO_ISET_DIO16_S 16U +#define GPIO_ISET_DIO16_SET 0x00010000U +#define GPIO_ISET_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Set DIO15 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO15 0x00008000U +#define GPIO_ISET_DIO15_M 0x00008000U +#define GPIO_ISET_DIO15_S 15U +#define GPIO_ISET_DIO15_SET 0x00008000U +#define GPIO_ISET_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Set DIO14 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO14 0x00004000U +#define GPIO_ISET_DIO14_M 0x00004000U +#define GPIO_ISET_DIO14_S 14U +#define GPIO_ISET_DIO14_SET 0x00004000U +#define GPIO_ISET_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Set DIO13 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO13 0x00002000U +#define GPIO_ISET_DIO13_M 0x00002000U +#define GPIO_ISET_DIO13_S 13U +#define GPIO_ISET_DIO13_SET 0x00002000U +#define GPIO_ISET_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Set DIO12 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO12 0x00001000U +#define GPIO_ISET_DIO12_M 0x00001000U +#define GPIO_ISET_DIO12_S 12U +#define GPIO_ISET_DIO12_SET 0x00001000U +#define GPIO_ISET_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Set DIO11 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO11 0x00000800U +#define GPIO_ISET_DIO11_M 0x00000800U +#define GPIO_ISET_DIO11_S 11U +#define GPIO_ISET_DIO11_SET 0x00000800U +#define GPIO_ISET_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Set DIO10 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO10 0x00000400U +#define GPIO_ISET_DIO10_M 0x00000400U +#define GPIO_ISET_DIO10_S 10U +#define GPIO_ISET_DIO10_SET 0x00000400U +#define GPIO_ISET_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Set DIO9 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO9 0x00000200U +#define GPIO_ISET_DIO9_M 0x00000200U +#define GPIO_ISET_DIO9_S 9U +#define GPIO_ISET_DIO9_SET 0x00000200U +#define GPIO_ISET_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Set DIO8 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO8 0x00000100U +#define GPIO_ISET_DIO8_M 0x00000100U +#define GPIO_ISET_DIO8_S 8U +#define GPIO_ISET_DIO8_SET 0x00000100U +#define GPIO_ISET_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Set DIO7 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO7 0x00000080U +#define GPIO_ISET_DIO7_M 0x00000080U +#define GPIO_ISET_DIO7_S 7U +#define GPIO_ISET_DIO7_SET 0x00000080U +#define GPIO_ISET_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Set DIO6 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO6 0x00000040U +#define GPIO_ISET_DIO6_M 0x00000040U +#define GPIO_ISET_DIO6_S 6U +#define GPIO_ISET_DIO6_SET 0x00000040U +#define GPIO_ISET_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Set DIO5 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO5 0x00000020U +#define GPIO_ISET_DIO5_M 0x00000020U +#define GPIO_ISET_DIO5_S 5U +#define GPIO_ISET_DIO5_SET 0x00000020U +#define GPIO_ISET_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Set DIO4 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO4 0x00000010U +#define GPIO_ISET_DIO4_M 0x00000010U +#define GPIO_ISET_DIO4_S 4U +#define GPIO_ISET_DIO4_SET 0x00000010U +#define GPIO_ISET_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Set DIO3 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO3 0x00000008U +#define GPIO_ISET_DIO3_M 0x00000008U +#define GPIO_ISET_DIO3_S 3U +#define GPIO_ISET_DIO3_SET 0x00000008U +#define GPIO_ISET_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Set DIO2 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO2 0x00000004U +#define GPIO_ISET_DIO2_M 0x00000004U +#define GPIO_ISET_DIO2_S 2U +#define GPIO_ISET_DIO2_SET 0x00000004U +#define GPIO_ISET_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Set DIO1 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO1 0x00000002U +#define GPIO_ISET_DIO1_M 0x00000002U +#define GPIO_ISET_DIO1_S 1U +#define GPIO_ISET_DIO1_SET 0x00000002U +#define GPIO_ISET_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Set DIO0 in RIS +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ISET_DIO0 0x00000001U +#define GPIO_ISET_DIO0_M 0x00000001U +#define GPIO_ISET_DIO0_S 0U +#define GPIO_ISET_DIO0_SET 0x00000001U +#define GPIO_ISET_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_ICLR +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Clears DIO25 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO25 0x02000000U +#define GPIO_ICLR_DIO25_M 0x02000000U +#define GPIO_ICLR_DIO25_S 25U +#define GPIO_ICLR_DIO25_CLR 0x02000000U +#define GPIO_ICLR_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Clears DIO24 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO24 0x01000000U +#define GPIO_ICLR_DIO24_M 0x01000000U +#define GPIO_ICLR_DIO24_S 24U +#define GPIO_ICLR_DIO24_CLR 0x01000000U +#define GPIO_ICLR_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Clears DIO23 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO23 0x00800000U +#define GPIO_ICLR_DIO23_M 0x00800000U +#define GPIO_ICLR_DIO23_S 23U +#define GPIO_ICLR_DIO23_CLR 0x00800000U +#define GPIO_ICLR_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Clears DIO22 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO22 0x00400000U +#define GPIO_ICLR_DIO22_M 0x00400000U +#define GPIO_ICLR_DIO22_S 22U +#define GPIO_ICLR_DIO22_CLR 0x00400000U +#define GPIO_ICLR_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Clears DIO21 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO21 0x00200000U +#define GPIO_ICLR_DIO21_M 0x00200000U +#define GPIO_ICLR_DIO21_S 21U +#define GPIO_ICLR_DIO21_CLR 0x00200000U +#define GPIO_ICLR_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Clears DIO20 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO20 0x00100000U +#define GPIO_ICLR_DIO20_M 0x00100000U +#define GPIO_ICLR_DIO20_S 20U +#define GPIO_ICLR_DIO20_CLR 0x00100000U +#define GPIO_ICLR_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Clears DIO19 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO19 0x00080000U +#define GPIO_ICLR_DIO19_M 0x00080000U +#define GPIO_ICLR_DIO19_S 19U +#define GPIO_ICLR_DIO19_CLR 0x00080000U +#define GPIO_ICLR_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Clears DIO18 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO18 0x00040000U +#define GPIO_ICLR_DIO18_M 0x00040000U +#define GPIO_ICLR_DIO18_S 18U +#define GPIO_ICLR_DIO18_CLR 0x00040000U +#define GPIO_ICLR_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Clears DIO17 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO17 0x00020000U +#define GPIO_ICLR_DIO17_M 0x00020000U +#define GPIO_ICLR_DIO17_S 17U +#define GPIO_ICLR_DIO17_CLR 0x00020000U +#define GPIO_ICLR_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Clears DIO16 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO16 0x00010000U +#define GPIO_ICLR_DIO16_M 0x00010000U +#define GPIO_ICLR_DIO16_S 16U +#define GPIO_ICLR_DIO16_CLR 0x00010000U +#define GPIO_ICLR_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Clears DIO15 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO15 0x00008000U +#define GPIO_ICLR_DIO15_M 0x00008000U +#define GPIO_ICLR_DIO15_S 15U +#define GPIO_ICLR_DIO15_CLR 0x00008000U +#define GPIO_ICLR_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Clears DIO14 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO14 0x00004000U +#define GPIO_ICLR_DIO14_M 0x00004000U +#define GPIO_ICLR_DIO14_S 14U +#define GPIO_ICLR_DIO14_CLR 0x00004000U +#define GPIO_ICLR_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Clears DIO13 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO13 0x00002000U +#define GPIO_ICLR_DIO13_M 0x00002000U +#define GPIO_ICLR_DIO13_S 13U +#define GPIO_ICLR_DIO13_CLR 0x00002000U +#define GPIO_ICLR_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Clears DIO12 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO12 0x00001000U +#define GPIO_ICLR_DIO12_M 0x00001000U +#define GPIO_ICLR_DIO12_S 12U +#define GPIO_ICLR_DIO12_CLR 0x00001000U +#define GPIO_ICLR_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Clears DIO11 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO11 0x00000800U +#define GPIO_ICLR_DIO11_M 0x00000800U +#define GPIO_ICLR_DIO11_S 11U +#define GPIO_ICLR_DIO11_CLR 0x00000800U +#define GPIO_ICLR_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Clears DIO10 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO10 0x00000400U +#define GPIO_ICLR_DIO10_M 0x00000400U +#define GPIO_ICLR_DIO10_S 10U +#define GPIO_ICLR_DIO10_CLR 0x00000400U +#define GPIO_ICLR_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Clears DIO9 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO9 0x00000200U +#define GPIO_ICLR_DIO9_M 0x00000200U +#define GPIO_ICLR_DIO9_S 9U +#define GPIO_ICLR_DIO9_CLR 0x00000200U +#define GPIO_ICLR_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Clears DIO8 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO8 0x00000100U +#define GPIO_ICLR_DIO8_M 0x00000100U +#define GPIO_ICLR_DIO8_S 8U +#define GPIO_ICLR_DIO8_CLR 0x00000100U +#define GPIO_ICLR_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Clears DIO7 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO7 0x00000080U +#define GPIO_ICLR_DIO7_M 0x00000080U +#define GPIO_ICLR_DIO7_S 7U +#define GPIO_ICLR_DIO7_CLR 0x00000080U +#define GPIO_ICLR_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Clears DIO6 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO6 0x00000040U +#define GPIO_ICLR_DIO6_M 0x00000040U +#define GPIO_ICLR_DIO6_S 6U +#define GPIO_ICLR_DIO6_CLR 0x00000040U +#define GPIO_ICLR_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Clears DIO5 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO5 0x00000020U +#define GPIO_ICLR_DIO5_M 0x00000020U +#define GPIO_ICLR_DIO5_S 5U +#define GPIO_ICLR_DIO5_CLR 0x00000020U +#define GPIO_ICLR_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Clears DIO4 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO4 0x00000010U +#define GPIO_ICLR_DIO4_M 0x00000010U +#define GPIO_ICLR_DIO4_S 4U +#define GPIO_ICLR_DIO4_CLR 0x00000010U +#define GPIO_ICLR_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Clears DIO3 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO3 0x00000008U +#define GPIO_ICLR_DIO3_M 0x00000008U +#define GPIO_ICLR_DIO3_S 3U +#define GPIO_ICLR_DIO3_CLR 0x00000008U +#define GPIO_ICLR_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Clears DIO2 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO2 0x00000004U +#define GPIO_ICLR_DIO2_M 0x00000004U +#define GPIO_ICLR_DIO2_S 2U +#define GPIO_ICLR_DIO2_CLR 0x00000004U +#define GPIO_ICLR_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Clears DIO1 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO1 0x00000002U +#define GPIO_ICLR_DIO1_M 0x00000002U +#define GPIO_ICLR_DIO1_S 1U +#define GPIO_ICLR_DIO1_CLR 0x00000002U +#define GPIO_ICLR_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Clears DIO0 in RIS +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define GPIO_ICLR_DIO0 0x00000001U +#define GPIO_ICLR_DIO0_M 0x00000001U +#define GPIO_ICLR_DIO0_S 0U +#define GPIO_ICLR_DIO0_CLR 0x00000001U +#define GPIO_ICLR_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_IMSET +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Sets DIO25 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO25 0x02000000U +#define GPIO_IMSET_DIO25_M 0x02000000U +#define GPIO_IMSET_DIO25_S 25U +#define GPIO_IMSET_DIO25_SET 0x02000000U +#define GPIO_IMSET_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Sets DIO24 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO24 0x01000000U +#define GPIO_IMSET_DIO24_M 0x01000000U +#define GPIO_IMSET_DIO24_S 24U +#define GPIO_IMSET_DIO24_SET 0x01000000U +#define GPIO_IMSET_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Sets DIO23 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO23 0x00800000U +#define GPIO_IMSET_DIO23_M 0x00800000U +#define GPIO_IMSET_DIO23_S 23U +#define GPIO_IMSET_DIO23_SET 0x00800000U +#define GPIO_IMSET_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Sets DIO22 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO22 0x00400000U +#define GPIO_IMSET_DIO22_M 0x00400000U +#define GPIO_IMSET_DIO22_S 22U +#define GPIO_IMSET_DIO22_SET 0x00400000U +#define GPIO_IMSET_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Sets DIO21 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO21 0x00200000U +#define GPIO_IMSET_DIO21_M 0x00200000U +#define GPIO_IMSET_DIO21_S 21U +#define GPIO_IMSET_DIO21_SET 0x00200000U +#define GPIO_IMSET_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Sets DIO20 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO20 0x00100000U +#define GPIO_IMSET_DIO20_M 0x00100000U +#define GPIO_IMSET_DIO20_S 20U +#define GPIO_IMSET_DIO20_SET 0x00100000U +#define GPIO_IMSET_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Sets DIO19 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO19 0x00080000U +#define GPIO_IMSET_DIO19_M 0x00080000U +#define GPIO_IMSET_DIO19_S 19U +#define GPIO_IMSET_DIO19_SET 0x00080000U +#define GPIO_IMSET_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Sets DIO18 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO18 0x00040000U +#define GPIO_IMSET_DIO18_M 0x00040000U +#define GPIO_IMSET_DIO18_S 18U +#define GPIO_IMSET_DIO18_SET 0x00040000U +#define GPIO_IMSET_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Sets DIO17 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO17 0x00020000U +#define GPIO_IMSET_DIO17_M 0x00020000U +#define GPIO_IMSET_DIO17_S 17U +#define GPIO_IMSET_DIO17_SET 0x00020000U +#define GPIO_IMSET_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Sets DIO16 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO16 0x00010000U +#define GPIO_IMSET_DIO16_M 0x00010000U +#define GPIO_IMSET_DIO16_S 16U +#define GPIO_IMSET_DIO16_SET 0x00010000U +#define GPIO_IMSET_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Sets DIO15 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO15 0x00008000U +#define GPIO_IMSET_DIO15_M 0x00008000U +#define GPIO_IMSET_DIO15_S 15U +#define GPIO_IMSET_DIO15_SET 0x00008000U +#define GPIO_IMSET_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Sets DIO14 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO14 0x00004000U +#define GPIO_IMSET_DIO14_M 0x00004000U +#define GPIO_IMSET_DIO14_S 14U +#define GPIO_IMSET_DIO14_SET 0x00004000U +#define GPIO_IMSET_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Sets DIO13 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO13 0x00002000U +#define GPIO_IMSET_DIO13_M 0x00002000U +#define GPIO_IMSET_DIO13_S 13U +#define GPIO_IMSET_DIO13_SET 0x00002000U +#define GPIO_IMSET_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Sets DIO12 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO12 0x00001000U +#define GPIO_IMSET_DIO12_M 0x00001000U +#define GPIO_IMSET_DIO12_S 12U +#define GPIO_IMSET_DIO12_SET 0x00001000U +#define GPIO_IMSET_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Sets DIO11 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO11 0x00000800U +#define GPIO_IMSET_DIO11_M 0x00000800U +#define GPIO_IMSET_DIO11_S 11U +#define GPIO_IMSET_DIO11_SET 0x00000800U +#define GPIO_IMSET_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Sets DIO10 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO10 0x00000400U +#define GPIO_IMSET_DIO10_M 0x00000400U +#define GPIO_IMSET_DIO10_S 10U +#define GPIO_IMSET_DIO10_SET 0x00000400U +#define GPIO_IMSET_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Sets DIO9 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO9 0x00000200U +#define GPIO_IMSET_DIO9_M 0x00000200U +#define GPIO_IMSET_DIO9_S 9U +#define GPIO_IMSET_DIO9_SET 0x00000200U +#define GPIO_IMSET_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Sets DIO8 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO8 0x00000100U +#define GPIO_IMSET_DIO8_M 0x00000100U +#define GPIO_IMSET_DIO8_S 8U +#define GPIO_IMSET_DIO8_SET 0x00000100U +#define GPIO_IMSET_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Sets DIO7 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO7 0x00000080U +#define GPIO_IMSET_DIO7_M 0x00000080U +#define GPIO_IMSET_DIO7_S 7U +#define GPIO_IMSET_DIO7_SET 0x00000080U +#define GPIO_IMSET_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Sets DIO6 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO6 0x00000040U +#define GPIO_IMSET_DIO6_M 0x00000040U +#define GPIO_IMSET_DIO6_S 6U +#define GPIO_IMSET_DIO6_SET 0x00000040U +#define GPIO_IMSET_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Sets DIO5 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO5 0x00000020U +#define GPIO_IMSET_DIO5_M 0x00000020U +#define GPIO_IMSET_DIO5_S 5U +#define GPIO_IMSET_DIO5_SET 0x00000020U +#define GPIO_IMSET_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Sets DIO4 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO4 0x00000010U +#define GPIO_IMSET_DIO4_M 0x00000010U +#define GPIO_IMSET_DIO4_S 4U +#define GPIO_IMSET_DIO4_SET 0x00000010U +#define GPIO_IMSET_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Sets DIO3 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO3 0x00000008U +#define GPIO_IMSET_DIO3_M 0x00000008U +#define GPIO_IMSET_DIO3_S 3U +#define GPIO_IMSET_DIO3_SET 0x00000008U +#define GPIO_IMSET_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Sets DIO2 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO2 0x00000004U +#define GPIO_IMSET_DIO2_M 0x00000004U +#define GPIO_IMSET_DIO2_S 2U +#define GPIO_IMSET_DIO2_SET 0x00000004U +#define GPIO_IMSET_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Sets DIO1 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO1 0x00000002U +#define GPIO_IMSET_DIO1_M 0x00000002U +#define GPIO_IMSET_DIO1_S 1U +#define GPIO_IMSET_DIO1_SET 0x00000002U +#define GPIO_IMSET_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Sets DIO0 in IMASK +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMSET_DIO0 0x00000001U +#define GPIO_IMSET_DIO0_M 0x00000001U +#define GPIO_IMSET_DIO0_S 0U +#define GPIO_IMSET_DIO0_SET 0x00000001U +#define GPIO_IMSET_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_IMCLR +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Clears DIO25 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO25 0x02000000U +#define GPIO_IMCLR_DIO25_M 0x02000000U +#define GPIO_IMCLR_DIO25_S 25U +#define GPIO_IMCLR_DIO25_CLR 0x02000000U +#define GPIO_IMCLR_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Clears DIO24 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO24 0x01000000U +#define GPIO_IMCLR_DIO24_M 0x01000000U +#define GPIO_IMCLR_DIO24_S 24U +#define GPIO_IMCLR_DIO24_CLR 0x01000000U +#define GPIO_IMCLR_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Clears DIO23 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO23 0x00800000U +#define GPIO_IMCLR_DIO23_M 0x00800000U +#define GPIO_IMCLR_DIO23_S 23U +#define GPIO_IMCLR_DIO23_CLR 0x00800000U +#define GPIO_IMCLR_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Clears DIO22 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO22 0x00400000U +#define GPIO_IMCLR_DIO22_M 0x00400000U +#define GPIO_IMCLR_DIO22_S 22U +#define GPIO_IMCLR_DIO22_CLR 0x00400000U +#define GPIO_IMCLR_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Clears DIO21 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO21 0x00200000U +#define GPIO_IMCLR_DIO21_M 0x00200000U +#define GPIO_IMCLR_DIO21_S 21U +#define GPIO_IMCLR_DIO21_CLR 0x00200000U +#define GPIO_IMCLR_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Clears DIO20 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO20 0x00100000U +#define GPIO_IMCLR_DIO20_M 0x00100000U +#define GPIO_IMCLR_DIO20_S 20U +#define GPIO_IMCLR_DIO20_CLR 0x00100000U +#define GPIO_IMCLR_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Clears DIO19 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO19 0x00080000U +#define GPIO_IMCLR_DIO19_M 0x00080000U +#define GPIO_IMCLR_DIO19_S 19U +#define GPIO_IMCLR_DIO19_CLR 0x00080000U +#define GPIO_IMCLR_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Clears DIO18 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO18 0x00040000U +#define GPIO_IMCLR_DIO18_M 0x00040000U +#define GPIO_IMCLR_DIO18_S 18U +#define GPIO_IMCLR_DIO18_CLR 0x00040000U +#define GPIO_IMCLR_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Clears DIO17 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO17 0x00020000U +#define GPIO_IMCLR_DIO17_M 0x00020000U +#define GPIO_IMCLR_DIO17_S 17U +#define GPIO_IMCLR_DIO17_CLR 0x00020000U +#define GPIO_IMCLR_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Clears DIO16 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO16 0x00010000U +#define GPIO_IMCLR_DIO16_M 0x00010000U +#define GPIO_IMCLR_DIO16_S 16U +#define GPIO_IMCLR_DIO16_CLR 0x00010000U +#define GPIO_IMCLR_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Clears DIO15 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO15 0x00008000U +#define GPIO_IMCLR_DIO15_M 0x00008000U +#define GPIO_IMCLR_DIO15_S 15U +#define GPIO_IMCLR_DIO15_CLR 0x00008000U +#define GPIO_IMCLR_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Clears DIO14 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO14 0x00004000U +#define GPIO_IMCLR_DIO14_M 0x00004000U +#define GPIO_IMCLR_DIO14_S 14U +#define GPIO_IMCLR_DIO14_CLR 0x00004000U +#define GPIO_IMCLR_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Clears DIO13 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO13 0x00002000U +#define GPIO_IMCLR_DIO13_M 0x00002000U +#define GPIO_IMCLR_DIO13_S 13U +#define GPIO_IMCLR_DIO13_CLR 0x00002000U +#define GPIO_IMCLR_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Clears DIO12 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO12 0x00001000U +#define GPIO_IMCLR_DIO12_M 0x00001000U +#define GPIO_IMCLR_DIO12_S 12U +#define GPIO_IMCLR_DIO12_CLR 0x00001000U +#define GPIO_IMCLR_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Clears DIO11 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO11 0x00000800U +#define GPIO_IMCLR_DIO11_M 0x00000800U +#define GPIO_IMCLR_DIO11_S 11U +#define GPIO_IMCLR_DIO11_CLR 0x00000800U +#define GPIO_IMCLR_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Clears DIO10 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO10 0x00000400U +#define GPIO_IMCLR_DIO10_M 0x00000400U +#define GPIO_IMCLR_DIO10_S 10U +#define GPIO_IMCLR_DIO10_CLR 0x00000400U +#define GPIO_IMCLR_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Clears DIO9 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO9 0x00000200U +#define GPIO_IMCLR_DIO9_M 0x00000200U +#define GPIO_IMCLR_DIO9_S 9U +#define GPIO_IMCLR_DIO9_CLR 0x00000200U +#define GPIO_IMCLR_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Clears DIO8 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO8 0x00000100U +#define GPIO_IMCLR_DIO8_M 0x00000100U +#define GPIO_IMCLR_DIO8_S 8U +#define GPIO_IMCLR_DIO8_CLR 0x00000100U +#define GPIO_IMCLR_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Clears DIO7 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO7 0x00000080U +#define GPIO_IMCLR_DIO7_M 0x00000080U +#define GPIO_IMCLR_DIO7_S 7U +#define GPIO_IMCLR_DIO7_CLR 0x00000080U +#define GPIO_IMCLR_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Clears DIO6 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO6 0x00000040U +#define GPIO_IMCLR_DIO6_M 0x00000040U +#define GPIO_IMCLR_DIO6_S 6U +#define GPIO_IMCLR_DIO6_CLR 0x00000040U +#define GPIO_IMCLR_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Clears DIO5 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO5 0x00000020U +#define GPIO_IMCLR_DIO5_M 0x00000020U +#define GPIO_IMCLR_DIO5_S 5U +#define GPIO_IMCLR_DIO5_CLR 0x00000020U +#define GPIO_IMCLR_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Clears DIO4 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO4 0x00000010U +#define GPIO_IMCLR_DIO4_M 0x00000010U +#define GPIO_IMCLR_DIO4_S 4U +#define GPIO_IMCLR_DIO4_CLR 0x00000010U +#define GPIO_IMCLR_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Clears DIO3 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO3 0x00000008U +#define GPIO_IMCLR_DIO3_M 0x00000008U +#define GPIO_IMCLR_DIO3_S 3U +#define GPIO_IMCLR_DIO3_CLR 0x00000008U +#define GPIO_IMCLR_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Clears DIO2 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO2 0x00000004U +#define GPIO_IMCLR_DIO2_M 0x00000004U +#define GPIO_IMCLR_DIO2_S 2U +#define GPIO_IMCLR_DIO2_CLR 0x00000004U +#define GPIO_IMCLR_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Clears DIO1 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO1 0x00000002U +#define GPIO_IMCLR_DIO1_M 0x00000002U +#define GPIO_IMCLR_DIO1_S 1U +#define GPIO_IMCLR_DIO1_CLR 0x00000002U +#define GPIO_IMCLR_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Clears DIO0 in IMASK +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define GPIO_IMCLR_DIO0 0x00000001U +#define GPIO_IMCLR_DIO0_M 0x00000001U +#define GPIO_IMCLR_DIO0_S 0U +#define GPIO_IMCLR_DIO0_CLR 0x00000001U +#define GPIO_IMCLR_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Data output for DIO3 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT3_0_DIO3 0x01000000U +#define GPIO_DOUT3_0_DIO3_M 0x01000000U +#define GPIO_DOUT3_0_DIO3_S 24U +#define GPIO_DOUT3_0_DIO3_ONE 0x01000000U +#define GPIO_DOUT3_0_DIO3_ZERO 0x00000000U + +// Field: [16] DIO2 +// +// Data output for DIO2 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT3_0_DIO2 0x00010000U +#define GPIO_DOUT3_0_DIO2_M 0x00010000U +#define GPIO_DOUT3_0_DIO2_S 16U +#define GPIO_DOUT3_0_DIO2_ONE 0x00010000U +#define GPIO_DOUT3_0_DIO2_ZERO 0x00000000U + +// Field: [8] DIO1 +// +// Data output for DIO1 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT3_0_DIO1 0x00000100U +#define GPIO_DOUT3_0_DIO1_M 0x00000100U +#define GPIO_DOUT3_0_DIO1_S 8U +#define GPIO_DOUT3_0_DIO1_ONE 0x00000100U +#define GPIO_DOUT3_0_DIO1_ZERO 0x00000000U + +// Field: [0] DIO0 +// +// Data output for DIO0 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT3_0_DIO0 0x00000001U +#define GPIO_DOUT3_0_DIO0_M 0x00000001U +#define GPIO_DOUT3_0_DIO0_S 0U +#define GPIO_DOUT3_0_DIO0_ONE 0x00000001U +#define GPIO_DOUT3_0_DIO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Data output for DIO7 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT7_4_DIO7 0x01000000U +#define GPIO_DOUT7_4_DIO7_M 0x01000000U +#define GPIO_DOUT7_4_DIO7_S 24U +#define GPIO_DOUT7_4_DIO7_ONE 0x01000000U +#define GPIO_DOUT7_4_DIO7_ZERO 0x00000000U + +// Field: [16] DIO6 +// +// Data output for DIO6 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT7_4_DIO6 0x00010000U +#define GPIO_DOUT7_4_DIO6_M 0x00010000U +#define GPIO_DOUT7_4_DIO6_S 16U +#define GPIO_DOUT7_4_DIO6_ONE 0x00010000U +#define GPIO_DOUT7_4_DIO6_ZERO 0x00000000U + +// Field: [8] DIO5 +// +// Data output for DIO5 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT7_4_DIO5 0x00000100U +#define GPIO_DOUT7_4_DIO5_M 0x00000100U +#define GPIO_DOUT7_4_DIO5_S 8U +#define GPIO_DOUT7_4_DIO5_ONE 0x00000100U +#define GPIO_DOUT7_4_DIO5_ZERO 0x00000000U + +// Field: [0] DIO4 +// +// Data output for DIO4 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT7_4_DIO4 0x00000001U +#define GPIO_DOUT7_4_DIO4_M 0x00000001U +#define GPIO_DOUT7_4_DIO4_S 0U +#define GPIO_DOUT7_4_DIO4_ONE 0x00000001U +#define GPIO_DOUT7_4_DIO4_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Data output for DIO11 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT11_8_DIO11 0x01000000U +#define GPIO_DOUT11_8_DIO11_M 0x01000000U +#define GPIO_DOUT11_8_DIO11_S 24U +#define GPIO_DOUT11_8_DIO11_ONE 0x01000000U +#define GPIO_DOUT11_8_DIO11_ZERO 0x00000000U + +// Field: [16] DIO10 +// +// Data output for DIO10 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT11_8_DIO10 0x00010000U +#define GPIO_DOUT11_8_DIO10_M 0x00010000U +#define GPIO_DOUT11_8_DIO10_S 16U +#define GPIO_DOUT11_8_DIO10_ONE 0x00010000U +#define GPIO_DOUT11_8_DIO10_ZERO 0x00000000U + +// Field: [8] DIO9 +// +// Data output for DIO9 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT11_8_DIO9 0x00000100U +#define GPIO_DOUT11_8_DIO9_M 0x00000100U +#define GPIO_DOUT11_8_DIO9_S 8U +#define GPIO_DOUT11_8_DIO9_ONE 0x00000100U +#define GPIO_DOUT11_8_DIO9_ZERO 0x00000000U + +// Field: [0] DIO8 +// +// Data output for DIO8 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT11_8_DIO8 0x00000001U +#define GPIO_DOUT11_8_DIO8_M 0x00000001U +#define GPIO_DOUT11_8_DIO8_S 0U +#define GPIO_DOUT11_8_DIO8_ONE 0x00000001U +#define GPIO_DOUT11_8_DIO8_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Data output for DIO15 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT15_12_DIO15 0x01000000U +#define GPIO_DOUT15_12_DIO15_M 0x01000000U +#define GPIO_DOUT15_12_DIO15_S 24U +#define GPIO_DOUT15_12_DIO15_ONE 0x01000000U +#define GPIO_DOUT15_12_DIO15_ZERO 0x00000000U + +// Field: [16] DIO14 +// +// Data output for DIO14 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT15_12_DIO14 0x00010000U +#define GPIO_DOUT15_12_DIO14_M 0x00010000U +#define GPIO_DOUT15_12_DIO14_S 16U +#define GPIO_DOUT15_12_DIO14_ONE 0x00010000U +#define GPIO_DOUT15_12_DIO14_ZERO 0x00000000U + +// Field: [8] DIO13 +// +// Data output for DIO13 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT15_12_DIO13 0x00000100U +#define GPIO_DOUT15_12_DIO13_M 0x00000100U +#define GPIO_DOUT15_12_DIO13_S 8U +#define GPIO_DOUT15_12_DIO13_ONE 0x00000100U +#define GPIO_DOUT15_12_DIO13_ZERO 0x00000000U + +// Field: [0] DIO12 +// +// Data output for DIO12 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT15_12_DIO12 0x00000001U +#define GPIO_DOUT15_12_DIO12_M 0x00000001U +#define GPIO_DOUT15_12_DIO12_S 0U +#define GPIO_DOUT15_12_DIO12_ONE 0x00000001U +#define GPIO_DOUT15_12_DIO12_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Data output for DIO19 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT19_16_DIO19 0x01000000U +#define GPIO_DOUT19_16_DIO19_M 0x01000000U +#define GPIO_DOUT19_16_DIO19_S 24U +#define GPIO_DOUT19_16_DIO19_ONE 0x01000000U +#define GPIO_DOUT19_16_DIO19_ZERO 0x00000000U + +// Field: [16] DIO18 +// +// Data output for DIO18 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT19_16_DIO18 0x00010000U +#define GPIO_DOUT19_16_DIO18_M 0x00010000U +#define GPIO_DOUT19_16_DIO18_S 16U +#define GPIO_DOUT19_16_DIO18_ONE 0x00010000U +#define GPIO_DOUT19_16_DIO18_ZERO 0x00000000U + +// Field: [8] DIO17 +// +// Data output for DIO17 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT19_16_DIO17 0x00000100U +#define GPIO_DOUT19_16_DIO17_M 0x00000100U +#define GPIO_DOUT19_16_DIO17_S 8U +#define GPIO_DOUT19_16_DIO17_ONE 0x00000100U +#define GPIO_DOUT19_16_DIO17_ZERO 0x00000000U + +// Field: [0] DIO16 +// +// Data output for DIO16 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT19_16_DIO16 0x00000001U +#define GPIO_DOUT19_16_DIO16_M 0x00000001U +#define GPIO_DOUT19_16_DIO16_S 0U +#define GPIO_DOUT19_16_DIO16_ONE 0x00000001U +#define GPIO_DOUT19_16_DIO16_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Data output for DIO23 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT23_20_DIO23 0x01000000U +#define GPIO_DOUT23_20_DIO23_M 0x01000000U +#define GPIO_DOUT23_20_DIO23_S 24U +#define GPIO_DOUT23_20_DIO23_ONE 0x01000000U +#define GPIO_DOUT23_20_DIO23_ZERO 0x00000000U + +// Field: [16] DIO22 +// +// Data output for DIO22 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT23_20_DIO22 0x00010000U +#define GPIO_DOUT23_20_DIO22_M 0x00010000U +#define GPIO_DOUT23_20_DIO22_S 16U +#define GPIO_DOUT23_20_DIO22_ONE 0x00010000U +#define GPIO_DOUT23_20_DIO22_ZERO 0x00000000U + +// Field: [8] DIO21 +// +// Data output for DIO21 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT23_20_DIO21 0x00000100U +#define GPIO_DOUT23_20_DIO21_M 0x00000100U +#define GPIO_DOUT23_20_DIO21_S 8U +#define GPIO_DOUT23_20_DIO21_ONE 0x00000100U +#define GPIO_DOUT23_20_DIO21_ZERO 0x00000000U + +// Field: [0] DIO20 +// +// Data output for DIO20 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT23_20_DIO20 0x00000001U +#define GPIO_DOUT23_20_DIO20_M 0x00000001U +#define GPIO_DOUT23_20_DIO20_S 0U +#define GPIO_DOUT23_20_DIO20_ONE 0x00000001U +#define GPIO_DOUT23_20_DIO20_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [8] DIO25 +// +// Data output for DIO25 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT27_24_DIO25 0x00000100U +#define GPIO_DOUT27_24_DIO25_M 0x00000100U +#define GPIO_DOUT27_24_DIO25_S 8U +#define GPIO_DOUT27_24_DIO25_ONE 0x00000100U +#define GPIO_DOUT27_24_DIO25_ZERO 0x00000000U + +// Field: [0] DIO24 +// +// Data output for DIO24 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT27_24_DIO24 0x00000001U +#define GPIO_DOUT27_24_DIO24_M 0x00000001U +#define GPIO_DOUT27_24_DIO24_S 0U +#define GPIO_DOUT27_24_DIO24_ONE 0x00000001U +#define GPIO_DOUT27_24_DIO24_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Data output for DIO25 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO25 0x02000000U +#define GPIO_DOUT31_0_DIO25_M 0x02000000U +#define GPIO_DOUT31_0_DIO25_S 25U +#define GPIO_DOUT31_0_DIO25_ONE 0x02000000U +#define GPIO_DOUT31_0_DIO25_ZERO 0x00000000U + +// Field: [24] DIO24 +// +// Data output for DIO24 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO24 0x01000000U +#define GPIO_DOUT31_0_DIO24_M 0x01000000U +#define GPIO_DOUT31_0_DIO24_S 24U +#define GPIO_DOUT31_0_DIO24_ONE 0x01000000U +#define GPIO_DOUT31_0_DIO24_ZERO 0x00000000U + +// Field: [23] DIO23 +// +// Data output for DIO23 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO23 0x00800000U +#define GPIO_DOUT31_0_DIO23_M 0x00800000U +#define GPIO_DOUT31_0_DIO23_S 23U +#define GPIO_DOUT31_0_DIO23_ONE 0x00800000U +#define GPIO_DOUT31_0_DIO23_ZERO 0x00000000U + +// Field: [22] DIO22 +// +// Data output for DIO22 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO22 0x00400000U +#define GPIO_DOUT31_0_DIO22_M 0x00400000U +#define GPIO_DOUT31_0_DIO22_S 22U +#define GPIO_DOUT31_0_DIO22_ONE 0x00400000U +#define GPIO_DOUT31_0_DIO22_ZERO 0x00000000U + +// Field: [21] DIO21 +// +// Data output for DIO21 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO21 0x00200000U +#define GPIO_DOUT31_0_DIO21_M 0x00200000U +#define GPIO_DOUT31_0_DIO21_S 21U +#define GPIO_DOUT31_0_DIO21_ONE 0x00200000U +#define GPIO_DOUT31_0_DIO21_ZERO 0x00000000U + +// Field: [20] DIO20 +// +// Data output for DIO20 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO20 0x00100000U +#define GPIO_DOUT31_0_DIO20_M 0x00100000U +#define GPIO_DOUT31_0_DIO20_S 20U +#define GPIO_DOUT31_0_DIO20_ONE 0x00100000U +#define GPIO_DOUT31_0_DIO20_ZERO 0x00000000U + +// Field: [19] DIO19 +// +// Data output for DIO19 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO19 0x00080000U +#define GPIO_DOUT31_0_DIO19_M 0x00080000U +#define GPIO_DOUT31_0_DIO19_S 19U +#define GPIO_DOUT31_0_DIO19_ONE 0x00080000U +#define GPIO_DOUT31_0_DIO19_ZERO 0x00000000U + +// Field: [18] DIO18 +// +// Data output for DIO18 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO18 0x00040000U +#define GPIO_DOUT31_0_DIO18_M 0x00040000U +#define GPIO_DOUT31_0_DIO18_S 18U +#define GPIO_DOUT31_0_DIO18_ONE 0x00040000U +#define GPIO_DOUT31_0_DIO18_ZERO 0x00000000U + +// Field: [17] DIO17 +// +// Data output for DIO17 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO17 0x00020000U +#define GPIO_DOUT31_0_DIO17_M 0x00020000U +#define GPIO_DOUT31_0_DIO17_S 17U +#define GPIO_DOUT31_0_DIO17_ONE 0x00020000U +#define GPIO_DOUT31_0_DIO17_ZERO 0x00000000U + +// Field: [16] DIO16 +// +// Data output for DIO16 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO16 0x00010000U +#define GPIO_DOUT31_0_DIO16_M 0x00010000U +#define GPIO_DOUT31_0_DIO16_S 16U +#define GPIO_DOUT31_0_DIO16_ONE 0x00010000U +#define GPIO_DOUT31_0_DIO16_ZERO 0x00000000U + +// Field: [15] DIO15 +// +// Data output for DIO15 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO15 0x00008000U +#define GPIO_DOUT31_0_DIO15_M 0x00008000U +#define GPIO_DOUT31_0_DIO15_S 15U +#define GPIO_DOUT31_0_DIO15_ONE 0x00008000U +#define GPIO_DOUT31_0_DIO15_ZERO 0x00000000U + +// Field: [14] DIO14 +// +// Data output for DIO14 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO14 0x00004000U +#define GPIO_DOUT31_0_DIO14_M 0x00004000U +#define GPIO_DOUT31_0_DIO14_S 14U +#define GPIO_DOUT31_0_DIO14_ONE 0x00004000U +#define GPIO_DOUT31_0_DIO14_ZERO 0x00000000U + +// Field: [13] DIO13 +// +// Data output for DIO13 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO13 0x00002000U +#define GPIO_DOUT31_0_DIO13_M 0x00002000U +#define GPIO_DOUT31_0_DIO13_S 13U +#define GPIO_DOUT31_0_DIO13_ONE 0x00002000U +#define GPIO_DOUT31_0_DIO13_ZERO 0x00000000U + +// Field: [12] DIO12 +// +// Data output for DIO12 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO12 0x00001000U +#define GPIO_DOUT31_0_DIO12_M 0x00001000U +#define GPIO_DOUT31_0_DIO12_S 12U +#define GPIO_DOUT31_0_DIO12_ONE 0x00001000U +#define GPIO_DOUT31_0_DIO12_ZERO 0x00000000U + +// Field: [11] DIO11 +// +// Data output for DIO11 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO11 0x00000800U +#define GPIO_DOUT31_0_DIO11_M 0x00000800U +#define GPIO_DOUT31_0_DIO11_S 11U +#define GPIO_DOUT31_0_DIO11_ONE 0x00000800U +#define GPIO_DOUT31_0_DIO11_ZERO 0x00000000U + +// Field: [10] DIO10 +// +// Data output for DIO10 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO10 0x00000400U +#define GPIO_DOUT31_0_DIO10_M 0x00000400U +#define GPIO_DOUT31_0_DIO10_S 10U +#define GPIO_DOUT31_0_DIO10_ONE 0x00000400U +#define GPIO_DOUT31_0_DIO10_ZERO 0x00000000U + +// Field: [9] DIO9 +// +// Data output for DIO9 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO9 0x00000200U +#define GPIO_DOUT31_0_DIO9_M 0x00000200U +#define GPIO_DOUT31_0_DIO9_S 9U +#define GPIO_DOUT31_0_DIO9_ONE 0x00000200U +#define GPIO_DOUT31_0_DIO9_ZERO 0x00000000U + +// Field: [8] DIO8 +// +// Data output for DIO8 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO8 0x00000100U +#define GPIO_DOUT31_0_DIO8_M 0x00000100U +#define GPIO_DOUT31_0_DIO8_S 8U +#define GPIO_DOUT31_0_DIO8_ONE 0x00000100U +#define GPIO_DOUT31_0_DIO8_ZERO 0x00000000U + +// Field: [7] DIO7 +// +// Data output for DIO7 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO7 0x00000080U +#define GPIO_DOUT31_0_DIO7_M 0x00000080U +#define GPIO_DOUT31_0_DIO7_S 7U +#define GPIO_DOUT31_0_DIO7_ONE 0x00000080U +#define GPIO_DOUT31_0_DIO7_ZERO 0x00000000U + +// Field: [6] DIO6 +// +// Data output for DIO6 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO6 0x00000040U +#define GPIO_DOUT31_0_DIO6_M 0x00000040U +#define GPIO_DOUT31_0_DIO6_S 6U +#define GPIO_DOUT31_0_DIO6_ONE 0x00000040U +#define GPIO_DOUT31_0_DIO6_ZERO 0x00000000U + +// Field: [5] DIO5 +// +// Data output for DIO5 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO5 0x00000020U +#define GPIO_DOUT31_0_DIO5_M 0x00000020U +#define GPIO_DOUT31_0_DIO5_S 5U +#define GPIO_DOUT31_0_DIO5_ONE 0x00000020U +#define GPIO_DOUT31_0_DIO5_ZERO 0x00000000U + +// Field: [4] DIO4 +// +// Data output for DIO4 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO4 0x00000010U +#define GPIO_DOUT31_0_DIO4_M 0x00000010U +#define GPIO_DOUT31_0_DIO4_S 4U +#define GPIO_DOUT31_0_DIO4_ONE 0x00000010U +#define GPIO_DOUT31_0_DIO4_ZERO 0x00000000U + +// Field: [3] DIO3 +// +// Data output for DIO3 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO3 0x00000008U +#define GPIO_DOUT31_0_DIO3_M 0x00000008U +#define GPIO_DOUT31_0_DIO3_S 3U +#define GPIO_DOUT31_0_DIO3_ONE 0x00000008U +#define GPIO_DOUT31_0_DIO3_ZERO 0x00000000U + +// Field: [2] DIO2 +// +// Data output for DIO2 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO2 0x00000004U +#define GPIO_DOUT31_0_DIO2_M 0x00000004U +#define GPIO_DOUT31_0_DIO2_S 2U +#define GPIO_DOUT31_0_DIO2_ONE 0x00000004U +#define GPIO_DOUT31_0_DIO2_ZERO 0x00000000U + +// Field: [1] DIO1 +// +// Data output for DIO1 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO1 0x00000002U +#define GPIO_DOUT31_0_DIO1_M 0x00000002U +#define GPIO_DOUT31_0_DIO1_S 1U +#define GPIO_DOUT31_0_DIO1_ONE 0x00000002U +#define GPIO_DOUT31_0_DIO1_ZERO 0x00000000U + +// Field: [0] DIO0 +// +// Data output for DIO0 +// ENUMs: +// ONE Output is set to 1 +// ZERO Output is set to 0 +#define GPIO_DOUT31_0_DIO0 0x00000001U +#define GPIO_DOUT31_0_DIO0_M 0x00000001U +#define GPIO_DOUT31_0_DIO0_S 0U +#define GPIO_DOUT31_0_DIO0_ONE 0x00000001U +#define GPIO_DOUT31_0_DIO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Set bit DOUT31_0.DIO25 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO25 0x02000000U +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000U +#define GPIO_DOUTSET31_0_DIO25_S 25U +#define GPIO_DOUTSET31_0_DIO25_SET 0x02000000U +#define GPIO_DOUTSET31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Set bit DOUT31_0.DIO24 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO24 0x01000000U +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000U +#define GPIO_DOUTSET31_0_DIO24_S 24U +#define GPIO_DOUTSET31_0_DIO24_SET 0x01000000U +#define GPIO_DOUTSET31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Set bit DOUT31_0.DIO23 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO23 0x00800000U +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000U +#define GPIO_DOUTSET31_0_DIO23_S 23U +#define GPIO_DOUTSET31_0_DIO23_SET 0x00800000U +#define GPIO_DOUTSET31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Set bit DOUT31_0.DIO22 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO22 0x00400000U +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000U +#define GPIO_DOUTSET31_0_DIO22_S 22U +#define GPIO_DOUTSET31_0_DIO22_SET 0x00400000U +#define GPIO_DOUTSET31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Set bit DOUT31_0.DIO21 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO21 0x00200000U +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000U +#define GPIO_DOUTSET31_0_DIO21_S 21U +#define GPIO_DOUTSET31_0_DIO21_SET 0x00200000U +#define GPIO_DOUTSET31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Set bit DOUT31_0.DIO20 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO20 0x00100000U +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000U +#define GPIO_DOUTSET31_0_DIO20_S 20U +#define GPIO_DOUTSET31_0_DIO20_SET 0x00100000U +#define GPIO_DOUTSET31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Set bit DOUT31_0.DIO19 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO19 0x00080000U +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000U +#define GPIO_DOUTSET31_0_DIO19_S 19U +#define GPIO_DOUTSET31_0_DIO19_SET 0x00080000U +#define GPIO_DOUTSET31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Set bit DOUT31_0.DIO18 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO18 0x00040000U +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000U +#define GPIO_DOUTSET31_0_DIO18_S 18U +#define GPIO_DOUTSET31_0_DIO18_SET 0x00040000U +#define GPIO_DOUTSET31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Set bit DOUT31_0.DIO17 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO17 0x00020000U +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000U +#define GPIO_DOUTSET31_0_DIO17_S 17U +#define GPIO_DOUTSET31_0_DIO17_SET 0x00020000U +#define GPIO_DOUTSET31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Set bit DOUT31_0.DIO16 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO16 0x00010000U +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000U +#define GPIO_DOUTSET31_0_DIO16_S 16U +#define GPIO_DOUTSET31_0_DIO16_SET 0x00010000U +#define GPIO_DOUTSET31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Set bit DOUT31_0.DIO15 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO15 0x00008000U +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000U +#define GPIO_DOUTSET31_0_DIO15_S 15U +#define GPIO_DOUTSET31_0_DIO15_SET 0x00008000U +#define GPIO_DOUTSET31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Set bit DOUT31_0.DIO14 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO14 0x00004000U +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000U +#define GPIO_DOUTSET31_0_DIO14_S 14U +#define GPIO_DOUTSET31_0_DIO14_SET 0x00004000U +#define GPIO_DOUTSET31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Set bit DOUT31_0.DIO13 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO13 0x00002000U +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000U +#define GPIO_DOUTSET31_0_DIO13_S 13U +#define GPIO_DOUTSET31_0_DIO13_SET 0x00002000U +#define GPIO_DOUTSET31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Set bit DOUT31_0.DIO12 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO12 0x00001000U +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000U +#define GPIO_DOUTSET31_0_DIO12_S 12U +#define GPIO_DOUTSET31_0_DIO12_SET 0x00001000U +#define GPIO_DOUTSET31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Set bit DOUT31_0.DIO11 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO11 0x00000800U +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800U +#define GPIO_DOUTSET31_0_DIO11_S 11U +#define GPIO_DOUTSET31_0_DIO11_SET 0x00000800U +#define GPIO_DOUTSET31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Set bit DOUT31_0.DIO10 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO10 0x00000400U +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400U +#define GPIO_DOUTSET31_0_DIO10_S 10U +#define GPIO_DOUTSET31_0_DIO10_SET 0x00000400U +#define GPIO_DOUTSET31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Set bit DOUT31_0.DIO9 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO9 0x00000200U +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200U +#define GPIO_DOUTSET31_0_DIO9_S 9U +#define GPIO_DOUTSET31_0_DIO9_SET 0x00000200U +#define GPIO_DOUTSET31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Set bit DOUT31_0.DIO8 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO8 0x00000100U +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100U +#define GPIO_DOUTSET31_0_DIO8_S 8U +#define GPIO_DOUTSET31_0_DIO8_SET 0x00000100U +#define GPIO_DOUTSET31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Set bit DOUT31_0.DIO7 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO7 0x00000080U +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080U +#define GPIO_DOUTSET31_0_DIO7_S 7U +#define GPIO_DOUTSET31_0_DIO7_SET 0x00000080U +#define GPIO_DOUTSET31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Set bit DOUT31_0.DIO6 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO6 0x00000040U +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040U +#define GPIO_DOUTSET31_0_DIO6_S 6U +#define GPIO_DOUTSET31_0_DIO6_SET 0x00000040U +#define GPIO_DOUTSET31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Set bit DOUT31_0.DIO5 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO5 0x00000020U +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020U +#define GPIO_DOUTSET31_0_DIO5_S 5U +#define GPIO_DOUTSET31_0_DIO5_SET 0x00000020U +#define GPIO_DOUTSET31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Set bit DOUT31_0.DIO4 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO4 0x00000010U +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010U +#define GPIO_DOUTSET31_0_DIO4_S 4U +#define GPIO_DOUTSET31_0_DIO4_SET 0x00000010U +#define GPIO_DOUTSET31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Set bit DOUT31_0.DIO3 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO3 0x00000008U +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008U +#define GPIO_DOUTSET31_0_DIO3_S 3U +#define GPIO_DOUTSET31_0_DIO3_SET 0x00000008U +#define GPIO_DOUTSET31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Set bit DOUT31_0.DIO2 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO2 0x00000004U +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004U +#define GPIO_DOUTSET31_0_DIO2_S 2U +#define GPIO_DOUTSET31_0_DIO2_SET 0x00000004U +#define GPIO_DOUTSET31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Set bit DOUT31_0.DIO1 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO1 0x00000002U +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002U +#define GPIO_DOUTSET31_0_DIO1_S 1U +#define GPIO_DOUTSET31_0_DIO1_SET 0x00000002U +#define GPIO_DOUTSET31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Set bit DOUT31_0.DIO0 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOUTSET31_0_DIO0 0x00000001U +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001U +#define GPIO_DOUTSET31_0_DIO0_S 0U +#define GPIO_DOUTSET31_0_DIO0_SET 0x00000001U +#define GPIO_DOUTSET31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Clear bit DOUT31_0.DIO25 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO25 0x02000000U +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000U +#define GPIO_DOUTCLR31_0_DIO25_S 25U +#define GPIO_DOUTCLR31_0_DIO25_CLR 0x02000000U +#define GPIO_DOUTCLR31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Clear bit DOUT31_0.DIO24 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO24 0x01000000U +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000U +#define GPIO_DOUTCLR31_0_DIO24_S 24U +#define GPIO_DOUTCLR31_0_DIO24_CLR 0x01000000U +#define GPIO_DOUTCLR31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Clear bit DOUT31_0.DIO23 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO23 0x00800000U +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000U +#define GPIO_DOUTCLR31_0_DIO23_S 23U +#define GPIO_DOUTCLR31_0_DIO23_CLR 0x00800000U +#define GPIO_DOUTCLR31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Clear bit DOUT31_0.DIO22 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO22 0x00400000U +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000U +#define GPIO_DOUTCLR31_0_DIO22_S 22U +#define GPIO_DOUTCLR31_0_DIO22_CLR 0x00400000U +#define GPIO_DOUTCLR31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Clear bit DOUT31_0.DIO21 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO21 0x00200000U +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000U +#define GPIO_DOUTCLR31_0_DIO21_S 21U +#define GPIO_DOUTCLR31_0_DIO21_CLR 0x00200000U +#define GPIO_DOUTCLR31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Clear bit DOUT31_0.DIO20 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO20 0x00100000U +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000U +#define GPIO_DOUTCLR31_0_DIO20_S 20U +#define GPIO_DOUTCLR31_0_DIO20_CLR 0x00100000U +#define GPIO_DOUTCLR31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Clear bit DOUT31_0.DIO19 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO19 0x00080000U +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000U +#define GPIO_DOUTCLR31_0_DIO19_S 19U +#define GPIO_DOUTCLR31_0_DIO19_CLR 0x00080000U +#define GPIO_DOUTCLR31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Clear bit DOUT31_0.DIO18 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO18 0x00040000U +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000U +#define GPIO_DOUTCLR31_0_DIO18_S 18U +#define GPIO_DOUTCLR31_0_DIO18_CLR 0x00040000U +#define GPIO_DOUTCLR31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Clear bit DOUT31_0.DIO17 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO17 0x00020000U +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000U +#define GPIO_DOUTCLR31_0_DIO17_S 17U +#define GPIO_DOUTCLR31_0_DIO17_CLR 0x00020000U +#define GPIO_DOUTCLR31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Clear bit DOUT31_0.DIO16 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO16 0x00010000U +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000U +#define GPIO_DOUTCLR31_0_DIO16_S 16U +#define GPIO_DOUTCLR31_0_DIO16_CLR 0x00010000U +#define GPIO_DOUTCLR31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Clear bit DOUT31_0.DIO15 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO15 0x00008000U +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000U +#define GPIO_DOUTCLR31_0_DIO15_S 15U +#define GPIO_DOUTCLR31_0_DIO15_CLR 0x00008000U +#define GPIO_DOUTCLR31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Clear bit DOUT31_0.DIO14 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO14 0x00004000U +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000U +#define GPIO_DOUTCLR31_0_DIO14_S 14U +#define GPIO_DOUTCLR31_0_DIO14_CLR 0x00004000U +#define GPIO_DOUTCLR31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Clear bit DOUT31_0.DIO13 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO13 0x00002000U +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000U +#define GPIO_DOUTCLR31_0_DIO13_S 13U +#define GPIO_DOUTCLR31_0_DIO13_CLR 0x00002000U +#define GPIO_DOUTCLR31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Clear bit DOUT31_0.DIO12 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO12 0x00001000U +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000U +#define GPIO_DOUTCLR31_0_DIO12_S 12U +#define GPIO_DOUTCLR31_0_DIO12_CLR 0x00001000U +#define GPIO_DOUTCLR31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Clear bit DOUT31_0.DIO11 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO11 0x00000800U +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800U +#define GPIO_DOUTCLR31_0_DIO11_S 11U +#define GPIO_DOUTCLR31_0_DIO11_CLR 0x00000800U +#define GPIO_DOUTCLR31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Clear bit DOUT31_0.DIO10 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO10 0x00000400U +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400U +#define GPIO_DOUTCLR31_0_DIO10_S 10U +#define GPIO_DOUTCLR31_0_DIO10_CLR 0x00000400U +#define GPIO_DOUTCLR31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Clear bit DOUT31_0.DIO9 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO9 0x00000200U +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200U +#define GPIO_DOUTCLR31_0_DIO9_S 9U +#define GPIO_DOUTCLR31_0_DIO9_CLR 0x00000200U +#define GPIO_DOUTCLR31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Clear bit DOUT31_0.DIO8 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO8 0x00000100U +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100U +#define GPIO_DOUTCLR31_0_DIO8_S 8U +#define GPIO_DOUTCLR31_0_DIO8_CLR 0x00000100U +#define GPIO_DOUTCLR31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Clear bit DOUT31_0.DIO7 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO7 0x00000080U +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080U +#define GPIO_DOUTCLR31_0_DIO7_S 7U +#define GPIO_DOUTCLR31_0_DIO7_CLR 0x00000080U +#define GPIO_DOUTCLR31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Clear bit DOUT31_0.DIO6 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO6 0x00000040U +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040U +#define GPIO_DOUTCLR31_0_DIO6_S 6U +#define GPIO_DOUTCLR31_0_DIO6_CLR 0x00000040U +#define GPIO_DOUTCLR31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Clear bit DOUT31_0.DIO5 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO5 0x00000020U +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020U +#define GPIO_DOUTCLR31_0_DIO5_S 5U +#define GPIO_DOUTCLR31_0_DIO5_CLR 0x00000020U +#define GPIO_DOUTCLR31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Clear bit DOUT31_0.DIO4 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO4 0x00000010U +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010U +#define GPIO_DOUTCLR31_0_DIO4_S 4U +#define GPIO_DOUTCLR31_0_DIO4_CLR 0x00000010U +#define GPIO_DOUTCLR31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Clear bit DOUT31_0.DIO3 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO3 0x00000008U +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008U +#define GPIO_DOUTCLR31_0_DIO3_S 3U +#define GPIO_DOUTCLR31_0_DIO3_CLR 0x00000008U +#define GPIO_DOUTCLR31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Clear bit DOUT31_0.DIO2 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO2 0x00000004U +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004U +#define GPIO_DOUTCLR31_0_DIO2_S 2U +#define GPIO_DOUTCLR31_0_DIO2_CLR 0x00000004U +#define GPIO_DOUTCLR31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Clear bit DOUT31_0.DIO1 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO1 0x00000002U +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002U +#define GPIO_DOUTCLR31_0_DIO1_S 1U +#define GPIO_DOUTCLR31_0_DIO1_CLR 0x00000002U +#define GPIO_DOUTCLR31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Clear bit DOUT31_0.DIO0 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOUTCLR31_0_DIO0 0x00000001U +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001U +#define GPIO_DOUTCLR31_0_DIO0_S 0U +#define GPIO_DOUTCLR31_0_DIO0_CLR 0x00000001U +#define GPIO_DOUTCLR31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Toggles bit DOUT31_0.DIO25 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO25 0x02000000U +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000U +#define GPIO_DOUTTGL31_0_DIO25_S 25U +#define GPIO_DOUTTGL31_0_DIO25_TOGGLE 0x02000000U +#define GPIO_DOUTTGL31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Toggles bit DOUT31_0.DIO24 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO24 0x01000000U +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000U +#define GPIO_DOUTTGL31_0_DIO24_S 24U +#define GPIO_DOUTTGL31_0_DIO24_TOGGLE 0x01000000U +#define GPIO_DOUTTGL31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Toggles bit DOUT31_0.DIO23 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO23 0x00800000U +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000U +#define GPIO_DOUTTGL31_0_DIO23_S 23U +#define GPIO_DOUTTGL31_0_DIO23_TOGGLE 0x00800000U +#define GPIO_DOUTTGL31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Toggles bit DOUT31_0.DIO22 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO22 0x00400000U +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000U +#define GPIO_DOUTTGL31_0_DIO22_S 22U +#define GPIO_DOUTTGL31_0_DIO22_TOGGLE 0x00400000U +#define GPIO_DOUTTGL31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Toggles bit DOUT31_0.DIO21 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO21 0x00200000U +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000U +#define GPIO_DOUTTGL31_0_DIO21_S 21U +#define GPIO_DOUTTGL31_0_DIO21_TOGGLE 0x00200000U +#define GPIO_DOUTTGL31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Toggles bit DOUT31_0.DIO20 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO20 0x00100000U +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000U +#define GPIO_DOUTTGL31_0_DIO20_S 20U +#define GPIO_DOUTTGL31_0_DIO20_TOGGLE 0x00100000U +#define GPIO_DOUTTGL31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Toggles bit DOUT31_0.DIO19 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO19 0x00080000U +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000U +#define GPIO_DOUTTGL31_0_DIO19_S 19U +#define GPIO_DOUTTGL31_0_DIO19_TOGGLE 0x00080000U +#define GPIO_DOUTTGL31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Toggles bit DOUT31_0.DIO18 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO18 0x00040000U +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000U +#define GPIO_DOUTTGL31_0_DIO18_S 18U +#define GPIO_DOUTTGL31_0_DIO18_TOGGLE 0x00040000U +#define GPIO_DOUTTGL31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Toggles bit DOUT31_0.DIO17 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO17 0x00020000U +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000U +#define GPIO_DOUTTGL31_0_DIO17_S 17U +#define GPIO_DOUTTGL31_0_DIO17_TOGGLE 0x00020000U +#define GPIO_DOUTTGL31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Toggles bit DOUT31_0.DIO16 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO16 0x00010000U +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000U +#define GPIO_DOUTTGL31_0_DIO16_S 16U +#define GPIO_DOUTTGL31_0_DIO16_TOGGLE 0x00010000U +#define GPIO_DOUTTGL31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Toggles bit DOUT31_0.DIO15 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO15 0x00008000U +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000U +#define GPIO_DOUTTGL31_0_DIO15_S 15U +#define GPIO_DOUTTGL31_0_DIO15_TOGGLE 0x00008000U +#define GPIO_DOUTTGL31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Toggles bit DOUT31_0.DIO14 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO14 0x00004000U +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000U +#define GPIO_DOUTTGL31_0_DIO14_S 14U +#define GPIO_DOUTTGL31_0_DIO14_TOGGLE 0x00004000U +#define GPIO_DOUTTGL31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Toggles bit DOUT31_0.DIO13 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO13 0x00002000U +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000U +#define GPIO_DOUTTGL31_0_DIO13_S 13U +#define GPIO_DOUTTGL31_0_DIO13_TOGGLE 0x00002000U +#define GPIO_DOUTTGL31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Toggles bit DOUT31_0.DIO12 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO12 0x00001000U +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000U +#define GPIO_DOUTTGL31_0_DIO12_S 12U +#define GPIO_DOUTTGL31_0_DIO12_TOGGLE 0x00001000U +#define GPIO_DOUTTGL31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Toggles bit DOUT31_0.DIO11 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO11 0x00000800U +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800U +#define GPIO_DOUTTGL31_0_DIO11_S 11U +#define GPIO_DOUTTGL31_0_DIO11_TOGGLE 0x00000800U +#define GPIO_DOUTTGL31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Toggles bit DOUT31_0.DIO10 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO10 0x00000400U +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400U +#define GPIO_DOUTTGL31_0_DIO10_S 10U +#define GPIO_DOUTTGL31_0_DIO10_TOGGLE 0x00000400U +#define GPIO_DOUTTGL31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Toggles bit DOUT31_0.DIO9 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO9 0x00000200U +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200U +#define GPIO_DOUTTGL31_0_DIO9_S 9U +#define GPIO_DOUTTGL31_0_DIO9_TOGGLE 0x00000200U +#define GPIO_DOUTTGL31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Toggles bit DOUT31_0.DIO8 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO8 0x00000100U +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100U +#define GPIO_DOUTTGL31_0_DIO8_S 8U +#define GPIO_DOUTTGL31_0_DIO8_TOGGLE 0x00000100U +#define GPIO_DOUTTGL31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Toggles bit DOUT31_0.DIO7 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO7 0x00000080U +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080U +#define GPIO_DOUTTGL31_0_DIO7_S 7U +#define GPIO_DOUTTGL31_0_DIO7_TOGGLE 0x00000080U +#define GPIO_DOUTTGL31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Toggles bit DOUT31_0.DIO6 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO6 0x00000040U +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040U +#define GPIO_DOUTTGL31_0_DIO6_S 6U +#define GPIO_DOUTTGL31_0_DIO6_TOGGLE 0x00000040U +#define GPIO_DOUTTGL31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Toggles bit DOUT31_0.DIO5 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO5 0x00000020U +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020U +#define GPIO_DOUTTGL31_0_DIO5_S 5U +#define GPIO_DOUTTGL31_0_DIO5_TOGGLE 0x00000020U +#define GPIO_DOUTTGL31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Toggles bit DOUT31_0.DIO4 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO4 0x00000010U +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010U +#define GPIO_DOUTTGL31_0_DIO4_S 4U +#define GPIO_DOUTTGL31_0_DIO4_TOGGLE 0x00000010U +#define GPIO_DOUTTGL31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Toggles bit DOUT31_0.DIO3 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO3 0x00000008U +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008U +#define GPIO_DOUTTGL31_0_DIO3_S 3U +#define GPIO_DOUTTGL31_0_DIO3_TOGGLE 0x00000008U +#define GPIO_DOUTTGL31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Toggles bit DOUT31_0.DIO2 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO2 0x00000004U +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004U +#define GPIO_DOUTTGL31_0_DIO2_S 2U +#define GPIO_DOUTTGL31_0_DIO2_TOGGLE 0x00000004U +#define GPIO_DOUTTGL31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Toggles bit DOUT31_0.DIO1 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO1 0x00000002U +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002U +#define GPIO_DOUTTGL31_0_DIO1_S 1U +#define GPIO_DOUTTGL31_0_DIO1_TOGGLE 0x00000002U +#define GPIO_DOUTTGL31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Toggles bit DOUT31_0.DIO0 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL31_0_DIO0 0x00000001U +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001U +#define GPIO_DOUTTGL31_0_DIO0_S 0U +#define GPIO_DOUTTGL31_0_DIO0_TOGGLE 0x00000001U +#define GPIO_DOUTTGL31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Toggles bit DOUT31_0.DIO3 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL3_0_DIO3 0x01000000U +#define GPIO_DOUTTGL3_0_DIO3_M 0x01000000U +#define GPIO_DOUTTGL3_0_DIO3_S 24U +#define GPIO_DOUTTGL3_0_DIO3_TOGGLE 0x01000000U +#define GPIO_DOUTTGL3_0_DIO3_NOEFF 0x00000000U + +// Field: [16] DIO2 +// +// Toggles bit DOUT31_0.DIO2 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL3_0_DIO2 0x00010000U +#define GPIO_DOUTTGL3_0_DIO2_M 0x00010000U +#define GPIO_DOUTTGL3_0_DIO2_S 16U +#define GPIO_DOUTTGL3_0_DIO2_TOGGLE 0x00010000U +#define GPIO_DOUTTGL3_0_DIO2_NOEFF 0x00000000U + +// Field: [8] DIO1 +// +// Toggles bit DOUT31_0.DIO1 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL3_0_DIO1 0x00000100U +#define GPIO_DOUTTGL3_0_DIO1_M 0x00000100U +#define GPIO_DOUTTGL3_0_DIO1_S 8U +#define GPIO_DOUTTGL3_0_DIO1_TOGGLE 0x00000100U +#define GPIO_DOUTTGL3_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Toggles bit DOUT31_0.DIO0 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL3_0_DIO0 0x00000001U +#define GPIO_DOUTTGL3_0_DIO0_M 0x00000001U +#define GPIO_DOUTTGL3_0_DIO0_S 0U +#define GPIO_DOUTTGL3_0_DIO0_TOGGLE 0x00000001U +#define GPIO_DOUTTGL3_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Toggles bit DOUT31_0.DIO7 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL7_4_DIO7 0x01000000U +#define GPIO_DOUTTGL7_4_DIO7_M 0x01000000U +#define GPIO_DOUTTGL7_4_DIO7_S 24U +#define GPIO_DOUTTGL7_4_DIO7_TOGGLE 0x01000000U +#define GPIO_DOUTTGL7_4_DIO7_NOEFF 0x00000000U + +// Field: [16] DIO6 +// +// Toggles bit DOUT31_0.DIO6 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL7_4_DIO6 0x00010000U +#define GPIO_DOUTTGL7_4_DIO6_M 0x00010000U +#define GPIO_DOUTTGL7_4_DIO6_S 16U +#define GPIO_DOUTTGL7_4_DIO6_TOGGLE 0x00010000U +#define GPIO_DOUTTGL7_4_DIO6_NOEFF 0x00000000U + +// Field: [8] DIO5 +// +// Toggles bit DOUT31_0.DIO5 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL7_4_DIO5 0x00000100U +#define GPIO_DOUTTGL7_4_DIO5_M 0x00000100U +#define GPIO_DOUTTGL7_4_DIO5_S 8U +#define GPIO_DOUTTGL7_4_DIO5_TOGGLE 0x00000100U +#define GPIO_DOUTTGL7_4_DIO5_NOEFF 0x00000000U + +// Field: [0] DIO4 +// +// Toggles bit DOUT31_0.DIO4 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL7_4_DIO4 0x00000001U +#define GPIO_DOUTTGL7_4_DIO4_M 0x00000001U +#define GPIO_DOUTTGL7_4_DIO4_S 0U +#define GPIO_DOUTTGL7_4_DIO4_TOGGLE 0x00000001U +#define GPIO_DOUTTGL7_4_DIO4_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Toggles bit DOUT31_0.DIO11 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL11_8_DIO11 0x01000000U +#define GPIO_DOUTTGL11_8_DIO11_M 0x01000000U +#define GPIO_DOUTTGL11_8_DIO11_S 24U +#define GPIO_DOUTTGL11_8_DIO11_TOGGLE 0x01000000U +#define GPIO_DOUTTGL11_8_DIO11_NOEFF 0x00000000U + +// Field: [16] DIO10 +// +// Toggles bit DOUT31_0.DIO10 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL11_8_DIO10 0x00010000U +#define GPIO_DOUTTGL11_8_DIO10_M 0x00010000U +#define GPIO_DOUTTGL11_8_DIO10_S 16U +#define GPIO_DOUTTGL11_8_DIO10_TOGGLE 0x00010000U +#define GPIO_DOUTTGL11_8_DIO10_NOEFF 0x00000000U + +// Field: [8] DIO9 +// +// Toggles bit DOUT31_0.DIO9 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL11_8_DIO9 0x00000100U +#define GPIO_DOUTTGL11_8_DIO9_M 0x00000100U +#define GPIO_DOUTTGL11_8_DIO9_S 8U +#define GPIO_DOUTTGL11_8_DIO9_TOGGLE 0x00000100U +#define GPIO_DOUTTGL11_8_DIO9_NOEFF 0x00000000U + +// Field: [0] DIO8 +// +// Toggles bit DOUT31_0.DIO8 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL11_8_DIO8 0x00000001U +#define GPIO_DOUTTGL11_8_DIO8_M 0x00000001U +#define GPIO_DOUTTGL11_8_DIO8_S 0U +#define GPIO_DOUTTGL11_8_DIO8_TOGGLE 0x00000001U +#define GPIO_DOUTTGL11_8_DIO8_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Toggles bit DOUT31_0.DIO15 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL15_12_DIO15 0x01000000U +#define GPIO_DOUTTGL15_12_DIO15_M 0x01000000U +#define GPIO_DOUTTGL15_12_DIO15_S 24U +#define GPIO_DOUTTGL15_12_DIO15_TOGGLE 0x01000000U +#define GPIO_DOUTTGL15_12_DIO15_NOEFF 0x00000000U + +// Field: [16] DIO14 +// +// Toggles bit DOUT31_0.DIO14 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL15_12_DIO14 0x00010000U +#define GPIO_DOUTTGL15_12_DIO14_M 0x00010000U +#define GPIO_DOUTTGL15_12_DIO14_S 16U +#define GPIO_DOUTTGL15_12_DIO14_TOGGLE 0x00010000U +#define GPIO_DOUTTGL15_12_DIO14_NOEFF 0x00000000U + +// Field: [8] DIO13 +// +// Toggles bit DOUT31_0.DIO13 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL15_12_DIO13 0x00000100U +#define GPIO_DOUTTGL15_12_DIO13_M 0x00000100U +#define GPIO_DOUTTGL15_12_DIO13_S 8U +#define GPIO_DOUTTGL15_12_DIO13_TOGGLE 0x00000100U +#define GPIO_DOUTTGL15_12_DIO13_NOEFF 0x00000000U + +// Field: [0] DIO12 +// +// Toggles bit DOUT31_0.DIO12 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL15_12_DIO12 0x00000001U +#define GPIO_DOUTTGL15_12_DIO12_M 0x00000001U +#define GPIO_DOUTTGL15_12_DIO12_S 0U +#define GPIO_DOUTTGL15_12_DIO12_TOGGLE 0x00000001U +#define GPIO_DOUTTGL15_12_DIO12_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Toggles bit DOUT31_0.DIO19 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL19_16_DIO19 0x01000000U +#define GPIO_DOUTTGL19_16_DIO19_M 0x01000000U +#define GPIO_DOUTTGL19_16_DIO19_S 24U +#define GPIO_DOUTTGL19_16_DIO19_TOGGLE 0x01000000U +#define GPIO_DOUTTGL19_16_DIO19_NOEFF 0x00000000U + +// Field: [16] DIO18 +// +// Toggles bit DOUT31_0.DIO18 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL19_16_DIO18 0x00010000U +#define GPIO_DOUTTGL19_16_DIO18_M 0x00010000U +#define GPIO_DOUTTGL19_16_DIO18_S 16U +#define GPIO_DOUTTGL19_16_DIO18_TOGGLE 0x00010000U +#define GPIO_DOUTTGL19_16_DIO18_NOEFF 0x00000000U + +// Field: [8] DIO17 +// +// Toggles bit DOUT31_0.DIO17 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL19_16_DIO17 0x00000100U +#define GPIO_DOUTTGL19_16_DIO17_M 0x00000100U +#define GPIO_DOUTTGL19_16_DIO17_S 8U +#define GPIO_DOUTTGL19_16_DIO17_TOGGLE 0x00000100U +#define GPIO_DOUTTGL19_16_DIO17_NOEFF 0x00000000U + +// Field: [0] DIO16 +// +// Toggles bit DOUT31_0.DIO16 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL19_16_DIO16 0x00000001U +#define GPIO_DOUTTGL19_16_DIO16_M 0x00000001U +#define GPIO_DOUTTGL19_16_DIO16_S 0U +#define GPIO_DOUTTGL19_16_DIO16_TOGGLE 0x00000001U +#define GPIO_DOUTTGL19_16_DIO16_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Toggles bit DOUT31_0.DIO23 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL23_20_DIO23 0x01000000U +#define GPIO_DOUTTGL23_20_DIO23_M 0x01000000U +#define GPIO_DOUTTGL23_20_DIO23_S 24U +#define GPIO_DOUTTGL23_20_DIO23_TOGGLE 0x01000000U +#define GPIO_DOUTTGL23_20_DIO23_NOEFF 0x00000000U + +// Field: [16] DIO22 +// +// Toggles bit DOUT31_0.DIO22 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL23_20_DIO22 0x00010000U +#define GPIO_DOUTTGL23_20_DIO22_M 0x00010000U +#define GPIO_DOUTTGL23_20_DIO22_S 16U +#define GPIO_DOUTTGL23_20_DIO22_TOGGLE 0x00010000U +#define GPIO_DOUTTGL23_20_DIO22_NOEFF 0x00000000U + +// Field: [8] DIO21 +// +// Toggles bit DOUT31_0.DIO21 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL23_20_DIO21 0x00000100U +#define GPIO_DOUTTGL23_20_DIO21_M 0x00000100U +#define GPIO_DOUTTGL23_20_DIO21_S 8U +#define GPIO_DOUTTGL23_20_DIO21_TOGGLE 0x00000100U +#define GPIO_DOUTTGL23_20_DIO21_NOEFF 0x00000000U + +// Field: [0] DIO20 +// +// Toggles bit DOUT31_0.DIO20 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL23_20_DIO20 0x00000001U +#define GPIO_DOUTTGL23_20_DIO20_M 0x00000001U +#define GPIO_DOUTTGL23_20_DIO20_S 0U +#define GPIO_DOUTTGL23_20_DIO20_TOGGLE 0x00000001U +#define GPIO_DOUTTGL23_20_DIO20_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL27_24 +// +//***************************************************************************** +// Field: [8] DIO25 +// +// Toggles bit DOUT31_0.DIO25 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL27_24_DIO25 0x00000100U +#define GPIO_DOUTTGL27_24_DIO25_M 0x00000100U +#define GPIO_DOUTTGL27_24_DIO25_S 8U +#define GPIO_DOUTTGL27_24_DIO25_TOGGLE 0x00000100U +#define GPIO_DOUTTGL27_24_DIO25_NOEFF 0x00000000U + +// Field: [0] DIO24 +// +// Toggles bit DOUT31_0.DIO24 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOUTTGL27_24_DIO24 0x00000001U +#define GPIO_DOUTTGL27_24_DIO24_M 0x00000001U +#define GPIO_DOUTTGL27_24_DIO24_S 0U +#define GPIO_DOUTTGL27_24_DIO24_TOGGLE 0x00000001U +#define GPIO_DOUTTGL27_24_DIO24_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Data output enable for DIO3 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE3_0_DIO3 0x01000000U +#define GPIO_DOE3_0_DIO3_M 0x01000000U +#define GPIO_DOE3_0_DIO3_S 24U +#define GPIO_DOE3_0_DIO3_EN 0x01000000U +#define GPIO_DOE3_0_DIO3_DIS 0x00000000U + +// Field: [16] DIO2 +// +// Data output enable for DIO2 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE3_0_DIO2 0x00010000U +#define GPIO_DOE3_0_DIO2_M 0x00010000U +#define GPIO_DOE3_0_DIO2_S 16U +#define GPIO_DOE3_0_DIO2_EN 0x00010000U +#define GPIO_DOE3_0_DIO2_DIS 0x00000000U + +// Field: [8] DIO1 +// +// Data output enable for DIO1 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE3_0_DIO1 0x00000100U +#define GPIO_DOE3_0_DIO1_M 0x00000100U +#define GPIO_DOE3_0_DIO1_S 8U +#define GPIO_DOE3_0_DIO1_EN 0x00000100U +#define GPIO_DOE3_0_DIO1_DIS 0x00000000U + +// Field: [0] DIO0 +// +// Data output enable for DIO0 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE3_0_DIO0 0x00000001U +#define GPIO_DOE3_0_DIO0_M 0x00000001U +#define GPIO_DOE3_0_DIO0_S 0U +#define GPIO_DOE3_0_DIO0_EN 0x00000001U +#define GPIO_DOE3_0_DIO0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Data output enable for DIO7 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE7_4_DIO7 0x01000000U +#define GPIO_DOE7_4_DIO7_M 0x01000000U +#define GPIO_DOE7_4_DIO7_S 24U +#define GPIO_DOE7_4_DIO7_EN 0x01000000U +#define GPIO_DOE7_4_DIO7_DIS 0x00000000U + +// Field: [16] DIO6 +// +// Data output enable for DIO6 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE7_4_DIO6 0x00010000U +#define GPIO_DOE7_4_DIO6_M 0x00010000U +#define GPIO_DOE7_4_DIO6_S 16U +#define GPIO_DOE7_4_DIO6_EN 0x00010000U +#define GPIO_DOE7_4_DIO6_DIS 0x00000000U + +// Field: [8] DIO5 +// +// Data output enable for DIO5 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE7_4_DIO5 0x00000100U +#define GPIO_DOE7_4_DIO5_M 0x00000100U +#define GPIO_DOE7_4_DIO5_S 8U +#define GPIO_DOE7_4_DIO5_EN 0x00000100U +#define GPIO_DOE7_4_DIO5_DIS 0x00000000U + +// Field: [0] DIO4 +// +// Data output enable for DIO4 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE7_4_DIO4 0x00000001U +#define GPIO_DOE7_4_DIO4_M 0x00000001U +#define GPIO_DOE7_4_DIO4_S 0U +#define GPIO_DOE7_4_DIO4_EN 0x00000001U +#define GPIO_DOE7_4_DIO4_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Data output enable for DIO11 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE11_8_DIO11 0x01000000U +#define GPIO_DOE11_8_DIO11_M 0x01000000U +#define GPIO_DOE11_8_DIO11_S 24U +#define GPIO_DOE11_8_DIO11_EN 0x01000000U +#define GPIO_DOE11_8_DIO11_DIS 0x00000000U + +// Field: [16] DIO10 +// +// Data output enable for DIO10 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE11_8_DIO10 0x00010000U +#define GPIO_DOE11_8_DIO10_M 0x00010000U +#define GPIO_DOE11_8_DIO10_S 16U +#define GPIO_DOE11_8_DIO10_EN 0x00010000U +#define GPIO_DOE11_8_DIO10_DIS 0x00000000U + +// Field: [8] DIO9 +// +// Data output enable for DIO9 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE11_8_DIO9 0x00000100U +#define GPIO_DOE11_8_DIO9_M 0x00000100U +#define GPIO_DOE11_8_DIO9_S 8U +#define GPIO_DOE11_8_DIO9_EN 0x00000100U +#define GPIO_DOE11_8_DIO9_DIS 0x00000000U + +// Field: [0] DIO8 +// +// Data output enable for DIO8 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE11_8_DIO8 0x00000001U +#define GPIO_DOE11_8_DIO8_M 0x00000001U +#define GPIO_DOE11_8_DIO8_S 0U +#define GPIO_DOE11_8_DIO8_EN 0x00000001U +#define GPIO_DOE11_8_DIO8_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Data output enable for DIO15 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE15_12_DIO15 0x01000000U +#define GPIO_DOE15_12_DIO15_M 0x01000000U +#define GPIO_DOE15_12_DIO15_S 24U +#define GPIO_DOE15_12_DIO15_EN 0x01000000U +#define GPIO_DOE15_12_DIO15_DIS 0x00000000U + +// Field: [16] DIO14 +// +// Data output enable for DIO14 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE15_12_DIO14 0x00010000U +#define GPIO_DOE15_12_DIO14_M 0x00010000U +#define GPIO_DOE15_12_DIO14_S 16U +#define GPIO_DOE15_12_DIO14_EN 0x00010000U +#define GPIO_DOE15_12_DIO14_DIS 0x00000000U + +// Field: [8] DIO13 +// +// Data output enable for DIO13 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE15_12_DIO13 0x00000100U +#define GPIO_DOE15_12_DIO13_M 0x00000100U +#define GPIO_DOE15_12_DIO13_S 8U +#define GPIO_DOE15_12_DIO13_EN 0x00000100U +#define GPIO_DOE15_12_DIO13_DIS 0x00000000U + +// Field: [0] DIO12 +// +// Data output enable for DIO12 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE15_12_DIO12 0x00000001U +#define GPIO_DOE15_12_DIO12_M 0x00000001U +#define GPIO_DOE15_12_DIO12_S 0U +#define GPIO_DOE15_12_DIO12_EN 0x00000001U +#define GPIO_DOE15_12_DIO12_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Data output enable for DIO19 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE19_16_DIO19 0x01000000U +#define GPIO_DOE19_16_DIO19_M 0x01000000U +#define GPIO_DOE19_16_DIO19_S 24U +#define GPIO_DOE19_16_DIO19_EN 0x01000000U +#define GPIO_DOE19_16_DIO19_DIS 0x00000000U + +// Field: [16] DIO18 +// +// Data output enable for DIO18 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE19_16_DIO18 0x00010000U +#define GPIO_DOE19_16_DIO18_M 0x00010000U +#define GPIO_DOE19_16_DIO18_S 16U +#define GPIO_DOE19_16_DIO18_EN 0x00010000U +#define GPIO_DOE19_16_DIO18_DIS 0x00000000U + +// Field: [8] DIO17 +// +// Data output enable for DIO17 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE19_16_DIO17 0x00000100U +#define GPIO_DOE19_16_DIO17_M 0x00000100U +#define GPIO_DOE19_16_DIO17_S 8U +#define GPIO_DOE19_16_DIO17_EN 0x00000100U +#define GPIO_DOE19_16_DIO17_DIS 0x00000000U + +// Field: [0] DIO16 +// +// Data output enable for DIO16 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE19_16_DIO16 0x00000001U +#define GPIO_DOE19_16_DIO16_M 0x00000001U +#define GPIO_DOE19_16_DIO16_S 0U +#define GPIO_DOE19_16_DIO16_EN 0x00000001U +#define GPIO_DOE19_16_DIO16_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Data output enable for DIO23 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE23_20_DIO23 0x01000000U +#define GPIO_DOE23_20_DIO23_M 0x01000000U +#define GPIO_DOE23_20_DIO23_S 24U +#define GPIO_DOE23_20_DIO23_EN 0x01000000U +#define GPIO_DOE23_20_DIO23_DIS 0x00000000U + +// Field: [16] DIO22 +// +// Data output enable for DIO22 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE23_20_DIO22 0x00010000U +#define GPIO_DOE23_20_DIO22_M 0x00010000U +#define GPIO_DOE23_20_DIO22_S 16U +#define GPIO_DOE23_20_DIO22_EN 0x00010000U +#define GPIO_DOE23_20_DIO22_DIS 0x00000000U + +// Field: [8] DIO21 +// +// Data output enable for DIO21 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE23_20_DIO21 0x00000100U +#define GPIO_DOE23_20_DIO21_M 0x00000100U +#define GPIO_DOE23_20_DIO21_S 8U +#define GPIO_DOE23_20_DIO21_EN 0x00000100U +#define GPIO_DOE23_20_DIO21_DIS 0x00000000U + +// Field: [0] DIO20 +// +// Data output enable for DIO20 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE23_20_DIO20 0x00000001U +#define GPIO_DOE23_20_DIO20_M 0x00000001U +#define GPIO_DOE23_20_DIO20_S 0U +#define GPIO_DOE23_20_DIO20_EN 0x00000001U +#define GPIO_DOE23_20_DIO20_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE27_24 +// +//***************************************************************************** +// Field: [8] DIO25 +// +// Data output enable for DIO25 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE27_24_DIO25 0x00000100U +#define GPIO_DOE27_24_DIO25_M 0x00000100U +#define GPIO_DOE27_24_DIO25_S 8U +#define GPIO_DOE27_24_DIO25_EN 0x00000100U +#define GPIO_DOE27_24_DIO25_DIS 0x00000000U + +// Field: [0] DIO24 +// +// Data output enable for DIO24 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE27_24_DIO24 0x00000001U +#define GPIO_DOE27_24_DIO24_M 0x00000001U +#define GPIO_DOE27_24_DIO24_S 0U +#define GPIO_DOE27_24_DIO24_EN 0x00000001U +#define GPIO_DOE27_24_DIO24_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Data output enable for DIO25 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO25 0x02000000U +#define GPIO_DOE31_0_DIO25_M 0x02000000U +#define GPIO_DOE31_0_DIO25_S 25U +#define GPIO_DOE31_0_DIO25_EN 0x02000000U +#define GPIO_DOE31_0_DIO25_DIS 0x00000000U + +// Field: [24] DIO24 +// +// Data output enable for DIO24 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO24 0x01000000U +#define GPIO_DOE31_0_DIO24_M 0x01000000U +#define GPIO_DOE31_0_DIO24_S 24U +#define GPIO_DOE31_0_DIO24_EN 0x01000000U +#define GPIO_DOE31_0_DIO24_DIS 0x00000000U + +// Field: [23] DIO23 +// +// Data output enable for DIO23 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO23 0x00800000U +#define GPIO_DOE31_0_DIO23_M 0x00800000U +#define GPIO_DOE31_0_DIO23_S 23U +#define GPIO_DOE31_0_DIO23_EN 0x00800000U +#define GPIO_DOE31_0_DIO23_DIS 0x00000000U + +// Field: [22] DIO22 +// +// Data output enable for DIO22 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO22 0x00400000U +#define GPIO_DOE31_0_DIO22_M 0x00400000U +#define GPIO_DOE31_0_DIO22_S 22U +#define GPIO_DOE31_0_DIO22_EN 0x00400000U +#define GPIO_DOE31_0_DIO22_DIS 0x00000000U + +// Field: [21] DIO21 +// +// Data output enable for DIO21 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO21 0x00200000U +#define GPIO_DOE31_0_DIO21_M 0x00200000U +#define GPIO_DOE31_0_DIO21_S 21U +#define GPIO_DOE31_0_DIO21_EN 0x00200000U +#define GPIO_DOE31_0_DIO21_DIS 0x00000000U + +// Field: [20] DIO20 +// +// Data output enable for DIO20 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO20 0x00100000U +#define GPIO_DOE31_0_DIO20_M 0x00100000U +#define GPIO_DOE31_0_DIO20_S 20U +#define GPIO_DOE31_0_DIO20_EN 0x00100000U +#define GPIO_DOE31_0_DIO20_DIS 0x00000000U + +// Field: [19] DIO19 +// +// Data output enable for DIO19 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO19 0x00080000U +#define GPIO_DOE31_0_DIO19_M 0x00080000U +#define GPIO_DOE31_0_DIO19_S 19U +#define GPIO_DOE31_0_DIO19_EN 0x00080000U +#define GPIO_DOE31_0_DIO19_DIS 0x00000000U + +// Field: [18] DIO18 +// +// Data output enable for DIO18 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO18 0x00040000U +#define GPIO_DOE31_0_DIO18_M 0x00040000U +#define GPIO_DOE31_0_DIO18_S 18U +#define GPIO_DOE31_0_DIO18_EN 0x00040000U +#define GPIO_DOE31_0_DIO18_DIS 0x00000000U + +// Field: [17] DIO17 +// +// Data output enable for DIO17 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO17 0x00020000U +#define GPIO_DOE31_0_DIO17_M 0x00020000U +#define GPIO_DOE31_0_DIO17_S 17U +#define GPIO_DOE31_0_DIO17_EN 0x00020000U +#define GPIO_DOE31_0_DIO17_DIS 0x00000000U + +// Field: [16] DIO16 +// +// Data output enable for DIO16 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO16 0x00010000U +#define GPIO_DOE31_0_DIO16_M 0x00010000U +#define GPIO_DOE31_0_DIO16_S 16U +#define GPIO_DOE31_0_DIO16_EN 0x00010000U +#define GPIO_DOE31_0_DIO16_DIS 0x00000000U + +// Field: [15] DIO15 +// +// Data output enable for DIO15 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO15 0x00008000U +#define GPIO_DOE31_0_DIO15_M 0x00008000U +#define GPIO_DOE31_0_DIO15_S 15U +#define GPIO_DOE31_0_DIO15_EN 0x00008000U +#define GPIO_DOE31_0_DIO15_DIS 0x00000000U + +// Field: [14] DIO14 +// +// Data output enable for DIO14 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO14 0x00004000U +#define GPIO_DOE31_0_DIO14_M 0x00004000U +#define GPIO_DOE31_0_DIO14_S 14U +#define GPIO_DOE31_0_DIO14_EN 0x00004000U +#define GPIO_DOE31_0_DIO14_DIS 0x00000000U + +// Field: [13] DIO13 +// +// Data output enable for DIO13 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO13 0x00002000U +#define GPIO_DOE31_0_DIO13_M 0x00002000U +#define GPIO_DOE31_0_DIO13_S 13U +#define GPIO_DOE31_0_DIO13_EN 0x00002000U +#define GPIO_DOE31_0_DIO13_DIS 0x00000000U + +// Field: [12] DIO12 +// +// Data output enable for DIO12 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO12 0x00001000U +#define GPIO_DOE31_0_DIO12_M 0x00001000U +#define GPIO_DOE31_0_DIO12_S 12U +#define GPIO_DOE31_0_DIO12_EN 0x00001000U +#define GPIO_DOE31_0_DIO12_DIS 0x00000000U + +// Field: [11] DIO11 +// +// Data output enable for DIO11 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO11 0x00000800U +#define GPIO_DOE31_0_DIO11_M 0x00000800U +#define GPIO_DOE31_0_DIO11_S 11U +#define GPIO_DOE31_0_DIO11_EN 0x00000800U +#define GPIO_DOE31_0_DIO11_DIS 0x00000000U + +// Field: [10] DIO10 +// +// Data output enable for DIO10 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO10 0x00000400U +#define GPIO_DOE31_0_DIO10_M 0x00000400U +#define GPIO_DOE31_0_DIO10_S 10U +#define GPIO_DOE31_0_DIO10_EN 0x00000400U +#define GPIO_DOE31_0_DIO10_DIS 0x00000000U + +// Field: [9] DIO9 +// +// Data output enable for DIO9 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO9 0x00000200U +#define GPIO_DOE31_0_DIO9_M 0x00000200U +#define GPIO_DOE31_0_DIO9_S 9U +#define GPIO_DOE31_0_DIO9_EN 0x00000200U +#define GPIO_DOE31_0_DIO9_DIS 0x00000000U + +// Field: [8] DIO8 +// +// Data output enable for DIO8 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO8 0x00000100U +#define GPIO_DOE31_0_DIO8_M 0x00000100U +#define GPIO_DOE31_0_DIO8_S 8U +#define GPIO_DOE31_0_DIO8_EN 0x00000100U +#define GPIO_DOE31_0_DIO8_DIS 0x00000000U + +// Field: [7] DIO7 +// +// Data output enable for DIO7 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO7 0x00000080U +#define GPIO_DOE31_0_DIO7_M 0x00000080U +#define GPIO_DOE31_0_DIO7_S 7U +#define GPIO_DOE31_0_DIO7_EN 0x00000080U +#define GPIO_DOE31_0_DIO7_DIS 0x00000000U + +// Field: [6] DIO6 +// +// Data output enable for DIO6 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO6 0x00000040U +#define GPIO_DOE31_0_DIO6_M 0x00000040U +#define GPIO_DOE31_0_DIO6_S 6U +#define GPIO_DOE31_0_DIO6_EN 0x00000040U +#define GPIO_DOE31_0_DIO6_DIS 0x00000000U + +// Field: [5] DIO5 +// +// Data output enable for DIO5 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO5 0x00000020U +#define GPIO_DOE31_0_DIO5_M 0x00000020U +#define GPIO_DOE31_0_DIO5_S 5U +#define GPIO_DOE31_0_DIO5_EN 0x00000020U +#define GPIO_DOE31_0_DIO5_DIS 0x00000000U + +// Field: [4] DIO4 +// +// Data output enable for DIO4 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO4 0x00000010U +#define GPIO_DOE31_0_DIO4_M 0x00000010U +#define GPIO_DOE31_0_DIO4_S 4U +#define GPIO_DOE31_0_DIO4_EN 0x00000010U +#define GPIO_DOE31_0_DIO4_DIS 0x00000000U + +// Field: [3] DIO3 +// +// Data output enable for DIO3 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO3 0x00000008U +#define GPIO_DOE31_0_DIO3_M 0x00000008U +#define GPIO_DOE31_0_DIO3_S 3U +#define GPIO_DOE31_0_DIO3_EN 0x00000008U +#define GPIO_DOE31_0_DIO3_DIS 0x00000000U + +// Field: [2] DIO2 +// +// Data output enable for DIO2 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO2 0x00000004U +#define GPIO_DOE31_0_DIO2_M 0x00000004U +#define GPIO_DOE31_0_DIO2_S 2U +#define GPIO_DOE31_0_DIO2_EN 0x00000004U +#define GPIO_DOE31_0_DIO2_DIS 0x00000000U + +// Field: [1] DIO1 +// +// Data output enable for DIO1 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO1 0x00000002U +#define GPIO_DOE31_0_DIO1_M 0x00000002U +#define GPIO_DOE31_0_DIO1_S 1U +#define GPIO_DOE31_0_DIO1_EN 0x00000002U +#define GPIO_DOE31_0_DIO1_DIS 0x00000000U + +// Field: [0] DIO0 +// +// Data output enable for DIO0 +// ENUMs: +// EN Output enabled +// DIS Output disabled +#define GPIO_DOE31_0_DIO0 0x00000001U +#define GPIO_DOE31_0_DIO0_M 0x00000001U +#define GPIO_DOE31_0_DIO0_S 0U +#define GPIO_DOE31_0_DIO0_EN 0x00000001U +#define GPIO_DOE31_0_DIO0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOESET31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Sets bit DOE31_0.DIO25 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO25 0x02000000U +#define GPIO_DOESET31_0_DIO25_M 0x02000000U +#define GPIO_DOESET31_0_DIO25_S 25U +#define GPIO_DOESET31_0_DIO25_SET 0x02000000U +#define GPIO_DOESET31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Sets bit DOE31_0.DIO24 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO24 0x01000000U +#define GPIO_DOESET31_0_DIO24_M 0x01000000U +#define GPIO_DOESET31_0_DIO24_S 24U +#define GPIO_DOESET31_0_DIO24_SET 0x01000000U +#define GPIO_DOESET31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Sets bit DOE31_0.DIO23 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO23 0x00800000U +#define GPIO_DOESET31_0_DIO23_M 0x00800000U +#define GPIO_DOESET31_0_DIO23_S 23U +#define GPIO_DOESET31_0_DIO23_SET 0x00800000U +#define GPIO_DOESET31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Sets bit DOE31_0.DIO22 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO22 0x00400000U +#define GPIO_DOESET31_0_DIO22_M 0x00400000U +#define GPIO_DOESET31_0_DIO22_S 22U +#define GPIO_DOESET31_0_DIO22_SET 0x00400000U +#define GPIO_DOESET31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Sets bit DOE31_0.DIO21 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO21 0x00200000U +#define GPIO_DOESET31_0_DIO21_M 0x00200000U +#define GPIO_DOESET31_0_DIO21_S 21U +#define GPIO_DOESET31_0_DIO21_SET 0x00200000U +#define GPIO_DOESET31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Sets bit DOE31_0.DIO20 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO20 0x00100000U +#define GPIO_DOESET31_0_DIO20_M 0x00100000U +#define GPIO_DOESET31_0_DIO20_S 20U +#define GPIO_DOESET31_0_DIO20_SET 0x00100000U +#define GPIO_DOESET31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Sets bit DOE31_0.DIO19 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO19 0x00080000U +#define GPIO_DOESET31_0_DIO19_M 0x00080000U +#define GPIO_DOESET31_0_DIO19_S 19U +#define GPIO_DOESET31_0_DIO19_SET 0x00080000U +#define GPIO_DOESET31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Sets bit DOE31_0.DIO18 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO18 0x00040000U +#define GPIO_DOESET31_0_DIO18_M 0x00040000U +#define GPIO_DOESET31_0_DIO18_S 18U +#define GPIO_DOESET31_0_DIO18_SET 0x00040000U +#define GPIO_DOESET31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Sets bit DOE31_0.DIO17 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO17 0x00020000U +#define GPIO_DOESET31_0_DIO17_M 0x00020000U +#define GPIO_DOESET31_0_DIO17_S 17U +#define GPIO_DOESET31_0_DIO17_SET 0x00020000U +#define GPIO_DOESET31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Sets bit DOE31_0.DIO16 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO16 0x00010000U +#define GPIO_DOESET31_0_DIO16_M 0x00010000U +#define GPIO_DOESET31_0_DIO16_S 16U +#define GPIO_DOESET31_0_DIO16_SET 0x00010000U +#define GPIO_DOESET31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Sets bit DOE31_0.DIO15 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO15 0x00008000U +#define GPIO_DOESET31_0_DIO15_M 0x00008000U +#define GPIO_DOESET31_0_DIO15_S 15U +#define GPIO_DOESET31_0_DIO15_SET 0x00008000U +#define GPIO_DOESET31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Sets bit DOE31_0.DIO14 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO14 0x00004000U +#define GPIO_DOESET31_0_DIO14_M 0x00004000U +#define GPIO_DOESET31_0_DIO14_S 14U +#define GPIO_DOESET31_0_DIO14_SET 0x00004000U +#define GPIO_DOESET31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Sets bit DOE31_0.DIO13 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO13 0x00002000U +#define GPIO_DOESET31_0_DIO13_M 0x00002000U +#define GPIO_DOESET31_0_DIO13_S 13U +#define GPIO_DOESET31_0_DIO13_SET 0x00002000U +#define GPIO_DOESET31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Sets bit DOE31_0.DIO12 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO12 0x00001000U +#define GPIO_DOESET31_0_DIO12_M 0x00001000U +#define GPIO_DOESET31_0_DIO12_S 12U +#define GPIO_DOESET31_0_DIO12_SET 0x00001000U +#define GPIO_DOESET31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Sets bit DOE31_0.DIO11 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO11 0x00000800U +#define GPIO_DOESET31_0_DIO11_M 0x00000800U +#define GPIO_DOESET31_0_DIO11_S 11U +#define GPIO_DOESET31_0_DIO11_SET 0x00000800U +#define GPIO_DOESET31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Sets bit DOE31_0.DIO10 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO10 0x00000400U +#define GPIO_DOESET31_0_DIO10_M 0x00000400U +#define GPIO_DOESET31_0_DIO10_S 10U +#define GPIO_DOESET31_0_DIO10_SET 0x00000400U +#define GPIO_DOESET31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Sets bit DOE31_0.DIO9 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO9 0x00000200U +#define GPIO_DOESET31_0_DIO9_M 0x00000200U +#define GPIO_DOESET31_0_DIO9_S 9U +#define GPIO_DOESET31_0_DIO9_SET 0x00000200U +#define GPIO_DOESET31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Sets bit DOE31_0.DIO8 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO8 0x00000100U +#define GPIO_DOESET31_0_DIO8_M 0x00000100U +#define GPIO_DOESET31_0_DIO8_S 8U +#define GPIO_DOESET31_0_DIO8_SET 0x00000100U +#define GPIO_DOESET31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Sets bit DOE31_0.DIO7 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO7 0x00000080U +#define GPIO_DOESET31_0_DIO7_M 0x00000080U +#define GPIO_DOESET31_0_DIO7_S 7U +#define GPIO_DOESET31_0_DIO7_SET 0x00000080U +#define GPIO_DOESET31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Sets bit DOE31_0.DIO6 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO6 0x00000040U +#define GPIO_DOESET31_0_DIO6_M 0x00000040U +#define GPIO_DOESET31_0_DIO6_S 6U +#define GPIO_DOESET31_0_DIO6_SET 0x00000040U +#define GPIO_DOESET31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Sets bit DOE31_0.DIO5 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO5 0x00000020U +#define GPIO_DOESET31_0_DIO5_M 0x00000020U +#define GPIO_DOESET31_0_DIO5_S 5U +#define GPIO_DOESET31_0_DIO5_SET 0x00000020U +#define GPIO_DOESET31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Sets bit DOE31_0.DIO4 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO4 0x00000010U +#define GPIO_DOESET31_0_DIO4_M 0x00000010U +#define GPIO_DOESET31_0_DIO4_S 4U +#define GPIO_DOESET31_0_DIO4_SET 0x00000010U +#define GPIO_DOESET31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Sets bit DOE31_0.DIO3 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO3 0x00000008U +#define GPIO_DOESET31_0_DIO3_M 0x00000008U +#define GPIO_DOESET31_0_DIO3_S 3U +#define GPIO_DOESET31_0_DIO3_SET 0x00000008U +#define GPIO_DOESET31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Sets bit DOE31_0.DIO2 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO2 0x00000004U +#define GPIO_DOESET31_0_DIO2_M 0x00000004U +#define GPIO_DOESET31_0_DIO2_S 2U +#define GPIO_DOESET31_0_DIO2_SET 0x00000004U +#define GPIO_DOESET31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Sets bit DOE31_0.DIO1 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO1 0x00000002U +#define GPIO_DOESET31_0_DIO1_M 0x00000002U +#define GPIO_DOESET31_0_DIO1_S 1U +#define GPIO_DOESET31_0_DIO1_SET 0x00000002U +#define GPIO_DOESET31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Sets bit DOE31_0.DIO0 +// ENUMs: +// SET +// NOEFF No effect +#define GPIO_DOESET31_0_DIO0 0x00000001U +#define GPIO_DOESET31_0_DIO0_M 0x00000001U +#define GPIO_DOESET31_0_DIO0_S 0U +#define GPIO_DOESET31_0_DIO0_SET 0x00000001U +#define GPIO_DOESET31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOECLR31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Clears bit DOE31_0.DIO25 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO25 0x02000000U +#define GPIO_DOECLR31_0_DIO25_M 0x02000000U +#define GPIO_DOECLR31_0_DIO25_S 25U +#define GPIO_DOECLR31_0_DIO25_CLR 0x02000000U +#define GPIO_DOECLR31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Clears bit DOE31_0.DIO24 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO24 0x01000000U +#define GPIO_DOECLR31_0_DIO24_M 0x01000000U +#define GPIO_DOECLR31_0_DIO24_S 24U +#define GPIO_DOECLR31_0_DIO24_CLR 0x01000000U +#define GPIO_DOECLR31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Clears bit DOE31_0.DIO23 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO23 0x00800000U +#define GPIO_DOECLR31_0_DIO23_M 0x00800000U +#define GPIO_DOECLR31_0_DIO23_S 23U +#define GPIO_DOECLR31_0_DIO23_CLR 0x00800000U +#define GPIO_DOECLR31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Clears bit DOE31_0.DIO22 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO22 0x00400000U +#define GPIO_DOECLR31_0_DIO22_M 0x00400000U +#define GPIO_DOECLR31_0_DIO22_S 22U +#define GPIO_DOECLR31_0_DIO22_CLR 0x00400000U +#define GPIO_DOECLR31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Clears bit DOE31_0.DIO21 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO21 0x00200000U +#define GPIO_DOECLR31_0_DIO21_M 0x00200000U +#define GPIO_DOECLR31_0_DIO21_S 21U +#define GPIO_DOECLR31_0_DIO21_CLR 0x00200000U +#define GPIO_DOECLR31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Clears bit DOE31_0.DIO20 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO20 0x00100000U +#define GPIO_DOECLR31_0_DIO20_M 0x00100000U +#define GPIO_DOECLR31_0_DIO20_S 20U +#define GPIO_DOECLR31_0_DIO20_CLR 0x00100000U +#define GPIO_DOECLR31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Clears bit DOE31_0.DIO19 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO19 0x00080000U +#define GPIO_DOECLR31_0_DIO19_M 0x00080000U +#define GPIO_DOECLR31_0_DIO19_S 19U +#define GPIO_DOECLR31_0_DIO19_CLR 0x00080000U +#define GPIO_DOECLR31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Clears bit DOE31_0.DIO18 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO18 0x00040000U +#define GPIO_DOECLR31_0_DIO18_M 0x00040000U +#define GPIO_DOECLR31_0_DIO18_S 18U +#define GPIO_DOECLR31_0_DIO18_CLR 0x00040000U +#define GPIO_DOECLR31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Clears bit DOE31_0.DIO17 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO17 0x00020000U +#define GPIO_DOECLR31_0_DIO17_M 0x00020000U +#define GPIO_DOECLR31_0_DIO17_S 17U +#define GPIO_DOECLR31_0_DIO17_CLR 0x00020000U +#define GPIO_DOECLR31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Clears bit DOE31_0.DIO16 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO16 0x00010000U +#define GPIO_DOECLR31_0_DIO16_M 0x00010000U +#define GPIO_DOECLR31_0_DIO16_S 16U +#define GPIO_DOECLR31_0_DIO16_CLR 0x00010000U +#define GPIO_DOECLR31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Clears bit DOE31_0.DIO15 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO15 0x00008000U +#define GPIO_DOECLR31_0_DIO15_M 0x00008000U +#define GPIO_DOECLR31_0_DIO15_S 15U +#define GPIO_DOECLR31_0_DIO15_CLR 0x00008000U +#define GPIO_DOECLR31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Clears bit DOE31_0.DIO14 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO14 0x00004000U +#define GPIO_DOECLR31_0_DIO14_M 0x00004000U +#define GPIO_DOECLR31_0_DIO14_S 14U +#define GPIO_DOECLR31_0_DIO14_CLR 0x00004000U +#define GPIO_DOECLR31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Clears bit DOE31_0.DIO13 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO13 0x00002000U +#define GPIO_DOECLR31_0_DIO13_M 0x00002000U +#define GPIO_DOECLR31_0_DIO13_S 13U +#define GPIO_DOECLR31_0_DIO13_CLR 0x00002000U +#define GPIO_DOECLR31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Clears bit DOE31_0.DIO12 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO12 0x00001000U +#define GPIO_DOECLR31_0_DIO12_M 0x00001000U +#define GPIO_DOECLR31_0_DIO12_S 12U +#define GPIO_DOECLR31_0_DIO12_CLR 0x00001000U +#define GPIO_DOECLR31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Clears bit DOE31_0.DIO11 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO11 0x00000800U +#define GPIO_DOECLR31_0_DIO11_M 0x00000800U +#define GPIO_DOECLR31_0_DIO11_S 11U +#define GPIO_DOECLR31_0_DIO11_CLR 0x00000800U +#define GPIO_DOECLR31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Clears bit DOE31_0.DIO10 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO10 0x00000400U +#define GPIO_DOECLR31_0_DIO10_M 0x00000400U +#define GPIO_DOECLR31_0_DIO10_S 10U +#define GPIO_DOECLR31_0_DIO10_CLR 0x00000400U +#define GPIO_DOECLR31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Clears bit DOE31_0.DIO9 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO9 0x00000200U +#define GPIO_DOECLR31_0_DIO9_M 0x00000200U +#define GPIO_DOECLR31_0_DIO9_S 9U +#define GPIO_DOECLR31_0_DIO9_CLR 0x00000200U +#define GPIO_DOECLR31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Clears bit DOE31_0.DIO8 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO8 0x00000100U +#define GPIO_DOECLR31_0_DIO8_M 0x00000100U +#define GPIO_DOECLR31_0_DIO8_S 8U +#define GPIO_DOECLR31_0_DIO8_CLR 0x00000100U +#define GPIO_DOECLR31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Clears bit DOE31_0.DIO7 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO7 0x00000080U +#define GPIO_DOECLR31_0_DIO7_M 0x00000080U +#define GPIO_DOECLR31_0_DIO7_S 7U +#define GPIO_DOECLR31_0_DIO7_CLR 0x00000080U +#define GPIO_DOECLR31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Clears bit DOE31_0.DIO6 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO6 0x00000040U +#define GPIO_DOECLR31_0_DIO6_M 0x00000040U +#define GPIO_DOECLR31_0_DIO6_S 6U +#define GPIO_DOECLR31_0_DIO6_CLR 0x00000040U +#define GPIO_DOECLR31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Clears bit DOE31_0.DIO5 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO5 0x00000020U +#define GPIO_DOECLR31_0_DIO5_M 0x00000020U +#define GPIO_DOECLR31_0_DIO5_S 5U +#define GPIO_DOECLR31_0_DIO5_CLR 0x00000020U +#define GPIO_DOECLR31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Clears bit DOE31_0.DIO4 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO4 0x00000010U +#define GPIO_DOECLR31_0_DIO4_M 0x00000010U +#define GPIO_DOECLR31_0_DIO4_S 4U +#define GPIO_DOECLR31_0_DIO4_CLR 0x00000010U +#define GPIO_DOECLR31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Clears bit DOE31_0.DIO3 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO3 0x00000008U +#define GPIO_DOECLR31_0_DIO3_M 0x00000008U +#define GPIO_DOECLR31_0_DIO3_S 3U +#define GPIO_DOECLR31_0_DIO3_CLR 0x00000008U +#define GPIO_DOECLR31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Clears bit DOE31_0.DIO2 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO2 0x00000004U +#define GPIO_DOECLR31_0_DIO2_M 0x00000004U +#define GPIO_DOECLR31_0_DIO2_S 2U +#define GPIO_DOECLR31_0_DIO2_CLR 0x00000004U +#define GPIO_DOECLR31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Clears bit DOE31_0.DIO1 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO1 0x00000002U +#define GPIO_DOECLR31_0_DIO1_M 0x00000002U +#define GPIO_DOECLR31_0_DIO1_S 1U +#define GPIO_DOECLR31_0_DIO1_CLR 0x00000002U +#define GPIO_DOECLR31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Clears bit DOE31_0.DIO0 +// ENUMs: +// CLR Clear +// NOEFF No effect +#define GPIO_DOECLR31_0_DIO0 0x00000001U +#define GPIO_DOECLR31_0_DIO0_M 0x00000001U +#define GPIO_DOECLR31_0_DIO0_S 0U +#define GPIO_DOECLR31_0_DIO0_CLR 0x00000001U +#define GPIO_DOECLR31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DOETGL31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Toggles bit DOE31_0.DIO25 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO25 0x02000000U +#define GPIO_DOETGL31_0_DIO25_M 0x02000000U +#define GPIO_DOETGL31_0_DIO25_S 25U +#define GPIO_DOETGL31_0_DIO25_TOGGLE 0x02000000U +#define GPIO_DOETGL31_0_DIO25_NOEFF 0x00000000U + +// Field: [24] DIO24 +// +// Toggles bit DOE31_0.DIO24 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO24 0x01000000U +#define GPIO_DOETGL31_0_DIO24_M 0x01000000U +#define GPIO_DOETGL31_0_DIO24_S 24U +#define GPIO_DOETGL31_0_DIO24_TOGGLE 0x01000000U +#define GPIO_DOETGL31_0_DIO24_NOEFF 0x00000000U + +// Field: [23] DIO23 +// +// Toggles bit DOE31_0.DIO23 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO23 0x00800000U +#define GPIO_DOETGL31_0_DIO23_M 0x00800000U +#define GPIO_DOETGL31_0_DIO23_S 23U +#define GPIO_DOETGL31_0_DIO23_TOGGLE 0x00800000U +#define GPIO_DOETGL31_0_DIO23_NOEFF 0x00000000U + +// Field: [22] DIO22 +// +// Toggles bit DOE31_0.DIO22 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO22 0x00400000U +#define GPIO_DOETGL31_0_DIO22_M 0x00400000U +#define GPIO_DOETGL31_0_DIO22_S 22U +#define GPIO_DOETGL31_0_DIO22_TOGGLE 0x00400000U +#define GPIO_DOETGL31_0_DIO22_NOEFF 0x00000000U + +// Field: [21] DIO21 +// +// Toggles bit DOE31_0.DIO21 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO21 0x00200000U +#define GPIO_DOETGL31_0_DIO21_M 0x00200000U +#define GPIO_DOETGL31_0_DIO21_S 21U +#define GPIO_DOETGL31_0_DIO21_TOGGLE 0x00200000U +#define GPIO_DOETGL31_0_DIO21_NOEFF 0x00000000U + +// Field: [20] DIO20 +// +// Toggles bit DOE31_0.DIO20 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO20 0x00100000U +#define GPIO_DOETGL31_0_DIO20_M 0x00100000U +#define GPIO_DOETGL31_0_DIO20_S 20U +#define GPIO_DOETGL31_0_DIO20_TOGGLE 0x00100000U +#define GPIO_DOETGL31_0_DIO20_NOEFF 0x00000000U + +// Field: [19] DIO19 +// +// Toggles bit DOE31_0.DIO19 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO19 0x00080000U +#define GPIO_DOETGL31_0_DIO19_M 0x00080000U +#define GPIO_DOETGL31_0_DIO19_S 19U +#define GPIO_DOETGL31_0_DIO19_TOGGLE 0x00080000U +#define GPIO_DOETGL31_0_DIO19_NOEFF 0x00000000U + +// Field: [18] DIO18 +// +// Toggles bit DOE31_0.DIO18 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO18 0x00040000U +#define GPIO_DOETGL31_0_DIO18_M 0x00040000U +#define GPIO_DOETGL31_0_DIO18_S 18U +#define GPIO_DOETGL31_0_DIO18_TOGGLE 0x00040000U +#define GPIO_DOETGL31_0_DIO18_NOEFF 0x00000000U + +// Field: [17] DIO17 +// +// Toggles bit DOE31_0.DIO17 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO17 0x00020000U +#define GPIO_DOETGL31_0_DIO17_M 0x00020000U +#define GPIO_DOETGL31_0_DIO17_S 17U +#define GPIO_DOETGL31_0_DIO17_TOGGLE 0x00020000U +#define GPIO_DOETGL31_0_DIO17_NOEFF 0x00000000U + +// Field: [16] DIO16 +// +// Toggles bit DOE31_0.DIO16 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO16 0x00010000U +#define GPIO_DOETGL31_0_DIO16_M 0x00010000U +#define GPIO_DOETGL31_0_DIO16_S 16U +#define GPIO_DOETGL31_0_DIO16_TOGGLE 0x00010000U +#define GPIO_DOETGL31_0_DIO16_NOEFF 0x00000000U + +// Field: [15] DIO15 +// +// Toggles bit DOE31_0.DIO15 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO15 0x00008000U +#define GPIO_DOETGL31_0_DIO15_M 0x00008000U +#define GPIO_DOETGL31_0_DIO15_S 15U +#define GPIO_DOETGL31_0_DIO15_TOGGLE 0x00008000U +#define GPIO_DOETGL31_0_DIO15_NOEFF 0x00000000U + +// Field: [14] DIO14 +// +// Toggles bit DOE31_0.DIO14 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO14 0x00004000U +#define GPIO_DOETGL31_0_DIO14_M 0x00004000U +#define GPIO_DOETGL31_0_DIO14_S 14U +#define GPIO_DOETGL31_0_DIO14_TOGGLE 0x00004000U +#define GPIO_DOETGL31_0_DIO14_NOEFF 0x00000000U + +// Field: [13] DIO13 +// +// Toggles bit DOE31_0.DIO13 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO13 0x00002000U +#define GPIO_DOETGL31_0_DIO13_M 0x00002000U +#define GPIO_DOETGL31_0_DIO13_S 13U +#define GPIO_DOETGL31_0_DIO13_TOGGLE 0x00002000U +#define GPIO_DOETGL31_0_DIO13_NOEFF 0x00000000U + +// Field: [12] DIO12 +// +// Toggles bit DOE31_0.DIO12 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO12 0x00001000U +#define GPIO_DOETGL31_0_DIO12_M 0x00001000U +#define GPIO_DOETGL31_0_DIO12_S 12U +#define GPIO_DOETGL31_0_DIO12_TOGGLE 0x00001000U +#define GPIO_DOETGL31_0_DIO12_NOEFF 0x00000000U + +// Field: [11] DIO11 +// +// Toggles bit DOE31_0.DIO11 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO11 0x00000800U +#define GPIO_DOETGL31_0_DIO11_M 0x00000800U +#define GPIO_DOETGL31_0_DIO11_S 11U +#define GPIO_DOETGL31_0_DIO11_TOGGLE 0x00000800U +#define GPIO_DOETGL31_0_DIO11_NOEFF 0x00000000U + +// Field: [10] DIO10 +// +// Toggles bit DOE31_0.DIO10 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO10 0x00000400U +#define GPIO_DOETGL31_0_DIO10_M 0x00000400U +#define GPIO_DOETGL31_0_DIO10_S 10U +#define GPIO_DOETGL31_0_DIO10_TOGGLE 0x00000400U +#define GPIO_DOETGL31_0_DIO10_NOEFF 0x00000000U + +// Field: [9] DIO9 +// +// Toggles bit DOE31_0.DIO9 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO9 0x00000200U +#define GPIO_DOETGL31_0_DIO9_M 0x00000200U +#define GPIO_DOETGL31_0_DIO9_S 9U +#define GPIO_DOETGL31_0_DIO9_TOGGLE 0x00000200U +#define GPIO_DOETGL31_0_DIO9_NOEFF 0x00000000U + +// Field: [8] DIO8 +// +// Toggles bit DOE31_0.DIO8 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO8 0x00000100U +#define GPIO_DOETGL31_0_DIO8_M 0x00000100U +#define GPIO_DOETGL31_0_DIO8_S 8U +#define GPIO_DOETGL31_0_DIO8_TOGGLE 0x00000100U +#define GPIO_DOETGL31_0_DIO8_NOEFF 0x00000000U + +// Field: [7] DIO7 +// +// Toggles bit DOE31_0.DIO7 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO7 0x00000080U +#define GPIO_DOETGL31_0_DIO7_M 0x00000080U +#define GPIO_DOETGL31_0_DIO7_S 7U +#define GPIO_DOETGL31_0_DIO7_TOGGLE 0x00000080U +#define GPIO_DOETGL31_0_DIO7_NOEFF 0x00000000U + +// Field: [6] DIO6 +// +// Toggles bit DOE31_0.DIO6 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO6 0x00000040U +#define GPIO_DOETGL31_0_DIO6_M 0x00000040U +#define GPIO_DOETGL31_0_DIO6_S 6U +#define GPIO_DOETGL31_0_DIO6_TOGGLE 0x00000040U +#define GPIO_DOETGL31_0_DIO6_NOEFF 0x00000000U + +// Field: [5] DIO5 +// +// Toggles bit DOE31_0.DIO5 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO5 0x00000020U +#define GPIO_DOETGL31_0_DIO5_M 0x00000020U +#define GPIO_DOETGL31_0_DIO5_S 5U +#define GPIO_DOETGL31_0_DIO5_TOGGLE 0x00000020U +#define GPIO_DOETGL31_0_DIO5_NOEFF 0x00000000U + +// Field: [4] DIO4 +// +// Toggles bit DOE31_0.DIO4 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO4 0x00000010U +#define GPIO_DOETGL31_0_DIO4_M 0x00000010U +#define GPIO_DOETGL31_0_DIO4_S 4U +#define GPIO_DOETGL31_0_DIO4_TOGGLE 0x00000010U +#define GPIO_DOETGL31_0_DIO4_NOEFF 0x00000000U + +// Field: [3] DIO3 +// +// Toggles bit DOE31_0.DIO3 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO3 0x00000008U +#define GPIO_DOETGL31_0_DIO3_M 0x00000008U +#define GPIO_DOETGL31_0_DIO3_S 3U +#define GPIO_DOETGL31_0_DIO3_TOGGLE 0x00000008U +#define GPIO_DOETGL31_0_DIO3_NOEFF 0x00000000U + +// Field: [2] DIO2 +// +// Toggles bit DOE31_0.DIO2 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO2 0x00000004U +#define GPIO_DOETGL31_0_DIO2_M 0x00000004U +#define GPIO_DOETGL31_0_DIO2_S 2U +#define GPIO_DOETGL31_0_DIO2_TOGGLE 0x00000004U +#define GPIO_DOETGL31_0_DIO2_NOEFF 0x00000000U + +// Field: [1] DIO1 +// +// Toggles bit DOE31_0.DIO1 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO1 0x00000002U +#define GPIO_DOETGL31_0_DIO1_M 0x00000002U +#define GPIO_DOETGL31_0_DIO1_S 1U +#define GPIO_DOETGL31_0_DIO1_TOGGLE 0x00000002U +#define GPIO_DOETGL31_0_DIO1_NOEFF 0x00000000U + +// Field: [0] DIO0 +// +// Toggles bit DOE31_0.DIO0 +// ENUMs: +// TOGGLE Toggle +// NOEFF No effect +#define GPIO_DOETGL31_0_DIO0 0x00000001U +#define GPIO_DOETGL31_0_DIO0_M 0x00000001U +#define GPIO_DOETGL31_0_DIO0_S 0U +#define GPIO_DOETGL31_0_DIO0_TOGGLE 0x00000001U +#define GPIO_DOETGL31_0_DIO0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Data input from DIO3 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN3_0_DIO3 0x01000000U +#define GPIO_DIN3_0_DIO3_M 0x01000000U +#define GPIO_DIN3_0_DIO3_S 24U +#define GPIO_DIN3_0_DIO3_ONE 0x01000000U +#define GPIO_DIN3_0_DIO3_ZERO 0x00000000U + +// Field: [16] DIO2 +// +// Data input from DIO2 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN3_0_DIO2 0x00010000U +#define GPIO_DIN3_0_DIO2_M 0x00010000U +#define GPIO_DIN3_0_DIO2_S 16U +#define GPIO_DIN3_0_DIO2_ONE 0x00010000U +#define GPIO_DIN3_0_DIO2_ZERO 0x00000000U + +// Field: [8] DIO1 +// +// Data input from DIO1 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN3_0_DIO1 0x00000100U +#define GPIO_DIN3_0_DIO1_M 0x00000100U +#define GPIO_DIN3_0_DIO1_S 8U +#define GPIO_DIN3_0_DIO1_ONE 0x00000100U +#define GPIO_DIN3_0_DIO1_ZERO 0x00000000U + +// Field: [0] DIO0 +// +// Data input from DIO0 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN3_0_DIO0 0x00000001U +#define GPIO_DIN3_0_DIO0_M 0x00000001U +#define GPIO_DIN3_0_DIO0_S 0U +#define GPIO_DIN3_0_DIO0_ONE 0x00000001U +#define GPIO_DIN3_0_DIO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Data input from DIO7 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN7_4_DIO7 0x01000000U +#define GPIO_DIN7_4_DIO7_M 0x01000000U +#define GPIO_DIN7_4_DIO7_S 24U +#define GPIO_DIN7_4_DIO7_ONE 0x01000000U +#define GPIO_DIN7_4_DIO7_ZERO 0x00000000U + +// Field: [16] DIO6 +// +// Data input from DIO6 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN7_4_DIO6 0x00010000U +#define GPIO_DIN7_4_DIO6_M 0x00010000U +#define GPIO_DIN7_4_DIO6_S 16U +#define GPIO_DIN7_4_DIO6_ONE 0x00010000U +#define GPIO_DIN7_4_DIO6_ZERO 0x00000000U + +// Field: [8] DIO5 +// +// Data input from DIO5 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN7_4_DIO5 0x00000100U +#define GPIO_DIN7_4_DIO5_M 0x00000100U +#define GPIO_DIN7_4_DIO5_S 8U +#define GPIO_DIN7_4_DIO5_ONE 0x00000100U +#define GPIO_DIN7_4_DIO5_ZERO 0x00000000U + +// Field: [0] DIO4 +// +// Data input from DIO4 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN7_4_DIO4 0x00000001U +#define GPIO_DIN7_4_DIO4_M 0x00000001U +#define GPIO_DIN7_4_DIO4_S 0U +#define GPIO_DIN7_4_DIO4_ONE 0x00000001U +#define GPIO_DIN7_4_DIO4_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Data input from DIO11 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN11_8_DIO11 0x01000000U +#define GPIO_DIN11_8_DIO11_M 0x01000000U +#define GPIO_DIN11_8_DIO11_S 24U +#define GPIO_DIN11_8_DIO11_ONE 0x01000000U +#define GPIO_DIN11_8_DIO11_ZERO 0x00000000U + +// Field: [16] DIO10 +// +// Data input from DIO10 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN11_8_DIO10 0x00010000U +#define GPIO_DIN11_8_DIO10_M 0x00010000U +#define GPIO_DIN11_8_DIO10_S 16U +#define GPIO_DIN11_8_DIO10_ONE 0x00010000U +#define GPIO_DIN11_8_DIO10_ZERO 0x00000000U + +// Field: [8] DIO9 +// +// Data input from DIO9 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN11_8_DIO9 0x00000100U +#define GPIO_DIN11_8_DIO9_M 0x00000100U +#define GPIO_DIN11_8_DIO9_S 8U +#define GPIO_DIN11_8_DIO9_ONE 0x00000100U +#define GPIO_DIN11_8_DIO9_ZERO 0x00000000U + +// Field: [0] DIO8 +// +// Data input from DIO8 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN11_8_DIO8 0x00000001U +#define GPIO_DIN11_8_DIO8_M 0x00000001U +#define GPIO_DIN11_8_DIO8_S 0U +#define GPIO_DIN11_8_DIO8_ONE 0x00000001U +#define GPIO_DIN11_8_DIO8_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Data input from DIO15 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN15_12_DIO15 0x01000000U +#define GPIO_DIN15_12_DIO15_M 0x01000000U +#define GPIO_DIN15_12_DIO15_S 24U +#define GPIO_DIN15_12_DIO15_ONE 0x01000000U +#define GPIO_DIN15_12_DIO15_ZERO 0x00000000U + +// Field: [16] DIO14 +// +// Data input from DIO14 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN15_12_DIO14 0x00010000U +#define GPIO_DIN15_12_DIO14_M 0x00010000U +#define GPIO_DIN15_12_DIO14_S 16U +#define GPIO_DIN15_12_DIO14_ONE 0x00010000U +#define GPIO_DIN15_12_DIO14_ZERO 0x00000000U + +// Field: [8] DIO13 +// +// Data input from DIO13 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN15_12_DIO13 0x00000100U +#define GPIO_DIN15_12_DIO13_M 0x00000100U +#define GPIO_DIN15_12_DIO13_S 8U +#define GPIO_DIN15_12_DIO13_ONE 0x00000100U +#define GPIO_DIN15_12_DIO13_ZERO 0x00000000U + +// Field: [0] DIO12 +// +// Data input from DIO12 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN15_12_DIO12 0x00000001U +#define GPIO_DIN15_12_DIO12_M 0x00000001U +#define GPIO_DIN15_12_DIO12_S 0U +#define GPIO_DIN15_12_DIO12_ONE 0x00000001U +#define GPIO_DIN15_12_DIO12_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Data input from DIO19 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN19_16_DIO19 0x01000000U +#define GPIO_DIN19_16_DIO19_M 0x01000000U +#define GPIO_DIN19_16_DIO19_S 24U +#define GPIO_DIN19_16_DIO19_ONE 0x01000000U +#define GPIO_DIN19_16_DIO19_ZERO 0x00000000U + +// Field: [16] DIO18 +// +// Data input from DIO18 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN19_16_DIO18 0x00010000U +#define GPIO_DIN19_16_DIO18_M 0x00010000U +#define GPIO_DIN19_16_DIO18_S 16U +#define GPIO_DIN19_16_DIO18_ONE 0x00010000U +#define GPIO_DIN19_16_DIO18_ZERO 0x00000000U + +// Field: [8] DIO17 +// +// Data input from DIO17 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN19_16_DIO17 0x00000100U +#define GPIO_DIN19_16_DIO17_M 0x00000100U +#define GPIO_DIN19_16_DIO17_S 8U +#define GPIO_DIN19_16_DIO17_ONE 0x00000100U +#define GPIO_DIN19_16_DIO17_ZERO 0x00000000U + +// Field: [0] DIO16 +// +// Data input from DIO16 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN19_16_DIO16 0x00000001U +#define GPIO_DIN19_16_DIO16_M 0x00000001U +#define GPIO_DIN19_16_DIO16_S 0U +#define GPIO_DIN19_16_DIO16_ONE 0x00000001U +#define GPIO_DIN19_16_DIO16_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Data input from DIO23 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN23_20_DIO23 0x01000000U +#define GPIO_DIN23_20_DIO23_M 0x01000000U +#define GPIO_DIN23_20_DIO23_S 24U +#define GPIO_DIN23_20_DIO23_ONE 0x01000000U +#define GPIO_DIN23_20_DIO23_ZERO 0x00000000U + +// Field: [16] DIO22 +// +// Data input from DIO22 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN23_20_DIO22 0x00010000U +#define GPIO_DIN23_20_DIO22_M 0x00010000U +#define GPIO_DIN23_20_DIO22_S 16U +#define GPIO_DIN23_20_DIO22_ONE 0x00010000U +#define GPIO_DIN23_20_DIO22_ZERO 0x00000000U + +// Field: [8] DIO21 +// +// Data input from DIO21 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN23_20_DIO21 0x00000100U +#define GPIO_DIN23_20_DIO21_M 0x00000100U +#define GPIO_DIN23_20_DIO21_S 8U +#define GPIO_DIN23_20_DIO21_ONE 0x00000100U +#define GPIO_DIN23_20_DIO21_ZERO 0x00000000U + +// Field: [0] DIO20 +// +// Data input from DIO20 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN23_20_DIO20 0x00000001U +#define GPIO_DIN23_20_DIO20_M 0x00000001U +#define GPIO_DIN23_20_DIO20_S 0U +#define GPIO_DIN23_20_DIO20_ONE 0x00000001U +#define GPIO_DIN23_20_DIO20_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN27_24 +// +//***************************************************************************** +// Field: [8] DIO25 +// +// Data input from DIO25 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN27_24_DIO25 0x00000100U +#define GPIO_DIN27_24_DIO25_M 0x00000100U +#define GPIO_DIN27_24_DIO25_S 8U +#define GPIO_DIN27_24_DIO25_ONE 0x00000100U +#define GPIO_DIN27_24_DIO25_ZERO 0x00000000U + +// Field: [0] DIO24 +// +// Data input from DIO24 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN27_24_DIO24 0x00000001U +#define GPIO_DIN27_24_DIO24_M 0x00000001U +#define GPIO_DIN27_24_DIO24_S 0U +#define GPIO_DIN27_24_DIO24_ONE 0x00000001U +#define GPIO_DIN27_24_DIO24_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [25] DIO25 +// +// Data input from DIO25 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO25 0x02000000U +#define GPIO_DIN31_0_DIO25_M 0x02000000U +#define GPIO_DIN31_0_DIO25_S 25U +#define GPIO_DIN31_0_DIO25_ONE 0x02000000U +#define GPIO_DIN31_0_DIO25_ZERO 0x00000000U + +// Field: [24] DIO24 +// +// Data input from DIO24 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO24 0x01000000U +#define GPIO_DIN31_0_DIO24_M 0x01000000U +#define GPIO_DIN31_0_DIO24_S 24U +#define GPIO_DIN31_0_DIO24_ONE 0x01000000U +#define GPIO_DIN31_0_DIO24_ZERO 0x00000000U + +// Field: [23] DIO23 +// +// Data input from DIO23 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO23 0x00800000U +#define GPIO_DIN31_0_DIO23_M 0x00800000U +#define GPIO_DIN31_0_DIO23_S 23U +#define GPIO_DIN31_0_DIO23_ONE 0x00800000U +#define GPIO_DIN31_0_DIO23_ZERO 0x00000000U + +// Field: [22] DIO22 +// +// Data input from DIO22 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO22 0x00400000U +#define GPIO_DIN31_0_DIO22_M 0x00400000U +#define GPIO_DIN31_0_DIO22_S 22U +#define GPIO_DIN31_0_DIO22_ONE 0x00400000U +#define GPIO_DIN31_0_DIO22_ZERO 0x00000000U + +// Field: [21] DIO21 +// +// Data input from DIO21 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO21 0x00200000U +#define GPIO_DIN31_0_DIO21_M 0x00200000U +#define GPIO_DIN31_0_DIO21_S 21U +#define GPIO_DIN31_0_DIO21_ONE 0x00200000U +#define GPIO_DIN31_0_DIO21_ZERO 0x00000000U + +// Field: [20] DIO20 +// +// Data input from DIO20 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO20 0x00100000U +#define GPIO_DIN31_0_DIO20_M 0x00100000U +#define GPIO_DIN31_0_DIO20_S 20U +#define GPIO_DIN31_0_DIO20_ONE 0x00100000U +#define GPIO_DIN31_0_DIO20_ZERO 0x00000000U + +// Field: [19] DIO19 +// +// Data input from DIO19 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO19 0x00080000U +#define GPIO_DIN31_0_DIO19_M 0x00080000U +#define GPIO_DIN31_0_DIO19_S 19U +#define GPIO_DIN31_0_DIO19_ONE 0x00080000U +#define GPIO_DIN31_0_DIO19_ZERO 0x00000000U + +// Field: [18] DIO18 +// +// Data input from DIO18 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO18 0x00040000U +#define GPIO_DIN31_0_DIO18_M 0x00040000U +#define GPIO_DIN31_0_DIO18_S 18U +#define GPIO_DIN31_0_DIO18_ONE 0x00040000U +#define GPIO_DIN31_0_DIO18_ZERO 0x00000000U + +// Field: [17] DIO17 +// +// Data input from DIO17 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO17 0x00020000U +#define GPIO_DIN31_0_DIO17_M 0x00020000U +#define GPIO_DIN31_0_DIO17_S 17U +#define GPIO_DIN31_0_DIO17_ONE 0x00020000U +#define GPIO_DIN31_0_DIO17_ZERO 0x00000000U + +// Field: [16] DIO16 +// +// Data input from DIO16 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO16 0x00010000U +#define GPIO_DIN31_0_DIO16_M 0x00010000U +#define GPIO_DIN31_0_DIO16_S 16U +#define GPIO_DIN31_0_DIO16_ONE 0x00010000U +#define GPIO_DIN31_0_DIO16_ZERO 0x00000000U + +// Field: [15] DIO15 +// +// Data input from DIO15 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO15 0x00008000U +#define GPIO_DIN31_0_DIO15_M 0x00008000U +#define GPIO_DIN31_0_DIO15_S 15U +#define GPIO_DIN31_0_DIO15_ONE 0x00008000U +#define GPIO_DIN31_0_DIO15_ZERO 0x00000000U + +// Field: [14] DIO14 +// +// Data input from DIO14 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO14 0x00004000U +#define GPIO_DIN31_0_DIO14_M 0x00004000U +#define GPIO_DIN31_0_DIO14_S 14U +#define GPIO_DIN31_0_DIO14_ONE 0x00004000U +#define GPIO_DIN31_0_DIO14_ZERO 0x00000000U + +// Field: [13] DIO13 +// +// Data input from DIO13 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO13 0x00002000U +#define GPIO_DIN31_0_DIO13_M 0x00002000U +#define GPIO_DIN31_0_DIO13_S 13U +#define GPIO_DIN31_0_DIO13_ONE 0x00002000U +#define GPIO_DIN31_0_DIO13_ZERO 0x00000000U + +// Field: [12] DIO12 +// +// Data input from DIO12 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO12 0x00001000U +#define GPIO_DIN31_0_DIO12_M 0x00001000U +#define GPIO_DIN31_0_DIO12_S 12U +#define GPIO_DIN31_0_DIO12_ONE 0x00001000U +#define GPIO_DIN31_0_DIO12_ZERO 0x00000000U + +// Field: [11] DIO11 +// +// Data input from DIO11 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO11 0x00000800U +#define GPIO_DIN31_0_DIO11_M 0x00000800U +#define GPIO_DIN31_0_DIO11_S 11U +#define GPIO_DIN31_0_DIO11_ONE 0x00000800U +#define GPIO_DIN31_0_DIO11_ZERO 0x00000000U + +// Field: [10] DIO10 +// +// Data input from DIO10 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO10 0x00000400U +#define GPIO_DIN31_0_DIO10_M 0x00000400U +#define GPIO_DIN31_0_DIO10_S 10U +#define GPIO_DIN31_0_DIO10_ONE 0x00000400U +#define GPIO_DIN31_0_DIO10_ZERO 0x00000000U + +// Field: [9] DIO9 +// +// Data input from DIO9 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO9 0x00000200U +#define GPIO_DIN31_0_DIO9_M 0x00000200U +#define GPIO_DIN31_0_DIO9_S 9U +#define GPIO_DIN31_0_DIO9_ONE 0x00000200U +#define GPIO_DIN31_0_DIO9_ZERO 0x00000000U + +// Field: [8] DIO8 +// +// Data input from DIO8 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO8 0x00000100U +#define GPIO_DIN31_0_DIO8_M 0x00000100U +#define GPIO_DIN31_0_DIO8_S 8U +#define GPIO_DIN31_0_DIO8_ONE 0x00000100U +#define GPIO_DIN31_0_DIO8_ZERO 0x00000000U + +// Field: [7] DIO7 +// +// Data input from DIO7 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO7 0x00000080U +#define GPIO_DIN31_0_DIO7_M 0x00000080U +#define GPIO_DIN31_0_DIO7_S 7U +#define GPIO_DIN31_0_DIO7_ONE 0x00000080U +#define GPIO_DIN31_0_DIO7_ZERO 0x00000000U + +// Field: [6] DIO6 +// +// Data input from DIO6 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO6 0x00000040U +#define GPIO_DIN31_0_DIO6_M 0x00000040U +#define GPIO_DIN31_0_DIO6_S 6U +#define GPIO_DIN31_0_DIO6_ONE 0x00000040U +#define GPIO_DIN31_0_DIO6_ZERO 0x00000000U + +// Field: [5] DIO5 +// +// Data input from DIO5 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO5 0x00000020U +#define GPIO_DIN31_0_DIO5_M 0x00000020U +#define GPIO_DIN31_0_DIO5_S 5U +#define GPIO_DIN31_0_DIO5_ONE 0x00000020U +#define GPIO_DIN31_0_DIO5_ZERO 0x00000000U + +// Field: [4] DIO4 +// +// Data input from DIO4 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO4 0x00000010U +#define GPIO_DIN31_0_DIO4_M 0x00000010U +#define GPIO_DIN31_0_DIO4_S 4U +#define GPIO_DIN31_0_DIO4_ONE 0x00000010U +#define GPIO_DIN31_0_DIO4_ZERO 0x00000000U + +// Field: [3] DIO3 +// +// Data input from DIO3 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO3 0x00000008U +#define GPIO_DIN31_0_DIO3_M 0x00000008U +#define GPIO_DIN31_0_DIO3_S 3U +#define GPIO_DIN31_0_DIO3_ONE 0x00000008U +#define GPIO_DIN31_0_DIO3_ZERO 0x00000000U + +// Field: [2] DIO2 +// +// Data input from DIO2 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO2 0x00000004U +#define GPIO_DIN31_0_DIO2_M 0x00000004U +#define GPIO_DIN31_0_DIO2_S 2U +#define GPIO_DIN31_0_DIO2_ONE 0x00000004U +#define GPIO_DIN31_0_DIO2_ZERO 0x00000000U + +// Field: [1] DIO1 +// +// Data input from DIO1 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO1 0x00000002U +#define GPIO_DIN31_0_DIO1_M 0x00000002U +#define GPIO_DIN31_0_DIO1_S 1U +#define GPIO_DIN31_0_DIO1_ONE 0x00000002U +#define GPIO_DIN31_0_DIO1_ZERO 0x00000000U + +// Field: [0] DIO0 +// +// Data input from DIO0 +// ENUMs: +// ONE Input value is 1 +// ZERO Input value is 0 +#define GPIO_DIN31_0_DIO0 0x00000001U +#define GPIO_DIN31_0_DIO0_M 0x00000001U +#define GPIO_DIN31_0_DIO0_S 0U +#define GPIO_DIN31_0_DIO0_ONE 0x00000001U +#define GPIO_DIN31_0_DIO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: GPIO_O_EVTCFG +// +//***************************************************************************** +// Field: [8] EVTEN +// +// Enables GPIO to publish edge qualified selected DIO event on SVT event +// fabric. +// Design note: The edge detector flop is cleared automatically for the +// selected DIO once the event is published. +// ENUMs: +// EN Enable +// DIS Disable +#define GPIO_EVTCFG_EVTEN 0x00000100U +#define GPIO_EVTCFG_EVTEN_M 0x00000100U +#define GPIO_EVTCFG_EVTEN_S 8U +#define GPIO_EVTCFG_EVTEN_EN 0x00000100U +#define GPIO_EVTCFG_EVTEN_DIS 0x00000000U + +// Field: [5:0] DIOSEL +// +// This is used to select DIO for event generation. For example, DIOSEL = 0x0 +// selects DIO0 and DIOSEL = 0x8 selects DIO8. +// ENUMs: +// MAXIMUM Maximum value +// MINIMUM Minimum value +#define GPIO_EVTCFG_DIOSEL_W 6U +#define GPIO_EVTCFG_DIOSEL_M 0x0000003FU +#define GPIO_EVTCFG_DIOSEL_S 0U +#define GPIO_EVTCFG_DIOSEL_MAXIMUM 0x0000003FU +#define GPIO_EVTCFG_DIOSEL_MINIMUM 0x00000000U + + +#endif // __GPIO__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_i2c.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_i2c.h new file mode 100644 index 00000000..6492c3f2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_i2c.h @@ -0,0 +1,710 @@ +/****************************************************************************** +* Filename: hw_i2c_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Target Own Address +#define I2C_O_TOAR 0x00000000U + +// Target Control and Status +#define I2C_O_TSTA 0x00000004U + +// Target control +#define I2C_O_TCTL 0x00000004U + +// Target Data +#define I2C_O_TDR 0x00000008U + +// Target Interrupt Mask +#define I2C_O_TIMR 0x0000000CU + +// Target Raw Interrupt Status +#define I2C_O_TRIS 0x00000010U + +// Target Masked Interrupt Status +#define I2C_O_TMIS 0x00000014U + +// Target Interrupt Clear +#define I2C_O_TICR 0x00000018U + +// Controller Target Address +#define I2C_O_CTA 0x00000800U + +// Controller Control and Status +#define I2C_O_CSTA 0x00000804U + +// Controller control +#define I2C_O_CCTL 0x00000804U + +// Controller Data +#define I2C_O_CDR 0x00000808U + +// Controller Timer Period +#define I2C_O_CTPR 0x0000080CU + +// Controller Interrupt Mask +#define I2C_O_CIMR 0x00000810U + +// Controller Raw Interrupt Status +#define I2C_O_CRIS 0x00000814U + +// Controller Masked Interrupt Status +#define I2C_O_CMIS 0x00000818U + +// Controller Interrupt Clear +#define I2C_O_CICR 0x0000081CU + +// Controller Configuration +#define I2C_O_CCR 0x00000820U + +//***************************************************************************** +// +// Register: I2C_O_TOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// Target own address. This field specifies bits a6 through a0 of the target +// address. +#define I2C_TOAR_OAR_W 7U +#define I2C_TOAR_OAR_M 0x0000007FU +#define I2C_TOAR_OAR_S 0U + +//***************************************************************************** +// +// Register: I2C_O_TSTA +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received. +// This bit is only applicable when the TSTA.RREQ bit is set and is +// automatically cleared when data has been read from the TDR register. +// Note: This bit is not used for target transmit operations. +// ENUMs: +// SET The first byte following the target's own address +// has been received. +// CLR The first byte following the target's own address +// has not been received +#define I2C_TSTA_FBR 0x00000004U +#define I2C_TSTA_FBR_M 0x00000004U +#define I2C_TSTA_FBR_S 2U +#define I2C_TSTA_FBR_SET 0x00000004U +#define I2C_TSTA_FBR_CLR 0x00000000U + +// Field: [1] TREQ +// +// This field reflects the transmit request status +// ENUMs: +// SET The I2C has been addressed as a target transmitter +// and is using clock stretching to delay the +// controller until data has been written to the +// TDR register +// CLR No outstanding transmit request +#define I2C_TSTA_TREQ 0x00000002U +#define I2C_TSTA_TREQ_M 0x00000002U +#define I2C_TSTA_TREQ_S 1U +#define I2C_TSTA_TREQ_SET 0x00000002U +#define I2C_TSTA_TREQ_CLR 0x00000000U + +// Field: [0] RREQ +// +// This field reflects the receive request status. +// ENUMs: +// SET The target has outstanding receive data from the +// external controller and is using clock +// stretching to delay the controller until data +// has been read from the TDR register +// CLR No outstanding receive data +#define I2C_TSTA_RREQ 0x00000001U +#define I2C_TSTA_RREQ_M 0x00000001U +#define I2C_TSTA_RREQ_S 0U +#define I2C_TSTA_RREQ_SET 0x00000001U +#define I2C_TSTA_RREQ_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_TCTL +// +//***************************************************************************** +// Field: [0] DA +// +// This field sets the device active control +// ENUMs: +// EN Enable the target operation +// DIS Disable the target operation +#define I2C_TCTL_DA 0x00000001U +#define I2C_TCTL_DA_M 0x00000001U +#define I2C_TCTL_DA_S 0U +#define I2C_TCTL_DA_EN 0x00000001U +#define I2C_TCTL_DA_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_TDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer. This field contains the data for transfer during a target +// receive or a transmit operation. When written, the register data is used as +// transmit data. When read, this register returns the last data received. Data +// is stored until next update, either by a system write to the controller for +// transmit or by an external controller to the target for receive. +#define I2C_TDR_DATA_W 8U +#define I2C_TDR_DATA_M 0x000000FFU +#define I2C_TDR_DATA_S 0U + +//***************************************************************************** +// +// Register: I2C_O_TIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define I2C_TIMR_STOPIM 0x00000004U +#define I2C_TIMR_STOPIM_M 0x00000004U +#define I2C_TIMR_STOPIM_S 2U +#define I2C_TIMR_STOPIM_EN 0x00000004U +#define I2C_TIMR_STOPIM_DIS 0x00000000U + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define I2C_TIMR_STARTIM 0x00000002U +#define I2C_TIMR_STARTIM_M 0x00000002U +#define I2C_TIMR_STARTIM_S 1U +#define I2C_TIMR_STARTIM_EN 0x00000002U +#define I2C_TIMR_STARTIM_DIS 0x00000000U + +// Field: [0] DATAIM +// +// Data interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define I2C_TIMR_DATAIM 0x00000001U +#define I2C_TIMR_DATAIM_M 0x00000001U +#define I2C_TIMR_DATAIM_S 0U +#define I2C_TIMR_DATAIM_EN 0x00000001U +#define I2C_TIMR_DATAIM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_TRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// This bit is cleared by writing a 1 to TICR.STOPIC. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define I2C_TRIS_STOPRIS 0x00000004U +#define I2C_TRIS_STOPRIS_M 0x00000004U +#define I2C_TRIS_STOPRIS_S 2U +#define I2C_TRIS_STOPRIS_SET 0x00000004U +#define I2C_TRIS_STOPRIS_CLR 0x00000000U + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// This bit is cleared by writing a 1 to TICR.STARTIC. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define I2C_TRIS_STARTRIS 0x00000002U +#define I2C_TRIS_STARTRIS_M 0x00000002U +#define I2C_TRIS_STARTRIS_S 1U +#define I2C_TRIS_STARTRIS_SET 0x00000002U +#define I2C_TRIS_STARTRIS_CLR 0x00000000U + +// Field: [0] DATARIS +// +// Data raw interrupt status +// This bit is cleared by writing a 1 to TICR.DATAIC. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define I2C_TRIS_DATARIS 0x00000001U +#define I2C_TRIS_DATARIS_M 0x00000001U +#define I2C_TRIS_DATARIS_S 0U +#define I2C_TRIS_DATARIS_SET 0x00000001U +#define I2C_TRIS_DATARIS_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_TMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// This bit is cleared by writing a 1 to TICR.STOPIC. +// ENUMs: +// SET Masked interrupt occured +// CLR Masked interrupt did not occur +#define I2C_TMIS_STOPMIS 0x00000004U +#define I2C_TMIS_STOPMIS_M 0x00000004U +#define I2C_TMIS_STOPMIS_S 2U +#define I2C_TMIS_STOPMIS_SET 0x00000004U +#define I2C_TMIS_STOPMIS_CLR 0x00000000U + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// This bit is cleared by writing a 1 to TICR.STARTIC. +// ENUMs: +// SET Masked interrput occured +// CLR Masked interrupt did not occur +#define I2C_TMIS_STARTMIS 0x00000002U +#define I2C_TMIS_STARTMIS_M 0x00000002U +#define I2C_TMIS_STARTMIS_S 1U +#define I2C_TMIS_STARTMIS_SET 0x00000002U +#define I2C_TMIS_STARTMIS_CLR 0x00000000U + +// Field: [0] DATAMIS +// +// Start condition masked interrupt status +// This bit is cleared by writing a 1 to TICR.DATAIC. +// ENUMs: +// SET Masked interrupt occured +// CLR Masked interrupt did not occur +#define I2C_TMIS_DATAMIS 0x00000001U +#define I2C_TMIS_DATAMIS_M 0x00000001U +#define I2C_TMIS_DATAMIS_S 0U +#define I2C_TMIS_DATAMIS_SET 0x00000001U +#define I2C_TMIS_DATAMIS_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_TICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// ENUMs: +// EN Clear interrupt +// Writing 1 to this bit +// clears TRIS.STOPRIS and TMIS.STOPMIS +// DIS No effect +#define I2C_TICR_STOPIC 0x00000004U +#define I2C_TICR_STOPIC_M 0x00000004U +#define I2C_TICR_STOPIC_S 2U +#define I2C_TICR_STOPIC_EN 0x00000004U +#define I2C_TICR_STOPIC_DIS 0x00000000U + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// ENUMs: +// EN Clear interrupt +// Writing 1 to this bit +// clears TRIS.STARTRIS and TMIS.STARTMIS +// DIS No effect +#define I2C_TICR_STARTIC 0x00000002U +#define I2C_TICR_STARTIC_M 0x00000002U +#define I2C_TICR_STARTIC_S 1U +#define I2C_TICR_STARTIC_EN 0x00000002U +#define I2C_TICR_STARTIC_DIS 0x00000000U + +// Field: [0] DATAIC +// +// Data interrupt clear +// ENUMs: +// EN Clear interrupt +// Writing 1 to this bit +// clears TRIS.DATARIS and TMIS.DATAMIS +// DIS No effect +#define I2C_TICR_DATAIC 0x00000001U +#define I2C_TICR_DATAIC_M 0x00000001U +#define I2C_TICR_DATAIC_S 0U +#define I2C_TICR_DATAIC_EN 0x00000001U +#define I2C_TICR_DATAIC_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CTA +// +//***************************************************************************** +// Field: [7:1] SA +// +// Controller target address +// Defines which target is addressed for the transaction in controller mode +#define I2C_CTA_SA_W 7U +#define I2C_CTA_SA_M 0x000000FEU +#define I2C_CTA_SA_S 1U + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies the next operation with addressed target CTA.SA. +// ENUMs: +// EN Receive data from target +// DIS Transmit/send data to target +#define I2C_CTA_RS 0x00000001U +#define I2C_CTA_RS_M 0x00000001U +#define I2C_CTA_RS_S 0U +#define I2C_CTA_RS_EN 0x00000001U +#define I2C_CTA_RS_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CSTA +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// Note:The bit changes based on the CCTRL.START and CCTRL.STOP conditions. +// ENUMs: +// SET The bus is busy. +// CLR The bus is idle. +#define I2C_CSTA_BUSBSY 0x00000040U +#define I2C_CSTA_BUSBSY_M 0x00000040U +#define I2C_CSTA_BUSBSY_S 6U +#define I2C_CSTA_BUSBSY_SET 0x00000040U +#define I2C_CSTA_BUSBSY_CLR 0x00000000U + +// Field: [5] IDLE +// +// This field specifies whether I2C is idle or not +// ENUMs: +// SET The controller is idle. +// CLR The controller is not idle. +#define I2C_CSTA_IDLE 0x00000020U +#define I2C_CSTA_IDLE_M 0x00000020U +#define I2C_CSTA_IDLE_S 5U +#define I2C_CSTA_IDLE_SET 0x00000020U +#define I2C_CSTA_IDLE_CLR 0x00000000U + +// Field: [4] ARBLST +// +// The filed specifies the arbitration status +// ENUMs: +// SET The controller lost arbitration. +// CLR The controller won arbitration. +#define I2C_CSTA_ARBLST 0x00000010U +#define I2C_CSTA_ARBLST_M 0x00000010U +#define I2C_CSTA_ARBLST_S 4U +#define I2C_CSTA_ARBLST_SET 0x00000010U +#define I2C_CSTA_ARBLST_CLR 0x00000000U + +// Field: [3] DATACKN +// +// This field contains Data acknowledge status +// ENUMs: +// SET The transmitted data was not acknowledged +// CLR The transmitted data was acknowledged +#define I2C_CSTA_DATACKN 0x00000008U +#define I2C_CSTA_DATACKN_M 0x00000008U +#define I2C_CSTA_DATACKN_S 3U +#define I2C_CSTA_DATACKN_SET 0x00000008U +#define I2C_CSTA_DATACKN_CLR 0x00000000U + +// Field: [2] ADRACKN +// +// This field reflects the address acknowledge status +// ENUMs: +// SET The transmitted address was not acknowledged +// CLR The transmitted address was acknowledged +#define I2C_CSTA_ADRACKN 0x00000004U +#define I2C_CSTA_ADRACKN_M 0x00000004U +#define I2C_CSTA_ADRACKN_S 2U +#define I2C_CSTA_ADRACKN_SET 0x00000004U +#define I2C_CSTA_ADRACKN_CLR 0x00000000U + +// Field: [1] ERR +// +// This field reflects the error status +// ENUMs: +// SET An error occurred with the last operation +// CLR No error was detected on the last operation +#define I2C_CSTA_ERR 0x00000002U +#define I2C_CSTA_ERR_M 0x00000002U +#define I2C_CSTA_ERR_S 1U +#define I2C_CSTA_ERR_SET 0x00000002U +#define I2C_CSTA_ERR_CLR 0x00000000U + +// Field: [0] BUSY +// +// This field reflects the I2C busy status +// Note: The I2C controller requires four CLKSVT clock cycles to assert the +// BUSY status after I2C controller operation has been initiated through a +// write into CCTL register. +// Hence after programming CCTL register, application is requested to wait for +// four CLKSVT clock cycles before issuing a controller status inquiry through +// a read from CSTA register. Any prior inquiry would result in wrong status +// being reported. +// ENUMs: +// SET The controller is busy +// CLR The controller is idle +#define I2C_CSTA_BUSY 0x00000001U +#define I2C_CSTA_BUSY_M 0x00000001U +#define I2C_CSTA_BUSY_S 0U +#define I2C_CSTA_BUSY_SET 0x00000001U +#define I2C_CSTA_BUSY_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CCTL +// +//***************************************************************************** +// Field: [3] ACK +// +// This field is to enable the data acknowledge. +// Note:This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the target transmitter. +// ENUMs: +// EN The received data byte is acknowledged +// automatically by the controller +// DIS The received data byte is not acknowledged +// automatically by the controller +#define I2C_CCTL_ACK 0x00000008U +#define I2C_CCTL_ACK_M 0x00000008U +#define I2C_CCTL_ACK_S 3U +#define I2C_CCTL_ACK_EN 0x00000008U +#define I2C_CCTL_ACK_DIS 0x00000000U + +// Field: [2] STOP +// +// This field is to set stop condition . +// Note: This bit-field determines if the cycle stops at the end of the data +// cycle or continues on to a repeated start condition. +// ENUMs: +// EN The controller generates the stop condition +// DIS The controller does not generate the stop +// condition +#define I2C_CCTL_STOP 0x00000004U +#define I2C_CCTL_STOP_M 0x00000004U +#define I2C_CCTL_STOP_S 2U +#define I2C_CCTL_STOP_EN 0x00000004U +#define I2C_CCTL_STOP_DIS 0x00000000U + +// Field: [1] START +// +// This field is to set start or repeated start condition. +// ENUMs: +// EN The controller generates the start condition. +// DIS The controller does not generate the start +// condition +#define I2C_CCTL_START 0x00000002U +#define I2C_CCTL_START_M 0x00000002U +#define I2C_CCTL_START_S 1U +#define I2C_CCTL_START_EN 0x00000002U +#define I2C_CCTL_START_DIS 0x00000000U + +// Field: [0] RUN +// +// This field is to set the controller enable. +// ENUMs: +// EN The controller is enabled to transmit or receive +// data +// DIS The controller is disabled. +#define I2C_CCTL_RUN 0x00000001U +#define I2C_CCTL_RUN_M 0x00000001U +#define I2C_CCTL_RUN_S 0U +#define I2C_CCTL_RUN_EN 0x00000001U +#define I2C_CCTL_RUN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_CDR_DATA_W 8U +#define I2C_CDR_DATA_M 0x000000FFU +#define I2C_CDR_DATA_S 0U + +//***************************************************************************** +// +// Register: I2C_O_CTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set CTPR.TPR. If set to 1, a write to CTPR.TPR will be +// ignored. +#define I2C_CTPR_TPR_7 0x00000080U +#define I2C_CTPR_TPR_7_M 0x00000080U +#define I2C_CTPR_TPR_7_S 7U + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD, where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the CLKSVT period in ns. +#define I2C_CTPR_TPR_W 7U +#define I2C_CTPR_TPR_M 0x0000007FU +#define I2C_CTPR_TPR_S 0U + +//***************************************************************************** +// +// Register: I2C_O_CIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define I2C_CIMR_IM 0x00000001U +#define I2C_CIMR_IM_M 0x00000001U +#define I2C_CIMR_IM_S 0U +#define I2C_CIMR_IM_EN 0x00000001U +#define I2C_CIMR_IM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// This bit is cleared by writing 1 to CICR.IC bit. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define I2C_CRIS_RIS 0x00000001U +#define I2C_CRIS_RIS_M 0x00000001U +#define I2C_CRIS_RIS_S 0U +#define I2C_CRIS_RIS_SET 0x00000001U +#define I2C_CRIS_RIS_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// This bit is cleared by writing 1 to CICR.IC bit. +// ENUMs: +// SET Masked interrupt occured +// CLR Masked interrupt did not occur +#define I2C_CMIS_MIS 0x00000001U +#define I2C_CMIS_MIS_M 0x00000001U +#define I2C_CMIS_MIS_S 0U +#define I2C_CMIS_MIS_SET 0x00000001U +#define I2C_CMIS_MIS_CLR 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// ENUMs: +// EN Clear Interrupt +// Writing 1 to this bit +// clears CRIS.RIS and CMIS.MIS. +// DIS No effect +#define I2C_CICR_IC 0x00000001U +#define I2C_CICR_IC_M 0x00000001U +#define I2C_CICR_IC_S 0U +#define I2C_CICR_IC_EN 0x00000001U +#define I2C_CICR_IC_DIS 0x00000000U + +//***************************************************************************** +// +// Register: I2C_O_CCR +// +//***************************************************************************** +// Field: [5] TFE +// +// I2C target function enable +// +// ENUMs: +// EN Target mode enabled +// DIS Target mode disabled +#define I2C_CCR_TFE 0x00000020U +#define I2C_CCR_TFE_M 0x00000020U +#define I2C_CCR_TFE_S 5U +#define I2C_CCR_TFE_EN 0x00000020U +#define I2C_CCR_TFE_DIS 0x00000000U + +// Field: [4] CFE +// +// I2C controller function enable +// ENUMs: +// EN Controller mode enabled +// DIS Controller mode disabled +#define I2C_CCR_CFE 0x00000010U +#define I2C_CCR_CFE_M 0x00000010U +#define I2C_CCR_CFE_S 4U +#define I2C_CCR_CFE_EN 0x00000010U +#define I2C_CCR_CFE_DIS 0x00000000U + +// Field: [0] LPBK +// +// I2C loopback +// ENUMs: +// EN Test mode (Loopback operation) enabled +// DIS Test mode (Loopback operation) disabled +#define I2C_CCR_LPBK 0x00000001U +#define I2C_CCR_LPBK_M 0x00000001U +#define I2C_CCR_LPBK_S 0U +#define I2C_CCR_LPBK_EN 0x00000001U +#define I2C_CCR_LPBK_DIS 0x00000000U + + +#endif // __I2C__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ints.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ints.h new file mode 100644 index 00000000..814cf73d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ints.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Filename: hw_ints_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the System Timer + // in NVIC. +#define INT_CPUIRQ0 16 // IRQ0: Configurable source controlled by + // EVTSVT.CPUIRQ0SEL +#define INT_CPUIRQ1 17 // IRQ1: Configurable source controlled by + // EVTSVT.CPUIRQ1SEL +#define INT_CPUIRQ2 18 // IRQ2: Configurable source controlled by + // EVTSVT.CPUIRQ2SEL +#define INT_CPUIRQ3 19 // IRQ3: Configurable source controlled by + // EVTSVT.CPUIRQ3SEL +#define INT_CPUIRQ4 20 // IRQ4: Configurable source controlled by + // EVTSVT.CPUIRQ4SEL +#define INT_GPIO_COMB 21 // GPIO combined wake up interrupt, + // interrupt flags can be found here + // GPIO:MIS +#define INT_LRFD_IRQ0 22 // LRFD combined event, interrupt flags can + // be found here LRFDDBELL:MIS0 +#define INT_LRFD_IRQ1 23 // LRFD combined event, interrupt flags can + // be found here LRFDDBELL:MIS1 +#define INT_DMA_DONE_COMB 24 // DMA combined done interrupt, + // corresponding flags can be found here + // DMA:REQDONE +#define INT_AES_COMB 25 // AES accelerator combined interrupt + // request, interrupt flags can be found + // here AES:MIS +#define INT_SPI0_COMB 26 // SPI0 combined interrupt request, + // interrupt flags can be found here + // SPI0:MIS +#define INT_UART0_COMB 27 // UART0 combined interrupt, interrupt + // flags are found here UART0:MIS +#define INT_I2C0_IRQ 28 // Interrupt event from I2C0, interrupt + // flags can be found here I2C0:MIS +#define INT_LGPT0_COMB 29 // LGPT0 combined interrupt, interrupt + // flags are found here LGPT0:MIS +#define INT_LGPT1_COMB 30 // LGPT1 combined interrupt, interrupt + // flags are found here LGPT1:MIS +#define INT_ADC_COMB 31 // ADC combined interrupt request, + // interrupt flags can be found here + // ADC:MIS0 +#define INT_CPUIRQ16 32 // IRQ16: Configurable source controlled by + // EVTSVT.CPUIRQ16SEL +#define INT_LGPT2_COMB 33 // LGPT2 combined interrupt, interrupt + // flags are found here LGPT2:MIS +#define INT_LGPT3_COMB 34 // LGPT3 combined interrupt, interrupt + // flags are found here LGPT3:MIS + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define INT_PRI_LEVEL0 0x00000000 // Priority level 0 value +#define INT_PRI_LEVEL1 0x00000040 // Priority level 1 value +#define INT_PRI_LEVEL2 0x00000080 // Priority level 2 value +#define INT_PRI_LEVEL3 0x000000C0 // Priority level 3 value +#define INT_PRIORITY_MASK 0x000000C0 // Priority level mask +#define NUM_INTERRUPTS 35 // Number of exceptions +#define NUM_PRIORITY 4 // Number of exception priority levels +#define NUM_PRIORITY_BITS 2 // Number of exception priority bits + +#endif // __HW_INTS__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ioc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ioc.h new file mode 100644 index 00000000..6fe14750 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ioc.h @@ -0,0 +1,4278 @@ +/****************************************************************************** +* Filename: hw_ioc_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Module Description +#define IOC_O_DESC 0x00000000U + +// Extended Module Description +#define IOC_O_DESCEX 0x00000004U + +// Configuration +#define IOC_O_IOC0 0x00000100U + +// Configuration +#define IOC_O_IOC1 0x00000104U + +// Configuration +#define IOC_O_IOC2 0x00000108U + +// Configuration +#define IOC_O_IOC3 0x0000010CU + +// Configuration +#define IOC_O_IOC4 0x00000110U + +// Configuration +#define IOC_O_IOC5 0x00000114U + +// Configuration +#define IOC_O_IOC6 0x00000118U + +// Configuration +#define IOC_O_IOC7 0x0000011CU + +// Configuration +#define IOC_O_IOC8 0x00000120U + +// Configuration +#define IOC_O_IOC9 0x00000124U + +// Configuration +#define IOC_O_IOC10 0x00000128U + +// Configuration +#define IOC_O_IOC11 0x0000012CU + +// Configuration +#define IOC_O_IOC12 0x00000130U + +// Configuration +#define IOC_O_IOC13 0x00000134U + +// Configuration +#define IOC_O_IOC14 0x00000138U + +// Configuration +#define IOC_O_IOC15 0x0000013CU + +// Configuration +#define IOC_O_IOC16 0x00000140U + +// Configuration +#define IOC_O_IOC17 0x00000144U + +// Configuration +#define IOC_O_IOC18 0x00000148U + +// Configuration +#define IOC_O_IOC19 0x0000014CU + +// Configuration +#define IOC_O_IOC20 0x00000150U + +// Configuration +#define IOC_O_IOC21 0x00000154U + +// Configuration +#define IOC_O_IOC22 0x00000158U + +// Configuration +#define IOC_O_IOC23 0x0000015CU + +// Configuration +#define IOC_O_IOC24 0x00000160U + +// Configuration +#define IOC_O_IOC25 0x00000164U + +// DTB configuration +#define IOC_O_DTBCFG 0x00000C00U + +// DTB output enable +#define IOC_O_DTBOE 0x00000C04U + +// Event configuration +#define IOC_O_EVTCFG 0x00000C08U + +// Test +#define IOC_O_TEST 0x00000C0CU + +// DTB status +#define IOC_O_DTBSTAT 0x00000C10U + +//***************************************************************************** +// +// Register: IOC_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define IOC_DESC_MODID_W 16U +#define IOC_DESC_MODID_M 0xFFFF0000U +#define IOC_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define IOC_DESC_STDIPOFF_W 4U +#define IOC_DESC_STDIPOFF_M 0x0000F000U +#define IOC_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define IOC_DESC_INSTIDX_W 4U +#define IOC_DESC_INSTIDX_M 0x00000F00U +#define IOC_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define IOC_DESC_MAJREV_W 4U +#define IOC_DESC_MAJREV_M 0x000000F0U +#define IOC_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define IOC_DESC_MINREV_W 4U +#define IOC_DESC_MINREV_M 0x0000000FU +#define IOC_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: IOC_O_DESCEX +// +//***************************************************************************** +// Field: [15:12] NUMDTBIO +// +// Number of DTB IOs supported. Total DTB IOs supported is NUMDTBIO value +1. +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define IOC_DESCEX_NUMDTBIO_W 4U +#define IOC_DESCEX_NUMDTBIO_M 0x0000F000U +#define IOC_DESCEX_NUMDTBIO_S 12U +#define IOC_DESCEX_NUMDTBIO_MAXIMUM 0x0000F000U +#define IOC_DESCEX_NUMDTBIO_MINIMUM 0x00000000U + +// Field: [11:7] NUMHDIO +// +// Number of high drive IOs supported. Total high drive IOs supported is +// NUMHDIO value +1. +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define IOC_DESCEX_NUMHDIO_W 5U +#define IOC_DESCEX_NUMHDIO_M 0x00000F80U +#define IOC_DESCEX_NUMHDIO_S 7U +#define IOC_DESCEX_NUMHDIO_MAXIMUM 0x00000F80U +#define IOC_DESCEX_NUMHDIO_MINIMUM 0x00000000U + +// Field: [6] HDIO +// +// High drive IO supported by IOC. +// ENUMs: +// PRESENT HD IO supported by IOC +// ABSENT HD IO not supported by IOC +#define IOC_DESCEX_HDIO 0x00000040U +#define IOC_DESCEX_HDIO_M 0x00000040U +#define IOC_DESCEX_HDIO_S 6U +#define IOC_DESCEX_HDIO_PRESENT 0x00000040U +#define IOC_DESCEX_HDIO_ABSENT 0x00000000U + +// Field: [5:0] NUMDIO +// +// Number of DIOs supported. Total DIOs supported is NUMDIO value +1. +// ENUMs: +// MAXIMUM Highest possible value +// MINIMUM Smallest value +#define IOC_DESCEX_NUMDIO_W 6U +#define IOC_DESCEX_NUMDIO_M 0x0000003FU +#define IOC_DESCEX_NUMDIO_S 0U +#define IOC_DESCEX_NUMDIO_MAXIMUM 0x0000003FU +#define IOC_DESCEX_NUMDIO_MINIMUM 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC0 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC0_HYSTEN 0x40000000U +#define IOC_IOC0_HYSTEN_M 0x40000000U +#define IOC_IOC0_HYSTEN_S 30U +#define IOC_IOC0_HYSTEN_EN 0x40000000U +#define IOC_IOC0_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC0_INPEN 0x20000000U +#define IOC_IOC0_INPEN_M 0x20000000U +#define IOC_IOC0_INPEN_S 29U +#define IOC_IOC0_INPEN_EN 0x20000000U +#define IOC_IOC0_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC0_IOMODE_W 3U +#define IOC_IOC0_IOMODE_M 0x07000000U +#define IOC_IOC0_IOMODE_S 24U +#define IOC_IOC0_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC0_IOMODE_OPENS 0x04000000U +#define IOC_IOC0_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC0_IOMODE_OPEND 0x02000000U +#define IOC_IOC0_IOMODE_INVERTED 0x01000000U +#define IOC_IOC0_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC0_WUCFGSD_W 2U +#define IOC_IOC0_WUCFGSD_M 0x00300000U +#define IOC_IOC0_WUCFGSD_S 20U +#define IOC_IOC0_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC0_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC0_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC0_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC0_WUENSB 0x00040000U +#define IOC_IOC0_WUENSB_M 0x00040000U +#define IOC_IOC0_WUENSB_S 18U +#define IOC_IOC0_WUENSB_EN 0x00040000U +#define IOC_IOC0_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC0_EDGEDET_W 2U +#define IOC_IOC0_EDGEDET_M 0x00030000U +#define IOC_IOC0_EDGEDET_S 16U +#define IOC_IOC0_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC0_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC0_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC0_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC0_PULLCTL_W 2U +#define IOC_IOC0_PULLCTL_M 0x00006000U +#define IOC_IOC0_PULLCTL_S 13U +#define IOC_IOC0_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC0_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC0_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO0 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC0_PORTCFG_W 3U +#define IOC_IOC0_PORTCFG_M 0x00000007U +#define IOC_IOC0_PORTCFG_S 0U +#define IOC_IOC0_PORTCFG_DTB 0x00000007U +#define IOC_IOC0_PORTCFG_ANA 0x00000006U +#define IOC_IOC0_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC0_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC0_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC0_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC0_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC0_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC1 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC1_HYSTEN 0x40000000U +#define IOC_IOC1_HYSTEN_M 0x40000000U +#define IOC_IOC1_HYSTEN_S 30U +#define IOC_IOC1_HYSTEN_EN 0x40000000U +#define IOC_IOC1_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC1_INPEN 0x20000000U +#define IOC_IOC1_INPEN_M 0x20000000U +#define IOC_IOC1_INPEN_S 29U +#define IOC_IOC1_INPEN_EN 0x20000000U +#define IOC_IOC1_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC1_IOMODE_W 3U +#define IOC_IOC1_IOMODE_M 0x07000000U +#define IOC_IOC1_IOMODE_S 24U +#define IOC_IOC1_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC1_IOMODE_OPENS 0x04000000U +#define IOC_IOC1_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC1_IOMODE_OPEND 0x02000000U +#define IOC_IOC1_IOMODE_INVERTED 0x01000000U +#define IOC_IOC1_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC1_WUCFGSD_W 2U +#define IOC_IOC1_WUCFGSD_M 0x00300000U +#define IOC_IOC1_WUCFGSD_S 20U +#define IOC_IOC1_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC1_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC1_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC1_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC1_WUENSB 0x00040000U +#define IOC_IOC1_WUENSB_M 0x00040000U +#define IOC_IOC1_WUENSB_S 18U +#define IOC_IOC1_WUENSB_EN 0x00040000U +#define IOC_IOC1_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC1_EDGEDET_W 2U +#define IOC_IOC1_EDGEDET_M 0x00030000U +#define IOC_IOC1_EDGEDET_S 16U +#define IOC_IOC1_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC1_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC1_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC1_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC1_PULLCTL_W 2U +#define IOC_IOC1_PULLCTL_M 0x00006000U +#define IOC_IOC1_PULLCTL_S 13U +#define IOC_IOC1_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC1_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC1_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO1 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC1_PORTCFG_W 3U +#define IOC_IOC1_PORTCFG_M 0x00000007U +#define IOC_IOC1_PORTCFG_S 0U +#define IOC_IOC1_PORTCFG_DTB 0x00000007U +#define IOC_IOC1_PORTCFG_ANA 0x00000006U +#define IOC_IOC1_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC1_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC1_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC1_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC1_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC1_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC2 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC2_HYSTEN 0x40000000U +#define IOC_IOC2_HYSTEN_M 0x40000000U +#define IOC_IOC2_HYSTEN_S 30U +#define IOC_IOC2_HYSTEN_EN 0x40000000U +#define IOC_IOC2_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC2_INPEN 0x20000000U +#define IOC_IOC2_INPEN_M 0x20000000U +#define IOC_IOC2_INPEN_S 29U +#define IOC_IOC2_INPEN_EN 0x20000000U +#define IOC_IOC2_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC2_IOMODE_W 3U +#define IOC_IOC2_IOMODE_M 0x07000000U +#define IOC_IOC2_IOMODE_S 24U +#define IOC_IOC2_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC2_IOMODE_OPENS 0x04000000U +#define IOC_IOC2_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC2_IOMODE_OPEND 0x02000000U +#define IOC_IOC2_IOMODE_INVERTED 0x01000000U +#define IOC_IOC2_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC2_WUCFGSD_W 2U +#define IOC_IOC2_WUCFGSD_M 0x00300000U +#define IOC_IOC2_WUCFGSD_S 20U +#define IOC_IOC2_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC2_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC2_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC2_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC2_WUENSB 0x00040000U +#define IOC_IOC2_WUENSB_M 0x00040000U +#define IOC_IOC2_WUENSB_S 18U +#define IOC_IOC2_WUENSB_EN 0x00040000U +#define IOC_IOC2_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC2_EDGEDET_W 2U +#define IOC_IOC2_EDGEDET_M 0x00030000U +#define IOC_IOC2_EDGEDET_S 16U +#define IOC_IOC2_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC2_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC2_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC2_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC2_PULLCTL_W 2U +#define IOC_IOC2_PULLCTL_M 0x00006000U +#define IOC_IOC2_PULLCTL_S 13U +#define IOC_IOC2_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC2_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC2_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO2 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC2_PORTCFG_W 3U +#define IOC_IOC2_PORTCFG_M 0x00000007U +#define IOC_IOC2_PORTCFG_S 0U +#define IOC_IOC2_PORTCFG_DTB 0x00000007U +#define IOC_IOC2_PORTCFG_ANA 0x00000006U +#define IOC_IOC2_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC2_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC2_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC2_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC2_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC2_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC3 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC3_HYSTEN 0x40000000U +#define IOC_IOC3_HYSTEN_M 0x40000000U +#define IOC_IOC3_HYSTEN_S 30U +#define IOC_IOC3_HYSTEN_EN 0x40000000U +#define IOC_IOC3_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC3_INPEN 0x20000000U +#define IOC_IOC3_INPEN_M 0x20000000U +#define IOC_IOC3_INPEN_S 29U +#define IOC_IOC3_INPEN_EN 0x20000000U +#define IOC_IOC3_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC3_IOMODE_W 3U +#define IOC_IOC3_IOMODE_M 0x07000000U +#define IOC_IOC3_IOMODE_S 24U +#define IOC_IOC3_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC3_IOMODE_OPENS 0x04000000U +#define IOC_IOC3_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC3_IOMODE_OPEND 0x02000000U +#define IOC_IOC3_IOMODE_INVERTED 0x01000000U +#define IOC_IOC3_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC3_WUCFGSD_W 2U +#define IOC_IOC3_WUCFGSD_M 0x00300000U +#define IOC_IOC3_WUCFGSD_S 20U +#define IOC_IOC3_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC3_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC3_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC3_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC3_WUENSB 0x00040000U +#define IOC_IOC3_WUENSB_M 0x00040000U +#define IOC_IOC3_WUENSB_S 18U +#define IOC_IOC3_WUENSB_EN 0x00040000U +#define IOC_IOC3_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC3_EDGEDET_W 2U +#define IOC_IOC3_EDGEDET_M 0x00030000U +#define IOC_IOC3_EDGEDET_S 16U +#define IOC_IOC3_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC3_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC3_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC3_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC3_PULLCTL_W 2U +#define IOC_IOC3_PULLCTL_M 0x00006000U +#define IOC_IOC3_PULLCTL_S 13U +#define IOC_IOC3_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC3_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC3_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO3 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC3_PORTCFG_W 3U +#define IOC_IOC3_PORTCFG_M 0x00000007U +#define IOC_IOC3_PORTCFG_S 0U +#define IOC_IOC3_PORTCFG_DTB 0x00000007U +#define IOC_IOC3_PORTCFG_ANA 0x00000006U +#define IOC_IOC3_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC3_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC3_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC3_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC3_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC3_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC4 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC4_HYSTEN 0x40000000U +#define IOC_IOC4_HYSTEN_M 0x40000000U +#define IOC_IOC4_HYSTEN_S 30U +#define IOC_IOC4_HYSTEN_EN 0x40000000U +#define IOC_IOC4_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC4_INPEN 0x20000000U +#define IOC_IOC4_INPEN_M 0x20000000U +#define IOC_IOC4_INPEN_S 29U +#define IOC_IOC4_INPEN_EN 0x20000000U +#define IOC_IOC4_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC4_IOMODE_W 3U +#define IOC_IOC4_IOMODE_M 0x07000000U +#define IOC_IOC4_IOMODE_S 24U +#define IOC_IOC4_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC4_IOMODE_OPENS 0x04000000U +#define IOC_IOC4_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC4_IOMODE_OPEND 0x02000000U +#define IOC_IOC4_IOMODE_INVERTED 0x01000000U +#define IOC_IOC4_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC4_WUCFGSD_W 2U +#define IOC_IOC4_WUCFGSD_M 0x00300000U +#define IOC_IOC4_WUCFGSD_S 20U +#define IOC_IOC4_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC4_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC4_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC4_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC4_WUENSB 0x00040000U +#define IOC_IOC4_WUENSB_M 0x00040000U +#define IOC_IOC4_WUENSB_S 18U +#define IOC_IOC4_WUENSB_EN 0x00040000U +#define IOC_IOC4_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC4_EDGEDET_W 2U +#define IOC_IOC4_EDGEDET_M 0x00030000U +#define IOC_IOC4_EDGEDET_S 16U +#define IOC_IOC4_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC4_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC4_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC4_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC4_PULLCTL_W 2U +#define IOC_IOC4_PULLCTL_M 0x00006000U +#define IOC_IOC4_PULLCTL_S 13U +#define IOC_IOC4_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC4_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC4_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO4 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC4_PORTCFG_W 3U +#define IOC_IOC4_PORTCFG_M 0x00000007U +#define IOC_IOC4_PORTCFG_S 0U +#define IOC_IOC4_PORTCFG_DTB 0x00000007U +#define IOC_IOC4_PORTCFG_ANA 0x00000006U +#define IOC_IOC4_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC4_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC4_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC4_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC4_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC4_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC5 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC5_HYSTEN 0x40000000U +#define IOC_IOC5_HYSTEN_M 0x40000000U +#define IOC_IOC5_HYSTEN_S 30U +#define IOC_IOC5_HYSTEN_EN 0x40000000U +#define IOC_IOC5_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC5_INPEN 0x20000000U +#define IOC_IOC5_INPEN_M 0x20000000U +#define IOC_IOC5_INPEN_S 29U +#define IOC_IOC5_INPEN_EN 0x20000000U +#define IOC_IOC5_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC5_IOMODE_W 3U +#define IOC_IOC5_IOMODE_M 0x07000000U +#define IOC_IOC5_IOMODE_S 24U +#define IOC_IOC5_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC5_IOMODE_OPENS 0x04000000U +#define IOC_IOC5_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC5_IOMODE_OPEND 0x02000000U +#define IOC_IOC5_IOMODE_INVERTED 0x01000000U +#define IOC_IOC5_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC5_WUCFGSD_W 2U +#define IOC_IOC5_WUCFGSD_M 0x00300000U +#define IOC_IOC5_WUCFGSD_S 20U +#define IOC_IOC5_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC5_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC5_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC5_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC5_WUENSB 0x00040000U +#define IOC_IOC5_WUENSB_M 0x00040000U +#define IOC_IOC5_WUENSB_S 18U +#define IOC_IOC5_WUENSB_EN 0x00040000U +#define IOC_IOC5_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC5_EDGEDET_W 2U +#define IOC_IOC5_EDGEDET_M 0x00030000U +#define IOC_IOC5_EDGEDET_S 16U +#define IOC_IOC5_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC5_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC5_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC5_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC5_PULLCTL_W 2U +#define IOC_IOC5_PULLCTL_M 0x00006000U +#define IOC_IOC5_PULLCTL_S 13U +#define IOC_IOC5_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC5_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC5_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO5 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC5_PORTCFG_W 3U +#define IOC_IOC5_PORTCFG_M 0x00000007U +#define IOC_IOC5_PORTCFG_S 0U +#define IOC_IOC5_PORTCFG_DTB 0x00000007U +#define IOC_IOC5_PORTCFG_ANA 0x00000006U +#define IOC_IOC5_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC5_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC5_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC5_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC5_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC5_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC6 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC6_HYSTEN 0x40000000U +#define IOC_IOC6_HYSTEN_M 0x40000000U +#define IOC_IOC6_HYSTEN_S 30U +#define IOC_IOC6_HYSTEN_EN 0x40000000U +#define IOC_IOC6_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC6_INPEN 0x20000000U +#define IOC_IOC6_INPEN_M 0x20000000U +#define IOC_IOC6_INPEN_S 29U +#define IOC_IOC6_INPEN_EN 0x20000000U +#define IOC_IOC6_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC6_IOMODE_W 3U +#define IOC_IOC6_IOMODE_M 0x07000000U +#define IOC_IOC6_IOMODE_S 24U +#define IOC_IOC6_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC6_IOMODE_OPENS 0x04000000U +#define IOC_IOC6_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC6_IOMODE_OPEND 0x02000000U +#define IOC_IOC6_IOMODE_INVERTED 0x01000000U +#define IOC_IOC6_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC6_WUCFGSD_W 2U +#define IOC_IOC6_WUCFGSD_M 0x00300000U +#define IOC_IOC6_WUCFGSD_S 20U +#define IOC_IOC6_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC6_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC6_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC6_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC6_WUENSB 0x00040000U +#define IOC_IOC6_WUENSB_M 0x00040000U +#define IOC_IOC6_WUENSB_S 18U +#define IOC_IOC6_WUENSB_EN 0x00040000U +#define IOC_IOC6_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC6_EDGEDET_W 2U +#define IOC_IOC6_EDGEDET_M 0x00030000U +#define IOC_IOC6_EDGEDET_S 16U +#define IOC_IOC6_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC6_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC6_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC6_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC6_PULLCTL_W 2U +#define IOC_IOC6_PULLCTL_M 0x00006000U +#define IOC_IOC6_PULLCTL_S 13U +#define IOC_IOC6_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC6_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC6_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO6 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC6_PORTCFG_W 3U +#define IOC_IOC6_PORTCFG_M 0x00000007U +#define IOC_IOC6_PORTCFG_S 0U +#define IOC_IOC6_PORTCFG_DTB 0x00000007U +#define IOC_IOC6_PORTCFG_ANA 0x00000006U +#define IOC_IOC6_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC6_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC6_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC6_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC6_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC6_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC7 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC7_HYSTEN 0x40000000U +#define IOC_IOC7_HYSTEN_M 0x40000000U +#define IOC_IOC7_HYSTEN_S 30U +#define IOC_IOC7_HYSTEN_EN 0x40000000U +#define IOC_IOC7_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC7_INPEN 0x20000000U +#define IOC_IOC7_INPEN_M 0x20000000U +#define IOC_IOC7_INPEN_S 29U +#define IOC_IOC7_INPEN_EN 0x20000000U +#define IOC_IOC7_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC7_IOMODE_W 3U +#define IOC_IOC7_IOMODE_M 0x07000000U +#define IOC_IOC7_IOMODE_S 24U +#define IOC_IOC7_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC7_IOMODE_OPENS 0x04000000U +#define IOC_IOC7_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC7_IOMODE_OPEND 0x02000000U +#define IOC_IOC7_IOMODE_INVERTED 0x01000000U +#define IOC_IOC7_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC7_WUCFGSD_W 2U +#define IOC_IOC7_WUCFGSD_M 0x00300000U +#define IOC_IOC7_WUCFGSD_S 20U +#define IOC_IOC7_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC7_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC7_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC7_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC7_WUENSB 0x00040000U +#define IOC_IOC7_WUENSB_M 0x00040000U +#define IOC_IOC7_WUENSB_S 18U +#define IOC_IOC7_WUENSB_EN 0x00040000U +#define IOC_IOC7_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC7_EDGEDET_W 2U +#define IOC_IOC7_EDGEDET_M 0x00030000U +#define IOC_IOC7_EDGEDET_S 16U +#define IOC_IOC7_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC7_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC7_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC7_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC7_PULLCTL_W 2U +#define IOC_IOC7_PULLCTL_M 0x00006000U +#define IOC_IOC7_PULLCTL_S 13U +#define IOC_IOC7_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC7_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC7_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO7 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC7_PORTCFG_W 3U +#define IOC_IOC7_PORTCFG_M 0x00000007U +#define IOC_IOC7_PORTCFG_S 0U +#define IOC_IOC7_PORTCFG_DTB 0x00000007U +#define IOC_IOC7_PORTCFG_ANA 0x00000006U +#define IOC_IOC7_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC7_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC7_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC7_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC7_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC7_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC8 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC8_HYSTEN 0x40000000U +#define IOC_IOC8_HYSTEN_M 0x40000000U +#define IOC_IOC8_HYSTEN_S 30U +#define IOC_IOC8_HYSTEN_EN 0x40000000U +#define IOC_IOC8_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC8_INPEN 0x20000000U +#define IOC_IOC8_INPEN_M 0x20000000U +#define IOC_IOC8_INPEN_S 29U +#define IOC_IOC8_INPEN_EN 0x20000000U +#define IOC_IOC8_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC8_IOMODE_W 3U +#define IOC_IOC8_IOMODE_M 0x07000000U +#define IOC_IOC8_IOMODE_S 24U +#define IOC_IOC8_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC8_IOMODE_OPENS 0x04000000U +#define IOC_IOC8_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC8_IOMODE_OPEND 0x02000000U +#define IOC_IOC8_IOMODE_INVERTED 0x01000000U +#define IOC_IOC8_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC8_WUCFGSD_W 2U +#define IOC_IOC8_WUCFGSD_M 0x00300000U +#define IOC_IOC8_WUCFGSD_S 20U +#define IOC_IOC8_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC8_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC8_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC8_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC8_WUENSB 0x00040000U +#define IOC_IOC8_WUENSB_M 0x00040000U +#define IOC_IOC8_WUENSB_S 18U +#define IOC_IOC8_WUENSB_EN 0x00040000U +#define IOC_IOC8_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC8_EDGEDET_W 2U +#define IOC_IOC8_EDGEDET_M 0x00030000U +#define IOC_IOC8_EDGEDET_S 16U +#define IOC_IOC8_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC8_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC8_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC8_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC8_PULLCTL_W 2U +#define IOC_IOC8_PULLCTL_M 0x00006000U +#define IOC_IOC8_PULLCTL_S 13U +#define IOC_IOC8_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC8_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC8_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO8 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC8_PORTCFG_W 3U +#define IOC_IOC8_PORTCFG_M 0x00000007U +#define IOC_IOC8_PORTCFG_S 0U +#define IOC_IOC8_PORTCFG_DTB 0x00000007U +#define IOC_IOC8_PORTCFG_ANA 0x00000006U +#define IOC_IOC8_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC8_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC8_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC8_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC8_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC8_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC9 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC9_HYSTEN 0x40000000U +#define IOC_IOC9_HYSTEN_M 0x40000000U +#define IOC_IOC9_HYSTEN_S 30U +#define IOC_IOC9_HYSTEN_EN 0x40000000U +#define IOC_IOC9_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC9_INPEN 0x20000000U +#define IOC_IOC9_INPEN_M 0x20000000U +#define IOC_IOC9_INPEN_S 29U +#define IOC_IOC9_INPEN_EN 0x20000000U +#define IOC_IOC9_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC9_IOMODE_W 3U +#define IOC_IOC9_IOMODE_M 0x07000000U +#define IOC_IOC9_IOMODE_S 24U +#define IOC_IOC9_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC9_IOMODE_OPENS 0x04000000U +#define IOC_IOC9_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC9_IOMODE_OPEND 0x02000000U +#define IOC_IOC9_IOMODE_INVERTED 0x01000000U +#define IOC_IOC9_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC9_WUCFGSD_W 2U +#define IOC_IOC9_WUCFGSD_M 0x00300000U +#define IOC_IOC9_WUCFGSD_S 20U +#define IOC_IOC9_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC9_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC9_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC9_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC9_WUENSB 0x00040000U +#define IOC_IOC9_WUENSB_M 0x00040000U +#define IOC_IOC9_WUENSB_S 18U +#define IOC_IOC9_WUENSB_EN 0x00040000U +#define IOC_IOC9_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC9_EDGEDET_W 2U +#define IOC_IOC9_EDGEDET_M 0x00030000U +#define IOC_IOC9_EDGEDET_S 16U +#define IOC_IOC9_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC9_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC9_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC9_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC9_PULLCTL_W 2U +#define IOC_IOC9_PULLCTL_M 0x00006000U +#define IOC_IOC9_PULLCTL_S 13U +#define IOC_IOC9_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC9_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC9_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO9 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC9_PORTCFG_W 3U +#define IOC_IOC9_PORTCFG_M 0x00000007U +#define IOC_IOC9_PORTCFG_S 0U +#define IOC_IOC9_PORTCFG_DTB 0x00000007U +#define IOC_IOC9_PORTCFG_ANA 0x00000006U +#define IOC_IOC9_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC9_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC9_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC9_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC9_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC9_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC10 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC10_HYSTEN 0x40000000U +#define IOC_IOC10_HYSTEN_M 0x40000000U +#define IOC_IOC10_HYSTEN_S 30U +#define IOC_IOC10_HYSTEN_EN 0x40000000U +#define IOC_IOC10_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC10_INPEN 0x20000000U +#define IOC_IOC10_INPEN_M 0x20000000U +#define IOC_IOC10_INPEN_S 29U +#define IOC_IOC10_INPEN_EN 0x20000000U +#define IOC_IOC10_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC10_IOMODE_W 3U +#define IOC_IOC10_IOMODE_M 0x07000000U +#define IOC_IOC10_IOMODE_S 24U +#define IOC_IOC10_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC10_IOMODE_OPENS 0x04000000U +#define IOC_IOC10_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC10_IOMODE_OPEND 0x02000000U +#define IOC_IOC10_IOMODE_INVERTED 0x01000000U +#define IOC_IOC10_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC10_WUCFGSD_W 2U +#define IOC_IOC10_WUCFGSD_M 0x00300000U +#define IOC_IOC10_WUCFGSD_S 20U +#define IOC_IOC10_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC10_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC10_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC10_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC10_WUENSB 0x00040000U +#define IOC_IOC10_WUENSB_M 0x00040000U +#define IOC_IOC10_WUENSB_S 18U +#define IOC_IOC10_WUENSB_EN 0x00040000U +#define IOC_IOC10_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC10_EDGEDET_W 2U +#define IOC_IOC10_EDGEDET_M 0x00030000U +#define IOC_IOC10_EDGEDET_S 16U +#define IOC_IOC10_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC10_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC10_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC10_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC10_PULLCTL_W 2U +#define IOC_IOC10_PULLCTL_M 0x00006000U +#define IOC_IOC10_PULLCTL_S 13U +#define IOC_IOC10_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC10_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC10_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO10 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC10_PORTCFG_W 3U +#define IOC_IOC10_PORTCFG_M 0x00000007U +#define IOC_IOC10_PORTCFG_S 0U +#define IOC_IOC10_PORTCFG_DTB 0x00000007U +#define IOC_IOC10_PORTCFG_ANA 0x00000006U +#define IOC_IOC10_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC10_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC10_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC10_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC10_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC10_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC11 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC11_HYSTEN 0x40000000U +#define IOC_IOC11_HYSTEN_M 0x40000000U +#define IOC_IOC11_HYSTEN_S 30U +#define IOC_IOC11_HYSTEN_EN 0x40000000U +#define IOC_IOC11_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC11_INPEN 0x20000000U +#define IOC_IOC11_INPEN_M 0x20000000U +#define IOC_IOC11_INPEN_S 29U +#define IOC_IOC11_INPEN_EN 0x20000000U +#define IOC_IOC11_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC11_IOMODE_W 3U +#define IOC_IOC11_IOMODE_M 0x07000000U +#define IOC_IOC11_IOMODE_S 24U +#define IOC_IOC11_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC11_IOMODE_OPENS 0x04000000U +#define IOC_IOC11_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC11_IOMODE_OPEND 0x02000000U +#define IOC_IOC11_IOMODE_INVERTED 0x01000000U +#define IOC_IOC11_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC11_WUCFGSD_W 2U +#define IOC_IOC11_WUCFGSD_M 0x00300000U +#define IOC_IOC11_WUCFGSD_S 20U +#define IOC_IOC11_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC11_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC11_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC11_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC11_WUENSB 0x00040000U +#define IOC_IOC11_WUENSB_M 0x00040000U +#define IOC_IOC11_WUENSB_S 18U +#define IOC_IOC11_WUENSB_EN 0x00040000U +#define IOC_IOC11_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC11_EDGEDET_W 2U +#define IOC_IOC11_EDGEDET_M 0x00030000U +#define IOC_IOC11_EDGEDET_S 16U +#define IOC_IOC11_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC11_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC11_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC11_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC11_PULLCTL_W 2U +#define IOC_IOC11_PULLCTL_M 0x00006000U +#define IOC_IOC11_PULLCTL_S 13U +#define IOC_IOC11_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC11_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC11_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO11 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC11_PORTCFG_W 3U +#define IOC_IOC11_PORTCFG_M 0x00000007U +#define IOC_IOC11_PORTCFG_S 0U +#define IOC_IOC11_PORTCFG_DTB 0x00000007U +#define IOC_IOC11_PORTCFG_ANA 0x00000006U +#define IOC_IOC11_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC11_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC11_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC11_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC11_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC11_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC12 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC12_HYSTEN 0x40000000U +#define IOC_IOC12_HYSTEN_M 0x40000000U +#define IOC_IOC12_HYSTEN_S 30U +#define IOC_IOC12_HYSTEN_EN 0x40000000U +#define IOC_IOC12_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC12_INPEN 0x20000000U +#define IOC_IOC12_INPEN_M 0x20000000U +#define IOC_IOC12_INPEN_S 29U +#define IOC_IOC12_INPEN_EN 0x20000000U +#define IOC_IOC12_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC12_IOMODE_W 3U +#define IOC_IOC12_IOMODE_M 0x07000000U +#define IOC_IOC12_IOMODE_S 24U +#define IOC_IOC12_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC12_IOMODE_OPENS 0x04000000U +#define IOC_IOC12_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC12_IOMODE_OPEND 0x02000000U +#define IOC_IOC12_IOMODE_INVERTED 0x01000000U +#define IOC_IOC12_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC12_WUCFGSD_W 2U +#define IOC_IOC12_WUCFGSD_M 0x00300000U +#define IOC_IOC12_WUCFGSD_S 20U +#define IOC_IOC12_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC12_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC12_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC12_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC12_WUENSB 0x00040000U +#define IOC_IOC12_WUENSB_M 0x00040000U +#define IOC_IOC12_WUENSB_S 18U +#define IOC_IOC12_WUENSB_EN 0x00040000U +#define IOC_IOC12_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC12_EDGEDET_W 2U +#define IOC_IOC12_EDGEDET_M 0x00030000U +#define IOC_IOC12_EDGEDET_S 16U +#define IOC_IOC12_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC12_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC12_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC12_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC12_PULLCTL_W 2U +#define IOC_IOC12_PULLCTL_M 0x00006000U +#define IOC_IOC12_PULLCTL_S 13U +#define IOC_IOC12_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC12_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC12_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC12_SLEWRED 0x00001000U +#define IOC_IOC12_SLEWRED_M 0x00001000U +#define IOC_IOC12_SLEWRED_S 12U +#define IOC_IOC12_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC12_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC12_IOCURR_W 2U +#define IOC_IOC12_IOCURR_M 0x00000C00U +#define IOC_IOC12_IOCURR_S 10U +#define IOC_IOC12_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC12_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC12_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC12_IOSTR_W 2U +#define IOC_IOC12_IOSTR_M 0x00000300U +#define IOC_IOC12_IOSTR_S 8U +#define IOC_IOC12_IOSTR_MAX 0x00000300U +#define IOC_IOC12_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC12_IOSTR_MIN 0x00000100U +#define IOC_IOC12_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO12 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC12_PORTCFG_W 3U +#define IOC_IOC12_PORTCFG_M 0x00000007U +#define IOC_IOC12_PORTCFG_S 0U +#define IOC_IOC12_PORTCFG_DTB 0x00000007U +#define IOC_IOC12_PORTCFG_ANA 0x00000006U +#define IOC_IOC12_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC12_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC12_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC12_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC12_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC12_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC13 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC13_HYSTEN 0x40000000U +#define IOC_IOC13_HYSTEN_M 0x40000000U +#define IOC_IOC13_HYSTEN_S 30U +#define IOC_IOC13_HYSTEN_EN 0x40000000U +#define IOC_IOC13_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC13_INPEN 0x20000000U +#define IOC_IOC13_INPEN_M 0x20000000U +#define IOC_IOC13_INPEN_S 29U +#define IOC_IOC13_INPEN_EN 0x20000000U +#define IOC_IOC13_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC13_IOMODE_W 3U +#define IOC_IOC13_IOMODE_M 0x07000000U +#define IOC_IOC13_IOMODE_S 24U +#define IOC_IOC13_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC13_IOMODE_OPENS 0x04000000U +#define IOC_IOC13_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC13_IOMODE_OPEND 0x02000000U +#define IOC_IOC13_IOMODE_INVERTED 0x01000000U +#define IOC_IOC13_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC13_WUCFGSD_W 2U +#define IOC_IOC13_WUCFGSD_M 0x00300000U +#define IOC_IOC13_WUCFGSD_S 20U +#define IOC_IOC13_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC13_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC13_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC13_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC13_WUENSB 0x00040000U +#define IOC_IOC13_WUENSB_M 0x00040000U +#define IOC_IOC13_WUENSB_S 18U +#define IOC_IOC13_WUENSB_EN 0x00040000U +#define IOC_IOC13_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC13_EDGEDET_W 2U +#define IOC_IOC13_EDGEDET_M 0x00030000U +#define IOC_IOC13_EDGEDET_S 16U +#define IOC_IOC13_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC13_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC13_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC13_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC13_PULLCTL_W 2U +#define IOC_IOC13_PULLCTL_M 0x00006000U +#define IOC_IOC13_PULLCTL_S 13U +#define IOC_IOC13_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC13_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC13_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO13 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC13_PORTCFG_W 3U +#define IOC_IOC13_PORTCFG_M 0x00000007U +#define IOC_IOC13_PORTCFG_S 0U +#define IOC_IOC13_PORTCFG_DTB 0x00000007U +#define IOC_IOC13_PORTCFG_ANA 0x00000006U +#define IOC_IOC13_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC13_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC13_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC13_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC13_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC13_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC14 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC14_HYSTEN 0x40000000U +#define IOC_IOC14_HYSTEN_M 0x40000000U +#define IOC_IOC14_HYSTEN_S 30U +#define IOC_IOC14_HYSTEN_EN 0x40000000U +#define IOC_IOC14_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC14_INPEN 0x20000000U +#define IOC_IOC14_INPEN_M 0x20000000U +#define IOC_IOC14_INPEN_S 29U +#define IOC_IOC14_INPEN_EN 0x20000000U +#define IOC_IOC14_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC14_IOMODE_W 3U +#define IOC_IOC14_IOMODE_M 0x07000000U +#define IOC_IOC14_IOMODE_S 24U +#define IOC_IOC14_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC14_IOMODE_OPENS 0x04000000U +#define IOC_IOC14_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC14_IOMODE_OPEND 0x02000000U +#define IOC_IOC14_IOMODE_INVERTED 0x01000000U +#define IOC_IOC14_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC14_WUCFGSD_W 2U +#define IOC_IOC14_WUCFGSD_M 0x00300000U +#define IOC_IOC14_WUCFGSD_S 20U +#define IOC_IOC14_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC14_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC14_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC14_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC14_WUENSB 0x00040000U +#define IOC_IOC14_WUENSB_M 0x00040000U +#define IOC_IOC14_WUENSB_S 18U +#define IOC_IOC14_WUENSB_EN 0x00040000U +#define IOC_IOC14_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC14_EDGEDET_W 2U +#define IOC_IOC14_EDGEDET_M 0x00030000U +#define IOC_IOC14_EDGEDET_S 16U +#define IOC_IOC14_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC14_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC14_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC14_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC14_PULLCTL_W 2U +#define IOC_IOC14_PULLCTL_M 0x00006000U +#define IOC_IOC14_PULLCTL_S 13U +#define IOC_IOC14_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC14_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC14_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO14 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC14_PORTCFG_W 3U +#define IOC_IOC14_PORTCFG_M 0x00000007U +#define IOC_IOC14_PORTCFG_S 0U +#define IOC_IOC14_PORTCFG_DTB 0x00000007U +#define IOC_IOC14_PORTCFG_ANA 0x00000006U +#define IOC_IOC14_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC14_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC14_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC14_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC14_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC14_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC15 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC15_HYSTEN 0x40000000U +#define IOC_IOC15_HYSTEN_M 0x40000000U +#define IOC_IOC15_HYSTEN_S 30U +#define IOC_IOC15_HYSTEN_EN 0x40000000U +#define IOC_IOC15_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC15_INPEN 0x20000000U +#define IOC_IOC15_INPEN_M 0x20000000U +#define IOC_IOC15_INPEN_S 29U +#define IOC_IOC15_INPEN_EN 0x20000000U +#define IOC_IOC15_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC15_IOMODE_W 3U +#define IOC_IOC15_IOMODE_M 0x07000000U +#define IOC_IOC15_IOMODE_S 24U +#define IOC_IOC15_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC15_IOMODE_OPENS 0x04000000U +#define IOC_IOC15_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC15_IOMODE_OPEND 0x02000000U +#define IOC_IOC15_IOMODE_INVERTED 0x01000000U +#define IOC_IOC15_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC15_WUCFGSD_W 2U +#define IOC_IOC15_WUCFGSD_M 0x00300000U +#define IOC_IOC15_WUCFGSD_S 20U +#define IOC_IOC15_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC15_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC15_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC15_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC15_WUENSB 0x00040000U +#define IOC_IOC15_WUENSB_M 0x00040000U +#define IOC_IOC15_WUENSB_S 18U +#define IOC_IOC15_WUENSB_EN 0x00040000U +#define IOC_IOC15_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC15_EDGEDET_W 2U +#define IOC_IOC15_EDGEDET_M 0x00030000U +#define IOC_IOC15_EDGEDET_S 16U +#define IOC_IOC15_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC15_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC15_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC15_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC15_PULLCTL_W 2U +#define IOC_IOC15_PULLCTL_M 0x00006000U +#define IOC_IOC15_PULLCTL_S 13U +#define IOC_IOC15_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC15_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC15_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO15 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC15_PORTCFG_W 3U +#define IOC_IOC15_PORTCFG_M 0x00000007U +#define IOC_IOC15_PORTCFG_S 0U +#define IOC_IOC15_PORTCFG_DTB 0x00000007U +#define IOC_IOC15_PORTCFG_ANA 0x00000006U +#define IOC_IOC15_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC15_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC15_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC15_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC15_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC15_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC16 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC16_HYSTEN 0x40000000U +#define IOC_IOC16_HYSTEN_M 0x40000000U +#define IOC_IOC16_HYSTEN_S 30U +#define IOC_IOC16_HYSTEN_EN 0x40000000U +#define IOC_IOC16_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC16_INPEN 0x20000000U +#define IOC_IOC16_INPEN_M 0x20000000U +#define IOC_IOC16_INPEN_S 29U +#define IOC_IOC16_INPEN_EN 0x20000000U +#define IOC_IOC16_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC16_IOMODE_W 3U +#define IOC_IOC16_IOMODE_M 0x07000000U +#define IOC_IOC16_IOMODE_S 24U +#define IOC_IOC16_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC16_IOMODE_OPENS 0x04000000U +#define IOC_IOC16_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC16_IOMODE_OPEND 0x02000000U +#define IOC_IOC16_IOMODE_INVERTED 0x01000000U +#define IOC_IOC16_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC16_WUCFGSD_W 2U +#define IOC_IOC16_WUCFGSD_M 0x00300000U +#define IOC_IOC16_WUCFGSD_S 20U +#define IOC_IOC16_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC16_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC16_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC16_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC16_WUENSB 0x00040000U +#define IOC_IOC16_WUENSB_M 0x00040000U +#define IOC_IOC16_WUENSB_S 18U +#define IOC_IOC16_WUENSB_EN 0x00040000U +#define IOC_IOC16_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC16_EDGEDET_W 2U +#define IOC_IOC16_EDGEDET_M 0x00030000U +#define IOC_IOC16_EDGEDET_S 16U +#define IOC_IOC16_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC16_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC16_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC16_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC16_PULLCTL_W 2U +#define IOC_IOC16_PULLCTL_M 0x00006000U +#define IOC_IOC16_PULLCTL_S 13U +#define IOC_IOC16_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC16_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC16_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC16_SLEWRED 0x00001000U +#define IOC_IOC16_SLEWRED_M 0x00001000U +#define IOC_IOC16_SLEWRED_S 12U +#define IOC_IOC16_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC16_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC16_IOCURR_W 2U +#define IOC_IOC16_IOCURR_M 0x00000C00U +#define IOC_IOC16_IOCURR_S 10U +#define IOC_IOC16_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC16_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC16_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC16_IOSTR_W 2U +#define IOC_IOC16_IOSTR_M 0x00000300U +#define IOC_IOC16_IOSTR_S 8U +#define IOC_IOC16_IOSTR_MAX 0x00000300U +#define IOC_IOC16_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC16_IOSTR_MIN 0x00000100U +#define IOC_IOC16_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO16 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC16_PORTCFG_W 3U +#define IOC_IOC16_PORTCFG_M 0x00000007U +#define IOC_IOC16_PORTCFG_S 0U +#define IOC_IOC16_PORTCFG_DTB 0x00000007U +#define IOC_IOC16_PORTCFG_ANA 0x00000006U +#define IOC_IOC16_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC16_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC16_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC16_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC16_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC16_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC17 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC17_HYSTEN 0x40000000U +#define IOC_IOC17_HYSTEN_M 0x40000000U +#define IOC_IOC17_HYSTEN_S 30U +#define IOC_IOC17_HYSTEN_EN 0x40000000U +#define IOC_IOC17_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC17_INPEN 0x20000000U +#define IOC_IOC17_INPEN_M 0x20000000U +#define IOC_IOC17_INPEN_S 29U +#define IOC_IOC17_INPEN_EN 0x20000000U +#define IOC_IOC17_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC17_IOMODE_W 3U +#define IOC_IOC17_IOMODE_M 0x07000000U +#define IOC_IOC17_IOMODE_S 24U +#define IOC_IOC17_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC17_IOMODE_OPENS 0x04000000U +#define IOC_IOC17_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC17_IOMODE_OPEND 0x02000000U +#define IOC_IOC17_IOMODE_INVERTED 0x01000000U +#define IOC_IOC17_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC17_WUCFGSD_W 2U +#define IOC_IOC17_WUCFGSD_M 0x00300000U +#define IOC_IOC17_WUCFGSD_S 20U +#define IOC_IOC17_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC17_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC17_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC17_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC17_WUENSB 0x00040000U +#define IOC_IOC17_WUENSB_M 0x00040000U +#define IOC_IOC17_WUENSB_S 18U +#define IOC_IOC17_WUENSB_EN 0x00040000U +#define IOC_IOC17_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC17_EDGEDET_W 2U +#define IOC_IOC17_EDGEDET_M 0x00030000U +#define IOC_IOC17_EDGEDET_S 16U +#define IOC_IOC17_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC17_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC17_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC17_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC17_PULLCTL_W 2U +#define IOC_IOC17_PULLCTL_M 0x00006000U +#define IOC_IOC17_PULLCTL_S 13U +#define IOC_IOC17_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC17_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC17_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC17_SLEWRED 0x00001000U +#define IOC_IOC17_SLEWRED_M 0x00001000U +#define IOC_IOC17_SLEWRED_S 12U +#define IOC_IOC17_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC17_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC17_IOCURR_W 2U +#define IOC_IOC17_IOCURR_M 0x00000C00U +#define IOC_IOC17_IOCURR_S 10U +#define IOC_IOC17_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC17_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC17_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC17_IOSTR_W 2U +#define IOC_IOC17_IOSTR_M 0x00000300U +#define IOC_IOC17_IOSTR_S 8U +#define IOC_IOC17_IOSTR_MAX 0x00000300U +#define IOC_IOC17_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC17_IOSTR_MIN 0x00000100U +#define IOC_IOC17_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO17 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC17_PORTCFG_W 3U +#define IOC_IOC17_PORTCFG_M 0x00000007U +#define IOC_IOC17_PORTCFG_S 0U +#define IOC_IOC17_PORTCFG_DTB 0x00000007U +#define IOC_IOC17_PORTCFG_ANA 0x00000006U +#define IOC_IOC17_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC17_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC17_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC17_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC17_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC17_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC18 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC18_HYSTEN 0x40000000U +#define IOC_IOC18_HYSTEN_M 0x40000000U +#define IOC_IOC18_HYSTEN_S 30U +#define IOC_IOC18_HYSTEN_EN 0x40000000U +#define IOC_IOC18_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC18_INPEN 0x20000000U +#define IOC_IOC18_INPEN_M 0x20000000U +#define IOC_IOC18_INPEN_S 29U +#define IOC_IOC18_INPEN_EN 0x20000000U +#define IOC_IOC18_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC18_IOMODE_W 3U +#define IOC_IOC18_IOMODE_M 0x07000000U +#define IOC_IOC18_IOMODE_S 24U +#define IOC_IOC18_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC18_IOMODE_OPENS 0x04000000U +#define IOC_IOC18_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC18_IOMODE_OPEND 0x02000000U +#define IOC_IOC18_IOMODE_INVERTED 0x01000000U +#define IOC_IOC18_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC18_WUCFGSD_W 2U +#define IOC_IOC18_WUCFGSD_M 0x00300000U +#define IOC_IOC18_WUCFGSD_S 20U +#define IOC_IOC18_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC18_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC18_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC18_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC18_WUENSB 0x00040000U +#define IOC_IOC18_WUENSB_M 0x00040000U +#define IOC_IOC18_WUENSB_S 18U +#define IOC_IOC18_WUENSB_EN 0x00040000U +#define IOC_IOC18_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC18_EDGEDET_W 2U +#define IOC_IOC18_EDGEDET_M 0x00030000U +#define IOC_IOC18_EDGEDET_S 16U +#define IOC_IOC18_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC18_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC18_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC18_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC18_PULLCTL_W 2U +#define IOC_IOC18_PULLCTL_M 0x00006000U +#define IOC_IOC18_PULLCTL_S 13U +#define IOC_IOC18_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC18_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC18_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC18_SLEWRED 0x00001000U +#define IOC_IOC18_SLEWRED_M 0x00001000U +#define IOC_IOC18_SLEWRED_S 12U +#define IOC_IOC18_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC18_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC18_IOCURR_W 2U +#define IOC_IOC18_IOCURR_M 0x00000C00U +#define IOC_IOC18_IOCURR_S 10U +#define IOC_IOC18_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC18_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC18_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC18_IOSTR_W 2U +#define IOC_IOC18_IOSTR_M 0x00000300U +#define IOC_IOC18_IOSTR_S 8U +#define IOC_IOC18_IOSTR_MAX 0x00000300U +#define IOC_IOC18_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC18_IOSTR_MIN 0x00000100U +#define IOC_IOC18_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO18 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC18_PORTCFG_W 3U +#define IOC_IOC18_PORTCFG_M 0x00000007U +#define IOC_IOC18_PORTCFG_S 0U +#define IOC_IOC18_PORTCFG_DTB 0x00000007U +#define IOC_IOC18_PORTCFG_ANA 0x00000006U +#define IOC_IOC18_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC18_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC18_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC18_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC18_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC18_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC19 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC19_HYSTEN 0x40000000U +#define IOC_IOC19_HYSTEN_M 0x40000000U +#define IOC_IOC19_HYSTEN_S 30U +#define IOC_IOC19_HYSTEN_EN 0x40000000U +#define IOC_IOC19_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC19_INPEN 0x20000000U +#define IOC_IOC19_INPEN_M 0x20000000U +#define IOC_IOC19_INPEN_S 29U +#define IOC_IOC19_INPEN_EN 0x20000000U +#define IOC_IOC19_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC19_IOMODE_W 3U +#define IOC_IOC19_IOMODE_M 0x07000000U +#define IOC_IOC19_IOMODE_S 24U +#define IOC_IOC19_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC19_IOMODE_OPENS 0x04000000U +#define IOC_IOC19_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC19_IOMODE_OPEND 0x02000000U +#define IOC_IOC19_IOMODE_INVERTED 0x01000000U +#define IOC_IOC19_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC19_WUCFGSD_W 2U +#define IOC_IOC19_WUCFGSD_M 0x00300000U +#define IOC_IOC19_WUCFGSD_S 20U +#define IOC_IOC19_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC19_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC19_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC19_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC19_WUENSB 0x00040000U +#define IOC_IOC19_WUENSB_M 0x00040000U +#define IOC_IOC19_WUENSB_S 18U +#define IOC_IOC19_WUENSB_EN 0x00040000U +#define IOC_IOC19_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC19_EDGEDET_W 2U +#define IOC_IOC19_EDGEDET_M 0x00030000U +#define IOC_IOC19_EDGEDET_S 16U +#define IOC_IOC19_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC19_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC19_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC19_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC19_PULLCTL_W 2U +#define IOC_IOC19_PULLCTL_M 0x00006000U +#define IOC_IOC19_PULLCTL_S 13U +#define IOC_IOC19_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC19_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC19_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC19_SLEWRED 0x00001000U +#define IOC_IOC19_SLEWRED_M 0x00001000U +#define IOC_IOC19_SLEWRED_S 12U +#define IOC_IOC19_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC19_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC19_IOCURR_W 2U +#define IOC_IOC19_IOCURR_M 0x00000C00U +#define IOC_IOC19_IOCURR_S 10U +#define IOC_IOC19_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC19_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC19_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC19_IOSTR_W 2U +#define IOC_IOC19_IOSTR_M 0x00000300U +#define IOC_IOC19_IOSTR_S 8U +#define IOC_IOC19_IOSTR_MAX 0x00000300U +#define IOC_IOC19_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC19_IOSTR_MIN 0x00000100U +#define IOC_IOC19_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO19 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC19_PORTCFG_W 3U +#define IOC_IOC19_PORTCFG_M 0x00000007U +#define IOC_IOC19_PORTCFG_S 0U +#define IOC_IOC19_PORTCFG_DTB 0x00000007U +#define IOC_IOC19_PORTCFG_ANA 0x00000006U +#define IOC_IOC19_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC19_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC19_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC19_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC19_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC19_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC20 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC20_HYSTEN 0x40000000U +#define IOC_IOC20_HYSTEN_M 0x40000000U +#define IOC_IOC20_HYSTEN_S 30U +#define IOC_IOC20_HYSTEN_EN 0x40000000U +#define IOC_IOC20_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC20_INPEN 0x20000000U +#define IOC_IOC20_INPEN_M 0x20000000U +#define IOC_IOC20_INPEN_S 29U +#define IOC_IOC20_INPEN_EN 0x20000000U +#define IOC_IOC20_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC20_IOMODE_W 3U +#define IOC_IOC20_IOMODE_M 0x07000000U +#define IOC_IOC20_IOMODE_S 24U +#define IOC_IOC20_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC20_IOMODE_OPENS 0x04000000U +#define IOC_IOC20_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC20_IOMODE_OPEND 0x02000000U +#define IOC_IOC20_IOMODE_INVERTED 0x01000000U +#define IOC_IOC20_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC20_WUCFGSD_W 2U +#define IOC_IOC20_WUCFGSD_M 0x00300000U +#define IOC_IOC20_WUCFGSD_S 20U +#define IOC_IOC20_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC20_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC20_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC20_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC20_WUENSB 0x00040000U +#define IOC_IOC20_WUENSB_M 0x00040000U +#define IOC_IOC20_WUENSB_S 18U +#define IOC_IOC20_WUENSB_EN 0x00040000U +#define IOC_IOC20_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC20_EDGEDET_W 2U +#define IOC_IOC20_EDGEDET_M 0x00030000U +#define IOC_IOC20_EDGEDET_S 16U +#define IOC_IOC20_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC20_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC20_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC20_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC20_PULLCTL_W 2U +#define IOC_IOC20_PULLCTL_M 0x00006000U +#define IOC_IOC20_PULLCTL_S 13U +#define IOC_IOC20_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC20_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC20_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO20 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC20_PORTCFG_W 3U +#define IOC_IOC20_PORTCFG_M 0x00000007U +#define IOC_IOC20_PORTCFG_S 0U +#define IOC_IOC20_PORTCFG_DTB 0x00000007U +#define IOC_IOC20_PORTCFG_ANA 0x00000006U +#define IOC_IOC20_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC20_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC20_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC20_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC20_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC20_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC21 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC21_HYSTEN 0x40000000U +#define IOC_IOC21_HYSTEN_M 0x40000000U +#define IOC_IOC21_HYSTEN_S 30U +#define IOC_IOC21_HYSTEN_EN 0x40000000U +#define IOC_IOC21_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC21_INPEN 0x20000000U +#define IOC_IOC21_INPEN_M 0x20000000U +#define IOC_IOC21_INPEN_S 29U +#define IOC_IOC21_INPEN_EN 0x20000000U +#define IOC_IOC21_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC21_IOMODE_W 3U +#define IOC_IOC21_IOMODE_M 0x07000000U +#define IOC_IOC21_IOMODE_S 24U +#define IOC_IOC21_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC21_IOMODE_OPENS 0x04000000U +#define IOC_IOC21_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC21_IOMODE_OPEND 0x02000000U +#define IOC_IOC21_IOMODE_INVERTED 0x01000000U +#define IOC_IOC21_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC21_WUCFGSD_W 2U +#define IOC_IOC21_WUCFGSD_M 0x00300000U +#define IOC_IOC21_WUCFGSD_S 20U +#define IOC_IOC21_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC21_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC21_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC21_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC21_WUENSB 0x00040000U +#define IOC_IOC21_WUENSB_M 0x00040000U +#define IOC_IOC21_WUENSB_S 18U +#define IOC_IOC21_WUENSB_EN 0x00040000U +#define IOC_IOC21_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC21_EDGEDET_W 2U +#define IOC_IOC21_EDGEDET_M 0x00030000U +#define IOC_IOC21_EDGEDET_S 16U +#define IOC_IOC21_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC21_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC21_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC21_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC21_PULLCTL_W 2U +#define IOC_IOC21_PULLCTL_M 0x00006000U +#define IOC_IOC21_PULLCTL_S 13U +#define IOC_IOC21_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC21_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC21_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO21 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC21_PORTCFG_W 3U +#define IOC_IOC21_PORTCFG_M 0x00000007U +#define IOC_IOC21_PORTCFG_S 0U +#define IOC_IOC21_PORTCFG_DTB 0x00000007U +#define IOC_IOC21_PORTCFG_ANA 0x00000006U +#define IOC_IOC21_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC21_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC21_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC21_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC21_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC21_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC22 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC22_HYSTEN 0x40000000U +#define IOC_IOC22_HYSTEN_M 0x40000000U +#define IOC_IOC22_HYSTEN_S 30U +#define IOC_IOC22_HYSTEN_EN 0x40000000U +#define IOC_IOC22_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC22_INPEN 0x20000000U +#define IOC_IOC22_INPEN_M 0x20000000U +#define IOC_IOC22_INPEN_S 29U +#define IOC_IOC22_INPEN_EN 0x20000000U +#define IOC_IOC22_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC22_IOMODE_W 3U +#define IOC_IOC22_IOMODE_M 0x07000000U +#define IOC_IOC22_IOMODE_S 24U +#define IOC_IOC22_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC22_IOMODE_OPENS 0x04000000U +#define IOC_IOC22_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC22_IOMODE_OPEND 0x02000000U +#define IOC_IOC22_IOMODE_INVERTED 0x01000000U +#define IOC_IOC22_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC22_WUCFGSD_W 2U +#define IOC_IOC22_WUCFGSD_M 0x00300000U +#define IOC_IOC22_WUCFGSD_S 20U +#define IOC_IOC22_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC22_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC22_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC22_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC22_WUENSB 0x00040000U +#define IOC_IOC22_WUENSB_M 0x00040000U +#define IOC_IOC22_WUENSB_S 18U +#define IOC_IOC22_WUENSB_EN 0x00040000U +#define IOC_IOC22_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC22_EDGEDET_W 2U +#define IOC_IOC22_EDGEDET_M 0x00030000U +#define IOC_IOC22_EDGEDET_S 16U +#define IOC_IOC22_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC22_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC22_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC22_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC22_PULLCTL_W 2U +#define IOC_IOC22_PULLCTL_M 0x00006000U +#define IOC_IOC22_PULLCTL_S 13U +#define IOC_IOC22_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC22_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC22_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO22 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC22_PORTCFG_W 3U +#define IOC_IOC22_PORTCFG_M 0x00000007U +#define IOC_IOC22_PORTCFG_S 0U +#define IOC_IOC22_PORTCFG_DTB 0x00000007U +#define IOC_IOC22_PORTCFG_ANA 0x00000006U +#define IOC_IOC22_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC22_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC22_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC22_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC22_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC22_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC23 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC23_HYSTEN 0x40000000U +#define IOC_IOC23_HYSTEN_M 0x40000000U +#define IOC_IOC23_HYSTEN_S 30U +#define IOC_IOC23_HYSTEN_EN 0x40000000U +#define IOC_IOC23_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC23_INPEN 0x20000000U +#define IOC_IOC23_INPEN_M 0x20000000U +#define IOC_IOC23_INPEN_S 29U +#define IOC_IOC23_INPEN_EN 0x20000000U +#define IOC_IOC23_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC23_IOMODE_W 3U +#define IOC_IOC23_IOMODE_M 0x07000000U +#define IOC_IOC23_IOMODE_S 24U +#define IOC_IOC23_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC23_IOMODE_OPENS 0x04000000U +#define IOC_IOC23_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC23_IOMODE_OPEND 0x02000000U +#define IOC_IOC23_IOMODE_INVERTED 0x01000000U +#define IOC_IOC23_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC23_WUCFGSD_W 2U +#define IOC_IOC23_WUCFGSD_M 0x00300000U +#define IOC_IOC23_WUCFGSD_S 20U +#define IOC_IOC23_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC23_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC23_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC23_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC23_WUENSB 0x00040000U +#define IOC_IOC23_WUENSB_M 0x00040000U +#define IOC_IOC23_WUENSB_S 18U +#define IOC_IOC23_WUENSB_EN 0x00040000U +#define IOC_IOC23_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC23_EDGEDET_W 2U +#define IOC_IOC23_EDGEDET_M 0x00030000U +#define IOC_IOC23_EDGEDET_S 16U +#define IOC_IOC23_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC23_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC23_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC23_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC23_PULLCTL_W 2U +#define IOC_IOC23_PULLCTL_M 0x00006000U +#define IOC_IOC23_PULLCTL_S 13U +#define IOC_IOC23_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC23_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC23_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO23 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC23_PORTCFG_W 3U +#define IOC_IOC23_PORTCFG_M 0x00000007U +#define IOC_IOC23_PORTCFG_S 0U +#define IOC_IOC23_PORTCFG_DTB 0x00000007U +#define IOC_IOC23_PORTCFG_ANA 0x00000006U +#define IOC_IOC23_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC23_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC23_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC23_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC23_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC23_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC24 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC24_HYSTEN 0x40000000U +#define IOC_IOC24_HYSTEN_M 0x40000000U +#define IOC_IOC24_HYSTEN_S 30U +#define IOC_IOC24_HYSTEN_EN 0x40000000U +#define IOC_IOC24_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC24_INPEN 0x20000000U +#define IOC_IOC24_INPEN_M 0x20000000U +#define IOC_IOC24_INPEN_S 29U +#define IOC_IOC24_INPEN_EN 0x20000000U +#define IOC_IOC24_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC24_IOMODE_W 3U +#define IOC_IOC24_IOMODE_M 0x07000000U +#define IOC_IOC24_IOMODE_S 24U +#define IOC_IOC24_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC24_IOMODE_OPENS 0x04000000U +#define IOC_IOC24_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC24_IOMODE_OPEND 0x02000000U +#define IOC_IOC24_IOMODE_INVERTED 0x01000000U +#define IOC_IOC24_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC24_WUCFGSD_W 2U +#define IOC_IOC24_WUCFGSD_M 0x00300000U +#define IOC_IOC24_WUCFGSD_S 20U +#define IOC_IOC24_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC24_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC24_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC24_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC24_WUENSB 0x00040000U +#define IOC_IOC24_WUENSB_M 0x00040000U +#define IOC_IOC24_WUENSB_S 18U +#define IOC_IOC24_WUENSB_EN 0x00040000U +#define IOC_IOC24_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC24_EDGEDET_W 2U +#define IOC_IOC24_EDGEDET_M 0x00030000U +#define IOC_IOC24_EDGEDET_S 16U +#define IOC_IOC24_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC24_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC24_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC24_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC24_PULLCTL_W 2U +#define IOC_IOC24_PULLCTL_M 0x00006000U +#define IOC_IOC24_PULLCTL_S 13U +#define IOC_IOC24_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC24_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC24_PULLCTL_PULL_DIS 0x00000000U + +// Field: [12] SLEWRED +// +// Slew rate configuration +// ENUMs: +// REDUCED Reduced slew rate +// NORMAL Normal slew rate +#define IOC_IOC24_SLEWRED 0x00001000U +#define IOC_IOC24_SLEWRED_M 0x00001000U +#define IOC_IOC24_SLEWRED_S 12U +#define IOC_IOC24_SLEWRED_REDUCED 0x00001000U +#define IOC_IOC24_SLEWRED_NORMAL 0x00000000U + +// Field: [11:10] IOCURR +// +// Output current configuration. Writing value 0x3 defaults to 2mA current +// setting. +// ENUMs: +// CUR_8MA +// CUR_4MA +// CUR_2MA +#define IOC_IOC24_IOCURR_W 2U +#define IOC_IOC24_IOCURR_M 0x00000C00U +#define IOC_IOC24_IOCURR_S 10U +#define IOC_IOC24_IOCURR_CUR_8MA 0x00000800U +#define IOC_IOC24_IOCURR_CUR_4MA 0x00000400U +#define IOC_IOC24_IOCURR_CUR_2MA 0x00000000U + +// Field: [9:8] IOSTR +// +// Drive strength configuration +// ENUMs: +// MAX Maximum drive strength +// MEDIUM Medium drive strength +// MIN Minimum drive stregnth +// AUTO Automatic drive strength adjustment +#define IOC_IOC24_IOSTR_W 2U +#define IOC_IOC24_IOSTR_M 0x00000300U +#define IOC_IOC24_IOSTR_S 8U +#define IOC_IOC24_IOSTR_MAX 0x00000300U +#define IOC_IOC24_IOSTR_MEDIUM 0x00000200U +#define IOC_IOC24_IOSTR_MIN 0x00000100U +#define IOC_IOC24_IOSTR_AUTO 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO24 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC24_PORTCFG_W 3U +#define IOC_IOC24_PORTCFG_M 0x00000007U +#define IOC_IOC24_PORTCFG_S 0U +#define IOC_IOC24_PORTCFG_DTB 0x00000007U +#define IOC_IOC24_PORTCFG_ANA 0x00000006U +#define IOC_IOC24_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC24_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC24_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC24_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC24_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC24_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_IOC25 +// +//***************************************************************************** +// Field: [30] HYSTEN +// +// This field controls input hysteresis +// ENUMs: +// EN Input hysteresis enabled +// DIS Input hysteresis disabled +#define IOC_IOC25_HYSTEN 0x40000000U +#define IOC_IOC25_HYSTEN_M 0x40000000U +#define IOC_IOC25_HYSTEN_S 30U +#define IOC_IOC25_HYSTEN_EN 0x40000000U +#define IOC_IOC25_HYSTEN_DIS 0x00000000U + +// Field: [29] INPEN +// +// This field controls the input capability of DIO +// ENUMs: +// EN Input enabled +// DIS Input disabled +#define IOC_IOC25_INPEN 0x20000000U +#define IOC_IOC25_INPEN_M 0x20000000U +#define IOC_IOC25_INPEN_S 29U +#define IOC_IOC25_INPEN_EN 0x20000000U +#define IOC_IOC25_INPEN_DIS 0x00000000U + +// Field: [26:24] IOMODE +// +// IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO +// behavior. +// ENUMs: +// OPENS_INV Open Source, inverted IO +// OPENS Open Source, normal IO +// OPEND_INV Open Drain, inverted IO +// OPEND Open Drain, normal IO +// INVERTED Inverted IO +// NORMAL Normal IO +#define IOC_IOC25_IOMODE_W 3U +#define IOC_IOC25_IOMODE_M 0x07000000U +#define IOC_IOC25_IOMODE_S 24U +#define IOC_IOC25_IOMODE_OPENS_INV 0x05000000U +#define IOC_IOC25_IOMODE_OPENS 0x04000000U +#define IOC_IOC25_IOMODE_OPEND_INV 0x03000000U +#define IOC_IOC25_IOMODE_OPEND 0x02000000U +#define IOC_IOC25_IOMODE_INVERTED 0x01000000U +#define IOC_IOC25_IOMODE_NORMAL 0x00000000U + +// Field: [21:20] WUCFGSD +// +// Wakeup configuration from shutdown +// ENUMs: +// WAKE_HIGH Wakeup triggered when pad level is high +// WAKE_LOW Wakeup triggered when pad level is low +// DIS_1 Wakeup disabled +// DIS_0 Wakeup disabled +#define IOC_IOC25_WUCFGSD_W 2U +#define IOC_IOC25_WUCFGSD_M 0x00300000U +#define IOC_IOC25_WUCFGSD_S 20U +#define IOC_IOC25_WUCFGSD_WAKE_HIGH 0x00300000U +#define IOC_IOC25_WUCFGSD_WAKE_LOW 0x00200000U +#define IOC_IOC25_WUCFGSD_DIS_1 0x00100000U +#define IOC_IOC25_WUCFGSD_DIS_0 0x00000000U + +// Field: [18] WUENSB +// +// Wakeup enable from standby +// ENUMs: +// EN Wakeup enabled (effective only if EDGEDET is +// enabled) +// DIS Wakeup disabled +#define IOC_IOC25_WUENSB 0x00040000U +#define IOC_IOC25_WUENSB_M 0x00040000U +#define IOC_IOC25_WUENSB_S 18U +#define IOC_IOC25_WUENSB_EN 0x00040000U +#define IOC_IOC25_WUENSB_DIS 0x00000000U + +// Field: [17:16] EDGEDET +// +// Edge detect configuration +// ENUMs: +// EDGE_BOTH Positive and negative edge detection +// EDGE_POS Positive edge detection +// EDGE_NEG Negative edge detection +// EDGE_DIS No edge detection +#define IOC_IOC25_EDGEDET_W 2U +#define IOC_IOC25_EDGEDET_M 0x00030000U +#define IOC_IOC25_EDGEDET_S 16U +#define IOC_IOC25_EDGEDET_EDGE_BOTH 0x00030000U +#define IOC_IOC25_EDGEDET_EDGE_POS 0x00020000U +#define IOC_IOC25_EDGEDET_EDGE_NEG 0x00010000U +#define IOC_IOC25_EDGEDET_EDGE_DIS 0x00000000U + +// Field: [14:13] PULLCTL +// +// Pull control. Setting this to value 0x3 disables pull. +// ENUMs: +// PULL_UP Pull up enabled +// PULL_DOWN Pull down enabled +// PULL_DIS No pull +#define IOC_IOC25_PULLCTL_W 2U +#define IOC_IOC25_PULLCTL_M 0x00006000U +#define IOC_IOC25_PULLCTL_S 13U +#define IOC_IOC25_PULLCTL_PULL_UP 0x00004000U +#define IOC_IOC25_PULLCTL_PULL_DOWN 0x00002000U +#define IOC_IOC25_PULLCTL_PULL_DIS 0x00000000U + +// Field: [2:0] PORTCFG +// +// Selects usage of DIO25 +// ENUMs: +// DTB Digital Test Bus function +// ANA Analog function +// PFUNC5 Digital peripheral function-5 +// PFUNC4 Digital peripheral function-4 +// PFUNC3 Digital peripheral function-3 +// PFUNC2 Digital peripheral function-2 +// PFUNC1 Digital peripheral function-1 +// BASE Base function +#define IOC_IOC25_PORTCFG_W 3U +#define IOC_IOC25_PORTCFG_M 0x00000007U +#define IOC_IOC25_PORTCFG_S 0U +#define IOC_IOC25_PORTCFG_DTB 0x00000007U +#define IOC_IOC25_PORTCFG_ANA 0x00000006U +#define IOC_IOC25_PORTCFG_PFUNC5 0x00000005U +#define IOC_IOC25_PORTCFG_PFUNC4 0x00000004U +#define IOC_IOC25_PORTCFG_PFUNC3 0x00000003U +#define IOC_IOC25_PORTCFG_PFUNC2 0x00000002U +#define IOC_IOC25_PORTCFG_PFUNC1 0x00000001U +#define IOC_IOC25_PORTCFG_BASE 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_DTBCFG +// +//***************************************************************************** +// Field: [23] DTB0DIV +// +// This bit is used to divide DTB[0] output by 8. +// ENUMs: +// EN Divide DTB[0] output by 8 +// DIS No divide +#define IOC_DTBCFG_DTB0DIV 0x00800000U +#define IOC_DTBCFG_DTB0DIV_M 0x00800000U +#define IOC_DTBCFG_DTB0DIV_S 23U +#define IOC_DTBCFG_DTB0DIV_EN 0x00800000U +#define IOC_DTBCFG_DTB0DIV_DIS 0x00000000U + +// Field: [18:16] PADSEL +// +// Selects which 3 DTB lines out of total 16 are routed to DTB pins 15 to 13. +// ENUMs: +// DTB2TO0 DTB[2:0] selected +// DTB5TO3 DTB[5:3] selected +// DTB8TO6 DTB[8:6] selected +// DTB11TO9 DTB[11:9] selected +// DTB14TO12 DTB[14:12] selected +// DTB15TO13 DTB[15:13] selected +#define IOC_DTBCFG_PADSEL_W 3U +#define IOC_DTBCFG_PADSEL_M 0x00070000U +#define IOC_DTBCFG_PADSEL_S 16U +#define IOC_DTBCFG_PADSEL_DTB2TO0 0x00050000U +#define IOC_DTBCFG_PADSEL_DTB5TO3 0x00040000U +#define IOC_DTBCFG_PADSEL_DTB8TO6 0x00030000U +#define IOC_DTBCFG_PADSEL_DTB11TO9 0x00020000U +#define IOC_DTBCFG_PADSEL_DTB14TO12 0x00010000U +#define IOC_DTBCFG_PADSEL_DTB15TO13 0x00000000U + +// Field: [12:8] ULLSEL +// +// ULL DTB Mux selection +#define IOC_DTBCFG_ULLSEL_W 5U +#define IOC_DTBCFG_ULLSEL_M 0x00001F00U +#define IOC_DTBCFG_ULLSEL_S 8U + +// Field: [4:0] SVTSEL +// +// SVT DTB Mux selection +#define IOC_DTBCFG_SVTSEL_W 5U +#define IOC_DTBCFG_SVTSEL_M 0x0000001FU +#define IOC_DTBCFG_SVTSEL_S 0U + +//***************************************************************************** +// +// Register: IOC_O_DTBOE +// +//***************************************************************************** +// Field: [15] EN15 +// +// Enables DTB output 15 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN15 0x00008000U +#define IOC_DTBOE_EN15_M 0x00008000U +#define IOC_DTBOE_EN15_S 15U +#define IOC_DTBOE_EN15_EN 0x00008000U +#define IOC_DTBOE_EN15_DIS 0x00000000U + +// Field: [14] EN14 +// +// Enables DTB output 14 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN14 0x00004000U +#define IOC_DTBOE_EN14_M 0x00004000U +#define IOC_DTBOE_EN14_S 14U +#define IOC_DTBOE_EN14_EN 0x00004000U +#define IOC_DTBOE_EN14_DIS 0x00000000U + +// Field: [13] EN13 +// +// Enables DTB output 13 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN13 0x00002000U +#define IOC_DTBOE_EN13_M 0x00002000U +#define IOC_DTBOE_EN13_S 13U +#define IOC_DTBOE_EN13_EN 0x00002000U +#define IOC_DTBOE_EN13_DIS 0x00000000U + +// Field: [12] EN12 +// +// Enables DTB output 12 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN12 0x00001000U +#define IOC_DTBOE_EN12_M 0x00001000U +#define IOC_DTBOE_EN12_S 12U +#define IOC_DTBOE_EN12_EN 0x00001000U +#define IOC_DTBOE_EN12_DIS 0x00000000U + +// Field: [11] EN11 +// +// Enables DTB output 11 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN11 0x00000800U +#define IOC_DTBOE_EN11_M 0x00000800U +#define IOC_DTBOE_EN11_S 11U +#define IOC_DTBOE_EN11_EN 0x00000800U +#define IOC_DTBOE_EN11_DIS 0x00000000U + +// Field: [10] EN10 +// +// Enables DTB output 10 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN10 0x00000400U +#define IOC_DTBOE_EN10_M 0x00000400U +#define IOC_DTBOE_EN10_S 10U +#define IOC_DTBOE_EN10_EN 0x00000400U +#define IOC_DTBOE_EN10_DIS 0x00000000U + +// Field: [9] EN9 +// +// Enables DTB output 9 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN9 0x00000200U +#define IOC_DTBOE_EN9_M 0x00000200U +#define IOC_DTBOE_EN9_S 9U +#define IOC_DTBOE_EN9_EN 0x00000200U +#define IOC_DTBOE_EN9_DIS 0x00000000U + +// Field: [8] EN8 +// +// Enables DTB output 8 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN8 0x00000100U +#define IOC_DTBOE_EN8_M 0x00000100U +#define IOC_DTBOE_EN8_S 8U +#define IOC_DTBOE_EN8_EN 0x00000100U +#define IOC_DTBOE_EN8_DIS 0x00000000U + +// Field: [7] EN7 +// +// Enables DTB output 7 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN7 0x00000080U +#define IOC_DTBOE_EN7_M 0x00000080U +#define IOC_DTBOE_EN7_S 7U +#define IOC_DTBOE_EN7_EN 0x00000080U +#define IOC_DTBOE_EN7_DIS 0x00000000U + +// Field: [6] EN6 +// +// Enables DTB output 6 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN6 0x00000040U +#define IOC_DTBOE_EN6_M 0x00000040U +#define IOC_DTBOE_EN6_S 6U +#define IOC_DTBOE_EN6_EN 0x00000040U +#define IOC_DTBOE_EN6_DIS 0x00000000U + +// Field: [5] EN5 +// +// Enables DTB output 5 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN5 0x00000020U +#define IOC_DTBOE_EN5_M 0x00000020U +#define IOC_DTBOE_EN5_S 5U +#define IOC_DTBOE_EN5_EN 0x00000020U +#define IOC_DTBOE_EN5_DIS 0x00000000U + +// Field: [4] EN4 +// +// Enables DTB output 4 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN4 0x00000010U +#define IOC_DTBOE_EN4_M 0x00000010U +#define IOC_DTBOE_EN4_S 4U +#define IOC_DTBOE_EN4_EN 0x00000010U +#define IOC_DTBOE_EN4_DIS 0x00000000U + +// Field: [3] EN3 +// +// Enables DTB output 3 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN3 0x00000008U +#define IOC_DTBOE_EN3_M 0x00000008U +#define IOC_DTBOE_EN3_S 3U +#define IOC_DTBOE_EN3_EN 0x00000008U +#define IOC_DTBOE_EN3_DIS 0x00000000U + +// Field: [2] EN2 +// +// Enables DTB output 2 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN2 0x00000004U +#define IOC_DTBOE_EN2_M 0x00000004U +#define IOC_DTBOE_EN2_S 2U +#define IOC_DTBOE_EN2_EN 0x00000004U +#define IOC_DTBOE_EN2_DIS 0x00000000U + +// Field: [1] EN1 +// +// Enables DTB output 1 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN1 0x00000002U +#define IOC_DTBOE_EN1_M 0x00000002U +#define IOC_DTBOE_EN1_S 1U +#define IOC_DTBOE_EN1_EN 0x00000002U +#define IOC_DTBOE_EN1_DIS 0x00000000U + +// Field: [0] EN0 +// +// Enables DTB output 0 +// ENUMs: +// EN DTB output enabled +// DIS DTB output disabled +#define IOC_DTBOE_EN0 0x00000001U +#define IOC_DTBOE_EN0_M 0x00000001U +#define IOC_DTBOE_EN0_S 0U +#define IOC_DTBOE_EN0_EN 0x00000001U +#define IOC_DTBOE_EN0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_EVTCFG +// +//***************************************************************************** +// Field: [8] EVTIFG +// +// Event flag. It is set when edge is detected on selected DIO. +// Note: The edge detector flop is cleared for the selected DIO when EVTIFG is +// cleared by software. +// ENUMs: +// SET Set ULL event +// CLR Clear ULL event +#define IOC_EVTCFG_EVTIFG 0x00000100U +#define IOC_EVTCFG_EVTIFG_M 0x00000100U +#define IOC_EVTCFG_EVTIFG_S 8U +#define IOC_EVTCFG_EVTIFG_SET 0x00000100U +#define IOC_EVTCFG_EVTIFG_CLR 0x00000000U + +// Field: [7] EVTEN +// +// Enables IOC to publish event on AON event fabric when EVTIFG is set. +// ENUMs: +// EN Enable +// DIS Disable +#define IOC_EVTCFG_EVTEN 0x00000080U +#define IOC_EVTCFG_EVTEN_M 0x00000080U +#define IOC_EVTCFG_EVTEN_S 7U +#define IOC_EVTCFG_EVTEN_EN 0x00000080U +#define IOC_EVTCFG_EVTEN_DIS 0x00000000U + +// Field: [5:0] DIOSEL +// +// This is used to select DIO for event generation. For example, DIOSEL = 0x0 +// selects DIO0 and DIOSEL = 0x8 selects DIO8. +#define IOC_EVTCFG_DIOSEL_W 6U +#define IOC_EVTCFG_DIOSEL_M 0x0000003FU +#define IOC_EVTCFG_DIOSEL_S 0U + +//***************************************************************************** +// +// Register: IOC_O_TEST +// +//***************************************************************************** +// Field: [0] SEL +// +// This is used to drive SWDIO (Serial Wire DIO) output data and output enable +// from debug sub-system onto DIO12 (Test Data Output) pad. +// ENUMs: +// HI Output data and output enable driven based on +// debug sub-system inputs +// LO Output data and output enable managed by IOC +#define IOC_TEST_SEL 0x00000001U +#define IOC_TEST_SEL_M 0x00000001U +#define IOC_TEST_SEL_S 0U +#define IOC_TEST_SEL_HI 0x00000001U +#define IOC_TEST_SEL_LO 0x00000000U + +//***************************************************************************** +// +// Register: IOC_O_DTBSTAT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// This bit field captures the final 16-bit value of DTB signals provided from +// IOC to device pins. +#define IOC_DTBSTAT_VAL_W 16U +#define IOC_DTBSTAT_VAL_M 0x0000FFFFU +#define IOC_DTBSTAT_VAL_S 0U + + +#endif // __IOC__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt.h new file mode 100644 index 00000000..cfabd972 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt.h @@ -0,0 +1,3125 @@ +/****************************************************************************** +* Filename: hw_lgpt_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LGPT_H__ +#define __HW_LGPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LGPT component +// +//***************************************************************************** +// Description Register. +#define LGPT_O_DESC 0x00000000U + +// Description Extended +#define LGPT_O_DESCEX 0x00000004U + +// Start Configuration +#define LGPT_O_STARTCFG 0x00000008U + +// Timer Control +#define LGPT_O_CTL 0x0000000CU + +// Output Control +#define LGPT_O_OUTCTL 0x00000010U + +// Counter +#define LGPT_O_CNTR 0x00000014U + +// Clock Prescaler Configuration +#define LGPT_O_PRECFG 0x00000018U + +// Prescaler Event +#define LGPT_O_PREEVENT 0x0000001CU + +// Channel Input Filter +#define LGPT_O_CHFILT 0x00000020U + +// Quadrature Decoder Status +#define LGPT_O_QDECSTAT 0x00000034U + +// IR Generation +#define LGPT_O_IRGEN 0x00000038U + +// Direct Memory Accsess +#define LGPT_O_DMA 0x0000003CU + +// Direct Memory Access +#define LGPT_O_DMARW 0x00000040U + +// ADC Trigger +#define LGPT_O_ADCTRG 0x00000044U + +// IO Controller +#define LGPT_O_IOCTL 0x00000048U + +// Interrupt mask. +#define LGPT_O_IMASK 0x00000068U + +// Raw interrupt status. +#define LGPT_O_RIS 0x0000006CU + +// Masked interrupt status. +#define LGPT_O_MIS 0x00000070U + +// Interrupt set register. +#define LGPT_O_ISET 0x00000074U + +// Interrupt clear register. +#define LGPT_O_ICLR 0x00000078U + +// Interrupt mask set register. +#define LGPT_O_IMSET 0x0000007CU + +// Interrupt mask clear register. +#define LGPT_O_IMCLR 0x00000080U + +// Debug control +#define LGPT_O_EMU 0x00000084U + +// Channel 0 Configuration +#define LGPT_O_C0CFG 0x000000C0U + +// Channel 1 Configuration +#define LGPT_O_C1CFG 0x000000C4U + +// Channel 2 Configuration +#define LGPT_O_C2CFG 0x000000C8U + +// Pipeline Target +#define LGPT_O_PTGT 0x000000FCU + +// Pipeline Channel 0 Capture Compare +#define LGPT_O_PC0CC 0x00000100U + +// Pipeline Channel 1 Capture Compare +#define LGPT_O_PC1CC 0x00000104U + +// Pipeline Channel 2 Capture Compare +#define LGPT_O_PC2CC 0x00000108U + +// Target +#define LGPT_O_TGT 0x0000013CU + +// Channel 0 Capture Compare +#define LGPT_O_C0CC 0x00000140U + +// Channel 1 Capture Compare +#define LGPT_O_C1CC 0x00000144U + +// Channel 2 Capture Compare +#define LGPT_O_C2CC 0x00000148U + +// Pipeline Target No Clear +#define LGPT_O_PTGTNC 0x0000017CU + +// Pipeline Channel 0 Capture Compare No Clear +#define LGPT_O_PC0CCNC 0x00000180U + +// Pipeline Channel 1 Capture Compare No Clear +#define LGPT_O_PC1CCNC 0x00000184U + +// Pipeline Channel 2 Capture Compare No Clear +#define LGPT_O_PC2CCNC 0x00000188U + +// Target No Clear +#define LGPT_O_TGTNC 0x000001BCU + +// Channel 0 Capture Compare No Clear +#define LGPT_O_C0CCNC 0x000001C0U + +// Channel 1 Capture Compare No Clear +#define LGPT_O_C1CCNC 0x000001C4U + +// Channel 2 Capture Compare No Clear +#define LGPT_O_C2CCNC 0x000001C8U + +//***************************************************************************** +// +// Register: LGPT_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define LGPT_DESC_MODID_W 16U +#define LGPT_DESC_MODID_M 0xFFFF0000U +#define LGPT_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define LGPT_DESC_STDIPOFF_W 4U +#define LGPT_DESC_STDIPOFF_M 0x0000F000U +#define LGPT_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number. +#define LGPT_DESC_INSTIDX_W 4U +#define LGPT_DESC_INSTIDX_M 0x00000F00U +#define LGPT_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP. +#define LGPT_DESC_MAJREV_W 4U +#define LGPT_DESC_MAJREV_M 0x000000F0U +#define LGPT_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP. +#define LGPT_DESC_MINREV_W 4U +#define LGPT_DESC_MINREV_M 0x0000000FU +#define LGPT_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_DESCEX +// +//***************************************************************************** +// Field: [19] HIR +// +// Has IR logic. +#define LGPT_DESCEX_HIR 0x00080000U +#define LGPT_DESCEX_HIR_M 0x00080000U +#define LGPT_DESCEX_HIR_S 19U + +// Field: [18] HDBF +// +// Has Dead-Band, Fault, and Park logic. +#define LGPT_DESCEX_HDBF 0x00040000U +#define LGPT_DESCEX_HDBF_M 0x00040000U +#define LGPT_DESCEX_HDBF_S 18U + +// Field: [17:14] PREW +// +// Prescale width. The prescaler can maximum be configured to 2^PREW-1. +#define LGPT_DESCEX_PREW_W 4U +#define LGPT_DESCEX_PREW_M 0x0003C000U +#define LGPT_DESCEX_PREW_S 14U + +// Field: [13] HQDEC +// +// Has Quadrature Decoder. +#define LGPT_DESCEX_HQDEC 0x00002000U +#define LGPT_DESCEX_HQDEC_M 0x00002000U +#define LGPT_DESCEX_HQDEC_S 13U + +// Field: [12] HCIF +// +// Has channel input filter. +#define LGPT_DESCEX_HCIF 0x00001000U +#define LGPT_DESCEX_HCIF_M 0x00001000U +#define LGPT_DESCEX_HCIF_S 12U + +// Field: [11:8] CIFS +// +// Channel input filter size. The prevailing state filter can maximum be +// configured to 2^CIFS-1. +#define LGPT_DESCEX_CIFS_W 4U +#define LGPT_DESCEX_CIFS_M 0x00000F00U +#define LGPT_DESCEX_CIFS_S 8U + +// Field: [7] HDMA +// +// Has uDMA output and logic. +#define LGPT_DESCEX_HDMA 0x00000080U +#define LGPT_DESCEX_HDMA_M 0x00000080U +#define LGPT_DESCEX_HDMA_S 7U + +// Field: [6] HINT +// +// Has interrupt output and logic. +#define LGPT_DESCEX_HINT 0x00000040U +#define LGPT_DESCEX_HINT_M 0x00000040U +#define LGPT_DESCEX_HINT_S 6U + +// Field: [5:4] CNTRW +// +// Counter bit-width. +// The maximum counter value is equal to 2^CNTRW-1. +// ENUMs: +// RESERVED RESERVED +// CNTR32 32-bit counter. +// CNTR24 24-bit counter. +// CNTR16 16-bit counter. +#define LGPT_DESCEX_CNTRW_W 2U +#define LGPT_DESCEX_CNTRW_M 0x00000030U +#define LGPT_DESCEX_CNTRW_S 4U +#define LGPT_DESCEX_CNTRW_RESERVED 0x00000030U +#define LGPT_DESCEX_CNTRW_CNTR32 0x00000020U +#define LGPT_DESCEX_CNTRW_CNTR24 0x00000010U +#define LGPT_DESCEX_CNTRW_CNTR16 0x00000000U + +// Field: [3:0] NCH +// +// Number of channels. +#define LGPT_DESCEX_NCH_W 4U +#define LGPT_DESCEX_NCH_M 0x0000000FU +#define LGPT_DESCEX_NCH_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_STARTCFG +// +//***************************************************************************** +// Field: [1:0] LGPT +// +// LGPT start +// ENUMs: +// EV_SYNC LGPT starts when synchronized event input is high. +// Configured here EVTSVT.LGPTSYNCSEL. +#define LGPT_STARTCFG_LGPT_W 2U +#define LGPT_STARTCFG_LGPT_M 0x00000003U +#define LGPT_STARTCFG_LGPT_S 0U +#define LGPT_STARTCFG_LGPT_EV_SYNC 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_CTL +// +//***************************************************************************** +// Field: [10] C2RST +// +// Channel 2 reset. +// ENUMs: +// RST Reset C2CC, PC2CC, and C2CFG. +// NOEFF No effect. +#define LGPT_CTL_C2RST 0x00000400U +#define LGPT_CTL_C2RST_M 0x00000400U +#define LGPT_CTL_C2RST_S 10U +#define LGPT_CTL_C2RST_RST 0x00000400U +#define LGPT_CTL_C2RST_NOEFF 0x00000000U + +// Field: [9] C1RST +// +// Channel 1 reset. +// ENUMs: +// RST Reset C1CC, PC1CC, and C1CFG. +// NOEFF No effect. +#define LGPT_CTL_C1RST 0x00000200U +#define LGPT_CTL_C1RST_M 0x00000200U +#define LGPT_CTL_C1RST_S 9U +#define LGPT_CTL_C1RST_RST 0x00000200U +#define LGPT_CTL_C1RST_NOEFF 0x00000000U + +// Field: [8] C0RST +// +// Channel 0 reset. +// ENUMs: +// RST Reset C0CC, PC0CC, and C0CFG. +// NOEFF No effect. +#define LGPT_CTL_C0RST 0x00000100U +#define LGPT_CTL_C0RST_M 0x00000100U +#define LGPT_CTL_C0RST_S 8U +#define LGPT_CTL_C0RST_RST 0x00000100U +#define LGPT_CTL_C0RST_NOEFF 0x00000000U + +// Field: [5] INTP +// +// Interrupt Phase. +// This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set. +// ENUMs: +// LATE RIS.TGT and RIS.ZERO are set one timer clock cycle +// after CNTR = TARGET/ZERO. +// EARLY RIS.TGT and RIS.ZERO are set one system clock +// cycle after CNTR = TARGET/ZERO. +#define LGPT_CTL_INTP 0x00000020U +#define LGPT_CTL_INTP_M 0x00000020U +#define LGPT_CTL_INTP_S 5U +#define LGPT_CTL_INTP_LATE 0x00000020U +#define LGPT_CTL_INTP_EARLY 0x00000000U + +// Field: [4:3] CMPDIR +// +// Compare direction. +// +// This bit field controls the direction the counter must have in order to set +// the [RIS.CnCC] channel interrupts. This bitfield is only relevant if +// [CnCFG.CCACT] is configured to a compare action. +// ENUMs: +// RESERVED RESERVED +// DOWN Compare RIS fields are only set on down count. +// UP Compare RIS fields are only set on up count. +// BOTH Compare RIS fields are set on up count and down +// count. +#define LGPT_CTL_CMPDIR_W 2U +#define LGPT_CTL_CMPDIR_M 0x00000018U +#define LGPT_CTL_CMPDIR_S 3U +#define LGPT_CTL_CMPDIR_RESERVED 0x00000018U +#define LGPT_CTL_CMPDIR_DOWN 0x00000010U +#define LGPT_CTL_CMPDIR_UP 0x00000008U +#define LGPT_CTL_CMPDIR_BOTH 0x00000000U + +// Field: [2:0] MODE +// +// Timer mode control +// +// The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, +// QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. +// +// When writing MODE all internally queued updates to the channels and TGT is +// cleared. +// +// When configuring the timer, MODE should be the last thing to configure. If +// changing timer configuration after MODE has been set is necessary, +// instructions, if any, given in the configuration registers should be +// followed. See for example C0CFG. +// ENUMs: +// SYNC_UPDWN_PER Start counting up and down periodically +// synchronous to another LGPT, selected within +// STARTCFG. The timer is started by setting +// CTL.MODE = UPDWN_PER automatically. +// It then operates as a +// normal timer in CTL.MODE = UPDWN_PER, counting +// from 0 to target value and back to 0, +// repeatedly. +// +// Period = (target value * +// 2) * timer clock period +// SYNC_UP_PER Start counting up periodically synchronous to +// another LGPT, selected within STARTCFG. The +// timer is started by setting CTL.MODE = UP_PER +// automatically. +// It then operates as a +// normal timer in CTL.MODE = UP_PER, incrementing +// from 0 to target value, repeatedly. +// +// Period = (target value * +// 2) * timer clock period +// SYNC_UP_ONCE Start counting up once synchronous to another +// LGPT, selected within STARTCFG. The timer is +// started by setting CTL.MODE = UP_ONCE +// automatically. +// It then functions as a +// normal timer in CTL.MODE = UP_ONCE, +// incrementing from 0 to target value, then +// stops and sets MODE to DIS. +// QDEC The timer functions as a quadrature decoder. IOC +// input 0, IOC input 1 and IOC input 2 are used +// respectivly as PHA, PHB and IDX inputs. IDX can +// be turned off by setting C2CFG.EDGE = NONE. +// The timer clock frequency +// sets the sample rate of the QDEC logic. This +// frequency can be configured in PRECFG. +// UPDWN_PER Count up and down periodically. The timer counts +// from 0 to target value and back to 0, +// repeatedly. +// +// Period = (target value * +// 2) * timer clock period +// UP_PER Count up periodically. The timer increments from 0 +// to target value, repeatedly. +// +// Period = (target value + +// 1) * timer clock period +// UP_ONCE Count up once. The timer increments from 0 to +// target value, then stops and sets MODE to DIS. +// DIS Disable timer. Updates to counter, channels, and +// events stop. +#define LGPT_CTL_MODE_W 3U +#define LGPT_CTL_MODE_M 0x00000007U +#define LGPT_CTL_MODE_S 0U +#define LGPT_CTL_MODE_SYNC_UPDWN_PER 0x00000007U +#define LGPT_CTL_MODE_SYNC_UP_PER 0x00000006U +#define LGPT_CTL_MODE_SYNC_UP_ONCE 0x00000005U +#define LGPT_CTL_MODE_QDEC 0x00000004U +#define LGPT_CTL_MODE_UPDWN_PER 0x00000003U +#define LGPT_CTL_MODE_UP_PER 0x00000002U +#define LGPT_CTL_MODE_UP_ONCE 0x00000001U +#define LGPT_CTL_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_OUTCTL +// +//***************************************************************************** +// Field: [5] SETOUT2 +// +// Set output 2. +// +// Write 1 to set output 2. +#define LGPT_OUTCTL_SETOUT2 0x00000020U +#define LGPT_OUTCTL_SETOUT2_M 0x00000020U +#define LGPT_OUTCTL_SETOUT2_S 5U + +// Field: [4] CLROUT2 +// +// Clear output 2. +// +// Write 1 to clear output 2. +#define LGPT_OUTCTL_CLROUT2 0x00000010U +#define LGPT_OUTCTL_CLROUT2_M 0x00000010U +#define LGPT_OUTCTL_CLROUT2_S 4U + +// Field: [3] SETOUT1 +// +// Set output 1. +// +// Write 1 to set output 1. +#define LGPT_OUTCTL_SETOUT1 0x00000008U +#define LGPT_OUTCTL_SETOUT1_M 0x00000008U +#define LGPT_OUTCTL_SETOUT1_S 3U + +// Field: [2] CLROUT1 +// +// Clear output 1. +// +// Write 1 to clear output 1. +#define LGPT_OUTCTL_CLROUT1 0x00000004U +#define LGPT_OUTCTL_CLROUT1_M 0x00000004U +#define LGPT_OUTCTL_CLROUT1_S 2U + +// Field: [1] SETOUT0 +// +// Set output 0. +// +// Write 1 to set output 0. +#define LGPT_OUTCTL_SETOUT0 0x00000002U +#define LGPT_OUTCTL_SETOUT0_M 0x00000002U +#define LGPT_OUTCTL_SETOUT0_S 1U + +// Field: [0] CLROUT0 +// +// Clear output 0. +// +// Write 1 to clear output 0. +#define LGPT_OUTCTL_CLROUT0 0x00000001U +#define LGPT_OUTCTL_CLROUT0_M 0x00000001U +#define LGPT_OUTCTL_CLROUT0_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_CNTR +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Current counter value. +// If CTL.MODE = QDEC this can be used to set the initial counter value during +// QDEC. Writing to CNTR in other modes than QDEC is possible, but may result +// in unpredictable behavior. +#define LGPT_CNTR_VAL_W 16U +#define LGPT_CNTR_VAL_M 0x0000FFFFU +#define LGPT_CNTR_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PRECFG +// +//***************************************************************************** +// Field: [15:8] TICKDIV +// +// Tick division. +// +// TICKDIV determines the timer clock frequency for the counter, and timer +// output updates. The timer clock frequency is the clock selected by TICKSRC +// divided by (TICKDIV + 1). This inverse is the timer clock period. +// +// 0x00: Divide by 1. +// 0x01: Divide by 2. +// ... +// 0xFF: Divide by 256. +#define LGPT_PRECFG_TICKDIV_W 8U +#define LGPT_PRECFG_TICKDIV_M 0x0000FF00U +#define LGPT_PRECFG_TICKDIV_S 8U + +// Field: [1:0] TICKSRC +// +// Prescaler tick source. +// +// TICKSRC determines the source which decrements the prescaler. +// ENUMs: +// BOTH_TICK Prescaler is updated at both edges of TICKEN. +// FALL_TICK Prescaler is updated at the falling edge of +// TICKEN. +// RISE_TICK Prescaler is updated at the rising edge of TICKEN. +// CLK Prescaler is updated at the system clock. +#define LGPT_PRECFG_TICKSRC_W 2U +#define LGPT_PRECFG_TICKSRC_M 0x00000003U +#define LGPT_PRECFG_TICKSRC_S 0U +#define LGPT_PRECFG_TICKSRC_BOTH_TICK 0x00000003U +#define LGPT_PRECFG_TICKSRC_FALL_TICK 0x00000002U +#define LGPT_PRECFG_TICKSRC_RISE_TICK 0x00000001U +#define LGPT_PRECFG_TICKSRC_CLK 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_PREEVENT +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Sets the HIGH time of the prescaler event output. +// +// Event goes high when the prescaler counter equals VAL. Event goes low when +// prescaler counter is 0. +// +// Note: +// - Can be used to precharge or turn an external component on for a short time +// before sampling, like in QDEC. +// - If there is a requirement to create such events that have very short +// periods compared to timer clock period, use two timers. One timer acts as +// prescaler and event generator for another timer. +#define LGPT_PREEVENT_VAL_W 8U +#define LGPT_PREEVENT_VAL_M 0x000000FFU +#define LGPT_PREEVENT_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_CHFILT +// +//***************************************************************************** +// Field: [15:8] LOAD +// +// The input of the channel filter is passed to the edge detection logic after +// LOAD + 1 consecutive equal samples. +#define LGPT_CHFILT_LOAD_W 8U +#define LGPT_CHFILT_LOAD_M 0x0000FF00U +#define LGPT_CHFILT_LOAD_S 8U + +// Field: [1:0] MODE +// +// Channel filter mode +// ENUMs: +// TIMERCLK Filter is clocked by timer clock. +// TICKSRC Filter is clocked by PRECFG.TICKSRC. +// CLK Filter is clocked by system clock. +// BYPASS Filter is bypassed. No Filter is used. +#define LGPT_CHFILT_MODE_W 2U +#define LGPT_CHFILT_MODE_M 0x00000003U +#define LGPT_CHFILT_MODE_S 0U +#define LGPT_CHFILT_MODE_TIMERCLK 0x00000003U +#define LGPT_CHFILT_MODE_TICKSRC 0x00000002U +#define LGPT_CHFILT_MODE_CLK 0x00000001U +#define LGPT_CHFILT_MODE_BYPASS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_QDECSTAT +// +//***************************************************************************** +// Field: [1] DBLTRANS +// +// Double transition +// ENUMs: +// DBL Double transition on phase inputs. +// NONE Single or no transition on phase inputs. +#define LGPT_QDECSTAT_DBLTRANS 0x00000002U +#define LGPT_QDECSTAT_DBLTRANS_M 0x00000002U +#define LGPT_QDECSTAT_DBLTRANS_S 1U +#define LGPT_QDECSTAT_DBLTRANS_DBL 0x00000002U +#define LGPT_QDECSTAT_DBLTRANS_NONE 0x00000000U + +// Field: [0] QDIR +// +// Direction of count during QDEC mode. +// ENUMs: +// DOWN Down (PHB leads PHA) +// UP Up (PHA leads PHB) +#define LGPT_QDECSTAT_QDIR 0x00000001U +#define LGPT_QDECSTAT_QDIR_M 0x00000001U +#define LGPT_QDECSTAT_QDIR_S 0U +#define LGPT_QDECSTAT_QDIR_DOWN 0x00000001U +#define LGPT_QDECSTAT_QDIR_UP 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_IRGEN +// +//***************************************************************************** +// Field: [0] CTL +// +// Control +// ENUMs: +// EN Enable. +// DIS Disable. +#define LGPT_IRGEN_CTL 0x00000001U +#define LGPT_IRGEN_CTL_M 0x00000001U +#define LGPT_IRGEN_CTL_S 0U +#define LGPT_IRGEN_CTL_EN 0x00000001U +#define LGPT_IRGEN_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_DMA +// +//***************************************************************************** +// Field: [19:16] RWCNTR +// +// The read/write counter. RWCNTR+1 is the number of times the DMA can access +// (read/write) the DMARW register. For each DMA access to DMARW an internal +// counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR +// is the final register address which can be accessed by the DMA. +#define LGPT_DMA_RWCNTR_W 4U +#define LGPT_DMA_RWCNTR_M 0x000F0000U +#define LGPT_DMA_RWCNTR_S 16U + +// Field: [14:8] RWADDR +// +// The base address which the DMA access when reading/writing DMARW. The base +// address is set by taking the 9 LSB of the physical address and divide by 4. +// For example, if you wanted the RWADDR to point to the PTGT register you +// should set RWADDR = 0x0FC/4. +#define LGPT_DMA_RWADDR_W 7U +#define LGPT_DMA_RWADDR_M 0x00007F00U +#define LGPT_DMA_RWADDR_S 8U + +// Field: [3:0] REQ +// +// ENUMs: +// C11CC Setting of RIS.C11CC generates a DMA request. +// C10CC Setting of RIS.C10CC generates a DMA request. +// C9CC Setting of RIS.C9CC generates a DMA request. +// C8CC Setting of RIS.C8CC generates a DMA request. +// C7CC Setting of RIS.C7CC generates a DMA request. +// C6CC Setting of RIS.C6CC generates a DMA request. +// C5CC Setting of RIS.C5CC generates a DMA request. +// C4CC Setting of RIS.C4CC generates a DMA request. +// C3CC Setting of RIS.C3CC generates a DMA request. +// C2CC Setting of RIS.C2CC generates a DMA request. +// C1CC Setting of RIS.C1CC generates a DMA request. +// C0CC Setting of RIS.C0CC generates a DMA request. +// FAULT Setting of RIS.FAULT generates a DMA request. +// ZERO Setting of RIS.ZERO generates a DMA request. +// TGT Setting of RIS.TGT generates a DMA request. +// DIS Disabled +#define LGPT_DMA_REQ_W 4U +#define LGPT_DMA_REQ_M 0x0000000FU +#define LGPT_DMA_REQ_S 0U +#define LGPT_DMA_REQ_C11CC 0x0000000FU +#define LGPT_DMA_REQ_C10CC 0x0000000EU +#define LGPT_DMA_REQ_C9CC 0x0000000DU +#define LGPT_DMA_REQ_C8CC 0x0000000CU +#define LGPT_DMA_REQ_C7CC 0x0000000BU +#define LGPT_DMA_REQ_C6CC 0x0000000AU +#define LGPT_DMA_REQ_C5CC 0x00000009U +#define LGPT_DMA_REQ_C4CC 0x00000008U +#define LGPT_DMA_REQ_C3CC 0x00000007U +#define LGPT_DMA_REQ_C2CC 0x00000006U +#define LGPT_DMA_REQ_C1CC 0x00000005U +#define LGPT_DMA_REQ_C0CC 0x00000004U +#define LGPT_DMA_REQ_FAULT 0x00000003U +#define LGPT_DMA_REQ_ZERO 0x00000002U +#define LGPT_DMA_REQ_TGT 0x00000001U +#define LGPT_DMA_REQ_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_DMARW +// +//***************************************************************************** +// Field: [15:0] VAL +// +// DMA read write value. +// +// The value that is read/written from/to the registers. +#define LGPT_DMARW_VAL_W 16U +#define LGPT_DMARW_VAL_M 0x0000FFFFU +#define LGPT_DMARW_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_ADCTRG +// +//***************************************************************************** +// Field: [3:0] SRC +// +// ENUMs: +// C11CC Setting of RIS.C11CC generates an ADC trigger. +// C10CC Setting of RIS.C10CC generates an ADC trigger. +// C9CC Setting of RIS.C9CC generates an ADC trigger. +// C8CC Setting of RIS.C8CC generates an ADC trigger. +// C7CC Setting of RIS.C7CC generates an ADC trigger. +// C6CC Setting of RIS.C6CC generates an ADC trigger. +// C5CC Setting of RIS.C5CC generates an ADC trigger. +// C4CC Setting of RIS.C4CC generates an ADC trigger. +// C3CC Setting of RIS.C3CC generates an ADC trigger. +// C2CC Setting of RIS.C2CC generates an ADC trigger. +// C1CC Setting of RIS.C1CC generates an ADC trigger. +// C0CC Setting of RIS.C0CC generates an ADC trigger. +// FAULT Setting of RIS.FAULT generates an ADC trigger. +// ZERO Setting of RIS.ZERO generates an ADC trigger. +// TGT Setting of RIS.TGT generates an ADC trigger. +// DIS Disabled +#define LGPT_ADCTRG_SRC_W 4U +#define LGPT_ADCTRG_SRC_M 0x0000000FU +#define LGPT_ADCTRG_SRC_S 0U +#define LGPT_ADCTRG_SRC_C11CC 0x0000000FU +#define LGPT_ADCTRG_SRC_C10CC 0x0000000EU +#define LGPT_ADCTRG_SRC_C9CC 0x0000000DU +#define LGPT_ADCTRG_SRC_C8CC 0x0000000CU +#define LGPT_ADCTRG_SRC_C7CC 0x0000000BU +#define LGPT_ADCTRG_SRC_C6CC 0x0000000AU +#define LGPT_ADCTRG_SRC_C5CC 0x00000009U +#define LGPT_ADCTRG_SRC_C4CC 0x00000008U +#define LGPT_ADCTRG_SRC_C3CC 0x00000007U +#define LGPT_ADCTRG_SRC_C2CC 0x00000006U +#define LGPT_ADCTRG_SRC_C1CC 0x00000005U +#define LGPT_ADCTRG_SRC_C0CC 0x00000004U +#define LGPT_ADCTRG_SRC_FAULT 0x00000003U +#define LGPT_ADCTRG_SRC_ZERO 0x00000002U +#define LGPT_ADCTRG_SRC_TGT 0x00000001U +#define LGPT_ADCTRG_SRC_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_IOCTL +// +//***************************************************************************** +// Field: [11:10] COUT2 +// +// IO complementary output 2 control +// +// This bit field controls IO complementary output 2. +// ENUMs: +// INV Inverted value. The IO complementary output is +// inverted. +// HIGH Driven high. The IO complementary output is driven +// high. +// LOW Driven low. The IO complementary output is driven +// low. +// NRM Normal output. The IO complementary output is not +// changed. +#define LGPT_IOCTL_COUT2_W 2U +#define LGPT_IOCTL_COUT2_M 0x00000C00U +#define LGPT_IOCTL_COUT2_S 10U +#define LGPT_IOCTL_COUT2_INV 0x00000C00U +#define LGPT_IOCTL_COUT2_HIGH 0x00000800U +#define LGPT_IOCTL_COUT2_LOW 0x00000400U +#define LGPT_IOCTL_COUT2_NRM 0x00000000U + +// Field: [9:8] OUT2 +// +// IO output 2 control +// +// This bit field controls IO output 2. +// ENUMs: +// INV Inverted value. The IO output is inverted. +// HIGH Driven high. The IO output is driven high. +// LOW Driven low. The IO output is driven low. +// NRM Normal output. The IO output is not changed. +#define LGPT_IOCTL_OUT2_W 2U +#define LGPT_IOCTL_OUT2_M 0x00000300U +#define LGPT_IOCTL_OUT2_S 8U +#define LGPT_IOCTL_OUT2_INV 0x00000300U +#define LGPT_IOCTL_OUT2_HIGH 0x00000200U +#define LGPT_IOCTL_OUT2_LOW 0x00000100U +#define LGPT_IOCTL_OUT2_NRM 0x00000000U + +// Field: [7:6] COUT1 +// +// IO complementary output 1 control +// +// This bit field controls IO complementary output 1. +// ENUMs: +// INV Inverted value. The IO complementary output is +// inverted. +// HIGH Driven high. The IO complementary output is driven +// high. +// LOW Driven low. The IO complementary output is driven +// low. +// NRM Normal output. The IO complementary output is not +// changed. +#define LGPT_IOCTL_COUT1_W 2U +#define LGPT_IOCTL_COUT1_M 0x000000C0U +#define LGPT_IOCTL_COUT1_S 6U +#define LGPT_IOCTL_COUT1_INV 0x000000C0U +#define LGPT_IOCTL_COUT1_HIGH 0x00000080U +#define LGPT_IOCTL_COUT1_LOW 0x00000040U +#define LGPT_IOCTL_COUT1_NRM 0x00000000U + +// Field: [5:4] OUT1 +// +// IO output 1 control +// +// This bit field controls IO output 1. +// ENUMs: +// INV Inverted value. The IO output is inverted. +// HIGH Driven high. The IO output is driven high. +// LOW Driven low. The IO output is driven low. +// NRM Normal output. The IO output is not changed. +#define LGPT_IOCTL_OUT1_W 2U +#define LGPT_IOCTL_OUT1_M 0x00000030U +#define LGPT_IOCTL_OUT1_S 4U +#define LGPT_IOCTL_OUT1_INV 0x00000030U +#define LGPT_IOCTL_OUT1_HIGH 0x00000020U +#define LGPT_IOCTL_OUT1_LOW 0x00000010U +#define LGPT_IOCTL_OUT1_NRM 0x00000000U + +// Field: [3:2] COUT0 +// +// IO complementary output 0 control +// +// This bit field controls IO complementary output 0. +// ENUMs: +// INV Inverted value. The IO complementary output is +// inverted. +// HIGH Driven high. The IO complementary output is driven +// high. +// LOW Driven low. The IO complementary output is driven +// low. +// NRM Normal output. The IO complementary output is not +// changed. +#define LGPT_IOCTL_COUT0_W 2U +#define LGPT_IOCTL_COUT0_M 0x0000000CU +#define LGPT_IOCTL_COUT0_S 2U +#define LGPT_IOCTL_COUT0_INV 0x0000000CU +#define LGPT_IOCTL_COUT0_HIGH 0x00000008U +#define LGPT_IOCTL_COUT0_LOW 0x00000004U +#define LGPT_IOCTL_COUT0_NRM 0x00000000U + +// Field: [1:0] OUT0 +// +// IO output 0 control +// +// This bit field controls IO output 0. +// ENUMs: +// INV Inverted value. The IO output is inverted. +// HIGH Driven high. The IO output is driven high. +// LOW Driven low. The IO output is driven low. +// NRM Normal output. The IO output is not changed. +#define LGPT_IOCTL_OUT0_W 2U +#define LGPT_IOCTL_OUT0_M 0x00000003U +#define LGPT_IOCTL_OUT0_S 0U +#define LGPT_IOCTL_OUT0_INV 0x00000003U +#define LGPT_IOCTL_OUT0_HIGH 0x00000002U +#define LGPT_IOCTL_OUT0_LOW 0x00000001U +#define LGPT_IOCTL_OUT0_NRM 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_IMASK +// +//***************************************************************************** +// Field: [10] C2CC +// +// Enable RIS.C2CC interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_C2CC 0x00000400U +#define LGPT_IMASK_C2CC_M 0x00000400U +#define LGPT_IMASK_C2CC_S 10U +#define LGPT_IMASK_C2CC_EN 0x00000400U +#define LGPT_IMASK_C2CC_DIS 0x00000000U + +// Field: [9] C1CC +// +// Enable RIS.C1CC interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_C1CC 0x00000200U +#define LGPT_IMASK_C1CC_M 0x00000200U +#define LGPT_IMASK_C1CC_S 9U +#define LGPT_IMASK_C1CC_EN 0x00000200U +#define LGPT_IMASK_C1CC_DIS 0x00000000U + +// Field: [8] C0CC +// +// Enable RIS.C0CC interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_C0CC 0x00000100U +#define LGPT_IMASK_C0CC_M 0x00000100U +#define LGPT_IMASK_C0CC_S 8U +#define LGPT_IMASK_C0CC_EN 0x00000100U +#define LGPT_IMASK_C0CC_DIS 0x00000000U + +// Field: [6] FAULT +// +// Enable RIS.FAULT interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_FAULT 0x00000040U +#define LGPT_IMASK_FAULT_M 0x00000040U +#define LGPT_IMASK_FAULT_S 6U +#define LGPT_IMASK_FAULT_EN 0x00000040U +#define LGPT_IMASK_FAULT_DIS 0x00000000U + +// Field: [5] IDX +// +// Enable RIS.IDX interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_IDX 0x00000020U +#define LGPT_IMASK_IDX_M 0x00000020U +#define LGPT_IMASK_IDX_S 5U +#define LGPT_IMASK_IDX_EN 0x00000020U +#define LGPT_IMASK_IDX_DIS 0x00000000U + +// Field: [4] DIRCHNG +// +// Enable RIS.DIRCHNG interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_DIRCHNG 0x00000010U +#define LGPT_IMASK_DIRCHNG_M 0x00000010U +#define LGPT_IMASK_DIRCHNG_S 4U +#define LGPT_IMASK_DIRCHNG_EN 0x00000010U +#define LGPT_IMASK_DIRCHNG_DIS 0x00000000U + +// Field: [3] CNTRCHNG +// +// Enable RIS.CNTRCHNG interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_CNTRCHNG 0x00000008U +#define LGPT_IMASK_CNTRCHNG_M 0x00000008U +#define LGPT_IMASK_CNTRCHNG_S 3U +#define LGPT_IMASK_CNTRCHNG_EN 0x00000008U +#define LGPT_IMASK_CNTRCHNG_DIS 0x00000000U + +// Field: [2] DBLTRANS +// +// Enable RIS.DBLTRANS interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_DBLTRANS 0x00000004U +#define LGPT_IMASK_DBLTRANS_M 0x00000004U +#define LGPT_IMASK_DBLTRANS_S 2U +#define LGPT_IMASK_DBLTRANS_EN 0x00000004U +#define LGPT_IMASK_DBLTRANS_DIS 0x00000000U + +// Field: [1] ZERO +// +// Enable RIS.ZERO interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_ZERO 0x00000002U +#define LGPT_IMASK_ZERO_M 0x00000002U +#define LGPT_IMASK_ZERO_S 1U +#define LGPT_IMASK_ZERO_EN 0x00000002U +#define LGPT_IMASK_ZERO_DIS 0x00000000U + +// Field: [0] TGT +// +// Enable RIS.TGT interrupt. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT_IMASK_TGT 0x00000001U +#define LGPT_IMASK_TGT_M 0x00000001U +#define LGPT_IMASK_TGT_S 0U +#define LGPT_IMASK_TGT_EN 0x00000001U +#define LGPT_IMASK_TGT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_RIS +// +//***************************************************************************** +// Field: [10] C2CC +// +// Status of the C2CC interrupt. The interrupt is set when C2CC has capture or +// compare event. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_C2CC 0x00000400U +#define LGPT_RIS_C2CC_M 0x00000400U +#define LGPT_RIS_C2CC_S 10U +#define LGPT_RIS_C2CC_SET 0x00000400U +#define LGPT_RIS_C2CC_CLR 0x00000000U + +// Field: [9] C1CC +// +// Status of the C1CC interrupt. The interrupt is set when C1CC has capture or +// compare event. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_C1CC 0x00000200U +#define LGPT_RIS_C1CC_M 0x00000200U +#define LGPT_RIS_C1CC_S 9U +#define LGPT_RIS_C1CC_SET 0x00000200U +#define LGPT_RIS_C1CC_CLR 0x00000000U + +// Field: [8] C0CC +// +// Status of the C0CC interrupt. The interrupt is set when C0CC has capture or +// compare event. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_C0CC 0x00000100U +#define LGPT_RIS_C0CC_M 0x00000100U +#define LGPT_RIS_C0CC_S 8U +#define LGPT_RIS_C0CC_SET 0x00000100U +#define LGPT_RIS_C0CC_CLR 0x00000000U + +// Field: [6] FAULT +// +// Status of the FAULT interrupt. The interrupt is set immediately on active +// fault input. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_FAULT 0x00000040U +#define LGPT_RIS_FAULT_M 0x00000040U +#define LGPT_RIS_FAULT_S 6U +#define LGPT_RIS_FAULT_SET 0x00000040U +#define LGPT_RIS_FAULT_CLR 0x00000000U + +// Field: [5] IDX +// +// Status of the IDX interrupt. The interrupt is set when IDX is active. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_IDX 0x00000020U +#define LGPT_RIS_IDX_M 0x00000020U +#define LGPT_RIS_IDX_S 5U +#define LGPT_RIS_IDX_SET 0x00000020U +#define LGPT_RIS_IDX_CLR 0x00000000U + +// Field: [4] DIRCHNG +// +// Status of the DIRCHNG interrupt. The interrupt is set when the direction of +// the counter changes. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_DIRCHNG 0x00000010U +#define LGPT_RIS_DIRCHNG_M 0x00000010U +#define LGPT_RIS_DIRCHNG_S 4U +#define LGPT_RIS_DIRCHNG_SET 0x00000010U +#define LGPT_RIS_DIRCHNG_CLR 0x00000000U + +// Field: [3] CNTRCHNG +// +// Status of the CNTRCHNG interrupt. The interrupt is set when the counter +// increments or decrements. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_CNTRCHNG 0x00000008U +#define LGPT_RIS_CNTRCHNG_M 0x00000008U +#define LGPT_RIS_CNTRCHNG_S 3U +#define LGPT_RIS_CNTRCHNG_SET 0x00000008U +#define LGPT_RIS_CNTRCHNG_CLR 0x00000000U + +// Field: [2] DBLTRANS +// +// Status of the DBLTRANS interrupt. The interrupt is set when a double +// transition has happened during QDEC mode. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_DBLTRANS 0x00000004U +#define LGPT_RIS_DBLTRANS_M 0x00000004U +#define LGPT_RIS_DBLTRANS_S 2U +#define LGPT_RIS_DBLTRANS_SET 0x00000004U +#define LGPT_RIS_DBLTRANS_CLR 0x00000000U + +// Field: [1] ZERO +// +// Status of the ZERO interrupt. The interrupt is set when CNTR = 0. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_ZERO 0x00000002U +#define LGPT_RIS_ZERO_M 0x00000002U +#define LGPT_RIS_ZERO_S 1U +#define LGPT_RIS_ZERO_SET 0x00000002U +#define LGPT_RIS_ZERO_CLR 0x00000000U + +// Field: [0] TGT +// +// Status of the TGT interrupt. The interrupt is set when CNTR = TGT. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_RIS_TGT 0x00000001U +#define LGPT_RIS_TGT_M 0x00000001U +#define LGPT_RIS_TGT_S 0U +#define LGPT_RIS_TGT_SET 0x00000001U +#define LGPT_RIS_TGT_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_MIS +// +//***************************************************************************** +// Field: [10] C2CC +// +// Masked status of the RIS.C2CC interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_C2CC 0x00000400U +#define LGPT_MIS_C2CC_M 0x00000400U +#define LGPT_MIS_C2CC_S 10U +#define LGPT_MIS_C2CC_SET 0x00000400U +#define LGPT_MIS_C2CC_CLR 0x00000000U + +// Field: [9] C1CC +// +// Masked status of the RIS.C1CC interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_C1CC 0x00000200U +#define LGPT_MIS_C1CC_M 0x00000200U +#define LGPT_MIS_C1CC_S 9U +#define LGPT_MIS_C1CC_SET 0x00000200U +#define LGPT_MIS_C1CC_CLR 0x00000000U + +// Field: [8] C0CC +// +// Masked status of the RIS.C0CC interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_C0CC 0x00000100U +#define LGPT_MIS_C0CC_M 0x00000100U +#define LGPT_MIS_C0CC_S 8U +#define LGPT_MIS_C0CC_SET 0x00000100U +#define LGPT_MIS_C0CC_CLR 0x00000000U + +// Field: [6] FAULT +// +// Masked status of the RIS.FAULT interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_FAULT 0x00000040U +#define LGPT_MIS_FAULT_M 0x00000040U +#define LGPT_MIS_FAULT_S 6U +#define LGPT_MIS_FAULT_SET 0x00000040U +#define LGPT_MIS_FAULT_CLR 0x00000000U + +// Field: [5] IDX +// +// Masked status of the RIS.IDX interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_IDX 0x00000020U +#define LGPT_MIS_IDX_M 0x00000020U +#define LGPT_MIS_IDX_S 5U +#define LGPT_MIS_IDX_SET 0x00000020U +#define LGPT_MIS_IDX_CLR 0x00000000U + +// Field: [4] DIRCHNG +// +// Masked status of the RIS.DIRCHNG interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_DIRCHNG 0x00000010U +#define LGPT_MIS_DIRCHNG_M 0x00000010U +#define LGPT_MIS_DIRCHNG_S 4U +#define LGPT_MIS_DIRCHNG_SET 0x00000010U +#define LGPT_MIS_DIRCHNG_CLR 0x00000000U + +// Field: [3] CNTRCHNG +// +// Masked status of the RIS.CNTRCHNG interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_CNTRCHNG 0x00000008U +#define LGPT_MIS_CNTRCHNG_M 0x00000008U +#define LGPT_MIS_CNTRCHNG_S 3U +#define LGPT_MIS_CNTRCHNG_SET 0x00000008U +#define LGPT_MIS_CNTRCHNG_CLR 0x00000000U + +// Field: [2] DBLTRANS +// +// Masked status of the RIS.DBLTRANS interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_DBLTRANS 0x00000004U +#define LGPT_MIS_DBLTRANS_M 0x00000004U +#define LGPT_MIS_DBLTRANS_S 2U +#define LGPT_MIS_DBLTRANS_SET 0x00000004U +#define LGPT_MIS_DBLTRANS_CLR 0x00000000U + +// Field: [1] ZERO +// +// Masked status of the RIS.ZERO interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_ZERO 0x00000002U +#define LGPT_MIS_ZERO_M 0x00000002U +#define LGPT_MIS_ZERO_S 1U +#define LGPT_MIS_ZERO_SET 0x00000002U +#define LGPT_MIS_ZERO_CLR 0x00000000U + +// Field: [0] TGT +// +// Masked status of the RIS.TGT interrupt. +// ENUMs: +// SET +// CLR Cleared +#define LGPT_MIS_TGT 0x00000001U +#define LGPT_MIS_TGT_M 0x00000001U +#define LGPT_MIS_TGT_S 0U +#define LGPT_MIS_TGT_SET 0x00000001U +#define LGPT_MIS_TGT_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_ISET +// +//***************************************************************************** +// Field: [10] C2CC +// +// Set the RIS.C2CC interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_C2CC 0x00000400U +#define LGPT_ISET_C2CC_M 0x00000400U +#define LGPT_ISET_C2CC_S 10U +#define LGPT_ISET_C2CC_SET 0x00000400U +#define LGPT_ISET_C2CC_NO_EFFECT 0x00000000U + +// Field: [9] C1CC +// +// Set the RIS.C1CC interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_C1CC 0x00000200U +#define LGPT_ISET_C1CC_M 0x00000200U +#define LGPT_ISET_C1CC_S 9U +#define LGPT_ISET_C1CC_SET 0x00000200U +#define LGPT_ISET_C1CC_NO_EFFECT 0x00000000U + +// Field: [8] C0CC +// +// Set the RIS.C0CC interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_C0CC 0x00000100U +#define LGPT_ISET_C0CC_M 0x00000100U +#define LGPT_ISET_C0CC_S 8U +#define LGPT_ISET_C0CC_SET 0x00000100U +#define LGPT_ISET_C0CC_NO_EFFECT 0x00000000U + +// Field: [6] FAULT +// +// Set the RIS.FAULT interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_FAULT 0x00000040U +#define LGPT_ISET_FAULT_M 0x00000040U +#define LGPT_ISET_FAULT_S 6U +#define LGPT_ISET_FAULT_SET 0x00000040U +#define LGPT_ISET_FAULT_NO_EFFECT 0x00000000U + +// Field: [5] IDX +// +// Set the RIS.IDX interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_IDX 0x00000020U +#define LGPT_ISET_IDX_M 0x00000020U +#define LGPT_ISET_IDX_S 5U +#define LGPT_ISET_IDX_SET 0x00000020U +#define LGPT_ISET_IDX_NO_EFFECT 0x00000000U + +// Field: [4] DIRCHNG +// +// Set the RIS.DIRCHNG interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_DIRCHNG 0x00000010U +#define LGPT_ISET_DIRCHNG_M 0x00000010U +#define LGPT_ISET_DIRCHNG_S 4U +#define LGPT_ISET_DIRCHNG_SET 0x00000010U +#define LGPT_ISET_DIRCHNG_NO_EFFECT 0x00000000U + +// Field: [3] CNTRCHNG +// +// Set the RIS.CNTRCHNG interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_CNTRCHNG 0x00000008U +#define LGPT_ISET_CNTRCHNG_M 0x00000008U +#define LGPT_ISET_CNTRCHNG_S 3U +#define LGPT_ISET_CNTRCHNG_SET 0x00000008U +#define LGPT_ISET_CNTRCHNG_NO_EFFECT 0x00000000U + +// Field: [2] DBLTRANS +// +// Set the RIS.DBLTRANS interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_DBLTRANS 0x00000004U +#define LGPT_ISET_DBLTRANS_M 0x00000004U +#define LGPT_ISET_DBLTRANS_S 2U +#define LGPT_ISET_DBLTRANS_SET 0x00000004U +#define LGPT_ISET_DBLTRANS_NO_EFFECT 0x00000000U + +// Field: [1] ZERO +// +// Set the RIS.ZERO interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_ZERO 0x00000002U +#define LGPT_ISET_ZERO_M 0x00000002U +#define LGPT_ISET_ZERO_S 1U +#define LGPT_ISET_ZERO_SET 0x00000002U +#define LGPT_ISET_ZERO_NO_EFFECT 0x00000000U + +// Field: [0] TGT +// +// Set the RIS.TGT interrupt. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_ISET_TGT 0x00000001U +#define LGPT_ISET_TGT_M 0x00000001U +#define LGPT_ISET_TGT_S 0U +#define LGPT_ISET_TGT_SET 0x00000001U +#define LGPT_ISET_TGT_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_ICLR +// +//***************************************************************************** +// Field: [10] C2CC +// +// Clear the RIS.C2CC interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_C2CC 0x00000400U +#define LGPT_ICLR_C2CC_M 0x00000400U +#define LGPT_ICLR_C2CC_S 10U +#define LGPT_ICLR_C2CC_CLR 0x00000400U +#define LGPT_ICLR_C2CC_NO_EFFECT 0x00000000U + +// Field: [9] C1CC +// +// Clear the RIS.C1CC interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_C1CC 0x00000200U +#define LGPT_ICLR_C1CC_M 0x00000200U +#define LGPT_ICLR_C1CC_S 9U +#define LGPT_ICLR_C1CC_CLR 0x00000200U +#define LGPT_ICLR_C1CC_NO_EFFECT 0x00000000U + +// Field: [8] C0CC +// +// Clear the RIS.C0CC interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_C0CC 0x00000100U +#define LGPT_ICLR_C0CC_M 0x00000100U +#define LGPT_ICLR_C0CC_S 8U +#define LGPT_ICLR_C0CC_CLR 0x00000100U +#define LGPT_ICLR_C0CC_NO_EFFECT 0x00000000U + +// Field: [6] FAULT +// +// Clear the RIS.FAULT interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_FAULT 0x00000040U +#define LGPT_ICLR_FAULT_M 0x00000040U +#define LGPT_ICLR_FAULT_S 6U +#define LGPT_ICLR_FAULT_CLR 0x00000040U +#define LGPT_ICLR_FAULT_NO_EFFECT 0x00000000U + +// Field: [5] IDX +// +// Clear the RIS.IDX interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_IDX 0x00000020U +#define LGPT_ICLR_IDX_M 0x00000020U +#define LGPT_ICLR_IDX_S 5U +#define LGPT_ICLR_IDX_CLR 0x00000020U +#define LGPT_ICLR_IDX_NO_EFFECT 0x00000000U + +// Field: [4] DIRCHNG +// +// Clear the RIS.DIRCHNG interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_DIRCHNG 0x00000010U +#define LGPT_ICLR_DIRCHNG_M 0x00000010U +#define LGPT_ICLR_DIRCHNG_S 4U +#define LGPT_ICLR_DIRCHNG_CLR 0x00000010U +#define LGPT_ICLR_DIRCHNG_NO_EFFECT 0x00000000U + +// Field: [3] CNTRCHNG +// +// Clear the RIS.CNTRCHNG interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_CNTRCHNG 0x00000008U +#define LGPT_ICLR_CNTRCHNG_M 0x00000008U +#define LGPT_ICLR_CNTRCHNG_S 3U +#define LGPT_ICLR_CNTRCHNG_CLR 0x00000008U +#define LGPT_ICLR_CNTRCHNG_NO_EFFECT 0x00000000U + +// Field: [2] DBLTRANS +// +// Clear the RIS.DBLTRANS interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_DBLTRANS 0x00000004U +#define LGPT_ICLR_DBLTRANS_M 0x00000004U +#define LGPT_ICLR_DBLTRANS_S 2U +#define LGPT_ICLR_DBLTRANS_CLR 0x00000004U +#define LGPT_ICLR_DBLTRANS_NO_EFFECT 0x00000000U + +// Field: [1] ZERO +// +// Clear the RIS.ZERO interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_ZERO 0x00000002U +#define LGPT_ICLR_ZERO_M 0x00000002U +#define LGPT_ICLR_ZERO_S 1U +#define LGPT_ICLR_ZERO_CLR 0x00000002U +#define LGPT_ICLR_ZERO_NO_EFFECT 0x00000000U + +// Field: [0] TGT +// +// Clear the RIS.TGT interrupt. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_ICLR_TGT 0x00000001U +#define LGPT_ICLR_TGT_M 0x00000001U +#define LGPT_ICLR_TGT_S 0U +#define LGPT_ICLR_TGT_CLR 0x00000001U +#define LGPT_ICLR_TGT_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_IMSET +// +//***************************************************************************** +// Field: [10] C2CC +// +// Set the MIS.C2CC mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_C2CC 0x00000400U +#define LGPT_IMSET_C2CC_M 0x00000400U +#define LGPT_IMSET_C2CC_S 10U +#define LGPT_IMSET_C2CC_SET 0x00000400U +#define LGPT_IMSET_C2CC_NO_EFFECT 0x00000000U + +// Field: [9] C1CC +// +// Set the MIS.C1CC mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_C1CC 0x00000200U +#define LGPT_IMSET_C1CC_M 0x00000200U +#define LGPT_IMSET_C1CC_S 9U +#define LGPT_IMSET_C1CC_SET 0x00000200U +#define LGPT_IMSET_C1CC_NO_EFFECT 0x00000000U + +// Field: [8] C0CC +// +// Set the MIS.C0CC mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_C0CC 0x00000100U +#define LGPT_IMSET_C0CC_M 0x00000100U +#define LGPT_IMSET_C0CC_S 8U +#define LGPT_IMSET_C0CC_SET 0x00000100U +#define LGPT_IMSET_C0CC_NO_EFFECT 0x00000000U + +// Field: [6] FAULT +// +// Set the MIS.FAULT mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_FAULT 0x00000040U +#define LGPT_IMSET_FAULT_M 0x00000040U +#define LGPT_IMSET_FAULT_S 6U +#define LGPT_IMSET_FAULT_SET 0x00000040U +#define LGPT_IMSET_FAULT_NO_EFFECT 0x00000000U + +// Field: [5] IDX +// +// Set the MIS.IDX mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_IDX 0x00000020U +#define LGPT_IMSET_IDX_M 0x00000020U +#define LGPT_IMSET_IDX_S 5U +#define LGPT_IMSET_IDX_SET 0x00000020U +#define LGPT_IMSET_IDX_NO_EFFECT 0x00000000U + +// Field: [4] DIRCHNG +// +// Set the MIS.DIRCHNG mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_DIRCHNG 0x00000010U +#define LGPT_IMSET_DIRCHNG_M 0x00000010U +#define LGPT_IMSET_DIRCHNG_S 4U +#define LGPT_IMSET_DIRCHNG_SET 0x00000010U +#define LGPT_IMSET_DIRCHNG_NO_EFFECT 0x00000000U + +// Field: [3] CNTRCHNG +// +// Set the MIS.CNTRCHNG mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_CNTRCHNG 0x00000008U +#define LGPT_IMSET_CNTRCHNG_M 0x00000008U +#define LGPT_IMSET_CNTRCHNG_S 3U +#define LGPT_IMSET_CNTRCHNG_SET 0x00000008U +#define LGPT_IMSET_CNTRCHNG_NO_EFFECT 0x00000000U + +// Field: [2] DBLTRANS +// +// Set the MIS.DBLTRANS mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_DBLTRANS 0x00000004U +#define LGPT_IMSET_DBLTRANS_M 0x00000004U +#define LGPT_IMSET_DBLTRANS_S 2U +#define LGPT_IMSET_DBLTRANS_SET 0x00000004U +#define LGPT_IMSET_DBLTRANS_NO_EFFECT 0x00000000U + +// Field: [1] ZERO +// +// Set the MIS.ZERO mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_ZERO 0x00000002U +#define LGPT_IMSET_ZERO_M 0x00000002U +#define LGPT_IMSET_ZERO_S 1U +#define LGPT_IMSET_ZERO_SET 0x00000002U +#define LGPT_IMSET_ZERO_NO_EFFECT 0x00000000U + +// Field: [0] TGT +// +// Set the MIS.TGT mask. +// ENUMs: +// SET +// NO_EFFECT No effect +#define LGPT_IMSET_TGT 0x00000001U +#define LGPT_IMSET_TGT_M 0x00000001U +#define LGPT_IMSET_TGT_S 0U +#define LGPT_IMSET_TGT_SET 0x00000001U +#define LGPT_IMSET_TGT_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_IMCLR +// +//***************************************************************************** +// Field: [10] C2CC +// +// Clear the MIS.C2CC mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_C2CC 0x00000400U +#define LGPT_IMCLR_C2CC_M 0x00000400U +#define LGPT_IMCLR_C2CC_S 10U +#define LGPT_IMCLR_C2CC_CLR 0x00000400U +#define LGPT_IMCLR_C2CC_NO_EFFECT 0x00000000U + +// Field: [9] C1CC +// +// Clear the MIS.C1CC mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_C1CC 0x00000200U +#define LGPT_IMCLR_C1CC_M 0x00000200U +#define LGPT_IMCLR_C1CC_S 9U +#define LGPT_IMCLR_C1CC_CLR 0x00000200U +#define LGPT_IMCLR_C1CC_NO_EFFECT 0x00000000U + +// Field: [8] C0CC +// +// Clear the MIS.C0CC mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_C0CC 0x00000100U +#define LGPT_IMCLR_C0CC_M 0x00000100U +#define LGPT_IMCLR_C0CC_S 8U +#define LGPT_IMCLR_C0CC_CLR 0x00000100U +#define LGPT_IMCLR_C0CC_NO_EFFECT 0x00000000U + +// Field: [6] FAULT +// +// Clear the MIS.FAULT mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_FAULT 0x00000040U +#define LGPT_IMCLR_FAULT_M 0x00000040U +#define LGPT_IMCLR_FAULT_S 6U +#define LGPT_IMCLR_FAULT_CLR 0x00000040U +#define LGPT_IMCLR_FAULT_NO_EFFECT 0x00000000U + +// Field: [5] IDX +// +// Clear the MIS.IDX mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_IDX 0x00000020U +#define LGPT_IMCLR_IDX_M 0x00000020U +#define LGPT_IMCLR_IDX_S 5U +#define LGPT_IMCLR_IDX_CLR 0x00000020U +#define LGPT_IMCLR_IDX_NO_EFFECT 0x00000000U + +// Field: [4] DIRCHNG +// +// Clear the MIS.DIRCHNG mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_DIRCHNG 0x00000010U +#define LGPT_IMCLR_DIRCHNG_M 0x00000010U +#define LGPT_IMCLR_DIRCHNG_S 4U +#define LGPT_IMCLR_DIRCHNG_CLR 0x00000010U +#define LGPT_IMCLR_DIRCHNG_NO_EFFECT 0x00000000U + +// Field: [3] CNTRCHNG +// +// Clear the MIS.CNTRCHNG mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_CNTRCHNG 0x00000008U +#define LGPT_IMCLR_CNTRCHNG_M 0x00000008U +#define LGPT_IMCLR_CNTRCHNG_S 3U +#define LGPT_IMCLR_CNTRCHNG_CLR 0x00000008U +#define LGPT_IMCLR_CNTRCHNG_NO_EFFECT 0x00000000U + +// Field: [2] DBLTRANS +// +// Clear the MIS.DBLTRANS mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_DBLTRANS 0x00000004U +#define LGPT_IMCLR_DBLTRANS_M 0x00000004U +#define LGPT_IMCLR_DBLTRANS_S 2U +#define LGPT_IMCLR_DBLTRANS_CLR 0x00000004U +#define LGPT_IMCLR_DBLTRANS_NO_EFFECT 0x00000000U + +// Field: [1] ZERO +// +// Clear the MIS.ZERO mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_ZERO 0x00000002U +#define LGPT_IMCLR_ZERO_M 0x00000002U +#define LGPT_IMCLR_ZERO_S 1U +#define LGPT_IMCLR_ZERO_CLR 0x00000002U +#define LGPT_IMCLR_ZERO_NO_EFFECT 0x00000000U + +// Field: [0] TGT +// +// Clear the MIS.TGT mask. +// ENUMs: +// CLR Clear +// NO_EFFECT No effect +#define LGPT_IMCLR_TGT 0x00000001U +#define LGPT_IMCLR_TGT_M 0x00000001U +#define LGPT_IMCLR_TGT_S 0U +#define LGPT_IMCLR_TGT_CLR 0x00000001U +#define LGPT_IMCLR_TGT_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_EMU +// +//***************************************************************************** +// Field: [1] CTL +// +// Halt control. +// +// Configure when the counter shall stop upon CPU halt. This bitfield only +// applies if HALT = 1. +// ENUMs: +// ZERCOND Zero condition. The counter stops when CNTR = 0. +// IMMEDIATE Immediate reaction. The counter stops immediately +// on debug halt. +#define LGPT_EMU_CTL 0x00000002U +#define LGPT_EMU_CTL_M 0x00000002U +#define LGPT_EMU_CTL_S 1U +#define LGPT_EMU_CTL_ZERCOND 0x00000002U +#define LGPT_EMU_CTL_IMMEDIATE 0x00000000U + +// Field: [0] HALT +// +// Halt LGPT when CPU is halted in debug. +// ENUMs: +// EN Enable. +// DIS Disable. +#define LGPT_EMU_HALT 0x00000001U +#define LGPT_EMU_HALT_M 0x00000001U +#define LGPT_EMU_HALT_S 0U +#define LGPT_EMU_HALT_EN 0x00000001U +#define LGPT_EMU_HALT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_C0CFG +// +//***************************************************************************** +// Field: [10] OUT2 +// +// Output 2 enable. +// +// When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 0 controls output 2. +// DIS Channel 0 does not control output 2. +#define LGPT_C0CFG_OUT2 0x00000400U +#define LGPT_C0CFG_OUT2_M 0x00000400U +#define LGPT_C0CFG_OUT2_S 10U +#define LGPT_C0CFG_OUT2_EN 0x00000400U +#define LGPT_C0CFG_OUT2_DIS 0x00000000U + +// Field: [9] OUT1 +// +// Output 1 enable. +// +// When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 0 controls output 1. +// DIS Channel 0 does not control output 1. +#define LGPT_C0CFG_OUT1 0x00000200U +#define LGPT_C0CFG_OUT1_M 0x00000200U +#define LGPT_C0CFG_OUT1_S 9U +#define LGPT_C0CFG_OUT1_EN 0x00000200U +#define LGPT_C0CFG_OUT1_DIS 0x00000000U + +// Field: [8] OUT0 +// +// Output 0 enable. +// +// When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 0 controls output 0. +// DIS Channel 0 does not control output 0. +#define LGPT_C0CFG_OUT0 0x00000100U +#define LGPT_C0CFG_OUT0_M 0x00000100U +#define LGPT_C0CFG_OUT0_S 8U +#define LGPT_C0CFG_OUT0_EN 0x00000100U +#define LGPT_C0CFG_OUT0_DIS 0x00000000U + +// Field: [6] INPUT +// +// Select channel input. +// ENUMs: +// IO IO controller +// EV Event fabric +#define LGPT_C0CFG_INPUT 0x00000040U +#define LGPT_C0CFG_INPUT_M 0x00000040U +#define LGPT_C0CFG_INPUT_S 6U +#define LGPT_C0CFG_INPUT_IO 0x00000040U +#define LGPT_C0CFG_INPUT_EV 0x00000000U + +// Field: [5:4] EDGE +// +// Determines the edge that triggers the channel input event. This happens post +// filter. +// ENUMs: +// BOTH Input event is triggered at both edges. +// FALL Input event is triggered at falling edge. +// RISE Input event is triggered at rising edge. +// NONE Input is turned off. +#define LGPT_C0CFG_EDGE_W 2U +#define LGPT_C0CFG_EDGE_M 0x00000030U +#define LGPT_C0CFG_EDGE_S 4U +#define LGPT_C0CFG_EDGE_BOTH 0x00000030U +#define LGPT_C0CFG_EDGE_FALL 0x00000020U +#define LGPT_C0CFG_EDGE_RISE 0x00000010U +#define LGPT_C0CFG_EDGE_NONE 0x00000000U + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. In every compare event the timer looks at +// the current value of CNTR. The corresponding output event will be set 1 +// timer period after CNTR = C0CC. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C0CC.VAL = CNTR.VAL. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C0CC.VAL = CNTR.VAL. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C0CC.VAL = CNTR.VAL. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When C0CC.VAL <= TGT.VAL: +// Duty cycle = C0CC.VAL +// / ( TGT.VAL + 1 ). +// +// When C0CC.VAL > TGT.VAL: +// Duty cycle = 1. +// +// Enabled outputs are +// cleared when C0CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When C0CC.VAL <= TGT.VAL: +// Duty cycle = 1 - ( +// C0CC.VAL / TGT.VAL ). +// +// When C0CC.VAL > TGT.VAL: +// Duty cycle = 0. +// +// Enabled outputs are set +// when C0CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C0CC.VAL. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by INPUT relative to the signal edge given by +// EDGE. +// +// Set enabled outputs and +// RIS.C0CC when C0CC.VAL contains signal period +// and PC0CC.VAL contains signal pulse width. +// +// Notes: +// - Make sure to configure +// INPUT and CCACT when CTL.MODE equals DIS, then +// set CTL.MODE to UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when C0CC.VAL contains +// the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - To observe a timeout +// event the RIS.TGT interrupt can be used, or +// another channel can be configured to SET_ON_CMP +// with compare value equal TGT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.TICKDIV ) * timer clock period. +// - Signal Period <= +// MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock +// period. +// - Signal low and high +// phase >= (1 + PRECFG.TICKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are +// cleared when C0CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C0CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are set +// when C0CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C0CC.VAL. +// - Disable channel. +// +// Primary use scenario is +// to select this function before starting the +// timer. +// Follow these steps to +// select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no output enable. +// - Configure INPUT +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before +// setting CCACT to SET_ON_CAPT_DIS. Output enable +// is optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define LGPT_C0CFG_CCACT_W 4U +#define LGPT_C0CFG_CCACT_M 0x0000000FU +#define LGPT_C0CFG_CCACT_S 0U +#define LGPT_C0CFG_CCACT_PULSE_ON_CMP 0x0000000FU +#define LGPT_C0CFG_CCACT_TGL_ON_CMP 0x0000000EU +#define LGPT_C0CFG_CCACT_SET_ON_CMP 0x0000000DU +#define LGPT_C0CFG_CCACT_CLR_ON_CMP 0x0000000CU +#define LGPT_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU +#define LGPT_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU +#define LGPT_C0CFG_CCACT_SET_ON_CAPT 0x00000009U +#define LGPT_C0CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U +#define LGPT_C0CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U +#define LGPT_C0CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U +#define LGPT_C0CFG_CCACT_SET_ON_CMP_DIS 0x00000005U +#define LGPT_C0CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U +#define LGPT_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U +#define LGPT_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U +#define LGPT_C0CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U +#define LGPT_C0CFG_CCACT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_C1CFG +// +//***************************************************************************** +// Field: [10] OUT2 +// +// Output 2 enable. +// +// When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 1 controls output 2. +// DIS Channel 1 does not control output 2. +#define LGPT_C1CFG_OUT2 0x00000400U +#define LGPT_C1CFG_OUT2_M 0x00000400U +#define LGPT_C1CFG_OUT2_S 10U +#define LGPT_C1CFG_OUT2_EN 0x00000400U +#define LGPT_C1CFG_OUT2_DIS 0x00000000U + +// Field: [9] OUT1 +// +// Output 1 enable. +// +// When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 1 controls output 1. +// DIS Channel 1 does not control output 1. +#define LGPT_C1CFG_OUT1 0x00000200U +#define LGPT_C1CFG_OUT1_M 0x00000200U +#define LGPT_C1CFG_OUT1_S 9U +#define LGPT_C1CFG_OUT1_EN 0x00000200U +#define LGPT_C1CFG_OUT1_DIS 0x00000000U + +// Field: [8] OUT0 +// +// Output 0 enable. +// When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 1 controls output 0. +// DIS Channel 1 does not control output 0. +#define LGPT_C1CFG_OUT0 0x00000100U +#define LGPT_C1CFG_OUT0_M 0x00000100U +#define LGPT_C1CFG_OUT0_S 8U +#define LGPT_C1CFG_OUT0_EN 0x00000100U +#define LGPT_C1CFG_OUT0_DIS 0x00000000U + +// Field: [6] INPUT +// +// Select channel input. +// ENUMs: +// IO IO controller +// EV Event fabric +#define LGPT_C1CFG_INPUT 0x00000040U +#define LGPT_C1CFG_INPUT_M 0x00000040U +#define LGPT_C1CFG_INPUT_S 6U +#define LGPT_C1CFG_INPUT_IO 0x00000040U +#define LGPT_C1CFG_INPUT_EV 0x00000000U + +// Field: [5:4] EDGE +// +// Determines the edge that triggers the channel input event. This happens post +// filter. +// ENUMs: +// BOTH Input event is triggered at both edges. +// FALL Input event is triggered at falling edge. +// RISE Input event is triggered at rising edge. +// NONE Input is turned off. +#define LGPT_C1CFG_EDGE_W 2U +#define LGPT_C1CFG_EDGE_M 0x00000030U +#define LGPT_C1CFG_EDGE_S 4U +#define LGPT_C1CFG_EDGE_BOTH 0x00000030U +#define LGPT_C1CFG_EDGE_FALL 0x00000020U +#define LGPT_C1CFG_EDGE_RISE 0x00000010U +#define LGPT_C1CFG_EDGE_NONE 0x00000000U + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. In every compare event the timer looks at +// the current value of CNTR. The corresponding output event will be set 1 +// timer period after CNTR = C1CC. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C1CC.VAL = CNTR.VAL. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C1CC.VAL = CNTR.VAL. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C1CC.VAL = CNTR.VAL. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When C1CC.VAL <= TGT.VAL: +// Duty cycle = C1CC.VAL +// / ( TGT.VAL + 1 ). +// +// When C1CC.VAL > TGT.VAL: +// Duty cycle = 1. +// +// Enabled outputs are +// cleared when C1CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When C1CC.VAL <= TGT.VAL: +// Duty cycle = 1 - ( +// C1CC.VAL / TGT.VAL ). +// +// When C1CC.VAL > TGT.VAL: +// Duty cycle = 0. +// +// Enabled outputs are set +// when C1CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C1CC.VAL. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by INPUT relative to the signal edge given by +// EDGE. +// +// Set enabled outputs and +// RIS.C1CC when C1CC.VAL contains signal period +// and PC1CC.VAL contains signal pulse width. +// +// Notes: +// - Make sure to configure +// INPUT and CCACT when CTL.MODE equals DIS, then +// set CTL.MODE to UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when C1CC.VAL contains +// the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - To observe a timeout +// event the RIS.TGT interrupt can be used, or +// another channel can be configured to SET_ON_CMP +// with compare value equal TGT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.TICKDIV ) * timer clock period. +// - Signal Period <= +// MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock +// period. +// - Signal low and high +// phase >= (1 + PRECFG.TICKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are +// cleared when C1CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C1CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are set +// when C1CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C1CC.VAL. +// - Disable channel. +// +// Primary use scenario is +// to select this function before starting the +// timer. +// Follow these steps to +// select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no output enable. +// - Configure INPUT +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before +// setting CCACT to SET_ON_CAPT_DIS. Output enable +// is optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define LGPT_C1CFG_CCACT_W 4U +#define LGPT_C1CFG_CCACT_M 0x0000000FU +#define LGPT_C1CFG_CCACT_S 0U +#define LGPT_C1CFG_CCACT_PULSE_ON_CMP 0x0000000FU +#define LGPT_C1CFG_CCACT_TGL_ON_CMP 0x0000000EU +#define LGPT_C1CFG_CCACT_SET_ON_CMP 0x0000000DU +#define LGPT_C1CFG_CCACT_CLR_ON_CMP 0x0000000CU +#define LGPT_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU +#define LGPT_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU +#define LGPT_C1CFG_CCACT_SET_ON_CAPT 0x00000009U +#define LGPT_C1CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U +#define LGPT_C1CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U +#define LGPT_C1CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U +#define LGPT_C1CFG_CCACT_SET_ON_CMP_DIS 0x00000005U +#define LGPT_C1CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U +#define LGPT_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U +#define LGPT_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U +#define LGPT_C1CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U +#define LGPT_C1CFG_CCACT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_C2CFG +// +//***************************************************************************** +// Field: [10] OUT2 +// +// Output 2 enable. +// +// When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 2 controls output 2. +// DIS Channel 2 does not control output 2. +#define LGPT_C2CFG_OUT2 0x00000400U +#define LGPT_C2CFG_OUT2_M 0x00000400U +#define LGPT_C2CFG_OUT2_S 10U +#define LGPT_C2CFG_OUT2_EN 0x00000400U +#define LGPT_C2CFG_OUT2_DIS 0x00000000U + +// Field: [9] OUT1 +// +// Output 1 enable. +// +// When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 2 controls output 1. +// DIS Channel 2 does not control output 1. +#define LGPT_C2CFG_OUT1 0x00000200U +#define LGPT_C2CFG_OUT1_M 0x00000200U +#define LGPT_C2CFG_OUT1_S 9U +#define LGPT_C2CFG_OUT1_EN 0x00000200U +#define LGPT_C2CFG_OUT1_DIS 0x00000000U + +// Field: [8] OUT0 +// +// Output 0 enable. +// +// When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. +// ENUMs: +// EN Channel 2 controls output 0. +// DIS Channel 2 does not control output 0. +#define LGPT_C2CFG_OUT0 0x00000100U +#define LGPT_C2CFG_OUT0_M 0x00000100U +#define LGPT_C2CFG_OUT0_S 8U +#define LGPT_C2CFG_OUT0_EN 0x00000100U +#define LGPT_C2CFG_OUT0_DIS 0x00000000U + +// Field: [6] INPUT +// +// Select channel input. +// ENUMs: +// IO IO controller +// EV Event fabric +#define LGPT_C2CFG_INPUT 0x00000040U +#define LGPT_C2CFG_INPUT_M 0x00000040U +#define LGPT_C2CFG_INPUT_S 6U +#define LGPT_C2CFG_INPUT_IO 0x00000040U +#define LGPT_C2CFG_INPUT_EV 0x00000000U + +// Field: [5:4] EDGE +// +// Determines the edge that triggers the channel input event. This happens post +// filter. +// ENUMs: +// BOTH Input event is triggered at both edges. +// FALL Input event is triggered at falling edge. +// RISE Input event is triggered at rising edge. +// NONE Input is turned off. +#define LGPT_C2CFG_EDGE_W 2U +#define LGPT_C2CFG_EDGE_M 0x00000030U +#define LGPT_C2CFG_EDGE_S 4U +#define LGPT_C2CFG_EDGE_BOTH 0x00000030U +#define LGPT_C2CFG_EDGE_FALL 0x00000020U +#define LGPT_C2CFG_EDGE_RISE 0x00000010U +#define LGPT_C2CFG_EDGE_NONE 0x00000000U + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. In every compare event the timer looks at +// the current value of CNTR. The corresponding output event will be set 1 +// timer period after CNTR = C2CC. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C2CC.VAL = CNTR.VAL. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C2CC.VAL = CNTR.VAL. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C2CC.VAL = CNTR.VAL. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When C2CC.VAL <= TGT.VAL: +// Duty cycle = C2CC.VAL +// / ( TGT.VAL + 1 ). +// +// When C2CC.VAL > TGT.VAL: +// Duty cycle = 1. +// +// Enabled outputs are +// cleared when C2CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When C2CC.VAL <= TGT.VAL: +// Duty cycle = 1 - ( +// C2CC.VAL / TGT.VAL ). +// +// When C2CC.VAL > TGT.VAL: +// Duty cycle = 0. +// +// Enabled outputs are set +// when C2CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C2CC.VAL. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by INPUT relative to the signal edge given by +// EDGE. +// +// Set enabled outputs and +// RIS.C2CC when C2CC.VAL contains signal period +// and PC2CC.VAL contains signal pulse width. +// +// Notes: +// - Make sure to configure +// INPUT and CCACT when CTL.MODE equals DIS, then +// set CTL.MODE to UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when C2CC.VAL contains +// the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - To observe a timeout +// event the RIS.TGT interrupt can be used, or +// another channel can be configured to SET_ON_CMP +// with compare value equal TGT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.TICKDIV ) * timer clock period. +// - Signal Period <= +// MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock +// period. +// - Signal low and high +// phase >= (1 + PRECFG.TICKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// +// The output is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are +// cleared when C2CC.VAL = 0 and CNTR.VAL = 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled outputs +// when CNTR.VAL = 0. +// - Toggle enabled outputs +// when C2CC.VAL = CNTR.VAL. +// - Disable channel. +// +// Enabled outputs are set +// when C2CC.VAL = 0 and CNTR.VAL = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled outputs on +// capture event and copy CNTR.VAL to C2CC.VAL. +// - Disable channel. +// +// Primary use scenario is +// to select this function before starting the +// timer. +// Follow these steps to +// select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no output enable. +// - Configure INPUT +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before +// setting CCACT to SET_ON_CAPT_DIS. Output enable +// is optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define LGPT_C2CFG_CCACT_W 4U +#define LGPT_C2CFG_CCACT_M 0x0000000FU +#define LGPT_C2CFG_CCACT_S 0U +#define LGPT_C2CFG_CCACT_PULSE_ON_CMP 0x0000000FU +#define LGPT_C2CFG_CCACT_TGL_ON_CMP 0x0000000EU +#define LGPT_C2CFG_CCACT_SET_ON_CMP 0x0000000DU +#define LGPT_C2CFG_CCACT_CLR_ON_CMP 0x0000000CU +#define LGPT_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU +#define LGPT_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU +#define LGPT_C2CFG_CCACT_SET_ON_CAPT 0x00000009U +#define LGPT_C2CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U +#define LGPT_C2CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U +#define LGPT_C2CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U +#define LGPT_C2CFG_CCACT_SET_ON_CMP_DIS 0x00000005U +#define LGPT_C2CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U +#define LGPT_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U +#define LGPT_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U +#define LGPT_C2CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U +#define LGPT_C2CFG_CCACT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT_O_PTGT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// The pipleline target value. +#define LGPT_PTGT_VAL_W 16U +#define LGPT_PTGT_VAL_M 0x0000FFFFU +#define LGPT_PTGT_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC0CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C0CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C0CFG.EDGE. +#define LGPT_PC0CC_VAL_W 16U +#define LGPT_PC0CC_VAL_M 0x0000FFFFU +#define LGPT_PC0CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC1CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C1CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C1CFG.EDGE. +#define LGPT_PC1CC_VAL_W 16U +#define LGPT_PC1CC_VAL_M 0x0000FFFFU +#define LGPT_PC1CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC2CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C2CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C2CFG.EDGE. +#define LGPT_PC2CC_VAL_W 16U +#define LGPT_PC2CC_VAL_M 0x0000FFFFU +#define LGPT_PC2CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_TGT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// User defined counter target value. +#define LGPT_TGT_VAL_W 16U +#define LGPT_TGT_VAL_M 0x0000FFFFU +#define LGPT_TGT_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C0CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C0CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C0CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C0CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C0CC_VAL_W 16U +#define LGPT_C0CC_VAL_M 0x0000FFFFU +#define LGPT_C0CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C1CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C1CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C1CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C1CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C1CC_VAL_W 16U +#define LGPT_C1CC_VAL_M 0x0000FFFFU +#define LGPT_C1CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C2CC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C2CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C2CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C2CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C2CC_VAL_W 16U +#define LGPT_C2CC_VAL_M 0x0000FFFFU +#define LGPT_C2CC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PTGTNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// A read or write to this register will not clear the RIS.TGT interrupt. +// +// If CTL.MODE != QDEC. +// Target value for next counter period. +// The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not +// happen when restarting the timer. +// This is useful to avoid period jitter in PWM applications with time-varying +// period, sometimes referenced as phase corrected PWM. +// +// If CTL.MODE = QDEC. +// The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when +// CNTR.VAL becomes 0. +#define LGPT_PTGTNC_VAL_W 16U +#define LGPT_PTGTNC_VAL_M 0x0000FFFFU +#define LGPT_PTGTNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC0CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C0CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C0CFG.EDGE. +#define LGPT_PC0CCNC_VAL_W 16U +#define LGPT_PC0CCNC_VAL_M 0x0000FFFFU +#define LGPT_PC0CCNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC1CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C1CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C1CFG.EDGE. +#define LGPT_PC1CCNC_VAL_W 16U +#define LGPT_PC1CCNC_VAL_M 0x0000FFFFU +#define LGPT_PC1CCNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_PC2CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C2CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C2CFG.EDGE. +#define LGPT_PC2CCNC_VAL_W 16U +#define LGPT_PC2CCNC_VAL_M 0x0000FFFFU +#define LGPT_PC2CCNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_TGTNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// User defined counter target value. +#define LGPT_TGTNC_VAL_W 16U +#define LGPT_TGTNC_VAL_M 0x0000FFFFU +#define LGPT_TGTNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C0CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C0CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C0CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C0CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C0CCNC_VAL_W 16U +#define LGPT_C0CCNC_VAL_M 0x0000FFFFU +#define LGPT_C0CCNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C1CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C1CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C1CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C1CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C1CCNC_VAL_W 16U +#define LGPT_C1CCNC_VAL_M 0x0000FFFFU +#define LGPT_C1CCNC_VAL_S 0U + +//***************************************************************************** +// +// Register: LGPT_O_C2CCNC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C2CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C2CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C2CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT_C2CCNC_VAL_W 16U +#define LGPT_C2CCNC_VAL_M 0x0000FFFFU +#define LGPT_C2CCNC_VAL_S 0U + + +#endif // __LGPT__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt1.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt1.h new file mode 100644 index 00000000..a749b69a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt1.h @@ -0,0 +1,316 @@ +/****************************************************************************** +* Filename: hw_lgpt1_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LGPT1_H__ +#define __HW_LGPT1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LGPT1 component +// +//***************************************************************************** +// Description Register. +// Description Extended +// Start Configuration +// Timer Control +// Output Control +// Counter +// Clock Prescaler Configuration +// Prescaler Event +// Channel Input Filter +// Fault +// Park +// Dead Band Delay +// Dead Band Control +// Direct Memory Accsess +// Direct Memory Access +// ADC Trigger +// IO Controller +// Interrupt mask. +// Raw interrupt status. +// Masked interrupt status. +// Interrupt set register. +// Interrupt clear register. +// Interrupt mask set register. +// Interrupt mask clear register. +// Debug control +// Channel 0 Configuration +// Channel 1 Configuration +// Channel 2 Configuration +// Pipeline Target +// Pipeline Channel 0 Capture Compare +// Pipeline Channel 1 Capture Compare +// Pipeline Channel 2 Capture Compare +// Target +// Channel 0 Capture Compare +// Channel 1 Capture Compare +// Channel 2 Capture Compare +// Pipeline Target No Clear +// Pipeline Channel 0 Capture Compare No Clear +// Pipeline Channel 1 Capture Compare No Clear +// Pipeline Channel 2 Capture Compare No Clear +// Target No Clear +// Channel 0 Capture Compare No Clear +// Channel 1 Capture Compare No Clear +// Channel 2 Capture Compare No Clear +#define LGPT1_O_FAULT 0x00000024U +#define LGPT1_O_PARK 0x00000028U +#define LGPT1_O_DBDLY 0x0000002CU +#define LGPT1_O_DBCTL 0x00000030U + +//***************************************************************************** +// +// Register: LGPT1_O_FAULT +// +//***************************************************************************** +// Field: [1:0] CTL +// +// Fault control +// +// On active fault input the counter can optionally stop. If the counter stops +// this is done by hardware, software must then restart the timer if wanted. +// The fault input overrides channel 0 IOC input when CTL != DIS. +// This means that channel 0 receives fault as input signal when C0CFG.INPUT = +// IO and CTL != DIS. +// +// CHFILT can be used to avoid glitching on the fault input. Fault is level +// triggered, the polarity is set by the C0CFG.EDGE field. Here C0CFG.EDGE = +// RISE gives active high and C0CFG.EDGE = FALL gives active low polarity. +// +// Fault is typically used together with PARK to stop the PWM signal to an +// external motor control circuit safely. Configure PARK to ensure predefined +// values of the PWM outputs. +// +// If CTL != DIS the RIS.FAULT interrupt is set immediately when the fault +// input is active while CTL.MODE != DIS. +// +// The three modes of fault is described below: +// +// CTL = IMMEDIATE +// In this mode the counter stops immediately on an active fault input. This is +// done by hardware by setting CTL.MODE = DIS. To start the counter software +// must set CTL.MODE != DIS. +// When the counter has stopped, the input synchronizers and the channel filter +// is not running. This means that if RIS.FAULT is cleared it will not be set +// again while CTL.MODE = DIS. +// +// CTL = ZEROCOND +// In this mode the counter stops when CNTR = 0 after an active fault input. If +// the RIS.FAULT interrupt has been cleared by software before CNTR = 0, and +// the fault input is inactive, the counter will continue as normal. +// When the counter stops on zero, it can be started again by clearing the +// RIS.FAULT interrupt if the fault input is inactive. To change the counter +// mode set CTL.MODE = DIS, clear the RIS.FAULT interrupt, then start timer in +// wanted mode. +// +// CTL = IRQ +// In this mode only the RIS.FAULT flag is set on an active fault input. +// ENUMs: +// IRQ Interrupt request. Only set RIS.FAULT on active +// fault. +// ZERCOND Zero condition. The counter stops when CNTR = 0. +// IMMEDIATE Immediate reaction. The counter stops immediately +// on fault. +// DIS Disable. The timer ignores fault. +#define LGPT1_FAULT_CTL_W 2U +#define LGPT1_FAULT_CTL_M 0x00000003U +#define LGPT1_FAULT_CTL_S 0U +#define LGPT1_FAULT_CTL_IRQ 0x00000003U +#define LGPT1_FAULT_CTL_ZERCOND 0x00000002U +#define LGPT1_FAULT_CTL_IMMEDIATE 0x00000001U +#define LGPT1_FAULT_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT1_O_PARK +// +//***************************************************************************** +// Field: [7] IOCPS2 +// +// IO Complementary Park State 2 +// +// Park state for IO Complementary output 2. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [6] IOPS2 +// +// IO Park State 2 +// +// Park state for IO output 2. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [5] IOCPS1 +// +// IO Complementary Park State 1 +// +// Park state for IO Complementary output 1. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [4] IOPS1 +// +// IO Park State 1 +// +// Park state for IO output 1. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [3] IOCPS0 +// +// IO Complementary Park State 0 +// +// Park state for IO Complementary output 0. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [2] IOPS0 +// +// IO Park State 0 +// +// Park state for IO output 0. +// ENUMs: +// HIGH Output is set high in park mode. +// LOW Output is set low in park mode. +// Field: [1:0] CTL +// +// Park Control. +// ENUMs: +// BOTH Enter parkmode on fault or debug. +// DEBUG Enter park mode on debug. +// FAULT Enter park mode on fault. +// DIS Disable park mode. +#define LGPT1_PARK_IOCPS2 0x00000080U +#define LGPT1_PARK_IOCPS2_M 0x00000080U +#define LGPT1_PARK_IOCPS2_S 7U +#define LGPT1_PARK_IOCPS2_HIGH 0x00000080U +#define LGPT1_PARK_IOCPS2_LOW 0x00000000U +#define LGPT1_PARK_IOPS2 0x00000040U +#define LGPT1_PARK_IOPS2_M 0x00000040U +#define LGPT1_PARK_IOPS2_S 6U +#define LGPT1_PARK_IOPS2_HIGH 0x00000040U +#define LGPT1_PARK_IOPS2_LOW 0x00000000U +#define LGPT1_PARK_IOCPS1 0x00000020U +#define LGPT1_PARK_IOCPS1_M 0x00000020U +#define LGPT1_PARK_IOCPS1_S 5U +#define LGPT1_PARK_IOCPS1_HIGH 0x00000020U +#define LGPT1_PARK_IOCPS1_LOW 0x00000000U +#define LGPT1_PARK_IOPS1 0x00000010U +#define LGPT1_PARK_IOPS1_M 0x00000010U +#define LGPT1_PARK_IOPS1_S 4U +#define LGPT1_PARK_IOPS1_HIGH 0x00000010U +#define LGPT1_PARK_IOPS1_LOW 0x00000000U +#define LGPT1_PARK_IOCPS0 0x00000008U +#define LGPT1_PARK_IOCPS0_M 0x00000008U +#define LGPT1_PARK_IOCPS0_S 3U +#define LGPT1_PARK_IOCPS0_HIGH 0x00000008U +#define LGPT1_PARK_IOCPS0_LOW 0x00000000U +#define LGPT1_PARK_IOPS0 0x00000004U +#define LGPT1_PARK_IOPS0_M 0x00000004U +#define LGPT1_PARK_IOPS0_S 2U +#define LGPT1_PARK_IOPS0_HIGH 0x00000004U +#define LGPT1_PARK_IOPS0_LOW 0x00000000U +#define LGPT1_PARK_CTL_W 2U +#define LGPT1_PARK_CTL_M 0x00000003U +#define LGPT1_PARK_CTL_S 0U +#define LGPT1_PARK_CTL_BOTH 0x00000003U +#define LGPT1_PARK_CTL_DEBUG 0x00000002U +#define LGPT1_PARK_CTL_FAULT 0x00000001U +#define LGPT1_PARK_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LGPT1_O_DBDLY +// +//***************************************************************************** +// Field: [27:16] FALLDLY +// +// Fall delay. +// +// The number of system clock periods inserted between the fall of the dead +// band reference signal and the rise of the inverted output signal. +// Field: [11:0] RISEDLY +// +// Rise delay. +// +// The number of system clock periods inserted between the rise of the dead +// band reference signal and the rise of the output signal. +#define LGPT1_DBDLY_FALLDLY_W 12U +#define LGPT1_DBDLY_FALLDLY_M 0x0FFF0000U +#define LGPT1_DBDLY_FALLDLY_S 16U +#define LGPT1_DBDLY_RISEDLY_W 12U +#define LGPT1_DBDLY_RISEDLY_M 0x00000FFFU +#define LGPT1_DBDLY_RISEDLY_S 0U + +//***************************************************************************** +// +// Register: LGPT1_O_DBCTL +// +//***************************************************************************** +// Field: [2] IO2 +// +// Enable dead band on IO and IO complementary output 2. +// ENUMs: +// EN Enable +// DIS Disable +// Field: [1] IO1 +// +// Enable dead band on IO and IO complementary output 1. +// ENUMs: +// EN Enable +// DIS Disable +// Field: [0] IO0 +// +// Enable dead band on IO and IO complementary output 0. +// ENUMs: +// EN Enable +// DIS Disable +#define LGPT1_DBCTL_IO2 0x00000004U +#define LGPT1_DBCTL_IO2_M 0x00000004U +#define LGPT1_DBCTL_IO2_S 2U +#define LGPT1_DBCTL_IO2_EN 0x00000004U +#define LGPT1_DBCTL_IO2_DIS 0x00000000U +#define LGPT1_DBCTL_IO1 0x00000002U +#define LGPT1_DBCTL_IO1_M 0x00000002U +#define LGPT1_DBCTL_IO1_S 1U +#define LGPT1_DBCTL_IO1_EN 0x00000002U +#define LGPT1_DBCTL_IO1_DIS 0x00000000U +#define LGPT1_DBCTL_IO0 0x00000001U +#define LGPT1_DBCTL_IO0_M 0x00000001U +#define LGPT1_DBCTL_IO0_S 0U +#define LGPT1_DBCTL_IO0_EN 0x00000001U +#define LGPT1_DBCTL_IO0_DIS 0x00000000U + + +#endif // __LGPT1__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt3.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt3.h new file mode 100644 index 00000000..01c18d27 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lgpt3.h @@ -0,0 +1,407 @@ +/****************************************************************************** +* Filename: hw_lgpt3_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LGPT3_H__ +#define __HW_LGPT3_H__ + +//***************************************************************************** +// +// Register: LGPT3_O_CNTR +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Current counter value. +// If CTL.MODE = QDEC this can be used to set the initial counter value during +// QDEC. Writing to CNTR in other modes than QDEC is possible, but may result +// in unpredictable behavior. +#define LGPT3_CNTR_VAL_W 24U +#define LGPT3_CNTR_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_DMARW +// +//***************************************************************************** +// Field: [23:0] VAL +// +// DMA read write value. +// +// The value that is read/written from/to the registers. +#define LGPT3_DMARW_VAL_W 24U +#define LGPT3_DMARW_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PTGT +// +//***************************************************************************** +// Field: [23:0] VAL +// +// The pipleline target value. +#define LGPT3_PTGT_VAL_W 24U +#define LGPT3_PTGT_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC0CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C0CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C0CFG.EDGE. +#define LGPT3_PC0CC_VAL_W 24U +#define LGPT3_PC0CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC1CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C1CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C1CFG.EDGE. +#define LGPT3_PC1CC_VAL_W 24U +#define LGPT3_PC1CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC2CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C2CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C2CFG.EDGE. +#define LGPT3_PC2CC_VAL_W 24U +#define LGPT3_PC2CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_TGT +// +//***************************************************************************** +// Field: [23:0] VAL +// +// User defined counter target value. +#define LGPT3_TGT_VAL_W 24U +#define LGPT3_TGT_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C0CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C0CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C0CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C0CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C0CC_VAL_W 24U +#define LGPT3_C0CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C1CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C1CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C1CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C1CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C1CC_VAL_W 24U +#define LGPT3_C1CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C2CC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will clear the RIS.C2CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C2CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C2CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C2CC_VAL_W 24U +#define LGPT3_C2CC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PTGTNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// A read or write to this register will not clear the RIS.TGT interrupt. +// +// If CTL.MODE != QDEC. +// Target value for next counter period. +// The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not +// happen when restarting the timer. +// This is useful to avoid period jitter in PWM applications with time-varying +// period, sometimes referenced as phase corrected PWM. +// +// If CTL.MODE = QDEC. +// The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when +// CNTR.VAL becomes 0. +#define LGPT3_PTGTNC_VAL_W 24U +#define LGPT3_PTGTNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC0CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C0CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C0CFG.EDGE. +#define LGPT3_PC0CCNC_VAL_W 24U +#define LGPT3_PC0CCNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC1CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C1CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C1CFG.EDGE. +#define LGPT3_PC1CCNC_VAL_W 24U +#define LGPT3_PC1CCNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_PC2CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Pipeline Capture Compare value. +// +// User defined pipeline compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C2CC interrupt. +// +// Compare mode: +// An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is +// zero and CTL.MODE is different from DIS. This is useful for PWM generation +// and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of +// the low or high phase of the selected signal. This is specified by +// C2CFG.EDGE. +#define LGPT3_PC2CCNC_VAL_W 24U +#define LGPT3_PC2CCNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_TGTNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// User defined counter target value. +#define LGPT3_TGTNC_VAL_W 24U +#define LGPT3_TGTNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C0CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C0CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C0CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C0CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C0CCNC_VAL_W 24U +#define LGPT3_C0CCNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C1CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C1CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C1CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C1CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C1CCNC_VAL_W 24U +#define LGPT3_C1CCNC_VAL_M 0x00FFFFFFU + +//***************************************************************************** +// +// Register: LGPT3_O_C2CCNC +// +//***************************************************************************** +// Field: [23:0] VAL +// +// Capture Compare value. +// +// User defined compare value or channel-updated capture value. +// +// A read or write to this register will not clear the RIS.C2CC interrupt. +// +// Compare mode: +// VAL is compared against CNTR.VAL and an event is generated as specified by +// C2CFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VAL when a capture event occurs. +// C2CFG.CCACT determines if VAL is a signal period or a regular capture value. +#define LGPT3_C2CCNC_VAL_W 24U +#define LGPT3_C2CCNC_VAL_M 0x00FFFFFFU + + +#endif // __LGPT3__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h new file mode 100644 index 00000000..f5eef3b3 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h @@ -0,0 +1,6818 @@ +/****************************************************************************** +* Filename: hw_lrfddbell_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDDBELL_H__ +#define __HW_LRFDDBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDDBELL component +// +//***************************************************************************** +// Description +#define LRFDDBELL_O_DESC 0x00000000U + +// Clock control +#define LRFDDBELL_O_CLKCTL 0x00000004U + +// DMA Configuration +#define LRFDDBELL_O_DMACFG 0x00000008U + +// Systimer Output Event Control Register +#define LRFDDBELL_O_SYSTIMOEV 0x0000000CU + +// System DMA Trigger +#define LRFDDBELL_O_SYSTDMATRIG 0x00000010U + +// GPO control +#define LRFDDBELL_O_GPOSEL0 0x00000014U + +// GPO control +#define LRFDDBELL_O_GPOSEL1 0x00000018U + +// Interrupt mask +#define LRFDDBELL_O_IMASK0 0x00000044U + +// Raw interrupt status +#define LRFDDBELL_O_RIS0 0x00000048U + +// Masked interrupt status +#define LRFDDBELL_O_MIS0 0x0000004CU + +// Interrupt set +#define LRFDDBELL_O_ISET0 0x00000050U + +// Interrupt clear +#define LRFDDBELL_O_ICLR0 0x00000054U + +// Interrupt mask +#define LRFDDBELL_O_IMASK1 0x00000084U + +// Raw interrupt status +#define LRFDDBELL_O_RIS1 0x00000088U + +// Masked interrupt status +#define LRFDDBELL_O_MIS1 0x0000008CU + +// Interrupt set +#define LRFDDBELL_O_ISET1 0x00000090U + +// Interrupt clear +#define LRFDDBELL_O_ICLR1 0x00000094U + +// Interrupt mask +#define LRFDDBELL_O_IMASK2 0x000000C4U + +// Raw interrupt status +#define LRFDDBELL_O_RIS2 0x000000C8U + +// Masked interrupt status +#define LRFDDBELL_O_MIS2 0x000000CCU + +// Interrupt set +#define LRFDDBELL_O_ISET2 0x000000D0U + +// Interrupt clear +#define LRFDDBELL_O_ICLR2 0x000000D4U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODULEID +// +// Module identifier used to uniquely identify this IP. +#define LRFDDBELL_DESC_MODULEID_W 16U +#define LRFDDBELL_DESC_MODULEID_M 0xFFFF0000U +#define LRFDDBELL_DESC_MODULEID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// ENUMs: +// STDIPMMR These MMRs begin at offset 64*STDIPOFF from IP +// base address +// NO_STDIPMMR STDIP MMRs do not exist +#define LRFDDBELL_DESC_STDIPOFF_W 4U +#define LRFDDBELL_DESC_STDIPOFF_M 0x0000F000U +#define LRFDDBELL_DESC_STDIPOFF_S 12U +#define LRFDDBELL_DESC_STDIPOFF_STDIPMMR 0x00001000U +#define LRFDDBELL_DESC_STDIPOFF_NO_STDIPMMR 0x00000000U + +// Field: [11:8] INSTNUM +// +// IP Instance Number. If multiple instances of IP exist in the device, this +// field can identify the instance number +#define LRFDDBELL_DESC_INSTNUM_W 4U +#define LRFDDBELL_DESC_INSTNUM_M 0x00000F00U +#define LRFDDBELL_DESC_INSTNUM_S 8U + +// Field: [7:4] MAJREV +// +// Major rev of the IP +#define LRFDDBELL_DESC_MAJREV_W 4U +#define LRFDDBELL_DESC_MAJREV_M 0x000000F0U +#define LRFDDBELL_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor rev of the IP +#define LRFDDBELL_DESC_MINREV_W 4U +#define LRFDDBELL_DESC_MINREV_M 0x0000000FU +#define LRFDDBELL_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_CLKCTL +// +//***************************************************************************** +// Field: [13] DEM +// +// Enable the clock to the demodulator. The modem will request this clock +// automatically. This bit is to force the clock to be free running +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_DEM 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_M 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_S 13U +#define LRFDDBELL_CLKCTL_DEM_EN 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_DIS 0x00000000U + +// Field: [12] MOD +// +// Enable the clock to the modulator. Modem will request this clock +// automatically, this bit is to force the modulator clock to be free running. +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MOD 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_M 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_S 12U +#define LRFDDBELL_CLKCTL_MOD_EN 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_DIS 0x00000000U + +// Field: [11] S2RRAM +// +// Enable the clock to the S2R RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_S2RRAM 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_M 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_S 11U +#define LRFDDBELL_CLKCTL_S2RRAM_EN 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_DIS 0x00000000U + +// Field: [10] BUFRAM +// +// Enable the clock to the BUFRAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_BUFRAM 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_M 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_S 10U +#define LRFDDBELL_CLKCTL_BUFRAM_EN 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_DIS 0x00000000U + +// Field: [9] DSBRAM +// +// Enable the clock to the DSB RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_DSBRAM 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_M 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_S 9U +#define LRFDDBELL_CLKCTL_DSBRAM_EN 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_DIS 0x00000000U + +// Field: [8] RFERAM +// +// Enable the clock to the RFE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_RFERAM 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_M 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_S 8U +#define LRFDDBELL_CLKCTL_RFERAM_EN 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_DIS 0x00000000U + +// Field: [7] MCERAM +// +// Enable the clock to the MCE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MCERAM 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_M 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_S 7U +#define LRFDDBELL_CLKCTL_MCERAM_EN 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_DIS 0x00000000U + +// Field: [6] PBERAM +// +// Enable the clock to the PBE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_PBERAM 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_M 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_S 6U +#define LRFDDBELL_CLKCTL_PBERAM_EN 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_DIS 0x00000000U + +// Field: [5] TRC +// +// Enable the clock to the Tracer +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_TRC 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_M 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_S 5U +#define LRFDDBELL_CLKCTL_TRC_EN 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_DIS 0x00000000U + +// Field: [4] S2R +// +// Enable the clock to Samples2RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_S2R 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_M 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_S 4U +#define LRFDDBELL_CLKCTL_S2R_EN 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_DIS 0x00000000U + +// Field: [3] RFE +// +// Enable the clock to the RFE +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_RFE 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_M 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_S 3U +#define LRFDDBELL_CLKCTL_RFE_EN 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_DIS 0x00000000U + +// Field: [2] MDM +// +// Enable the clock to the Modem +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MDM 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_M 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_S 2U +#define LRFDDBELL_CLKCTL_MDM_EN 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_DIS 0x00000000U + +// Field: [1] PBE +// +// Enable the clock to the PBE +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_PBE 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_M 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_S 1U +#define LRFDDBELL_CLKCTL_PBE_EN 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_DIS 0x00000000U + +// Field: [0] BRIDGE +// +// Clock enable to AHB bridge. The bridge will request it's own clock, this bit +// it to override that feature to have a free running clock. +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_BRIDGE 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_M 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_S 0U +#define LRFDDBELL_CLKCTL_BRIDGE_EN 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_DMACFG +// +//***************************************************************************** +// Field: [2:1] TRIGSRC +// +// Select DMA trigger source +// ENUMs: +// FIFO The DMA is triggered from the FIFO. See the FIFO +// configration register for what FIFO event will +// generate the trigger +// RFEFW The DMA is triggered by the MCE FW trigger +// MCEFW The DMA is triggered by the MCE FW trigger +// PBEFW The DMA is triggered by the PBE FW trigger +#define LRFDDBELL_DMACFG_TRIGSRC_W 2U +#define LRFDDBELL_DMACFG_TRIGSRC_M 0x00000006U +#define LRFDDBELL_DMACFG_TRIGSRC_S 1U +#define LRFDDBELL_DMACFG_TRIGSRC_FIFO 0x00000006U +#define LRFDDBELL_DMACFG_TRIGSRC_RFEFW 0x00000004U +#define LRFDDBELL_DMACFG_TRIGSRC_MCEFW 0x00000002U +#define LRFDDBELL_DMACFG_TRIGSRC_PBEFW 0x00000000U + +// Field: [0] EN +// +// Enables the DMA interface +// ENUMs: +// ON Enable DMA interface. The triggers are able to +// give activity on the interface +// OFF Disable DMA interface, no activity on interface +#define LRFDDBELL_DMACFG_EN 0x00000001U +#define LRFDDBELL_DMACFG_EN_M 0x00000001U +#define LRFDDBELL_DMACFG_EN_S 0U +#define LRFDDBELL_DMACFG_EN_ON 0x00000001U +#define LRFDDBELL_DMACFG_EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_SYSTIMOEV +// +//***************************************************************************** +// Field: [11:8] SRC2 +// +// Select source of systimer output event 2 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC2_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC2_M 0x00000F00U +#define LRFDDBELL_SYSTIMOEV_SRC2_S 8U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM2 0x00000C00U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM1 0x00000B00U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM0 0x00000A00U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW2 0x00000900U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW1 0x00000800U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW0 0x00000700U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM2 0x00000600U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM1 0x00000500U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM0 0x00000400U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM2 0x00000300U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM1 0x00000200U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM0 0x00000100U +#define LRFDDBELL_SYSTIMOEV_SRC2_DIS 0x00000000U + +// Field: [7:4] SRC1 +// +// Select source of systimer output event 1 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC1_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC1_M 0x000000F0U +#define LRFDDBELL_SYSTIMOEV_SRC1_S 4U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM2 0x000000C0U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM1 0x000000B0U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM0 0x000000A0U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW2 0x00000090U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW1 0x00000080U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW0 0x00000070U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM2 0x00000060U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM1 0x00000050U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM0 0x00000040U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM2 0x00000030U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM1 0x00000020U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM0 0x00000010U +#define LRFDDBELL_SYSTIMOEV_SRC1_DIS 0x00000000U + +// Field: [3:0] SRC0 +// +// Select source of systimer output event 0 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC0_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC0_M 0x0000000FU +#define LRFDDBELL_SYSTIMOEV_SRC0_S 0U +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM2 0x0000000CU +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM1 0x0000000BU +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM0 0x0000000AU +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW2 0x00000009U +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW1 0x00000008U +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW0 0x00000007U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM2 0x00000006U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM1 0x00000005U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM0 0x00000004U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM2 0x00000003U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM1 0x00000002U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM0 0x00000001U +#define LRFDDBELL_SYSTIMOEV_SRC0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_SYSTDMATRIG +// +//***************************************************************************** +// Field: [3] DMA +// +// Trigger a DMA request from the Radio +// ENUMs: +// TRIG DMA request manually triggered +// NOTRIG DMA not manually triggered +#define LRFDDBELL_SYSTDMATRIG_DMA 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_M 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_S 3U +#define LRFDDBELL_SYSTDMATRIG_DMA_TRIG 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_NOTRIG 0x00000000U + +// Field: [2] SYST2 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST2 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_M 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_S 2U +#define LRFDDBELL_SYSTDMATRIG_SYST2_TRIG 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_NOTRIG 0x00000000U + +// Field: [1] SYST1 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST1 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_M 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_S 1U +#define LRFDDBELL_SYSTDMATRIG_SYST1_TRIG 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_NOTRIG 0x00000000U + +// Field: [0] SYST0 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST0 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_M 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_S 0U +#define LRFDDBELL_SYSTDMATRIG_SYST0_TRIG 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_NOTRIG 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_GPOSEL0 +// +//***************************************************************************** +// Field: [28:24] SRC3 +// +// Select source of radio GPO line 3 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 3 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC3_W 5U +#define LRFDDBELL_GPOSEL0_SRC3_M 0x1F000000U +#define LRFDDBELL_GPOSEL0_SRC3_S 24U +#define LRFDDBELL_GPOSEL0_SRC3_RFCTRC 0x19000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO7 0x18000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO6 0x17000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO5 0x16000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO4 0x15000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO3 0x14000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO2 0x13000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO1 0x12000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO0 0x11000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO7 0x10000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO6 0x0F000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO5 0x0E000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO4 0x0D000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO3 0x0C000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO2 0x0B000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO1 0x0A000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO0 0x09000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO7 0x08000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO6 0x07000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO5 0x06000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO4 0x05000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO3 0x04000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO2 0x03000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO1 0x02000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO0 0x01000000U +#define LRFDDBELL_GPOSEL0_SRC3_DIS 0x00000000U + +// Field: [20:16] SRC2 +// +// Select source of radio GPO line 2 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 2 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC2_W 5U +#define LRFDDBELL_GPOSEL0_SRC2_M 0x001F0000U +#define LRFDDBELL_GPOSEL0_SRC2_S 16U +#define LRFDDBELL_GPOSEL0_SRC2_RFCTRC 0x00190000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO7 0x00180000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO6 0x00170000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO5 0x00160000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO4 0x00150000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO3 0x00140000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO2 0x00130000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO1 0x00120000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO0 0x00110000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO7 0x00100000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO6 0x000F0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO5 0x000E0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO4 0x000D0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO3 0x000C0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO2 0x000B0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO1 0x000A0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO0 0x00090000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO7 0x00080000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO6 0x00070000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO5 0x00060000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO4 0x00050000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO3 0x00040000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO2 0x00030000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO1 0x00020000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO0 0x00010000U +#define LRFDDBELL_GPOSEL0_SRC2_DIS 0x00000000U + +// Field: [12:8] SRC1 +// +// Select source of radio GPO line 1 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 1 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC1_W 5U +#define LRFDDBELL_GPOSEL0_SRC1_M 0x00001F00U +#define LRFDDBELL_GPOSEL0_SRC1_S 8U +#define LRFDDBELL_GPOSEL0_SRC1_RFCTRC 0x00001900U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO7 0x00001800U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO6 0x00001700U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO5 0x00001600U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO4 0x00001500U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO3 0x00001400U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO2 0x00001300U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO1 0x00001200U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO0 0x00001100U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO7 0x00001000U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO6 0x00000F00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO5 0x00000E00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO4 0x00000D00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO3 0x00000C00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO2 0x00000B00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO1 0x00000A00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO0 0x00000900U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO7 0x00000800U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO6 0x00000700U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO5 0x00000600U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO4 0x00000500U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO3 0x00000400U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO2 0x00000300U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO1 0x00000200U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO0 0x00000100U +#define LRFDDBELL_GPOSEL0_SRC1_DIS 0x00000000U + +// Field: [4:0] SRC0 +// +// Select source of radio GPO line 0 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 0 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC0_W 5U +#define LRFDDBELL_GPOSEL0_SRC0_M 0x0000001FU +#define LRFDDBELL_GPOSEL0_SRC0_S 0U +#define LRFDDBELL_GPOSEL0_SRC0_RFCTRC 0x00000019U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO7 0x00000018U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO6 0x00000017U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO5 0x00000016U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO4 0x00000015U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO3 0x00000014U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO2 0x00000013U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO1 0x00000012U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO0 0x00000011U +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO7 0x00000010U +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO6 0x0000000FU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO5 0x0000000EU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO4 0x0000000DU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO3 0x0000000CU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO2 0x0000000BU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO1 0x0000000AU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO0 0x00000009U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO7 0x00000008U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO6 0x00000007U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO5 0x00000006U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO4 0x00000005U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO3 0x00000004U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO2 0x00000003U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO1 0x00000002U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO0 0x00000001U +#define LRFDDBELL_GPOSEL0_SRC0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_GPOSEL1 +// +//***************************************************************************** +// Field: [28:24] SRC7 +// +// Select source of radio GPO line 7 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 7 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC7_W 5U +#define LRFDDBELL_GPOSEL1_SRC7_M 0x1F000000U +#define LRFDDBELL_GPOSEL1_SRC7_S 24U +#define LRFDDBELL_GPOSEL1_SRC7_RFCTRC 0x19000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO7 0x18000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO6 0x17000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO5 0x16000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO4 0x15000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO3 0x14000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO2 0x13000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO1 0x12000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO0 0x11000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO7 0x10000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO6 0x0F000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO5 0x0E000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO4 0x0D000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO3 0x0C000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO2 0x0B000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO1 0x0A000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO0 0x09000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO7 0x08000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO6 0x07000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO5 0x06000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO4 0x05000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO3 0x04000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO2 0x03000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO1 0x02000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO0 0x01000000U +#define LRFDDBELL_GPOSEL1_SRC7_DIS 0x00000000U + +// Field: [20:16] SRC6 +// +// Select source of radio GPO line 6 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 6 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Selevt RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC6_W 5U +#define LRFDDBELL_GPOSEL1_SRC6_M 0x001F0000U +#define LRFDDBELL_GPOSEL1_SRC6_S 16U +#define LRFDDBELL_GPOSEL1_SRC6_RFCTRC 0x00190000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO7 0x00180000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO6 0x00170000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO5 0x00160000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO4 0x00150000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO3 0x00140000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO2 0x00130000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO1 0x00120000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO0 0x00110000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO7 0x00100000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO6 0x000F0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO5 0x000E0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO4 0x000D0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO3 0x000C0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO2 0x000B0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO1 0x000A0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO0 0x00090000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO7 0x00080000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO6 0x00070000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO5 0x00060000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO4 0x00050000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO3 0x00040000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO2 0x00030000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO1 0x00020000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO0 0x00010000U +#define LRFDDBELL_GPOSEL1_SRC6_DIS 0x00000000U + +// Field: [12:8] SRC5 +// +// Select source of radio GPO line 5 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 5 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC5_W 5U +#define LRFDDBELL_GPOSEL1_SRC5_M 0x00001F00U +#define LRFDDBELL_GPOSEL1_SRC5_S 8U +#define LRFDDBELL_GPOSEL1_SRC5_RFCTRC 0x00001900U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO7 0x00001800U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO6 0x00001700U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO5 0x00001600U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO4 0x00001500U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO3 0x00001400U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO2 0x00001300U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO1 0x00001200U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO0 0x00001100U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO7 0x00001000U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO6 0x00000F00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO5 0x00000E00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO4 0x00000D00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO3 0x00000C00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO2 0x00000B00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO1 0x00000A00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO0 0x00000900U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO7 0x00000800U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO6 0x00000700U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO5 0x00000600U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO4 0x00000500U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO3 0x00000400U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO2 0x00000300U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO1 0x00000200U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO0 0x00000100U +#define LRFDDBELL_GPOSEL1_SRC5_DIS 0x00000000U + +// Field: [4:0] SRC4 +// +// Select source of radio GPO line 4 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 4 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC4_W 5U +#define LRFDDBELL_GPOSEL1_SRC4_M 0x0000001FU +#define LRFDDBELL_GPOSEL1_SRC4_S 0U +#define LRFDDBELL_GPOSEL1_SRC4_RFCTRC 0x00000019U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO7 0x00000018U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO6 0x00000017U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO5 0x00000016U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO4 0x00000015U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO3 0x00000014U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO2 0x00000013U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO1 0x00000012U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO0 0x00000011U +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO7 0x00000010U +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO6 0x0000000FU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO5 0x0000000EU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO4 0x0000000DU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO3 0x0000000CU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO2 0x0000000BU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO1 0x0000000AU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO0 0x00000009U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO7 0x00000008U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO6 0x00000007U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO5 0x00000006U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO4 0x00000005U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO3 0x00000004U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO2 0x00000003U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO1 0x00000002U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO0 0x00000001U +#define LRFDDBELL_GPOSEL1_SRC4_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM2 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_S 31U +#define LRFDDBELL_IMASK0_SYSTIM2_EN 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_DIS 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM1 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_S 30U +#define LRFDDBELL_IMASK0_SYSTIM1_EN 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_DIS 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM0 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_S 29U +#define LRFDDBELL_IMASK0_SYSTIM0_EN 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_DIS 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMDONE 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_M 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_S 28U +#define LRFDDBELL_IMASK0_MDMDONE_EN 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_DIS 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMIN 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_M 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_S 27U +#define LRFDDBELL_IMASK0_MDMIN_EN 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_DIS 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMOUT 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_M 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_S 26U +#define LRFDDBELL_IMASK0_MDMOUT_EN 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_DIS 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT2 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_S 25U +#define LRFDDBELL_IMASK0_MDMSOFT2_EN 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_DIS 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT1 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_S 24U +#define LRFDDBELL_IMASK0_MDMSOFT1_EN 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_DIS 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT0 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_S 23U +#define LRFDDBELL_IMASK0_MDMSOFT0_EN 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_DIS 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFEDONE 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_M 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_S 22U +#define LRFDDBELL_IMASK0_RFEDONE_EN 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_DIS 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFESOFT1 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_S 21U +#define LRFDDBELL_IMASK0_RFESOFT1_EN 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_DIS 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFESOFT0 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_S 20U +#define LRFDDBELL_IMASK0_RFESOFT0_EN 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_DIS 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_LOCK 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_M 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_S 19U +#define LRFDDBELL_IMASK0_LOCK_EN 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_DIS 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_LOL 0x00040000U +#define LRFDDBELL_IMASK0_LOL_M 0x00040000U +#define LRFDDBELL_IMASK0_LOL_S 18U +#define LRFDDBELL_IMASK0_LOL_EN 0x00040000U +#define LRFDDBELL_IMASK0_LOL_DIS 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_TXFIFO 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_M 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_S 17U +#define LRFDDBELL_IMASK0_TXFIFO_EN 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_DIS 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RXFIFO 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_S 16U +#define LRFDDBELL_IMASK0_RXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_DIS 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE15 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_M 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_S 15U +#define LRFDDBELL_IMASK0_PBE15_EN 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_DIS 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE14 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_M 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_S 14U +#define LRFDDBELL_IMASK0_PBE14_EN 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_DIS 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE13 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_M 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_S 13U +#define LRFDDBELL_IMASK0_PBE13_EN 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_DIS 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE12 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_M 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_S 12U +#define LRFDDBELL_IMASK0_PBE12_EN 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_DIS 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE11 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_M 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_S 11U +#define LRFDDBELL_IMASK0_PBE11_EN 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_DIS 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE10 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_M 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_S 10U +#define LRFDDBELL_IMASK0_PBE10_EN 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE8 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_S 8U +#define LRFDDBELL_IMASK0_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE7 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_S 7U +#define LRFDDBELL_IMASK0_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE6 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_S 6U +#define LRFDDBELL_IMASK0_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE5 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_S 5U +#define LRFDDBELL_IMASK0_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE4 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_S 4U +#define LRFDDBELL_IMASK0_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE3 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_S 3U +#define LRFDDBELL_IMASK0_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE2 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_S 2U +#define LRFDDBELL_IMASK0_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE1 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_S 1U +#define LRFDDBELL_IMASK0_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE0 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_S 0U +#define LRFDDBELL_IMASK0_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_S 31U +#define LRFDDBELL_RIS0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_S 30U +#define LRFDDBELL_RIS0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_S 29U +#define LRFDDBELL_RIS0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMDONE 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_S 28U +#define LRFDDBELL_RIS0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMIN 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_S 27U +#define LRFDDBELL_RIS0_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMOUT 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_S 26U +#define LRFDDBELL_RIS0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_S 25U +#define LRFDDBELL_RIS0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_S 24U +#define LRFDDBELL_RIS0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_S 23U +#define LRFDDBELL_RIS0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFEDONE 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_S 22U +#define LRFDDBELL_RIS0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_S 21U +#define LRFDDBELL_RIS0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_S 20U +#define LRFDDBELL_RIS0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_LOCK 0x00080000U +#define LRFDDBELL_RIS0_LOCK_M 0x00080000U +#define LRFDDBELL_RIS0_LOCK_S 19U +#define LRFDDBELL_RIS0_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS0_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_LOL 0x00040000U +#define LRFDDBELL_RIS0_LOL_M 0x00040000U +#define LRFDDBELL_RIS0_LOL_S 18U +#define LRFDDBELL_RIS0_LOL_SET 0x00040000U +#define LRFDDBELL_RIS0_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_TXFIFO 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_S 17U +#define LRFDDBELL_RIS0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RXFIFO 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_S 16U +#define LRFDDBELL_RIS0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE15 0x00008000U +#define LRFDDBELL_RIS0_PBE15_M 0x00008000U +#define LRFDDBELL_RIS0_PBE15_S 15U +#define LRFDDBELL_RIS0_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS0_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE14 0x00004000U +#define LRFDDBELL_RIS0_PBE14_M 0x00004000U +#define LRFDDBELL_RIS0_PBE14_S 14U +#define LRFDDBELL_RIS0_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS0_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE13 0x00002000U +#define LRFDDBELL_RIS0_PBE13_M 0x00002000U +#define LRFDDBELL_RIS0_PBE13_S 13U +#define LRFDDBELL_RIS0_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS0_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE12 0x00001000U +#define LRFDDBELL_RIS0_PBE12_M 0x00001000U +#define LRFDDBELL_RIS0_PBE12_S 12U +#define LRFDDBELL_RIS0_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS0_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE11 0x00000800U +#define LRFDDBELL_RIS0_PBE11_M 0x00000800U +#define LRFDDBELL_RIS0_PBE11_S 11U +#define LRFDDBELL_RIS0_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS0_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE10 0x00000400U +#define LRFDDBELL_RIS0_PBE10_M 0x00000400U +#define LRFDDBELL_RIS0_PBE10_S 10U +#define LRFDDBELL_RIS0_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS0_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE9 0x00000200U +#define LRFDDBELL_RIS0_PBE9_M 0x00000200U +#define LRFDDBELL_RIS0_PBE9_S 9U +#define LRFDDBELL_RIS0_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS0_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE8 0x00000100U +#define LRFDDBELL_RIS0_PBE8_M 0x00000100U +#define LRFDDBELL_RIS0_PBE8_S 8U +#define LRFDDBELL_RIS0_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS0_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE7 0x00000080U +#define LRFDDBELL_RIS0_PBE7_M 0x00000080U +#define LRFDDBELL_RIS0_PBE7_S 7U +#define LRFDDBELL_RIS0_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS0_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE6 0x00000040U +#define LRFDDBELL_RIS0_PBE6_M 0x00000040U +#define LRFDDBELL_RIS0_PBE6_S 6U +#define LRFDDBELL_RIS0_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS0_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE5 0x00000020U +#define LRFDDBELL_RIS0_PBE5_M 0x00000020U +#define LRFDDBELL_RIS0_PBE5_S 5U +#define LRFDDBELL_RIS0_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS0_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE4 0x00000010U +#define LRFDDBELL_RIS0_PBE4_M 0x00000010U +#define LRFDDBELL_RIS0_PBE4_S 4U +#define LRFDDBELL_RIS0_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS0_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE3 0x00000008U +#define LRFDDBELL_RIS0_PBE3_M 0x00000008U +#define LRFDDBELL_RIS0_PBE3_S 3U +#define LRFDDBELL_RIS0_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS0_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE2 0x00000004U +#define LRFDDBELL_RIS0_PBE2_M 0x00000004U +#define LRFDDBELL_RIS0_PBE2_S 2U +#define LRFDDBELL_RIS0_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS0_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE1 0x00000002U +#define LRFDDBELL_RIS0_PBE1_M 0x00000002U +#define LRFDDBELL_RIS0_PBE1_S 1U +#define LRFDDBELL_RIS0_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS0_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE0 0x00000001U +#define LRFDDBELL_RIS0_PBE0_M 0x00000001U +#define LRFDDBELL_RIS0_PBE0_S 0U +#define LRFDDBELL_RIS0_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS0_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_S 31U +#define LRFDDBELL_MIS0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_S 30U +#define LRFDDBELL_MIS0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_S 29U +#define LRFDDBELL_MIS0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMDONE 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_S 28U +#define LRFDDBELL_MIS0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMIN 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_S 27U +#define LRFDDBELL_MIS0_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMOUT 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_S 26U +#define LRFDDBELL_MIS0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_S 25U +#define LRFDDBELL_MIS0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_S 24U +#define LRFDDBELL_MIS0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_S 23U +#define LRFDDBELL_MIS0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFEDONE 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_S 22U +#define LRFDDBELL_MIS0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_S 21U +#define LRFDDBELL_MIS0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_S 20U +#define LRFDDBELL_MIS0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_LOCK 0x00080000U +#define LRFDDBELL_MIS0_LOCK_M 0x00080000U +#define LRFDDBELL_MIS0_LOCK_S 19U +#define LRFDDBELL_MIS0_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS0_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_LOL 0x00040000U +#define LRFDDBELL_MIS0_LOL_M 0x00040000U +#define LRFDDBELL_MIS0_LOL_S 18U +#define LRFDDBELL_MIS0_LOL_SET 0x00040000U +#define LRFDDBELL_MIS0_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_TXFIFO 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_S 17U +#define LRFDDBELL_MIS0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RXFIFO 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_S 16U +#define LRFDDBELL_MIS0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE15 0x00008000U +#define LRFDDBELL_MIS0_PBE15_M 0x00008000U +#define LRFDDBELL_MIS0_PBE15_S 15U +#define LRFDDBELL_MIS0_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS0_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE14 0x00004000U +#define LRFDDBELL_MIS0_PBE14_M 0x00004000U +#define LRFDDBELL_MIS0_PBE14_S 14U +#define LRFDDBELL_MIS0_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS0_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE13 0x00002000U +#define LRFDDBELL_MIS0_PBE13_M 0x00002000U +#define LRFDDBELL_MIS0_PBE13_S 13U +#define LRFDDBELL_MIS0_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS0_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE12 0x00001000U +#define LRFDDBELL_MIS0_PBE12_M 0x00001000U +#define LRFDDBELL_MIS0_PBE12_S 12U +#define LRFDDBELL_MIS0_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS0_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE11 0x00000800U +#define LRFDDBELL_MIS0_PBE11_M 0x00000800U +#define LRFDDBELL_MIS0_PBE11_S 11U +#define LRFDDBELL_MIS0_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS0_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE10 0x00000400U +#define LRFDDBELL_MIS0_PBE10_M 0x00000400U +#define LRFDDBELL_MIS0_PBE10_S 10U +#define LRFDDBELL_MIS0_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS0_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE9 0x00000200U +#define LRFDDBELL_MIS0_PBE9_M 0x00000200U +#define LRFDDBELL_MIS0_PBE9_S 9U +#define LRFDDBELL_MIS0_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS0_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE8 0x00000100U +#define LRFDDBELL_MIS0_PBE8_M 0x00000100U +#define LRFDDBELL_MIS0_PBE8_S 8U +#define LRFDDBELL_MIS0_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS0_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE7 0x00000080U +#define LRFDDBELL_MIS0_PBE7_M 0x00000080U +#define LRFDDBELL_MIS0_PBE7_S 7U +#define LRFDDBELL_MIS0_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS0_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE6 0x00000040U +#define LRFDDBELL_MIS0_PBE6_M 0x00000040U +#define LRFDDBELL_MIS0_PBE6_S 6U +#define LRFDDBELL_MIS0_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS0_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE5 0x00000020U +#define LRFDDBELL_MIS0_PBE5_M 0x00000020U +#define LRFDDBELL_MIS0_PBE5_S 5U +#define LRFDDBELL_MIS0_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS0_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE4 0x00000010U +#define LRFDDBELL_MIS0_PBE4_M 0x00000010U +#define LRFDDBELL_MIS0_PBE4_S 4U +#define LRFDDBELL_MIS0_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS0_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE3 0x00000008U +#define LRFDDBELL_MIS0_PBE3_M 0x00000008U +#define LRFDDBELL_MIS0_PBE3_S 3U +#define LRFDDBELL_MIS0_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS0_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE2 0x00000004U +#define LRFDDBELL_MIS0_PBE2_M 0x00000004U +#define LRFDDBELL_MIS0_PBE2_S 2U +#define LRFDDBELL_MIS0_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS0_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE1 0x00000002U +#define LRFDDBELL_MIS0_PBE1_M 0x00000002U +#define LRFDDBELL_MIS0_PBE1_S 1U +#define LRFDDBELL_MIS0_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS0_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE0 0x00000001U +#define LRFDDBELL_MIS0_PBE0_M 0x00000001U +#define LRFDDBELL_MIS0_PBE0_S 0U +#define LRFDDBELL_MIS0_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS0_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_S 31U +#define LRFDDBELL_ISET0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_S 30U +#define LRFDDBELL_ISET0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_S 29U +#define LRFDDBELL_ISET0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMDONE 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_S 28U +#define LRFDDBELL_ISET0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMIN 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_S 27U +#define LRFDDBELL_ISET0_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMOUT 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_S 26U +#define LRFDDBELL_ISET0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_S 25U +#define LRFDDBELL_ISET0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_S 24U +#define LRFDDBELL_ISET0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_S 23U +#define LRFDDBELL_ISET0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFEDONE 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_S 22U +#define LRFDDBELL_ISET0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_S 21U +#define LRFDDBELL_ISET0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_S 20U +#define LRFDDBELL_ISET0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_LOCK 0x00080000U +#define LRFDDBELL_ISET0_LOCK_M 0x00080000U +#define LRFDDBELL_ISET0_LOCK_S 19U +#define LRFDDBELL_ISET0_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET0_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_LOL 0x00040000U +#define LRFDDBELL_ISET0_LOL_M 0x00040000U +#define LRFDDBELL_ISET0_LOL_S 18U +#define LRFDDBELL_ISET0_LOL_SET 0x00040000U +#define LRFDDBELL_ISET0_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_TXFIFO 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_S 17U +#define LRFDDBELL_ISET0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RXFIFO 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_S 16U +#define LRFDDBELL_ISET0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE15 0x00008000U +#define LRFDDBELL_ISET0_PBE15_M 0x00008000U +#define LRFDDBELL_ISET0_PBE15_S 15U +#define LRFDDBELL_ISET0_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET0_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE14 0x00004000U +#define LRFDDBELL_ISET0_PBE14_M 0x00004000U +#define LRFDDBELL_ISET0_PBE14_S 14U +#define LRFDDBELL_ISET0_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET0_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE13 0x00002000U +#define LRFDDBELL_ISET0_PBE13_M 0x00002000U +#define LRFDDBELL_ISET0_PBE13_S 13U +#define LRFDDBELL_ISET0_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET0_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE12 0x00001000U +#define LRFDDBELL_ISET0_PBE12_M 0x00001000U +#define LRFDDBELL_ISET0_PBE12_S 12U +#define LRFDDBELL_ISET0_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET0_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE11 0x00000800U +#define LRFDDBELL_ISET0_PBE11_M 0x00000800U +#define LRFDDBELL_ISET0_PBE11_S 11U +#define LRFDDBELL_ISET0_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET0_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE10 0x00000400U +#define LRFDDBELL_ISET0_PBE10_M 0x00000400U +#define LRFDDBELL_ISET0_PBE10_S 10U +#define LRFDDBELL_ISET0_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET0_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE9 0x00000200U +#define LRFDDBELL_ISET0_PBE9_M 0x00000200U +#define LRFDDBELL_ISET0_PBE9_S 9U +#define LRFDDBELL_ISET0_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET0_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE8 0x00000100U +#define LRFDDBELL_ISET0_PBE8_M 0x00000100U +#define LRFDDBELL_ISET0_PBE8_S 8U +#define LRFDDBELL_ISET0_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET0_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE7 0x00000080U +#define LRFDDBELL_ISET0_PBE7_M 0x00000080U +#define LRFDDBELL_ISET0_PBE7_S 7U +#define LRFDDBELL_ISET0_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET0_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE6 0x00000040U +#define LRFDDBELL_ISET0_PBE6_M 0x00000040U +#define LRFDDBELL_ISET0_PBE6_S 6U +#define LRFDDBELL_ISET0_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET0_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE5 0x00000020U +#define LRFDDBELL_ISET0_PBE5_M 0x00000020U +#define LRFDDBELL_ISET0_PBE5_S 5U +#define LRFDDBELL_ISET0_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET0_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE4 0x00000010U +#define LRFDDBELL_ISET0_PBE4_M 0x00000010U +#define LRFDDBELL_ISET0_PBE4_S 4U +#define LRFDDBELL_ISET0_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET0_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE3 0x00000008U +#define LRFDDBELL_ISET0_PBE3_M 0x00000008U +#define LRFDDBELL_ISET0_PBE3_S 3U +#define LRFDDBELL_ISET0_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET0_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE2 0x00000004U +#define LRFDDBELL_ISET0_PBE2_M 0x00000004U +#define LRFDDBELL_ISET0_PBE2_S 2U +#define LRFDDBELL_ISET0_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET0_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE1 0x00000002U +#define LRFDDBELL_ISET0_PBE1_M 0x00000002U +#define LRFDDBELL_ISET0_PBE1_S 1U +#define LRFDDBELL_ISET0_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET0_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE0 0x00000001U +#define LRFDDBELL_ISET0_PBE0_M 0x00000001U +#define LRFDDBELL_ISET0_PBE0_S 0U +#define LRFDDBELL_ISET0_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET0_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_S 31U +#define LRFDDBELL_ICLR0_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_S 30U +#define LRFDDBELL_ICLR0_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_S 29U +#define LRFDDBELL_ICLR0_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_S 28U +#define LRFDDBELL_ICLR0_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMIN 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_S 27U +#define LRFDDBELL_ICLR0_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_S 26U +#define LRFDDBELL_ICLR0_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR0_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR0_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR0_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_S 22U +#define LRFDDBELL_ICLR0_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_S 21U +#define LRFDDBELL_ICLR0_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_S 20U +#define LRFDDBELL_ICLR0_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_LOCK 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_S 19U +#define LRFDDBELL_ICLR0_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_LOL 0x00040000U +#define LRFDDBELL_ICLR0_LOL_M 0x00040000U +#define LRFDDBELL_ICLR0_LOL_S 18U +#define LRFDDBELL_ICLR0_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR0_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_S 17U +#define LRFDDBELL_ICLR0_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_S 16U +#define LRFDDBELL_ICLR0_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE15 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_S 15U +#define LRFDDBELL_ICLR0_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE14 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_S 14U +#define LRFDDBELL_ICLR0_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE13 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_S 13U +#define LRFDDBELL_ICLR0_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE12 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_S 12U +#define LRFDDBELL_ICLR0_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE11 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_S 11U +#define LRFDDBELL_ICLR0_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE10 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_S 10U +#define LRFDDBELL_ICLR0_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE9 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_S 9U +#define LRFDDBELL_ICLR0_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE8 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_S 8U +#define LRFDDBELL_ICLR0_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE7 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_S 7U +#define LRFDDBELL_ICLR0_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE6 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_S 6U +#define LRFDDBELL_ICLR0_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE5 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_S 5U +#define LRFDDBELL_ICLR0_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE4 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_S 4U +#define LRFDDBELL_ICLR0_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE3 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_S 3U +#define LRFDDBELL_ICLR0_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE2 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_S 2U +#define LRFDDBELL_ICLR0_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE1 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_S 1U +#define LRFDDBELL_ICLR0_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE0 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_S 0U +#define LRFDDBELL_ICLR0_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK1 +// +//***************************************************************************** +// Field: [30] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM2 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_M 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_S 30U +#define LRFDDBELL_IMASK1_SYSTIM2_EN 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_DIS 0x00000000U + +// Field: [29] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM1 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_M 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_S 29U +#define LRFDDBELL_IMASK1_SYSTIM1_EN 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_DIS 0x00000000U + +// Field: [28] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM0 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_M 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_S 28U +#define LRFDDBELL_IMASK1_SYSTIM0_EN 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_DIS 0x00000000U + +// Field: [27] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMDONE 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_M 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_S 27U +#define LRFDDBELL_IMASK1_MDMDONE_EN 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_DIS 0x00000000U + +// Field: [26] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMIN 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_M 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_S 26U +#define LRFDDBELL_IMASK1_MDMIN_EN 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_DIS 0x00000000U + +// Field: [25] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMOUT 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_M 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_S 25U +#define LRFDDBELL_IMASK1_MDMOUT_EN 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_DIS 0x00000000U + +// Field: [24] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT2 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_M 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_S 24U +#define LRFDDBELL_IMASK1_MDMSOFT2_EN 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_DIS 0x00000000U + +// Field: [23] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT1 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_M 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_S 23U +#define LRFDDBELL_IMASK1_MDMSOFT1_EN 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_DIS 0x00000000U + +// Field: [22] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT0 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_M 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_S 22U +#define LRFDDBELL_IMASK1_MDMSOFT0_EN 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_DIS 0x00000000U + +// Field: [21] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFEDONE 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_M 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_S 21U +#define LRFDDBELL_IMASK1_RFEDONE_EN 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_DIS 0x00000000U + +// Field: [20] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFESOFT1 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_M 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_S 20U +#define LRFDDBELL_IMASK1_RFESOFT1_EN 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_DIS 0x00000000U + +// Field: [19] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFESOFT0 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_M 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_S 19U +#define LRFDDBELL_IMASK1_RFESOFT0_EN 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_DIS 0x00000000U + +// Field: [18] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_LOCK 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_M 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_S 18U +#define LRFDDBELL_IMASK1_LOCK_EN 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_DIS 0x00000000U + +// Field: [17] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_LOL 0x00020000U +#define LRFDDBELL_IMASK1_LOL_M 0x00020000U +#define LRFDDBELL_IMASK1_LOL_S 17U +#define LRFDDBELL_IMASK1_LOL_EN 0x00020000U +#define LRFDDBELL_IMASK1_LOL_DIS 0x00000000U + +// Field: [16] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_TXFIFO 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_S 16U +#define LRFDDBELL_IMASK1_TXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_DIS 0x00000000U + +// Field: [15] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RXFIFO 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_M 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_S 15U +#define LRFDDBELL_IMASK1_RXFIFO_EN 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_DIS 0x00000000U + +// Field: [14] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE15 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_M 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_S 14U +#define LRFDDBELL_IMASK1_PBE15_EN 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_DIS 0x00000000U + +// Field: [13] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE14 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_M 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_S 13U +#define LRFDDBELL_IMASK1_PBE14_EN 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_DIS 0x00000000U + +// Field: [12] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE13 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_M 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_S 12U +#define LRFDDBELL_IMASK1_PBE13_EN 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_DIS 0x00000000U + +// Field: [11] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE12 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_M 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_S 11U +#define LRFDDBELL_IMASK1_PBE12_EN 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_DIS 0x00000000U + +// Field: [10] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE11 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_M 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_S 10U +#define LRFDDBELL_IMASK1_PBE11_EN 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_DIS 0x00000000U + +// Field: [9] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE10 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_M 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_S 9U +#define LRFDDBELL_IMASK1_PBE10_EN 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE8 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_S 8U +#define LRFDDBELL_IMASK1_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE7 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_S 7U +#define LRFDDBELL_IMASK1_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE6 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_S 6U +#define LRFDDBELL_IMASK1_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE5 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_S 5U +#define LRFDDBELL_IMASK1_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE4 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_S 4U +#define LRFDDBELL_IMASK1_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE3 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_S 3U +#define LRFDDBELL_IMASK1_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE2 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_S 2U +#define LRFDDBELL_IMASK1_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE1 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_S 1U +#define LRFDDBELL_IMASK1_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE0 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_S 0U +#define LRFDDBELL_IMASK1_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_S 31U +#define LRFDDBELL_RIS1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_S 30U +#define LRFDDBELL_RIS1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_S 29U +#define LRFDDBELL_RIS1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMDONE 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_S 28U +#define LRFDDBELL_RIS1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMIN 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_S 27U +#define LRFDDBELL_RIS1_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMOUT 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_S 26U +#define LRFDDBELL_RIS1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_S 25U +#define LRFDDBELL_RIS1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_S 24U +#define LRFDDBELL_RIS1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_S 23U +#define LRFDDBELL_RIS1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFEDONE 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_S 22U +#define LRFDDBELL_RIS1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_S 21U +#define LRFDDBELL_RIS1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_S 20U +#define LRFDDBELL_RIS1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_LOCK 0x00080000U +#define LRFDDBELL_RIS1_LOCK_M 0x00080000U +#define LRFDDBELL_RIS1_LOCK_S 19U +#define LRFDDBELL_RIS1_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS1_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_LOL 0x00040000U +#define LRFDDBELL_RIS1_LOL_M 0x00040000U +#define LRFDDBELL_RIS1_LOL_S 18U +#define LRFDDBELL_RIS1_LOL_SET 0x00040000U +#define LRFDDBELL_RIS1_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_TXFIFO 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_S 17U +#define LRFDDBELL_RIS1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RXFIFO 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_S 16U +#define LRFDDBELL_RIS1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE15 0x00008000U +#define LRFDDBELL_RIS1_PBE15_M 0x00008000U +#define LRFDDBELL_RIS1_PBE15_S 15U +#define LRFDDBELL_RIS1_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS1_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE14 0x00004000U +#define LRFDDBELL_RIS1_PBE14_M 0x00004000U +#define LRFDDBELL_RIS1_PBE14_S 14U +#define LRFDDBELL_RIS1_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS1_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE13 0x00002000U +#define LRFDDBELL_RIS1_PBE13_M 0x00002000U +#define LRFDDBELL_RIS1_PBE13_S 13U +#define LRFDDBELL_RIS1_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS1_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE12 0x00001000U +#define LRFDDBELL_RIS1_PBE12_M 0x00001000U +#define LRFDDBELL_RIS1_PBE12_S 12U +#define LRFDDBELL_RIS1_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS1_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE11 0x00000800U +#define LRFDDBELL_RIS1_PBE11_M 0x00000800U +#define LRFDDBELL_RIS1_PBE11_S 11U +#define LRFDDBELL_RIS1_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS1_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE10 0x00000400U +#define LRFDDBELL_RIS1_PBE10_M 0x00000400U +#define LRFDDBELL_RIS1_PBE10_S 10U +#define LRFDDBELL_RIS1_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS1_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE9 0x00000200U +#define LRFDDBELL_RIS1_PBE9_M 0x00000200U +#define LRFDDBELL_RIS1_PBE9_S 9U +#define LRFDDBELL_RIS1_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS1_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE8 0x00000100U +#define LRFDDBELL_RIS1_PBE8_M 0x00000100U +#define LRFDDBELL_RIS1_PBE8_S 8U +#define LRFDDBELL_RIS1_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS1_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE7 0x00000080U +#define LRFDDBELL_RIS1_PBE7_M 0x00000080U +#define LRFDDBELL_RIS1_PBE7_S 7U +#define LRFDDBELL_RIS1_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS1_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE6 0x00000040U +#define LRFDDBELL_RIS1_PBE6_M 0x00000040U +#define LRFDDBELL_RIS1_PBE6_S 6U +#define LRFDDBELL_RIS1_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS1_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE5 0x00000020U +#define LRFDDBELL_RIS1_PBE5_M 0x00000020U +#define LRFDDBELL_RIS1_PBE5_S 5U +#define LRFDDBELL_RIS1_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS1_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE4 0x00000010U +#define LRFDDBELL_RIS1_PBE4_M 0x00000010U +#define LRFDDBELL_RIS1_PBE4_S 4U +#define LRFDDBELL_RIS1_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS1_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE3 0x00000008U +#define LRFDDBELL_RIS1_PBE3_M 0x00000008U +#define LRFDDBELL_RIS1_PBE3_S 3U +#define LRFDDBELL_RIS1_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS1_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE2 0x00000004U +#define LRFDDBELL_RIS1_PBE2_M 0x00000004U +#define LRFDDBELL_RIS1_PBE2_S 2U +#define LRFDDBELL_RIS1_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS1_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE1 0x00000002U +#define LRFDDBELL_RIS1_PBE1_M 0x00000002U +#define LRFDDBELL_RIS1_PBE1_S 1U +#define LRFDDBELL_RIS1_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS1_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE0 0x00000001U +#define LRFDDBELL_RIS1_PBE0_M 0x00000001U +#define LRFDDBELL_RIS1_PBE0_S 0U +#define LRFDDBELL_RIS1_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS1_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_S 31U +#define LRFDDBELL_MIS1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_S 30U +#define LRFDDBELL_MIS1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_S 29U +#define LRFDDBELL_MIS1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMDONE 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_S 28U +#define LRFDDBELL_MIS1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMIN 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_S 27U +#define LRFDDBELL_MIS1_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMOUT 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_S 26U +#define LRFDDBELL_MIS1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_S 25U +#define LRFDDBELL_MIS1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_S 24U +#define LRFDDBELL_MIS1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_S 23U +#define LRFDDBELL_MIS1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFEDONE 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_S 22U +#define LRFDDBELL_MIS1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_S 21U +#define LRFDDBELL_MIS1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_S 20U +#define LRFDDBELL_MIS1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_LOCK 0x00080000U +#define LRFDDBELL_MIS1_LOCK_M 0x00080000U +#define LRFDDBELL_MIS1_LOCK_S 19U +#define LRFDDBELL_MIS1_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS1_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_LOL 0x00040000U +#define LRFDDBELL_MIS1_LOL_M 0x00040000U +#define LRFDDBELL_MIS1_LOL_S 18U +#define LRFDDBELL_MIS1_LOL_SET 0x00040000U +#define LRFDDBELL_MIS1_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_TXFIFO 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_S 17U +#define LRFDDBELL_MIS1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RXFIFO 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_S 16U +#define LRFDDBELL_MIS1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE15 0x00008000U +#define LRFDDBELL_MIS1_PBE15_M 0x00008000U +#define LRFDDBELL_MIS1_PBE15_S 15U +#define LRFDDBELL_MIS1_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS1_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE14 0x00004000U +#define LRFDDBELL_MIS1_PBE14_M 0x00004000U +#define LRFDDBELL_MIS1_PBE14_S 14U +#define LRFDDBELL_MIS1_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS1_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE13 0x00002000U +#define LRFDDBELL_MIS1_PBE13_M 0x00002000U +#define LRFDDBELL_MIS1_PBE13_S 13U +#define LRFDDBELL_MIS1_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS1_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE12 0x00001000U +#define LRFDDBELL_MIS1_PBE12_M 0x00001000U +#define LRFDDBELL_MIS1_PBE12_S 12U +#define LRFDDBELL_MIS1_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS1_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE11 0x00000800U +#define LRFDDBELL_MIS1_PBE11_M 0x00000800U +#define LRFDDBELL_MIS1_PBE11_S 11U +#define LRFDDBELL_MIS1_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS1_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE10 0x00000400U +#define LRFDDBELL_MIS1_PBE10_M 0x00000400U +#define LRFDDBELL_MIS1_PBE10_S 10U +#define LRFDDBELL_MIS1_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS1_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE9 0x00000200U +#define LRFDDBELL_MIS1_PBE9_M 0x00000200U +#define LRFDDBELL_MIS1_PBE9_S 9U +#define LRFDDBELL_MIS1_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS1_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE8 0x00000100U +#define LRFDDBELL_MIS1_PBE8_M 0x00000100U +#define LRFDDBELL_MIS1_PBE8_S 8U +#define LRFDDBELL_MIS1_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS1_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE7 0x00000080U +#define LRFDDBELL_MIS1_PBE7_M 0x00000080U +#define LRFDDBELL_MIS1_PBE7_S 7U +#define LRFDDBELL_MIS1_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS1_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE6 0x00000040U +#define LRFDDBELL_MIS1_PBE6_M 0x00000040U +#define LRFDDBELL_MIS1_PBE6_S 6U +#define LRFDDBELL_MIS1_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS1_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE5 0x00000020U +#define LRFDDBELL_MIS1_PBE5_M 0x00000020U +#define LRFDDBELL_MIS1_PBE5_S 5U +#define LRFDDBELL_MIS1_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS1_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE4 0x00000010U +#define LRFDDBELL_MIS1_PBE4_M 0x00000010U +#define LRFDDBELL_MIS1_PBE4_S 4U +#define LRFDDBELL_MIS1_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS1_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE3 0x00000008U +#define LRFDDBELL_MIS1_PBE3_M 0x00000008U +#define LRFDDBELL_MIS1_PBE3_S 3U +#define LRFDDBELL_MIS1_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS1_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE2 0x00000004U +#define LRFDDBELL_MIS1_PBE2_M 0x00000004U +#define LRFDDBELL_MIS1_PBE2_S 2U +#define LRFDDBELL_MIS1_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS1_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE1 0x00000002U +#define LRFDDBELL_MIS1_PBE1_M 0x00000002U +#define LRFDDBELL_MIS1_PBE1_S 1U +#define LRFDDBELL_MIS1_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS1_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE0 0x00000001U +#define LRFDDBELL_MIS1_PBE0_M 0x00000001U +#define LRFDDBELL_MIS1_PBE0_S 0U +#define LRFDDBELL_MIS1_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS1_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_S 31U +#define LRFDDBELL_ISET1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_S 30U +#define LRFDDBELL_ISET1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_S 29U +#define LRFDDBELL_ISET1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMDONE 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_S 28U +#define LRFDDBELL_ISET1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMIN 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_S 27U +#define LRFDDBELL_ISET1_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMOUT 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_S 26U +#define LRFDDBELL_ISET1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_S 25U +#define LRFDDBELL_ISET1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_S 24U +#define LRFDDBELL_ISET1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_S 23U +#define LRFDDBELL_ISET1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFEDONE 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_S 22U +#define LRFDDBELL_ISET1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_S 21U +#define LRFDDBELL_ISET1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_S 20U +#define LRFDDBELL_ISET1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_LOCK 0x00080000U +#define LRFDDBELL_ISET1_LOCK_M 0x00080000U +#define LRFDDBELL_ISET1_LOCK_S 19U +#define LRFDDBELL_ISET1_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET1_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_LOL 0x00040000U +#define LRFDDBELL_ISET1_LOL_M 0x00040000U +#define LRFDDBELL_ISET1_LOL_S 18U +#define LRFDDBELL_ISET1_LOL_SET 0x00040000U +#define LRFDDBELL_ISET1_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_TXFIFO 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_S 17U +#define LRFDDBELL_ISET1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RXFIFO 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_S 16U +#define LRFDDBELL_ISET1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE15 0x00008000U +#define LRFDDBELL_ISET1_PBE15_M 0x00008000U +#define LRFDDBELL_ISET1_PBE15_S 15U +#define LRFDDBELL_ISET1_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET1_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE14 0x00004000U +#define LRFDDBELL_ISET1_PBE14_M 0x00004000U +#define LRFDDBELL_ISET1_PBE14_S 14U +#define LRFDDBELL_ISET1_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET1_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE13 0x00002000U +#define LRFDDBELL_ISET1_PBE13_M 0x00002000U +#define LRFDDBELL_ISET1_PBE13_S 13U +#define LRFDDBELL_ISET1_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET1_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE12 0x00001000U +#define LRFDDBELL_ISET1_PBE12_M 0x00001000U +#define LRFDDBELL_ISET1_PBE12_S 12U +#define LRFDDBELL_ISET1_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET1_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE11 0x00000800U +#define LRFDDBELL_ISET1_PBE11_M 0x00000800U +#define LRFDDBELL_ISET1_PBE11_S 11U +#define LRFDDBELL_ISET1_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET1_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE10 0x00000400U +#define LRFDDBELL_ISET1_PBE10_M 0x00000400U +#define LRFDDBELL_ISET1_PBE10_S 10U +#define LRFDDBELL_ISET1_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET1_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE9 0x00000200U +#define LRFDDBELL_ISET1_PBE9_M 0x00000200U +#define LRFDDBELL_ISET1_PBE9_S 9U +#define LRFDDBELL_ISET1_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET1_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE8 0x00000100U +#define LRFDDBELL_ISET1_PBE8_M 0x00000100U +#define LRFDDBELL_ISET1_PBE8_S 8U +#define LRFDDBELL_ISET1_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET1_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE7 0x00000080U +#define LRFDDBELL_ISET1_PBE7_M 0x00000080U +#define LRFDDBELL_ISET1_PBE7_S 7U +#define LRFDDBELL_ISET1_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET1_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE6 0x00000040U +#define LRFDDBELL_ISET1_PBE6_M 0x00000040U +#define LRFDDBELL_ISET1_PBE6_S 6U +#define LRFDDBELL_ISET1_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET1_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE5 0x00000020U +#define LRFDDBELL_ISET1_PBE5_M 0x00000020U +#define LRFDDBELL_ISET1_PBE5_S 5U +#define LRFDDBELL_ISET1_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET1_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE4 0x00000010U +#define LRFDDBELL_ISET1_PBE4_M 0x00000010U +#define LRFDDBELL_ISET1_PBE4_S 4U +#define LRFDDBELL_ISET1_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET1_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE3 0x00000008U +#define LRFDDBELL_ISET1_PBE3_M 0x00000008U +#define LRFDDBELL_ISET1_PBE3_S 3U +#define LRFDDBELL_ISET1_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET1_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE2 0x00000004U +#define LRFDDBELL_ISET1_PBE2_M 0x00000004U +#define LRFDDBELL_ISET1_PBE2_S 2U +#define LRFDDBELL_ISET1_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET1_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE1 0x00000002U +#define LRFDDBELL_ISET1_PBE1_M 0x00000002U +#define LRFDDBELL_ISET1_PBE1_S 1U +#define LRFDDBELL_ISET1_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET1_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE0 0x00000001U +#define LRFDDBELL_ISET1_PBE0_M 0x00000001U +#define LRFDDBELL_ISET1_PBE0_S 0U +#define LRFDDBELL_ISET1_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET1_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_S 31U +#define LRFDDBELL_ICLR1_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_S 30U +#define LRFDDBELL_ICLR1_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_S 29U +#define LRFDDBELL_ICLR1_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_S 28U +#define LRFDDBELL_ICLR1_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMIN 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_S 27U +#define LRFDDBELL_ICLR1_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_S 26U +#define LRFDDBELL_ICLR1_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR1_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR1_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR1_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_S 22U +#define LRFDDBELL_ICLR1_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_S 21U +#define LRFDDBELL_ICLR1_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_S 20U +#define LRFDDBELL_ICLR1_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_LOCK 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_S 19U +#define LRFDDBELL_ICLR1_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_LOL 0x00040000U +#define LRFDDBELL_ICLR1_LOL_M 0x00040000U +#define LRFDDBELL_ICLR1_LOL_S 18U +#define LRFDDBELL_ICLR1_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR1_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_S 17U +#define LRFDDBELL_ICLR1_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_S 16U +#define LRFDDBELL_ICLR1_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE15 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_S 15U +#define LRFDDBELL_ICLR1_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE14 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_S 14U +#define LRFDDBELL_ICLR1_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE13 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_S 13U +#define LRFDDBELL_ICLR1_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE12 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_S 12U +#define LRFDDBELL_ICLR1_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE11 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_S 11U +#define LRFDDBELL_ICLR1_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE10 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_S 10U +#define LRFDDBELL_ICLR1_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE9 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_S 9U +#define LRFDDBELL_ICLR1_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE8 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_S 8U +#define LRFDDBELL_ICLR1_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE7 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_S 7U +#define LRFDDBELL_ICLR1_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE6 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_S 6U +#define LRFDDBELL_ICLR1_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE5 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_S 5U +#define LRFDDBELL_ICLR1_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE4 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_S 4U +#define LRFDDBELL_ICLR1_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE3 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_S 3U +#define LRFDDBELL_ICLR1_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE2 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_S 2U +#define LRFDDBELL_ICLR1_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE1 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_S 1U +#define LRFDDBELL_ICLR1_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE0 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_S 0U +#define LRFDDBELL_ICLR1_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK2 +// +//***************************************************************************** +// Field: [30] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM2 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_M 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_S 30U +#define LRFDDBELL_IMASK2_SYSTIM2_EN 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_DIS 0x00000000U + +// Field: [29] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM1 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_M 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_S 29U +#define LRFDDBELL_IMASK2_SYSTIM1_EN 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_DIS 0x00000000U + +// Field: [28] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM0 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_M 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_S 28U +#define LRFDDBELL_IMASK2_SYSTIM0_EN 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_DIS 0x00000000U + +// Field: [27] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMDONE 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_M 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_S 27U +#define LRFDDBELL_IMASK2_MDMDONE_EN 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_DIS 0x00000000U + +// Field: [26] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMIN 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_M 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_S 26U +#define LRFDDBELL_IMASK2_MDMIN_EN 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_DIS 0x00000000U + +// Field: [25] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMOUT 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_M 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_S 25U +#define LRFDDBELL_IMASK2_MDMOUT_EN 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_DIS 0x00000000U + +// Field: [24] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT2 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_M 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_S 24U +#define LRFDDBELL_IMASK2_MDMSOFT2_EN 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_DIS 0x00000000U + +// Field: [23] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT1 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_M 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_S 23U +#define LRFDDBELL_IMASK2_MDMSOFT1_EN 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_DIS 0x00000000U + +// Field: [22] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT0 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_M 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_S 22U +#define LRFDDBELL_IMASK2_MDMSOFT0_EN 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_DIS 0x00000000U + +// Field: [21] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFEDONE 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_M 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_S 21U +#define LRFDDBELL_IMASK2_RFEDONE_EN 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_DIS 0x00000000U + +// Field: [20] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFESOFT1 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_M 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_S 20U +#define LRFDDBELL_IMASK2_RFESOFT1_EN 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_DIS 0x00000000U + +// Field: [19] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFESOFT0 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_M 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_S 19U +#define LRFDDBELL_IMASK2_RFESOFT0_EN 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_DIS 0x00000000U + +// Field: [18] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_LOCK 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_M 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_S 18U +#define LRFDDBELL_IMASK2_LOCK_EN 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_DIS 0x00000000U + +// Field: [17] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_LOL 0x00020000U +#define LRFDDBELL_IMASK2_LOL_M 0x00020000U +#define LRFDDBELL_IMASK2_LOL_S 17U +#define LRFDDBELL_IMASK2_LOL_EN 0x00020000U +#define LRFDDBELL_IMASK2_LOL_DIS 0x00000000U + +// Field: [16] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_TXFIFO 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_S 16U +#define LRFDDBELL_IMASK2_TXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_DIS 0x00000000U + +// Field: [15] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RXFIFO 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_M 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_S 15U +#define LRFDDBELL_IMASK2_RXFIFO_EN 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_DIS 0x00000000U + +// Field: [14] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE15 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_M 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_S 14U +#define LRFDDBELL_IMASK2_PBE15_EN 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_DIS 0x00000000U + +// Field: [13] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE14 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_M 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_S 13U +#define LRFDDBELL_IMASK2_PBE14_EN 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_DIS 0x00000000U + +// Field: [12] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE13 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_M 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_S 12U +#define LRFDDBELL_IMASK2_PBE13_EN 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_DIS 0x00000000U + +// Field: [11] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE12 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_M 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_S 11U +#define LRFDDBELL_IMASK2_PBE12_EN 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_DIS 0x00000000U + +// Field: [10] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE11 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_M 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_S 10U +#define LRFDDBELL_IMASK2_PBE11_EN 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_DIS 0x00000000U + +// Field: [9] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE10 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_M 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_S 9U +#define LRFDDBELL_IMASK2_PBE10_EN 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE8 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_S 8U +#define LRFDDBELL_IMASK2_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE7 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_S 7U +#define LRFDDBELL_IMASK2_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE6 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_S 6U +#define LRFDDBELL_IMASK2_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE5 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_S 5U +#define LRFDDBELL_IMASK2_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE4 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_S 4U +#define LRFDDBELL_IMASK2_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE3 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_S 3U +#define LRFDDBELL_IMASK2_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE2 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_S 2U +#define LRFDDBELL_IMASK2_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE1 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_S 1U +#define LRFDDBELL_IMASK2_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE0 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_S 0U +#define LRFDDBELL_IMASK2_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_S 31U +#define LRFDDBELL_RIS2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_S 30U +#define LRFDDBELL_RIS2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_S 29U +#define LRFDDBELL_RIS2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMDONE 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_S 28U +#define LRFDDBELL_RIS2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMIN 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_S 27U +#define LRFDDBELL_RIS2_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMOUT 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_S 26U +#define LRFDDBELL_RIS2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_S 25U +#define LRFDDBELL_RIS2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_S 24U +#define LRFDDBELL_RIS2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_S 23U +#define LRFDDBELL_RIS2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFEDONE 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_S 22U +#define LRFDDBELL_RIS2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_S 21U +#define LRFDDBELL_RIS2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_S 20U +#define LRFDDBELL_RIS2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_LOCK 0x00080000U +#define LRFDDBELL_RIS2_LOCK_M 0x00080000U +#define LRFDDBELL_RIS2_LOCK_S 19U +#define LRFDDBELL_RIS2_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS2_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_LOL 0x00040000U +#define LRFDDBELL_RIS2_LOL_M 0x00040000U +#define LRFDDBELL_RIS2_LOL_S 18U +#define LRFDDBELL_RIS2_LOL_SET 0x00040000U +#define LRFDDBELL_RIS2_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_TXFIFO 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_S 17U +#define LRFDDBELL_RIS2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RXFIFO 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_S 16U +#define LRFDDBELL_RIS2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE15 0x00008000U +#define LRFDDBELL_RIS2_PBE15_M 0x00008000U +#define LRFDDBELL_RIS2_PBE15_S 15U +#define LRFDDBELL_RIS2_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS2_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE14 0x00004000U +#define LRFDDBELL_RIS2_PBE14_M 0x00004000U +#define LRFDDBELL_RIS2_PBE14_S 14U +#define LRFDDBELL_RIS2_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS2_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE13 0x00002000U +#define LRFDDBELL_RIS2_PBE13_M 0x00002000U +#define LRFDDBELL_RIS2_PBE13_S 13U +#define LRFDDBELL_RIS2_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS2_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE12 0x00001000U +#define LRFDDBELL_RIS2_PBE12_M 0x00001000U +#define LRFDDBELL_RIS2_PBE12_S 12U +#define LRFDDBELL_RIS2_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS2_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE11 0x00000800U +#define LRFDDBELL_RIS2_PBE11_M 0x00000800U +#define LRFDDBELL_RIS2_PBE11_S 11U +#define LRFDDBELL_RIS2_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS2_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE10 0x00000400U +#define LRFDDBELL_RIS2_PBE10_M 0x00000400U +#define LRFDDBELL_RIS2_PBE10_S 10U +#define LRFDDBELL_RIS2_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS2_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE9 0x00000200U +#define LRFDDBELL_RIS2_PBE9_M 0x00000200U +#define LRFDDBELL_RIS2_PBE9_S 9U +#define LRFDDBELL_RIS2_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS2_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE8 0x00000100U +#define LRFDDBELL_RIS2_PBE8_M 0x00000100U +#define LRFDDBELL_RIS2_PBE8_S 8U +#define LRFDDBELL_RIS2_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS2_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE7 0x00000080U +#define LRFDDBELL_RIS2_PBE7_M 0x00000080U +#define LRFDDBELL_RIS2_PBE7_S 7U +#define LRFDDBELL_RIS2_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS2_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE6 0x00000040U +#define LRFDDBELL_RIS2_PBE6_M 0x00000040U +#define LRFDDBELL_RIS2_PBE6_S 6U +#define LRFDDBELL_RIS2_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS2_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE5 0x00000020U +#define LRFDDBELL_RIS2_PBE5_M 0x00000020U +#define LRFDDBELL_RIS2_PBE5_S 5U +#define LRFDDBELL_RIS2_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS2_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE4 0x00000010U +#define LRFDDBELL_RIS2_PBE4_M 0x00000010U +#define LRFDDBELL_RIS2_PBE4_S 4U +#define LRFDDBELL_RIS2_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS2_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE3 0x00000008U +#define LRFDDBELL_RIS2_PBE3_M 0x00000008U +#define LRFDDBELL_RIS2_PBE3_S 3U +#define LRFDDBELL_RIS2_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS2_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE2 0x00000004U +#define LRFDDBELL_RIS2_PBE2_M 0x00000004U +#define LRFDDBELL_RIS2_PBE2_S 2U +#define LRFDDBELL_RIS2_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS2_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE1 0x00000002U +#define LRFDDBELL_RIS2_PBE1_M 0x00000002U +#define LRFDDBELL_RIS2_PBE1_S 1U +#define LRFDDBELL_RIS2_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS2_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE0 0x00000001U +#define LRFDDBELL_RIS2_PBE0_M 0x00000001U +#define LRFDDBELL_RIS2_PBE0_S 0U +#define LRFDDBELL_RIS2_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS2_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_S 31U +#define LRFDDBELL_MIS2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_S 30U +#define LRFDDBELL_MIS2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_S 29U +#define LRFDDBELL_MIS2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMDONE 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_S 28U +#define LRFDDBELL_MIS2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMIN 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_S 27U +#define LRFDDBELL_MIS2_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMOUT 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_S 26U +#define LRFDDBELL_MIS2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_S 25U +#define LRFDDBELL_MIS2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_S 24U +#define LRFDDBELL_MIS2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_S 23U +#define LRFDDBELL_MIS2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFEDONE 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_S 22U +#define LRFDDBELL_MIS2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_S 21U +#define LRFDDBELL_MIS2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_S 20U +#define LRFDDBELL_MIS2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_LOCK 0x00080000U +#define LRFDDBELL_MIS2_LOCK_M 0x00080000U +#define LRFDDBELL_MIS2_LOCK_S 19U +#define LRFDDBELL_MIS2_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS2_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_LOL 0x00040000U +#define LRFDDBELL_MIS2_LOL_M 0x00040000U +#define LRFDDBELL_MIS2_LOL_S 18U +#define LRFDDBELL_MIS2_LOL_SET 0x00040000U +#define LRFDDBELL_MIS2_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_TXFIFO 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_S 17U +#define LRFDDBELL_MIS2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RXFIFO 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_S 16U +#define LRFDDBELL_MIS2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE15 0x00008000U +#define LRFDDBELL_MIS2_PBE15_M 0x00008000U +#define LRFDDBELL_MIS2_PBE15_S 15U +#define LRFDDBELL_MIS2_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS2_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE14 0x00004000U +#define LRFDDBELL_MIS2_PBE14_M 0x00004000U +#define LRFDDBELL_MIS2_PBE14_S 14U +#define LRFDDBELL_MIS2_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS2_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE13 0x00002000U +#define LRFDDBELL_MIS2_PBE13_M 0x00002000U +#define LRFDDBELL_MIS2_PBE13_S 13U +#define LRFDDBELL_MIS2_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS2_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE12 0x00001000U +#define LRFDDBELL_MIS2_PBE12_M 0x00001000U +#define LRFDDBELL_MIS2_PBE12_S 12U +#define LRFDDBELL_MIS2_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS2_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE11 0x00000800U +#define LRFDDBELL_MIS2_PBE11_M 0x00000800U +#define LRFDDBELL_MIS2_PBE11_S 11U +#define LRFDDBELL_MIS2_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS2_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE10 0x00000400U +#define LRFDDBELL_MIS2_PBE10_M 0x00000400U +#define LRFDDBELL_MIS2_PBE10_S 10U +#define LRFDDBELL_MIS2_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS2_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE9 0x00000200U +#define LRFDDBELL_MIS2_PBE9_M 0x00000200U +#define LRFDDBELL_MIS2_PBE9_S 9U +#define LRFDDBELL_MIS2_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS2_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE8 0x00000100U +#define LRFDDBELL_MIS2_PBE8_M 0x00000100U +#define LRFDDBELL_MIS2_PBE8_S 8U +#define LRFDDBELL_MIS2_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS2_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE7 0x00000080U +#define LRFDDBELL_MIS2_PBE7_M 0x00000080U +#define LRFDDBELL_MIS2_PBE7_S 7U +#define LRFDDBELL_MIS2_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS2_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE6 0x00000040U +#define LRFDDBELL_MIS2_PBE6_M 0x00000040U +#define LRFDDBELL_MIS2_PBE6_S 6U +#define LRFDDBELL_MIS2_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS2_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE5 0x00000020U +#define LRFDDBELL_MIS2_PBE5_M 0x00000020U +#define LRFDDBELL_MIS2_PBE5_S 5U +#define LRFDDBELL_MIS2_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS2_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE4 0x00000010U +#define LRFDDBELL_MIS2_PBE4_M 0x00000010U +#define LRFDDBELL_MIS2_PBE4_S 4U +#define LRFDDBELL_MIS2_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS2_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE3 0x00000008U +#define LRFDDBELL_MIS2_PBE3_M 0x00000008U +#define LRFDDBELL_MIS2_PBE3_S 3U +#define LRFDDBELL_MIS2_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS2_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE2 0x00000004U +#define LRFDDBELL_MIS2_PBE2_M 0x00000004U +#define LRFDDBELL_MIS2_PBE2_S 2U +#define LRFDDBELL_MIS2_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS2_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE1 0x00000002U +#define LRFDDBELL_MIS2_PBE1_M 0x00000002U +#define LRFDDBELL_MIS2_PBE1_S 1U +#define LRFDDBELL_MIS2_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS2_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE0 0x00000001U +#define LRFDDBELL_MIS2_PBE0_M 0x00000001U +#define LRFDDBELL_MIS2_PBE0_S 0U +#define LRFDDBELL_MIS2_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS2_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_S 31U +#define LRFDDBELL_ISET2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_S 30U +#define LRFDDBELL_ISET2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_S 29U +#define LRFDDBELL_ISET2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMDONE 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_S 28U +#define LRFDDBELL_ISET2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMIN 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_S 27U +#define LRFDDBELL_ISET2_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMOUT 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_S 26U +#define LRFDDBELL_ISET2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_S 25U +#define LRFDDBELL_ISET2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_S 24U +#define LRFDDBELL_ISET2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_S 23U +#define LRFDDBELL_ISET2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFEDONE 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_S 22U +#define LRFDDBELL_ISET2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_S 21U +#define LRFDDBELL_ISET2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_S 20U +#define LRFDDBELL_ISET2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_LOCK 0x00080000U +#define LRFDDBELL_ISET2_LOCK_M 0x00080000U +#define LRFDDBELL_ISET2_LOCK_S 19U +#define LRFDDBELL_ISET2_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET2_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_LOL 0x00040000U +#define LRFDDBELL_ISET2_LOL_M 0x00040000U +#define LRFDDBELL_ISET2_LOL_S 18U +#define LRFDDBELL_ISET2_LOL_SET 0x00040000U +#define LRFDDBELL_ISET2_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_TXFIFO 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_S 17U +#define LRFDDBELL_ISET2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RXFIFO 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_S 16U +#define LRFDDBELL_ISET2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE15 0x00008000U +#define LRFDDBELL_ISET2_PBE15_M 0x00008000U +#define LRFDDBELL_ISET2_PBE15_S 15U +#define LRFDDBELL_ISET2_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET2_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE14 0x00004000U +#define LRFDDBELL_ISET2_PBE14_M 0x00004000U +#define LRFDDBELL_ISET2_PBE14_S 14U +#define LRFDDBELL_ISET2_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET2_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE13 0x00002000U +#define LRFDDBELL_ISET2_PBE13_M 0x00002000U +#define LRFDDBELL_ISET2_PBE13_S 13U +#define LRFDDBELL_ISET2_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET2_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE12 0x00001000U +#define LRFDDBELL_ISET2_PBE12_M 0x00001000U +#define LRFDDBELL_ISET2_PBE12_S 12U +#define LRFDDBELL_ISET2_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET2_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE11 0x00000800U +#define LRFDDBELL_ISET2_PBE11_M 0x00000800U +#define LRFDDBELL_ISET2_PBE11_S 11U +#define LRFDDBELL_ISET2_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET2_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE10 0x00000400U +#define LRFDDBELL_ISET2_PBE10_M 0x00000400U +#define LRFDDBELL_ISET2_PBE10_S 10U +#define LRFDDBELL_ISET2_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET2_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE9 0x00000200U +#define LRFDDBELL_ISET2_PBE9_M 0x00000200U +#define LRFDDBELL_ISET2_PBE9_S 9U +#define LRFDDBELL_ISET2_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET2_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE8 0x00000100U +#define LRFDDBELL_ISET2_PBE8_M 0x00000100U +#define LRFDDBELL_ISET2_PBE8_S 8U +#define LRFDDBELL_ISET2_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET2_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE7 0x00000080U +#define LRFDDBELL_ISET2_PBE7_M 0x00000080U +#define LRFDDBELL_ISET2_PBE7_S 7U +#define LRFDDBELL_ISET2_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET2_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE6 0x00000040U +#define LRFDDBELL_ISET2_PBE6_M 0x00000040U +#define LRFDDBELL_ISET2_PBE6_S 6U +#define LRFDDBELL_ISET2_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET2_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE5 0x00000020U +#define LRFDDBELL_ISET2_PBE5_M 0x00000020U +#define LRFDDBELL_ISET2_PBE5_S 5U +#define LRFDDBELL_ISET2_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET2_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE4 0x00000010U +#define LRFDDBELL_ISET2_PBE4_M 0x00000010U +#define LRFDDBELL_ISET2_PBE4_S 4U +#define LRFDDBELL_ISET2_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET2_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE3 0x00000008U +#define LRFDDBELL_ISET2_PBE3_M 0x00000008U +#define LRFDDBELL_ISET2_PBE3_S 3U +#define LRFDDBELL_ISET2_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET2_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE2 0x00000004U +#define LRFDDBELL_ISET2_PBE2_M 0x00000004U +#define LRFDDBELL_ISET2_PBE2_S 2U +#define LRFDDBELL_ISET2_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET2_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE1 0x00000002U +#define LRFDDBELL_ISET2_PBE1_M 0x00000002U +#define LRFDDBELL_ISET2_PBE1_S 1U +#define LRFDDBELL_ISET2_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET2_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE0 0x00000001U +#define LRFDDBELL_ISET2_PBE0_M 0x00000001U +#define LRFDDBELL_ISET2_PBE0_S 0U +#define LRFDDBELL_ISET2_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET2_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_S 31U +#define LRFDDBELL_ICLR2_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_S 30U +#define LRFDDBELL_ICLR2_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_S 29U +#define LRFDDBELL_ICLR2_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_S 28U +#define LRFDDBELL_ICLR2_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMIN 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_S 27U +#define LRFDDBELL_ICLR2_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_S 26U +#define LRFDDBELL_ICLR2_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR2_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR2_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR2_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_S 22U +#define LRFDDBELL_ICLR2_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_S 21U +#define LRFDDBELL_ICLR2_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_S 20U +#define LRFDDBELL_ICLR2_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_LOCK 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_S 19U +#define LRFDDBELL_ICLR2_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_LOL 0x00040000U +#define LRFDDBELL_ICLR2_LOL_M 0x00040000U +#define LRFDDBELL_ICLR2_LOL_S 18U +#define LRFDDBELL_ICLR2_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR2_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_S 17U +#define LRFDDBELL_ICLR2_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_S 16U +#define LRFDDBELL_ICLR2_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE15 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_S 15U +#define LRFDDBELL_ICLR2_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE14 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_S 14U +#define LRFDDBELL_ICLR2_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE13 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_S 13U +#define LRFDDBELL_ICLR2_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE12 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_S 12U +#define LRFDDBELL_ICLR2_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE11 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_S 11U +#define LRFDDBELL_ICLR2_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE10 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_S 10U +#define LRFDDBELL_ICLR2_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE9 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_S 9U +#define LRFDDBELL_ICLR2_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE8 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_S 8U +#define LRFDDBELL_ICLR2_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE7 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_S 7U +#define LRFDDBELL_ICLR2_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE6 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_S 6U +#define LRFDDBELL_ICLR2_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE5 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_S 5U +#define LRFDDBELL_ICLR2_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE4 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_S 4U +#define LRFDDBELL_ICLR2_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE3 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_S 3U +#define LRFDDBELL_ICLR2_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE2 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_S 2U +#define LRFDDBELL_ICLR2_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE1 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_S 1U +#define LRFDDBELL_ICLR2_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE0 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_S 0U +#define LRFDDBELL_ICLR2_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_NOEFF 0x00000000U + + +#endif // __LRFDDBELL__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h new file mode 100644 index 00000000..dd3413c9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h @@ -0,0 +1,62 @@ +/****************************************************************************** +* Filename: hw_lrfdrxf_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDRXF_H__ +#define __HW_LRFDRXF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDRXF component +// +//***************************************************************************** +// Data to from RXFIFO +#define LRFDRXF_O_RXD 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRXF_O_RXD +// +//***************************************************************************** +// Field: [31:0] DATA +// +// RX FIFO data. When written the register data is pushed to the RX FIFO. When +// read, data is popped from the RX FIFO. When writing or reading this register +// the access size will determine how many bytes are pushed to or popped from +// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the +// access being done. +#define LRFDRXF_RXD_DATA_W 32U +#define LRFDRXF_RXD_DATA_M 0xFFFFFFFFU +#define LRFDRXF_RXD_DATA_S 0U + + +#endif // __LRFDRXF__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h new file mode 100644 index 00000000..d6756c39 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h @@ -0,0 +1,62 @@ +/****************************************************************************** +* Filename: hw_lrfdtxf_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDTXF_H__ +#define __HW_LRFDTXF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDTXF component +// +//***************************************************************************** +// Data to from TXFIFO +#define LRFDTXF_O_TXD 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTXF_O_TXD +// +//***************************************************************************** +// Field: [31:0] DATA +// +// TX FIFO data. When written the register data is pushed to the TX FIFO. When +// read, data is popped from the TX FIFO. When writing or reading this register +// the access size will determine how many bytes are pushed to or popped from +// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the +// access being done. +#define LRFDTXF_TXD_DATA_W 32U +#define LRFDTXF_TXD_DATA_M 0xFFFFFFFFU +#define LRFDTXF_TXD_DATA_S 0U + + +#endif // __LRFDTXF__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap.h new file mode 100644 index 00000000..60233785 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Filename: hw_memmap_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASH_MAIN_BASE 0x00000000 // FLASH_MAIN + #define FLASH_MAIN_SIZE 0x80000 +#define ROM_BASE 0x0F000000 // ROM + #define ROM_SIZE 0x3000 +#define SRAM_BASE 0x20000000 // SRAM + #define SRAM_SIZE 0x9000 +#define PMCTL_BASE 0x40000000 // PMCTL +#define CKMD_BASE 0x40001000 // CKMD +#define RTC_BASE 0x40002000 // RTC +#define IOC_BASE 0x40003000 // IOC +#define SYS0_BASE 0x40004000 // SYS0 +#define EVTULL_BASE 0x40005000 // EVTULL +#define PMUD_BASE 0x40006000 // PMUD +#define DBGSS_BASE 0x4000F000 // DBGSS +#define CLKCTL_BASE 0x40020000 // CLKCTL +#define FLASH_BASE 0x40021000 // FLASH +#define SYSTIM_BASE 0x40022000 // SYSTIM +#define GPIO_BASE 0x40023000 // GPIO +#define VIMS_BASE 0x40024000 // VIMS +#define EVTSVT_BASE 0x40025000 // EVTSVT +#define DMA_BASE 0x40026000 // DMA +#define SPI0_BASE 0x40030000 // SPI +#define UART0_BASE 0x40034000 // UART +#define I2C0_BASE 0x40038000 // I2C +#define ADC_BASE 0x40050000 // ADC +#define LGPT0_BASE 0x40060000 // LGPT0 +#define LGPT1_BASE 0x40061000 // LGPT1 +#define LGPT2_BASE 0x40062000 // LGPT2 +#define LGPT3_BASE 0x40063000 // LGPT3 +#define LRFDDBELL_BASE 0x40080000 // LRFDDBELL +#define LRFDPBE_BASE 0x40081000 // LRFDPBE +#define LRFDPBE32_BASE 0x40081400 // LRFDPBE32 +#define LRFDTXF_BASE 0x40081800 // LRFDTXF +#define LRFDRXF_BASE 0x40081C00 // LRFDRXF +#define LRFDMDM_BASE 0x40082000 // LRFDMDM +#define LRFDMDM32_BASE 0x40082400 // LRFDMDM32 +#define LRFDRFE_BASE 0x40083000 // LRFDRFE +#define LRFDRFE32_BASE 0x40083400 // LRFDRFE32 +#define LRFDTRC_BASE 0x40084000 // LRFDTRC +#define LRFDS2R_BASE 0x40085000 // LRFDS2R +#define LRFD_PBERAM_BASE 0x40090000 // LRFD_PBERAM + #define LRFD_PBERAM_SIZE 0x1000 +#define LRFD_BUFRAM_BASE 0x40092000 // LRFD_BUFRAM + #define LRFD_BUFRAM_SIZE 0x600 +#define LRFD_MCERAM_BASE 0x40094000 // LRFD_MCERAM + #define LRFD_MCERAM_SIZE 0x1000 +#define LRFD_RFERAM_BASE 0x40096000 // LRFD_RFERAM + #define LRFD_RFERAM_SIZE 0x1000 +#define LRFD_S2RRAM_BASE 0x40098000 // LRFD_S2RRAM + #define LRFD_S2RRAM_SIZE 0x1000 +#define AES_BASE 0x400C0000 // AES +#define FCFG_BASE 0x4E000000 // FCFG + #define FCFG_SIZE 0x400 +#define CCFG_BASE 0x4E020000 // CCFG + #define CCFG_SIZE 0x800 +#define BPU_BASE 0xE0002000 // BPU +#define NVIC_BASE 0xE000E000 // NVIC +#define SYSTICK_BASE 0xE000E010 // SYSTICK +#define SCB_BASE 0xE000ED00 // SCB +#define DCB_BASE 0xE000ED30 // DCB +#define SCSCS_BASE 0xE000EFC0 // SCSCS +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap_common.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap_common.h new file mode 100644 index 00000000..9c0cee78 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_memmap_common.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: hw_memmap_common.h +* +* Description: Common memory map macros. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_COMMON_H__ +#define __HW_MEMMAP_COMMON_H__ + +#include +#include + +//***************************************************************************** +// +// Offset for secure peripheral addresses. Defined for all devices as a +// convenience, but only relevant on M33 and M33F cores with TrustZone. +// +//***************************************************************************** +#define NONSECURE_OFFSET 0x0 + +#endif // __HW_MEMMAP_COMMON_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_nvic.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_nvic.h new file mode 100644 index 00000000..70a08ce9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_nvic.h @@ -0,0 +1,397 @@ +/****************************************************************************** +* Filename: hw_nvic_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// NVIC component +// +//***************************************************************************** +// Interrupt Set-Enable Register +#define NVIC_O_ISER 0x00000100U + +// Interrupt Clear-Enable Register +#define NVIC_O_ICER 0x00000180U + +// Interrupt Set-Pending Register +#define NVIC_O_ISPR 0x00000200U + +// Interrupt Clear-Pending Register +#define NVIC_O_ICPR 0x00000280U + +// Interrupt Priority Register 0 +#define NVIC_O_IPR0 0x00000400U + +// Interrupt Priority Register 1 +#define NVIC_O_IPR1 0x00000404U + +// Interrupt Priority Register 2 +#define NVIC_O_IPR2 0x00000408U + +// Interrupt Priority Register 3 +#define NVIC_O_IPR3 0x0000040CU + +// Interrupt Priority Register 4 +#define NVIC_O_IPR4 0x00000410U + +// Interrupt Priority Register 5 +#define NVIC_O_IPR5 0x00000414U + +// Interrupt Priority Register 6 +#define NVIC_O_IPR6 0x00000418U + +// Interrupt Priority Register 7 +#define NVIC_O_IPR7 0x0000041CU + +//***************************************************************************** +// +// Register: NVIC_O_ISER +// +//***************************************************************************** +// Field: [31:0] SETENA +// +// Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the +// corresponding interrupt. Reading the bit returns its current enable state. +// Reset clears the SETENA fields. +#define NVIC_ISER_SETENA_W 32U +#define NVIC_ISER_SETENA_M 0xFFFFFFFFU +#define NVIC_ISER_SETENA_S 0U + +//***************************************************************************** +// +// Register: NVIC_O_ICER +// +//***************************************************************************** +// Field: [31:0] CLRENA +// +// Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the +// corresponding interrupt. Reading the bit returns its current enable state. +// Reset clears the CLRENA field. +#define NVIC_ICER_CLRENA_W 32U +#define NVIC_ICER_CLRENA_M 0xFFFFFFFFU +#define NVIC_ICER_CLRENA_S 0U + +//***************************************************************************** +// +// Register: NVIC_O_ISPR +// +//***************************************************************************** +// Field: [31:0] SETPEND +// +// Interrupt set-pending bits for a: Write: 1 = pend interrupt 0 = no effect; +// Read: 1 = interrupt is pending 0 = interrupt is not pending. +#define NVIC_ISPR_SETPEND_W 32U +#define NVIC_ISPR_SETPEND_M 0xFFFFFFFFU +#define NVIC_ISPR_SETPEND_S 0U + +//***************************************************************************** +// +// Register: NVIC_O_ICPR +// +//***************************************************************************** +// Field: [31:0] CLRPEND +// +// Interrupt clear-pending bits: Write: 1 = clear interrupt pending bit, 0 = no +// effect; Read: 1 = interrupt is pending 0 = interrupt is not pending. +#define NVIC_ICPR_CLRPEND_W 32U +#define NVIC_ICPR_CLRPEND_M 0xFFFFFFFFU +#define NVIC_ICPR_CLRPEND_S 0U + +//***************************************************************************** +// +// Register: NVIC_O_IPR0 +// +//***************************************************************************** +// Field: [31:30] IP_3 +// +// Priority of interrupt 3 +#define NVIC_IPR0_IP_3_W 2U +#define NVIC_IPR0_IP_3_M 0xC0000000U +#define NVIC_IPR0_IP_3_S 30U + +// Field: [23:22] IP_2 +// +// Priority of interrupt 2 +#define NVIC_IPR0_IP_2_W 2U +#define NVIC_IPR0_IP_2_M 0x00C00000U +#define NVIC_IPR0_IP_2_S 22U + +// Field: [15:14] IP_1 +// +// Priority of interrupt 1 +#define NVIC_IPR0_IP_1_W 2U +#define NVIC_IPR0_IP_1_M 0x0000C000U +#define NVIC_IPR0_IP_1_S 14U + +// Field: [7:6] IP_0 +// +// Priority of interrupt 0 +#define NVIC_IPR0_IP_0_W 2U +#define NVIC_IPR0_IP_0_M 0x000000C0U +#define NVIC_IPR0_IP_0_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR1 +// +//***************************************************************************** +// Field: [31:30] IP_7 +// +// Priority of interrupt 7 +#define NVIC_IPR1_IP_7_W 2U +#define NVIC_IPR1_IP_7_M 0xC0000000U +#define NVIC_IPR1_IP_7_S 30U + +// Field: [23:22] IP_6 +// +// Priority of interrupt 6 +#define NVIC_IPR1_IP_6_W 2U +#define NVIC_IPR1_IP_6_M 0x00C00000U +#define NVIC_IPR1_IP_6_S 22U + +// Field: [15:14] IP_5 +// +// Priority of interrupt 5 +#define NVIC_IPR1_IP_5_W 2U +#define NVIC_IPR1_IP_5_M 0x0000C000U +#define NVIC_IPR1_IP_5_S 14U + +// Field: [7:6] IP_4 +// +// Priority of interrupt 4 +#define NVIC_IPR1_IP_4_W 2U +#define NVIC_IPR1_IP_4_M 0x000000C0U +#define NVIC_IPR1_IP_4_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR2 +// +//***************************************************************************** +// Field: [31:30] IP_11 +// +// Priority of interrupt 11 +#define NVIC_IPR2_IP_11_W 2U +#define NVIC_IPR2_IP_11_M 0xC0000000U +#define NVIC_IPR2_IP_11_S 30U + +// Field: [23:22] IP_10 +// +// Priority of interrupt 10 +#define NVIC_IPR2_IP_10_W 2U +#define NVIC_IPR2_IP_10_M 0x00C00000U +#define NVIC_IPR2_IP_10_S 22U + +// Field: [15:14] IP_9 +// +// Priority of interrupt 9 +#define NVIC_IPR2_IP_9_W 2U +#define NVIC_IPR2_IP_9_M 0x0000C000U +#define NVIC_IPR2_IP_9_S 14U + +// Field: [7:6] IP_8 +// +// Priority of interrupt 8 +#define NVIC_IPR2_IP_8_W 2U +#define NVIC_IPR2_IP_8_M 0x000000C0U +#define NVIC_IPR2_IP_8_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR3 +// +//***************************************************************************** +// Field: [31:30] IP_15 +// +// Priority of interrupt 15 +#define NVIC_IPR3_IP_15_W 2U +#define NVIC_IPR3_IP_15_M 0xC0000000U +#define NVIC_IPR3_IP_15_S 30U + +// Field: [23:22] IP_14 +// +// Priority of interrupt 14 +#define NVIC_IPR3_IP_14_W 2U +#define NVIC_IPR3_IP_14_M 0x00C00000U +#define NVIC_IPR3_IP_14_S 22U + +// Field: [15:14] IP_13 +// +// Priority of interrupt 13 +#define NVIC_IPR3_IP_13_W 2U +#define NVIC_IPR3_IP_13_M 0x0000C000U +#define NVIC_IPR3_IP_13_S 14U + +// Field: [7:6] IP_12 +// +// Priority of interrupt 12 +#define NVIC_IPR3_IP_12_W 2U +#define NVIC_IPR3_IP_12_M 0x000000C0U +#define NVIC_IPR3_IP_12_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR4 +// +//***************************************************************************** +// Field: [31:30] IP_19 +// +// Priority of interrupt 19 +#define NVIC_IPR4_IP_19_W 2U +#define NVIC_IPR4_IP_19_M 0xC0000000U +#define NVIC_IPR4_IP_19_S 30U + +// Field: [23:22] IP_18 +// +// Priority of interrupt 18 +#define NVIC_IPR4_IP_18_W 2U +#define NVIC_IPR4_IP_18_M 0x00C00000U +#define NVIC_IPR4_IP_18_S 22U + +// Field: [15:14] IP_17 +// +// Priority of interrupt 17 +#define NVIC_IPR4_IP_17_W 2U +#define NVIC_IPR4_IP_17_M 0x0000C000U +#define NVIC_IPR4_IP_17_S 14U + +// Field: [7:6] IP_16 +// +// Priority of interrupt 16 +#define NVIC_IPR4_IP_16_W 2U +#define NVIC_IPR4_IP_16_M 0x000000C0U +#define NVIC_IPR4_IP_16_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR5 +// +//***************************************************************************** +// Field: [31:30] IP_23 +// +// Priority of interrupt 23 +#define NVIC_IPR5_IP_23_W 2U +#define NVIC_IPR5_IP_23_M 0xC0000000U +#define NVIC_IPR5_IP_23_S 30U + +// Field: [23:22] IP_22 +// +// Priority of interrupt 22 +#define NVIC_IPR5_IP_22_W 2U +#define NVIC_IPR5_IP_22_M 0x00C00000U +#define NVIC_IPR5_IP_22_S 22U + +// Field: [15:14] IP_21 +// +// Priority of interrupt 21 +#define NVIC_IPR5_IP_21_W 2U +#define NVIC_IPR5_IP_21_M 0x0000C000U +#define NVIC_IPR5_IP_21_S 14U + +// Field: [7:6] IP_20 +// +// Priority of interrupt 20 +#define NVIC_IPR5_IP_20_W 2U +#define NVIC_IPR5_IP_20_M 0x000000C0U +#define NVIC_IPR5_IP_20_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR6 +// +//***************************************************************************** +// Field: [31:30] IP_27 +// +// Priority of interrupt 27 +#define NVIC_IPR6_IP_27_W 2U +#define NVIC_IPR6_IP_27_M 0xC0000000U +#define NVIC_IPR6_IP_27_S 30U + +// Field: [23:22] IP_26 +// +// Priority of interrupt 26 +#define NVIC_IPR6_IP_26_W 2U +#define NVIC_IPR6_IP_26_M 0x00C00000U +#define NVIC_IPR6_IP_26_S 22U + +// Field: [15:14] IP_25 +// +// Priority of interrupt 25 +#define NVIC_IPR6_IP_25_W 2U +#define NVIC_IPR6_IP_25_M 0x0000C000U +#define NVIC_IPR6_IP_25_S 14U + +// Field: [7:6] IP_24 +// +// Priority of interrupt 24 +#define NVIC_IPR6_IP_24_W 2U +#define NVIC_IPR6_IP_24_M 0x000000C0U +#define NVIC_IPR6_IP_24_S 6U + +//***************************************************************************** +// +// Register: NVIC_O_IPR7 +// +//***************************************************************************** +// Field: [31:30] IP_31 +// +// Priority of interrupt 31 +#define NVIC_IPR7_IP_31_W 2U +#define NVIC_IPR7_IP_31_M 0xC0000000U +#define NVIC_IPR7_IP_31_S 30U + +// Field: [23:22] IP_30 +// +// Priority of interrupt 30 +#define NVIC_IPR7_IP_30_W 2U +#define NVIC_IPR7_IP_30_M 0x00C00000U +#define NVIC_IPR7_IP_30_S 22U + +// Field: [15:14] IP_29 +// +// Priority of interrupt 29 +#define NVIC_IPR7_IP_29_W 2U +#define NVIC_IPR7_IP_29_M 0x0000C000U +#define NVIC_IPR7_IP_29_S 14U + +// Field: [7:6] IP_28 +// +// Priority of interrupt 28 +#define NVIC_IPR7_IP_28_W 2U +#define NVIC_IPR7_IP_28_M 0x000000C0U +#define NVIC_IPR7_IP_28_S 6U + + +#endif // __NVIC__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_platform.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_platform.h new file mode 100644 index 00000000..9b1ea104 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_platform.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * Copyright (c) 2021-2023 Texas Instruments Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ +#ifndef __HW_PLATFORM_H__ +#define __HW_PLATFORM_H__ +#include "hw_memmap.h" +#include "hw_pmctl.h" + +//***************************************************************************** +// +// Address, offset and constant definitions +// +//***************************************************************************** +// --- ROM definitions --- +/// Address of ROM FW revision structure +#define ROM_FWREV_ADDR (ROM_BASE + 0x0048) +/// Base address of HAPI table in ROM +#define ROM_HAPI_BASE (ROM_BASE + 0x004C) +/// Address of CRC32 calculated over entire ROM +#define ROM_CRC_ADDR (ROM_BASE + ROM_SIZE - 4) + +// --- SRAM definitions --- +/// Magic value used in Fcfg.criticalTrim.sramRepair.magicWord to +/// indicate that SRAM repair information is valid +#define SRAMREP_MAGICWORD 0x40008100 + +//***************************************************************************** +// +// Boot status definitions (available through PMCTL::BOOTSTA) in addition to +// the defines listed in hw_pmctl.h +// +//***************************************************************************** +/// Boot sequence completed +#define PMCTL_BOOTSTA_BOOT_COMPLETE (PMCTL_BOOTSTA_FLAG_MODE_BLDR) +/// Bootloader start initiated +#define PMCTL_BOOTSTA_BLDR_START_INIT (PMCTL_BOOTSTA_FLAG_MODE_BLDR | 0x02) +/// ROM serial bootloader complete +#define PMCTL_BOOTSTA_BLDR_COMPLETE (PMCTL_BOOTSTA_FLAG_MODE_APP) +/// Application start initiated +#define PMCTL_BOOTSTA_APP_START_INIT (PMCTL_BOOTSTA_FLAG_MODE_APP | 0x02) + +#if !(defined(__ASM_INCLUDE__)) +// Only included in C files + +/// Data type for passing flags to bootloader/application entry function +typedef union +{ + uint32_t val32; ///< 32b value of word + struct + { + uint32_t bCcfgValid:1; ///< Is CCFG valid? + uint32_t bAppCanBoot:1; ///< Does a bootable application exist? + uint32_t bChipEraseAllowed:1; ///< Is ChipErase operation allowed? + uint32_t bParamsFromCcfg:1; ///< Entry function params argument is CCFG(1) or FCFG(0) + uint32_t bBldrAllowDbg:1; ///< Is debugging of bootloader allowed? + uint32_t res0:27; ///< (Reserved for future use) + } bldr; +} bldrEntryFlags_t; + +#endif //!(defined(__ASM_INCLUDE__) + +#endif // __HW_PLATFORM_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmctl.h new file mode 100644 index 00000000..9e376dea --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmctl.h @@ -0,0 +1,754 @@ +/****************************************************************************** +* Filename: hw_pmctl_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_PMCTL_H__ +#define __HW_PMCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PMCTL component +// +//***************************************************************************** +// Description Register. +#define PMCTL_O_DESC 0x00000000U + +// Extended Description Register. +#define PMCTL_O_DESCEX 0x00000004U + +// Shutdown Register. +#define PMCTL_O_SHTDWN 0x00000008U + +// Sleep Control Register. +#define PMCTL_O_SLPCTL 0x0000000CU + +// Wakeup Status Register +#define PMCTL_O_WUSTA 0x00000010U + +// VDDR Control Register. +#define PMCTL_O_VDDRCTL 0x00000014U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_SYSFSET 0x00000020U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_SYSFCLR 0x00000024U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_SYSFSTA 0x00000028U + +// Reset Control Register. +#define PMCTL_O_RSTCTL 0x0000002CU + +// Reset Status. +#define PMCTL_O_RSTSTA 0x00000030U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_BOOTSTA 0x00000034U + +// AON Register Status 1. +#define PMCTL_O_AONRSTA1 0x0000003CU + +// AON Register Set 1. +#define PMCTL_O_AONRSET1 0x00000040U + +// AON Register Clear 1. +#define PMCTL_O_AONRCLR1 0x00000044U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_ETPP 0x00000064U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG0 0x0000007CU + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG1 0x00000080U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG2 0x00000084U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG3 0x00000088U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG4 0x0000008CU + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG5 0x00000090U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG6 0x00000094U + +// Internal. Only to be used through TI provided API. +#define PMCTL_O_RETCFG7 0x00000098U + +//***************************************************************************** +// +// Register: PMCTL_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define PMCTL_DESC_MODID_W 16U +#define PMCTL_DESC_MODID_M 0xFFFF0000U +#define PMCTL_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define PMCTL_DESC_STDIPOFF_W 4U +#define PMCTL_DESC_STDIPOFF_M 0x0000F000U +#define PMCTL_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define PMCTL_DESC_INSTIDX_W 4U +#define PMCTL_DESC_INSTIDX_M 0x00000F00U +#define PMCTL_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define PMCTL_DESC_MAJREV_W 4U +#define PMCTL_DESC_MAJREV_M 0x000000F0U +#define PMCTL_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define PMCTL_DESC_MINREV_W 4U +#define PMCTL_DESC_MINREV_M 0x0000000FU +#define PMCTL_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: PMCTL_O_DESCEX +// +//***************************************************************************** +// Field: [31:30] FLASHSZ +// +// System flash availability +// ENUMs: +// SZ3 Flash size set to level 3 (Max size) +// SZ2 Flash size set to level 2 +// SZ1 Flash size set to level 1 +// SZ0 Flash size set to level 0 (Min size) +#define PMCTL_DESCEX_FLASHSZ_W 2U +#define PMCTL_DESCEX_FLASHSZ_M 0xC0000000U +#define PMCTL_DESCEX_FLASHSZ_S 30U +#define PMCTL_DESCEX_FLASHSZ_SZ3 0xC0000000U +#define PMCTL_DESCEX_FLASHSZ_SZ2 0x80000000U +#define PMCTL_DESCEX_FLASHSZ_SZ1 0x40000000U +#define PMCTL_DESCEX_FLASHSZ_SZ0 0x00000000U + +// Field: [29:28] SRAMSZ +// +// System SRAM availability +// ENUMs: +// SZ3 SRAM size set to level 3 (Max size) +// SZ2 SRAM size set to level 2 +// SZ1 SRAM size set to level 1 +// SZ0 SRAM size set to level 0 (Min size) +#define PMCTL_DESCEX_SRAMSZ_W 2U +#define PMCTL_DESCEX_SRAMSZ_M 0x30000000U +#define PMCTL_DESCEX_SRAMSZ_S 28U +#define PMCTL_DESCEX_SRAMSZ_SZ3 0x30000000U +#define PMCTL_DESCEX_SRAMSZ_SZ2 0x20000000U +#define PMCTL_DESCEX_SRAMSZ_SZ1 0x10000000U +#define PMCTL_DESCEX_SRAMSZ_SZ0 0x00000000U + +// Field: [27] TSD +// +// TSD (thermal shutdown) IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define PMCTL_DESCEX_TSD 0x08000000U +#define PMCTL_DESCEX_TSD_M 0x08000000U +#define PMCTL_DESCEX_TSD_S 27U +#define PMCTL_DESCEX_TSD_IP_AVAIL 0x08000000U +#define PMCTL_DESCEX_TSD_IP_UNAVAIL 0x00000000U + +// Field: [26] LPCMP +// +// LPCMP (low power comparator) IP status on device +// ENUMs: +// IP_AVAIL IP is available +// IP_UNAVAIL IP is unavailable +#define PMCTL_DESCEX_LPCMP 0x04000000U +#define PMCTL_DESCEX_LPCMP_M 0x04000000U +#define PMCTL_DESCEX_LPCMP_S 26U +#define PMCTL_DESCEX_LPCMP_IP_AVAIL 0x04000000U +#define PMCTL_DESCEX_LPCMP_IP_UNAVAIL 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_SHTDWN +// +//***************************************************************************** +// Field: [15:0] KEY +// +// Setting a valid key will trigger the device to enter SHUTDOWN mode. +// ENUMs: +// VALID This is the only valid key value that will trigger +// SHUTDOWN mode. +// All other values are +// invalid and will have no effect. +#define PMCTL_SHTDWN_KEY_W 16U +#define PMCTL_SHTDWN_KEY_M 0x0000FFFFU +#define PMCTL_SHTDWN_KEY_S 0U +#define PMCTL_SHTDWN_KEY_VALID 0x0000A5A5U + +//***************************************************************************** +// +// Register: PMCTL_O_SLPCTL +// +//***************************************************************************** +// Field: [0] SLPN +// +// The boot code will set this bit field and disable sleep mode, automatically +// unless waking up from a SHUTDOWN RSTSTA.SDDET is set. +// Application software must reconfigure the state for all IO's before setting +// this bit field upon waking up from a SHUTDOWN to avoid glitches on pins. +// ENUMs: +// DIS I/O pad sleep mode is disabled +// EN I/O pad sleep mode is enabled +#define PMCTL_SLPCTL_SLPN 0x00000001U +#define PMCTL_SLPCTL_SLPN_M 0x00000001U +#define PMCTL_SLPCTL_SLPN_S 0U +#define PMCTL_SLPCTL_SLPN_DIS 0x00000001U +#define PMCTL_SLPCTL_SLPN_EN 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_WUSTA +// +//***************************************************************************** +// Field: [1:0] SRC +// +// This field shows the device wakeup source. +// ENUMs: +// STBY Wakeup from STANDBY mode. +// RST_SHTDWN Wakeup from system reset / SHUTDOWN mode. +// See RSTSTA for more +// status information. +#define PMCTL_WUSTA_SRC_W 2U +#define PMCTL_WUSTA_SRC_M 0x00000003U +#define PMCTL_WUSTA_SRC_S 0U +#define PMCTL_WUSTA_SRC_STBY 0x00000002U +#define PMCTL_WUSTA_SRC_RST_SHTDWN 0x00000001U + +//***************************************************************************** +// +// Register: PMCTL_O_VDDRCTL +// +//***************************************************************************** +// Field: [1] STBY +// +// Select between continuous or duty-cycled VDDR regulation in STANDBY mode. +// ENUMs: +// PSUEDO Continuous VDDR regulation in STANDBY mode. +// NORMAL Duty-cycled VDDR regulation in STANDBY mode. +#define PMCTL_VDDRCTL_STBY 0x00000002U +#define PMCTL_VDDRCTL_STBY_M 0x00000002U +#define PMCTL_VDDRCTL_STBY_S 1U +#define PMCTL_VDDRCTL_STBY_PSUEDO 0x00000002U +#define PMCTL_VDDRCTL_STBY_NORMAL 0x00000000U + +// Field: [0] SELECT +// +// Select between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY +// mode). +// ENUMs: +// DCDC DCDC enabled for regulation of VDDR voltage +// GLDO GLDO enabled for regulation of VDDR voltage +#define PMCTL_VDDRCTL_SELECT 0x00000001U +#define PMCTL_VDDRCTL_SELECT_M 0x00000001U +#define PMCTL_VDDRCTL_SELECT_S 0U +#define PMCTL_VDDRCTL_SELECT_DCDC 0x00000001U +#define PMCTL_VDDRCTL_SELECT_GLDO 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_SYSFSET +// +//***************************************************************************** +// Field: [2] FLAG2 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSET_FLAG2 0x00000004U +#define PMCTL_SYSFSET_FLAG2_M 0x00000004U +#define PMCTL_SYSFSET_FLAG2_S 2U +#define PMCTL_SYSFSET_FLAG2_SET 0x00000004U +#define PMCTL_SYSFSET_FLAG2_NOEFF 0x00000000U + +// Field: [1] FLAG1 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSET_FLAG1 0x00000002U +#define PMCTL_SYSFSET_FLAG1_M 0x00000002U +#define PMCTL_SYSFSET_FLAG1_S 1U +#define PMCTL_SYSFSET_FLAG1_SET 0x00000002U +#define PMCTL_SYSFSET_FLAG1_NOEFF 0x00000000U + +// Field: [0] FLAG0 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSET_FLAG0 0x00000001U +#define PMCTL_SYSFSET_FLAG0_M 0x00000001U +#define PMCTL_SYSFSET_FLAG0_S 0U +#define PMCTL_SYSFSET_FLAG0_SET 0x00000001U +#define PMCTL_SYSFSET_FLAG0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_SYSFCLR +// +//***************************************************************************** +// Field: [2] FLAG2 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// CLR Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFCLR_FLAG2 0x00000004U +#define PMCTL_SYSFCLR_FLAG2_M 0x00000004U +#define PMCTL_SYSFCLR_FLAG2_S 2U +#define PMCTL_SYSFCLR_FLAG2_CLR 0x00000004U +#define PMCTL_SYSFCLR_FLAG2_NOEFF 0x00000000U + +// Field: [1] FLAG1 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// CLR Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFCLR_FLAG1 0x00000002U +#define PMCTL_SYSFCLR_FLAG1_M 0x00000002U +#define PMCTL_SYSFCLR_FLAG1_S 1U +#define PMCTL_SYSFCLR_FLAG1_CLR 0x00000002U +#define PMCTL_SYSFCLR_FLAG1_NOEFF 0x00000000U + +// Field: [0] FLAG0 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// CLR Internal. Only to be used through TI provided API. +// NOEFF Internal. Only to be used through TI provided API. +#define PMCTL_SYSFCLR_FLAG0 0x00000001U +#define PMCTL_SYSFCLR_FLAG0_M 0x00000001U +#define PMCTL_SYSFCLR_FLAG0_S 0U +#define PMCTL_SYSFCLR_FLAG0_CLR 0x00000001U +#define PMCTL_SYSFCLR_FLAG0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_SYSFSTA +// +//***************************************************************************** +// Field: [2] FLAG2 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL1 Internal. Only to be used through TI provided API. +// VAL0 Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSTA_FLAG2 0x00000004U +#define PMCTL_SYSFSTA_FLAG2_M 0x00000004U +#define PMCTL_SYSFSTA_FLAG2_S 2U +#define PMCTL_SYSFSTA_FLAG2_VAL1 0x00000004U +#define PMCTL_SYSFSTA_FLAG2_VAL0 0x00000000U + +// Field: [1] FLAG1 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL1 Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSTA_FLAG1 0x00000002U +#define PMCTL_SYSFSTA_FLAG1_M 0x00000002U +#define PMCTL_SYSFSTA_FLAG1_S 1U +#define PMCTL_SYSFSTA_FLAG1_VAL1 0x00000002U + +// Field: [0] FLAG0 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL1 Internal. Only to be used through TI provided API. +// VAL0 Internal. Only to be used through TI provided API. +#define PMCTL_SYSFSTA_FLAG0 0x00000001U +#define PMCTL_SYSFSTA_FLAG0_M 0x00000001U +#define PMCTL_SYSFSTA_FLAG0_S 0U +#define PMCTL_SYSFSTA_FLAG0_VAL1 0x00000001U +#define PMCTL_SYSFSTA_FLAG0_VAL0 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_RSTCTL +// +//***************************************************************************** +// Field: [2] LFLOSS +// +// LF clock loss reset enable. +// Trigger system reset when LF clock loss is detected, which reset the entire +// device and causes a reboot of the system. +// The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and +// RSTSTA.SYSSRC set to LFLOSSEV. +// ENUMs: +// ARMED LF clock loss detection will trigger a system +// reset. +// DISARMED LF clock loss detection will not trigger a system +// reset. +#define PMCTL_RSTCTL_LFLOSS 0x00000004U +#define PMCTL_RSTCTL_LFLOSS_M 0x00000004U +#define PMCTL_RSTCTL_LFLOSS_S 2U +#define PMCTL_RSTCTL_LFLOSS_ARMED 0x00000004U +#define PMCTL_RSTCTL_LFLOSS_DISARMED 0x00000000U + +// Field: [1] TSDEN +// +// TSD (Thermal Shutdown) enable. +// TSD will trigger an immediate system reset, which reset the entire device +// and causes a reboot of the system. +// The device will be in reset until released by the TSD IP. +// The system reset event is captured as RSTSTA.TSDEV flag set. +// ENUMs: +// EN Temperature shutdown comparator enable. +// Note: If TSD IP not +// present, see DESCEX.TSD, enable will have no +// effect. +// NOEFF No effect +#define PMCTL_RSTCTL_TSDEN 0x00000002U +#define PMCTL_RSTCTL_TSDEN_M 0x00000002U +#define PMCTL_RSTCTL_TSDEN_S 1U +#define PMCTL_RSTCTL_TSDEN_EN 0x00000002U +#define PMCTL_RSTCTL_TSDEN_NOEFF 0x00000000U + +// Field: [0] SYSRST +// +// Trigger system reset, which will reset the entire device and causes a reboot +// of the system. +// The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and +// RSTSTA.SYSSRC set to SYSRSTEV. +// ENUMs: +// SET Trigger a system reset. +// NOEFF No effect +#define PMCTL_RSTCTL_SYSRST 0x00000001U +#define PMCTL_RSTCTL_SYSRST_M 0x00000001U +#define PMCTL_RSTCTL_SYSRST_S 0U +#define PMCTL_RSTCTL_SYSRST_SET 0x00000001U +#define PMCTL_RSTCTL_SYSRST_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_RSTSTA +// +//***************************************************************************** +// Field: [17] SDDET +// +// Wakeup from SHUTDOWN flag. +// Note: This flag will be cleared when SLPCTL.SLPN is asserted. +// ENUMs: +// TRIG Wakeup from SHUTDOWN mode +// NO_TRIG Wakeup from SHUTDOWN mode not triggered +#define PMCTL_RSTSTA_SDDET 0x00020000U +#define PMCTL_RSTSTA_SDDET_M 0x00020000U +#define PMCTL_RSTSTA_SDDET_S 17U +#define PMCTL_RSTSTA_SDDET_TRIG 0x00020000U +#define PMCTL_RSTSTA_SDDET_NO_TRIG 0x00000000U + +// Field: [16] IOWUSD +// +// Wakeup from SHUTDOWN on an I/O event flag. +// Note: This flag will be cleared when SLPCTL.SLPN is asserted. +// ENUMs: +// TRIG Wakeup from SHUTDOWN triggered by an I/O event. +// NO_TRIG Wakeup from SHUTDOWN not triggered by an I/O +// event. +#define PMCTL_RSTSTA_IOWUSD 0x00010000U +#define PMCTL_RSTSTA_IOWUSD_M 0x00010000U +#define PMCTL_RSTSTA_IOWUSD_S 16U +#define PMCTL_RSTSTA_IOWUSD_TRIG 0x00010000U +#define PMCTL_RSTSTA_IOWUSD_NO_TRIG 0x00000000U + +// Field: [7:4] SYSSRC +// +// Shows which reset event that triggered SYSRESET in RESETSRC +// ENUMs: +// DERREV Digital Error reset event +// AERREV Analog Error reset event +// AFSMEV Analog FSM timeout event +// SWDRSTEV Serial Wire Debug reset event +// SYSRSTEV System reset event +// WDTEV Watchdog timeout event +// LOCKUPEV CPU LOCKUP event +// CPURSTEV CPU reset event +// LFLOSSEV LF clock loss event +#define PMCTL_RSTSTA_SYSSRC_W 4U +#define PMCTL_RSTSTA_SYSSRC_M 0x000000F0U +#define PMCTL_RSTSTA_SYSSRC_S 4U +#define PMCTL_RSTSTA_SYSSRC_DERREV 0x000000F0U +#define PMCTL_RSTSTA_SYSSRC_AERREV 0x000000E0U +#define PMCTL_RSTSTA_SYSSRC_AFSMEV 0x00000060U +#define PMCTL_RSTSTA_SYSSRC_SWDRSTEV 0x00000050U +#define PMCTL_RSTSTA_SYSSRC_SYSRSTEV 0x00000040U +#define PMCTL_RSTSTA_SYSSRC_WDTEV 0x00000030U +#define PMCTL_RSTSTA_SYSSRC_LOCKUPEV 0x00000020U +#define PMCTL_RSTSTA_SYSSRC_CPURSTEV 0x00000010U +#define PMCTL_RSTSTA_SYSSRC_LFLOSSEV 0x00000000U + +// Field: [3] TSDEV +// +// System reset triggered by TSD event +// ENUMs: +// TRIG System reset triggered by TSD event +// NO_TRIG TSD event not triggered +#define PMCTL_RSTSTA_TSDEV 0x00000008U +#define PMCTL_RSTSTA_TSDEV_M 0x00000008U +#define PMCTL_RSTSTA_TSDEV_S 3U +#define PMCTL_RSTSTA_TSDEV_TRIG 0x00000008U +#define PMCTL_RSTSTA_TSDEV_NO_TRIG 0x00000000U + +// Field: [2:0] RESETSRC +// +// Shows the root cause of the last system reset. More than one reported reset +// source can have been active during the last system reset, but only the root +// cause is reported. +// If reset cause is SYSRESET or PINRESET, the other reset flags must be read +// to determine actual root cause. +// ENUMs: +// SYSRESET Digital system reset. Actual root cause is given +// by SYSSRC. +// VDDRLOSS Brown out detect on VDDR +// VDDSLOSS Brown out detect on VDDS +// PINRESET Reset pin. TSD will also trigger a pin reset, so +// actual root cause is given by TSDEV reset flag +// status. +// PWRON Power on reset +#define PMCTL_RSTSTA_RESETSRC_W 3U +#define PMCTL_RSTSTA_RESETSRC_M 0x00000007U +#define PMCTL_RSTSTA_RESETSRC_S 0U +#define PMCTL_RSTSTA_RESETSRC_SYSRESET 0x00000006U +#define PMCTL_RSTSTA_RESETSRC_VDDRLOSS 0x00000004U +#define PMCTL_RSTSTA_RESETSRC_VDDSLOSS 0x00000002U +#define PMCTL_RSTSTA_RESETSRC_PINRESET 0x00000001U +#define PMCTL_RSTSTA_RESETSRC_PWRON 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_BOOTSTA +// +//***************************************************************************** +// Field: [7:0] FLAG +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// APP_FAULT_HANDLER Internal. Only to be used through TI provided API. +// APP_FAIL_APPTRANSFER Internal. Only to be used through TI provided API. +// APP_FAIL_NOAPP Internal. Only to be used through TI provided API. +// APP_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. +// MODE_APP Internal. Only to be used through TI provided API. +// BLDR_FAULT_HANDLER Internal. Only to be used through TI provided API. +// BLDR_FAIL_APPTRANSFER Internal. Only to be used through TI provided API. +// BLDR_FAIL_EXECUTION_CONTEXTInternal. Only to be used through TI provided +// API. +// BLDR_CMD_PROCESSING Internal. Only to be used through TI provided API. +// BLDR_CMD_IDLE Internal. Only to be used through TI provided API. +// BLDR_STARTED Internal. Only to be used through TI provided API. +// BLDR_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. +// MODE_BLDR Internal. Only to be used through TI provided API. +// BOOT_FAULT_HANDLER Internal. Only to be used through TI provided API. +// BOOT_FAIL_SRAM_REPAIR Internal. Only to be used through TI provided API. +// BOOT_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. +// BOOT_EXITED_SACI Internal. Only to be used through TI provided API. +// BOOT_WAIT_SWD_DISCONNECT Internal. Only to be used through TI provided API. +// BOOT_ENTERED_SACI Internal. Only to be used through TI provided API. +// BOOT_GENERAL_TRIMS Internal. Only to be used through TI provided API. +// BOOT_SRAM_REP_DONE Internal. Only to be used through TI provided API. +// BOOT_COLD_BOOT Internal. Only to be used through TI provided API. +// BOOT_RESET Internal. Only to be used through TI provided API. +#define PMCTL_BOOTSTA_FLAG_W 8U +#define PMCTL_BOOTSTA_FLAG_M 0x000000FFU +#define PMCTL_BOOTSTA_FLAG_S 0U +#define PMCTL_BOOTSTA_FLAG_APP_FAULT_HANDLER 0x000000FFU +#define PMCTL_BOOTSTA_FLAG_APP_FAIL_APPTRANSFER 0x000000FEU +#define PMCTL_BOOTSTA_FLAG_APP_FAIL_NOAPP 0x000000FDU +#define PMCTL_BOOTSTA_FLAG_APP_WAITLOOP_DBGPROBE 0x000000C1U +#define PMCTL_BOOTSTA_FLAG_MODE_APP 0x000000C0U +#define PMCTL_BOOTSTA_FLAG_BLDR_FAULT_HANDLER 0x000000BFU +#define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_APPTRANSFER 0x000000BEU +#define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_EXECUTION_CONTEXT 0x000000BDU +#define PMCTL_BOOTSTA_FLAG_BLDR_CMD_PROCESSING 0x000000BCU +#define PMCTL_BOOTSTA_FLAG_BLDR_CMD_IDLE 0x000000BBU +#define PMCTL_BOOTSTA_FLAG_BLDR_STARTED 0x000000BAU +#define PMCTL_BOOTSTA_FLAG_BLDR_WAITLOOP_DBGPROBE 0x00000081U +#define PMCTL_BOOTSTA_FLAG_MODE_BLDR 0x00000080U +#define PMCTL_BOOTSTA_FLAG_BOOT_FAULT_HANDLER 0x0000003FU +#define PMCTL_BOOTSTA_FLAG_BOOT_FAIL_SRAM_REPAIR 0x0000003EU +#define PMCTL_BOOTSTA_FLAG_BOOT_WAITLOOP_DBGPROBE 0x00000038U +#define PMCTL_BOOTSTA_FLAG_BOOT_EXITED_SACI 0x00000037U +#define PMCTL_BOOTSTA_FLAG_BOOT_WAIT_SWD_DISCONNECT 0x00000036U +#define PMCTL_BOOTSTA_FLAG_BOOT_ENTERED_SACI 0x00000020U +#define PMCTL_BOOTSTA_FLAG_BOOT_GENERAL_TRIMS 0x00000003U +#define PMCTL_BOOTSTA_FLAG_BOOT_SRAM_REP_DONE 0x00000002U +#define PMCTL_BOOTSTA_FLAG_BOOT_COLD_BOOT 0x00000001U +#define PMCTL_BOOTSTA_FLAG_BOOT_RESET 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_AONRSTA1 +// +//***************************************************************************** +// Field: [17:0] FLAG +// +// State of the AON register flags +#define PMCTL_AONRSTA1_FLAG_W 18U +#define PMCTL_AONRSTA1_FLAG_M 0x0003FFFFU +#define PMCTL_AONRSTA1_FLAG_S 0U + +//***************************************************************************** +// +// Register: PMCTL_O_AONRSET1 +// +//***************************************************************************** +// Field: [17:0] FLAG +// +// Write 1 to set AONRSTA1.FLAG +// ENUMs: +// ALL_SET Set all flags +// NOEFF No flags changed status +#define PMCTL_AONRSET1_FLAG_W 18U +#define PMCTL_AONRSET1_FLAG_M 0x0003FFFFU +#define PMCTL_AONRSET1_FLAG_S 0U +#define PMCTL_AONRSET1_FLAG_ALL_SET 0x0003FFFFU +#define PMCTL_AONRSET1_FLAG_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_AONRCLR1 +// +//***************************************************************************** +// Field: [17:0] FLAG +// +// Write 1 to clear AONRSTA1.FLAG +// ENUMs: +// ALL_CLR Clear all flags +// NOEFF No flags changed status +#define PMCTL_AONRCLR1_FLAG_W 18U +#define PMCTL_AONRCLR1_FLAG_M 0x0003FFFFU +#define PMCTL_AONRCLR1_FLAG_S 0U +#define PMCTL_AONRCLR1_FLAG_ALL_CLR 0x0003FFFFU +#define PMCTL_AONRCLR1_FLAG_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: PMCTL_O_ETPP +// +//***************************************************************************** +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG0 +// +//***************************************************************************** +// Field: [0] VAL +// +// Internal. Only to be used through TI provided API. +#define PMCTL_RETCFG0_VAL 0x00000001U +#define PMCTL_RETCFG0_VAL_M 0x00000001U +#define PMCTL_RETCFG0_VAL_S 0U + +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG1 +// +//***************************************************************************** +// Field: [0] VAL +// +// Internal. Only to be used through TI provided API. +#define PMCTL_RETCFG1_VAL 0x00000001U +#define PMCTL_RETCFG1_VAL_M 0x00000001U +#define PMCTL_RETCFG1_VAL_S 0U + +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG2 +// +//***************************************************************************** +// Field: [2:0] VAL +// +// Internal. Only to be used through TI provided API. +#define PMCTL_RETCFG2_VAL_W 3U +#define PMCTL_RETCFG2_VAL_M 0x00000007U +#define PMCTL_RETCFG2_VAL_S 0U + +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG5 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG6 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: PMCTL_O_RETCFG7 +// +//***************************************************************************** + +#endif // __PMCTL__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h new file mode 100644 index 00000000..58c83efd --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h @@ -0,0 +1,930 @@ +/****************************************************************************** +* Filename: hw_pmud_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_PMUD_H__ +#define __HW_PMUD_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PMUD component +// +//***************************************************************************** +// Control +#define PMUD_O_CTL 0x00000000U + +// Internal. Only to be used through TI provided API. +#define PMUD_O_MEASCFG 0x00000004U + +// Last Measured Battery Voltage +#define PMUD_O_BAT 0x00000028U + +// Battery Update +#define PMUD_O_BATUPD 0x0000002CU + +// Last measured Temperature in Degree Celsius +#define PMUD_O_TEMP 0x00000030U + +// Temperature Update +#define PMUD_O_TEMPUPD 0x00000034U + +// Event Mask +#define PMUD_O_EVENTMASK 0x00000048U + +// Event +#define PMUD_O_EVENT 0x0000004CU + +// Battery Upper Limit +#define PMUD_O_BATTUL 0x00000050U + +// Battery Lower Limit +#define PMUD_O_BATTLL 0x00000054U + +// Temperature Upper Limit +#define PMUD_O_TEMPUL 0x00000058U + +// Temperature Lower Limit +#define PMUD_O_TEMPLL 0x0000005CU + +// Internal. Only to be used through TI provided API. +#define PMUD_O_PREG0 0x00000090U + +// Internal. Only to be used through TI provided API. +#define PMUD_O_PREG1 0x00000094U + +// Internal. Only to be used through TI provided API. +#define PMUD_O_PREG2 0x00000098U + +// DCDC configuration +#define PMUD_O_DCDCCFG 0x0000009CU + +// DCDC status +#define PMUD_O_DCDCSTAT 0x000000A0U + +//***************************************************************************** +// +// Register: PMUD_O_CTL +// +//***************************************************************************** +// Field: [2] HYST_EN +// +// Enables hysteresis on both battery and temperature measurements. +// ENUMs: +// EN Enable +// DIS Disable +#define PMUD_CTL_HYST_EN 0x00000004U +#define PMUD_CTL_HYST_EN_M 0x00000004U +#define PMUD_CTL_HYST_EN_S 2U +#define PMUD_CTL_HYST_EN_EN 0x00000004U +#define PMUD_CTL_HYST_EN_DIS 0x00000000U + +// Field: [1] CALC_EN +// +// Configuration of the calculation block that converts the digital +// battery/temperature level to a Volt/Celsius value. +// ENUMs: +// EN Calculation enabled +// DIS Calculation disabled +#define PMUD_CTL_CALC_EN 0x00000002U +#define PMUD_CTL_CALC_EN_M 0x00000002U +#define PMUD_CTL_CALC_EN_S 1U +#define PMUD_CTL_CALC_EN_EN 0x00000002U +#define PMUD_CTL_CALC_EN_DIS 0x00000000U + +// Field: [0] MEAS_EN +// +// Configuration of the measurement block that interfaces with the analog +// domain. +// ENUMs: +// EN Measurements enabled (battery voltage and +// temperature) +// DIS Measurements disabled +#define PMUD_CTL_MEAS_EN 0x00000001U +#define PMUD_CTL_MEAS_EN_M 0x00000001U +#define PMUD_CTL_MEAS_EN_S 0U +#define PMUD_CTL_MEAS_EN_EN 0x00000001U +#define PMUD_CTL_MEAS_EN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// _32CYC Internal. Only to be used through TI provided API. +// _16CYC Internal. Only to be used through TI provided API. +// _8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define PMUD_MEASCFG_PER_W 2U +#define PMUD_MEASCFG_PER_M 0x00000003U +#define PMUD_MEASCFG_PER_S 0U +#define PMUD_MEASCFG_PER__32CYC 0x00000003U +#define PMUD_MEASCFG_PER__16CYC 0x00000002U +#define PMUD_MEASCFG_PER__8CYC 0x00000001U +#define PMUD_MEASCFG_PER_CONT 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: Battery voltage = 0V + fractional part +// ... +// 0x3: Battery voltage = 3V + fractional part +// 0x4: Battery voltage = 4V + fractional part +#define PMUD_BAT_INT_W 3U +#define PMUD_BAT_INT_M 0x00000700U +#define PMUD_BAT_INT_S 8U + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V +#define PMUD_BAT_FRAC_W 8U +#define PMUD_BAT_FRAC_M 0x000000FFU +#define PMUD_BAT_FRAC_S 0U + +//***************************************************************************** +// +// Register: PMUD_O_BATUPD +// +//***************************************************************************** +// Field: [0] STA +// +// Battery update status. Write 1 to clear the status. +// ENUMs: +// UPD New battery voltage present +// NOUPD No update since last clear +#define PMUD_BATUPD_STA 0x00000001U +#define PMUD_BATUPD_STA_M 0x00000001U +#define PMUD_BATUPD_STA_S 0U +#define PMUD_BATUPD_STA_UPD 0x00000001U +#define PMUD_BATUPD_STA_NOUPD 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part of temperature value (signed) +// Total value = INT + FRAC +// 2's complement encoding +// +// 0x100: Min value (-256°C) +// 0x1D8: -40°C +// 0x1FF: -1°C +// 0x00: 0°C +// 0x1B: 27°C +// 0x55: 85°C +// 0xFF: Max value (255°C) +#define PMUD_TEMP_INT_W 9U +#define PMUD_TEMP_INT_M 0x0001FF00U +#define PMUD_TEMP_INT_S 8U + +// Field: [7:6] FRAC +// +// Fractional part of temperature value. +// Total value = INT + FRAC +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0°C +// 01: 0.25°C +// 10: 0.5°C +// 11: 0.75°C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define PMUD_TEMP_FRAC_W 2U +#define PMUD_TEMP_FRAC_M 0x000000C0U +#define PMUD_TEMP_FRAC_S 6U + +//***************************************************************************** +// +// Register: PMUD_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STA +// +// Temperature update status. Write 1 to clear the status. +// ENUMs: +// UPD New temperature value present +// NOUPD No temperature update since last clear +#define PMUD_TEMPUPD_STA 0x00000001U +#define PMUD_TEMPUPD_STA_M 0x00000001U +#define PMUD_TEMPUPD_STA_S 0U +#define PMUD_TEMPUPD_STA_UPD 0x00000001U +#define PMUD_TEMPUPD_STA_NOUPD 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_EVENTMASK +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE_MASK +// +// 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON +// 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_TEMP_UPDATE_MASK 0x00000020U +#define PMUD_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020U +#define PMUD_EVENTMASK_TEMP_UPDATE_MASK_S 5U + +// Field: [4] BATT_UPDATE_MASK +// +// 1: EVENT.BATT_UPDATE contributes to combined event from BATMON +// 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_BATT_UPDATE_MASK 0x00000010U +#define PMUD_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010U +#define PMUD_EVENTMASK_BATT_UPDATE_MASK_S 4U + +// Field: [3] TEMP_BELOW_LL_MASK +// +// 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008U +#define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008U +#define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_S 3U + +// Field: [2] TEMP_OVER_UL_MASK +// +// 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON +// 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004U +#define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004U +#define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_S 2U + +// Field: [1] BATT_BELOW_LL_MASK +// +// 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002U +#define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002U +#define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_S 1U + +// Field: [0] BATT_OVER_UL_MASK +// +// 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON +// 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON +#define PMUD_EVENTMASK_BATT_OVER_UL_MASK 0x00000001U +#define PMUD_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001U +#define PMUD_EVENTMASK_BATT_OVER_UL_MASK_S 0U + +//***************************************************************************** +// +// Register: PMUD_O_EVENT +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE +// +// Alias to TEMPUPD.STA +#define PMUD_EVENT_TEMP_UPDATE 0x00000020U +#define PMUD_EVENT_TEMP_UPDATE_M 0x00000020U +#define PMUD_EVENT_TEMP_UPDATE_S 5U + +// Field: [4] BATT_UPDATE +// +// Alias to BATUPD.STA +#define PMUD_EVENT_BATT_UPDATE 0x00000010U +#define PMUD_EVENT_BATT_UPDATE_M 0x00000010U +#define PMUD_EVENT_BATT_UPDATE_S 4U + +// Field: [3] TEMP_BELOW_LL +// +// Read: +// 1: Temperature level is below the lower limit set by TEMPLL. +// 0: Temperature level is not below the lower limit set by TEMPLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define PMUD_EVENT_TEMP_BELOW_LL 0x00000008U +#define PMUD_EVENT_TEMP_BELOW_LL_M 0x00000008U +#define PMUD_EVENT_TEMP_BELOW_LL_S 3U + +// Field: [2] TEMP_OVER_UL +// +// Read: +// 1: Temperature level is above the upper limit set by TEMPUL. +// 0: Temperature level is not above the upper limit set by TEMPUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define PMUD_EVENT_TEMP_OVER_UL 0x00000004U +#define PMUD_EVENT_TEMP_OVER_UL_M 0x00000004U +#define PMUD_EVENT_TEMP_OVER_UL_S 2U + +// Field: [1] BATT_BELOW_LL +// +// Read: +// 1: Battery level is below the lower limit set by BATTLL. +// 0: Battery level is not below the lower limit set by BATTLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define PMUD_EVENT_BATT_BELOW_LL 0x00000002U +#define PMUD_EVENT_BATT_BELOW_LL_M 0x00000002U +#define PMUD_EVENT_BATT_BELOW_LL_S 1U + +// Field: [0] BATT_OVER_UL +// +// Read: +// 1: Battery level is above the upper limit set by BATTUL. +// 0: Battery level is not above the upper limit set by BATTUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define PMUD_EVENT_BATT_OVER_UL 0x00000001U +#define PMUD_EVENT_BATT_OVER_UL_M 0x00000001U +#define PMUD_EVENT_BATT_OVER_UL_S 0U + +//***************************************************************************** +// +// Register: PMUD_O_BATTUL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// Total battery voltage = INT + FRAC (integer and fractional part) +// +// 0x0: Battery voltage = 0V + fractional part +// ... +// 0x3: Battery voltage = 3V + fractional part +// 0x4: Battery voltage = 4V + fractional part +#define PMUD_BATTUL_INT_W 3U +#define PMUD_BATTUL_INT_M 0x00000700U +#define PMUD_BATTUL_INT_S 8U + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V +#define PMUD_BATTUL_FRAC_W 8U +#define PMUD_BATTUL_FRAC_M 0x000000FFU +#define PMUD_BATTUL_FRAC_S 0U + +//***************************************************************************** +// +// Register: PMUD_O_BATTLL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// Total battery voltage = INT + FRAC (integer and fractional part) +// +// 0x0: Battery voltage = 0V + fractional part +// ... +// 0x3: Battery voltage = 3V + fractional part +// 0x4: Battery voltage = 4V + fractional part +#define PMUD_BATTLL_INT_W 3U +#define PMUD_BATTLL_INT_M 0x00000700U +#define PMUD_BATTLL_INT_S 8U + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V +#define PMUD_BATTLL_FRAC_W 8U +#define PMUD_BATTLL_FRAC_M 0x000000FFU +#define PMUD_BATTLL_FRAC_S 0U + +//***************************************************************************** +// +// Register: PMUD_O_TEMPUL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature upper limit. +// Total value = INT + FRAC +// 2's complement encoding +// +// 0x100: Min value (-256°C) +// 0x1D8: -40°C +// 0x1FF: -1°C +// 0x00: 0°C +// 0x1B: 27°C +// 0x55: 85°C +// 0xFF: Max value (255°C) +#define PMUD_TEMPUL_INT_W 9U +#define PMUD_TEMPUL_INT_M 0x0001FF00U +#define PMUD_TEMPUL_INT_S 8U + +// Field: [7:6] FRAC +// +// Fractional part of temperature upper limit. +// Total value = INT + FRAC +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0°C +// 01: 0.25°C +// 10: 0.5°C +// 11: 0.75°C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define PMUD_TEMPUL_FRAC_W 2U +#define PMUD_TEMPUL_FRAC_M 0x000000C0U +#define PMUD_TEMPUL_FRAC_S 6U + +//***************************************************************************** +// +// Register: PMUD_O_TEMPLL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature lower limit. +// Total value = INT + FRAC +// 2's complement encoding +// +// 0x100: Min value (-256°C) +// 0x1D8: -40°C +// 0x1FF: -1°C +// 0x00: 0°C +// 0x1B: 27°C +// 0x55: 85°C +// 0xFF: Max value (255°C) +#define PMUD_TEMPLL_INT_W 9U +#define PMUD_TEMPLL_INT_M 0x0001FF00U +#define PMUD_TEMPLL_INT_S 8U + +// Field: [7:6] FRAC +// +// Fractional part of temperature lower limit. +// Total value = INT + FRAC +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0°C +// 01: 0.25°C +// 10: 0.5°C +// 11: 0.75°C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define PMUD_TEMPLL_FRAC_W 2U +#define PMUD_TEMPLL_FRAC_M 0x000000C0U +#define PMUD_TEMPLL_FRAC_S 6U + +//***************************************************************************** +// +// Register: PMUD_O_PREG0 +// +//***************************************************************************** +// Field: [11] LOW_IPEAK_DIS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREG0_LOW_IPEAK_DIS 0x00000800U +#define PMUD_PREG0_LOW_IPEAK_DIS_M 0x00000800U +#define PMUD_PREG0_LOW_IPEAK_DIS_S 11U +#define PMUD_PREG0_LOW_IPEAK_DIS_SET 0x00000800U +#define PMUD_PREG0_LOW_IPEAK_DIS_CLR 0x00000000U + +// Field: [10] SOCLDO_ITESTEN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG0_SOCLDO_ITESTEN 0x00000400U +#define PMUD_PREG0_SOCLDO_ITESTEN_M 0x00000400U +#define PMUD_PREG0_SOCLDO_ITESTEN_S 10U +#define PMUD_PREG0_SOCLDO_ITESTEN_EN 0x00000400U +#define PMUD_PREG0_SOCLDO_ITESTEN_DIS 0x00000000U + +// Field: [9:7] SOCLDO_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// SOCLDO_VREF_AMP_OUT Internal. Only to be used through TI provided API. +// SOCLDO_ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define PMUD_PREG0_SOCLDO_ATBSEL_W 3U +#define PMUD_PREG0_SOCLDO_ATBSEL_M 0x00000380U +#define PMUD_PREG0_SOCLDO_ATBSEL_S 7U +#define PMUD_PREG0_SOCLDO_ATBSEL_VDD_AON 0x00000200U +#define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_VREF_AMP_OUT 0x00000100U +#define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_ITEST 0x00000080U +#define PMUD_PREG0_SOCLDO_ATBSEL_NC 0x00000000U + +// Field: [6:5] UDIGLDO_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL3 Internal. Only to be used through TI provided API. +// VAL2 Internal. Only to be used through TI provided API. +// VAL1 Internal. Only to be used through TI provided API. +// VAL0 Internal. Only to be used through TI provided API. +#define PMUD_PREG0_UDIGLDO_ATBSEL_W 2U +#define PMUD_PREG0_UDIGLDO_ATBSEL_M 0x00000060U +#define PMUD_PREG0_UDIGLDO_ATBSEL_S 5U +#define PMUD_PREG0_UDIGLDO_ATBSEL_VAL3 0x00000060U +#define PMUD_PREG0_UDIGLDO_ATBSEL_VAL2 0x00000040U +#define PMUD_PREG0_UDIGLDO_ATBSEL_VAL1 0x00000020U +#define PMUD_PREG0_UDIGLDO_ATBSEL_VAL0 0x00000000U + +// Field: [4:2] DIGLDO_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VAL4 Internal. Only to be used through TI provided API. +// VAL2 Internal. Only to be used through TI provided API. +// VAL1 Internal. Only to be used through TI provided API. +// VAL0 Internal. Only to be used through TI provided API. +#define PMUD_PREG0_DIGLDO_ATBSEL_W 3U +#define PMUD_PREG0_DIGLDO_ATBSEL_M 0x0000001CU +#define PMUD_PREG0_DIGLDO_ATBSEL_S 2U +#define PMUD_PREG0_DIGLDO_ATBSEL_VAL4 0x00000010U +#define PMUD_PREG0_DIGLDO_ATBSEL_VAL2 0x00000008U +#define PMUD_PREG0_DIGLDO_ATBSEL_VAL1 0x00000004U +#define PMUD_PREG0_DIGLDO_ATBSEL_VAL0 0x00000000U + +// Field: [1] SPARE +// +// Internal. Only to be used through TI provided API. +#define PMUD_PREG0_SPARE 0x00000002U +#define PMUD_PREG0_SPARE_M 0x00000002U +#define PMUD_PREG0_SPARE_S 1U + +// Field: [0] UDIGLDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG0_UDIGLDO_EN 0x00000001U +#define PMUD_PREG0_UDIGLDO_EN_M 0x00000001U +#define PMUD_PREG0_UDIGLDO_EN_S 0U +#define PMUD_PREG0_UDIGLDO_EN_EN 0x00000001U +#define PMUD_PREG0_UDIGLDO_EN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_PREG1 +// +//***************************************************************************** +// Field: [19] TEST_DCDC_NMOS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_TEST_DCDC_NMOS 0x00080000U +#define PMUD_PREG1_TEST_DCDC_NMOS_M 0x00080000U +#define PMUD_PREG1_TEST_DCDC_NMOS_S 19U +#define PMUD_PREG1_TEST_DCDC_NMOS_EN 0x00080000U +#define PMUD_PREG1_TEST_DCDC_NMOS_DIS 0x00000000U + +// Field: [18] TEST_DCDC_PMOS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_TEST_DCDC_PMOS 0x00040000U +#define PMUD_PREG1_TEST_DCDC_PMOS_M 0x00040000U +#define PMUD_PREG1_TEST_DCDC_PMOS_S 18U +#define PMUD_PREG1_TEST_DCDC_PMOS_EN 0x00040000U +#define PMUD_PREG1_TEST_DCDC_PMOS_DIS 0x00000000U + +// Field: [17] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_DITHER_EN 0x00020000U +#define PMUD_PREG1_DITHER_EN_M 0x00020000U +#define PMUD_PREG1_DITHER_EN_S 17U +#define PMUD_PREG1_DITHER_EN_EN 0x00020000U +#define PMUD_PREG1_DITHER_EN_DIS 0x00000000U + +// Field: [16] GLDO_AON +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_GLDO_AON 0x00010000U +#define PMUD_PREG1_GLDO_AON_M 0x00010000U +#define PMUD_PREG1_GLDO_AON_S 16U +#define PMUD_PREG1_GLDO_AON_EN 0x00010000U +#define PMUD_PREG1_GLDO_AON_DIS 0x00000000U + +// Field: [15] RCHG_BLK_VTRIG_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_RCHG_BLK_VTRIG_EN 0x00008000U +#define PMUD_PREG1_RCHG_BLK_VTRIG_EN_M 0x00008000U +#define PMUD_PREG1_RCHG_BLK_VTRIG_EN_S 15U +#define PMUD_PREG1_RCHG_BLK_VTRIG_EN_EN 0x00008000U +#define PMUD_PREG1_RCHG_BLK_VTRIG_EN_DIS 0x00000000U + +// Field: [14] RCHG_BLK_ATEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_RCHG_BLK_ATEST_EN 0x00004000U +#define PMUD_PREG1_RCHG_BLK_ATEST_EN_M 0x00004000U +#define PMUD_PREG1_RCHG_BLK_ATEST_EN_S 14U +#define PMUD_PREG1_RCHG_BLK_ATEST_EN_EN 0x00004000U +#define PMUD_PREG1_RCHG_BLK_ATEST_EN_DIS 0x00000000U + +// Field: [13] RCHG_FORCE_SAMP_VREF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_RCHG_FORCE_SAMP_VREF 0x00002000U +#define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_M 0x00002000U +#define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_S 13U +#define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_EN 0x00002000U +#define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_DIS 0x00000000U + +// Field: [12] RCHG_COMP_CLK_DIS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIS Internal. Only to be used through TI provided API. +// EN Internal. Only to be used through TI provided API. +#define PMUD_PREG1_RCHG_COMP_CLK_DIS 0x00001000U +#define PMUD_PREG1_RCHG_COMP_CLK_DIS_M 0x00001000U +#define PMUD_PREG1_RCHG_COMP_CLK_DIS_S 12U +#define PMUD_PREG1_RCHG_COMP_CLK_DIS_DIS 0x00001000U +#define PMUD_PREG1_RCHG_COMP_CLK_DIS_EN 0x00000000U + +// Field: [7] SPARE +// +// Internal. Only to be used through TI provided API. +#define PMUD_PREG1_SPARE 0x00000080U +#define PMUD_PREG1_SPARE_M 0x00000080U +#define PMUD_PREG1_SPARE_S 7U + +// Field: [6] VDDR_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define PMUD_PREG1_VDDR_ATBSEL 0x00000040U +#define PMUD_PREG1_VDDR_ATBSEL_M 0x00000040U +#define PMUD_PREG1_VDDR_ATBSEL_S 6U +#define PMUD_PREG1_VDDR_ATBSEL_EN 0x00000040U +#define PMUD_PREG1_VDDR_ATBSEL_DIS 0x00000000U + +// Field: [5] GLDO_EA_BIAS_DIS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// OFF Internal. Only to be used through TI provided API. +// ON Internal. Only to be used through TI provided API. +#define PMUD_PREG1_GLDO_EA_BIAS_DIS 0x00000020U +#define PMUD_PREG1_GLDO_EA_BIAS_DIS_M 0x00000020U +#define PMUD_PREG1_GLDO_EA_BIAS_DIS_S 5U +#define PMUD_PREG1_GLDO_EA_BIAS_DIS_OFF 0x00000020U +#define PMUD_PREG1_GLDO_EA_BIAS_DIS_ON 0x00000000U + +// Field: [4:1] GLDO_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDROK Internal. Only to be used through TI provided API. +// IB1U Internal. Only to be used through TI provided API. +// PASSGATE Internal. Only to be used through TI provided API. +// ERRAMP_OUT Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define PMUD_PREG1_GLDO_ATBSEL_W 4U +#define PMUD_PREG1_GLDO_ATBSEL_M 0x0000001EU +#define PMUD_PREG1_GLDO_ATBSEL_S 1U +#define PMUD_PREG1_GLDO_ATBSEL_VDDROK 0x00000010U +#define PMUD_PREG1_GLDO_ATBSEL_IB1U 0x00000008U +#define PMUD_PREG1_GLDO_ATBSEL_PASSGATE 0x00000004U +#define PMUD_PREG1_GLDO_ATBSEL_ERRAMP_OUT 0x00000002U +#define PMUD_PREG1_GLDO_ATBSEL_NC 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_PREG2 +// +//***************************************************************************** +// Field: [5] RSTNMASK +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BM Internal. Only to be used through TI provided API. +// BNM Internal. Only to be used through TI provided API. +#define PMUD_PREG2_RSTNMASK 0x00000020U +#define PMUD_PREG2_RSTNMASK_M 0x00000020U +#define PMUD_PREG2_RSTNMASK_S 5U +#define PMUD_PREG2_RSTNMASK_BM 0x00000020U +#define PMUD_PREG2_RSTNMASK_BNM 0x00000000U + +// Field: [4] DCDC_RCHG_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// RCHG_BLK Internal. Only to be used through TI provided API. +// DCDC_GLDO Internal. Only to be used through TI provided API. +#define PMUD_PREG2_DCDC_RCHG_ATBSEL 0x00000010U +#define PMUD_PREG2_DCDC_RCHG_ATBSEL_M 0x00000010U +#define PMUD_PREG2_DCDC_RCHG_ATBSEL_S 4U +#define PMUD_PREG2_DCDC_RCHG_ATBSEL_RCHG_BLK 0x00000010U +#define PMUD_PREG2_DCDC_RCHG_ATBSEL_DCDC_GLDO 0x00000000U + +// Field: [3:0] PMUREG_ATBSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DCDC_ATEST0_RCHG_ATEST1 Internal. Only to be used through TI provided API. +// SOCLDOI_A0 Internal. Only to be used through TI provided API. +// RESERVED Internal. Only to be used through TI provided API. +// SOCLDOV_A1 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define PMUD_PREG2_PMUREG_ATBSEL_W 4U +#define PMUD_PREG2_PMUREG_ATBSEL_M 0x0000000FU +#define PMUD_PREG2_PMUREG_ATBSEL_S 0U +#define PMUD_PREG2_PMUREG_ATBSEL_DCDC_ATEST0_RCHG_ATEST1 0x00000008U +#define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOI_A0 0x00000004U +#define PMUD_PREG2_PMUREG_ATBSEL_RESERVED 0x00000002U +#define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOV_A1 0x00000001U +#define PMUD_PREG2_PMUREG_ATBSEL_NC 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_DCDCCFG +// +//***************************************************************************** +// Field: [22:16] LM_HIGHTH +// +// DCDC load meter high threshold value for adaptive IPEAK adjustment. DCDC +// load meter output is in percentage scale so the applicable values are 'd1 to +// 'd100. Values from 'd101 to 'd127 are invalid and not to be used. +#define PMUD_DCDCCFG_LM_HIGHTH_W 7U +#define PMUD_DCDCCFG_LM_HIGHTH_M 0x007F0000U +#define PMUD_DCDCCFG_LM_HIGHTH_S 16U + +// Field: [14:8] LM_LOWTH +// +// DCDC load meter low threshold value for adaptive IPEAK adjustment. DCDC load +// meter output is in percentage scale so the applicable values are 'd1 to +// 'd100. Values from 'd101 to 'd127 are invalid and not to be used. +#define PMUD_DCDCCFG_LM_LOWTH_W 7U +#define PMUD_DCDCCFG_LM_LOWTH_M 0x00007F00U +#define PMUD_DCDCCFG_LM_LOWTH_S 8U + +// Field: [4] ADP_IPEAK_EN +// +// This bit is used to enable adaptive IPEAK adjustment scheme in hardware. +// When this bit is set, DCDC IPEAK value is automatically adjusted to suitable +// value by sensing the DCDC load meter output for better DCDC operational +// efficiency. +// ENUMs: +// EN Enable +// DIS Disable +#define PMUD_DCDCCFG_ADP_IPEAK_EN 0x00000010U +#define PMUD_DCDCCFG_ADP_IPEAK_EN_M 0x00000010U +#define PMUD_DCDCCFG_ADP_IPEAK_EN_S 4U +#define PMUD_DCDCCFG_ADP_IPEAK_EN_EN 0x00000010U +#define PMUD_DCDCCFG_ADP_IPEAK_EN_DIS 0x00000000U + +// Field: [0] LMEN +// +// This bit is used to enable DCDC load meter. Software can obtain DCDC load +// meter value from DCDCSTAT regiser and adjust IPEAK setting in SYS0.TDCDC +// register accordingly. +// ENUMs: +// EN Enable +// DIS Disable +#define PMUD_DCDCCFG_LMEN 0x00000001U +#define PMUD_DCDCCFG_LMEN_M 0x00000001U +#define PMUD_DCDCCFG_LMEN_S 0U +#define PMUD_DCDCCFG_LMEN_EN 0x00000001U +#define PMUD_DCDCCFG_LMEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: PMUD_O_DCDCSTAT +// +//***************************************************************************** +// Field: [10:8] IPEAK +// +// DCDC IPEAK value. This value is same as what is programmed in +// SYS0:TMUTE4.IPEAK when adaptive IPEAK adjustment scheme is not enabled, and +// it shows current IPEAK value applied by hardware when adaptive IPEAK +// adjustment scheme is enabled. +// Note: Software can only support IPEAK = 1 +#define PMUD_DCDCSTAT_IPEAK_W 3U +#define PMUD_DCDCSTAT_IPEAK_M 0x00000700U +#define PMUD_DCDCSTAT_IPEAK_S 8U + +// Field: [6:0] LOAD +// +// This indicates DCDC load meter output value in percentage scale. +// Applicable range is 'd1 to 'd100. +#define PMUD_DCDCSTAT_LOAD_W 7U +#define PMUD_DCDCSTAT_LOAD_M 0x0000007FU +#define PMUD_DCDCSTAT_LOAD_S 0U + + +#endif // __PMUD__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_rtc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_rtc.h new file mode 100644 index 00000000..b7569524 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_rtc.h @@ -0,0 +1,520 @@ +/****************************************************************************** +* Filename: hw_rtc_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_RTC_H__ +#define __HW_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RTC component +// +//***************************************************************************** +// Module Description +#define RTC_O_DESC 0x00000000U + +// RTC control Register +#define RTC_O_CTL 0x00000004U + +// Channel Arming Set +#define RTC_O_ARMSET 0x00000008U + +// Channel Arming Clear +#define RTC_O_ARMCLR 0x0000000CU + +// RTC Lower Time Slice +#define RTC_O_TIME8U 0x00000018U + +// RTC Upper Time Slice +#define RTC_O_TIME524M 0x0000001CU + +// Channel0 compare value +#define RTC_O_CH0CC8U 0x00000028U + +// Channel1 capture Value +#define RTC_O_CH1CC8U 0x00000038U + +// channel1 Input Configuration +#define RTC_O_CH1CFG 0x0000003CU + +// Interrupt mask +#define RTC_O_IMASK 0x00000044U + +// Raw interrupt status +#define RTC_O_RIS 0x00000048U + +// Masked interrupt status +#define RTC_O_MIS 0x0000004CU + +// Interrupt set +#define RTC_O_ISET 0x00000050U + +// Interrupt clear +#define RTC_O_ICLR 0x00000054U + +// Interrupt mask set +#define RTC_O_IMSET 0x00000058U + +// Interrupt clear +#define RTC_O_IMCLR 0x0000005CU + +// Emulation +#define RTC_O_EMU 0x00000060U + +//***************************************************************************** +// +// Register: RTC_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define RTC_DESC_MODID_W 16U +#define RTC_DESC_MODID_M 0xFFFF0000U +#define RTC_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define RTC_DESC_STDIPOFF_W 4U +#define RTC_DESC_STDIPOFF_M 0x0000F000U +#define RTC_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define RTC_DESC_INSTIDX_W 4U +#define RTC_DESC_INSTIDX_M 0x00000F00U +#define RTC_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define RTC_DESC_MAJREV_W 4U +#define RTC_DESC_MAJREV_M 0x000000F0U +#define RTC_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define RTC_DESC_MINREV_W 4U +#define RTC_DESC_MINREV_M 0x0000000FU +#define RTC_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: RTC_O_CTL +// +//***************************************************************************** +// Field: [0] RST +// +// RTC counter reset. Writing 1 to this bit will reset the RTC counter, and +// cause it to resume counting from 0x0 +// ENUMs: +// CLR Reset the timer. +// NOEFF No effect +#define RTC_CTL_RST 0x00000001U +#define RTC_CTL_RST_M 0x00000001U +#define RTC_CTL_RST_S 0U +#define RTC_CTL_RST_CLR 0x00000001U +#define RTC_CTL_RST_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_ARMSET +// +//***************************************************************************** +// Field: [1] CH1 +// +// Arming Channel 1 for capture operation. +// ENUMs: +// SET Enable the Channel 1 for capture operation +// NOEFF No effect on the channel +#define RTC_ARMSET_CH1 0x00000002U +#define RTC_ARMSET_CH1_M 0x00000002U +#define RTC_ARMSET_CH1_S 1U +#define RTC_ARMSET_CH1_SET 0x00000002U +#define RTC_ARMSET_CH1_NOEFF 0x00000000U + +// Field: [0] CH0 +// +// No effect on arming the channel. Read will give the status of the Channel 0. +// ENUMs: +// SET No effect on the compare channel +// NOEFF No effect on the channel +#define RTC_ARMSET_CH0 0x00000001U +#define RTC_ARMSET_CH0_M 0x00000001U +#define RTC_ARMSET_CH0_S 0U +#define RTC_ARMSET_CH0_SET 0x00000001U +#define RTC_ARMSET_CH0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_ARMCLR +// +//***************************************************************************** +// Field: [1] CH1 +// +// Disarming Channel 1 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a capture event happens in the +// same cycle +// NOEFF No effect on the channel +#define RTC_ARMCLR_CH1 0x00000002U +#define RTC_ARMCLR_CH1_M 0x00000002U +#define RTC_ARMCLR_CH1_S 1U +#define RTC_ARMCLR_CH1_CLR 0x00000002U +#define RTC_ARMCLR_CH1_NOEFF 0x00000000U + +// Field: [0] CH0 +// +// Disarming Channel 0 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare event happens in the +// same cycle +// NOEFF No effect on the channel +#define RTC_ARMCLR_CH0 0x00000001U +#define RTC_ARMCLR_CH0_M 0x00000001U +#define RTC_ARMCLR_CH0_S 0U +#define RTC_ARMCLR_CH0_CLR 0x00000001U +#define RTC_ARMCLR_CH0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_TIME8U +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Unsigned integer representing [34:3]slice of real time counter. +#define RTC_TIME8U_VAL_W 32U +#define RTC_TIME8U_VAL_M 0xFFFFFFFFU +#define RTC_TIME8U_VAL_S 0U + +//***************************************************************************** +// +// Register: RTC_O_TIME524M +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Unsigned integer representing. [50:19]slice of real time counter. +#define RTC_TIME524M_VAL_W 32U +#define RTC_TIME524M_VAL_M 0xFFFFFFFFU +#define RTC_TIME524M_VAL_S 0U + +//***************************************************************************** +// +// Register: RTC_O_CH0CC8U +// +//***************************************************************************** +// Field: [31:0] VAL +// +// RTC Channel 0 compare value. This value is compared against TIME8U.VAL. A +// Channel 0 event is generated when TIME8U.VAL value reaches or exceeds this +// compare value. +#define RTC_CH0CC8U_VAL_W 32U +#define RTC_CH0CC8U_VAL_M 0xFFFFFFFFU +#define RTC_CH0CC8U_VAL_S 0U + +//***************************************************************************** +// +// Register: RTC_O_CH1CC8U +// +//***************************************************************************** +// Field: [20:0] VAL +// +// TIME8U.VAL captured value at the last selected edge of capture event. +#define RTC_CH1CC8U_VAL_W 21U +#define RTC_CH1CC8U_VAL_M 0x001FFFFFU +#define RTC_CH1CC8U_VAL_S 0U + +//***************************************************************************** +// +// Register: RTC_O_CH1CFG +// +//***************************************************************************** +// Field: [0] EDGE +// +// Edge detect configuration for capture source +// ENUMs: +// FALL Falling Edge. +// RISE Rising Edge. +#define RTC_CH1CFG_EDGE 0x00000001U +#define RTC_CH1CFG_EDGE_M 0x00000001U +#define RTC_CH1CFG_EDGE_S 0U +#define RTC_CH1CFG_EDGE_FALL 0x00000001U +#define RTC_CH1CFG_EDGE_RISE 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_IMASK +// +//***************************************************************************** +// Field: [1] EV1 +// +// Channel 1 Event Interrupt Mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Clear Interrupt Mask +#define RTC_IMASK_EV1 0x00000002U +#define RTC_IMASK_EV1_M 0x00000002U +#define RTC_IMASK_EV1_S 1U +#define RTC_IMASK_EV1_EN 0x00000002U +#define RTC_IMASK_EV1_DIS 0x00000000U + +// Field: [0] EV0 +// +// Channel 0 Event Interrupt Mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define RTC_IMASK_EV0 0x00000001U +#define RTC_IMASK_EV0_M 0x00000001U +#define RTC_IMASK_EV0_S 0U +#define RTC_IMASK_EV0_EN 0x00000001U +#define RTC_IMASK_EV0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_RIS +// +//***************************************************************************** +// Field: [1] EV1 +// +// Raw interrupt status for Channel 1 event. +// This bit is set to 1 when a capture event is received on Channel 1. +// This bit will be cleared when the bit in ICLR.EV1 is set to 1 or when the +// captured time value is read from the CH1CC8U register. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define RTC_RIS_EV1 0x00000002U +#define RTC_RIS_EV1_M 0x00000002U +#define RTC_RIS_EV1_S 1U +#define RTC_RIS_EV1_SET 0x00000002U +#define RTC_RIS_EV1_CLR 0x00000000U + +// Field: [0] EV0 +// +// Raw interrupt status for Channel 0 event. +// This bit is set to 1 when a compare event occurs on Channel 0. +// This bit will be cleared. When the corresponding bit in ICLR.EV0 is set to +// 1. Or when a new compare value is written in CH0CC8U register +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define RTC_RIS_EV0 0x00000001U +#define RTC_RIS_EV0_M 0x00000001U +#define RTC_RIS_EV0_S 0U +#define RTC_RIS_EV0_SET 0x00000001U +#define RTC_RIS_EV0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_MIS +// +//***************************************************************************** +// Field: [1] EV1 +// +// Masked interrupt status for channel 1 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define RTC_MIS_EV1 0x00000002U +#define RTC_MIS_EV1_M 0x00000002U +#define RTC_MIS_EV1_S 1U +#define RTC_MIS_EV1_SET 0x00000002U +#define RTC_MIS_EV1_CLR 0x00000000U + +// Field: [0] EV0 +// +// Masked interrupt status for channel 0 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define RTC_MIS_EV0 0x00000001U +#define RTC_MIS_EV0_M 0x00000001U +#define RTC_MIS_EV0_S 0U +#define RTC_MIS_EV0_SET 0x00000001U +#define RTC_MIS_EV0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_ISET +// +//***************************************************************************** +// Field: [1] EV1 +// +// Set Channel 1 event Interrupt. +// ENUMs: +// SET Set interrupt +// NO_EFFECT Writing 0 has no effect +#define RTC_ISET_EV1 0x00000002U +#define RTC_ISET_EV1_M 0x00000002U +#define RTC_ISET_EV1_S 1U +#define RTC_ISET_EV1_SET 0x00000002U +#define RTC_ISET_EV1_NO_EFFECT 0x00000000U + +// Field: [0] EV0 +// +// Set Channel 0 event Interrupt. +// ENUMs: +// SET Set interrupt +// NO_EFFECT Writing 0 has no effect +#define RTC_ISET_EV0 0x00000001U +#define RTC_ISET_EV0_M 0x00000001U +#define RTC_ISET_EV0_S 0U +#define RTC_ISET_EV0_SET 0x00000001U +#define RTC_ISET_EV0_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_ICLR +// +//***************************************************************************** +// Field: [1] EV1 +// +// Clears channel 1 event interrupt. +// ENUMs: +// CLR Clear Interrupt +// NO_EFF Writing 0 has no effect +#define RTC_ICLR_EV1 0x00000002U +#define RTC_ICLR_EV1_M 0x00000002U +#define RTC_ICLR_EV1_S 1U +#define RTC_ICLR_EV1_CLR 0x00000002U +#define RTC_ICLR_EV1_NO_EFF 0x00000000U + +// Field: [0] EV0 +// +// Clears channel 0 event interrupt. +// ENUMs: +// CLR Clear Interrupt. +// NO_EFF Writing 0 has no effect +#define RTC_ICLR_EV0 0x00000001U +#define RTC_ICLR_EV0_M 0x00000001U +#define RTC_ICLR_EV0_S 0U +#define RTC_ICLR_EV0_CLR 0x00000001U +#define RTC_ICLR_EV0_NO_EFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_IMSET +// +//***************************************************************************** +// Field: [1] EV1 +// +// Set channel 1 event interrupt mask. +// ENUMs: +// SET Set interrupt mask +// NO_EFF Writing 0 has no effect +#define RTC_IMSET_EV1 0x00000002U +#define RTC_IMSET_EV1_M 0x00000002U +#define RTC_IMSET_EV1_S 1U +#define RTC_IMSET_EV1_SET 0x00000002U +#define RTC_IMSET_EV1_NO_EFF 0x00000000U + +// Field: [0] EV0 +// +// Set channel 0 event interrupt mask. +// ENUMs: +// SET Set interrupt mask +// NO_EFF Writing 0 has no effect +#define RTC_IMSET_EV0 0x00000001U +#define RTC_IMSET_EV0_M 0x00000001U +#define RTC_IMSET_EV0_S 0U +#define RTC_IMSET_EV0_SET 0x00000001U +#define RTC_IMSET_EV0_NO_EFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_IMCLR +// +//***************************************************************************** +// Field: [1] EV1 +// +// Clears Channel 1 event interrupt mask. +// ENUMs: +// CLR Clear Interrupt Mask +// NO_EFF Writing 0 has no effect +#define RTC_IMCLR_EV1 0x00000002U +#define RTC_IMCLR_EV1_M 0x00000002U +#define RTC_IMCLR_EV1_S 1U +#define RTC_IMCLR_EV1_CLR 0x00000002U +#define RTC_IMCLR_EV1_NO_EFF 0x00000000U + +// Field: [0] EV0 +// +// Clears Channel 0 event interrupt mask. +// ENUMs: +// CLR Clear Interrupt Mask +// NO_EFF Writing 0 has no effect +#define RTC_IMCLR_EV0 0x00000001U +#define RTC_IMCLR_EV0_M 0x00000001U +#define RTC_IMCLR_EV0_S 0U +#define RTC_IMCLR_EV0_CLR 0x00000001U +#define RTC_IMCLR_EV0_NO_EFF 0x00000000U + +//***************************************************************************** +// +// Register: RTC_O_EMU +// +//***************************************************************************** +// Field: [0] HALT +// +// Halt control. +// ENUMs: +// STOP Freeze option. The IP freezes functionality when +// the core halted input is asserted, and resumes +// when it is deasserted. The freeze can either be +// immediate or after the IP has reached a +// boundary from where it can resume without +// corruption. +// RUN Free run option. The IP ignores the state of the +// core halted input. +#define RTC_EMU_HALT 0x00000001U +#define RTC_EMU_HALT_M 0x00000001U +#define RTC_EMU_HALT_S 0U +#define RTC_EMU_HALT_STOP 0x00000001U +#define RTC_EMU_HALT_RUN 0x00000000U + + +#endif // __RTC__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scb.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scb.h new file mode 100644 index 00000000..a1d7a35a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scb.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* Filename: hw_scb_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SCB_H__ +#define __HW_SCB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SCB component +// +//***************************************************************************** +// CPUID Base Register +#define SCB_O_CPUID 0x00000000U + +// Interrupt Control State Register +#define SCB_O_ICSR 0x00000004U + +// Vector Table Offset Register +#define SCB_O_VTOR 0x00000008U + +// Application Interrupt and Reset Control Register +#define SCB_O_AIRCR 0x0000000CU + +// System Control Register +#define SCB_O_SCR 0x00000010U + +// Configuration and Control Register +#define SCB_O_CCR 0x00000014U + +// System Handler Priority Register 2 +#define SCB_O_SHPR2 0x0000001CU + +// System Handler Priority Register 3 +#define SCB_O_SHPR3 0x00000020U + +// System Handler Control and State Register +#define SCB_O_SHCSR 0x00000024U + +//***************************************************************************** +// +// Register: SCB_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code: 0x41 = ARM +#define SCB_CPUID_IMPLEMENTER_W 8U +#define SCB_CPUID_IMPLEMENTER_M 0xFF000000U +#define SCB_CPUID_IMPLEMENTER_S 24U + +// Field: [23:20] VARIANT +// +// Implementation defined variant number: 0x0 (for r0) +#define SCB_CPUID_VARIANT_W 4U +#define SCB_CPUID_VARIANT_M 0x00F00000U +#define SCB_CPUID_VARIANT_S 20U + +// Field: [19:16] CONSTANT +// +// Reads as 0xC +#define SCB_CPUID_CONSTANT_W 4U +#define SCB_CPUID_CONSTANT_M 0x000F0000U +#define SCB_CPUID_CONSTANT_S 16U + +// Field: [15:4] PARTNO +// +// Number of processor within family: 0xC20 +#define SCB_CPUID_PARTNO_W 12U +#define SCB_CPUID_PARTNO_M 0x0000FFF0U +#define SCB_CPUID_PARTNO_S 4U + +// Field: [3:0] REVISION +// +// Implementation defined revision number: 0x1 = processor p1 revision. +#define SCB_CPUID_REVISION_W 4U +#define SCB_CPUID_REVISION_M 0x0000000FU +#define SCB_CPUID_REVISION_S 0U + +//***************************************************************************** +// +// Register: SCB_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Setting this bit will activate an NMI. Since NMI is the highest priority +// exception, it will activate as soon as it is registered. Reads back with +// current state (1 if Pending, 0 if not). +// 0x0:No effect +// 0x1:Set pending nmi +#define SCB_ICSR_NMIPENDSET 0x80000000U +#define SCB_ICSR_NMIPENDSET_M 0x80000000U +#define SCB_ICSR_NMIPENDSET_S 31U + +// Field: [28] PENDSVSET +// +// Set pending PendSV bit. On reads this bit returns the pending state of +// PendSV +// 0x0:No effect +// 0x1:Set pending pendsv +#define SCB_ICSR_PENDSVSET 0x10000000U +#define SCB_ICSR_PENDSVSET_M 0x10000000U +#define SCB_ICSR_PENDSVSET_S 28U + +// Field: [27] PENDSVCLR +// +// Clear pending PendSV bit +// 0x0:No effect +// 0x1:Clear pending pendsv +#define SCB_ICSR_PENDSVCLR 0x08000000U +#define SCB_ICSR_PENDSVCLR_M 0x08000000U +#define SCB_ICSR_PENDSVCLR_S 27U + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. On reads this bit returns the pending state of +// SysTick. +// 0x0:No effect +// 0x1:Set pending systick +#define SCB_ICSR_PENDSTSET 0x04000000U +#define SCB_ICSR_PENDSTSET_M 0x04000000U +#define SCB_ICSR_PENDSTSET_S 26U + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// 0x0:No effect +// 0x1:Clear pending systick +#define SCB_ICSR_PENDSTCLR 0x02000000U +#define SCB_ICSR_PENDSTCLR_M 0x02000000U +#define SCB_ICSR_PENDSTCLR_S 25U + +// Field: [23] ISRPREEMPT +// +// The system can only access this bit when the core is halted. It indicates +// that a pending interrupt is to be taken in the next running cycle. If +// C_MASKINTS is clear in the Debug Halting Control and Status Register, the +// interrupt is serviced. +// 0x0:A pending exception is not serviced. +// 0x1:A pending exception is serviced on exit from the debug halt state +#define SCB_ICSR_ISRPREEMPT 0x00800000U +#define SCB_ICSR_ISRPREEMPT_M 0x00800000U +#define SCB_ICSR_ISRPREEMPT_S 23U + +// Field: [22] ISRPENDING +// +// External interrupt pending flag +// 0x0:Interrupt not pending +// 0x1:Interrupt pending +#define SCB_ICSR_ISRPENDING 0x00400000U +#define SCB_ICSR_ISRPENDING_M 0x00400000U +#define SCB_ICSR_ISRPENDING_S 22U + +// Field: [20:12] VECTPENDING +// +// Indicates the exception number for the highest priority pending exception: 0 +// = no pending exceptions. Non zero = The pending state includes the effect of +// memory-mapped enable and mask registers. It does not include the PRIMASK +// special-purpose register qualifier. +#define SCB_ICSR_VECTPENDING_W 9U +#define SCB_ICSR_VECTPENDING_M 0x001FF000U +#define SCB_ICSR_VECTPENDING_S 12U + +// Field: [8:0] VECTACTIVE +// +// Active exception number field. Reset clears the VECTACTIVE field. +#define SCB_ICSR_VECTACTIVE_W 9U +#define SCB_ICSR_VECTACTIVE_M 0x000001FFU +#define SCB_ICSR_VECTACTIVE_S 0U + +//***************************************************************************** +// +// Register: SCB_O_VTOR +// +//***************************************************************************** +// Field: [31:8] TBLOFF +// +// Bits [31:8] of the indicate the vector table offset address. +#define SCB_VTOR_TBLOFF_W 24U +#define SCB_VTOR_TBLOFF_M 0xFFFFFF00U +#define SCB_VTOR_TBLOFF_S 8U + +//***************************************************************************** +// +// Register: SCB_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. To write to other parts of this register, you must ensure +// 0x5FA is written into the VECTKEY field. +#define SCB_AIRCR_VECTKEY_W 16U +#define SCB_AIRCR_VECTKEY_M 0xFFFF0000U +#define SCB_AIRCR_VECTKEY_S 16U + +// Field: [15] ENDIANESS +// +// Data endianness bit. The read value depends on the endian configuration +// implemented +// 0x0:Little endian +// 0x1:Be-8 big-endian +#define SCB_AIRCR_ENDIANESS 0x00008000U +#define SCB_AIRCR_ENDIANESS_M 0x00008000U +#define SCB_AIRCR_ENDIANESS_S 15U + +// Field: [2] SYSRESETREQ +// +// Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to +// be asserted to request a reset. The intention is to force a large system +// reset of all major components except for debug. The C_HALT bit in the DHCSR +// is cleared as a result of the system reset requested. The debugger does not +// lose contact with the device. +#define SCB_AIRCR_SYSRESETREQ 0x00000004U +#define SCB_AIRCR_SYSRESETREQ_M 0x00000004U +#define SCB_AIRCR_SYSRESETREQ_S 2U + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for fixed and configurable exceptions. +// This bit: is self-clearing, can only be set by the DAP when the core is +// halted. When set: clears all active exception status of the processor, +// forces a return to Thread mode, forces an IPSR of 0. A debugger must +// re-initialize the stack. +#define SCB_AIRCR_VECTCLRACTIVE 0x00000002U +#define SCB_AIRCR_VECTCLRACTIVE_M 0x00000002U +#define SCB_AIRCR_VECTCLRACTIVE_S 1U + +//***************************************************************************** +// +// Register: SCB_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// When enabled, this causes WFE to wake up when an interrupt moves from +// inactive to pended. Otherwise, WFE only wakes up from an event signal, +// external and SEV instruction generated. The event input, RXEV, is registered +// even when not waiting for an event, and so effects the next WFE. +#define SCB_SCR_SEVONPEND 0x00000010U +#define SCB_SCR_SEVONPEND_M 0x00000010U +#define SCB_SCR_SEVONPEND_S 4U + +// Field: [2] SLEEPDEEP +// +// Sleep deep bit. +// ENUMs: +// DSLP_EN indicates to the system that Cortex-M0 clock can +// be stopped. Setting this bit causes the +// SLEEPDEEP port to be asserted when the +// processor can be stopped. +// DSLP_DIS not OK to turn off system clock +#define SCB_SCR_SLEEPDEEP 0x00000004U +#define SCB_SCR_SLEEPDEEP_M 0x00000004U +#define SCB_SCR_SLEEPDEEP_S 2U +#define SCB_SCR_SLEEPDEEP_DSLP_EN 0x00000004U +#define SCB_SCR_SLEEPDEEP_DSLP_DIS 0x00000000U + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// ENUMs: +// SLP_EN Sleep on return to thread mode +// SLP_DIS Do not sleep when returning to thread mode +#define SCB_SCR_SLEEPONEXIT 0x00000002U +#define SCB_SCR_SLEEPONEXIT_M 0x00000002U +#define SCB_SCR_SLEEPONEXIT_S 1U +#define SCB_SCR_SLEEPONEXIT_SLP_EN 0x00000002U +#define SCB_SCR_SLEEPONEXIT_SLP_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SCB_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Always set to 1. On exception entry, all exceptions are entered with 8-byte +// stack alignment and the context to restore it is saved. The SP is restored +// on the associated exception return. +#define SCB_CCR_STKALIGN 0x00000200U +#define SCB_CCR_STKALIGN_M 0x00000200U +#define SCB_CCR_STKALIGN_S 9U + +// Field: [3] UNALIGN_TRP +// +// Indicates that all unaligned accesses results in a Hard Fault. Trap for +// unaligned access is fixed at 1. +#define SCB_CCR_UNALIGN_TRP 0x00000008U +#define SCB_CCR_UNALIGN_TRP_M 0x00000008U +#define SCB_CCR_UNALIGN_TRP_S 3U + +//***************************************************************************** +// +// Register: SCB_O_SHPR2 +// +//***************************************************************************** +// Field: [31:30] PRI_11 +// +// Priority of system handler 11, SVCall +#define SCB_SHPR2_PRI_11_W 2U +#define SCB_SHPR2_PRI_11_M 0xC0000000U +#define SCB_SHPR2_PRI_11_S 30U + +//***************************************************************************** +// +// Register: SCB_O_SHPR3 +// +//***************************************************************************** +// Field: [31:30] PRI_15 +// +// Priority of system handler 15, SysTick +#define SCB_SHPR3_PRI_15_W 2U +#define SCB_SHPR3_PRI_15_M 0xC0000000U +#define SCB_SHPR3_PRI_15_S 30U + +// Field: [23:22] PRI_14 +// +// Priority of system handler 14, PendSV +#define SCB_SHPR3_PRI_14_W 2U +#define SCB_SHPR3_PRI_14_M 0x00C00000U +#define SCB_SHPR3_PRI_14_S 22U + +//***************************************************************************** +// +// Register: SCB_O_SHCSR +// +//***************************************************************************** +// Field: [15] SVCALLPENDED +// +// Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to +// clear pending SVCall. +#define SCB_SHCSR_SVCALLPENDED 0x00008000U +#define SCB_SHCSR_SVCALLPENDED_M 0x00008000U +#define SCB_SHCSR_SVCALLPENDED_S 15U + + +#endif // __SCB__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scscs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scscs.h new file mode 100644 index 00000000..7075d3dc --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_scscs.h @@ -0,0 +1,261 @@ +/****************************************************************************** +* Filename: hw_scscs_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SCSCS_H__ +#define __HW_SCSCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SCSCS component +// +//***************************************************************************** +// Peripheral ID Register 4 +#define SCSCS_O_PIDR4 0x00000010U + +// Peripheral ID Register 5 +#define SCSCS_O_PIDR5 0x00000014U + +// Peripheral ID Register 6 +#define SCSCS_O_PIDR6 0x00000018U + +// Peripheral ID Register 7 +#define SCSCS_O_PIDR7 0x0000001CU + +// Peripheral ID Register 0 +#define SCSCS_O_PIDR0 0x00000020U + +// Peripheral ID Register 1 +#define SCSCS_O_PIDR1 0x00000024U + +// Peripheral ID Register 2 +#define SCSCS_O_PIDR2 0x00000028U + +// Peripheral ID Register 3 +#define SCSCS_O_PIDR3 0x0000002CU + +// Component ID Register 0 +#define SCSCS_O_CIDR0 0x00000030U + +// Component ID Register 1 +#define SCSCS_O_CIDR1 0x00000034U + +// Component ID Register 2 +#define SCSCS_O_CIDR2 0x00000038U + +// Component ID Register 3 +#define SCSCS_O_CIDR3 0x0000003CU + +//***************************************************************************** +// +// Register: SCSCS_O_PIDR4 +// +//***************************************************************************** +// Field: [7:4] SIZE +// +// This is a 4-bit value that indicates the total contiguous size of the memory +// window used by this component in powers of 2 from the standard 4KB. If a +// component only requires the standard 4KB then this should read as 0x0, 4KB +// only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. +#define SCSCS_PIDR4_SIZE_W 4U +#define SCSCS_PIDR4_SIZE_M 0x000000F0U +#define SCSCS_PIDR4_SIZE_S 4U + +// Field: [3:0] DES_2 +// +// Number of JEDEC continuation codes. Indicates the designer of the component +// (along with the identity code) +#define SCSCS_PIDR4_DES_2_W 4U +#define SCSCS_PIDR4_DES_2_M 0x0000000FU +#define SCSCS_PIDR4_DES_2_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_PIDR5 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: SCSCS_O_PIDR6 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: SCSCS_O_PIDR7 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: SCSCS_O_PIDR0 +// +//***************************************************************************** +// Field: [7:0] PART_0 +// +// Bits [7:0] of the component's part number. This is selected by the designer +// of the component. +#define SCSCS_PIDR0_PART_0_W 8U +#define SCSCS_PIDR0_PART_0_M 0x000000FFU +#define SCSCS_PIDR0_PART_0_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_PIDR1 +// +//***************************************************************************** +// Field: [7:4] DES_0 +// +// Bits [3:0] of the JEDEC identity code indicating the designer of the +// component (along with the continuation code) +#define SCSCS_PIDR1_DES_0_W 4U +#define SCSCS_PIDR1_DES_0_M 0x000000F0U +#define SCSCS_PIDR1_DES_0_S 4U + +// Field: [3:0] PART_1 +// +// Bits [11:8] of the component's part number. This is selected by the designer +// of the component. +#define SCSCS_PIDR1_PART_1_W 4U +#define SCSCS_PIDR1_PART_1_M 0x0000000FU +#define SCSCS_PIDR1_PART_1_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_PIDR2 +// +//***************************************************************************** +// Field: [7:4] REVISION +// +// The Revision field is an incremental value starting at 0x0 for the first +// design of this component. This only increases by 1 for both major and minor +// revisions and is simply used as a look-up to establish the exact major/minor +// revision. +#define SCSCS_PIDR2_REVISION_W 4U +#define SCSCS_PIDR2_REVISION_M 0x000000F0U +#define SCSCS_PIDR2_REVISION_S 4U + +// Field: [3] JEDEC +// +// Always set. Indicates that a JEDEC assigned value is used +#define SCSCS_PIDR2_JEDEC 0x00000008U +#define SCSCS_PIDR2_JEDEC_M 0x00000008U +#define SCSCS_PIDR2_JEDEC_S 3U + +// Field: [2:0] DES_1 +// +// Bits [6:4] of the JEDEC identity code indicating the designer of the +// component (along with the continuation code) +#define SCSCS_PIDR2_DES_1_W 3U +#define SCSCS_PIDR2_DES_1_M 0x00000007U +#define SCSCS_PIDR2_DES_1_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_PIDR3 +// +//***************************************************************************** +// Field: [7:4] REVAND +// +// This field indicates minor errata fixes specific to this design, for example +// metal fixes after implementation. In most cases this field is zero. It is +// recommended that component designers ensure this field can be changed by a +// metal fix if required, for example by driving it from registers that reset +// to zero. +#define SCSCS_PIDR3_REVAND_W 4U +#define SCSCS_PIDR3_REVAND_M 0x000000F0U +#define SCSCS_PIDR3_REVAND_S 4U + +// Field: [3:0] CMOD +// +// Where the component is reusable IP, this value indicates if the customer has +// modified the behavior of the component. In most cases this field is zero. +#define SCSCS_PIDR3_CMOD_W 4U +#define SCSCS_PIDR3_CMOD_M 0x0000000FU +#define SCSCS_PIDR3_CMOD_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_CIDR0 +// +//***************************************************************************** +// Field: [7:0] PRMBL_0 +// +// Contains bits [7:0] of the component identification +#define SCSCS_CIDR0_PRMBL_0_W 8U +#define SCSCS_CIDR0_PRMBL_0_M 0x000000FFU +#define SCSCS_CIDR0_PRMBL_0_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_CIDR1 +// +//***************************************************************************** +// Field: [7:4] CLASS +// +// Class of the component. E.g. ROM table, CoreSight component etc. Constitutes +// bits [15:12] of the component identification. +#define SCSCS_CIDR1_CLASS_W 4U +#define SCSCS_CIDR1_CLASS_M 0x000000F0U +#define SCSCS_CIDR1_CLASS_S 4U + +// Field: [3:0] PRMBL_1 +// +// Contains bits [11:8] of the component identification +#define SCSCS_CIDR1_PRMBL_1_W 4U +#define SCSCS_CIDR1_PRMBL_1_M 0x0000000FU +#define SCSCS_CIDR1_PRMBL_1_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_CIDR2 +// +//***************************************************************************** +// Field: [7:0] PRMBL_2 +// +// Contains bits [23:16] of the component identification +#define SCSCS_CIDR2_PRMBL_2_W 8U +#define SCSCS_CIDR2_PRMBL_2_M 0x000000FFU +#define SCSCS_CIDR2_PRMBL_2_S 0U + +//***************************************************************************** +// +// Register: SCSCS_O_CIDR3 +// +//***************************************************************************** +// Field: [7:0] PRMBL_3 +// +// Contains bits [31:24] of the component identification +#define SCSCS_CIDR3_PRMBL_3_W 8U +#define SCSCS_CIDR3_PRMBL_3_M 0x000000FFU +#define SCSCS_CIDR3_PRMBL_3_S 0U + + +#endif // __SCSCS__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h new file mode 100644 index 00000000..ed6ac46c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h @@ -0,0 +1,1822 @@ +/****************************************************************************** +* Filename: hw_spi_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SPI_H__ +#define __HW_SPI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SPI component +// +//***************************************************************************** +// Module Description +#define SPI_O_DESC 0x00000000U + +// Interrupt mask +#define SPI_O_IMASK 0x00000044U + +// Raw interrupt status +#define SPI_O_RIS 0x00000048U + +// Masked interrupt status +#define SPI_O_MIS 0x0000004CU + +// Interrupt set +#define SPI_O_ISET 0x00000050U + +// Interrupt clear +#define SPI_O_ICLR 0x00000054U + +// Interrupt mask set +#define SPI_O_IMSET 0x00000058U + +// Interrupt mask clear +#define SPI_O_IMCLR 0x0000005CU + +// Emulation +#define SPI_O_EMU 0x00000060U + +// Control 0 +#define SPI_O_CTL0 0x00000100U + +// Control 1 +#define SPI_O_CTL1 0x00000104U + +// Clock configuration 0 +#define SPI_O_CLKCFG0 0x00000108U + +// Clock configuration 1 +#define SPI_O_CLKCFG1 0x0000010CU + +// Interrupt FIFO Level Select +#define SPI_O_IFLS 0x00000110U + +// DMA control +#define SPI_O_DMACR 0x00000114U + +// Receive CRC +#define SPI_O_RXCRC 0x00000118U + +// Transmit CRC +#define SPI_O_TXCRC 0x0000011CU + +// Header write for 32bits +#define SPI_O_TXFHDR32 0x00000120U + +// Header write for 24bits +#define SPI_O_TXFHDR24 0x00000124U + +// Header write for 16bits +#define SPI_O_TXFHDR16 0x00000128U + +// Header write for 8bits +#define SPI_O_TXFHDR8 0x0000012CU + +// Atomic header control +#define SPI_O_TXFHDRC 0x00000130U + +// Receive data +#define SPI_O_RXDATA 0x00000140U + +// Transmit data +#define SPI_O_TXDATA 0x00000150U + +// Status +#define SPI_O_STA 0x00000160U + +//***************************************************************************** +// +// Register: SPI_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define SPI_DESC_MODID_W 16U +#define SPI_DESC_MODID_M 0xFFFF0000U +#define SPI_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define SPI_DESC_STDIPOFF_W 4U +#define SPI_DESC_STDIPOFF_M 0x0000F000U +#define SPI_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define SPI_DESC_INSTIDX_W 4U +#define SPI_DESC_INSTIDX_M 0x00000F00U +#define SPI_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define SPI_DESC_MAJREV_W 4U +#define SPI_DESC_MAJREV_M 0x000000F0U +#define SPI_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define SPI_DESC_MINREV_W 4U +#define SPI_DESC_MINREV_M 0x0000000FU +#define SPI_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: SPI_O_IMASK +// +//***************************************************************************** +// Field: [8] DMATX +// +// DMA Done TX event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_DMATX 0x00000100U +#define SPI_IMASK_DMATX_M 0x00000100U +#define SPI_IMASK_DMATX_S 8U +#define SPI_IMASK_DMATX_SET 0x00000100U +#define SPI_IMASK_DMATX_CLR 0x00000000U + +// Field: [7] DMARX +// +// DMA Done RX event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_DMARX 0x00000080U +#define SPI_IMASK_DMARX_M 0x00000080U +#define SPI_IMASK_DMARX_S 7U +#define SPI_IMASK_DMARX_SET 0x00000080U +#define SPI_IMASK_DMARX_CLR 0x00000000U + +// Field: [6] IDLE +// +// SPI Idle event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_IDLE 0x00000040U +#define SPI_IMASK_IDLE_M 0x00000040U +#define SPI_IMASK_IDLE_S 6U +#define SPI_IMASK_IDLE_SET 0x00000040U +#define SPI_IMASK_IDLE_CLR 0x00000000U + +// Field: [5] TXEMPTY +// +// Transmit FIFO Empty event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_TXEMPTY 0x00000020U +#define SPI_IMASK_TXEMPTY_M 0x00000020U +#define SPI_IMASK_TXEMPTY_S 5U +#define SPI_IMASK_TXEMPTY_SET 0x00000020U +#define SPI_IMASK_TXEMPTY_CLR 0x00000000U + +// Field: [4] TX +// +// Transmit FIFO event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_TX 0x00000010U +#define SPI_IMASK_TX_M 0x00000010U +#define SPI_IMASK_TX_S 4U +#define SPI_IMASK_TX_SET 0x00000010U +#define SPI_IMASK_TX_CLR 0x00000000U + +// Field: [3] RX +// +// Receive FIFO event. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_RX 0x00000008U +#define SPI_IMASK_RX_M 0x00000008U +#define SPI_IMASK_RX_S 3U +#define SPI_IMASK_RX_SET 0x00000008U +#define SPI_IMASK_RX_CLR 0x00000000U + +// Field: [2] RTOUT +// +// SPI Receive Time-Out event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_RTOUT 0x00000004U +#define SPI_IMASK_RTOUT_M 0x00000004U +#define SPI_IMASK_RTOUT_S 2U +#define SPI_IMASK_RTOUT_SET 0x00000004U +#define SPI_IMASK_RTOUT_CLR 0x00000000U + +// Field: [1] PER +// +// Parity error event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_PER 0x00000002U +#define SPI_IMASK_PER_M 0x00000002U +#define SPI_IMASK_PER_S 1U +#define SPI_IMASK_PER_SET 0x00000002U +#define SPI_IMASK_PER_CLR 0x00000000U + +// Field: [0] RXOVF +// +// RXFIFO overflow event mask. +// ENUMs: +// SET Set Interrrupt Mask +// CLR Clear Interrupt Mask +#define SPI_IMASK_RXOVF 0x00000001U +#define SPI_IMASK_RXOVF_M 0x00000001U +#define SPI_IMASK_RXOVF_S 0U +#define SPI_IMASK_RXOVF_SET 0x00000001U +#define SPI_IMASK_RXOVF_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_RIS +// +//***************************************************************************** +// Field: [8] DMATX +// +// DMA Done event for TX. This interrupt is set if the TX DMA channel sends the +// DONE signal. This allows the handling of the TX DMA event inside SPI. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_DMATX 0x00000100U +#define SPI_RIS_DMATX_M 0x00000100U +#define SPI_RIS_DMATX_S 8U +#define SPI_RIS_DMATX_SET 0x00000100U +#define SPI_RIS_DMATX_CLR 0x00000000U + +// Field: [7] DMARX +// +// DMA Done event for RX. This interrupt is set if the RX DMA channel sends the +// DONE signal. This allows handling of the DMA RX event inside SPI. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_DMARX 0x00000080U +#define SPI_RIS_DMARX_M 0x00000080U +#define SPI_RIS_DMARX_S 7U +#define SPI_RIS_DMARX_SET 0x00000080U +#define SPI_RIS_DMARX_CLR 0x00000000U + +// Field: [6] IDLE +// +// SPI has completed transfers and moved to IDLE mode. This bit is set when +// STA.BUSY goes low. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_IDLE 0x00000040U +#define SPI_RIS_IDLE_M 0x00000040U +#define SPI_RIS_IDLE_S 6U +#define SPI_RIS_IDLE_SET 0x00000040U +#define SPI_RIS_IDLE_CLR 0x00000000U + +// Field: [5] TXEMPTY +// +// Transmit FIFO Empty interrupt mask. This interrupt is set when all data in +// the Transmit FIFO has been moved to the shift register. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_TXEMPTY 0x00000020U +#define SPI_RIS_TXEMPTY_M 0x00000020U +#define SPI_RIS_TXEMPTY_S 5U +#define SPI_RIS_TXEMPTY_SET 0x00000020U +#define SPI_RIS_TXEMPTY_CLR 0x00000000U + +// Field: [4] TX +// +// Transmit FIFO event. This interrupt is set if the selected Transmit FIFO +// level has been reached. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_TX 0x00000010U +#define SPI_RIS_TX_M 0x00000010U +#define SPI_RIS_TX_S 4U +#define SPI_RIS_TX_SET 0x00000010U +#define SPI_RIS_TX_CLR 0x00000000U + +// Field: [3] RX +// +// Receive FIFO event. This interrupt is set if the selected Receive FIFO level +// has been reached +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_RX 0x00000008U +#define SPI_RIS_RX_M 0x00000008U +#define SPI_RIS_RX_S 3U +#define SPI_RIS_RX_SET 0x00000008U +#define SPI_RIS_RX_CLR 0x00000000U + +// Field: [2] RTOUT +// +// SPI Receive Time-Out event. This interrupt is set if no activity is detected +// on the input clock line within the time period dictated by CTL1.RTOUT value. +// This is applicable only in peripheral mode. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_RTOUT 0x00000004U +#define SPI_RIS_RTOUT_M 0x00000004U +#define SPI_RIS_RTOUT_S 2U +#define SPI_RIS_RTOUT_SET 0x00000004U +#define SPI_RIS_RTOUT_CLR 0x00000000U + +// Field: [1] PER +// +// Parity error event. This bit is set if a Parity error has been detected +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_PER 0x00000002U +#define SPI_RIS_PER_M 0x00000002U +#define SPI_RIS_PER_S 1U +#define SPI_RIS_PER_SET 0x00000002U +#define SPI_RIS_PER_CLR 0x00000000U + +// Field: [0] RXOVF +// +// RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been +// detected. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_RIS_RXOVF 0x00000001U +#define SPI_RIS_RXOVF_M 0x00000001U +#define SPI_RIS_RXOVF_S 0U +#define SPI_RIS_RXOVF_SET 0x00000001U +#define SPI_RIS_RXOVF_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_MIS +// +//***************************************************************************** +// Field: [8] DMATX +// +// Masked DMA Done event for TX. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_DMATX 0x00000100U +#define SPI_MIS_DMATX_M 0x00000100U +#define SPI_MIS_DMATX_S 8U +#define SPI_MIS_DMATX_SET 0x00000100U +#define SPI_MIS_DMATX_CLR 0x00000000U + +// Field: [7] DMARX +// +// Masked DMA Done event for RX. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_DMARX 0x00000080U +#define SPI_MIS_DMARX_M 0x00000080U +#define SPI_MIS_DMARX_S 7U +#define SPI_MIS_DMARX_SET 0x00000080U +#define SPI_MIS_DMARX_CLR 0x00000000U + +// Field: [6] IDLE +// +// Masked SPI IDLE event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_IDLE 0x00000040U +#define SPI_MIS_IDLE_M 0x00000040U +#define SPI_MIS_IDLE_S 6U +#define SPI_MIS_IDLE_SET 0x00000040U +#define SPI_MIS_IDLE_CLR 0x00000000U + +// Field: [5] TXEMPTY +// +// Masked Transmit FIFO Empty event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_TXEMPTY 0x00000020U +#define SPI_MIS_TXEMPTY_M 0x00000020U +#define SPI_MIS_TXEMPTY_S 5U +#define SPI_MIS_TXEMPTY_SET 0x00000020U +#define SPI_MIS_TXEMPTY_CLR 0x00000000U + +// Field: [4] TX +// +// Masked Transmit FIFO event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_TX 0x00000010U +#define SPI_MIS_TX_M 0x00000010U +#define SPI_MIS_TX_S 4U +#define SPI_MIS_TX_SET 0x00000010U +#define SPI_MIS_TX_CLR 0x00000000U + +// Field: [3] RX +// +// Masked receive FIFO event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_RX 0x00000008U +#define SPI_MIS_RX_M 0x00000008U +#define SPI_MIS_RX_S 3U +#define SPI_MIS_RX_SET 0x00000008U +#define SPI_MIS_RX_CLR 0x00000000U + +// Field: [2] RTOUT +// +// Masked SPI Receive Time-Out event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_RTOUT 0x00000004U +#define SPI_MIS_RTOUT_M 0x00000004U +#define SPI_MIS_RTOUT_S 2U +#define SPI_MIS_RTOUT_SET 0x00000004U +#define SPI_MIS_RTOUT_CLR 0x00000000U + +// Field: [1] PER +// +// Masked Parity error event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_PER 0x00000002U +#define SPI_MIS_PER_M 0x00000002U +#define SPI_MIS_PER_S 1U +#define SPI_MIS_PER_SET 0x00000002U +#define SPI_MIS_PER_CLR 0x00000000U + +// Field: [0] RXOVF +// +// Masked RXFIFO overflow event. +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define SPI_MIS_RXOVF 0x00000001U +#define SPI_MIS_RXOVF_M 0x00000001U +#define SPI_MIS_RXOVF_S 0U +#define SPI_MIS_RXOVF_SET 0x00000001U +#define SPI_MIS_RXOVF_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_ISET +// +//***************************************************************************** +// Field: [8] DMATX +// +// Set DMA Done event for TX. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_DMATX 0x00000100U +#define SPI_ISET_DMATX_M 0x00000100U +#define SPI_ISET_DMATX_S 8U +#define SPI_ISET_DMATX_SET 0x00000100U +#define SPI_ISET_DMATX_NOEFF 0x00000000U + +// Field: [7] DMARX +// +// Set DMA Done event for RX. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_DMARX 0x00000080U +#define SPI_ISET_DMARX_M 0x00000080U +#define SPI_ISET_DMARX_S 7U +#define SPI_ISET_DMARX_SET 0x00000080U +#define SPI_ISET_DMARX_NOEFF 0x00000000U + +// Field: [6] IDLE +// +// Set SPI IDLE event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_IDLE 0x00000040U +#define SPI_ISET_IDLE_M 0x00000040U +#define SPI_ISET_IDLE_S 6U +#define SPI_ISET_IDLE_SET 0x00000040U +#define SPI_ISET_IDLE_NOEFF 0x00000000U + +// Field: [5] TXEMPTY +// +// Set Transmit FIFO Empty event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_TXEMPTY 0x00000020U +#define SPI_ISET_TXEMPTY_M 0x00000020U +#define SPI_ISET_TXEMPTY_S 5U +#define SPI_ISET_TXEMPTY_SET 0x00000020U +#define SPI_ISET_TXEMPTY_NOEFF 0x00000000U + +// Field: [4] TX +// +// Set Transmit FIFO event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_TX 0x00000010U +#define SPI_ISET_TX_M 0x00000010U +#define SPI_ISET_TX_S 4U +#define SPI_ISET_TX_SET 0x00000010U +#define SPI_ISET_TX_NOEFF 0x00000000U + +// Field: [3] RX +// +// Set Receive FIFO event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_RX 0x00000008U +#define SPI_ISET_RX_M 0x00000008U +#define SPI_ISET_RX_S 3U +#define SPI_ISET_RX_SET 0x00000008U +#define SPI_ISET_RX_NOEFF 0x00000000U + +// Field: [2] RTOUT +// +// Set SPI Receive Time-Out Event. +// ENUMs: +// SET Set Interrrupt Mask +// NOEFF Writing 0 has no effect +#define SPI_ISET_RTOUT 0x00000004U +#define SPI_ISET_RTOUT_M 0x00000004U +#define SPI_ISET_RTOUT_S 2U +#define SPI_ISET_RTOUT_SET 0x00000004U +#define SPI_ISET_RTOUT_NOEFF 0x00000000U + +// Field: [1] PER +// +// Set Parity error event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_PER 0x00000002U +#define SPI_ISET_PER_M 0x00000002U +#define SPI_ISET_PER_S 1U +#define SPI_ISET_PER_SET 0x00000002U +#define SPI_ISET_PER_NOEFF 0x00000000U + +// Field: [0] RXOVF +// +// Set RXFIFO overflow event. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ISET_RXOVF 0x00000001U +#define SPI_ISET_RXOVF_M 0x00000001U +#define SPI_ISET_RXOVF_S 0U +#define SPI_ISET_RXOVF_SET 0x00000001U +#define SPI_ISET_RXOVF_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_ICLR +// +//***************************************************************************** +// Field: [8] DMATX +// +// Clear DMA Done event for TX. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_DMATX 0x00000100U +#define SPI_ICLR_DMATX_M 0x00000100U +#define SPI_ICLR_DMATX_S 8U +#define SPI_ICLR_DMATX_CLR 0x00000100U +#define SPI_ICLR_DMATX_NOEFF 0x00000000U + +// Field: [7] DMARX +// +// Clear DMA Done event for RX. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_DMARX 0x00000080U +#define SPI_ICLR_DMARX_M 0x00000080U +#define SPI_ICLR_DMARX_S 7U +#define SPI_ICLR_DMARX_CLR 0x00000080U +#define SPI_ICLR_DMARX_NOEFF 0x00000000U + +// Field: [6] IDLE +// +// Clear SPI IDLE event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_IDLE 0x00000040U +#define SPI_ICLR_IDLE_M 0x00000040U +#define SPI_ICLR_IDLE_S 6U +#define SPI_ICLR_IDLE_CLR 0x00000040U +#define SPI_ICLR_IDLE_NOEFF 0x00000000U + +// Field: [5] TXEMPTY +// +// Clear Transmit FIFO Empty event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_TXEMPTY 0x00000020U +#define SPI_ICLR_TXEMPTY_M 0x00000020U +#define SPI_ICLR_TXEMPTY_S 5U +#define SPI_ICLR_TXEMPTY_CLR 0x00000020U +#define SPI_ICLR_TXEMPTY_NOEFF 0x00000000U + +// Field: [4] TX +// +// Clear Transmit FIFO event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_TX 0x00000010U +#define SPI_ICLR_TX_M 0x00000010U +#define SPI_ICLR_TX_S 4U +#define SPI_ICLR_TX_CLR 0x00000010U +#define SPI_ICLR_TX_NOEFF 0x00000000U + +// Field: [3] RX +// +// Clear Receive FIFO event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_RX 0x00000008U +#define SPI_ICLR_RX_M 0x00000008U +#define SPI_ICLR_RX_S 3U +#define SPI_ICLR_RX_CLR 0x00000008U +#define SPI_ICLR_RX_NOEFF 0x00000000U + +// Field: [2] RTOUT +// +// Clear SPI Receive Time-Out Event. +// ENUMs: +// CLR Set Interrrupt Mask +// NOEFF Writing 0 has no effect +#define SPI_ICLR_RTOUT 0x00000004U +#define SPI_ICLR_RTOUT_M 0x00000004U +#define SPI_ICLR_RTOUT_S 2U +#define SPI_ICLR_RTOUT_CLR 0x00000004U +#define SPI_ICLR_RTOUT_NOEFF 0x00000000U + +// Field: [1] PER +// +// Clear Parity error event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_PER 0x00000002U +#define SPI_ICLR_PER_M 0x00000002U +#define SPI_ICLR_PER_S 1U +#define SPI_ICLR_PER_CLR 0x00000002U +#define SPI_ICLR_PER_NOEFF 0x00000000U + +// Field: [0] RXOVF +// +// Clear RXFIFO overflow event. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SPI_ICLR_RXOVF 0x00000001U +#define SPI_ICLR_RXOVF_M 0x00000001U +#define SPI_ICLR_RXOVF_S 0U +#define SPI_ICLR_RXOVF_CLR 0x00000001U +#define SPI_ICLR_RXOVF_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_IMSET +// +//***************************************************************************** +// Field: [8] DMATX +// +// Set DMA Done for TX event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_DMATX 0x00000100U +#define SPI_IMSET_DMATX_M 0x00000100U +#define SPI_IMSET_DMATX_S 8U +#define SPI_IMSET_DMATX_SET 0x00000100U +#define SPI_IMSET_DMATX_NOEFF 0x00000000U + +// Field: [7] DMARX +// +// Set DMA Done for RX event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_DMARX 0x00000080U +#define SPI_IMSET_DMARX_M 0x00000080U +#define SPI_IMSET_DMARX_S 7U +#define SPI_IMSET_DMARX_SET 0x00000080U +#define SPI_IMSET_DMARX_NOEFF 0x00000000U + +// Field: [6] IDLE +// +// Set SPI IDLE event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_IDLE 0x00000040U +#define SPI_IMSET_IDLE_M 0x00000040U +#define SPI_IMSET_IDLE_S 6U +#define SPI_IMSET_IDLE_SET 0x00000040U +#define SPI_IMSET_IDLE_NOEFF 0x00000000U + +// Field: [5] TXEMPTY +// +// Set Transmit FIFO Empty event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_TXEMPTY 0x00000020U +#define SPI_IMSET_TXEMPTY_M 0x00000020U +#define SPI_IMSET_TXEMPTY_S 5U +#define SPI_IMSET_TXEMPTY_SET 0x00000020U +#define SPI_IMSET_TXEMPTY_NOEFF 0x00000000U + +// Field: [4] TX +// +// Set Transmit FIFO event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_TX 0x00000010U +#define SPI_IMSET_TX_M 0x00000010U +#define SPI_IMSET_TX_S 4U +#define SPI_IMSET_TX_SET 0x00000010U +#define SPI_IMSET_TX_NOEFF 0x00000000U + +// Field: [3] RX +// +// Set Receive FIFO event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_RX 0x00000008U +#define SPI_IMSET_RX_M 0x00000008U +#define SPI_IMSET_RX_S 3U +#define SPI_IMSET_RX_SET 0x00000008U +#define SPI_IMSET_RX_NOEFF 0x00000000U + +// Field: [2] RTOUT +// +// Set SPI Receive Time-Out event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_RTOUT 0x00000004U +#define SPI_IMSET_RTOUT_M 0x00000004U +#define SPI_IMSET_RTOUT_S 2U +#define SPI_IMSET_RTOUT_SET 0x00000004U +#define SPI_IMSET_RTOUT_NOEFF 0x00000000U + +// Field: [1] PER +// +// Set Parity error event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_PER 0x00000002U +#define SPI_IMSET_PER_M 0x00000002U +#define SPI_IMSET_PER_S 1U +#define SPI_IMSET_PER_SET 0x00000002U +#define SPI_IMSET_PER_NOEFF 0x00000000U + +// Field: [0] RXOVF +// +// Set RXFIFO overflow event mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMSET_RXOVF 0x00000001U +#define SPI_IMSET_RXOVF_M 0x00000001U +#define SPI_IMSET_RXOVF_S 0U +#define SPI_IMSET_RXOVF_SET 0x00000001U +#define SPI_IMSET_RXOVF_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_IMCLR +// +//***************************************************************************** +// Field: [8] DMATX +// +// Clear DMA Done for TX event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_DMATX 0x00000100U +#define SPI_IMCLR_DMATX_M 0x00000100U +#define SPI_IMCLR_DMATX_S 8U +#define SPI_IMCLR_DMATX_CLR 0x00000100U +#define SPI_IMCLR_DMATX_NOEFF 0x00000000U + +// Field: [7] DMARX +// +// Clear DMA Done for RX event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_DMARX 0x00000080U +#define SPI_IMCLR_DMARX_M 0x00000080U +#define SPI_IMCLR_DMARX_S 7U +#define SPI_IMCLR_DMARX_CLR 0x00000080U +#define SPI_IMCLR_DMARX_NOEFF 0x00000000U + +// Field: [6] IDLE +// +// Clear SPI IDLE event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_IDLE 0x00000040U +#define SPI_IMCLR_IDLE_M 0x00000040U +#define SPI_IMCLR_IDLE_S 6U +#define SPI_IMCLR_IDLE_CLR 0x00000040U +#define SPI_IMCLR_IDLE_NOEFF 0x00000000U + +// Field: [5] TXEMPTY +// +// Clear Transmit FIFO Empty event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_TXEMPTY 0x00000020U +#define SPI_IMCLR_TXEMPTY_M 0x00000020U +#define SPI_IMCLR_TXEMPTY_S 5U +#define SPI_IMCLR_TXEMPTY_CLR 0x00000020U +#define SPI_IMCLR_TXEMPTY_NOEFF 0x00000000U + +// Field: [4] TX +// +// Clear Transmit FIFO event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_TX 0x00000010U +#define SPI_IMCLR_TX_M 0x00000010U +#define SPI_IMCLR_TX_S 4U +#define SPI_IMCLR_TX_CLR 0x00000010U +#define SPI_IMCLR_TX_NOEFF 0x00000000U + +// Field: [3] RX +// +// Clear Receive FIFO event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_RX 0x00000008U +#define SPI_IMCLR_RX_M 0x00000008U +#define SPI_IMCLR_RX_S 3U +#define SPI_IMCLR_RX_CLR 0x00000008U +#define SPI_IMCLR_RX_NOEFF 0x00000000U + +// Field: [2] RTOUT +// +// Clear SPI Receive Time-Out event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_RTOUT 0x00000004U +#define SPI_IMCLR_RTOUT_M 0x00000004U +#define SPI_IMCLR_RTOUT_S 2U +#define SPI_IMCLR_RTOUT_CLR 0x00000004U +#define SPI_IMCLR_RTOUT_NOEFF 0x00000000U + +// Field: [1] PER +// +// Clear Parity error event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_PER 0x00000002U +#define SPI_IMCLR_PER_M 0x00000002U +#define SPI_IMCLR_PER_S 1U +#define SPI_IMCLR_PER_CLR 0x00000002U +#define SPI_IMCLR_PER_NOEFF 0x00000000U + +// Field: [0] RXOVF +// +// Clear RXFIFO overflow event mask +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SPI_IMCLR_RXOVF 0x00000001U +#define SPI_IMCLR_RXOVF_M 0x00000001U +#define SPI_IMCLR_RXOVF_S 0U +#define SPI_IMCLR_RXOVF_CLR 0x00000001U +#define SPI_IMCLR_RXOVF_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_EMU +// +//***************************************************************************** +// Field: [0] HALT +// +// Halt control +// ENUMs: +// STOP Freeze option. The IP freezes functionality when +// the core halted input is asserted, and resumes +// when it is deasserted. The freeze can either be +// immediate or after the IP has reached a +// boundary (end of word boundary, based on DSS +// configuration) from where it can resume without +// corruption. +// RUN Free run option. The IP ignores the state of the +// core halted input. +#define SPI_EMU_HALT 0x00000001U +#define SPI_EMU_HALT_M 0x00000001U +#define SPI_EMU_HALT_S 0U +#define SPI_EMU_HALT_STOP 0x00000001U +#define SPI_EMU_HALT_RUN 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_CTL0 +// +//***************************************************************************** +// Field: [17] IDLEPOCI +// +// The Idle value of POCI - when TXFIFO is empty and before data is written +// into TXFIFO - can be controlled by this field. +// ENUMs: +// IDLE_ONE POCI outputs idle value of '1' +// IDLE_ZERO POCI output idle value of '0' +#define SPI_CTL0_IDLEPOCI 0x00020000U +#define SPI_CTL0_IDLEPOCI_M 0x00020000U +#define SPI_CTL0_IDLEPOCI_S 17U +#define SPI_CTL0_IDLEPOCI_IDLE_ONE 0x00020000U +#define SPI_CTL0_IDLEPOCI_IDLE_ZERO 0x00000000U + +// Field: [16] GPCRCEN +// +// General purpose CRC enable. This bit enables transmit side CRC unit for +// general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit +// must be 0 when SPI is enabled. +// ENUMs: +// EN Transmit side CRC unit is available for general +// purpose software use +// DIS Transmit side CRC unit is not available for +// general purpose software use +#define SPI_CTL0_GPCRCEN 0x00010000U +#define SPI_CTL0_GPCRCEN_M 0x00010000U +#define SPI_CTL0_GPCRCEN_S 16U +#define SPI_CTL0_GPCRCEN_EN 0x00010000U +#define SPI_CTL0_GPCRCEN_DIS 0x00000000U + +// Field: [15] CRCPOLY +// +// CRC polynomial selection. +// ENUMs: +// SIZE16BIT Selects 16-bit CCITT CRC polynomial +// SIZE8BIT Selects 8-bit CCITT CRC polynomial +#define SPI_CTL0_CRCPOLY 0x00008000U +#define SPI_CTL0_CRCPOLY_M 0x00008000U +#define SPI_CTL0_CRCPOLY_S 15U +#define SPI_CTL0_CRCPOLY_SIZE16BIT 0x00008000U +#define SPI_CTL0_CRCPOLY_SIZE8BIT 0x00000000U + +// Field: [14] AUTOCRC +// +// Auto insert CRC +// ENUMs: +// EN Insert CRC into TXFIFO upon TXFIFO underflow +// DIS Do not insert CRC into TXFIFO upon TXFIFO +// underflow +#define SPI_CTL0_AUTOCRC 0x00004000U +#define SPI_CTL0_AUTOCRC_M 0x00004000U +#define SPI_CTL0_AUTOCRC_S 14U +#define SPI_CTL0_AUTOCRC_EN 0x00004000U +#define SPI_CTL0_AUTOCRC_DIS 0x00000000U + +// Field: [13] CRCEND +// +// CRC16 Endianness +// ENUMs: +// CRC_END_LSB Auto-insertion of CRC16 is least-significant byte +// first +// CRC_END_MSB Auto-insertion of CRC16 is most-significant byte +// first +#define SPI_CTL0_CRCEND 0x00002000U +#define SPI_CTL0_CRCEND_M 0x00002000U +#define SPI_CTL0_CRCEND_S 13U +#define SPI_CTL0_CRCEND_CRC_END_LSB 0x00002000U +#define SPI_CTL0_CRCEND_CRC_END_MSB 0x00000000U + +// Field: [12] CSCLR +// +// Clear shift register counter on CS inactive. +// This bit is relevant only in the peripheral mode, when CTL1.MS=0. +// ENUMs: +// EN Enable automatic clear of shift register when CS +// goes inactive. +// DIS Disable automatic clear of shift register when CS +// goes inactive. +#define SPI_CTL0_CSCLR 0x00001000U +#define SPI_CTL0_CSCLR_M 0x00001000U +#define SPI_CTL0_CSCLR_S 12U +#define SPI_CTL0_CSCLR_EN 0x00001000U +#define SPI_CTL0_CSCLR_DIS 0x00000000U + +// Field: [11] FIFORST +// +// This bit is used to reset transmit and receive FIFO pointers. This bit is +// auto cleared once the FIFO pointer reset operation is completed. +// ENUMs: +// RST_TRIG Trigger FIFO pointers reset when written to 1. +// RST_DONE FIFO pointers reset completed when 0 is read +#define SPI_CTL0_FIFORST 0x00000800U +#define SPI_CTL0_FIFORST_M 0x00000800U +#define SPI_CTL0_FIFORST_S 11U +#define SPI_CTL0_FIFORST_RST_TRIG 0x00000800U +#define SPI_CTL0_FIFORST_RST_DONE 0x00000000U + +// Field: [10] HWCSN +// +// Hardware controlled chip select (CS) value. When set CS is zero till TX FIFO +// is empty, as in - +// a. CS is de-asserted +// b. All data bytes are transmitted +// c. CS is asserted +// ENUMs: +// EN HWCSN Enable +// DIS HWCSN Disable +#define SPI_CTL0_HWCSN 0x00000400U +#define SPI_CTL0_HWCSN_M 0x00000400U +#define SPI_CTL0_HWCSN_S 10U +#define SPI_CTL0_HWCSN_EN 0x00000400U +#define SPI_CTL0_HWCSN_DIS 0x00000000U + +// Field: [9] SPH +// +// SCLK phase (Motorola SPI frame format only). +// This bit selects the clock edge that captures data and enables it to change +// state. +// It has the most impact on the first bit transmitted by either permitting or +// not permitting a clock transition before the first data capture clock edge. +// ENUMs: +// SECOND Data is captured on the second clock edge +// transition. +// FIRST Data is captured on the first clock edge +// transition. +#define SPI_CTL0_SPH 0x00000200U +#define SPI_CTL0_SPH_M 0x00000200U +#define SPI_CTL0_SPH_S 9U +#define SPI_CTL0_SPH_SECOND 0x00000200U +#define SPI_CTL0_SPH_FIRST 0x00000000U + +// Field: [8] SPO +// +// SCLK polarity (Motorola SPI frame format only). +// ENUMs: +// HI SPI produces a steady state HI value on the SCLK +// LO SPI produces a steady state LO value on the SCLK +#define SPI_CTL0_SPO 0x00000100U +#define SPI_CTL0_SPO_M 0x00000100U +#define SPI_CTL0_SPO_S 8U +#define SPI_CTL0_SPO_HI 0x00000100U +#define SPI_CTL0_SPO_LO 0x00000000U + +// Field: [6:5] FRF +// +// Frame format select +// ENUMs: +// MICROWIRE MICROWIRE frame format +// TI_SYNC TI synchronous serial frame format +// MOTOROLA_4WIRE Motorola SPI frame format (4-wire mode) +// MOTOROLA_3WIRE Motorola SPI frame format (3-wire mode) +#define SPI_CTL0_FRF_W 2U +#define SPI_CTL0_FRF_M 0x00000060U +#define SPI_CTL0_FRF_S 5U +#define SPI_CTL0_FRF_MICROWIRE 0x00000060U +#define SPI_CTL0_FRF_TI_SYNC 0x00000040U +#define SPI_CTL0_FRF_MOTOROLA_4WIRE 0x00000020U +#define SPI_CTL0_FRF_MOTOROLA_3WIRE 0x00000000U + +// Field: [3:0] DSS +// +// Data size select. The applicable DSS values for controller mode operation +// are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values +// 0x0 to 0x2 are reserved and must not be used. +// ENUMs: +// BITS_16 16-bits data size +// BITS_15 15-bits data size +// BITS_14 14-bits data size +// BITS_13 13-bits data size +// BITS_12 12-bits data size +// BITS_11 11-bits data size +// BITS_10 10-bits data size +// BITS_9 9-bits data size +// BITS_8 8-bits data size +// BITS_7 7-bits data size +// BITS_6 6-bits data size +// BITS_5 5-bits data size +// BITS_4 4-bits data size +#define SPI_CTL0_DSS_W 4U +#define SPI_CTL0_DSS_M 0x0000000FU +#define SPI_CTL0_DSS_S 0U +#define SPI_CTL0_DSS_BITS_16 0x0000000FU +#define SPI_CTL0_DSS_BITS_15 0x0000000EU +#define SPI_CTL0_DSS_BITS_14 0x0000000DU +#define SPI_CTL0_DSS_BITS_13 0x0000000CU +#define SPI_CTL0_DSS_BITS_12 0x0000000BU +#define SPI_CTL0_DSS_BITS_11 0x0000000AU +#define SPI_CTL0_DSS_BITS_10 0x00000009U +#define SPI_CTL0_DSS_BITS_9 0x00000008U +#define SPI_CTL0_DSS_BITS_8 0x00000007U +#define SPI_CTL0_DSS_BITS_7 0x00000006U +#define SPI_CTL0_DSS_BITS_6 0x00000005U +#define SPI_CTL0_DSS_BITS_5 0x00000004U +#define SPI_CTL0_DSS_BITS_4 0x00000003U + +//***************************************************************************** +// +// Register: SPI_O_CTL1 +// +//***************************************************************************** +// Field: [29:24] RTOUT +// +// Receive Timeout (only for Peripheral mode) +// Defines the number of CLKSVT clock cycles after which the Receive Timeout +// flag RIS.RTOUT is set. +// A value of 0 disables this function. +#define SPI_CTL1_RTOUT_W 6U +#define SPI_CTL1_RTOUT_M 0x3F000000U +#define SPI_CTL1_RTOUT_S 24U + +// Field: [23:16] REPTX +// +// Counter to repeat last transfer (only in controller mode) +// 0: repeat last transfer is disabled. +// x: repeat the last transfer with the provided value. +// The transfer will be started with writing a data into the TX FIFO. Sending +// the data will be repeated REPTX number of times, so the data will be +// transferred x+1 times in total. +// It can be used to clean a transfer or to pull a certain amount of data by a +// peripheral. +// ENUMs: +// DIS REPTX disable +#define SPI_CTL1_REPTX_W 8U +#define SPI_CTL1_REPTX_M 0x00FF0000U +#define SPI_CTL1_REPTX_S 16U +#define SPI_CTL1_REPTX_DIS 0x00000000U + +// Field: [15:12] CDMODE +// +// Commnd Data Mode. This bit field value determines the behavior of C/D or CS +// signal when CDEN = 1. CS pin held low indicates command phase and CS pin +// held high indicates data phase. +// When CDMODE = 0x0, the CS pin is always held high during transfer indicating +// data phase only operation (manual mode). +// When CDMODE = 0xF, the CS pin is always held low during transfer indicating +// command phase only operation (manual mode). +// When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes +// indicated by CDMODE value for the command phase and held high for the +// remaining transfers in the data phase (automatic mode). +// When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation +// indicates the remaining bytes to be transferred in the command phase. +// ENUMs: +// COMMAND Manual mode: Command +// DATA Manual mode: Data +#define SPI_CTL1_CDMODE_W 4U +#define SPI_CTL1_CDMODE_M 0x0000F000U +#define SPI_CTL1_CDMODE_S 12U +#define SPI_CTL1_CDMODE_COMMAND 0x0000F000U +#define SPI_CTL1_CDMODE_DATA 0x00000000U + +// Field: [11] CDEN +// +// Command/Data mode enable. This feature is applicable only in controller mode +// and for 8-bit transfers (CTL0.DSS = 7). The chip select pin is used for +// command/data signaling in Motorola SPI frame format (3-wire) operation. +// ENUMs: +// EN C/D Mode Enable +// DIS C/D Mode Disable +#define SPI_CTL1_CDEN 0x00000800U +#define SPI_CTL1_CDEN_M 0x00000800U +#define SPI_CTL1_CDEN_S 11U +#define SPI_CTL1_CDEN_EN 0x00000800U +#define SPI_CTL1_CDEN_DIS 0x00000000U + +// Field: [7] PBS +// +// Parity bit select +// ENUMs: +// BIT1 Bit 1 is used for Parity, Bit 0 is ignored +// BIT0 Bit 0 is used for Parity +#define SPI_CTL1_PBS 0x00000080U +#define SPI_CTL1_PBS_M 0x00000080U +#define SPI_CTL1_PBS_S 7U +#define SPI_CTL1_PBS_BIT1 0x00000080U +#define SPI_CTL1_PBS_BIT0 0x00000000U + +// Field: [6] PES +// +// Even parity select. +// ENUMs: +// EVEN Even Parity mode +// ODD Odd Parity mode +#define SPI_CTL1_PES 0x00000040U +#define SPI_CTL1_PES_M 0x00000040U +#define SPI_CTL1_PES_S 6U +#define SPI_CTL1_PES_EVEN 0x00000040U +#define SPI_CTL1_PES_ODD 0x00000000U + +// Field: [5] PEN +// +// Parity enable. If enabled the last bit will be used as parity to evaluate +// the correct reception of the previous bits. +// In case of parity mismatch the parity error flag RIS.PER will be set. This +// feature is available only in SPI controller mode. +// ENUMs: +// EN Enable Parity function +// DIS Disable Parity function +#define SPI_CTL1_PEN 0x00000020U +#define SPI_CTL1_PEN_M 0x00000020U +#define SPI_CTL1_PEN_S 5U +#define SPI_CTL1_PEN_EN 0x00000020U +#define SPI_CTL1_PEN_DIS 0x00000000U + +// Field: [4] MSB +// +// MSB first select. Controls the direction of receive and transmit shift +// register. MSB first configuration (MSB = 1) must be selected when CRC +// feature is used for SPI communication. +// ENUMs: +// MSB MSB first +// LSB LSB first +#define SPI_CTL1_MSB 0x00000010U +#define SPI_CTL1_MSB_M 0x00000010U +#define SPI_CTL1_MSB_S 4U +#define SPI_CTL1_MSB_MSB 0x00000010U +#define SPI_CTL1_MSB_LSB 0x00000000U + +// Field: [3] POD +// +// Peripheral data output disable. +// This bit is relevant only in the peripheral mode, MS=1. In +// multiple-peripheral systems, it is possible for a SPI controller to +// broadcast a message to all peripherals in the system while ensuring that +// only one peripheral drives data onto its serial output line. In such systems +// the POCI lines from multiple peripherals could be tied together. To operate +// in such systems, this bit field can be set if the SPI peripheral is not +// supposed to drive the POCI output. +// ENUMs: +// EN SPI cannot drive the POCI output in peripheral +// mode. +// DIS SPI can drive the POCI output in peripheral mode. +#define SPI_CTL1_POD 0x00000008U +#define SPI_CTL1_POD_M 0x00000008U +#define SPI_CTL1_POD_S 3U +#define SPI_CTL1_POD_EN 0x00000008U +#define SPI_CTL1_POD_DIS 0x00000000U + +// Field: [2] MS +// +// Controller or peripheral mode select. This bit can be modified only when SPI +// is disabled, CTL1.EN=0. +// ENUMs: +// CONTROLLER Select Controller mode +// PERIPHERAL Select Peripheral mode +#define SPI_CTL1_MS 0x00000004U +#define SPI_CTL1_MS_M 0x00000004U +#define SPI_CTL1_MS_S 2U +#define SPI_CTL1_MS_CONTROLLER 0x00000004U +#define SPI_CTL1_MS_PERIPHERAL 0x00000000U + +// Field: [1] LBM +// +// Loop back mode control +// ENUMs: +// EN Enable loopback mode. Output of transmit serial +// shifter is connected to input of receive serial +// shifter internally. +// DIS Disable loopback mode. Normal serial port +// operation enabled. +#define SPI_CTL1_LBM 0x00000002U +#define SPI_CTL1_LBM_M 0x00000002U +#define SPI_CTL1_LBM_S 1U +#define SPI_CTL1_LBM_EN 0x00000002U +#define SPI_CTL1_LBM_DIS 0x00000000U + +// Field: [0] EN +// +// SPI enable. +// NOTE: This bit field must be set to 1 using a separate write access, after +// the other bit fields have been configured. +// ENUMs: +// EN SPI Enabled and released for operation. +// DIS SPI is disabled +#define SPI_CTL1_EN 0x00000001U +#define SPI_CTL1_EN_M 0x00000001U +#define SPI_CTL1_EN_S 0U +#define SPI_CTL1_EN_EN 0x00000001U +#define SPI_CTL1_EN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_CLKCFG0 +// +//***************************************************************************** +// Field: [2:0] PRESC +// +// Prescaler configuration +// ENUMs: +// DIV_BY_8 Divide clock source by 8 +// DIV_BY_7 Divide clock source by 7 +// DIV_BY_6 Divide clock source by 6 +// DIV_BY_5 Divide clock source by 5 +// DIV_BY_4 Divide clock source by 4 +// DIV_BY_3 Divide clock source by 3 +// DIV_BY_2 Divide clock source by 2 +// DIV_BY_1 Do not divide clock source +#define SPI_CLKCFG0_PRESC_W 3U +#define SPI_CLKCFG0_PRESC_M 0x00000007U +#define SPI_CLKCFG0_PRESC_S 0U +#define SPI_CLKCFG0_PRESC_DIV_BY_8 0x00000007U +#define SPI_CLKCFG0_PRESC_DIV_BY_7 0x00000006U +#define SPI_CLKCFG0_PRESC_DIV_BY_6 0x00000005U +#define SPI_CLKCFG0_PRESC_DIV_BY_5 0x00000004U +#define SPI_CLKCFG0_PRESC_DIV_BY_4 0x00000003U +#define SPI_CLKCFG0_PRESC_DIV_BY_3 0x00000002U +#define SPI_CLKCFG0_PRESC_DIV_BY_2 0x00000001U +#define SPI_CLKCFG0_PRESC_DIV_BY_1 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_CLKCFG1 +// +//***************************************************************************** +// Field: [19:16] DSAMPLE +// +// Delayed sampling. In controller mode the data on the POCI pin will be +// delayed sampled by the defined CLKSVT clock cycles. DSAMPLE values can range +// from 0 to SCR+1. Typically, values of 1 or 2 would suffice. +#define SPI_CLKCFG1_DSAMPLE_W 4U +#define SPI_CLKCFG1_DSAMPLE_M 0x000F0000U +#define SPI_CLKCFG1_DSAMPLE_S 16U + +// Field: [9:0] SCR +// +// Serial clock divider. This is used to generate the transmit and receive bit +// rate of the SPI. +// The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value +// can be from 0 to 1023. +#define SPI_CLKCFG1_SCR_W 10U +#define SPI_CLKCFG1_SCR_M 0x000003FFU +#define SPI_CLKCFG1_SCR_S 0U + +//***************************************************************************** +// +// Register: SPI_O_IFLS +// +//***************************************************************************** +// Field: [10:8] RXSEL +// +// Receive FIFO Level Select. The trigger points for the receive interrupt are +// as follows: +// ENUMs: +// LEVEL_1 Trigger when RX FIFO contains >= 1 byte +// LVL_RES6 Reserved +// LVL_FULL RX FIFO is full +// LVL_RES4 Reserved +// LVL_3_4 RX FIFO >= 3/4 full +// LVL_1_2 RX FIFO >= 1/2 full (default) +// LVL_1_4 RX FIFO >= 1/4 full +// LVL_OFF Reserved +#define SPI_IFLS_RXSEL_W 3U +#define SPI_IFLS_RXSEL_M 0x00000700U +#define SPI_IFLS_RXSEL_S 8U +#define SPI_IFLS_RXSEL_LEVEL_1 0x00000700U +#define SPI_IFLS_RXSEL_LVL_RES6 0x00000600U +#define SPI_IFLS_RXSEL_LVL_FULL 0x00000500U +#define SPI_IFLS_RXSEL_LVL_RES4 0x00000400U +#define SPI_IFLS_RXSEL_LVL_3_4 0x00000300U +#define SPI_IFLS_RXSEL_LVL_1_2 0x00000200U +#define SPI_IFLS_RXSEL_LVL_1_4 0x00000100U +#define SPI_IFLS_RXSEL_LVL_OFF 0x00000000U + +// Field: [2:0] TXSEL +// +// Transmit FIFO Level Select. The trigger points for the transmit interrupt +// are as follows: +// ENUMs: +// LEVEL_1 Trigger when TX FIFO has >= 1 byte free +// LVL_RES6 Reserved +// LVL_EMPTY TX FIFO is empty +// LVL_RES4 Reserved +// LVL_1_4 TX FIFO <= 1/4 empty +// LVL_1_2 TX FIFO <= 1/2 empty (default) +// LVL_3_4 TX FIFO <= 3/4 empty +// LVL_OFF Reserved +#define SPI_IFLS_TXSEL_W 3U +#define SPI_IFLS_TXSEL_M 0x00000007U +#define SPI_IFLS_TXSEL_S 0U +#define SPI_IFLS_TXSEL_LEVEL_1 0x00000007U +#define SPI_IFLS_TXSEL_LVL_RES6 0x00000006U +#define SPI_IFLS_TXSEL_LVL_EMPTY 0x00000005U +#define SPI_IFLS_TXSEL_LVL_RES4 0x00000004U +#define SPI_IFLS_TXSEL_LVL_1_4 0x00000003U +#define SPI_IFLS_TXSEL_LVL_1_2 0x00000002U +#define SPI_IFLS_TXSEL_LVL_3_4 0x00000001U +#define SPI_IFLS_TXSEL_LVL_OFF 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_DMACR +// +//***************************************************************************** +// Field: [8] TXEN +// +// Transmit DMA enable. If this bit is set to 1, DMA for the trasmit FIFO is +// enabled. +// ENUMs: +// EN Enable TX DMA +// DIS Disable TX DMA +#define SPI_DMACR_TXEN 0x00000100U +#define SPI_DMACR_TXEN_M 0x00000100U +#define SPI_DMACR_TXEN_S 8U +#define SPI_DMACR_TXEN_EN 0x00000100U +#define SPI_DMACR_TXEN_DIS 0x00000000U + +// Field: [0] RXEN +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +// ENUMs: +// EN Enable RX DMA +// DIS Disable RX DMA +#define SPI_DMACR_RXEN 0x00000001U +#define SPI_DMACR_RXEN_M 0x00000001U +#define SPI_DMACR_RXEN_S 0U +#define SPI_DMACR_RXEN_EN 0x00000001U +#define SPI_DMACR_RXEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_RXCRC +// +//***************************************************************************** +// Field: [15:0] DATA +// +// CRC value +// SW should read RXCRC register at the end of data transmission to reinitiaze +// the seed value to all ones +#define SPI_RXCRC_DATA_W 16U +#define SPI_RXCRC_DATA_M 0x0000FFFFU +#define SPI_RXCRC_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXCRC +// +//***************************************************************************** +// Field: [31] AUTOCRCINS +// +// Status to indicate if Auto CRC has been inserted into TXFIFO. +// This is applicable only if CTL0.AUTOCRC enable bit is set. +// SW should read TXCRC register to clear auto inserted CRC at the end of the +// transfer. +// ENUMs: +// INS Auto CRC inserted +// NOTINS Auto CRC not yet inserted +#define SPI_TXCRC_AUTOCRCINS 0x80000000U +#define SPI_TXCRC_AUTOCRCINS_M 0x80000000U +#define SPI_TXCRC_AUTOCRCINS_S 31U +#define SPI_TXCRC_AUTOCRCINS_INS 0x80000000U +#define SPI_TXCRC_AUTOCRCINS_NOTINS 0x00000000U + +// Field: [15:0] DATA +// +// CRC value +#define SPI_TXCRC_DATA_W 16U +#define SPI_TXCRC_DATA_M 0x0000FFFFU +#define SPI_TXCRC_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXFHDR32 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// This field can be used to write four bytes of header data into the TXFIFO +#define SPI_TXFHDR32_DATA_W 32U +#define SPI_TXFHDR32_DATA_M 0xFFFFFFFFU +#define SPI_TXFHDR32_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXFHDR24 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// This field can be used to write three bytes of header data into the TXFIFO. +#define SPI_TXFHDR24_DATA_W 32U +#define SPI_TXFHDR24_DATA_M 0xFFFFFFFFU +#define SPI_TXFHDR24_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXFHDR16 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// This field can be used to write two bytes of header data into the TXFIFO. +#define SPI_TXFHDR16_DATA_W 32U +#define SPI_TXFHDR16_DATA_M 0xFFFFFFFFU +#define SPI_TXFHDR16_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXFHDR8 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// This field can be used to write one byte of header data into the TXFIFO. +#define SPI_TXFHDR8_DATA_W 32U +#define SPI_TXFHDR8_DATA_M 0xFFFFFFFFU +#define SPI_TXFHDR8_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXFHDRC +// +//***************************************************************************** +// Field: [3] CSGATE +// +// Chip Select Gating control register. If this bit is set, header update +// register writes are blocked when chip select (CS) is active low, and HDRIGN +// bit is set. +// This bit resets to 0. +// ENUMs: +// BLK Header update register writes are blocked when CS +// is active (low) +// UNBLK The first header update register write is not +// blocked based on CS active status (low). +// If no header update +// occurred when CS was high (inactive), the first +// header update is allowed when CS is low +// (active), and the HDRCMT bit is set. The use +// case is for the external controller to ensure +// that the SCLK is not driven during this header +// update. +// If the header is already +// updated when CS is high and inactive, HDRCMT is +// set immediately when CS drops to active low +// state, and header writes when CS is low are +// ignored even if this UNBLK bit is set. +#define SPI_TXFHDRC_CSGATE 0x00000008U +#define SPI_TXFHDRC_CSGATE_M 0x00000008U +#define SPI_TXFHDRC_CSGATE_S 3U +#define SPI_TXFHDRC_CSGATE_BLK 0x00000008U +#define SPI_TXFHDRC_CSGATE_UNBLK 0x00000000U + +// Field: [2] HDRCMT +// +// Header Committed field. This bit is set when the HDREN bit is set and CS is +// sampled low. This bit remains 0 otherwise. When set, this bit can be written +// to a value of 0 to clear. +// ENUMs: +// SET Header update is committed +// CLR Header update is not committed +#define SPI_TXFHDRC_HDRCMT 0x00000004U +#define SPI_TXFHDRC_HDRCMT_M 0x00000004U +#define SPI_TXFHDRC_HDRCMT_S 2U +#define SPI_TXFHDRC_HDRCMT_SET 0x00000004U +#define SPI_TXFHDRC_HDRCMT_CLR 0x00000000U + +// Field: [1] HDRIGN +// +// Header Ignored field. When CSGATE is set to BLK, this bit is set when the +// last Header update register TXFHDRn is written when CS is low or HDRCMT is +// already set. When CSGATE is set to UNBLK, this bit is set only when the +// header update register is written when HDRCMT is already set. This bit +// remains 0 otherwise. When set, this bit can be written to a value of 0 to +// clear. +// ENUMs: +// SET Header update is ignored +// CLR Header update is not ignored +#define SPI_TXFHDRC_HDRIGN 0x00000002U +#define SPI_TXFHDRC_HDRIGN_M 0x00000002U +#define SPI_TXFHDRC_HDRIGN_S 1U +#define SPI_TXFHDRC_HDRIGN_SET 0x00000002U +#define SPI_TXFHDRC_HDRIGN_CLR 0x00000000U + +// Field: [0] HDREN +// +// Header enable field. When CSGATE is set to BLK, this bit has to be set by +// software to enable atomic header feature. When CSGATE is set to UNBLK, this +// field is set automatically whenever a write to header update registers +// TXFHDRn occurs. +// ENUMs: +// EN Atomic header update feature enable +// DIS Atomic header update feature disable +#define SPI_TXFHDRC_HDREN 0x00000001U +#define SPI_TXFHDRC_HDREN_M 0x00000001U +#define SPI_TXFHDRC_HDREN_S 0U +#define SPI_TXFHDRC_HDREN_EN 0x00000001U +#define SPI_TXFHDRC_HDREN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SPI_O_RXDATA +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Received Data. When read, the entry in the receive FIFO, pointed to by the +// current FIFO read pointer is accessed. As data values are read by the +// receive logic from the incoming data frame, they are placed into the entry +// in the receive FIFO, pointed to by the current RX FIFO write pointer. +// Received data less than 16 bits is automatically right-justified in the +// receive buffer. +#define SPI_RXDATA_DATA_W 16U +#define SPI_RXDATA_DATA_M 0x0000FFFFU +#define SPI_RXDATA_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_TXDATA +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit Data. When read, the last entry in the transmit FIFO, pointed to by +// the current FIFO write pointer is accessed. +// When written, the entry in the TX FIFO pointed to by the write pointer, is +// written to. Data values are read from the transmit FIFO by the transmit +// logic. It is loaded into the transmit serial shifter, then serially shifted +// out onto the output pin at the programmed bit rate. +// When a data size of less than 16 bits is selected, the user must +// right-justify data written to the transmit FIFO. The transmit logic ignores +// the unused bits. +#define SPI_TXDATA_DATA_W 16U +#define SPI_TXDATA_DATA_M 0x0000FFFFU +#define SPI_TXDATA_DATA_S 0U + +//***************************************************************************** +// +// Register: SPI_O_STA +// +//***************************************************************************** +// Field: [13:8] TXFIFOLVL +// +// Indicates how many locations of TXFIFO are currently filled with data +#define SPI_STA_TXFIFOLVL_W 6U +#define SPI_STA_TXFIFOLVL_M 0x00003F00U +#define SPI_STA_TXFIFOLVL_S 8U + +// Field: [6] TXDONE +// +// Transmit done. Indicates whether the last bit has left the Shift register +// after a transmission +// ENUMs: +// TX_DONE Last bit has been shifted out, and the +// transmission is done +// TX_ONGOING Last bit has not yet left the Shift register, and +// the transmission is ongoing. +#define SPI_STA_TXDONE 0x00000040U +#define SPI_STA_TXDONE_M 0x00000040U +#define SPI_STA_TXDONE_S 6U +#define SPI_STA_TXDONE_TX_DONE 0x00000040U +#define SPI_STA_TXDONE_TX_ONGOING 0x00000000U + +// Field: [5] CSD +// +// Detection of CS deassertion in the middle of a data frame transmission +// results in this error being set. This feature is only available in the +// peripheral mode. +// ENUMs: +// ERR An error is generated when CS posedge +// (deassertion) is detected before the entire +// data frame is transmitted. +// NOERR No CS posedge is detected before the entire data +// frame has been transmitted. +#define SPI_STA_CSD 0x00000020U +#define SPI_STA_CSD_M 0x00000020U +#define SPI_STA_CSD_S 5U +#define SPI_STA_CSD_ERR 0x00000020U +#define SPI_STA_CSD_NOERR 0x00000000U + +// Field: [4] BUSY +// +// SPI Busy status +// ENUMs: +// ACTIVE SPI is currently transmitting and/or recieving +// data, or transmit FIFO is not empty. +// IDLE SPI is in idle mode. +#define SPI_STA_BUSY 0x00000010U +#define SPI_STA_BUSY_M 0x00000010U +#define SPI_STA_BUSY_S 4U +#define SPI_STA_BUSY_ACTIVE 0x00000010U +#define SPI_STA_BUSY_IDLE 0x00000000U + +// Field: [3] RNF +// +// Receive FIFO not full status. +// ENUMs: +// NOT_FULL Receive FIFO is not full. +// FULL Receive FIFO is full. +#define SPI_STA_RNF 0x00000008U +#define SPI_STA_RNF_M 0x00000008U +#define SPI_STA_RNF_S 3U +#define SPI_STA_RNF_NOT_FULL 0x00000008U +#define SPI_STA_RNF_FULL 0x00000000U + +// Field: [2] RFE +// +// Receive FIFO empty status. +// ENUMs: +// EMPTY Receive FIFO is empty. +// NOT_EMPTY Receive FIFO is not empty. +#define SPI_STA_RFE 0x00000004U +#define SPI_STA_RFE_M 0x00000004U +#define SPI_STA_RFE_S 2U +#define SPI_STA_RFE_EMPTY 0x00000004U +#define SPI_STA_RFE_NOT_EMPTY 0x00000000U + +// Field: [1] TNF +// +// Transmit FIFO not full status. +// ENUMs: +// NOT_FULL Transmit FIFO is not full. +// FULL Transmit FIFO is full. +#define SPI_STA_TNF 0x00000002U +#define SPI_STA_TNF_M 0x00000002U +#define SPI_STA_TNF_S 1U +#define SPI_STA_TNF_NOT_FULL 0x00000002U +#define SPI_STA_TNF_FULL 0x00000000U + +// Field: [0] TFE +// +// Transmit FIFO empty status. +// ENUMs: +// EMPTY Transmit FIFO is empty. +// NOT_EMPTY Transmit FIFO is not empty. +#define SPI_STA_TFE 0x00000001U +#define SPI_STA_TFE_M 0x00000001U +#define SPI_STA_TFE_S 0U +#define SPI_STA_TFE_EMPTY 0x00000001U +#define SPI_STA_TFE_NOT_EMPTY 0x00000000U + + +#endif // __SPI__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h new file mode 100644 index 00000000..82e77e70 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h @@ -0,0 +1,832 @@ +/****************************************************************************** +* Filename: hw_sys0_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SYS0_H__ +#define __HW_SYS0_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SYS0 component +// +//***************************************************************************** +// Description Register +#define SYS0_O_DESC 0x00000000U + +// Mutable section Unlock +#define SYS0_O_MUNLOCK 0x0000000CU + +// ATEST Configuration +#define SYS0_O_ATESTCFG 0x00000100U + +// TSENSE Configuration +#define SYS0_O_TSENSCFG 0x00000108U + +// LPCMP configuration +#define SYS0_O_LPCMPCFG 0x0000010CU + +// Device ID +#define SYS0_O_DEVICEID 0x000003FCU + +// Part ID +#define SYS0_O_PARTID 0x000007F8U + +// Internal. Only to be used through TI provided API. +#define SYS0_O_TMUTE0 0x00000800U + +// Internal. Only to be used through TI provided API. +#define SYS0_O_TMUTE1 0x00000804U + +// TMUTE2 trim Register +#define SYS0_O_TMUTE2 0x00000808U + +// Internal. Only to be used through TI provided API. +#define SYS0_O_TMUTE3 0x0000080CU + +// TMUTE4 trim Register +#define SYS0_O_TMUTE4 0x00000810U + +// Internal. Only to be used through TI provided API. +#define SYS0_O_TMUTE5 0x00000814U + +//***************************************************************************** +// +// Register: SYS0_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module Identifier is used to uniquely identify this IP +#define SYS0_DESC_MODID_W 16U +#define SYS0_DESC_MODID_M 0xFFFF0000U +#define SYS0_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set from aggregated +// IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define SYS0_DESC_STDIPOFF_W 4U +#define SYS0_DESC_STDIPOFF_M 0x0000F000U +#define SYS0_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define SYS0_DESC_INSTIDX_W 4U +#define SYS0_DESC_INSTIDX_M 0x00000F00U +#define SYS0_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define SYS0_DESC_MAJREV_W 4U +#define SYS0_DESC_MAJREV_M 0x000000F0U +#define SYS0_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define SYS0_DESC_MINREV_W 4U +#define SYS0_DESC_MINREV_M 0x0000000FU +#define SYS0_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_MUNLOCK +// +//***************************************************************************** +// Field: [31:0] KEY +// +// Write the unlock key 0xC5AF_6927 to temporarily unlock registers in mutable +// section. The lock is set automatically if no write accesses, to the mutable +// section, are detected for consecutive 32 CLKULL (24MHz) clock cycles. +// Writing any value other that the unlock key will immediately lock the +// mutable register space for write access. +// ENUMs: +// UNLOCK Unlock registers in the mutable section +// LOCK Lock registers in the mutable section +#define SYS0_MUNLOCK_KEY_W 32U +#define SYS0_MUNLOCK_KEY_M 0xFFFFFFFFU +#define SYS0_MUNLOCK_KEY_S 0U +#define SYS0_MUNLOCK_KEY_UNLOCK 0xC5AF6927U +#define SYS0_MUNLOCK_KEY_LOCK 0x00000000U + +//***************************************************************************** +// +// Register: SYS0_O_ATESTCFG +// +//***************************************************************************** +// Field: [31:24] KEY +// +// Key must be written with value 0x5A for successful write to ATESTCFG and to +// unlock register state. +// Write with any value other than 0x5A to KEY will be ignored and register +// content is not updated. +// It is recommended to write this register with incorrect KEY to lock back +// register state after necessary ATESTCFG updates are done. +// Read value of KEY is 0x0. +#define SYS0_ATESTCFG_KEY_W 8U +#define SYS0_ATESTCFG_KEY_M 0xFF000000U +#define SYS0_ATESTCFG_KEY_S 24U + +// Field: [8] VSEL +// +// Selects supply for ATEST switches. +// ENUMs: +// VDDA Selects VDDA +// VDDBST Selects VDDBOOST +#define SYS0_ATESTCFG_VSEL 0x00000100U +#define SYS0_ATESTCFG_VSEL_M 0x00000100U +#define SYS0_ATESTCFG_VSEL_S 8U +#define SYS0_ATESTCFG_VSEL_VDDA 0x00000100U +#define SYS0_ATESTCFG_VSEL_VDDBST 0x00000000U + +// Field: [7] VA2VA1 +// +// Enables isolation switch between VA_ATEST_A1 and VA_PAD_A1. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_VA2VA1 0x00000080U +#define SYS0_ATESTCFG_VA2VA1_M 0x00000080U +#define SYS0_ATESTCFG_VA2VA1_S 7U +#define SYS0_ATESTCFG_VA2VA1_CLOSE 0x00000080U +#define SYS0_ATESTCFG_VA2VA1_OPEN 0x00000000U + +// Field: [6] VA2VA0 +// +// Enables isolation switch between VA_ATEST_A0 and VA_PAD_A0. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_VA2VA0 0x00000040U +#define SYS0_ATESTCFG_VA2VA0_M 0x00000040U +#define SYS0_ATESTCFG_VA2VA0_S 6U +#define SYS0_ATESTCFG_VA2VA0_CLOSE 0x00000040U +#define SYS0_ATESTCFG_VA2VA0_OPEN 0x00000000U + +// Field: [5] VR2VA1 +// +// Enables isolation switch between VR_ATEST_A1 and VA_ATEST_A1. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_VR2VA1 0x00000020U +#define SYS0_ATESTCFG_VR2VA1_M 0x00000020U +#define SYS0_ATESTCFG_VR2VA1_S 5U +#define SYS0_ATESTCFG_VR2VA1_CLOSE 0x00000020U +#define SYS0_ATESTCFG_VR2VA1_OPEN 0x00000000U + +// Field: [4] VR2VA0 +// +// Enables isolation switch between VR_ATEST_A0 and VA_ATEST_A0. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_VR2VA0 0x00000010U +#define SYS0_ATESTCFG_VR2VA0_M 0x00000010U +#define SYS0_ATESTCFG_VR2VA0_S 4U +#define SYS0_ATESTCFG_VR2VA0_CLOSE 0x00000010U +#define SYS0_ATESTCFG_VR2VA0_OPEN 0x00000000U + +// Field: [3] SHTVA1 +// +// Shorts VA_ATEST_A1 to ground. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_SHTVA1 0x00000008U +#define SYS0_ATESTCFG_SHTVA1_M 0x00000008U +#define SYS0_ATESTCFG_SHTVA1_S 3U +#define SYS0_ATESTCFG_SHTVA1_CLOSE 0x00000008U +#define SYS0_ATESTCFG_SHTVA1_OPEN 0x00000000U + +// Field: [2] SHTVA0 +// +// Shorts VA_ATEST_A0 to ground. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_SHTVA0 0x00000004U +#define SYS0_ATESTCFG_SHTVA0_M 0x00000004U +#define SYS0_ATESTCFG_SHTVA0_S 2U +#define SYS0_ATESTCFG_SHTVA0_CLOSE 0x00000004U +#define SYS0_ATESTCFG_SHTVA0_OPEN 0x00000000U + +// Field: [1] SHTVR1 +// +// Shorts VR_ATEST_A1 to ground. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_SHTVR1 0x00000002U +#define SYS0_ATESTCFG_SHTVR1_M 0x00000002U +#define SYS0_ATESTCFG_SHTVR1_S 1U +#define SYS0_ATESTCFG_SHTVR1_CLOSE 0x00000002U +#define SYS0_ATESTCFG_SHTVR1_OPEN 0x00000000U + +// Field: [0] SHTVR0 +// +// Shorts VR_ATEST_A0 to ground. +// ENUMs: +// CLOSE Switch is closed +// OPEN Switch is open +#define SYS0_ATESTCFG_SHTVR0 0x00000001U +#define SYS0_ATESTCFG_SHTVR0_M 0x00000001U +#define SYS0_ATESTCFG_SHTVR0_S 0U +#define SYS0_ATESTCFG_SHTVR0_CLOSE 0x00000001U +#define SYS0_ATESTCFG_SHTVR0_OPEN 0x00000000U + +//***************************************************************************** +// +// Register: SYS0_O_TSENSCFG +// +//***************************************************************************** +// Field: [11:8] SPARE +// +// Spare bits +#define SYS0_TSENSCFG_SPARE_W 4U +#define SYS0_TSENSCFG_SPARE_M 0x00000F00U +#define SYS0_TSENSCFG_SPARE_S 8U + +// Field: [1:0] SEL +// +// Used to enable and configure temperature sensor module. Setting the value to +// 0x3 will disable the temperature sensor. +// ENUMs: +// GND 20uA current is injected on VR_ATEST_A0 and ground +// measured on VR_ATEST_A1 +// VALUE 20uA current is injected on VR_ATEST_A0 and +// voltage measured on VR_ATEST_A1 +// DISABLE Temperature sensor is disabled +#define SYS0_TSENSCFG_SEL_W 2U +#define SYS0_TSENSCFG_SEL_M 0x00000003U +#define SYS0_TSENSCFG_SEL_S 0U +#define SYS0_TSENSCFG_SEL_GND 0x00000002U +#define SYS0_TSENSCFG_SEL_VALUE 0x00000001U +#define SYS0_TSENSCFG_SEL_DISABLE 0x00000000U + +//***************************************************************************** +// +// Register: SYS0_O_LPCMPCFG +// +//***************************************************************************** +// Field: [30] HYSPOL +// +// Spare bit for LPCOMP +#define SYS0_LPCMPCFG_HYSPOL 0x40000000U +#define SYS0_LPCMPCFG_HYSPOL_M 0x40000000U +#define SYS0_LPCMPCFG_HYSPOL_S 30U + +// Field: [29:28] ATESTMUX +// +// Used to configure ATEST mux in comparator module and provides chosen output +// on VA_ATEST_A0. +// Note: This bit field is write-protected using global lock indicator on +// production device. +// ENUMs: +// IBIASOUT Selects bias current output +// COMP_VIN_NEG Selects voltage divider output +// COMPOUT Selects comparator output +// OFF ATEST mux is off +#define SYS0_LPCMPCFG_ATESTMUX_W 2U +#define SYS0_LPCMPCFG_ATESTMUX_M 0x30000000U +#define SYS0_LPCMPCFG_ATESTMUX_S 28U +#define SYS0_LPCMPCFG_ATESTMUX_IBIASOUT 0x30000000U +#define SYS0_LPCMPCFG_ATESTMUX_COMP_VIN_NEG 0x20000000U +#define SYS0_LPCMPCFG_ATESTMUX_COMPOUT 0x10000000U +#define SYS0_LPCMPCFG_ATESTMUX_OFF 0x00000000U + +// Field: [24] EVTIFG +// +// Event flag +// +// The event flag is set when the comparator output transition is qualified +// based on the edge polarity configuration in EDGCFG. +// ENUMs: +// SET +// CLR Clear +#define SYS0_LPCMPCFG_EVTIFG 0x01000000U +#define SYS0_LPCMPCFG_EVTIFG_M 0x01000000U +#define SYS0_LPCMPCFG_EVTIFG_S 24U +#define SYS0_LPCMPCFG_EVTIFG_SET 0x01000000U +#define SYS0_LPCMPCFG_EVTIFG_CLR 0x00000000U + +// Field: [21] COUTEN +// +// Enables LPCOMP output on device pin. +// ENUMs: +// EN Enabled +// DIS Disabled +#define SYS0_LPCMPCFG_COUTEN 0x00200000U +#define SYS0_LPCMPCFG_COUTEN_M 0x00200000U +#define SYS0_LPCMPCFG_COUTEN_S 21U +#define SYS0_LPCMPCFG_COUTEN_EN 0x00200000U +#define SYS0_LPCMPCFG_COUTEN_DIS 0x00000000U + +// Field: [20] COUT +// +// LPCOMP output status. This bit captures the value LPCOMP raw output. +// ENUMs: +// HIGH Output is high +// LOW Output is low +#define SYS0_LPCMPCFG_COUT 0x00100000U +#define SYS0_LPCMPCFG_COUT_M 0x00100000U +#define SYS0_LPCMPCFG_COUT_S 20U +#define SYS0_LPCMPCFG_COUT_HIGH 0x00100000U +#define SYS0_LPCMPCFG_COUT_LOW 0x00000000U + +// Field: [18] WUENSB +// +// Enables lpcmpcfg output to wake device from standby. +// ENUMs: +// EN Enable +// DIS Disable +#define SYS0_LPCMPCFG_WUENSB 0x00040000U +#define SYS0_LPCMPCFG_WUENSB_M 0x00040000U +#define SYS0_LPCMPCFG_WUENSB_S 18U +#define SYS0_LPCMPCFG_WUENSB_EN 0x00040000U +#define SYS0_LPCMPCFG_WUENSB_DIS 0x00000000U + +// Field: [17] EVTEN +// +// Enables event generation. Comparator module will produce event on ULL event +// fabric when EVTIFG is set. +// ENUMs: +// EN Enable +// DIS Disable +#define SYS0_LPCMPCFG_EVTEN 0x00020000U +#define SYS0_LPCMPCFG_EVTEN_M 0x00020000U +#define SYS0_LPCMPCFG_EVTEN_S 17U +#define SYS0_LPCMPCFG_EVTEN_EN 0x00020000U +#define SYS0_LPCMPCFG_EVTEN_DIS 0x00000000U + +// Field: [16] EDGCFG +// +// Selects positive edge or negative edge detection on comparator output to set +// the event flag +// ENUMs: +// FALL Fall edge detection +// RISE Rise edge detection +#define SYS0_LPCMPCFG_EDGCFG 0x00010000U +#define SYS0_LPCMPCFG_EDGCFG_M 0x00010000U +#define SYS0_LPCMPCFG_EDGCFG_S 16U +#define SYS0_LPCMPCFG_EDGCFG_FALL 0x00010000U +#define SYS0_LPCMPCFG_EDGCFG_RISE 0x00000000U + +// Field: [14:12] NSEL +// +// Negative input selection. Setting values 0x5-0x7 will open all the switches. +// ENUMs: +// VDDD Selects VDDD +// VDDA Selects VDDA +// VA_PAD_A3 Selects VA_PAD_A3 +// VA_PAD_A2 Selects VA_PAD_A2 +// OPEN All switches are open +#define SYS0_LPCMPCFG_NSEL_W 3U +#define SYS0_LPCMPCFG_NSEL_M 0x00007000U +#define SYS0_LPCMPCFG_NSEL_S 12U +#define SYS0_LPCMPCFG_NSEL_VDDD 0x00004000U +#define SYS0_LPCMPCFG_NSEL_VDDA 0x00003000U +#define SYS0_LPCMPCFG_NSEL_VA_PAD_A3 0x00002000U +#define SYS0_LPCMPCFG_NSEL_VA_PAD_A2 0x00001000U +#define SYS0_LPCMPCFG_NSEL_OPEN 0x00000000U + +// Field: [11:8] PSEL +// +// Positive input selection. Setting values 0x9-0xF will open all the switches. +// ENUMs: +// VDDA Selects VDDA +// VA_ATEST_A1 Selects VA_ATEST_A1 +// VA_ATEST_A0 Selects VA_ATEST_A0 +// VR_ATEST_A1 Selects VR_ATEST_A1 +// VR_ATEST_A0 Selects VR_ATEST_A0 +// VA_PAD_A3 Selects VA_PAD_A3 +// VA_PAD_A2 Selects VA_PAD_A2 +// VA_PAD_A1 Selects VA_PAD_A1 +// OPEN All switches are open +#define SYS0_LPCMPCFG_PSEL_W 4U +#define SYS0_LPCMPCFG_PSEL_M 0x00000F00U +#define SYS0_LPCMPCFG_PSEL_S 8U +#define SYS0_LPCMPCFG_PSEL_VDDA 0x00000800U +#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A1 0x00000700U +#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A0 0x00000600U +#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A1 0x00000500U +#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A0 0x00000400U +#define SYS0_LPCMPCFG_PSEL_VA_PAD_A3 0x00000300U +#define SYS0_LPCMPCFG_PSEL_VA_PAD_A2 0x00000200U +#define SYS0_LPCMPCFG_PSEL_VA_PAD_A1 0x00000100U +#define SYS0_LPCMPCFG_PSEL_OPEN 0x00000000U + +// Field: [7:5] HYSSEL +// +// Used to enable and select hysteresis level +// +// Hysteresis is disabled when HYSSEL = 0 and enabled for other values of +// HYSSEL from 1 to 7. Refer to device specific datasheet for individual +// hysteresis values. +// ENUMs: +// VAL7 Hysteresis value: TBD +// VAL6 Hysteresis value: TBD +// VAL5 Hysteresis value: TBD +// VAL4 Hysteresis value: TBD +// VAL3 Hysteresis value: TBD +// VAL2 Hysteresis value: TBD +// VAL1 Hysteresis value: TBD +// VAL0 Hysteresis is disabled +#define SYS0_LPCMPCFG_HYSSEL_W 3U +#define SYS0_LPCMPCFG_HYSSEL_M 0x000000E0U +#define SYS0_LPCMPCFG_HYSSEL_S 5U +#define SYS0_LPCMPCFG_HYSSEL_VAL7 0x000000E0U +#define SYS0_LPCMPCFG_HYSSEL_VAL6 0x000000C0U +#define SYS0_LPCMPCFG_HYSSEL_VAL5 0x000000A0U +#define SYS0_LPCMPCFG_HYSSEL_VAL4 0x00000080U +#define SYS0_LPCMPCFG_HYSSEL_VAL3 0x00000060U +#define SYS0_LPCMPCFG_HYSSEL_VAL2 0x00000040U +#define SYS0_LPCMPCFG_HYSSEL_VAL1 0x00000020U +#define SYS0_LPCMPCFG_HYSSEL_VAL0 0x00000000U + +// Field: [4] DIVPATH +// +// Used to select the path on which voltage divider is applied +// ENUMs: +// PSIDE Divider is applied on P-side +// NSIDE Divider is applied on N-side +#define SYS0_LPCMPCFG_DIVPATH 0x00000010U +#define SYS0_LPCMPCFG_DIVPATH_M 0x00000010U +#define SYS0_LPCMPCFG_DIVPATH_S 4U +#define SYS0_LPCMPCFG_DIVPATH_PSIDE 0x00000010U +#define SYS0_LPCMPCFG_DIVPATH_NSIDE 0x00000000U + +// Field: [3:1] DIV +// +// Used to configure reference divider. Setting values 0x5-0x7 will set the +// divide value to 1. +// ENUMs: +// VAL4 Divide value is 1/4 +// VAL3 Divide value is 1/3 +// VAL2 Divide value is 1/2 +// VAL1 Divide value is 3/4 +// VAL0 Divide value is 1 +#define SYS0_LPCMPCFG_DIV_W 3U +#define SYS0_LPCMPCFG_DIV_M 0x0000000EU +#define SYS0_LPCMPCFG_DIV_S 1U +#define SYS0_LPCMPCFG_DIV_VAL4 0x00000008U +#define SYS0_LPCMPCFG_DIV_VAL3 0x00000006U +#define SYS0_LPCMPCFG_DIV_VAL2 0x00000004U +#define SYS0_LPCMPCFG_DIV_VAL1 0x00000002U +#define SYS0_LPCMPCFG_DIV_VAL0 0x00000000U + +// Field: [0] EN +// +// Used to enable comparator module. +// ENUMs: +// EN Enable +// DIS Disable +#define SYS0_LPCMPCFG_EN 0x00000001U +#define SYS0_LPCMPCFG_EN_M 0x00000001U +#define SYS0_LPCMPCFG_EN_S 0U +#define SYS0_LPCMPCFG_EN_EN 0x00000001U +#define SYS0_LPCMPCFG_EN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYS0_O_DEVICEID +// +//***************************************************************************** +// Field: [31:28] VERSION +// +// Monotonic increasing value indicating new hardware revision. A newer +// hardware revision shall never have a lower version than an older revision of +// hardware. +#define SYS0_DEVICEID_VERSION_W 4U +#define SYS0_DEVICEID_VERSION_M 0xF0000000U +#define SYS0_DEVICEID_VERSION_S 28U + +// Field: [27:12] DEVICE +// +// Value generated by RAMP for the SOC. This value uniquely identifies the die +// from any other TI device. +#define SYS0_DEVICEID_DEVICE_W 16U +#define SYS0_DEVICEID_DEVICE_M 0x0FFFF000U +#define SYS0_DEVICEID_DEVICE_S 12U + +// Field: [11:1] MANFACTURER +// +// JEP 106 assigned manufacturer ID. This field identifies the device as a +// Texas Instruments device. +#define SYS0_DEVICEID_MANFACTURER_W 11U +#define SYS0_DEVICEID_MANFACTURER_M 0x00000FFEU +#define SYS0_DEVICEID_MANFACTURER_S 1U + +// Field: [0] ALWAYSONE +// +// Value 1 in this bit field means that a 32-bit scan register exists. +#define SYS0_DEVICEID_ALWAYSONE 0x00000001U +#define SYS0_DEVICEID_ALWAYSONE_M 0x00000001U +#define SYS0_DEVICEID_ALWAYSONE_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_PARTID +// +//***************************************************************************** +// Field: [31] START +// +// Start bit +// ENUMs: +// SET +// CLR Clear +#define SYS0_PARTID_START 0x80000000U +#define SYS0_PARTID_START_M 0x80000000U +#define SYS0_PARTID_START_S 31U +#define SYS0_PARTID_START_SET 0x80000000U +#define SYS0_PARTID_START_CLR 0x00000000U + +// Field: [30:28] MAJORREV +// +// Monotonic increasing value indicating a new revision of the SKU significant +// enough that users of the device may have to revise PCB or software design +#define SYS0_PARTID_MAJORREV_W 3U +#define SYS0_PARTID_MAJORREV_M 0x70000000U +#define SYS0_PARTID_MAJORREV_S 28U + +// Field: [27:24] MINORREV +// +// Monotonic increasing value indicating a new revision of the SKU that +// preserves compatibility with lesser MINORREV values +#define SYS0_PARTID_MINORREV_W 4U +#define SYS0_PARTID_MINORREV_M 0x0F000000U +#define SYS0_PARTID_MINORREV_S 24U + +// Field: [23:16] VARIANT +// +// Bit pattern uniquely identifying a variant of a part +#define SYS0_PARTID_VARIANT_W 8U +#define SYS0_PARTID_VARIANT_M 0x00FF0000U +#define SYS0_PARTID_VARIANT_S 16U + +// Field: [15:0] PART +// +// Bit pattern uniquely identifying a part +#define SYS0_PARTID_PART_W 16U +#define SYS0_PARTID_PART_M 0x0000FFFFU +#define SYS0_PARTID_PART_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE0 +// +//***************************************************************************** +// Field: [31:0] CDACL +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE0_CDACL_W 32U +#define SYS0_TMUTE0_CDACL_M 0xFFFFFFFFU +#define SYS0_TMUTE0_CDACL_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE1 +// +//***************************************************************************** +// Field: [31:0] CDACM +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE1_CDACM_W 32U +#define SYS0_TMUTE1_CDACM_M 0xFFFFFFFFU +#define SYS0_TMUTE1_CDACM_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE2 +// +//***************************************************************************** +// Field: [30:26] IBTRIM +// +// LPCOMP: Bias current trim, 250nA to be terminated across I2V, 1M ohm +// setting. Resulting target trim voltage 250mV. +#define SYS0_TMUTE2_IBTRIM_W 5U +#define SYS0_TMUTE2_IBTRIM_M 0x7C000000U +#define SYS0_TMUTE2_IBTRIM_S 26U + +// Field: [25:23] TRIM +// +// ADC REFBUF trim bits. +#define SYS0_TMUTE2_TRIM_W 3U +#define SYS0_TMUTE2_TRIM_M 0x03800000U +#define SYS0_TMUTE2_TRIM_S 23U + +// Field: [22:16] LATCH +// +// SOC ADC: Latch trim bits. These bits are used in the analog IP. +#define SYS0_TMUTE2_LATCH_W 7U +#define SYS0_TMUTE2_LATCH_M 0x007F0000U +#define SYS0_TMUTE2_LATCH_S 16U + +// Field: [15:4] OFFSET +// +// SOCADC: Offset trim bits. These bits are used in DTC. +#define SYS0_TMUTE2_OFFSET_W 12U +#define SYS0_TMUTE2_OFFSET_M 0x0000FFF0U +#define SYS0_TMUTE2_OFFSET_S 4U + +// Field: [3:2] RES +// +// SOCADC: Resistor trim bits. These bits are used in the analog IP. +#define SYS0_TMUTE2_RES_W 2U +#define SYS0_TMUTE2_RES_M 0x0000000CU +#define SYS0_TMUTE2_RES_S 2U + +// Field: [1:0] CDACU +// +// SOCADC: Upper 2 bits of CDAC trim. These bits are used in DTC. +#define SYS0_TMUTE2_CDACU_W 2U +#define SYS0_TMUTE2_CDACU_M 0x00000003U +#define SYS0_TMUTE2_CDACU_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE3 +// +//***************************************************************************** +// Field: [31:26] BATC1 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE3_BATC1_W 6U +#define SYS0_TMUTE3_BATC1_M 0xFC000000U +#define SYS0_TMUTE3_BATC1_S 26U + +// Field: [25:19] BATC0 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE3_BATC0_W 7U +#define SYS0_TMUTE3_BATC0_M 0x03F80000U +#define SYS0_TMUTE3_BATC0_S 19U + +// Field: [18:14] TEMPC2 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE3_TEMPC2_W 5U +#define SYS0_TMUTE3_TEMPC2_M 0x0007C000U +#define SYS0_TMUTE3_TEMPC2_S 14U + +// Field: [13:8] TEMPC1 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE3_TEMPC1_W 6U +#define SYS0_TMUTE3_TEMPC1_M 0x00003F00U +#define SYS0_TMUTE3_TEMPC1_S 8U + +// Field: [7:0] TEMPC0 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE3_TEMPC0_W 8U +#define SYS0_TMUTE3_TEMPC0_M 0x000000FFU +#define SYS0_TMUTE3_TEMPC0_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE4 +// +//***************************************************************************** +// Field: [31:28] RECHCOMPREFLVL +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_RECHCOMPREFLVL_W 4U +#define SYS0_TMUTE4_RECHCOMPREFLVL_M 0xF0000000U +#define SYS0_TMUTE4_RECHCOMPREFLVL_S 28U + +// Field: [27:26] IOSTRCFG2 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_IOSTRCFG2_W 2U +#define SYS0_TMUTE4_IOSTRCFG2_M 0x0C000000U +#define SYS0_TMUTE4_IOSTRCFG2_S 26U + +// Field: [25:22] IOSTRCFG1 +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_IOSTRCFG1_W 4U +#define SYS0_TMUTE4_IOSTRCFG1_M 0x03C00000U +#define SYS0_TMUTE4_IOSTRCFG1_S 22U + +// Field: [21:19] MAX +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_MAX_W 3U +#define SYS0_TMUTE4_MAX_M 0x00380000U +#define SYS0_TMUTE4_MAX_S 19U + +// Field: [18:16] MED +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_MED_W 3U +#define SYS0_TMUTE4_MED_M 0x00070000U +#define SYS0_TMUTE4_MED_S 16U + +// Field: [15:13] MIN +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_MIN_W 3U +#define SYS0_TMUTE4_MIN_M 0x0000E000U +#define SYS0_TMUTE4_MIN_S 13U + +// Field: [12:11] DCDCLOAD +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_DCDCLOAD_W 2U +#define SYS0_TMUTE4_DCDCLOAD_M 0x00001800U +#define SYS0_TMUTE4_DCDCLOAD_S 11U + +// Field: [10:8] IPEAK +// +// DCDC: Set inductor peak current +#define SYS0_TMUTE4_IPEAK_W 3U +#define SYS0_TMUTE4_IPEAK_M 0x00000700U +#define SYS0_TMUTE4_IPEAK_S 8U + +// Field: [7:6] DTIME +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_DTIME_W 2U +#define SYS0_TMUTE4_DTIME_M 0x000000C0U +#define SYS0_TMUTE4_DTIME_S 6U + +// Field: [5:3] LENSEL +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_LENSEL_W 3U +#define SYS0_TMUTE4_LENSEL_M 0x00000038U +#define SYS0_TMUTE4_LENSEL_S 3U + +// Field: [2:0] HENSEL +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE4_HENSEL_W 3U +#define SYS0_TMUTE4_HENSEL_M 0x00000007U +#define SYS0_TMUTE4_HENSEL_S 0U + +//***************************************************************************** +// +// Register: SYS0_O_TMUTE5 +// +//***************************************************************************** +// Field: [12:10] DCDCDRVDS +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE5_DCDCDRVDS_W 3U +#define SYS0_TMUTE5_DCDCDRVDS_M 0x00001C00U +#define SYS0_TMUTE5_DCDCDRVDS_S 10U + +// Field: [9:5] GLDOISCLR +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE5_GLDOISCLR_W 5U +#define SYS0_TMUTE5_GLDOISCLR_M 0x000003E0U +#define SYS0_TMUTE5_GLDOISCLR_S 5U + +// Field: [4:0] GLDOISSET +// +// Internal. Only to be used through TI provided API. +#define SYS0_TMUTE5_GLDOISSET_W 5U +#define SYS0_TMUTE5_GLDOISSET_M 0x0000001FU +#define SYS0_TMUTE5_GLDOISSET_S 0U + + +#endif // __SYS0__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sysctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sysctl.h new file mode 100644 index 00000000..973698ce --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sysctl.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systick.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systick.h new file mode 100644 index 00000000..4e297387 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systick.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_systick_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SYSTICK_H__ +#define __HW_SYSTICK_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SYSTICK component +// +//***************************************************************************** +// SysTick Control and Status Register +#define SYSTICK_O_CSR 0x00000000U + +// SysTick Reload Value Register +#define SYSTICK_O_RVR 0x00000004U + +// SysTick Current Value Register +#define SYSTICK_O_CVR 0x00000008U + +// SysTick Calibration Value Register +#define SYSTICK_O_CALIB 0x0000000CU + +//***************************************************************************** +// +// Register: SYSTICK_O_CSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application or debugger. +#define SYSTICK_CSR_COUNTFLAG 0x00010000U +#define SYSTICK_CSR_COUNTFLAG_M 0x00010000U +#define SYSTICK_CSR_COUNTFLAG_S 16U + +// Field: [2] CLKSOURCE +// +// SysTick clock source. Always reads as one if STCALIB reports NOREF. +// 0x0:Systick driven by external reference clock. +// 0x1:Systick driven by processor clock +#define SYSTICK_CSR_CLKSOURCE 0x00000004U +#define SYSTICK_CSR_CLKSOURCE_M 0x00000004U +#define SYSTICK_CSR_CLKSOURCE_S 2U + +// Field: [1] TICKINT +// +// +// 0x0:Counting down to zero does not pend the systick handler. software can +// use countflag to determine if the systick handler has ever counted to zero. +// 0x1:Counting down to zero pends the systick handler. +#define SYSTICK_CSR_TICKINT 0x00000002U +#define SYSTICK_CSR_TICKINT_M 0x00000002U +#define SYSTICK_CSR_TICKINT_S 1U + +// Field: [0] ENABLE +// +// Enable SysTick counter +// 0x0:Counter disabled +// 0x1:Counter operates in a multi-shot way. that is, counter loads with the +// reload value and then begins counting down. on reaching 0, it sets the +// countflag to 1 and optionally pends the systick handler, based on tickint. +// it then loads the reload value again, and begins counting. +#define SYSTICK_CSR_ENABLE 0x00000001U +#define SYSTICK_CSR_ENABLE_M 0x00000001U +#define SYSTICK_CSR_ENABLE_S 0U + +//***************************************************************************** +// +// Register: SYSTICK_O_RVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register when the counter +// reaches 0. +#define SYSTICK_RVR_RELOAD_W 24U +#define SYSTICK_RVR_RELOAD_M 0x00FFFFFFU +#define SYSTICK_RVR_RELOAD_S 0U + +//***************************************************************************** +// +// Register: SYSTICK_O_CVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Reads return the current value of the SysTick counter. This register is +// write-clear. Writing to it with any value clears the register to 0. Clearing +// this register also clears the COUNTFLAG bit of the SysTick Control and +// Status Register. +#define SYSTICK_CVR_CURRENT_W 24U +#define SYSTICK_CVR_CURRENT_M 0x00FFFFFFU +#define SYSTICK_CVR_CURRENT_S 0U + +//***************************************************************************** +// +// Register: SYSTICK_O_CALIB +// +//***************************************************************************** +// Field: [31] NOREF +// +// If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of +// the SysTick Control and Status register will be forced to 1 and cannot be +// cleared to 0. +#define SYSTICK_CALIB_NOREF 0x80000000U +#define SYSTICK_CALIB_NOREF_M 0x80000000U +#define SYSTICK_CALIB_NOREF_S 31U + +// Field: [30] SKEW +// +// If reads as 1, the calibration value for 10ms is inexact (due to clock +// frequency). +#define SYSTICK_CALIB_SKEW 0x40000000U +#define SYSTICK_CALIB_SKEW_M 0x40000000U +#define SYSTICK_CALIB_SKEW_S 30U + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. If the value reads as 0, the calibration value is +// not known. +#define SYSTICK_CALIB_TENMS_W 24U +#define SYSTICK_CALIB_TENMS_M 0x00FFFFFFU +#define SYSTICK_CALIB_TENMS_S 0U + + +#endif // __SYSTICK__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systim.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systim.h new file mode 100644 index 00000000..1057174a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_systim.h @@ -0,0 +1,1436 @@ +/****************************************************************************** +* Filename: hw_systim_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_SYSTIM_H__ +#define __HW_SYSTIM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SYSTIM component +// +//***************************************************************************** +// Module Description +#define SYSTIM_O_DESC 0x00000000U + +// Interrupt mask +#define SYSTIM_O_IMASK 0x00000044U + +// Raw interrupt status +#define SYSTIM_O_RIS 0x00000048U + +// Masked interrupt status +#define SYSTIM_O_MIS 0x0000004CU + +// Interrupt set +#define SYSTIM_O_ISET 0x00000050U + +// Interrupt clear +#define SYSTIM_O_ICLR 0x00000054U + +// Interrupt mask set +#define SYSTIM_O_IMSET 0x00000058U + +// Interrupt mask clear +#define SYSTIM_O_IMCLR 0x0000005CU + +// Emulation +#define SYSTIM_O_EMU 0x00000060U + +// Systime Count Value [31:0] +#define SYSTIM_O_TIME250N 0x00000100U + +// Systime Count Value [33:2] +#define SYSTIM_O_TIME1U 0x00000104U + +// channel's Ouput Value +#define SYSTIM_O_OUT 0x00000108U + +// channel0 Configuration. +#define SYSTIM_O_CH0CFG 0x0000010CU + +// channel1 Configuration. +#define SYSTIM_O_CH1CFG 0x00000110U + +// channel2 Configuration. +#define SYSTIM_O_CH2CFG 0x00000114U + +// channel3 Configuration. +#define SYSTIM_O_CH3CFG 0x00000118U + +// channel4 Configuration. +#define SYSTIM_O_CH4CFG 0x0000011CU + +// Channel 0 Capture/Compare Value +#define SYSTIM_O_CH0CC 0x00000120U + +// Channel 1 Capture/Compare Value +#define SYSTIM_O_CH1CC 0x00000124U + +// Channel 2 Capture/Compare Value +#define SYSTIM_O_CH2CC 0x00000128U + +// Channel 3 Capture/Compare Value +#define SYSTIM_O_CH3CC 0x0000012CU + +// Channel 4 Capture/Compare Value +#define SYSTIM_O_CH4CC 0x00000130U + +// Systimer's Time bit +#define SYSTIM_O_TIMEBIT 0x00000134U + +// Timer Status +#define SYSTIM_O_STATUS 0x00000140U + +// Channel arming set +#define SYSTIM_O_ARMSET 0x00000144U + +// Channel Arming clear +#define SYSTIM_O_ARMCLR 0x00000148U + +// Channel 0 Save/Restore Value +#define SYSTIM_O_CH0CCSR 0x0000014CU + +// Channel 1 Save/Restore Value +#define SYSTIM_O_CH1CCSR 0x00000150U + +// Channel 2 Save/Restore Value +#define SYSTIM_O_CH2CCSR 0x00000154U + +// Channel 3 Save/Restore Value +#define SYSTIM_O_CH3CCSR 0x00000158U + +// Channel 4 Save/Restore Value +#define SYSTIM_O_CH4CCSR 0x0000015CU + +//***************************************************************************** +// +// Register: SYSTIM_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define SYSTIM_DESC_MODID_W 16U +#define SYSTIM_DESC_MODID_M 0xFFFF0000U +#define SYSTIM_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define SYSTIM_DESC_STDIPOFF_W 4U +#define SYSTIM_DESC_STDIPOFF_M 0x0000F000U +#define SYSTIM_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exists in SOC, this field +// can identify the instance number 0-15 +#define SYSTIM_DESC_INSTIDX_W 4U +#define SYSTIM_DESC_INSTIDX_M 0x00000F00U +#define SYSTIM_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP 0-15 +#define SYSTIM_DESC_MAJREV_W 4U +#define SYSTIM_DESC_MAJREV_M 0x000000F0U +#define SYSTIM_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP 0-15. +#define SYSTIM_DESC_MINREV_W 4U +#define SYSTIM_DESC_MINREV_M 0x0000000FU +#define SYSTIM_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_IMASK +// +//***************************************************************************** +// Field: [5] OVFL +// +// Systimer counter overflow event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_OVFL 0x00000020U +#define SYSTIM_IMASK_OVFL_M 0x00000020U +#define SYSTIM_IMASK_OVFL_S 5U +#define SYSTIM_IMASK_OVFL_EN 0x00000020U +#define SYSTIM_IMASK_OVFL_DIS 0x00000000U + +// Field: [4] EV4 +// +// Systimer channel 4 event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_EV4 0x00000010U +#define SYSTIM_IMASK_EV4_M 0x00000010U +#define SYSTIM_IMASK_EV4_S 4U +#define SYSTIM_IMASK_EV4_EN 0x00000010U +#define SYSTIM_IMASK_EV4_DIS 0x00000000U + +// Field: [3] EV3 +// +// Systimer channel 3 event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_EV3 0x00000008U +#define SYSTIM_IMASK_EV3_M 0x00000008U +#define SYSTIM_IMASK_EV3_S 3U +#define SYSTIM_IMASK_EV3_EN 0x00000008U +#define SYSTIM_IMASK_EV3_DIS 0x00000000U + +// Field: [2] EV2 +// +// Systimer channel 2 event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_EV2 0x00000004U +#define SYSTIM_IMASK_EV2_M 0x00000004U +#define SYSTIM_IMASK_EV2_S 2U +#define SYSTIM_IMASK_EV2_EN 0x00000004U +#define SYSTIM_IMASK_EV2_DIS 0x00000000U + +// Field: [1] EV1 +// +// Systimer channel 1 event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_EV1 0x00000002U +#define SYSTIM_IMASK_EV1_M 0x00000002U +#define SYSTIM_IMASK_EV1_S 1U +#define SYSTIM_IMASK_EV1_EN 0x00000002U +#define SYSTIM_IMASK_EV1_DIS 0x00000000U + +// Field: [0] EV0 +// +// Systimer channel 0 event interrupt mask. +// ENUMs: +// EN Enable Interrrupt Mask +// DIS Disable Interrupt Mask +#define SYSTIM_IMASK_EV0 0x00000001U +#define SYSTIM_IMASK_EV0_M 0x00000001U +#define SYSTIM_IMASK_EV0_S 0U +#define SYSTIM_IMASK_EV0_EN 0x00000001U +#define SYSTIM_IMASK_EV0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_RIS +// +//***************************************************************************** +// Field: [5] OVFL +// +// Raw interrupt status for Systimer counter overflow event. +// This bit is set to 1 when an event is received on SysTimer Overflow occurs. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_OVFL 0x00000020U +#define SYSTIM_RIS_OVFL_M 0x00000020U +#define SYSTIM_RIS_OVFL_S 5U +#define SYSTIM_RIS_OVFL_SET 0x00000020U +#define SYSTIM_RIS_OVFL_CLR 0x00000000U + +// Field: [4] EV4 +// +// Raw interrupt status for channel 4 event. +// This bit is set to 1 when a CAPTURE or COMPARE event is received on channel +// 4. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_EV4 0x00000010U +#define SYSTIM_RIS_EV4_M 0x00000010U +#define SYSTIM_RIS_EV4_S 4U +#define SYSTIM_RIS_EV4_SET 0x00000010U +#define SYSTIM_RIS_EV4_CLR 0x00000000U + +// Field: [3] EV3 +// +// Raw interrupt status for channel 3 event. +// This bit is set to 1 when a CAPTURE or COMPARE event is received on channel +// 3. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_EV3 0x00000008U +#define SYSTIM_RIS_EV3_M 0x00000008U +#define SYSTIM_RIS_EV3_S 3U +#define SYSTIM_RIS_EV3_SET 0x00000008U +#define SYSTIM_RIS_EV3_CLR 0x00000000U + +// Field: [2] EV2 +// +// Raw interrupt status for channel 2 Event. +// This bit is set to 1 when a CAPTURE or COMPARE event is received on channel +// 2. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_EV2 0x00000004U +#define SYSTIM_RIS_EV2_M 0x00000004U +#define SYSTIM_RIS_EV2_S 2U +#define SYSTIM_RIS_EV2_SET 0x00000004U +#define SYSTIM_RIS_EV2_CLR 0x00000000U + +// Field: [1] EV1 +// +// Raw interrupt status for channel 1 event. +// This bit is set to 1 when a CAPTURE or COMPARE event is received on channel +// 1. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_EV1 0x00000002U +#define SYSTIM_RIS_EV1_M 0x00000002U +#define SYSTIM_RIS_EV1_S 1U +#define SYSTIM_RIS_EV1_SET 0x00000002U +#define SYSTIM_RIS_EV1_CLR 0x00000000U + +// Field: [0] EV0 +// +// Raw interrupt status for channel 0 event. +// This bit is set to 1 when a CAPTURE or COMPARE event is received on channel +// 0. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_RIS_EV0 0x00000001U +#define SYSTIM_RIS_EV0_M 0x00000001U +#define SYSTIM_RIS_EV0_S 0U +#define SYSTIM_RIS_EV0_SET 0x00000001U +#define SYSTIM_RIS_EV0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_MIS +// +//***************************************************************************** +// Field: [5] OVFL +// +// Mask Interrupt status for Systimer counter overflow Event in MIS register. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_OVFL 0x00000020U +#define SYSTIM_MIS_OVFL_M 0x00000020U +#define SYSTIM_MIS_OVFL_S 5U +#define SYSTIM_MIS_OVFL_SET 0x00000020U +#define SYSTIM_MIS_OVFL_CLR 0x00000000U + +// Field: [4] EV4 +// +// Mask interrupt status for channel 4 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_EV4 0x00000010U +#define SYSTIM_MIS_EV4_M 0x00000010U +#define SYSTIM_MIS_EV4_S 4U +#define SYSTIM_MIS_EV4_SET 0x00000010U +#define SYSTIM_MIS_EV4_CLR 0x00000000U + +// Field: [3] EV3 +// +// Mask interrupt status for channel 3 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_EV3 0x00000008U +#define SYSTIM_MIS_EV3_M 0x00000008U +#define SYSTIM_MIS_EV3_S 3U +#define SYSTIM_MIS_EV3_SET 0x00000008U +#define SYSTIM_MIS_EV3_CLR 0x00000000U + +// Field: [2] EV2 +// +// Mask interrupt status for channel 2 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_EV2 0x00000004U +#define SYSTIM_MIS_EV2_M 0x00000004U +#define SYSTIM_MIS_EV2_S 2U +#define SYSTIM_MIS_EV2_SET 0x00000004U +#define SYSTIM_MIS_EV2_CLR 0x00000000U + +// Field: [1] EV1 +// +// Mask interrupt status for channel 1 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_EV1 0x00000002U +#define SYSTIM_MIS_EV1_M 0x00000002U +#define SYSTIM_MIS_EV1_S 1U +#define SYSTIM_MIS_EV1_SET 0x00000002U +#define SYSTIM_MIS_EV1_CLR 0x00000000U + +// Field: [0] EV0 +// +// Mask interrupt status for channel 0 event. +// ENUMs: +// SET Interrupt occured +// CLR Interrupt did not occur +#define SYSTIM_MIS_EV0 0x00000001U +#define SYSTIM_MIS_EV0_M 0x00000001U +#define SYSTIM_MIS_EV0_S 0U +#define SYSTIM_MIS_EV0_SET 0x00000001U +#define SYSTIM_MIS_EV0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_ISET +// +//***************************************************************************** +// Field: [5] OVFL +// +// Sets Systimer counter overflow interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_OVFL 0x00000020U +#define SYSTIM_ISET_OVFL_M 0x00000020U +#define SYSTIM_ISET_OVFL_S 5U +#define SYSTIM_ISET_OVFL_SET 0x00000020U +#define SYSTIM_ISET_OVFL_NOEFF 0x00000000U + +// Field: [4] EV4 +// +// Sets channel 4 interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_EV4 0x00000010U +#define SYSTIM_ISET_EV4_M 0x00000010U +#define SYSTIM_ISET_EV4_S 4U +#define SYSTIM_ISET_EV4_SET 0x00000010U +#define SYSTIM_ISET_EV4_NOEFF 0x00000000U + +// Field: [3] EV3 +// +// Sets channel 3 interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_EV3 0x00000008U +#define SYSTIM_ISET_EV3_M 0x00000008U +#define SYSTIM_ISET_EV3_S 3U +#define SYSTIM_ISET_EV3_SET 0x00000008U +#define SYSTIM_ISET_EV3_NOEFF 0x00000000U + +// Field: [2] EV2 +// +// Sets channel 2 interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_EV2 0x00000004U +#define SYSTIM_ISET_EV2_M 0x00000004U +#define SYSTIM_ISET_EV2_S 2U +#define SYSTIM_ISET_EV2_SET 0x00000004U +#define SYSTIM_ISET_EV2_NOEFF 0x00000000U + +// Field: [1] EV1 +// +// Sets channel 1 interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_EV1 0x00000002U +#define SYSTIM_ISET_EV1_M 0x00000002U +#define SYSTIM_ISET_EV1_S 1U +#define SYSTIM_ISET_EV1_SET 0x00000002U +#define SYSTIM_ISET_EV1_NOEFF 0x00000000U + +// Field: [0] EV0 +// +// Sets channel 0 interrupt. +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ISET_EV0 0x00000001U +#define SYSTIM_ISET_EV0_M 0x00000001U +#define SYSTIM_ISET_EV0_S 0U +#define SYSTIM_ISET_EV0_SET 0x00000001U +#define SYSTIM_ISET_EV0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_ICLR +// +//***************************************************************************** +// Field: [5] OVFL +// +// Clears Systimer counter overflow interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_OVFL 0x00000020U +#define SYSTIM_ICLR_OVFL_M 0x00000020U +#define SYSTIM_ICLR_OVFL_S 5U +#define SYSTIM_ICLR_OVFL_CLR 0x00000020U +#define SYSTIM_ICLR_OVFL_NOEFF 0x00000000U + +// Field: [4] EV4 +// +// Clears channel 4 interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_EV4 0x00000010U +#define SYSTIM_ICLR_EV4_M 0x00000010U +#define SYSTIM_ICLR_EV4_S 4U +#define SYSTIM_ICLR_EV4_CLR 0x00000010U +#define SYSTIM_ICLR_EV4_NOEFF 0x00000000U + +// Field: [3] EV3 +// +// Clears channel 3 interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_EV3 0x00000008U +#define SYSTIM_ICLR_EV3_M 0x00000008U +#define SYSTIM_ICLR_EV3_S 3U +#define SYSTIM_ICLR_EV3_CLR 0x00000008U +#define SYSTIM_ICLR_EV3_NOEFF 0x00000000U + +// Field: [2] EV2 +// +// Clears channel 2 interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_EV2 0x00000004U +#define SYSTIM_ICLR_EV2_M 0x00000004U +#define SYSTIM_ICLR_EV2_S 2U +#define SYSTIM_ICLR_EV2_CLR 0x00000004U +#define SYSTIM_ICLR_EV2_NOEFF 0x00000000U + +// Field: [1] EV1 +// +// Clears channel 1 interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_EV1 0x00000002U +#define SYSTIM_ICLR_EV1_M 0x00000002U +#define SYSTIM_ICLR_EV1_S 1U +#define SYSTIM_ICLR_EV1_CLR 0x00000002U +#define SYSTIM_ICLR_EV1_NOEFF 0x00000000U + +// Field: [0] EV0 +// +// Clears channel 0 interrupt. +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define SYSTIM_ICLR_EV0 0x00000001U +#define SYSTIM_ICLR_EV0_M 0x00000001U +#define SYSTIM_ICLR_EV0_S 0U +#define SYSTIM_ICLR_EV0_CLR 0x00000001U +#define SYSTIM_ICLR_EV0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_IMSET +// +//***************************************************************************** +// Field: [5] OVFL +// +// Sets Timer Overflow Event Interrupt Mask. +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_OVFL 0x00000020U +#define SYSTIM_IMSET_OVFL_M 0x00000020U +#define SYSTIM_IMSET_OVFL_S 5U +#define SYSTIM_IMSET_OVFL_SET 0x00000020U +#define SYSTIM_IMSET_OVFL_NOEFF 0x00000000U + +// Field: [4] EV4 +// +// Sets channel4 Event Interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_EV4 0x00000010U +#define SYSTIM_IMSET_EV4_M 0x00000010U +#define SYSTIM_IMSET_EV4_S 4U +#define SYSTIM_IMSET_EV4_SET 0x00000010U +#define SYSTIM_IMSET_EV4_NOEFF 0x00000000U + +// Field: [3] EV3 +// +// Sets channel3 Event Interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_EV3 0x00000008U +#define SYSTIM_IMSET_EV3_M 0x00000008U +#define SYSTIM_IMSET_EV3_S 3U +#define SYSTIM_IMSET_EV3_SET 0x00000008U +#define SYSTIM_IMSET_EV3_NOEFF 0x00000000U + +// Field: [2] EV2 +// +// Sets channel2 Event Interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_EV2 0x00000004U +#define SYSTIM_IMSET_EV2_M 0x00000004U +#define SYSTIM_IMSET_EV2_S 2U +#define SYSTIM_IMSET_EV2_SET 0x00000004U +#define SYSTIM_IMSET_EV2_NOEFF 0x00000000U + +// Field: [1] EV1 +// +// Sets channel1 Event Interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_EV1 0x00000002U +#define SYSTIM_IMSET_EV1_M 0x00000002U +#define SYSTIM_IMSET_EV1_S 1U +#define SYSTIM_IMSET_EV1_SET 0x00000002U +#define SYSTIM_IMSET_EV1_NOEFF 0x00000000U + +// Field: [0] EV0 +// +// Sets channel0 Event Interrupt mask +// ENUMs: +// SET Set interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMSET_EV0 0x00000001U +#define SYSTIM_IMSET_EV0_M 0x00000001U +#define SYSTIM_IMSET_EV0_S 0U +#define SYSTIM_IMSET_EV0_SET 0x00000001U +#define SYSTIM_IMSET_EV0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_IMCLR +// +//***************************************************************************** +// Field: [5] OVFL +// +// Clears Timer Overflow Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_OVFL 0x00000020U +#define SYSTIM_IMCLR_OVFL_M 0x00000020U +#define SYSTIM_IMCLR_OVFL_S 5U +#define SYSTIM_IMCLR_OVFL_CLR 0x00000020U +#define SYSTIM_IMCLR_OVFL_NOEFF 0x00000000U + +// Field: [4] EV4 +// +// Clears channel4 Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_EV4 0x00000010U +#define SYSTIM_IMCLR_EV4_M 0x00000010U +#define SYSTIM_IMCLR_EV4_S 4U +#define SYSTIM_IMCLR_EV4_CLR 0x00000010U +#define SYSTIM_IMCLR_EV4_NOEFF 0x00000000U + +// Field: [3] EV3 +// +// Clears channel3 Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_EV3 0x00000008U +#define SYSTIM_IMCLR_EV3_M 0x00000008U +#define SYSTIM_IMCLR_EV3_S 3U +#define SYSTIM_IMCLR_EV3_CLR 0x00000008U +#define SYSTIM_IMCLR_EV3_NOEFF 0x00000000U + +// Field: [2] EV2 +// +// Clears channel2 Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_EV2 0x00000004U +#define SYSTIM_IMCLR_EV2_M 0x00000004U +#define SYSTIM_IMCLR_EV2_S 2U +#define SYSTIM_IMCLR_EV2_CLR 0x00000004U +#define SYSTIM_IMCLR_EV2_NOEFF 0x00000000U + +// Field: [1] EV1 +// +// Clears channel1 Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_EV1 0x00000002U +#define SYSTIM_IMCLR_EV1_M 0x00000002U +#define SYSTIM_IMCLR_EV1_S 1U +#define SYSTIM_IMCLR_EV1_CLR 0x00000002U +#define SYSTIM_IMCLR_EV1_NOEFF 0x00000000U + +// Field: [0] EV0 +// +// Clears channel0 Event Interrupt Mask. +// ENUMs: +// CLR Clear interrupt mask +// NOEFF Writing 0 has no effect +#define SYSTIM_IMCLR_EV0 0x00000001U +#define SYSTIM_IMCLR_EV0_M 0x00000001U +#define SYSTIM_IMCLR_EV0_S 0U +#define SYSTIM_IMCLR_EV0_CLR 0x00000001U +#define SYSTIM_IMCLR_EV0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_EMU +// +//***************************************************************************** +// Field: [0] HALT +// +// Halt control. +// ENUMs: +// STOP Freeze option. The IP freezes functionality when +// the core halted input is asserted, and resumes +// when it is deasserted. The freeze can either be +// immediate or after the IP has reached a +// boundary from where it can resume without +// corruption. +// RUN Free run option. The IP ignores the state of the +// core halted input. +#define SYSTIM_EMU_HALT 0x00000001U +#define SYSTIM_EMU_HALT_M 0x00000001U +#define SYSTIM_EMU_HALT_S 0U +#define SYSTIM_EMU_HALT_STOP 0x00000001U +#define SYSTIM_EMU_HALT_RUN 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_TIME250N +// +//***************************************************************************** +// Field: [31:0] VAL +// +// 32-bit counter value [31:0]. This will provide a 250ns resolution and a +// range of 17.9m. +#define SYSTIM_TIME250N_VAL_W 32U +#define SYSTIM_TIME250N_VAL_M 0xFFFFFFFFU +#define SYSTIM_TIME250N_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_TIME1U +// +//***************************************************************************** +// Field: [31:0] VAL +// +// 32-bit counter value [33:2]. This will provide a resolution of 1us and a +// range of 1hr and 11m. +#define SYSTIM_TIME1U_VAL_W 32U +#define SYSTIM_TIME1U_VAL_M 0xFFFFFFFFU +#define SYSTIM_TIME1U_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_OUT +// +//***************************************************************************** +// Field: [4] OUT4 +// +// Output Value of channel 4. +// ENUMs: +// SET Event occured +// CLR Event did not occur. +#define SYSTIM_OUT_OUT4 0x00000010U +#define SYSTIM_OUT_OUT4_M 0x00000010U +#define SYSTIM_OUT_OUT4_S 4U +#define SYSTIM_OUT_OUT4_SET 0x00000010U +#define SYSTIM_OUT_OUT4_CLR 0x00000000U + +// Field: [3] OUT3 +// +// Output Value of channel 3. +// ENUMs: +// SET Event occured +// CLR Event did not occur. +#define SYSTIM_OUT_OUT3 0x00000008U +#define SYSTIM_OUT_OUT3_M 0x00000008U +#define SYSTIM_OUT_OUT3_S 3U +#define SYSTIM_OUT_OUT3_SET 0x00000008U +#define SYSTIM_OUT_OUT3_CLR 0x00000000U + +// Field: [2] OUT2 +// +// Output Value of channel 2. +// ENUMs: +// SET Event occured +// CLR Event did not occur. +#define SYSTIM_OUT_OUT2 0x00000004U +#define SYSTIM_OUT_OUT2_M 0x00000004U +#define SYSTIM_OUT_OUT2_S 2U +#define SYSTIM_OUT_OUT2_SET 0x00000004U +#define SYSTIM_OUT_OUT2_CLR 0x00000000U + +// Field: [1] OUT1 +// +// Output Value of channel 1. +// ENUMs: +// SET Event occured +// CLR Event did not occur. +#define SYSTIM_OUT_OUT1 0x00000002U +#define SYSTIM_OUT_OUT1_M 0x00000002U +#define SYSTIM_OUT_OUT1_S 1U +#define SYSTIM_OUT_OUT1_SET 0x00000002U +#define SYSTIM_OUT_OUT1_CLR 0x00000000U + +// Field: [0] OUT0 +// +// Output Value of channel 0. +// ENUMs: +// SET Event occured +// CLR Event did not occur. +#define SYSTIM_OUT_OUT0 0x00000001U +#define SYSTIM_OUT_OUT0_M 0x00000001U +#define SYSTIM_OUT_OUT0_S 0U +#define SYSTIM_OUT_OUT0_SET 0x00000001U +#define SYSTIM_OUT_OUT0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH0CFG +// +//***************************************************************************** +// Field: [4] RES +// +// This bit decides the RESOLUTION of the channel that will be used. +// ENUMs: +// NS channel Works in Timer's 250ns resolution +// US channel Works in Timer's 1us Resolution. +#define SYSTIM_CH0CFG_RES 0x00000010U +#define SYSTIM_CH0CFG_RES_M 0x00000010U +#define SYSTIM_CH0CFG_RES_S 4U +#define SYSTIM_CH0CFG_RES_NS 0x00000010U +#define SYSTIM_CH0CFG_RES_US 0x00000000U + +// Field: [3] REARM +// +// When Rearm is enabled the channel remains in continous capture mode. +// Otherwise it'll be in one shot capture mode. Rearm is only valid for capture +// mode. +// ENUMs: +// EN Re arm is enabled +// DIS Re Arm is disabled +#define SYSTIM_CH0CFG_REARM 0x00000008U +#define SYSTIM_CH0CFG_REARM_M 0x00000008U +#define SYSTIM_CH0CFG_REARM_S 3U +#define SYSTIM_CH0CFG_REARM_EN 0x00000008U +#define SYSTIM_CH0CFG_REARM_DIS 0x00000000U + +// Field: [2:1] INP +// +// Decides the channel input signal's mode. Setting the Value as 2'b11 selects +// the Rise Function. +// ENUMs: +// BOTH Capture on both Edge +// FALL Capture on Falling Edge +// RISE Capture on rising edge +#define SYSTIM_CH0CFG_INP_W 2U +#define SYSTIM_CH0CFG_INP_M 0x00000006U +#define SYSTIM_CH0CFG_INP_S 1U +#define SYSTIM_CH0CFG_INP_BOTH 0x00000004U +#define SYSTIM_CH0CFG_INP_FALL 0x00000002U +#define SYSTIM_CH0CFG_INP_RISE 0x00000000U + +// Field: [0] MODE +// +// Decides the channel mode. +// ENUMs: +// CAPT channel is in capture mode +// DIS channel is disabled +#define SYSTIM_CH0CFG_MODE 0x00000001U +#define SYSTIM_CH0CFG_MODE_M 0x00000001U +#define SYSTIM_CH0CFG_MODE_S 0U +#define SYSTIM_CH0CFG_MODE_CAPT 0x00000001U +#define SYSTIM_CH0CFG_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH1CFG +// +//***************************************************************************** +// Field: [3] REARM +// +// When Rearm is enabled the channel remains in continous capture mode. +// Otherwise it'll be in one shot capture mode. Rearm is only valid for capture +// mode. +// ENUMs: +// EN Re arm is enabled +// DIS Re Arm is disabled +#define SYSTIM_CH1CFG_REARM 0x00000008U +#define SYSTIM_CH1CFG_REARM_M 0x00000008U +#define SYSTIM_CH1CFG_REARM_S 3U +#define SYSTIM_CH1CFG_REARM_EN 0x00000008U +#define SYSTIM_CH1CFG_REARM_DIS 0x00000000U + +// Field: [2:1] INP +// +// Decides the channel input signal's mode. Setting the Value as 2'b11 selects +// the Rise Function +// ENUMs: +// BOTH Capture on both Edge +// FALL Capture on Falling Edge +// RISE Capture on rising edge +#define SYSTIM_CH1CFG_INP_W 2U +#define SYSTIM_CH1CFG_INP_M 0x00000006U +#define SYSTIM_CH1CFG_INP_S 1U +#define SYSTIM_CH1CFG_INP_BOTH 0x00000004U +#define SYSTIM_CH1CFG_INP_FALL 0x00000002U +#define SYSTIM_CH1CFG_INP_RISE 0x00000000U + +// Field: [0] MODE +// +// Decides the channel mode. +// ENUMs: +// CAPT channel is in capture mode +// DIS channel is disabled +#define SYSTIM_CH1CFG_MODE 0x00000001U +#define SYSTIM_CH1CFG_MODE_M 0x00000001U +#define SYSTIM_CH1CFG_MODE_S 0U +#define SYSTIM_CH1CFG_MODE_CAPT 0x00000001U +#define SYSTIM_CH1CFG_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH2CFG +// +//***************************************************************************** +// Field: [3] REARM +// +// When Rearm is enabled the channel remains in continous capture mode. +// Otherwise it'll be in one shot capture mode. Rearm is only valid for capture +// mode. +// ENUMs: +// EN Re arm is enabled +// DIS Re Arm is disabled +#define SYSTIM_CH2CFG_REARM 0x00000008U +#define SYSTIM_CH2CFG_REARM_M 0x00000008U +#define SYSTIM_CH2CFG_REARM_S 3U +#define SYSTIM_CH2CFG_REARM_EN 0x00000008U +#define SYSTIM_CH2CFG_REARM_DIS 0x00000000U + +// Field: [2:1] INP +// +// Decides the channel input signal's mode. Setting the Value as 2'b11 selects +// the Rise Function +// ENUMs: +// BOTH Capture on both Edge +// FALL Capture on Falling Edge +// RISE Capture on rising edge +#define SYSTIM_CH2CFG_INP_W 2U +#define SYSTIM_CH2CFG_INP_M 0x00000006U +#define SYSTIM_CH2CFG_INP_S 1U +#define SYSTIM_CH2CFG_INP_BOTH 0x00000004U +#define SYSTIM_CH2CFG_INP_FALL 0x00000002U +#define SYSTIM_CH2CFG_INP_RISE 0x00000000U + +// Field: [0] MODE +// +// Decides the channel mode. +// ENUMs: +// CAPT channel is in capture mode +// DIS channel is disabled +#define SYSTIM_CH2CFG_MODE 0x00000001U +#define SYSTIM_CH2CFG_MODE_M 0x00000001U +#define SYSTIM_CH2CFG_MODE_S 0U +#define SYSTIM_CH2CFG_MODE_CAPT 0x00000001U +#define SYSTIM_CH2CFG_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH3CFG +// +//***************************************************************************** +// Field: [3] REARM +// +// When Rearm is enabled the channel remains in continous capture mode. +// Otherwise it'll be in one shot capture mode. Rearm is only valid for capture +// mode. +// ENUMs: +// EN Re arm is enabled +// DIS Re Arm is disabled +#define SYSTIM_CH3CFG_REARM 0x00000008U +#define SYSTIM_CH3CFG_REARM_M 0x00000008U +#define SYSTIM_CH3CFG_REARM_S 3U +#define SYSTIM_CH3CFG_REARM_EN 0x00000008U +#define SYSTIM_CH3CFG_REARM_DIS 0x00000000U + +// Field: [2:1] INP +// +// Decides the channel input signal's mode. Setting the Value as 2'b11 selects +// the Rise Function +// ENUMs: +// BOTH Capture on both Edge +// FALL Capture on Falling Edge +// RISE Capture on rising edge +#define SYSTIM_CH3CFG_INP_W 2U +#define SYSTIM_CH3CFG_INP_M 0x00000006U +#define SYSTIM_CH3CFG_INP_S 1U +#define SYSTIM_CH3CFG_INP_BOTH 0x00000004U +#define SYSTIM_CH3CFG_INP_FALL 0x00000002U +#define SYSTIM_CH3CFG_INP_RISE 0x00000000U + +// Field: [0] MODE +// +// Decides the channel mode. +// ENUMs: +// CAPT channel is in capture mode +// DIS channel is disabled +#define SYSTIM_CH3CFG_MODE 0x00000001U +#define SYSTIM_CH3CFG_MODE_M 0x00000001U +#define SYSTIM_CH3CFG_MODE_S 0U +#define SYSTIM_CH3CFG_MODE_CAPT 0x00000001U +#define SYSTIM_CH3CFG_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH4CFG +// +//***************************************************************************** +// Field: [3] REARM +// +// When Rearm is enabled the channel remains in continous capture mode. +// Otherwise it'll be in one shot capture mode. Rearm is only valid for capture +// mode. +// ENUMs: +// EN Re arm is enabled +// DIS Re Arm is disabled +#define SYSTIM_CH4CFG_REARM 0x00000008U +#define SYSTIM_CH4CFG_REARM_M 0x00000008U +#define SYSTIM_CH4CFG_REARM_S 3U +#define SYSTIM_CH4CFG_REARM_EN 0x00000008U +#define SYSTIM_CH4CFG_REARM_DIS 0x00000000U + +// Field: [2:1] INP +// +// Decides the channel input signal's mode. Setting the Value as 2'b11 selects +// the Rise Function +// ENUMs: +// BOTH Capture on both Edge +// FALL Capture on Falling Edge +// RISE Capture on rising edge +#define SYSTIM_CH4CFG_INP_W 2U +#define SYSTIM_CH4CFG_INP_M 0x00000006U +#define SYSTIM_CH4CFG_INP_S 1U +#define SYSTIM_CH4CFG_INP_BOTH 0x00000004U +#define SYSTIM_CH4CFG_INP_FALL 0x00000002U +#define SYSTIM_CH4CFG_INP_RISE 0x00000000U + +// Field: [0] MODE +// +// Decides the channel mode. +// ENUMs: +// CAPT channel is in capture mode +// DIS channel is disabled +#define SYSTIM_CH4CFG_MODE 0x00000001U +#define SYSTIM_CH4CFG_MODE_M 0x00000001U +#define SYSTIM_CH4CFG_MODE_S 0U +#define SYSTIM_CH4CFG_MODE_CAPT 0x00000001U +#define SYSTIM_CH4CFG_MODE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH0CC +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH0CC_VAL_W 32U +#define SYSTIM_CH0CC_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH0CC_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH1CC +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH1CC_VAL_W 32U +#define SYSTIM_CH1CC_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH1CC_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH2CC +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH2CC_VAL_W 32U +#define SYSTIM_CH2CC_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH2CC_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH3CC +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH3CC_VAL_W 32U +#define SYSTIM_CH3CC_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH3CC_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH4CC +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH4CC_VAL_W 32U +#define SYSTIM_CH4CC_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH4CC_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_TIMEBIT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// The corresponding bit will have value '1' rest should be '0'. If more than +// one bit is asserted, output is "or" of all the bits. +// ENUMs: +// BIT17 Bit17 is forwarded to the event fabric. +// BIT16 Bit16 is forwarded to the event fabric. +// BIT15 Bit15 is forwarded to the event fabric. +// BIT14 Bit14 is forwarded to the event fabric. +// BIT13 Bit13 is forwarded to the event fabric. +// BIT12 Bit12 is forwarded to the event fabric. +// BIT11 Bit11 is forwarded to the event fabric. +// BIT10 Bit10 is forwarded to the event fabric. +// BIT9 Bit9 is forwarded to the event fabric. +// BIT8 Bit8 is forwarded to the event fabric. +// BIT7 Bit7 is forwarded to the event fabric. +// BIT6 Bit6 is forwarded to the event fabric. +// BIT5 Bit5 is forwarded to the event fabric. +// BIT4 Bit4 is forwarded to the event fabric. +// BIT3 Bit3 is forwarded to the event fabric. +// BIT2 Bit2 is forwarded to the event fabric. +// NOBIT No bit is forwarded to the event fabric. +#define SYSTIM_TIMEBIT_VAL_W 16U +#define SYSTIM_TIMEBIT_VAL_M 0x0000FFFFU +#define SYSTIM_TIMEBIT_VAL_S 0U +#define SYSTIM_TIMEBIT_VAL_BIT17 0x00008000U +#define SYSTIM_TIMEBIT_VAL_BIT16 0x00004000U +#define SYSTIM_TIMEBIT_VAL_BIT15 0x00002000U +#define SYSTIM_TIMEBIT_VAL_BIT14 0x00001000U +#define SYSTIM_TIMEBIT_VAL_BIT13 0x00000800U +#define SYSTIM_TIMEBIT_VAL_BIT12 0x00000400U +#define SYSTIM_TIMEBIT_VAL_BIT11 0x00000200U +#define SYSTIM_TIMEBIT_VAL_BIT10 0x00000100U +#define SYSTIM_TIMEBIT_VAL_BIT9 0x00000080U +#define SYSTIM_TIMEBIT_VAL_BIT8 0x00000040U +#define SYSTIM_TIMEBIT_VAL_BIT7 0x00000020U +#define SYSTIM_TIMEBIT_VAL_BIT6 0x00000010U +#define SYSTIM_TIMEBIT_VAL_BIT5 0x00000008U +#define SYSTIM_TIMEBIT_VAL_BIT4 0x00000004U +#define SYSTIM_TIMEBIT_VAL_BIT3 0x00000002U +#define SYSTIM_TIMEBIT_VAL_BIT2 0x00000001U +#define SYSTIM_TIMEBIT_VAL_NOBIT 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_STATUS +// +//***************************************************************************** +// Field: [4] SYNCUP +// +// This bit indicates sync status of Systimer with RTC. The bitfield has a +// reset value of '1', which gets cleared to '0' after the Systimer +// synchronizes with RTC on the first LFTICK edge. A write to this bit +// resynchronizes the Systimer with RTC on the next LFTICK edge. A read value +// of '1' indicates the synchronization is ongoing and a read of '0' indicates +// the synchronization is done. +#define SYSTIM_STATUS_SYNCUP 0x00000010U +#define SYSTIM_STATUS_SYNCUP_M 0x00000010U +#define SYSTIM_STATUS_SYNCUP_S 4U + +// Field: [0] VAL +// +// This bit indicates if the system time is initialized and running. +// ENUMs: +// RUN system timer is running +// STOP system timer is not running. +#define SYSTIM_STATUS_VAL 0x00000001U +#define SYSTIM_STATUS_VAL_M 0x00000001U +#define SYSTIM_STATUS_VAL_S 0U +#define SYSTIM_STATUS_VAL_RUN 0x00000001U +#define SYSTIM_STATUS_VAL_STOP 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_ARMSET +// +//***************************************************************************** +// Field: [4] CH4 +// +// Arming channel 4 for either compare or capture operation. +// ENUMs: +// SET if channel 4 is in CAPTURE state then no effect on +// the channel else it can set channel in COMPARE +// mode using existing CH4CC.VAL value. +// NOEFF No effect on the channel +#define SYSTIM_ARMSET_CH4 0x00000010U +#define SYSTIM_ARMSET_CH4_M 0x00000010U +#define SYSTIM_ARMSET_CH4_S 4U +#define SYSTIM_ARMSET_CH4_SET 0x00000010U +#define SYSTIM_ARMSET_CH4_NOEFF 0x00000000U + +// Field: [3] CH3 +// +// Arming channel 3 for either compare or capture operation. +// ENUMs: +// SET if channel 3 is in CAPTURE state then no effect on +// the channel else it can set channel in COMPARE +// mode using existing CH3CC.VAL value +// NOEFF No effect on the channel +#define SYSTIM_ARMSET_CH3 0x00000008U +#define SYSTIM_ARMSET_CH3_M 0x00000008U +#define SYSTIM_ARMSET_CH3_S 3U +#define SYSTIM_ARMSET_CH3_SET 0x00000008U +#define SYSTIM_ARMSET_CH3_NOEFF 0x00000000U + +// Field: [2] CH2 +// +// Arming channel 2 for either compare or capture operation. +// ENUMs: +// SET if channel 2 is in CAPTURE state then no effect on +// the channel else it can set channel in COMPARE +// mode using existing CH2CC.VAL value +// NOEFF No effect on the channel +#define SYSTIM_ARMSET_CH2 0x00000004U +#define SYSTIM_ARMSET_CH2_M 0x00000004U +#define SYSTIM_ARMSET_CH2_S 2U +#define SYSTIM_ARMSET_CH2_SET 0x00000004U +#define SYSTIM_ARMSET_CH2_NOEFF 0x00000000U + +// Field: [1] CH1 +// +// Arming channel 1 for either compare or capture operation. +// ENUMs: +// SET if channel 1 is in CAPTURE state then no effect on +// the channel else it can Set channel in COMPARE +// mode using existing CH1CC.VAL value +// NOEFF No effect on the channel +#define SYSTIM_ARMSET_CH1 0x00000002U +#define SYSTIM_ARMSET_CH1_M 0x00000002U +#define SYSTIM_ARMSET_CH1_S 1U +#define SYSTIM_ARMSET_CH1_SET 0x00000002U +#define SYSTIM_ARMSET_CH1_NOEFF 0x00000000U + +// Field: [0] CH0 +// +// Arming channel 0 for either compare or capture operation. +// ENUMs: +// SET if channel 0 is in CAPTURE state then no effect on +// the channel else it can set channel in COMPARE +// mode using existing CH0CC.VAL value +// NOEFF No effect on the channel +#define SYSTIM_ARMSET_CH0 0x00000001U +#define SYSTIM_ARMSET_CH0_M 0x00000001U +#define SYSTIM_ARMSET_CH0_S 0U +#define SYSTIM_ARMSET_CH0_SET 0x00000001U +#define SYSTIM_ARMSET_CH0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_ARMCLR +// +//***************************************************************************** +// Field: [4] CH4 +// +// Disarming channel 4 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare/capture event happens in +// the same cycle +// NOEFF No effect on the channel +#define SYSTIM_ARMCLR_CH4 0x00000010U +#define SYSTIM_ARMCLR_CH4_M 0x00000010U +#define SYSTIM_ARMCLR_CH4_S 4U +#define SYSTIM_ARMCLR_CH4_CLR 0x00000010U +#define SYSTIM_ARMCLR_CH4_NOEFF 0x00000000U + +// Field: [3] CH3 +// +// Disarming channel 3 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare/capture event happens in +// the same cycle +// NOEFF No effect on the channel +#define SYSTIM_ARMCLR_CH3 0x00000008U +#define SYSTIM_ARMCLR_CH3_M 0x00000008U +#define SYSTIM_ARMCLR_CH3_S 3U +#define SYSTIM_ARMCLR_CH3_CLR 0x00000008U +#define SYSTIM_ARMCLR_CH3_NOEFF 0x00000000U + +// Field: [2] CH2 +// +// Disarming channel 2 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare/capture event happens in +// the same cycle +// NOEFF No effect on the channel +#define SYSTIM_ARMCLR_CH2 0x00000004U +#define SYSTIM_ARMCLR_CH2_M 0x00000004U +#define SYSTIM_ARMCLR_CH2_S 2U +#define SYSTIM_ARMCLR_CH2_CLR 0x00000004U +#define SYSTIM_ARMCLR_CH2_NOEFF 0x00000000U + +// Field: [1] CH1 +// +// Disarming channel 1 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare/capture event happens in +// the same cycle +// NOEFF No effect on the channel +#define SYSTIM_ARMCLR_CH1 0x00000002U +#define SYSTIM_ARMCLR_CH1_M 0x00000002U +#define SYSTIM_ARMCLR_CH1_S 1U +#define SYSTIM_ARMCLR_CH1_CLR 0x00000002U +#define SYSTIM_ARMCLR_CH1_NOEFF 0x00000000U + +// Field: [0] CH0 +// +// Disarming channel 0 +// ENUMs: +// CLR Set channel in UNARMED state without triggering +// event unless a compare/capture event happens in +// the same cycle +// NOEFF No effect on the channel +#define SYSTIM_ARMCLR_CH0 0x00000001U +#define SYSTIM_ARMCLR_CH0_M 0x00000001U +#define SYSTIM_ARMCLR_CH0_S 0U +#define SYSTIM_ARMCLR_CH0_CLR 0x00000001U +#define SYSTIM_ARMCLR_CH0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH0CCSR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH0CCSR_VAL_W 32U +#define SYSTIM_CH0CCSR_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH0CCSR_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH1CCSR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH1CCSR_VAL_W 32U +#define SYSTIM_CH1CCSR_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH1CCSR_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH2CCSR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH2CCSR_VAL_W 32U +#define SYSTIM_CH2CCSR_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH2CCSR_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH3CCSR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH3CCSR_VAL_W 32U +#define SYSTIM_CH3CCSR_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH3CCSR_VAL_S 0U + +//***************************************************************************** +// +// Register: SYSTIM_O_CH4CCSR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value +#define SYSTIM_CH4CCSR_VAL_W 32U +#define SYSTIM_CH4CCSR_VAL_M 0xFFFFFFFFU +#define SYSTIM_CH4CCSR_VAL_S 0U + + +#endif // __SYSTIM__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h new file mode 100644 index 00000000..c6849804 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h @@ -0,0 +1,94 @@ +/****************************************************************************** +* Filename: hw_types.h +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +#endif // __HW_TYPES_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_uart.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_uart.h new file mode 100644 index 00000000..711b1299 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_uart.h @@ -0,0 +1,1137 @@ +/****************************************************************************** +* Filename: hw_uart_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000U + +// Status +#define UART_O_RSR_ECR 0x00000004U + +// Flag +#define UART_O_FR 0x00000018U + +// IrDA Low-Power Counter Register +#define UART_O_UARTILPR 0x00000020U + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024U + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028U + +// Line Control +#define UART_O_LCRH 0x0000002CU + +// Control +#define UART_O_CTL 0x00000030U + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034U + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038U + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003CU + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040U + +// Interrupt Clear +#define UART_O_ICR 0x00000044U + +// DMA Control +#define UART_O_DMACTL 0x00000048U + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800U +#define UART_DR_OE_M 0x00000800U +#define UART_DR_OE_S 11U + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400U +#define UART_DR_BE_M 0x00000400U +#define UART_DR_BE_S 10U + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_PE 0x00000200U +#define UART_DR_PE_M 0x00000200U +#define UART_DR_PE_S 9U + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_FE 0x00000100U +#define UART_DR_FE_M 0x00000100U +#define UART_DR_FE_S 8U + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8U +#define UART_DR_DATA_M 0x000000FFU +#define UART_DR_DATA_S 0U + +//***************************************************************************** +// +// Register: UART_O_RSR_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +// ENUMs: +// CLEAR_ERROR_1 Clears error flag if error is set. Write value is +// not important. +// ERROR_NOTSET Error flag is not set +#define UART_RSR_ECR_OE 0x00000008U +#define UART_RSR_ECR_OE_M 0x00000008U +#define UART_RSR_ECR_OE_S 3U +#define UART_RSR_ECR_OE_CLEAR_ERROR_1 0x00000008U +#define UART_RSR_ECR_OE_ERROR_NOTSET 0x00000000U + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +// ENUMs: +// CLEAR_ERROR_1 Clears error flag if error is set. Write value is +// not important. +// ERROR_NOTSET Error flag is not set +#define UART_RSR_ECR_BE 0x00000004U +#define UART_RSR_ECR_BE_M 0x00000004U +#define UART_RSR_ECR_BE_S 2U +#define UART_RSR_ECR_BE_CLEAR_ERROR_1 0x00000004U +#define UART_RSR_ECR_BE_ERROR_NOTSET 0x00000000U + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// ENUMs: +// CLEAR_ERROR_1 Clears error flag if error is set. Write value is +// not important. +// ERROR_NOTSET Error flag is not set +#define UART_RSR_ECR_PE 0x00000002U +#define UART_RSR_ECR_PE_M 0x00000002U +#define UART_RSR_ECR_PE_S 1U +#define UART_RSR_ECR_PE_CLEAR_ERROR_1 0x00000002U +#define UART_RSR_ECR_PE_ERROR_NOTSET 0x00000000U + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// ENUMs: +// CLEAR_ERROR_1 Clears error flag if error is set. Write value is +// not important. +// ERROR_NOTSET Error flag is not set +#define UART_RSR_ECR_FE 0x00000001U +#define UART_RSR_ECR_FE_M 0x00000001U +#define UART_RSR_ECR_FE_S 0U +#define UART_RSR_ECR_FE_CLEAR_ERROR_1 0x00000001U +#define UART_RSR_ECR_FE_ERROR_NOTSET 0x00000000U + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080U +#define UART_FR_TXFE_M 0x00000080U +#define UART_FR_TXFE_S 7U + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040U +#define UART_FR_RXFF_M 0x00000040U +#define UART_FR_RXFF_S 6U + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020U +#define UART_FR_TXFF_M 0x00000020U +#define UART_FR_TXFF_S 5U + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010U +#define UART_FR_RXFE_M 0x00000010U +#define UART_FR_RXFE_S 4U + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008U +#define UART_FR_BUSY_M 0x00000008U +#define UART_FR_BUSY_S 3U + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001U +#define UART_FR_CTS_M 0x00000001U +#define UART_FR_CTS_S 0U + +//***************************************************************************** +// +// Register: UART_O_UARTILPR +// +//***************************************************************************** +// Field: [7:0] ILPDVSR +// +// 8 bit low-power divisor value. In low-power IrDA mode the UART rejects +// random noise on the received serial data +// input by ignoring SIRIN pulses that are less than 3 periods of IrLPBaud16. +#define UART_UARTILPR_ILPDVSR_W 8U +#define UART_UARTILPR_ILPDVSR_M 0x000000FFU +#define UART_UARTILPR_ILPDVSR_S 0U + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// Refer to Section 19.1.5 for an example calculation. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16U +#define UART_IBRD_DIVINT_M 0x0000FFFFU +#define UART_IBRD_DIVINT_S 0U + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// Refer to Section 19.1.5 for an example calculation. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6U +#define UART_FBRD_DIVFRAC_M 0x0000003FU +#define UART_FBRD_DIVFRAC_S 0U + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080U +#define UART_LCRH_SPS_M 0x00000080U +#define UART_LCRH_SPS_S 7U + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// BITL8 Word Length 8 bits +// BITL7 Word Length 7 bits +// BITL6 Word Length 6 bits +// BITL5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2U +#define UART_LCRH_WLEN_M 0x00000060U +#define UART_LCRH_WLEN_S 5U +#define UART_LCRH_WLEN_BITL8 0x00000060U +#define UART_LCRH_WLEN_BITL7 0x00000040U +#define UART_LCRH_WLEN_BITL6 0x00000020U +#define UART_LCRH_WLEN_BITL5 0x00000000U + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010U +#define UART_LCRH_FEN_M 0x00000010U +#define UART_LCRH_FEN_S 4U +#define UART_LCRH_FEN_EN 0x00000010U +#define UART_LCRH_FEN_DIS 0x00000000U + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008U +#define UART_LCRH_STP2_M 0x00000008U +#define UART_LCRH_STP2_S 3U + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004U +#define UART_LCRH_EPS_M 0x00000004U +#define UART_LCRH_EPS_S 2U +#define UART_LCRH_EPS_EVEN 0x00000004U +#define UART_LCRH_EPS_ODD 0x00000000U + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002U +#define UART_LCRH_PEN_M 0x00000002U +#define UART_LCRH_PEN_S 1U +#define UART_LCRH_PEN_EN 0x00000002U +#define UART_LCRH_PEN_DIS 0x00000000U + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001U +#define UART_LCRH_BRK_M 0x00000001U +#define UART_LCRH_BRK_S 0U + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000U +#define UART_CTL_CTSEN_M 0x00008000U +#define UART_CTL_CTSEN_S 15U +#define UART_CTL_CTSEN_EN 0x00008000U +#define UART_CTL_CTSEN_DIS 0x00000000U + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000U +#define UART_CTL_RTSEN_M 0x00004000U +#define UART_CTL_RTSEN_S 14U +#define UART_CTL_RTSEN_EN 0x00004000U +#define UART_CTL_RTSEN_DIS 0x00000000U + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800U +#define UART_CTL_RTS_M 0x00000800U +#define UART_CTL_RTS_S 11U + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200U +#define UART_CTL_RXE_M 0x00000200U +#define UART_CTL_RXE_S 9U +#define UART_CTL_RXE_EN 0x00000200U +#define UART_CTL_RXE_DIS 0x00000000U + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100U +#define UART_CTL_TXE_M 0x00000100U +#define UART_CTL_TXE_S 8U +#define UART_CTL_TXE_EN 0x00000100U +#define UART_CTL_TXE_DIS 0x00000000U + +// Field: [7] LBE +// +// UART Loop Back Enable +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080U +#define UART_CTL_LBE_M 0x00000080U +#define UART_CTL_LBE_S 7U +#define UART_CTL_LBE_EN 0x00000080U +#define UART_CTL_LBE_DIS 0x00000000U + +// Field: [6] FCEN +// +// UART FIFO Concatenation Enable +// Enabling the FIFO concatenation in TX mode resulting in 16 TX buffers. +// ENUMs: +// EN UART FIFO Concatenation enabled +// DIS UART FIFO Concatenation disabled +#define UART_CTL_FCEN 0x00000040U +#define UART_CTL_FCEN_M 0x00000040U +#define UART_CTL_FCEN_S 6U +#define UART_CTL_FCEN_EN 0x00000040U +#define UART_CTL_FCEN_DIS 0x00000000U + +// Field: [2] SIRLP +// +// SIR low power IrDA mode +// This bit selects the IrDA encoding mode +// ENUMs: +// EN Low-level bits are transmitted with a pulse width +// of 3 times the period of IrLPBaud16(which has a +// frequency of (UARTCLK +// frequency)/UARTILP.ILPDVSR), regardless of the +// selected bit rate. +// In low-power IrDA mode +// the UART rejects random noise on the received +// serial data +// input by ignoring SIRIN +// pulses that are less than 3 periods of +// IrLPBaud16. +// DIS Low-level bits are transmitted as active high with +// a 3/16th period width, +#define UART_CTL_SIRLP 0x00000004U +#define UART_CTL_SIRLP_M 0x00000004U +#define UART_CTL_SIRLP_S 2U +#define UART_CTL_SIRLP_EN 0x00000004U +#define UART_CTL_SIRLP_DIS 0x00000000U + +// Field: [1] SIREN +// +// SIR Enable +// This bit has no effect if UARTEN bit disables the UART. +// ENUMs: +// EN IrDA SIR ENDEC is enabled. Data is transmitted and +// received via nSIROUT and SIRIN. +// DIS IrDA SIR ENDEC is disabled +#define UART_CTL_SIREN 0x00000002U +#define UART_CTL_SIREN_M 0x00000002U +#define UART_CTL_SIREN_S 1U +#define UART_CTL_SIREN_EN 0x00000002U +#define UART_CTL_SIREN_DIS 0x00000000U + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001U +#define UART_CTL_UARTEN_M 0x00000001U +#define UART_CTL_UARTEN_S 0U +#define UART_CTL_UARTEN_EN 0x00000001U +#define UART_CTL_UARTEN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// THREEQU Receive FIFO becomes >= 3/4 full +// HALF Receive FIFO becomes >= 1/2 full +// QUARTER Receive FIFO becomes >= 1/4 full +#define UART_IFLS_RXSEL_W 3U +#define UART_IFLS_RXSEL_M 0x00000038U +#define UART_IFLS_RXSEL_S 3U +#define UART_IFLS_RXSEL_THREEQU 0x00000018U +#define UART_IFLS_RXSEL_HALF 0x00000010U +#define UART_IFLS_RXSEL_QUARTER 0x00000008U + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// THREEQU Transmit FIFO becomes <= 3/4 full +// HALF Transmit FIFO becomes <= 1/2 full +// QUARTER Transmit FIFO becomes <= 1/4 full +#define UART_IFLS_TXSEL_W 3U +#define UART_IFLS_TXSEL_M 0x00000007U +#define UART_IFLS_TXSEL_S 0U +#define UART_IFLS_TXSEL_THREEQU 0x00000003U +#define UART_IFLS_TXSEL_HALF 0x00000002U +#define UART_IFLS_TXSEL_QUARTER 0x00000001U + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [13] RXDMADONE +// +// RX DMA done interrupt mask. A read returns the current mask for UART's +// RXDMADONE interrupt. On a write of 1, the mask of the RXDMADONE interrupt is +// set which means the interrupt state will be reflected in MIS.RXDMADONE. A +// write of 0 clears the mask which means MIS.RXDMADONE will not reflect the +// interrupt. +#define UART_IMSC_RXDMADONE 0x00002000U +#define UART_IMSC_RXDMADONE_M 0x00002000U +#define UART_IMSC_RXDMADONE_S 13U + +// Field: [12] TXDMADONE +// +// TX DMA done interrupt mask. A read returns the current mask for UART's +// TXDMADONE interrupt. On a write of 1, the mask of the TXDMADONE interrupt is +// set which means the interrupt state will be reflected in MIS.TXDMADONE. A +// write of 0 clears the mask which means MIS.TXDMADONE will not reflect the +// interrupt. +#define UART_IMSC_TXDMADONE 0x00001000U +#define UART_IMSC_TXDMADONE_M 0x00001000U +#define UART_IMSC_TXDMADONE_S 12U + +// Field: [11] EOT +// +// End of Transmission interrupt mask. A read returns the current mask for +// UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set +// which means the interrupt state will be reflected in MIS.EOT. A write of 0 +// clears the mask which means MIS.EOT will not reflect the interrupt. +#define UART_IMSC_EOT 0x00000800U +#define UART_IMSC_EOT_M 0x00000800U +#define UART_IMSC_EOT_S 11U + +// Field: [10] OE +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OE. A write of 0 clears the mask which means MIS.OE will not reflect the +// interrupt. +#define UART_IMSC_OE 0x00000400U +#define UART_IMSC_OE_M 0x00000400U +#define UART_IMSC_OE_S 10U + +// Field: [9] BE +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BE. A write of +// 0 clears the mask which means MIS.BE will not reflect the interrupt. +#define UART_IMSC_BE 0x00000200U +#define UART_IMSC_BE_M 0x00000200U +#define UART_IMSC_BE_S 9U + +// Field: [8] PE +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PE. A write of 0 clears the mask which means MIS.PE will not reflect the +// interrupt. +#define UART_IMSC_PE 0x00000100U +#define UART_IMSC_PE_M 0x00000100U +#define UART_IMSC_PE_S 8U + +// Field: [7] FE +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FE. A write of 0 clears the mask which means MIS.FE will not reflect the +// interrupt. +#define UART_IMSC_FE 0x00000080U +#define UART_IMSC_FE_M 0x00000080U +#define UART_IMSC_FE_S 7U + +// Field: [6] RT +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RT. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RT cannot be set unless the mask +// is set (RT = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RT and RIS.RT. +#define UART_IMSC_RT 0x00000040U +#define UART_IMSC_RT_M 0x00000040U +#define UART_IMSC_RT_S 6U + +// Field: [5] TX +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TX. A write of 0 +// clears the mask which means MIS.TX will not reflect the interrupt. +#define UART_IMSC_TX 0x00000020U +#define UART_IMSC_TX_M 0x00000020U +#define UART_IMSC_TX_S 5U + +// Field: [4] RX +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RX. A write of 0 +// clears the mask which means MIS.RX will not reflect the interrupt. +#define UART_IMSC_RX 0x00000010U +#define UART_IMSC_RX_M 0x00000010U +#define UART_IMSC_RX_S 4U + +// Field: [1] CTSM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSM. A write of 0 clears the mask which means MIS.CTSM will not reflect +// the interrupt. +#define UART_IMSC_CTSM 0x00000002U +#define UART_IMSC_CTSM_M 0x00000002U +#define UART_IMSC_CTSM_S 1U + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [13] RXDMADONE +// +// RX DMA done interrupt status: +// This field returns the raw interrupt state of UART's RX DMA done interrupt. +// RX DMA done flag is set when you recieve RX DMA done status from dma module. +#define UART_RIS_RXDMADONE 0x00002000U +#define UART_RIS_RXDMADONE_M 0x00002000U +#define UART_RIS_RXDMADONE_S 13U + +// Field: [12] TXDMADONE +// +// TX DMA done interrupt status: +// This field returns the raw interrupt state of UART's TX DMA done interrupt. +// TX DMA done flag is set when you recieve TX DMA done status from dma module. +#define UART_RIS_TXDMADONE 0x00001000U +#define UART_RIS_TXDMADONE_M 0x00001000U +#define UART_RIS_TXDMADONE_S 12U + +// Field: [11] EOT +// +// End of Transmission interrupt status: +// This field returns the raw interrupt state of UART's end of transmission +// interrupt. End of transmission flag is set when all the Transmit data in the +// FIFO and on the TX Line is tranmitted. +#define UART_RIS_EOT 0x00000800U +#define UART_RIS_EOT_M 0x00000800U +#define UART_RIS_EOT_S 11U + +// Field: [10] OE +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OE 0x00000400U +#define UART_RIS_OE_M 0x00000400U +#define UART_RIS_OE_S 10U + +// Field: [9] BE +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BE 0x00000200U +#define UART_RIS_BE_M 0x00000200U +#define UART_RIS_BE_S 9U + +// Field: [8] PE +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PE 0x00000100U +#define UART_RIS_PE_M 0x00000100U +#define UART_RIS_PE_S 8U + +// Field: [7] FE +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FE 0x00000080U +#define UART_RIS_FE_M 0x00000080U +#define UART_RIS_FE_S 7U + +// Field: [6] RT +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RT. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RT = 1). This is because the mask acts as an enable for power saving. +// That is, the same status can be read from MIS.RT and RT. +#define UART_RIS_RT 0x00000040U +#define UART_RIS_RT_M 0x00000040U +#define UART_RIS_RT_S 6U + +// Field: [5] TX +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TX. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TX. +#define UART_RIS_TX 0x00000020U +#define UART_RIS_TX_M 0x00000020U +#define UART_RIS_TX_S 5U + +// Field: [4] RX +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RX. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RX. +#define UART_RIS_RX 0x00000010U +#define UART_RIS_RX_M 0x00000010U +#define UART_RIS_RX_S 4U + +// Field: [1] CTSM +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSM 0x00000002U +#define UART_RIS_CTSM_M 0x00000002U +#define UART_RIS_CTSM_S 1U + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [13] RXDMADONE +// +// RX DMA done interrupt status: +// This field returns the masked interrupt state of the RX DMA done interrupt +// which is the bitiwse AND product of raw interrupt state RIS.RXDMADONE and +// the mask setting IMSC.RXDMADONE. +#define UART_MIS_RXDMADONE 0x00002000U +#define UART_MIS_RXDMADONE_M 0x00002000U +#define UART_MIS_RXDMADONE_S 13U + +// Field: [12] TXDMADONE +// +// TX DMA done interrupt status: +// This field returns the masked interrupt state of the TX DMA done interrupt +// which is the bitwise AND product of raw interrupt state RIS.TXDMADONE and +// the mask setting IMSC.TXDMADONE. +#define UART_MIS_TXDMADONE 0x00001000U +#define UART_MIS_TXDMADONE_M 0x00001000U +#define UART_MIS_TXDMADONE_S 12U + +// Field: [11] EOT +// +// End of Transmission interrupt status: +// This field returns the masked interrupt state of the End of transmission +// interrupt which is the bitwise AND product of raw interrupt state RIS.EOT +// and the mask setting IMSC.EOT. +#define UART_MIS_EOT 0x00000800U +#define UART_MIS_EOT_M 0x00000800U +#define UART_MIS_EOT_S 11U + +// Field: [10] OE +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the bitwise AND product of raw interrupt state RIS.OE and the mask +// setting IMSC.OE. +#define UART_MIS_OE 0x00000400U +#define UART_MIS_OE_M 0x00000400U +#define UART_MIS_OE_S 10U + +// Field: [9] BE +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the bitiwse AND product of raw interrupt state RIS.BE and the mask +// setting IMSC.BE. +#define UART_MIS_BE 0x00000200U +#define UART_MIS_BE_M 0x00000200U +#define UART_MIS_BE_S 9U + +// Field: [8] PE +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the bitiwise AND product of raw interrupt state RIS.PE and the mask +// setting IMSC.PE. +#define UART_MIS_PE 0x00000100U +#define UART_MIS_PE_M 0x00000100U +#define UART_MIS_PE_S 8U + +// Field: [7] FE +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the bitiwse AND product of raw +// interrupt state RIS.FE and the mask setting IMSC.FE. +#define UART_MIS_FE 0x00000080U +#define UART_MIS_FE_M 0x00000080U +#define UART_MIS_FE_S 7U + +// Field: [6] RT +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RT = 1). This is because the mask acts as an enable for power saving. +// That is, the same status can be read from MIS.RT and RIS.RT. +#define UART_MIS_RT 0x00000040U +#define UART_MIS_RT_M 0x00000040U +#define UART_MIS_RT_S 6U + +// Field: [5] TX +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the bitiwse AND product of raw interrupt state RIS.TX and the mask +// setting IMSC.TX. +#define UART_MIS_TX 0x00000020U +#define UART_MIS_TX_M 0x00000020U +#define UART_MIS_TX_S 5U + +// Field: [4] RX +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the bitwise AND product of raw interrupt state RIS.RX and the mask +// setting IMSC.RX. +#define UART_MIS_RX 0x00000010U +#define UART_MIS_RX_M 0x00000010U +#define UART_MIS_RX_S 4U + +// Field: [1] CTSM +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the bitwise AND product of raw interrupt state RIS.CTS and the mask +// setting IMSC.CTS. +#define UART_MIS_CTSM 0x00000002U +#define UART_MIS_CTSM_M 0x00000002U +#define UART_MIS_CTSM_S 1U + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [13] RXDMADONE +// +// RX DMA Done interrupt clear: +// Writing 1 to this field clears the RX DMA done interrupt (RIS.RXDMADONE). +// Writing 0 has no effect. +#define UART_ICR_RXDMADONE 0x00002000U +#define UART_ICR_RXDMADONE_M 0x00002000U +#define UART_ICR_RXDMADONE_S 13U + +// Field: [12] TXDMADONE +// +// TX DMA Done interrupt clear: +// Writing 1 to this field clears the TX DMA done interrupt (RIS.TXDMADONE). +// Writing 0 has no effect. +#define UART_ICR_TXDMADONE 0x00001000U +#define UART_ICR_TXDMADONE_M 0x00001000U +#define UART_ICR_TXDMADONE_S 12U + +// Field: [11] EOT +// +// End of Transmission interrupt clear: +// Writing 1 to this field clears the End of Transmission interrupt (RIS.EOT). +// Writing 0 has no effect. +#define UART_ICR_EOT 0x00000800U +#define UART_ICR_EOT_M 0x00000800U +#define UART_ICR_EOT_S 11U + +// Field: [10] OE +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OE). Writing +// 0 has no effect. +#define UART_ICR_OE 0x00000400U +#define UART_ICR_OE_M 0x00000400U +#define UART_ICR_OE_S 10U + +// Field: [9] BE +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BE). Writing 0 +// has no effect. +#define UART_ICR_BE 0x00000200U +#define UART_ICR_BE_M 0x00000200U +#define UART_ICR_BE_S 9U + +// Field: [8] PE +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PE). Writing +// 0 has no effect. +#define UART_ICR_PE 0x00000100U +#define UART_ICR_PE_M 0x00000100U +#define UART_ICR_PE_S 8U + +// Field: [7] FE +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FE). Writing +// 0 has no effect. +#define UART_ICR_FE 0x00000080U +#define UART_ICR_FE_M 0x00000080U +#define UART_ICR_FE_S 7U + +// Field: [6] RT +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RT). +// Writing 0 has no effect. +#define UART_ICR_RT 0x00000040U +#define UART_ICR_RT_M 0x00000040U +#define UART_ICR_RT_S 6U + +// Field: [5] TX +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TX). Writing 0 +// has no effect. +#define UART_ICR_TX 0x00000020U +#define UART_ICR_TX_M 0x00000020U +#define UART_ICR_TX_S 5U + +// Field: [4] RX +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RX). Writing 0 has +// no effect. +#define UART_ICR_RX 0x00000010U +#define UART_ICR_RX_M 0x00000010U +#define UART_ICR_RX_S 4U + +// Field: [1] CTSM +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTS). +// Writing 0 has no effect. +#define UART_ICR_CTSM 0x00000002U +#define UART_ICR_CTSM_M 0x00000002U +#define UART_ICR_CTSM_S 1U + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004U +#define UART_DMACTL_DMAONERR_M 0x00000004U +#define UART_DMACTL_DMAONERR_S 2U + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002U +#define UART_DMACTL_TXDMAE_M 0x00000002U +#define UART_DMACTL_TXDMAE_S 1U + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001U +#define UART_DMACTL_RXDMAE_M 0x00000001U +#define UART_DMACTL_RXDMAE_S 0U + + +#endif // __UART__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_vims.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_vims.h new file mode 100644 index 00000000..d58602a0 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_vims.h @@ -0,0 +1,604 @@ +/****************************************************************************** +* Filename: hw_vims_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Module Description +#define VIMS_O_DESC 0x00000000U + +// Extended Module Description +#define VIMS_O_DESCEX 0x00000004U + +// Internal. Only to be used through TI provided API. +#define VIMS_O_FLWS1T 0x00000008U + +// Internal. Only to be used through TI provided API. +#define VIMS_O_FLWS2T 0x0000000CU + +// Internal. Only to be used through TI provided API. +#define VIMS_O_PTRMC0 0x00000018U + +// Internal. Only to be used through TI provided API. +#define VIMS_O_B0TRMC1 0x0000001CU + +// Internal. Only to be used through TI provided API. +#define VIMS_O_B0TRMC0 0x00000020U + +// Internal. Only to be used through TI provided API. +#define VIMS_O_FLBLCK 0x00000100U + +// Internal. Only to be used through TI provided API. +#define VIMS_O_CFG 0x000003FCU + +// Flash main region write/erase protection configuration 1 +#define VIMS_O_WEPRA 0x00000410U + +// Flash main region write/erase protection configuration 2 +#define VIMS_O_WEPRB 0x00000414U + +// Flash write/erase protection configuration for other regions +#define VIMS_O_WEPRAUX 0x0000041CU + +// Flash status +#define VIMS_O_FLBSTAT 0x00000420U + +// Cache control +#define VIMS_O_CCHCTRL 0x00000424U + +//***************************************************************************** +// +// Register: VIMS_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODID +// +// Module identifier used to uniquely identify this IP. +#define VIMS_DESC_MODID_W 16U +#define VIMS_DESC_MODID_M 0xFFFF0000U +#define VIMS_DESC_MODID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// +// 0: Standard IP MMRs do not exist +// +// 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP +// address) +#define VIMS_DESC_STDIPOFF_W 4U +#define VIMS_DESC_STDIPOFF_M 0x0000F000U +#define VIMS_DESC_STDIPOFF_S 12U + +// Field: [11:8] INSTIDX +// +// IP Instance ID number. If multiple instances of IP exist in the device, this +// field can identify the instance number (0-15). +#define VIMS_DESC_INSTIDX_W 4U +#define VIMS_DESC_INSTIDX_M 0x00000F00U +#define VIMS_DESC_INSTIDX_S 8U + +// Field: [7:4] MAJREV +// +// Major revision of IP (0-15). +#define VIMS_DESC_MAJREV_W 4U +#define VIMS_DESC_MAJREV_M 0x000000F0U +#define VIMS_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor revision of IP (0-15). +#define VIMS_DESC_MINREV_W 4U +#define VIMS_DESC_MINREV_M 0x0000000FU +#define VIMS_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_DESCEX +// +//***************************************************************************** +// Field: [27] NBANK +// +// Provides the FLASH Bank count +#define VIMS_DESCEX_NBANK 0x08000000U +#define VIMS_DESCEX_NBANK_M 0x08000000U +#define VIMS_DESCEX_NBANK_S 27U + +// Field: [26:15] FLSZ +// +// This provides the total FLASH size in Kilo Bytes. The total FLASH size is +// (FLSZ + 1)KB +#define VIMS_DESCEX_FLSZ_W 12U +#define VIMS_DESCEX_FLSZ_M 0x07FF8000U +#define VIMS_DESCEX_FLSZ_S 15U + +// Field: [14:0] ROMSZ +// +// Provides the size of ROM in Bytes. +#define VIMS_DESCEX_ROMSZ_W 15U +#define VIMS_DESCEX_ROMSZ_M 0x00007FFFU +#define VIMS_DESCEX_ROMSZ_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_FLWS1T +// +//***************************************************************************** +// Field: [2:0] VAL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// WS7 Internal. Only to be used through TI provided API. +// WS6 Internal. Only to be used through TI provided API. +// WS5 Internal. Only to be used through TI provided API. +// WS4 Internal. Only to be used through TI provided API. +// WS3 Internal. Only to be used through TI provided API. +// WS2 Internal. Only to be used through TI provided API. +// WS1 Internal. Only to be used through TI provided API. +// WS0 Internal. Only to be used through TI provided API. +#define VIMS_FLWS1T_VAL_W 3U +#define VIMS_FLWS1T_VAL_M 0x00000007U +#define VIMS_FLWS1T_VAL_S 0U +#define VIMS_FLWS1T_VAL_WS7 0x00000007U +#define VIMS_FLWS1T_VAL_WS6 0x00000006U +#define VIMS_FLWS1T_VAL_WS5 0x00000005U +#define VIMS_FLWS1T_VAL_WS4 0x00000004U +#define VIMS_FLWS1T_VAL_WS3 0x00000003U +#define VIMS_FLWS1T_VAL_WS2 0x00000002U +#define VIMS_FLWS1T_VAL_WS1 0x00000001U +#define VIMS_FLWS1T_VAL_WS0 0x00000000U + +//***************************************************************************** +// +// Register: VIMS_O_FLWS2T +// +//***************************************************************************** +// Field: [2:0] VAL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// WS7 Internal. Only to be used through TI provided API. +// WS6 Internal. Only to be used through TI provided API. +// WS5 Internal. Only to be used through TI provided API. +// WS4 Internal. Only to be used through TI provided API. +// WS3 Internal. Only to be used through TI provided API. +// WS2 Internal. Only to be used through TI provided API. +// WS1 Internal. Only to be used through TI provided API. +// WS0 Internal. Only to be used through TI provided API. +#define VIMS_FLWS2T_VAL_W 3U +#define VIMS_FLWS2T_VAL_M 0x00000007U +#define VIMS_FLWS2T_VAL_S 0U +#define VIMS_FLWS2T_VAL_WS7 0x00000007U +#define VIMS_FLWS2T_VAL_WS6 0x00000006U +#define VIMS_FLWS2T_VAL_WS5 0x00000005U +#define VIMS_FLWS2T_VAL_WS4 0x00000004U +#define VIMS_FLWS2T_VAL_WS3 0x00000003U +#define VIMS_FLWS2T_VAL_WS2 0x00000002U +#define VIMS_FLWS2T_VAL_WS1 0x00000001U +#define VIMS_FLWS2T_VAL_WS0 0x00000000U + +//***************************************************************************** +// +// Register: VIMS_O_PTRMC0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Internal. Only to be used through TI provided API. +#define VIMS_PTRMC0_VAL_W 32U +#define VIMS_PTRMC0_VAL_M 0xFFFFFFFFU +#define VIMS_PTRMC0_VAL_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_B0TRMC1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Internal. Only to be used through TI provided API. +#define VIMS_B0TRMC1_VAL_W 32U +#define VIMS_B0TRMC1_VAL_M 0xFFFFFFFFU +#define VIMS_B0TRMC1_VAL_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_B0TRMC0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Internal. Only to be used through TI provided API. +#define VIMS_B0TRMC0_VAL_W 32U +#define VIMS_B0TRMC0_VAL_M 0xFFFFFFFFU +#define VIMS_B0TRMC0_VAL_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_FLBLCK +// +//***************************************************************************** +// Field: [0] VAL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BLOCK Internal. Only to be used through TI provided API. +// ALLOW Internal. Only to be used through TI provided API. +#define VIMS_FLBLCK_VAL 0x00000001U +#define VIMS_FLBLCK_VAL_M 0x00000001U +#define VIMS_FLBLCK_VAL_S 0U +#define VIMS_FLBLCK_VAL_BLOCK 0x00000001U +#define VIMS_FLBLCK_VAL_ALLOW 0x00000000U + +//***************************************************************************** +// +// Register: VIMS_O_CFG +// +//***************************************************************************** +// Field: [1] TRMVLID +// +// Internal. Only to be used through TI provided API. +#define VIMS_CFG_TRMVLID 0x00000002U +#define VIMS_CFG_TRMVLID_M 0x00000002U +#define VIMS_CFG_TRMVLID_S 1U + +// Field: [0] WEPRTRM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ALLOW Internal. Only to be used through TI provided API. +// RESTRICT Internal. Only to be used through TI provided API. +#define VIMS_CFG_WEPRTRM 0x00000001U +#define VIMS_CFG_WEPRTRM_M 0x00000001U +#define VIMS_CFG_WEPRTRM_S 0U +#define VIMS_CFG_WEPRTRM_ALLOW 0x00000001U +#define VIMS_CFG_WEPRTRM_RESTRICT 0x00000000U + +//***************************************************************************** +// +// Register: VIMS_O_WEPRA +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Flash write/erase protection configuration value. +#define VIMS_WEPRA_VAL_W 32U +#define VIMS_WEPRA_VAL_M 0xFFFFFFFFU +#define VIMS_WEPRA_VAL_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_WEPRB +// +//***************************************************************************** +// Field: [27:0] VAL +// +// Flash write/erase protection configuration value. +#define VIMS_WEPRB_VAL_W 28U +#define VIMS_WEPRB_VAL_M 0x0FFFFFFFU +#define VIMS_WEPRB_VAL_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_WEPRAUX +// +//***************************************************************************** +// Field: [2] WEPREGR +// +// Flash engr region write/erase protection configuration value. +#define VIMS_WEPRAUX_WEPREGR 0x00000004U +#define VIMS_WEPRAUX_WEPREGR_M 0x00000004U +#define VIMS_WEPRAUX_WEPREGR_S 2U + +// Field: [1] WEPRTRM +// +// Flash trim region write/erase protection configuration value. +#define VIMS_WEPRAUX_WEPRTRM 0x00000002U +#define VIMS_WEPRAUX_WEPRTRM_M 0x00000002U +#define VIMS_WEPRAUX_WEPRTRM_S 1U + +// Field: [0] WEPRNMN +// +// Flash non main region write/erase protection configuration value. +#define VIMS_WEPRAUX_WEPRNMN 0x00000001U +#define VIMS_WEPRAUX_WEPRNMN_M 0x00000001U +#define VIMS_WEPRAUX_WEPRNMN_S 0U + +//***************************************************************************** +// +// Register: VIMS_O_FLBSTAT +// +//***************************************************************************** +// Field: [3] PARERR +// +// This bit indicates parity error on write/erase and read protection MMRs. +// This bit is sticky when set to 1 by hardware. +// ENUMs: +// ERROR Error +// NOERROR No Error +#define VIMS_FLBSTAT_PARERR 0x00000008U +#define VIMS_FLBSTAT_PARERR_M 0x00000008U +#define VIMS_FLBSTAT_PARERR_S 3U +#define VIMS_FLBSTAT_PARERR_ERROR 0x00000008U +#define VIMS_FLBSTAT_PARERR_NOERROR 0x00000000U + +// Field: [2] B0BSY +// +// This bit indicates if flash is busy. +// ENUMs: +// BUSY Busy +// IDLE Idle +#define VIMS_FLBSTAT_B0BSY 0x00000004U +#define VIMS_FLBSTAT_B0BSY_M 0x00000004U +#define VIMS_FLBSTAT_B0BSY_S 2U +#define VIMS_FLBSTAT_B0BSY_BUSY 0x00000004U +#define VIMS_FLBSTAT_B0BSY_IDLE 0x00000000U + +// Field: [1] B2TRDY +// +// This bit indicates if flash is ready in 2T mode. +// ENUMs: +// READY Ready +// NOTREADY Not Ready +#define VIMS_FLBSTAT_B2TRDY 0x00000002U +#define VIMS_FLBSTAT_B2TRDY_M 0x00000002U +#define VIMS_FLBSTAT_B2TRDY_S 1U +#define VIMS_FLBSTAT_B2TRDY_READY 0x00000002U +#define VIMS_FLBSTAT_B2TRDY_NOTREADY 0x00000000U + +// Field: [0] B1TRDY +// +// This bit indicates if flash is ready in 1T mode. +// ENUMs: +// READY Ready +// NOTREADY Not Ready +#define VIMS_FLBSTAT_B1TRDY 0x00000001U +#define VIMS_FLBSTAT_B1TRDY_M 0x00000001U +#define VIMS_FLBSTAT_B1TRDY_S 0U +#define VIMS_FLBSTAT_B1TRDY_READY 0x00000001U +#define VIMS_FLBSTAT_B1TRDY_NOTREADY 0x00000000U + +//***************************************************************************** +// +// Register: VIMS_O_CCHCTRL +// +//***************************************************************************** +// Field: [2] CCHMPEN +// +// This bit is used to enable the micropredictor unit. +// ENUMs: +// EN Enable +// DIS Disable +#define VIMS_CCHCTRL_CCHMPEN 0x00000004U +#define VIMS_CCHCTRL_CCHMPEN_M 0x00000004U +#define VIMS_CCHCTRL_CCHMPEN_S 2U +#define VIMS_CCHCTRL_CCHMPEN_EN 0x00000004U +#define VIMS_CCHCTRL_CCHMPEN_DIS 0x00000000U + +// Field: [1] CCHPFEN +// +// This bit is used to enable the prefetch unit. +// ENUMs: +// EN Enable +// DIS Disable +#define VIMS_CCHCTRL_CCHPFEN 0x00000002U +#define VIMS_CCHCTRL_CCHPFEN_M 0x00000002U +#define VIMS_CCHCTRL_CCHPFEN_S 1U +#define VIMS_CCHCTRL_CCHPFEN_EN 0x00000002U +#define VIMS_CCHCTRL_CCHPFEN_DIS 0x00000000U + +// Field: [0] CCHEN +// +// This bit is used to enable the cache. +// ENUMs: +// EN Enable +// DIS Disable +#define VIMS_CCHCTRL_CCHEN 0x00000001U +#define VIMS_CCHCTRL_CCHEN_M 0x00000001U +#define VIMS_CCHCTRL_CCHEN_S 0U +#define VIMS_CCHCTRL_CCHEN_EN 0x00000001U +#define VIMS_CCHCTRL_CCHEN_DIS 0x00000000U + + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + + +#endif // __VIMS__ diff --git a/simplelink_lpf3/source/ti/drivers/BatteryMonitor.h b/simplelink_lpf3/source/ti/drivers/BatteryMonitor.h new file mode 100644 index 00000000..74002241 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/BatteryMonitor.h @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file BatteryMonitor.h + * + * @brief Battery Monitor driver + * + * @anchor ti_drivers_BatteryMonitor_Overview + * # Overview # + * The Battery Monitor driver provides services related to measuring and + * reacting to the current supply voltage of the device, and changes to it. + * + * The two main services provided are: + * - Getting the current supply voltage + * - Providing notification callbacks when the supply voltage changes + * + * @anchor ti_drivers_BatteryMonitor_Usage + * # Usage # + * + * ## Initialisation # + * Unlike most drivers, there is only a single instance of the Battery Monitor + * driver that is always available once #BatteryMonitor_init() is called. + * #BatteryMonitor_init() should be called once before using other Battery + * Monitor driver APIs. Subsequent #BatteryMonitor_init() calls will have no + * effect. + * + * ## Getting the Current Supply Voltage # + * The driver can read the current supply voltage and return it. The resolution + * is device-specific (see device-specific Battery Monitor documentation), but + * the voltage will always be encoded as an unsigned integer in millivolts + * (mV). + * + * ## Notifications # + * The Battery Monitor driver can notify the application when the supply + * voltage crosses an application-defined threshold. + * + * There are three default use cases for this: + * - High threshold. + * The application will receive a notification callback when + * currentVoltage >= thresholdHigh. + * - Low threshold. + * The application will receive a notification callback when + * currentVoltage <= thresholdLow. + * - Range threshold. + * The application will receive a notification callback when + * currentVoltage >= thresholdHigh || currentVoltage <= + * thresholdLow. This setup addresses use cases + * where a notification is required when the supply voltage changes by a + * certain amount regardless of whether it is up or down. + * + * ### Registering Notifications + * There are three functions that register a notification for the application: + * - #BatteryMonitor_registerNotifyHigh() + * - #BatteryMonitor_registerNotifyLow() + * - #BatteryMonitor_registerNotifyRange() + * + * Multiple notifications may be registered. The different parts of the + * application and drivers that need to respond to a supply voltage change do + * not need to know of one another. + * Each notification must have its own #BatteryMonitor_NotifyObj and must be + * registered individually. + * + * ### Notification Callbacks + * Once the supply voltage crosses the smallest "high threshold" or largest + * "low threshold amongst the registered notifications, the driver will + * iterate over the entire list of registered notification and check which + * ones have triggered. Notifications that have triggered are removed from the + * list of registered notifications before their callback function is invoked. + * + * If an application wishes to re-register a notification that just triggered + * and was unregistered, it may register it again from within the notification + * callback or another context. + * + * It is possible to determine whether the high or low threshold triggered + * the notification callback as follows: + * - currentVoltage <= thresholdVoltage: Low threshold triggered + * - currentVoltage >= thresholdVoltage: High threshold triggered + * This information is only reasonably useful when registering a notification + * with both a high and low threshold using + * #BatteryMonitor_registerNotifyRange(). Even then, the expected basic use + * case only cares about the current voltage and adding an offset to it when + * registering the notification again. + * + * ### Unregistering Notifications + * Registered notifications are unregistered in two ways: + * - Automatically when a notification triggers + * - By calling #BatteryMonitor_unregisterNotify() + * + * Unregistered notifications may be registered again at any time. + * + * @anchor ti_drivers_BatteryMonitor_Synopsis + * # Synopsis # + * @anchor ti_drivers_BatteryMonitor_Synopsis_Code + * @code + * #include + * + * #define WINDOW_DELTA_MILLIVOLT 300 + * + * BatteryMonitor_init(); + * + * currentVoltage = BatteryMonitor_getVoltage(); + * + * result = BatteryMonitor_registerNotifyRange(¬ifyObject, + * currentVoltage + WINDOW_DELTA_MILLIVOLT, + * currentVoltage - WINDOW_DELTA_MILLIVOLT, + * myNotifyFxn, + * clientArg); + * @endcode + * + * @anchor ti_drivers_BatteryMonitor_Examples + * # Examples # + * + * ## Register a High Threshold Notification # + * + * @code + * + * // The notification will trigger when the supply voltage reaches 3.5V + * #define THRESHOLD_CUTOFF_MILLIVOLT 3500 + * + * #include + * + * void thresholdNotifyFxn(uint16_t currentVoltage, + * uint16_t thresholdVoltage, + * uintptr_t clientArg, + * BatteryMonitor_NotifyObj *notifyObject) { + * // Post a semaphore, set a flag, or otherwise act upon the voltage change. + * } + * + * ... + * + * // Initialize the Battery Monitor driver and register a notification. + * + * BatteryMonitor_init(); + * + * int_fast16_t status = BatteryMonitor_registerNotifyHigh(notifyObject, + * THRESHOLD_CUTOFF_MILLIVOLT, + * thresholdNotifyFxn, + * NULL); + * + * if (status != BatteryMonitor_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * ## Register a Range Threshold Notification and re-register in Callback # + * + * @code + * + * #define THRESHOLD_DELTA_MILLIVOLT 300 + * + * #include + * + * + * void deltaNotificationFxn(uint16_t currentVoltage, + * uint16_t thresholdVoltage, + * uintptr_t clientArg, + * BatteryMonitor_NotifyObj *notifyObject) { + * int_fast16_t status; + * + * status = BatteryMonitor_registerNotifyRange(notifyObject, + * currentVoltage + THRESHOLD_DELTA_MILLIVOLT, + * currentVoltage - THRESHOLD_DELTA_MILLIVOLT, + * deltaNotificationFxn, + * clientArg); + * + * if (status != BatteryMonitor_STATUS_SUCCESS) { + * while(1); + * } + * } + * + * ... + * + * // Initialize the Battery Monitor driver and register a notification. + * + * BatteryMonitor_init(); + * + * BatteryMonitor_NotifyObj rangeNotifyObject; + * + * uint16_t currentVoltage = BatteryMonitor_getVoltage(); + * + * int_fast16_t status = BatteryMonitor_registerNotifyRange(6rangeNotifyObject, + * currentVoltage + THRESHOLD_DELTA_MILLIVOLT, + * currentVoltage - THRESHOLD_DELTA_MILLIVOLT, + * deltaNotificationFxn, + * (uintptr_t)NULL); + * @endcode + */ + +#ifndef ti_drivers_BatteryMonitor__include +#define ti_drivers_BatteryMonitor__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common Battery Monitor status code reservation offset. + * Battery Monitor driver implementations should offset status codes with + * BatteryMonitor_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define BatteryMonitorXYZ_STATUS_ERROR0 BatteryMonitor_STATUS_RESERVED - 0 + * #define BatteryMonitorXYZ_STATUS_ERROR1 BatteryMonitor_STATUS_RESERVED - 1 + * #define BatteryMonitorXYZ_STATUS_ERROR2 BatteryMonitor_STATUS_RESERVED - 2 + * @endcode + */ +#define BatteryMonitor_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return BatteryMonitor_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define BatteryMonitor_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return BatteryMonitor_STATUS_ERROR if the function was not executed + * successfully. + */ +#define BatteryMonitor_STATUS_ERROR (-1) + +/* @cond NODOC + * + * Type declaration for the notification object made separately from the + * struct definition because of the circular dependency between + * #BatteryMonitor_NotifyFxn() and #BatteryMonitor_NotifyObj. + */ +typedef struct BatteryMonitor_NotifyObj BatteryMonitor_NotifyObj; +/* @endcond */ + +/*! + * @brief Function prototype for a notification callback. + * + * @param [in] currentVoltage Current supply voltage in millivolts + * + * @param [in] thresholdVoltage Voltage threshold in millivolts that + * caused this notification callback. + * + * @param [in] clientArg Argument provided by the application + * during registration. + * + * @param [in/out] notifyObject Pointer to notification object that was + * registered previously. This may be used + * to register the notification again with + * updated inputs from within the + * notification callback. + */ +typedef void (*BatteryMonitor_NotifyFxn)(uint16_t currentVoltage, + uint16_t thresholdVoltage, + uintptr_t clientArg, + BatteryMonitor_NotifyObj *notifyObject); + +/*! + * @brief Battery Monitor notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * #BatteryMonitor_registerNotifyHigh(), #BatteryMonitor_registerNotifyLow(), + * or #BatteryMonitor_registerNotifyRange() will take care initializing the + * internal elements appropriately. + */ +struct BatteryMonitor_NotifyObj +{ + List_Elem link; /*!< For placing on the notify list */ + BatteryMonitor_NotifyFxn notifyFxn; /*!< Application callback function */ + uint16_t thresholdHigh; /*!< High threshold in millivolts */ + uint16_t thresholdLow; /*!< Low threshold in millivolts */ + uintptr_t clientArg; /*!< Application provided arg */ + bool isRegistered; /*!< Is the notification active */ +}; + +/*! + * @brief This function initializes the Battery Monitor driver. + * + * This function initializes the internal state of the Battery Monitor driver. + * It must be called before calling any other Battery Monitor functions. + * Subsequent calls to this function have no effect. + */ +void BatteryMonitor_init(void); + +/*! + * @brief Gets the current supply voltage in millivolts. + * + * @return Current supply voltage in millivolts + */ +uint16_t BatteryMonitor_getVoltage(void); + +/*! + * @brief Registers a notification with a high threshold. + * + * This function registers a Battery Monitor notification with a high + * threshold. Once the supply voltage rises above @c thresholdHigh, + * the notification is automatically unregistered and function @c notifyFxn is + * called. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh Threshold supply voltage in millivolts + * + * @param [in] notifyFxn Callback function that is called once the + * supply voltage rises above @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #BatteryMonitor_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #BatteryMonitor_STATUS_ERROR There was an error during + * registration. + * + * @pre BatteryMonitor_init() called + */ +int_fast16_t BatteryMonitor_registerNotifyHigh(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdHigh, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with a low threshold. + * + * This function registers a Battery Monitor notification with a low threshold. + * Once the supply voltage falls below @c thresholdLow, the notification is + * automatically unregistered and function @c notifyFxn is called. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdLow Threshold supply voltage in millivolts + * + * @param [in] notifyFxn Callback function that is called once the + * supply voltage falls below @c thresholdLow. + * + * @param [in] clientArg Application-specified argument + * + * @retval #BatteryMonitor_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #BatteryMonitor_STATUS_ERROR There was an error during registration. + * + * @pre BatteryMonitor_init() called + */ +int_fast16_t BatteryMonitor_registerNotifyLow(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdLow, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with both a high and low threshold. + * + * This function registers a Battery Monitor notification with a high and low + * threshold. Once the supply voltage rises above @c thresholdHigh or + * falls below @c thresholdLow, the notification is automatically unregistered + * and function @c notifyFxn is called. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh High threshold supply voltage in millivolts + * + * @param [in] thresholdLow Low threshold supply voltage in millivolts + * + * @param [in] notifyFxn Callback function that is called once the + * supply voltage falls below + * @c thresholdLow, or rises above + * @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #BatteryMonitor_STATUS_SUCCESS The notification was successfully + * registered + * @retval #BatteryMonitor_STATUS_ERROR There was an error during + * registration + * + * @pre BatteryMonitor_init() called + */ +int_fast16_t BatteryMonitor_registerNotifyRange(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdHigh, + uint16_t thresholdLow, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Unregisters a currently registered notification. + * + * This function unregisters a currently registered notification. + * + * @param notifyObject Notification to unregister. + * + * @retval #BatteryMonitor_STATUS_SUCCESS The notification was successfully + * unregistered. + * @retval #BatteryMonitor_STATUS_ERROR There was an error during + * unregistration. + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyHigh(), + * #BatteryMonitor_registerNotifyLow(), or #BatteryMonitor_registerNotifyRange() + */ +int_fast16_t BatteryMonitor_unregisterNotify(BatteryMonitor_NotifyObj *notifyObject); + +/*! + * @brief Get the high threshold of a notification. + * + * @warning This function should not be called on a @c notifyObject registered + * with #BatteryMonitor_registerNotifyLow(). The high threshold value returned + * in that case will be a device-specific invalid voltage. + * + * @param notifyObject Notification to get the high threshold of. + * + * @return High threshold in millivolts. + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyHigh(), + * or #BatteryMonitor_registerNotifyRange() + */ +static inline uint16_t BatteryMonitor_getThresholdHigh(BatteryMonitor_NotifyObj *notifyObject) +{ + return notifyObject->thresholdHigh; +} + +/*! + * @brief Get the low threshold of a notification. + * + * @warning This function should not be called on a @c notifyObject registered + * with #BatteryMonitor_registerNotifyHigh(). The low threshold value returned + * in that case will be a device-specific invalid voltage. + * + * @param notifyObject Notification to get the low threshold of. + * + * @return Low threshold in millivolts. + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyLow(), + * or #BatteryMonitor_registerNotifyRange() + */ +static inline uint16_t BatteryMonitor_getThresholdLow(BatteryMonitor_NotifyObj *notifyObject) +{ + return notifyObject->thresholdLow; +} + +/*! + * @brief Get the high and low threshold of a notification. + * + * @warning This function should not be called on a @c notifyObject registered + * with #BatteryMonitor_registerNotifyLow() or + * #BatteryMonitor_registerNotifyHigh(). The unconfigured threshold value + * returned in that case will be a device-specific invalid voltage. + * + * @param notifyObject Notification to get the high and low threshold + * of. + * + * @param [out] thresholdHigh High threshold value in millivolts written + * back by this function. + * + * @param [out] thresholdLow Low threshold value in millivolts written + * back by this function. + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyRange() + */ +static inline void BatteryMonitor_getThresholdRange(BatteryMonitor_NotifyObj *notifyObject, + uint16_t *thresholdHigh, + uint16_t *thresholdLow) +{ + *thresholdHigh = notifyObject->thresholdHigh; + *thresholdLow = notifyObject->thresholdLow; +} + +/*! + * @brief Get the application-provided clientArg of a notification. + * + * @param notifyObject Notification to get the clientArg of. + * + * @return The clientArg provided during registration. + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyHigh(), + * #BatteryMonitor_registerNotifyLow(), or #BatteryMonitor_registerNotifyRange() + */ +static inline uintptr_t BatteryMonitor_getClientArg(BatteryMonitor_NotifyObj *notifyObject) +{ + return notifyObject->clientArg; +} + +/*! + * @brief Get the notifyFxn provided during registration. + * + * @param notifyObject Notification to get the notifyFxn of. + * + * @return The notifyFxn provided during registration + * + * @pre Register @c notifyObject with #BatteryMonitor_registerNotifyHigh(), + * #BatteryMonitor_registerNotifyLow(), or #BatteryMonitor_registerNotifyRange() + */ +static inline BatteryMonitor_NotifyFxn BatteryMonitor_getNotifyFxn(BatteryMonitor_NotifyObj *notifyObject) +{ + return notifyObject->notifyFxn; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_BatteryMonitor__include */ diff --git a/simplelink_lpf3/source/ti/drivers/Board.h b/simplelink_lpf3/source/ti/drivers/Board.h new file mode 100644 index 00000000..de868865 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/Board.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!**************************************************************************** + * @file Board.h + * @brief Portable board-specific symbols + * + * The Board header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * This header serves as device-independent interface for applications using + * peripherals connected to the device via standard digital interfaces; e.g, + * GPIO, SPI, I2C, UART, etc. Its purpose is to enable application code that + * references a peripheral to be portable to any device and board that + * supports the peripheral. + * + * ## Usage ## + * + * @anchor ti_drivers_Board_Synopsis + * ### Synopsis # + * @anchor ti_drivers_Board_Synopsis_Code + * @code + * #include + * + * void main(void) + * { + * Board_init(); + * : + * } + * @endcode + * + * ## Initializing the hardware ## + * + * \p Board_init() must be called before any other driver API. This function + * is owned by the user (typically generated by SysConfig), and is + * responsible for device specific initialization; e.g., initializing clocks + * and power management functionality. + ****************************************************************************** + */ + +#ifndef ti_drivers_Board__include +#define ti_drivers_Board__include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Performs "early" board-level initialization required by TI-DRIVERS + * + * Board_init() must be called before any other TI-DRIVER API. This function + * calls all device and board specific initialization functions needed by + * TI-DRIVERS; e.g., to initialize clocks and power management functionality. + * + * This function should only be called once and as early in the application's + * startup as possible. In most applications, a call to Board_init() is the + * first statement in \p main(). + * + * @pre \p Board_init must be called after every CPU reset and _prior_ to + * enabling any interrupts. + */ +extern void Board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Board_include */ diff --git a/simplelink_lpf3/source/ti/drivers/Power.h b/simplelink_lpf3/source/ti/drivers/Power.h new file mode 100644 index 00000000..2048c614 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/Power.h @@ -0,0 +1,961 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file Power.h + * @brief Power Manager + * + * @anchor ti_drivers_Power_Overview + * # Overview + * + * The Power Manager facilitates the transition of the MCU from active states + * to sleep states and vice versa. It provides other drivers the + * ability to set and release dependencies on hardware resources, and keeps + * reference counts on each resource to know when to enable or disable the + * resource. It provides drivers the ability to register callback functions + * to be invoked upon specific power events. In addition, drivers and + * applications can set or release constraints to prevent the MCU from + * transitioning into specific active or sleep states. Refer to the device + * specific power driver header file device specific information. + * + *
+ * @anchor ti_drivers_Power_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_Power_Synopsis + * "usage summary" and a set of @ref ti_drivers_Power_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * @anchor ti_drivers_Power_Synopsis + * ## Synopsis + * @anchor ti_drivers_Power_Synopsis_Code + * + * @note The following example demonstrates usage of some of the Power + * driver APIs.This example is intended for reference only and is not intended + * for application use. You should refer to the device specific Power driver + * header for valid API usage and arguments. + * + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set power dependency on a resource + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Other application code + * + * // Release a previously set power constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Examples + * # Examples + * + * @note + * The following examples are intended for reference only and are not + * intended for application use. You should refer to the device specific + * Power driver header file for more usage information. + * + * @li @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @li @ref ti_drivers_Power_Examples_disable "Disabling power policy" + * @li @ref ti_drivers_Power_Examples_constraint "Using power constraints" + * @li @ref ti_drivers_Power_Examples_dependency "Using power dependency" + * @li @ref ti_drivers_Power_Examples_notify "Using power notify" + * @li @ref ti_drivers_Power_Examples_transistion "Power transitions" + * + * + * @anchor ti_drivers_Power_Examples_enable + * ## Enabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Enable power policy + * Power_enablePolicy(); + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_disable + * ## Disabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * bool flag; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Disable power policy + * flag = Power_disablePolicy(); + * if (flag == false) { + * // Power policy was already disabled + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_constraint + * ## Using Power Constraints + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t mask; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred setting constraint + * } + * + * // Read mask of currently set power constraints + * mask = Power_getConstraintMask(); + * + * // Release previously set constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred releasing constraint + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_dependency + * ## Using Power Dependency + * + * @code + * // Import Power Driver definitions + * #include + * + * int16_t count; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power dependency + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred setting dependency + * } + * + * // Get the dependency count of the resource + * count = Power_getDependencyCount(resourceId); + * if (count == Power_EINVALIDINPUT) { + * // Invalid resourceId used + * } + * + * if (count > 0) { + * // At least 1 dependency exists for the resource. + * // Regardless, we may safely release the dependency when we + * // no longer need the resource. + * } + * + * // Release a power dependency + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred releasing dependency + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_notify + * ## Using Power Notify + * + * The application must define a #Power_NotifyFxn function and + * allocate memory for the #Power_NotifyObj object. + * + * @code + * // Import Power Driver definitions + * #include + * + * // Application Power_NotifyObj object + * Power_NotifyObj powerNotifyObj; + * + * // Application Power_NotifyFxn function prototype + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg); + * @endcode + * + * The application must register for the event. Here, we use pseudo event + * names. You should refer to the device specific power driver header file + * for eventTypes. Inside the infinite loop, we wait for a semaphore to be + * post from our notification callback. + * + * @code + * // Application thread + * void thread(void) + * { + * int16_t status; + * unsigned int eventTypes = LOW_POWER_EXIT | LOW_POWER_ENTER; + * uintptr_t clientArg = semaphoreHandle; + * + * status = Power_registerNotify(&powerNotifyObj, eventTypes, + * postNotifyFxn, clientArg); + * + * while (1) + * { + * sem_wait(semaphoreHandle); + * // Do something + * + * // Unregister for the notification. After this call, + * // our postNotifyFxn() will never be called again unless + * // we use Power_registerNotify() again. + * Power_unregisterNotify(&powerNotifyObj); + * + * break; + * } + * } + * @endcode + * + * The application may implement the power notify function to fit their + * needs. The #Power_NotifyFxn should always return #Power_NOTIFYDONE or + * #Power_NOTIFYERROR. + * + * @code + * // Application Power_NotifyFxn function implementation + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg) + * { + * sem_t semaphoreHandle = (sem_t) clientArg; + * + * if (eventType == LOW_POWER_EXIT) { + * sem_post(semaphoreHandle); + * return (Power_NOTIFYDONE); + * } + * + * if (eventType == LOW_POWER_ENTER) { + * // Store something in RAM + * return (Power_NOTIFYDONE); + * } + * + * // We received an unexpected event type + * return (Power_NOTIFYERROR); + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_transistion + * ## Power transitions + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t totalLatency, resumeLatency; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Get the current power transition state + * status = Power_getTransitionState(); + * + * switch (status) + * { + * case Power_ACTIVE: + * // No transitions in progress + * break; + * case Power_ENTERING_SLEEP: + * // Transition to sleep in progress + * break; + * case Power_EXITING_SLEEP: + * // Transition from sleep in progress + * break; + * } + * + * // Get the Power_TOTAL and Power_RESUME transition latency for a + * // device specific sleepState. Latency is in microseconds. + * totalLatency = Power_getTransitionLatency(sleepState, Power_TOTAL); + * resumeLatency = Power_getTransitionLatency(sleepState, Power_RESUME); + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Configuration + * # Configuration + * + * @note The Power Manager APIs and configuration parameters are described here. + * For a detailed description of terms and concepts, and usage by different + * types of software components (peripheral drivers, power policies, + * and applications) please see the + * SimpleLink SDK Power Management User's Guide. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_Power__include +#define ti_drivers_Power__include + +/* @cond */ +#include +#include +/* @endcond */ + +#include +#include + +/* Note: Device specific Power include files are included in the bottom of this file. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @addtogroup Power_Latency_Type + * @{ + */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ +/*! @}*/ + +/*! @addtogroup Power_Notify_Response + * @{ + */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ +/*! @}*/ + +/*! @addtogroup Power_Status + * @{ + */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ +/*! @}*/ + +/*! @addtogroup Power_Transition_State + * @{ + */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +/*! @}*/ + +/*! + * @brief Power policy initialization function pointer + */ +typedef void (*Power_PolicyInitFxn)(void); + +/*! + * @brief Power policy function pointer + */ +typedef void (*Power_PolicyFxn)(void); + +/*! + * @brief Power notify callback function used with the + * Power_registerNotify() + * + * @param[in] eventType The eventTypes parameter identifies the type of + * power event for which the notify callback function was called. + * + * @param[in] eventArg An optional @p eventType specific argument. + * + * @param[in] clientArg Pointer to a custom argument. + * + * @retval #Power_NOTIFYDONE if the client processed the notification + * successfully + * + * @retval #Power_NOTIFYERROR if an error occurred during notification. + * + * @sa Power_registerNotify() + * @sa Power_unregisterNotify() + * @sa Power_NotifyObj + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, uintptr_t eventArg, uintptr_t clientArg); + +/*! + * @brief Power notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * Power_registerNotify() will take care initializing the internal elements + * appropriately. + * + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef struct +{ + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ +} Power_NotifyObj; + +/*! + * @brief Power resource identifier + */ +typedef uint32_t Power_Resource; + +/*! + * @brief Disable the configured power policy from running when the CPU is + * idle + * + * Calling this function clears the flag that controls whether the configured + * power policy function is invoked on each pass through the Idle loop. + * This function call will override both a 'true' setting of the + * "enablePolicy" setting in the Power Manager configuration object, as well + * as a previous runtime call to the Power_enablePolicy() function. + * + * @return The old value of "enablePolicy". + * + * @sa Power_enablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +bool Power_disablePolicy(void); + +/*! + * @brief Enable the configured power policy to run when the CPU is idle + * + * Calling this function sets a flag that will cause the configured power + * policy function to be invoked on each pass through the Idle loop. This + * function call will override both a 'false' setting of the "enablePolicy" + * setting in the Power Manager configuration object, as well as a previous + * runtime call to the Power_disablePolicy() function. + * + * For some processor families, automatic power transitions can make initial + * application development more difficult, as well as being at odds with + * basic debugger operation. This convenience function allows an application + * to be initially configured, built, and debugged, without automatic power + * transitions during idle time. When the application is found to be working, + * this function can be called (typically in main()) to enable the policy + * to run, without having to change the application configuration. + * + * @sa Power_disablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +void Power_enablePolicy(void); + +/*! + * @brief Get the constraints that have been declared with Power + * + * This function returns a bitmask indicating the constraints that are + * currently declared to the Power Manager (via previous calls to + * Power_setConstraint()). For each constraint that is currently declared, + * the corresponding bit in the bitmask will be set. For example, if two + * clients have independently declared two different constraints, the returned + * bitmask will have two bits set. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. The corresponding bit in the + * bitmask returned by this function can be derived by a left-shift using + * the constraint identifier. For example, for CC26XX, for the corresponding + * bit for the PowerCC26XX_DISALLOW_STANDBY constraint, the bit position is + * determined by the operation: (1 << PowerCC26XX_DISALLOW_STANDBY) + * + * @return A bitmask of the currently declared constraints. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +uint_fast32_t Power_getConstraintMask(void); + +/*! + * @brief Get the current dependency count for a resource + * + * This function returns the number of dependencies that are currently + * declared upon a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return The number of dependencies declared for the resource. + * + * @retval #Power_EINVALIDINPUT if the @p resourceId is invalid or this + * function is not supported by the device specific implementation. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_getDependencyCount(Power_Resource resourceId); + +/*! + * @brief Get the current constraint count for an operational transition + * + * This function returns the current number of constraints that is set on the + * given operational transition. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h, and to see how many constraints there + * currently are on entering standby, call this function with argument + * PowerCC26XX_DISALLOW_STANDBY + * + * @param[in] constraintId constraint identifier + * + * @return The count for the given power constraint identifier + * + * @retval #Power_EINVALIDINPUT if the @p constraintId is invalid or this + * function is not supported by the device specific implementation. + * + * @sa Power_setConstraint() + */ +int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId); + +/*! + * @brief Get the hardware transition latency for a sleep state + * + * This function reports the minimal hardware transition latency for a specific + * sleep state. The reported latency is that for a direct transition, and does + * not include any additional latency that might occur due to software-based + * notifications. + * + * Sleep states are device specific, and defined in the device-specific Power + * include file. For example, the sleep states for CC32XX are defined in + * PowerCC32XX.h. + * + * This function is typically called by the power policy function. The latency + * is reported in units of microseconds. + * + * @param[in] sleepState the sleep state + * + * @param[in] type @ref Power_Latency_Type (#Power_TOTAL or #Power_RESUME) + * + * @return The latency value, in units of microseconds. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, uint_fast16_t type); + +/*! + * @brief Get the current transition state of the Power Manager + * + * @return The current @ref Power_Transition_State. + * + * @retval #Power_ACTIVE returned when no transitions are in progress. + * + * @retval #Power_ENTERING_SLEEP returned during the transition to + * sleep, before sleep has occurred. + * + * @retval #Power_EXITING_SLEEP returned after wakeup, as the device is + * being transitioned back to #Power_ACTIVE. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast16_t Power_getTransitionState(void); + +/*! + * @brief Power function to be added to the application idle loop + * + * This function should be added to the application idle loop. (The method to + * do this depends upon the operating system being used.) This function + * will invoke the configured power policy function when appropriate. The + * specific policy function to be invoked is configured as the 'policyFxn' + * in the application-defined Power configuration object. + * + */ +void Power_idleFunc(void); + +/*! + * @brief Power initialization function + * + * This function initializes Power Manager internal state. + * + * @warning The application is responsible for ensuring this function is + * called prior to any other Power API. Additionally, this function must be + * be called prior to any other TI-Driver's APIs. This function is normally + * called prior to any operating system initialization. + * + * @return #Power_SOK + */ +int_fast16_t Power_init(void); + +/*! + * @brief Register a function to be called upon a specific power event + * + * This function registers a function to be called when a Power event occurs. + * Registrations and the corresponding notifications are processed in + * first-in-first-out (FIFO) order. The function registered must behave as + * described later, below. + * + * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object + * that will be used by Power to support the notification. This object could + * be dynamically allocated, or declared as a global object. This function + * will properly initialized the object's fields as appropriate; the caller + * just needs to provide a pointer to this pre-existing object. + * + * The eventTypes parameter identifies the type of power event(s) for which + * the notify function being registered is to be called. (Event identifiers are + * device specific, and defined in the device-specific Power include file. + * For example, the events for CC26XX are defined in PowerCC26XX.h.) The + * eventTypes parameter for this function call is treated as a bitmask, so + * multiple event types can be registered at once, using a common callback + * function. For example, to call the specified notifyFxn when both + * the entering deepsleep and awake from deepsleep events occur, eventTypes + * should be specified as: PowerCC26XX_ENTERING_STANDBY | + * PowerCC26XX_AWAKE_STANDBY + * + * The notifyFxn parameter specifies a callback function to be called when the + * specified Power event occurs. The notifyFxn must implement the following + * signature: + * status = notifyFxn(eventType, eventArg, clientArg); + * + * Where: eventType identifies the event being signaled, eventArg is an + * optional event-specific argument, and clientArg is an arbitrary argument + * specified by the client at registration. Note that multiple types of events + * can be specified when registering the notification callback function, + * but when the callback function is actually called by Power, only a + * single eventType will be specified for the callback (i.e., the current + * event). The status returned by the client notification function must + * be one of the following constants: Power_NOTIFYDONE if the client processed + * the notification successfully, or Power_NOTIFYERROR if an error occurred + * during notification. + * + * The clientArg parameter is an arbitrary, client-defined argument to be + * passed back to the client upon notification. This argument may allow one + * notify function to be used by multiple instances of a driver (that is, the + * clientArg can be used to identify the instance of the driver that is being + * notified). + * + * @param[in] pNotifyObj #Power_NotifyObj preallocated by caller + * + * @param[in] eventTypes event type or types + * + * @param[in] notifyFxn client's #Power_NotifyFxn function + * + * @param[in] clientArg client-specified argument to pass with + * notification + * + * @retval #Power_SOK on success. + * + * @retval #Power_EINVALIDPOINTER if either @p pNotifyObj or @p notifyFxn + * are NULL. + * + * @sa Power_unregisterNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Release a previously declared constraint + * + * This function releases a constraint that was previously declared with + * Power_setConstraint(). For example, if a device driver is starting an I/O + * transaction and wants to prohibit activation of a sleep state during the + * transaction, it uses Power_setConstraint() to declare the constraint, + * before starting the transaction. When the transaction completes, the + * driver calls this function to release the constraint, to allow the Power + * manager to once again allow transitions to sleep. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. + * + * Only one constraint can be specified with each call to this function; to + * release multiple constraints this function must be called multiple times. + * + * It is critical that clients call Power_releaseConstraint() when operational + * constraints no longer exists. Otherwise, Power may be left unnecessarily + * restricted from activating power savings. + * + * @pre Power_setConstraint() must have been called first. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the constraintId is + * valid,valid, and that the constraint count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid, and + * #Power_EFAIL if the constraint count is already zero. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); + +/*! + * @brief Release a previously declared dependency + * + * This function releases a dependency that had been previously declared upon + * a resource (by a call to Power_setDependency()). + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the resourceId is valid, + * and that the resource reference count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the resourceId is invalid, and #Power_EFAIL + * if the resource reference count is already zero. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId); + +/*! + * @brief Resets the system and causes it to reboot + * + * This function causes the system to reset and then boot up again. The impact + * this has on the existing system state such as what memory is retained is + * device-specific. Unless otherwise specified in the device-specific + * documentation, this function will trigger the most comprehensive reset of + * the system triggerable from software. + */ +void Power_reset(void); + +/*! + * @brief Declare an operational constraint + * + * Before taking certain actions, the Power Manager checks to see if the + * requested action would conflict with a client-declared constraint. If the + * action does conflict, Power will not proceed with the request. This is the + * function that allows clients to declare their constraints with Power. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. + * + * Only one constraint can be specified with each call to this function; to + * declare multiple constraints this function must be called multiple times. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the constraintId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid. + * + * @sa Power_releaseConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId); + +/*! + * @brief Declare a dependency upon a resource + * + * This function declares a dependency upon a resource. For example, if a + * UART driver needs a specific UART peripheral, it uses this function to + * declare this to the Power Manager. If the resource had been inactive, + * then Power will activate the peripheral during this function call. + * + * What is needed to make a peripheral resource 'active' will vary by device + * family. For some devices this may be a simple enable of a clock to the + * specified peripheral. For others it may also require a power on of a + * power domain. In either case, the Power Manager will take care of these + * details, and will also implement reference counting for resources and their + * interdependencies. For example, if multiple UART peripherals reside in + * a shared serial power domain, the Power Manager will power up the serial + * domain when it is first needed, and then automatically power the domain off + * later, when all related dependencies for the relevant peripherals are + * released. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the resourceId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the reseourceId is invalid. + * + * @sa Power_releaseDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_setDependency(Power_Resource resourceId); + +/*! + * @brief Set a new Power policy + * + * This function allows a new #Power_PolicyFxn function to be selected at + * runtime. + * + * @param[in] policy the new #Power_PolicyFxn function + */ +void Power_setPolicy(Power_PolicyFxn policy); + +/*! + * @brief Put the device into a shutdown state + * + * This function will transition the device into a shutdown state. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for an + * 'entering shutdown' event. The event name is device specific, and defined + * in the device-specific Power include file. For example, for CC32XX, the + * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in + * PowerCC32XX.h. Once notifications have been completed, the device shutdown + * will commence. + * + * If the device is successfully transitioned to shutdown, this function + * call will never return. Upon wakeup, the device and application will + * be rebooted (through a device reset). If the transition is not + * successful, one of the error codes listed below will be returned. + * + * On some devices a timed wakeup from shutdown can be specified, using + * the shutdownTime parameter. This enables an autonomous application reboot + * at a future time. For example, an application can go to shutdown, and then + * automatically reboot at a future time to do some work. And once that work + * is done, the application can shutdown again, for another timed interval. + * The time interval is specified via the shutdownTime parameter. (On devices + * that do not support this feature, any value specified for shutdownTime will + * be ignored.) If the specified shutdownTime is zero, or otherwise less than + * the total shutdown latency for the device, the shutdownTime parameter will + * be ignored. The shutdown latency for the device can be found in the + * device-specific Power include file. For example, for the CC32XX, this + * latency is defined in PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) + * + * @param[in] shutdownState the device-specific shutdown state + * + * @param[in] shutdownTime the amount of time (in milliseconds) to keep + * the the device in the shutdown state; this parameter is not supported on + * all device families. + * + * @retval #Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting + * shutdown. + * + * @retval #Power_EFAIL if an error occurred during client notifications. + * + * @retval #Power_EINVALIDINPUT if the shutdownState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, uint_fast32_t shutdownTime); + +/*! + * @brief Transition the device into a sleep state + * + * This function is called from the power policy when it has made a decision + * to put the device in a specific sleep state. This function returns to the + * caller (the policy function) once the device has awoken from sleep. + * + * @warning This function must be called with interrupts disabled, and + * should not be called directly by the application, or by any drivers. + * This function does not check declared constraints; the policy function + * must check constraints before calling this function to initiate sleep. + * + * @param[in] sleepState the sleep state + * + * @retval #Power_SOK on success, the device has slept and is awake again. + * + * @retval #Power_EFAIL if an error occurred during client notifications, or + * if a general failure occurred. + * + * @retval #Power_EINVALIDINPUT if the @p sleepState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState); + +/*! + * @brief Unregister previously registered notifications + * + * This function unregisters for event notifications that were previously + * registered with Power_registerNotify(). The caller must specify a pointer + * to the same notification object used during registration. + * + * @param[in] pNotifyObj The #Power_NotifyObj used with the original + * call to Power_registerNotify() + * + * @sa Power_registerNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); + +#ifdef __cplusplus +} +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#elif (DeviceFamily_ID == DeviceFamily_ID_CC3220 || DeviceFamily_ID == DeviceFamily_ID_CC3200) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + #include +#endif + +#endif /* ti_drivers_Power__include */ diff --git a/simplelink_lpf3/source/ti/drivers/Temperature.c b/simplelink_lpf3/source/ti/drivers/Temperature.c new file mode 100644 index 00000000..e73147db --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/Temperature.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== Temperature.c ======== + * + */ + +#include +#include + +#include + +/* + * ======== Temperature_getThresholdHigh ======== + */ +int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject) { + return notifyObject->thresholdHigh; +} + +/* + * ======== Temperature_getThresholdLow ======== + */ +int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject) { + return notifyObject->thresholdLow; +} + +/* + * ======== Temperature_getThresholdRange ======== + */ +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, + int16_t *thresholdHigh, + int16_t *thresholdLow) { + *thresholdHigh = notifyObject->thresholdHigh; + *thresholdLow = notifyObject->thresholdLow; +} + +/* + * ======== Temperature_getClientArg ======== + */ +uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject) { + return notifyObject->clientArg; +} + +/* + * ======== Temperature_getNotifyFxn ======== + */ +Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject) { + return notifyObject->notifyFxn; +} diff --git a/simplelink_lpf3/source/ti/drivers/Temperature.h b/simplelink_lpf3/source/ti/drivers/Temperature.h new file mode 100644 index 00000000..99c40700 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/Temperature.h @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file Temperature.h + * + * @brief Temperature driver + * + * @anchor ti_drivers_Temperature_Overview + * # Overview # + * The Temperature driver provides services related to measuring and reacting + * to the current temperature of the chip and changes to it. + * + * The two main services provided are: + * - Getting the current temperature + * - Providing notification callbacks when the temperature changes + * + * @anchor ti_drivers_Temperature_Usage + * # Usage # + * + * ## Initialisation # + * Unlike most drivers, there is only a single instance of the temperature + * driver that is always available once #Temperature_init() is called. + * #Temperature_init() should be called once before using other Temperature + * driver APIs. Subsequent #Temperature_init() calls will have no effect. + * + * ## Getting the Current Temperature # + * The most basic function of the driver is to provide the current temperature + * and return it. It is encoded as a signed integer in degrees C. + * + * ## Notifications # + * The other major function of the Temperature driver is to notify the + * application when the temperature changes and crosses an application-defined + * threshold. + * + * There are three default usecases for this: + * - High threshold. + * The application will receive a notification callback when + * currentTemperature >= thresholdHigh. + * - Low threshold. + * The application will receive a notification callback when + * currentTemperature <= thresholdLow. + * - Range threshold. + * The application will receive a notification callback when + * currentTemperature >= thresholdHigh || currentTemperature <= + * thresholdLow. This setup addresses usecases + * where a notification is required when the temperature changes by a + * certain amount regardless of whether it is up or down. Adjusting + * clock offsets based on temperature is a good example of this. + * + * ### Registering Notifications + * There are three functions that register a notification for the application: + * - #Temperature_registerNotifyHigh() + * - #Temperature_registerNotifyLow() + * - #Temperature_registerNotifyRange() + * + * Multiple notifications may be registered. The different parts of the + * application and drivers that need to respond to a temperature change do not + * need to know of one another. + * Each notification must have its own #Temperature_NotifyObj and must be + * registered individually. + * + * ### Notification Callbacks + * Once the chip temperature crosses the smallest high threshold or largest + * low threshold amongst the registered notifications, the driver will + * iterate over the entire list of registered notification and check which + * ones have triggered. Notifications that have triggered are removed from + * the list of registered notifications and thus are no longer registered. + * Their callback function is then invoked. + * + * If an application wishes to reregister a notification that just triggered + * and was unregistered, it may register it again from within the notification + * callback or another context. + * + * It is possible to determine whether the high or low threshold triggered + * the notification callback as follows: + * - currentTemperature <= thresholdTemperature: Low threshold triggered + * - currentTemperature >= thresholdTemperature: High threshold triggered + * This information is only reasonably useful when registering a notification + * with both a high and low threshold using #Temperature_registerNotifyRange(). + * Even then, the expected basic usecase only cares about the current + * temperature and adding an offset to it when registering the notification + * again. + * + * ### Unregistering Notifications + * Registered notifications are unregistered in two ways: + * - Automatically when a notification triggers + * - By calling #Temperature_unregisterNotify() + * + * Unregistered notifications may be registered again at any time. + * + * # Measured vs True Temperature + * While the driver aims to supply and act on an accurate absolute temperature, + * there will be differences between the measured vs the true temperature due + * to inherent variances in the manufacturing process. The nature of these + * differences varies by device family. + * + * Examples of such differences: + * - A constant per-chip offset between the measured and the true + * temperature + * - An temperature dependent per-chip offset between the measured and the + * true temperature + * - A variance in the measured temperature when measuring multiple times + * at the same chip temperature + * + * It is strongly recommended to read the device-specific Temperature driver + * documentation for details of the temperature sensor characteristics and + * how they might affect choices of threshold values. + * + * @anchor ti_drivers_Temperature_Synopsis + * # Synopsis # + * @anchor ti_drivers_Temperature_Synopsis_Code + * @code + * #include + * + * #define WINDOW_DELTA 10 + * + * Temperature_init(); + * + * currentTemperature = Temperature_getTemperature(); + * + * result = Temperature_registerNotifyRange(¬ifyObject, + * currentTemperature + WINDOW_DELTA, + * currentTemperature - WINDOW_DELTA, + * myNotifyFxn, + * clientArg); + * @endcode + * + * @anchor ti_drivers_Temperature_Examples + * # Examples # + * + * ## Register a High Threshold Notification # + * + * @code + * + * // The notification will trigger when the temperature reaches 40 C + * #define THRESHOLD_CUTOFF 40 + * + * #include + * + * void thresholdNotifyFxn(int16_t currentTemperature, + * int16_t thresholdTemperature, + * uintptr_t clientArg, + * Temperature_NotifyObj *notifyObject) { + * // Post a semaphore, set a flag, or otherwise act upon the temperature + * // change. + * } + * + * ... + * + * // Initialize the Temperature driver and register a notification. + * + * Temperature_init(); + * + * int_fast16_t status = Temperature_registerNotifyHigh(notifyObject, + * THRESHOLD_CUTOFF, + * thresholdNotifyFxn, + * NULL); + * + * if (status != Temperature_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * ## Register a Range Threshold Notification and Reregister in Callback # + * + * @code + * + * #define THRESHOLD_DELTA 5 + * + * #include + * + * + * void deltaNotificationFxn(int16_t currentTemperature, + * int16_t thresholdTemperature, + * uintptr_t clientArg, + * Temperature_NotifyObj *notifyObject) { + * int_fast16_t status; + * + * status = Temperature_registerNotifyRange(notifyObject, + * currentTemperature + THRESHOLD_DELTA, + * currentTemperature - THRESHOLD_DELTA, + * deltaNotificationFxn, + * NULL); + * + * if (status != Temperature_STATUS_SUCCESS) { + * while(1); + * } + * } + * + * ... + * + * // Initialize the Temperature driver and register a notification. + * + * Temperature_init(); + * + * int16_t currentTemperature = Temperature_getTemperature(); + * + * int_fast16_t status = Temperature_registerNotifyRange(notifyObject, + * currentTemperature + THRESHOLD_DELTA, + * currentTemperature - THRESHOLD_DELTA, + * deltaNotificationFxn, + * NULL); + * @endcode + */ + +#ifndef ti_drivers_Temperature__include +#define ti_drivers_Temperature__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common Temperature status code reservation offset. + * Temperature driver implementations should offset status codes with + * Temperature_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TemperatureXYZ_STATUS_ERROR0 Temperature_STATUS_RESERVED - 0 + * #define TemperatureXYZ_STATUS_ERROR1 Temperature_STATUS_RESERVED - 1 + * #define TemperatureXYZ_STATUS_ERROR2 Temperature_STATUS_RESERVED - 2 + * @endcode + */ +#define Temperature_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return Temperature_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define Temperature_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return Temperature_STATUS_ERROR if the function was not executed + * successfully. + */ +#define Temperature_STATUS_ERROR (-1) + + +/* @cond + * + * Type declaration for the notification object made separately from the + * struct definition because of the circular dependency between + * #Temperature_NotifyFxn() and #Temperature_NotifyObj. + */ +typedef struct Temperature_NotifyObj Temperature_NotifyObj; +/* @endcond */ + +/*! + * @brief Function prototype for a notification callback. + * + * @param [in] currentTemperature Current chip temperature + * + * @param [in] thresholdTemperature Temperature threshold that caused + * this notification callback. + * + * @param [in] clientArg Argument provided by the application + * during registration. + * + * @param [in/out] notifyObject The notification object that was + * registered previously. This pointer + * may be used to register the + * notification again with updated + * inputs from within the notification + * callback. + */ +typedef void (*Temperature_NotifyFxn) (int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); + +/*! + * @brief Temperature notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * #Temperature_registerNotifyHigh(), #Temperature_registerNotifyLow(), + * or #Temperature_registerNotifyRange() will take care initializing the + * internal elements appropriately. + */ +struct Temperature_NotifyObj { + List_Elem link; /*!< For placing on the notify list */ + Temperature_NotifyFxn notifyFxn; /*!< Application callback function */ + int16_t thresholdHigh; /*!< High threshold in degrees C */ + int16_t thresholdLow; /*!< Low threshold in degrees C */ + uintptr_t clientArg; /*!< Application provided arg */ + bool isRegistered; /*!< Is the notification active */ +}; + + +/*! + * @brief This function initializes the Temperature driver. + * + * This function initializes the internal state of the Temperature driver. + * It must be called before calling any other Temperature functions. Calling + * this function multiple times will only have an effect the first time. + */ +void Temperature_init(); + +/*! + * @brief Gets the current temperature in degrees C. + * + * @return Current temperature in degrees C + */ +int16_t Temperature_getTemperature(void); + +/*! + * @brief Registers a notification with a high threshold. + * + * This function registers a Temperature notification with a high threshold. + * Once the chip temperature rises above @c thresholdHigh, @c notifyFxn is + * called and the notification is automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh Threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature rises above + * @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #Temperature_STATUS_ERROR There was an error during registration. + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyHigh(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with a low threshold. + * + * This function registers a Temperature notification with a low threshold. + * Once the chip temperature falls below @c thresholdLow, @c notifyFxn is + * called and the notification is automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdLow Threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature falls below + * @c thresholdLow. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #Temperature_STATUS_ERROR There was an error during registration. + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyLow(Temperature_NotifyObj *notifyObject, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with both a high and low threshold. + * + * This function registers a Temperature notification with a high and low + * threshold. Once the chip temperature rises above @c thresholdHigh or + * falls below @c thresholdLow, @c notifyFxn is called and the notification is + * automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh High threshold temperature in degrees C + * + * @param [in] thresholdLow Low threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature falls below + * @c thresholdLow, or rises above + * @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered + * @retval #Temperature_STATUS_ERROR There was an error during registration + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyRange(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + + +/*! + * @brief Unregisters a currently registered notification. + * + * This function unregisters a currently registered notification. It should not + * be called on a @c notifyObject that is not currently registered. + * + * @param notifyObject Notification to unregister. + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * unregistered. + * @retval #Temperature_STATUS_ERROR There was an error during + * unregistration. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +int_fast16_t Temperature_unregisterNotify(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the high threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyLow(). The high threshold value returned in + * that case will be a device-specific invalid temperature. + * + * @param notifyObject Notification to get the high threshold of. + * + * @return High threshold in degrees C. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * or #Temperature_registerNotifyRange() + */ +int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the low threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyHigh(). The low threshold value returned in + * that case will be a device-specific invalid temperature. + * + * @param notifyObject Notification to get the low threshold of. + * + * @return Low threshold in degrees C. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyLow(), + * or #Temperature_registerNotifyRange() + */ +int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the high and low threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyLow() or #Temperature_registerNotifyHigh(). + * The unconfigured threshold value returned in that case will be a + * device-specific invalid temperature. + * + * @param notifyObject Notification to get the high and low threshold of. + * + * @param [out] thresholdHigh High threshold value in degrees C written back + * by this function. + * + * @param [out] thresholdLow Low threshold value in degrees C written back + * by this function. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyRange() + */ +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, + int16_t *thresholdHigh, + int16_t *thresholdLow); + +/*! + * @brief Get the application-provided clientArg of a notification. + * + * @param notifyObject Notification to get the clientArg of. + * + * @return The clientArg provided during registration. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the notifyFxn provided during registration. + * + * @param notifyObject Notification to get the notifyFxn of. + * + * @return The notifyFxn provided during registration + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Temperature__include */ diff --git a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c new file mode 100644 index 00000000..29a6e496 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== BatMonSupportLPF3.c ======== + * + */ + +/* Includes */ +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_evtull.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_pmud.h) +#include DeviceFamily_constructPath(inc/hw_types.h) + +/* Forward declarations */ +static void batMonHwiFxn(uintptr_t arg0); + +/* Globals */ + +/* HWI struct for the shared BATMON interrupt */ +static HwiP_Struct batMonHwi; + +/* Allocate memory for registered event callback functions */ +static BatMonSupportLPF3_EventCb temperatureCb = NULL; +static BatMonSupportLPF3_EventCb batteryCb = NULL; + +/* Event masks for the registered event callback functions */ +static uint32_t temperatureEventMask = 0; +static uint32_t batteryEventMask = 0; + +static bool isInitialized = false; + +//extern const BatMonSupportLPF3_Config BatMonSupportLPF3_config; + +// TODO: make this configurable +const BatMonSupportLPF3_Config BatMonSupportLPF3_config = { + .intNum = INT_CPUIRQ0, + .intPriority = (~0), + .intMux = EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB +}; + +/* + * ======== batMonHwiFxn ======== + * + * AON_PMU_COMB Interrupt + */ +static void batMonHwiFxn(uintptr_t arg0) +{ + uint32_t events = HWREG(PMUD_BASE + PMUD_O_EVENT); + + if (((events & batteryEventMask) != 0) && (batteryCb != NULL)) + { + batteryCb(events & batteryEventMask); + } + + if (((events & temperatureEventMask) != 0) && (temperatureCb != NULL)) + { + temperatureCb(events & temperatureEventMask); + } + + HwiP_clearInterrupt(BatMonSupportLPF3_config.intNum); +} + +/* + * ======== BatMonSupportLPF3_init ======== + */ +void BatMonSupportLPF3_init(void) +{ + uint32_t key; + + key = HwiP_disable(); + + if (isInitialized == false) + { + /* Claim configurable CPUIRQ as AON_PMU_COMB */ + HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ0SEL + (BatMonSupportLPF3_config.intNum - INT_CPUIRQ0) * sizeof(uint32_t)) = BatMonSupportLPF3_config.intMux; + + /* Initialise the BatMon HWI. The temperature sensor shares this + * interrupt with the battery voltage monitoring events. + */ + HwiP_Params hwiParams; + HwiP_Params_init(&hwiParams); + hwiParams.priority = BatMonSupportLPF3_config.intPriority; + hwiParams.enableInt = true; + HwiP_construct(&batMonHwi, BatMonSupportLPF3_config.intNum, batMonHwiFxn, &hwiParams); + + /* Disable all events */ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) = 0; + + /* Enable BATMON */ + HWREG(PMUD_BASE + PMUD_O_CTL) |= (PMUD_CTL_CALC_EN | PMUD_CTL_MEAS_EN); + + /* Set the combined BATMON interrupt as a wakeup source. This means the + * BATMON can bring the device out of standby when an event is + * triggered. + */ + HWREG(EVTULL_BASE + EVTULL_O_WKUPMASK) |= EVTULL_WKUPMASK_AON_PMU_COMB; + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== BatMonSupportLPF3_registerTemperatureCb ======== + */ +void BatMonSupportLPF3_registerTemperatureCb(uint32_t eventMask, BatMonSupportLPF3_EventCb callback) +{ + uint32_t key; + + key = HwiP_disable(); + + temperatureEventMask = eventMask; + temperatureCb = callback; + + HwiP_restore(key); +} + +/* + * ======== BatMonSupportLPF3_registerBatteryCb ======== + */ +void BatMonSupportLPF3_registerBatteryCb(uint32_t eventMask, BatMonSupportLPF3_EventCb callback) +{ + uint32_t key; + + key = HwiP_disable(); + + batteryEventMask = eventMask; + batteryCb = callback; + + HwiP_restore(key); +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.h b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.h new file mode 100644 index 00000000..3196ca05 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file BatMonSupportLPF3.h + * + * @brief BatMon Support layer + * + * @anchor ti_drivers_batterymonitor_BatMonSupportLPF3_Overview + * # Overview # + * The purpose of the BatMon Support layer is to provide a way for multiple + * drivers to share the the BATMON hardware resource. The BATMON provides both + * temperature and supply voltage measurements. For this reason, both the + * Temperature driver and the Battery Monitor driver depends on the BATMON + * module. + * + * Only a combined interrupt request for BATMON exists, and this needs to be + * shared by multiple drivers. + * + * The two main services provided are: + * - Initializing the BATMON module + * - Dispatching the combined BATMON interrupt (AON_PMU_COMB) to registered + * callback functions + * + * @note The BatMon Support layer is not intended to be used by the application. + * It is only intended to be used by TI drivers. + * + * @anchor ti_drivers_batterymonitor_BatMonSupportLPF3_Usage + * # Usage # + * + * ## Initialisation # + * The BatMon Support layer needs to be initialized by calling + * #BatMonSupportLPF3_init(). + * #BatMonSupportLPF3_init() should be called once before using other BatMon + * Support APIs. Subsequent #BatMonSupportLPF3_init() calls will have no + * effect. + * + * ## BATMON Event Callbacks # + * The main function of the BatMon Support layer is to dispatch the combined + * BATMON interrupt to registered callback functions when certain event flags + * are set. + * + * ### Registering Event Callbacks + * There are two functions that register an event callback: + * - #BatMonSupportLPF3_registerTemperatureCb() + * - #BatMonSupportLPF3_registerBatteryCb() + * + * Only one Temperature Callback and one Battery Callback can be registered, + * and registered callbacks cannot be unregistered. + * + * @anchor ti_drivers_batterymonitor_BatMonSupportLPF3_Synopsis + * # Synopsis # + * @anchor ti_drivers_batterymonitor_BatMonSupportLPF3_Code + * @code + * #include + * + * BatMonSupportLPF3_init(); + * + * BatMonSupportLPF3_registerTemperatureCb(PMUD_EVENT_TEMP_BELOW_LL | PMUD_EVENT_TEMP_OVER_UL, myTempCb); + * BatMonSupportLPF3_registerBatteryCb(PMUD_EVENT_BATT_BELOW_LL | PMUD_EVENT_BATT_OVER_UL, myBattCb); + * @endcode + */ +#ifndef ti_drivers_batterymonitor_BatMonSupportLPF3__include +#define ti_drivers_batterymonitor_BatMonSupportLPF3__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief BatMon Support Configuration + * + * A sample structure is shown below: + * @code + * const BatMonSupportLPF3_Config BatMonSupportLPF3_config = { + * .intNum = INT_CPUIRQ2, + * .intPriority = (~0), + * .intMux = EVTSVT_CPUIRQ2SEL_PUBID_AON_PMU_COMB, + * }; + * @endcode + */ +typedef struct +{ + uint32_t intNum; /*!< Device-specific interrupt number */ + uint32_t intPriority; /*!< Device-specific interrupt priority */ + uint32_t intMux; /*!< Device-specific interrupt muxing */ +} BatMonSupportLPF3_Config; + +/*! + * @brief Function prototype for an event callback. + * + * The callback function is responsible for clearing the event flags associated + * with the callback + * + * @param [in] eventFlags The event flags read from PMUD.EVENT masked with + * the event mask used when registering the + * callback function in + * #BatMonSupportLPF3_registerTemperatureCb() + * or #BatMonSupportLPF3_registerBatteryCb(). + */ +typedef void (*BatMonSupportLPF3_EventCb)(uint32_t eventFlags); + +/*! + * @brief This function initializes the BatMon Support layer. + * + * This function initializes the internal state of the BatMon Support layer. + * It must be called before calling any other BatMon Support functions. + * Subsequent calls to this function have no effect. + */ +extern void BatMonSupportLPF3_init(void); + +/*! + * @brief This function registers a callback dedicated for the Temperature driver + * + * @note This function does not set PMUD.EVENTMASK. The @c eventMask parameter + * is only used as a filter for when to to call the callback function defined + * by @c callback. The calling function is responsible to setting up BATMON to + * actually generate the desired events. + * + * @param [in] eventMask Event mask used as filter for when to call the + * callback function defined by @c callback. + * In the AON_PMU_COMB ISR the value of PMUD.EVENT + * will be AND'ed with @c eventMask, if the result + * is non-zero the callback function will be + * called. + * + * @param [in] callback The callback function that is called by the + * AON_PMU_COMB ISR if any of the event flags + * defined by @c eventMask is set in PMUD.EVENT. + */ +extern void BatMonSupportLPF3_registerTemperatureCb(uint32_t eventMask, BatMonSupportLPF3_EventCb callback); + +/*! + * @brief This function registers a callback dedicated for the Battery Monitor + * driver + * + * @note This function does not set PMUD.EVENTMASK. The @c eventMask parameter + * is only used as a filter for when to to call the callback function defined + * by @c callback. The calling function is responsible to setting up BATMON to + * actually generate the desired events. + * + * @param [in] eventMask Event mask used as filter for when to call the + * callback function defined by @c callback. + * In the AON_PMU_COMB ISR the value of PMUD.EVENT + * will be AND'ed with @c eventMask, if the result + * is non-zero the callback function will be + * called. + * + * @param [in] callback The callback function that is called by the + * AON_PMU_COMB ISR if any of the event flags + * defined by @c eventMask is set in PMUD.EVENT. + */ +extern void BatMonSupportLPF3_registerBatteryCb(uint32_t eventMask, BatMonSupportLPF3_EventCb callback); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_batterymonitor_BatMonSupportLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c new file mode 100644 index 00000000..0ed7165b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== BatteryMonitorLPF3.c ======== + * + */ + +/* Includes */ +#include +#include + +#include + +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_evtull.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_pmud.h) +#include DeviceFamily_constructPath(inc/hw_pmctl.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +/* Macros */ +#define BATMON_VOLTAGE_MAX (7996) +#define BATMON_VOLTAGE_MIN (0) + +#define INVALID_VOLTAGE_MAX BATMON_VOLTAGE_MAX +#define INVALID_VOLTAGE_MIN BATMON_VOLTAGE_MIN + +/* Forward declarations */ +static void walkNotifyList(uint16_t currentVoltage); +static void setNextThresholds(void); +static void batteryEventCb(uint32_t eventMask); +static void updateThresholds(uint16_t thresholdHigh, uint16_t thresholdLow); +static uint32_t millivoltsToCode(uint16_t voltageMillivolts); +static void setBatLowerLimit(uint16_t thresholdLow); +static void setBatUpperLimit(uint16_t thresholdHigh); +static void enableBatLowerLimit(void); +static void enableBatUpperLimit(void); +static void disableBatLowerLimit(void); +static void disableBatUpperLimit(void); +static void clearEventFlags(void); + +/* Globals */ + +/* Global list that stores all registered notifications */ +static List_List notificationList; + +/* Current threshold values. These should always reflect the state of the + * BATMON registers without the need to read them out, and convert to + * millivolts. + */ +static volatile uint16_t currentThresholdHigh = INVALID_VOLTAGE_MAX; +static volatile uint16_t currentThresholdLow = INVALID_VOLTAGE_MIN; + +static bool isInitialized = false; + +/* + * ======== millivoltsToCode ======== + */ +static uint32_t millivoltsToCode(uint16_t voltageMillivolts) +{ + /* Add fractional bits */ + uint32_t voltageCode = voltageMillivolts << PMUD_BAT_INT_S; + + /* Convert from millivolts to volts */ + voltageCode = Math_divideBy1000(voltageCode); + + /* Mask result */ + voltageCode &= (PMUD_BAT_INT_M | PMUD_BAT_FRAC_M); + + return voltageCode; +} + +/* + * ======== setBatLowerLimit ======== + */ +static void setBatLowerLimit(uint16_t thresholdLow) +{ + uint32_t voltageCode = millivoltsToCode(thresholdLow); + + HWREG(PMUD_BASE + PMUD_O_BATTLL) = voltageCode; + + currentThresholdLow = thresholdLow; +} + +/* + * ======== setBatUpperLimit ======== + */ +static void setBatUpperLimit(uint16_t thresholdHigh) +{ + uint32_t voltageCode = millivoltsToCode(thresholdHigh); + + HWREG(PMUD_BASE + PMUD_O_BATTUL) = voltageCode; + + currentThresholdHigh = thresholdHigh; +} + +/* + * ======== enableBatLowerLimit ======== + */ +static void enableBatLowerLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) |= PMUD_EVENTMASK_BATT_BELOW_LL_MASK; +} + +/* + * ======== enableBatUpperLimit ======== + */ +static void enableBatUpperLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) |= PMUD_EVENTMASK_BATT_OVER_UL_MASK; +} + +/* + * ======== disableBatLowerLimit ======== + */ +static void disableBatLowerLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) &= ~PMUD_EVENTMASK_BATT_BELOW_LL_MASK; +} + +/* + * ======== disableBatUpperLimit ======== + */ +static void disableBatUpperLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) &= ~PMUD_EVENTMASK_BATT_OVER_UL_MASK; +} + +/* + * ======== clearEventFlags ======== + */ +static void clearEventFlags(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENT) &= (PMUD_EVENT_BATT_BELOW_LL | PMUD_EVENT_BATT_OVER_UL); +} + +/* + * ======== setNextThresholds ======== + */ +static void setNextThresholds(void) +{ + List_Elem *notifyLink; + int16_t nextThresholdHigh = INVALID_VOLTAGE_MAX; + int16_t nextThresholdLow = INVALID_VOLTAGE_MIN; + uint32_t key; + + key = HwiP_disable(); + + /* Starting with the head of the list, keep track of the smallest high + * threshold and largest low threshold. + */ + notifyLink = List_head(¬ificationList); + + while (notifyLink != NULL) + { + BatteryMonitor_NotifyObj *notifyObject = (BatteryMonitor_NotifyObj *)notifyLink; + + nextThresholdHigh = Math_MIN(nextThresholdHigh, notifyObject->thresholdHigh); + nextThresholdLow = Math_MAX(nextThresholdLow, notifyObject->thresholdLow); + + notifyLink = List_next(notifyLink); + } + + /* Now that we have found the next upper and lower thresholds, set them. + * These could be INVALID_VOLTAGE_MAX and/or INVALID_VOLTAGE_MIN + * if the list is empty or only high/low notifications were registered. + */ + updateThresholds(nextThresholdHigh, nextThresholdLow); + + HwiP_restore(key); +} + +/* + * ======== walkNotifyList ======== + */ +static void walkNotifyList(uint16_t currentVoltage) +{ + List_Elem *notifyLink = List_head(¬ificationList); + + /* If the notification list is empty, the head pointer will be + * NULL and the while loop will never execute the statement. + */ + while (notifyLink != NULL) + { + BatteryMonitor_NotifyObj *notifyObject = (BatteryMonitor_NotifyObj *)notifyLink; + + /* Buffer the next link in case the notification triggers. + * Without buffering, we might skip list entries if the + * notifyObject is freed or re-registered and the notifyObject->link.next + * pointer is altered. + */ + List_Elem *notifyLinkNext = List_next(notifyLink); + + /* If the current voltage is below this notification's low + * threshold or above its high threshold, remove it from the list and + * call the callback fxn + */ + if (currentVoltage <= notifyObject->thresholdLow || currentVoltage >= notifyObject->thresholdHigh) + { + + /* Choose the threshold to provide to the notifyFxn based on the + * thresholds and the current voltage. + */ + uint16_t threshold = (currentVoltage <= notifyObject->thresholdLow) ? notifyObject->thresholdLow + : notifyObject->thresholdHigh; + + List_remove(¬ificationList, notifyLink); + notifyObject->isRegistered = false; + + notifyObject->notifyFxn(currentVoltage, threshold, notifyObject->clientArg, notifyObject); + } + + notifyLink = notifyLinkNext; + } +} + +/* + * ======== updateThresholds ======== + */ +static void updateThresholds(uint16_t thresholdHigh, uint16_t thresholdLow) +{ + if (thresholdHigh < currentThresholdHigh) + { + setBatUpperLimit(thresholdHigh); + enableBatUpperLimit(); + } + + if (thresholdLow > currentThresholdLow) + { + setBatLowerLimit(thresholdLow); + enableBatLowerLimit(); + } +} + +/* + * ======== batteryEventCb ======== + * + * BATMON interrupt triggered on high or low battery event + */ +static void batteryEventCb(uint32_t eventMask) +{ + /* Get the current voltage */ + uint16_t currentVoltage = BatteryMonitor_getVoltage(); + + /* Only walk through notify list if the current voltage is actually above the high threshold or below the low + * threshold. */ + if (currentVoltage <= currentThresholdLow || currentVoltage >= currentThresholdHigh) + { + setBatUpperLimit(INVALID_VOLTAGE_MAX); + disableBatUpperLimit(); + + setBatLowerLimit(INVALID_VOLTAGE_MIN); + disableBatLowerLimit(); + + /* Walk the notification list and issue any callbacks that have triggered + * at the current voltage. + */ + walkNotifyList(currentVoltage); + + /* Walk the queue another time to find and set the next set of thresholds. + */ + setNextThresholds(); + } + + /* Clear event flags. */ + clearEventFlags(); +} + +/* + * ======== BatteryMonitor_init ======== + */ +void BatteryMonitor_init(void) +{ + uint32_t key; + + key = HwiP_disable(); + + if (isInitialized == false) + { + BatMonSupportLPF3_init(); + BatMonSupportLPF3_registerBatteryCb((PMUD_EVENT_BATT_BELOW_LL | PMUD_EVENT_BATT_OVER_UL), batteryEventCb); + + /* Wait until first measurement is ready to prevent BatteryMonitor_getVoltage + * returning an invalid value. + */ + while ((HWREG(PMUD_BASE + PMUD_O_BATUPD) & PMUD_BATUPD_STA_M) != PMUD_BATUPD_STA_M) {} + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== BatteryMonitor_getVoltage ======== + */ +uint16_t BatteryMonitor_getVoltage(void) +{ + /* The voltage on LPF3 is stored in a 32-bit register + * containing a 3-bit unsigned integer part and a 8-bit unsigned fractional + * part. + */ + + /* Voltage in 3.8 fixed-point format (in Volts) */ + uint32_t voltage = HWREG(PMUD_BASE + PMUD_O_BAT) & (PMUD_BAT_INT_M | PMUD_BAT_FRAC_M); + + /* Convert to mV by multiplying by 1000 */ + voltage *= 1000; + + /* Round to nearest integer and discard fractional part */ + voltage = (voltage + (1 << (PMUD_BAT_INT_S - 1))) >> PMUD_BAT_INT_S; + + return voltage; +} + +/* + * ======== BatteryMonitor_registerNotifyHigh ======== + */ +int_fast16_t BatteryMonitor_registerNotifyHigh(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdHigh, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = INVALID_VOLTAGE_MIN; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return BatteryMonitor_STATUS_SUCCESS; +} + +/* + * ======== BatteryMonitor_registerNotifyLow ======== + */ +int_fast16_t BatteryMonitor_registerNotifyLow(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdLow, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = INVALID_VOLTAGE_MAX; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return BatteryMonitor_STATUS_SUCCESS; +} + +/* + * ======== BatteryMonitor_registerNotifyRange ======== + */ +int_fast16_t BatteryMonitor_registerNotifyRange(BatteryMonitor_NotifyObj *notifyObject, + uint16_t thresholdHigh, + uint16_t thresholdLow, + BatteryMonitor_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return BatteryMonitor_STATUS_SUCCESS; +} + +/* + * ======== BatteryMonitor_unregisterNotify ======== + */ +int_fast16_t BatteryMonitor_unregisterNotify(BatteryMonitor_NotifyObj *notifyObject) +{ + uint32_t key; + + key = HwiP_disable(); + + if (notifyObject->isRegistered == true) + { + /* Remove the notification from the list */ + List_remove(¬ificationList, &(notifyObject->link)); + + notifyObject->isRegistered = false; + } + + /* Find the next set of thresholds and update the registers */ + setNextThresholds(); + + HwiP_restore(key); + + return BatteryMonitor_STATUS_SUCCESS; +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.h b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.h new file mode 100644 index 00000000..fa2c00e3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatteryMonitorLPF3.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file BatteryMonitorLPF3.h + * + * @brief Battery Monitor driver implementation for the LPF3 family + * + * The Battery Monitor driver on LPF3 is a part of the battery monitoring + * system in the Always On domain (AON). It periodically takes measurements of + * the supply voltage of the device and will issue interrupts if the configured + * upper limit or lower limit is crossed. + * + * # Supply Voltage Resolution + * The battery monitoring system on LPF3 has a resolution of 1/256 V (around + * 3.91 mV). The #BatteryMonitor_getVoltage() function will round the voltage + * to the nearest mV. For example, if the supply voltage is measured to be + * 2003.91 mV, then #BatteryMonitor_getVoltage() will return 2004. + * + * # Standby Power Mode Behavior # + * The supply voltage measurement remains active in standby power mode. + * The interrupt used by the battery monitor module is capable of bringing the + * device out of standby and into active mode to handle it. That means that + * an application will not miss a change in supply voltage just because the device + * has transitioned to standby power mode. + * While in standby, the supply voltage will only be sampled during a VDDR + * recharge pulse. This means that the sampling frequency in standby will be + * determined by the temperature as leakage increases with temperature and + * requires more frequent recharging of VDDR. + */ + +#ifndef ti_drivers_batterymonitor_BatteryMonitorLPF3__include +#define ti_drivers_batterymonitor_BatteryMonitorLPF3__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_batterymonitor_BatteryMonitorLPF3__include */ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h new file mode 100644 index 00000000..f701d5b0 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ClockP.h + * + * @brief Clock interface for the RTOS Porting Interface + * + * The ClockP module can be used to schedule functions that run at intervals + * specified in the underlying kernel's system ticks. ClockP instances are + * one-shot. The one-shot function will be run once + * after the specified period has elapsed since calling ClockP_start(). + * + * The ClockP module can also be used to obtain the period of the kernel's + * system tick in microseconds. This is useful for determining the number of + * ticks needed for setting a Clock object's period. + * + * When using the TI-RTOS kernel, ClockP functions are run at software + * interrupt level. With FreeRTOS, the ClockP functions are run by a timer + * service task with priority configured by the application. + * + * A common use case is to post a semaphore in the clock function. There is a + * specific API for this: Semaphore_postFromClock(). This must be used in a + * clock function (instead of Semaphore_post). + * + * ============================================================================ + */ + +#ifndef ti_dpl_ClockP__include +#define ti_dpl_ClockP__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Prototype for a ClockP function. + */ +typedef void (*ClockP_Fxn)(uintptr_t arg); + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * ClockP object. + * + * nortos: 32 (biggest of the HW-specific ClockP instance structs) + * SysBIOS: 36 + * Zephyr: Modified to match size of ClockP_Obj + */ +#define ClockP_STRUCT_SIZE (sizeof(struct k_timer) + \ + sizeof(ClockP_Fxn) + sizeof(uintptr_t) + \ + sizeof(uint32_t) * 2) + sizeof(bool) + +/*! + * @brief ClockP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific ClockP objects. + */ +typedef union ClockP_Struct { + uint32_t dummy; /*!< Align object */ + char data[ClockP_STRUCT_SIZE]; +} ClockP_Struct; + +/*! + * @brief Frequency-in-hertz struct + */ +typedef struct { + uint32_t hi; /*!< most significant 32-bits of frequency */ + uint32_t lo; /*!< least significant 32-bits of frequency */ +} ClockP_FreqHz; + +/*! + * @brief Status codes for ClockP APIs + */ +typedef enum { + ClockP_OK = 0, + ClockP_FAILURE = -1 +} ClockP_Status; + +/*! + * @brief Opaque client reference to an instance of a ClockP + * + * A ClockP_Handle returned from the ::ClockP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::ClockP_start, + * ::ClockP_stop, etc.). + */ +typedef void *ClockP_Handle; + +#define ClockP_handle(x) ((ClockP_Handle)(x)) + +extern uint32_t ClockP_tickPeriod; + +/*! + * @brief Basic ClockP Parameters + * + * Structure that contains the parameters passed into ::ClockP_create + * when creating a ClockP instance. The ::ClockP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The ClockP default parameters are noted in + * ClockP_Params_init. + * The default startFlag is false, meaning the user will have to call + * ClockP_start(). If startFlag is true, the clock instance will be + * started automatically when it is created. + * + * The default value of period is 0, indicating a one-shot clock object. + * A non-zero period indicates the clock function will be called + * periodically at the period rate (in system clock ticks), after the + * clock is initially started and set to expire with the 'timeout' + * argument. + */ +typedef struct { + bool startFlag; /*!< Start immediately after instance is created. */ + uint32_t period; /*!< Period of clock object. */ + uintptr_t arg; /*!< Argument passed into the clock function. */ +} ClockP_Params; + + +/*! + * @brief Function to construct a clock object. + * + * @param clockP Pointer to ClockP_Struct object. + * @param timeout The startup timeout, if supported by the RTOS. + * @param clockFxn Function called when timeout or period expires. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error + */ +extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, + ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to destruct a clock object + * + * @param clockP Pointer to a ClockP_Struct object that was passed to + * ClockP_construct(). + * + * @return + */ +extern void ClockP_destruct(ClockP_Struct *clockP); + +/*! + * @brief Function to create a clock object. + * + * @param clockFxn Function called when timeout or period expires. + * @param timeout The startup timeout, if supported by the RTOS. + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::ClockP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error. This handle can + * be passed to ClockP_start() + */ +extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to delete a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_delete(ClockP_Handle handle); + +/*! + * @brief Get CPU frequency in Hz + * + * @param freq Pointer to the FreqHz structure + */ +extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); + +/*! + * @brief Get the system tick period in microseconds. + * + * @return The kernel's system tick period in microseconds. + */ +extern uint32_t ClockP_getSystemTickPeriod(); + +/*! + * @brief Get the current tick value + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 32 bits. + * + * @return Time in system clock ticks + */ +extern uint32_t ClockP_getSystemTicks(); + +/*! + * @brief Get number of ClockP tick periods expected to expire between + * now and the next interrupt from the timer peripheral + * + * Returns the number of ClockP tick periods that are expected to expore + * between now and the next interrupt from the timer peripheral. + * + * Used internally by PowerCC26XX module + * + * @return count in ticks + */ +extern uint32_t ClockP_getTicksUntilInterrupt(); + +/*! + * @brief Get timeout of clock instance. + * + * Returns the remaining time in clock ticks if the instance has + * been started. If the clock is not active, the initial timeout value + * is returned. + * + * @return remaining timeout in clock ticks. + * + * Cannot change the initial timeout if the clock has been started. + */ +extern uint32_t ClockP_getTimeout(ClockP_Handle handle); + +/*! + * @brief Determine if a clock object is currently active (i.e., running) + * + * Returns true if the clock object is currently active, otherwise + * returns false. + * + * @return active state + */ +extern bool ClockP_isActive(ClockP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * - arg: 0 + * + * @param params Pointer to the instance configuration parameters. + */ +extern void ClockP_Params_init(ClockP_Params *params); + +/*! + * @brief Set the initial timeout + * + * @param timeout Initial timeout in ClockP ticks + * + * Cannot change the initial timeout if the clock has been started. + */ +extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to start a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_start(ClockP_Handle handle); + +/*! + * @brief Function to stop a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * It is ok to call ClockP_stop() for a clock that has not been started. + * + * @return Status of the functions + * - ClockP_OK: Stopped the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern void ClockP_stop(ClockP_Handle handle); + +extern void ClockP_timestamp(ClockP_Handle handle); + +/*! + * @brief Set delay in microseconds + * + * @param usec A duration in micro seconds + * + * @return ClockP_OK + */ +extern void ClockP_usleep(uint32_t usec); + +/*! + * @brief Set delay in seconds + * + * @param sec A duration in seconds + * + * @return ClockP_OK + */ +extern void ClockP_sleep(uint32_t sec); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_ClockP__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dpl/DebugP.h b/simplelink_lpf3/source/ti/drivers/dpl/DebugP.h new file mode 100644 index 00000000..e7def8b6 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/DebugP.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DebugP.h + * + * @brief Debug support + * + * The DebugP module allows application to do logging and assert checking. + * + * DebugP_assert calls can be added into code. If the code + * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + * + * This module sits on top of the assert checking of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * Similarly, DebugP_logN calls can be added into code. If the code + * is compiled with the compiler define DebugP_LOG_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_LOG_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + + * This module sits on top of the logging of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * ============================================================================ + */ + +#ifndef ti_dpl_DebugP__include +#define ti_dpl_DebugP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif + +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#if DebugP_ASSERT_ENABLED +extern void _DebugP_assert(int expression, const char *file, int line); +/*! + * @brief Assert checking function + * + * If the expression is evaluated to true, the API does nothing. + * If it is evaluated to false, the underlying RTOS port implementation + * handles the assert via its mechanisms. + * + * @param expression Expression to evaluate + */ +#define DebugP_assert(expression) (_DebugP_assert(expression, \ + __FILE__, __LINE__)) +#else +#define DebugP_assert(expression) +#endif + +#if DebugP_LOG_ENABLED +/*! + * @brief Debug log function with 0 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + */ +extern void DebugP_log0(const char *format); + +/*! + * @brief Debug log function with 1 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + */ +extern void DebugP_log1(const char *format, uintptr_t p1); + +/*! + * @brief Debug log function with 2 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + */ +extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); + +/*! + * @brief Debug log function with 3 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + */ +extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); + +/*! + * @brief Debug log function with 4 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + * @param p4 fourth parameter to format string + */ +extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); +#else +#define DebugP_log0(format) +#define DebugP_log1(format, p1) +#define DebugP_log2(format, p1, p2) +#define DebugP_log3(format, p1, p2, p3) +#define DebugP_log4(format, p1, p2, p3, p4) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_DebugP__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dpl/HwiP.h b/simplelink_lpf3/source/ti/drivers/dpl/HwiP.h new file mode 100644 index 00000000..d0bd73aa --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/HwiP.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file HwiP.h + * + * @brief Hardware Interrupt module for the RTOS Porting Interface + * + * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order + * of the HwiP_restore calls, must be in reversed order. For example: + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_HwiP__include +#define ti_dpl_HwiP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * HwiP object. + * + * nortos: 12 + * SysBIOS: 28 + */ +#define HwiP_STRUCT_SIZE (28) + +/*! + * @brief HwiP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS + * specific HwiP objects. + */ +typedef union HwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[HwiP_STRUCT_SIZE]; +} HwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a HwiP + * + * A HwiP_Handle returned from the ::HwiP_create represents that instance. + */ +typedef void *HwiP_Handle; + +/*! + * @brief Status codes for HwiP APIs + */ +typedef enum { + HwiP_OK = 0, + HwiP_FAILURE = -1 +} HwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*HwiP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic HwiP Parameters + * + * Structure that contains the parameters passed into ::HwiP_create + * when creating a HwiP instance. The ::HwiP_Params_init function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The HwiP default parameters are noted in + * HwiP_Params_init. + * + * Parameter enableInt specifies if the interrupt should be enabled + * upon creation of the HwiP object. The default is true. + */ +typedef struct { + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority. */ + bool enableInt; /*!< Enable interrupt on creation. */ +} HwiP_Params; + +/*! + * @brief Interrupt number posted by SwiP + * + * The SwiP module needs its scheduler to run at key points in SwiP + * processing. This is accomplished via an interrupt that is configured + * at the lowest possible interrupt priority level and is plugged with + * the SwiP scheduler. This interrupt must be the *only* interrupt at + * that lowest priority. SwiP will post this interrupt whenever its + * scheduler needs to run. + * + * The default value for your device should suffice, but if a different + * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum + * can be assigned with this interrupt (early on, before HwiPs are created + * and before any SwiP gets posted). + */ +extern int HwiP_swiPIntNum; + +/*! + * @brief Function to construct a hardware interrupt object. + * + * @param hwiP Pointer to HwiP_Struct object. + * @param interruptNum Interrupt Vector Id + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params); + +/*! + * @brief Function to destruct a hardware interrupt object + * + * @param hwiP Pointer to a HwiP_Struct object that was passed to + * HwiP_construct(). + * + * @return + */ +extern void HwiP_destruct(HwiP_Struct *hwiP); + +/*! + * @brief Function to clear a single interrupt + * + * @param interruptNum interrupt number to clear + */ +extern void HwiP_clearInterrupt(int interruptNum); + +/*! + * @brief Function to create an interrupt on CortexM devices + * + * @param interruptNum Interrupt Vector Id + * + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, + HwiP_Params *params); + +/*! + * @brief Function to delete an interrupt on CortexM devices + * + * @param handle returned from the HwiP_create call + * + * @return + */ +extern void HwiP_delete(HwiP_Handle handle); + +/*! + * @brief Function to disable interrupts to enter a critical region + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to HwiP_restore to re-enable interrupts. + */ +extern uintptr_t HwiP_disable(void); + +/*! + * @brief Function to enable interrupts + */ +extern void HwiP_enable(void); + +/*! + * @brief Function to disable a single interrupt + * + * @param interruptNum interrupt number to disable + */ +extern void HwiP_disableInterrupt(int interruptNum); + +/*! + * @brief Function to enable a single interrupt + * + * @param interruptNum interrupt number to enable + */ +extern void HwiP_enableInterrupt(int interruptNum); + +/*! + * @brief Function to return a status based on whether it is in an interrupt + * context. + * + * @return A status: indicating whether the function was called in an + * ISR (true) or at thread level (false). + */ +extern bool HwiP_inISR(void); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - arg: 0 + * - priority: ~0 + * - enableInt: true + * + * @param params Pointer to the instance configuration parameters. + */ +extern void HwiP_Params_init(HwiP_Params *params); + +/*! + * @brief Function to plug an interrupt vector + * + * @param interruptNum ID of interrupt to plug + * @param fxn ISR that services plugged interrupt + */ +extern void HwiP_plug(int interruptNum, void *fxn); + +/*! + * @brief Function to generate an interrupt + * + * @param interruptNum ID of interrupt to generate + */ +extern void HwiP_post(int interruptNum); + +/*! + * @brief Function to restore interrupts to exit a critical region + * + * @param key return from HwiP_disable + */ +extern void HwiP_restore(uintptr_t key); + +/*! + * @brief Function to overwrite HwiP function and arg + * + * @param hwiP handle returned from the HwiP_create or construct call + * @param fxn pointer to ISR function + * @param arg argument to ISR function + */ +extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); + +/*! + * @brief Function to set the priority of a hardware interrupt + * + * @param interruptNum id of the interrupt to change + * @param priority new priority + */ +extern void HwiP_setPriority(int interruptNum, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_HwiP__include */ diff --git a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c new file mode 100644 index 00000000..47f5fa0e --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c @@ -0,0 +1,1226 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC23X0.c ======== + */ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_clkctl.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_evtull.h) +#include DeviceFamily_constructPath(inc/hw_ckmd.h) +#include DeviceFamily_constructPath(inc/hw_rtc.h) +#include DeviceFamily_constructPath(inc/hw_systim.h) +#include DeviceFamily_constructPath(inc/hw_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_pmud.h) +#include DeviceFamily_constructPath(inc/hw_sys0.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/hapi.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/lrfd.h) +#include DeviceFamily_constructPath(driverlib/pmctl.h) +#include DeviceFamily_constructPath(cmsis/core/cmsis_compiler.h) + +/* Forward declarations */ +int_fast16_t PowerCC23X0_notify(uint_fast16_t eventType); +static void PowerCC23X0_oscillatorISR(uintptr_t arg); +static void PowerCC23X0_enterStandby(void); +static void PowerCC23X0_setDependencyCount(Power_Resource resourceId, uint8_t count); +bool PowerCC23X0_isValidResourceId(Power_Resource resourceId); +static void PowerCC23X0_startHFXT(void); +static void PowerCC23X0_hfxtCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); +static uint32_t PowerCC23X0_temperatureToRatio(int16_t temperature); +static void PowerCC23X0_updateHFXTRatio(uint32_t ratio); + +/* Externs */ +extern const PowerCC23X0_Config PowerCC23X0_config; +extern const uint_least8_t GPIO_pinLowerBound; +extern const uint_least8_t GPIO_pinUpperBound; + +/* Function Macros */ + +/* We need to define the IOC_BASE_PIN_REG address ourselves since IOC_O_IOC0 + * does not exist on CC2340R2 + */ +#define IOC_BASE_PIN_REG 0x00000100 +#define IOC_ADDR(index) (IOC_BASE + IOC_BASE_PIN_REG + (sizeof(uint32_t) * index)) + +/* Macro used to extract the resource group from a resource ID */ +#define RESOURCE_GROUP(resourceId) ((resourceId)&PowerCC23X0_PERIPH_GROUP_M) + +/* Macro used to extract the bit index shift encoded from a resource ID */ +#define RESOURCE_BIT_INDEX(resourceId) ((resourceId)&PowerCC23X0_PERIPH_BIT_INDEX_M) + +#define HFXT_COMP_MAX_TEMP (125) +#define HFXT_COMP_MIN_TEMP (-40) + +/* Type definitions */ + +/*! Type used for passing configuration information to HFXT temperature + * notification callback + */ +typedef union +{ + struct + { + int16_t delta; + int16_t threshold; + } temperature; + uint32_t value; +} PowerCC23X0_hfxtConfig; + +/* Static Globals */ + +/*! Temperature notification to compensate the HFXT */ +static Temperature_NotifyObj PowerCC23X0_hfxtCompNotifyObj = {0}; + +/*! Temperature compensation coefficients for HFXT */ +static struct +{ + int32_t P0; + int32_t P1; + int32_t P2; + int32_t P3; + uint8_t shift; +} PowerCC23X0_hfxtCompCoefficients; + +/* Global state variable to track if HFXT compensation is enabled or not. + * It is used to check whether temperature notifications should be re-enabled + * after an update or not, in case compensation has been asynchronously disabled + */ +static bool PowerCC23X0_hfxtCompEnabled = false; + +/* Array to maintain constraint reference counts */ +static uint8_t constraintCounts[PowerCC23X0_NUMCONSTRAINTS]; + +/* Mask of Power constraints for quick access */ +static uint32_t constraintMask = 0; + +/* Arrays to maintain resource dependency reference counts. + * Each resource group will have an array associated with it, and the arrays can + * be indexed using the bit index shift value encoded in the resource ID. + */ +static uint8_t resourceCountsClkctl0[PowerCC23X0_NUMRESOURCES_CLKCTL0]; +static uint8_t resourceCountsLrfd[PowerCC23X0_NUMRESOURCES_LRFD]; + +/* Keeps track of the configured Power policy. Power_idleFunc() will not run + * the policy if this is set to NULL + */ +static Power_PolicyFxn policyFxn = NULL; + +/* Is the Power policy enabled? */ +static bool isPolicyEnabled = false; + +/* Has the Power driver been initialized */ +static bool isInitialized = false; + +/* Power state of the system. Idle, active, standby, etc */ +static uint8_t powerState = Power_ACTIVE; + +/* Event notification list */ +static List_List notifyList; + +/* Interrupt for handling clock switching */ +static HwiP_Struct ckmHwi; + +/* Non-static Globals */ + +/* Interrupt for ClockP and Power policy */ +HwiP_Struct clockHwi; + +/* ****************** Power APIs ******************** */ + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + /* If this function has already been called, just return */ + if (isInitialized) + { + return Power_SOK; + } + + isInitialized = true; + + isPolicyEnabled = PowerCC23X0_config.policyFxn != NULL; + + policyFxn = PowerCC23X0_config.policyFxn; + + /* Construct the CKM hwi responsible for oscillator related events. + * Since there is no dedicated CKM interrupt line, we need to mux one of + * the configurable lines to the CKM. + * CPUIRQ3 is dedicated to this purpose. + */ + HwiP_construct(&ckmHwi, INT_CPUIRQ3, PowerCC23X0_oscillatorISR, NULL); + + HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = EVTSVT_CPUIRQ3SEL_PUBID_AON_CKM_COMB; + + /* Enable a selection of CKM signals as interrupt sources. For now, + * we will stick to LKCLKGOOD and AMPSETTLED since those are related to existing + * notifications. + */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_AMPSETTLED | CKMD_IMASK_HFXTFAULT; + + HwiP_enableInterrupt(INT_CPUIRQ3); + + /* Use RTC channel 0 in compare mode. Channel 1 could be used for other + * purposes. + */ + HWREG(RTC_BASE + RTC_O_IMSET) = RTC_IMSET_EV0_M; + + /* Configure RTC to halt when CPU stopped during debug */ + HWREG(RTC_BASE + RTC_O_EMU) = RTC_EMU_HALT_STOP; + + /* Configure SysTimer to halt when CPU stopped during debug. The setting + * is sync'd from RTC_EMU on each wakeup from standby. + */ + HWREG(SYSTIM_BASE + SYSTIM_O_EMU) = SYSTIM_EMU_HALT_STOP; + + /* Start HFXT */ + PowerCC23X0_startHFXT(); + + /* Enable tracking loop with HFXT as reference. This will automatically + * calibrate LFOSC against HFXT whenever HFXT is enabled; usually after + * waking up from standby. + * This is needed to ensure fast HFXT startup and a reasonably accurate + * LFOSC frequency. + */ + HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) |= CKMD_HFTRACKCTL_EN_M | CKMD_HFTRACKCTL_REFCLK_HFXT; + + /* Enable GPIO and RTC standby wakeup sources */ + HWREG(EVTULL_BASE + EVTULL_O_WKUPMASK) = EVTULL_WKUPMASK_AON_IOC_COMB_M | EVTULL_WKUPMASK_AON_RTC_COMB_M; + + return Power_SOK; +} + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool wasPolicyEnabled = isPolicyEnabled; + + isPolicyEnabled = false; + + return wasPolicyEnabled; +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + isPolicyEnabled = true; +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + policyFxn = policy; +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return constraintMask; +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(Power_Resource resourceId) +{ + DebugP_assert(PowerCC23X0_isValidResourceId(resourceId)); + + uint8_t bitIndex = RESOURCE_BIT_INDEX(resourceId); + uint_fast16_t group = RESOURCE_GROUP(resourceId); + if (group == PowerCC23X0_PERIPH_GROUP_CLKCTL0) + { + return (int_fast16_t)resourceCountsClkctl0[bitIndex]; + } + else if (group == PowerCC23X0_PERIPH_GROUP_LRFD) + { + return (int_fast16_t)resourceCountsLrfd[bitIndex]; + } + + return (int_fast16_t)Power_EINVALIDINPUT; +} + +/* + * ======== Power_getConstraintCount ======== + * Get the count of constraints that are currently set on a certain + * operational transition + */ +int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId) +{ + DebugP_assert(constraintId < PowerCC23X0_NUMCONSTRAINTS); + + if (constraintId < PowerCC23X0_NUMCONSTRAINTS) + { + return (int_fast16_t)constraintCounts[constraintId]; + } + else + { + return (int_fast16_t)Power_EINVALIDINPUT; + } +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) + { + if (sleepState == PowerLPF3_STANDBY) + { + latency = PowerCC23X0_RESUMETIMESTANDBY; + } + } + else + { + if (sleepState == PowerLPF3_STANDBY) + { + latency = PowerCC23X0_TOTALTIMESTANDBY; + } + } + + return latency; +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return powerState; +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if it is not NULL. + */ +void Power_idleFunc() +{ + if (policyFxn != NULL && isPolicyEnabled == true) + { + (*(policyFxn))(); + } +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *notifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* Check for NULL pointers */ + if ((notifyObj == NULL) || (notifyFxn == NULL)) + { + status = Power_EINVALIDPOINTER; + } + else + { + notifyObj->eventTypes = eventTypes; + notifyObj->notifyFxn = notifyFxn; + notifyObj->clientArg = clientArg; + + /* Place notify object on event notification queue. Assume that + * List_Elem struct member is the first struct member in + * Power_NotifyObj. + */ + List_put(¬ifyList, (List_Elem *)notifyObj); + } + + return status; +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj *notifyObj) +{ + /* Remove notify object from its event queue */ + List_remove(¬ifyList, (List_Elem *)notifyObj); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + uintptr_t key; + + DebugP_assert(constraintId < PowerCC23X0_NUMCONSTRAINTS); + + key = HwiP_disable(); + + /* Set the specified constraint in the constraintMask for faster access */ + constraintMask |= 1 << constraintId; + + /* Increment the specified constraint count */ + constraintCounts[constraintId]++; + + HwiP_restore(key); + + return Power_SOK; +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + uintptr_t key; + + DebugP_assert(constraintId < PowerCC23X0_NUMCONSTRAINTS); + + key = HwiP_disable(); + + DebugP_assert(constraintCounts[constraintId] != 0); + + constraintCounts[constraintId]--; + + /* Only update the constraint mask if we removed the constraint entirely */ + if (constraintCounts[constraintId] == 0) + { + constraintMask &= ~(1 << constraintId); + } + + HwiP_restore(key); + + return Power_SOK; +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(Power_Resource resourceId) +{ + uint8_t previousCount; + uintptr_t key; + uint8_t bitIndex; + + DebugP_assert(PowerCC23X0_isValidResourceId(resourceId)); + + key = HwiP_disable(); + + /* Buffer previous reference count */ + previousCount = Power_getDependencyCount(resourceId); + + /* Increment reference count */ + PowerCC23X0_setDependencyCount(resourceId, previousCount + 1); + + /* If the resource was NOT activated previously ... */ + if (previousCount == 0) + { + bitIndex = RESOURCE_BIT_INDEX(resourceId); + /* Turn on the peripheral */ + switch (RESOURCE_GROUP(resourceId)) + { + case PowerCC23X0_PERIPH_GROUP_CLKCTL0: + HWREG(CLKCTL_BASE + CLKCTL_O_CLKENSET0) = 1 << bitIndex; + break; + case PowerCC23X0_PERIPH_GROUP_LRFD: + LRFDSetClockDependency(1 << bitIndex, LRFD_CLK_DEP_POWER); + break; + default: + break; + } + } + + HwiP_restore(key); + + return Power_SOK; +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId) +{ + uint8_t resourceCount; + uintptr_t key; + uint8_t bitIndex; + + DebugP_assert(PowerCC23X0_isValidResourceId(resourceId)); + + key = HwiP_disable(); + + resourceCount = Power_getDependencyCount(resourceId); + + DebugP_assert(resourceCount != 0); + + /* Decrement the reference count */ + resourceCount--; + PowerCC23X0_setDependencyCount(resourceId, resourceCount); + + /* If this was the last dependency being released.. */ + if (resourceCount == 0) + { + bitIndex = RESOURCE_BIT_INDEX(resourceId); + /* Turn off the peripheral */ + switch (RESOURCE_GROUP(resourceId)) + { + case PowerCC23X0_PERIPH_GROUP_CLKCTL0: + HWREG(CLKCTL_BASE + CLKCTL_O_CLKENCLR0) = 1 << bitIndex; + break; + case PowerCC23X0_PERIPH_GROUP_LRFD: + LRFDReleaseClockDependency(1 << bitIndex, LRFD_CLK_DEP_POWER); + break; + default: + break; + } + } + + HwiP_restore(key); + + return Power_SOK; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, uint_fast32_t shutdownTime) +{ + int_fast16_t notifyStatus; + uint32_t hwiKey; + uint8_t i; + bool ioPending = false; + + hwiKey = HwiP_disable(); + + /* Check if there is a constraint to prohibit shutdown */ + if (Power_getConstraintMask() & (1 << PowerLPF3_DISALLOW_SHUTDOWN)) + { + HwiP_restore(hwiKey); + return Power_ECHANGE_NOT_ALLOWED; + } + + /* Check whether we were transitioning to another power state */ + if (powerState != Power_ACTIVE) + { + HwiP_restore(hwiKey); + return Power_EBUSY; + } + + /* Set new transition state to entering shutdown */ + powerState = Power_ENTERING_SHUTDOWN; + + /* Signal all clients registered for pre-shutdown notification */ + notifyStatus = PowerCC23X0_notify(PowerLPF3_ENTERING_SHUTDOWN); + + for (i = GPIO_pinLowerBound; i <= GPIO_pinUpperBound; i++) + { + /* Read WUCFGSD field once and check both values. + * Use IOC3 since CC2340R2 does not have IOC0, IOC1, or IOC2. + */ + uint32_t ioShutdownConfig = HWREG(IOC_ADDR(i)) & IOC_IOC3_WUCFGSD_M; + + if ((ioShutdownConfig == IOC_IOC3_WUCFGSD_WAKE_HIGH || ioShutdownConfig == IOC_IOC3_WUCFGSD_WAKE_LOW) && + GPIOGetEventDio(i)) + { + ioPending = true; + } + } + + /* If no IO event is pending on a shutdown wakeup IO, go to shutdown */ + if (ioPending == false && notifyStatus == Power_SOK) + { + HWREG(PMCTL_BASE + PMCTL_O_SHTDWN) = PMCTL_SHTDWN_KEY_VALID; + } + + /* If shutdown succeeded, should never get here */ + + powerState = Power_ACTIVE; + + HwiP_restore(hwiKey); + + /* If we get here, failed to shutdown, return error code */ + return Power_EFAIL; +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + + /* Signal all clients registered for pre standby wakeup notification */ + status = PowerCC23X0_notify(PowerLPF3_ENTERING_STANDBY); + + /* Check for any error */ + if (status != Power_SOK) + { + powerState = Power_ACTIVE; + return status; + } + + /* Call wrapper function to ensure that R0-R3 are saved and restored before + * and after this function call. Otherwise, compilers will attempt to stash + * values on the stack while on the PSP and then restore them just after + * HapiEnterStandby() on the MSP. Which will cause wildly unexpected + * behaviour. + */ + PowerCC23X0_enterStandby(); + + /* Now that we have returned and are executing code from flash again, start + * up the HFXT using the workaround for the HFXT amplitude control ADC bias + * point + */ + PowerCC23X0_startHFXT(); + + /* Now clear the transition state before re-enabling the scheduler */ + powerState = Power_ACTIVE; + + return status; +} + +/* + * ======== Power_reset ======== + */ +void Power_reset(void) +{ + PMCTLResetSystem(); +} + +/* + * ======== PowerCC23X0_doWFI ======== + */ +void PowerCC23X0_doWFI(void) +{ + __WFI(); +} + +/* + * ======== PowerCC23X0_enterStandby ======== + * Wrapper function to ensure that R0-R3 are saved and restored before and + * after this function call. Otherwise, compilers will attempt to stash + * values on the stack while on the PSP and then restore them just after + * HapiEnterStandby() on the MSP. Which will cause wildly unexpected behaviour. + */ +void PowerCC23X0_enterStandby(void) +{ + /* Declare static volatile variable to ensure the toolchain does not use + * stack for the variable and does not optimize this memory allocation + * away. + */ + static volatile uint32_t controlPreStandby; + + /* Clear all CKM LDO SW control bits. If we do not do this before entering + * standby, the LDO will remain on in standby and consume power. We do not + * disable it earlier after turning on HFXT to avoid waiting 20us to safely + * disable it. + */ + HWREG(CKMD_BASE + CKMD_O_LDOCTL) = 0x0; + + /* Stash current CONTROL configuration to re-apply after wakeup. + * Depending on the kernel used, we could be on PSP or MSP + */ + controlPreStandby = __get_CONTROL(); + + /* Switch to MSP. HapiEnterStandby() must execute from MSP since the + * device reboots into privileged mode on MSP and HapiEnterStandby() + * assumes it will be called running on MSP. + */ + __set_CONTROL(0 << 1); + + /* - Save CPU state on MSP and MSP in CLKCTL_STBYPTR + * - Enter standby + * - Exit standby + * - Restore CPU state from MSP + * - Apply copyList + */ + HapiEnterStandby(NULL); + + /* Switch back to previous stack pointer. */ + __set_CONTROL(controlPreStandby); +} + +/* + * ======== PowerLPF3_selectLFOSC ======== + */ +void PowerLPF3_selectLFOSC(void) +{ + /* Increase LFOSC nanoamp bias current to 150nA to minimise RTN */ + HWREG(CKMD_BASE + CKMD_O_TRIM1) |= CKMD_TRIM1_NABIAS_LFOSC; + + /* Select LFOSC */ + HWREG(CKMD_BASE + CKMD_O_LFCLKSEL) = CKMD_LFCLKSEL_MAIN_LFOSC; + + /* Start LFOSC */ + HWREG(CKMD_BASE + CKMD_O_LFOSCCTL) = CKMD_LFOSCCTL_EN; + + /* Disable LFINC filter settling preventing standby */ + HWREG(CKMD_BASE + CKMD_O_LFINCCTL) &= ~CKMD_LFINCCTL_PREVENTSTBY_M; + + /* Enable LFCLKGOOD and TRACKREFLOSS. TRACKREFLOSS may occur when entering + * and exiting fake standby with the debugger attached. + */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_LFCLKGOOD | CKMD_MIS_TRACKREFLOSS_M; + + /* Disallow standby until LF clock is running. Otherwise, we will only + * vector to the ISR after we wake up from standby the next time since the + * CKM interrupt is purposefully not configured as a wakeup source. + */ + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== PowerLPF3_selectLFXT ======== + */ +void PowerLPF3_selectLFXT(void) +{ + /* Set LFINC override to 32.768 kHz. + * Will not impact RTC since the fake LF ticks will have a higher priority + * than LFINCOVR. + */ + HWREG(CKMD_BASE + CKMD_O_LFINCOVR) = 0x001E8480 | CKMD_LFINCOVR_OVERRIDE_M; + + /* Set LFCLK */ + HWREG(CKMD_BASE + CKMD_O_LFCLKSEL) = CKMD_LFCLKSEL_MAIN_LFXT; + + /* Start LFXT */ + HWREG(CKMD_BASE + CKMD_O_LFXTCTL) = CKMD_LFXTCTL_EN; + + /* Enable LFCLKGOOD */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_LFCLKGOOD; + + /* Disallow standby until LF clock is running. Otherwise, we will only + * vector to the ISR after we wake up from standby the next time since the + * CKM interrupt is purposefully not configured as a wakeup source. + */ + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== PowerCC23X0_oscillatorISR ======== + */ +static void PowerCC23X0_oscillatorISR(uintptr_t arg) +{ + uint32_t maskedStatus = HWREG(CKMD_BASE + CKMD_O_MIS); + + /* Manipulating ICLR alone does not actually do anything. The CKM_COMB + * signals are almost all level values that reset one cycle after writing to + * ICLR. We need to update the mask instead to avoid looping in the ISR + */ + HWREG(CKMD_BASE + CKMD_O_ICLR) = maskedStatus; + HWREG(CKMD_BASE + CKMD_O_IMCLR) = maskedStatus; + + if (maskedStatus & CKMD_MIS_AMPSETTLED_M) + { + PowerCC23X0_notify(PowerLPF3_HFXT_AVAILABLE); + + /* Allow standby again now that HFXT has finished starting */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + else if (maskedStatus & CKMD_MIS_HFXTFAULT_M) + { + /* If there was a fault, restart HFXT. Consider issuing a notification + * to allow logging. If we keep it like this, we could get stuck in an + * infinite loop restarting a faulty oscillator. Then again, it is not + * like there is a great way to recover from that. + */ + HWREG(CKMD_BASE + CKMD_O_HFXTCTL) &= ~CKMD_HFXTCTL_EN_M; + + /* Start up the HFXT using the workaround for the HFXT amplitude control ADC + * bias point + */ + PowerCC23X0_startHFXT(); + } + + if (maskedStatus & CKMD_MIS_LFCLKGOOD_M) + { + /* Enable LF clock monitoring */ + HWREG(CKMD_BASE + CKMD_O_LFMONCTL) = CKMD_LFMONCTL_EN; + + /* Enable LF clock loss reset while in standby */ + HWREG(PMCTL_BASE + PMCTL_O_RSTCTL) |= PMCTL_RSTCTL_LFLOSS_ARMED; + + /* Send out notification for LF clock switch */ + PowerCC23X0_notify(PowerLPF3_LFCLK_SWITCHED); + + /* Allow standby again now that we have sent out the notification */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + if (maskedStatus & CKMD_MIS_TRACKREFLOSS_M) + { + /* Disable interrupts as HFXT SWTCXO may interrupt and modify HFTRACKCTL + * with a higher priority depending on user interrupt priorities. + */ + uintptr_t key = HwiP_disable(); + + /* Disable tracking */ + HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) &= ~CKMD_HFTRACKCTL_EN_M; + + /* Re-enable tracking */ + HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) |= CKMD_HFTRACKCTL_EN_M; + + HwiP_restore(key); + + /* Re-enable TRACKREFLOSS */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_MIS_TRACKREFLOSS_M; + } +} + +/* + * ======== PowerCC23X0_startHFXT ======== + * We need to manually start HFXT because the bias voltage around HFXT swings + * is not stable across voltage or temperature because it is not remeasured + * every time HFXT starts up. + * Not manually starting HFXT can lead to: + * - HFXT never becoming available + * - Poor phase noise in the radio + */ +static void PowerCC23X0_startHFXT(void) +{ + /* Return immediately if HFXT is already enabled. Not doing so will cause + * TRACKREFLOSS when starting the LDO. This situation can arise when: + * - Waking up from fake standby. Fake standby does not shut down the HFXT, + * unlike real standby. + * - Waking up without actually entering real standby. If a wakeup source is + * pending when we reach WFI in the ROM function, the hardware will just + * turn that into a NOP instead and not run through the regular state + * machine. + */ + if ((HWREG(CKMD_BASE + CKMD_O_HFXTCTL) & CKMD_HFXTCTL_EN_M) == CKMD_HFXTCTL_EN) + { + return; + } + + /* Start LDO */ + HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_STARTCTL | CKMD_LDOCTL_START | CKMD_LDOCTL_EN); + + /* Bypass a lowpass filter that is connected to the reference voltage for + * 66us to ensure that reference has settled + */ + HapiWaitUs(66); + + /* Clear START bits */ + HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_HFXTLVLEN | CKMD_LDOCTL_EN); + + /* Force bias measurement before enabling HFXT - Set SRCSEL = BIAS. + * Enable the peak detector in the HFXT amplitude control loop to control + * RF phase jumps. + */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_PEAKDETEN_ENABLE | + CKMD_AMPADCCTL_ADCEN_ENABLE); + + /* Delay to settle PEAKDET + ADC */ + HapiWaitUs(6); + + /* Clear raw interrupt for ADCBIASUPD */ + HWREG(CKMD_BASE + CKMD_O_ICLR) = CKMD_ICLR_ADCBIASUPD; + + /* Start an SAR conversion */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) |= CKMD_AMPADCCTL_SARSTRT; + + /* Immediately prevent any SAR new conversions from starting. The one + * started above will complete though. + */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SARSTRT; + + /* Wait until HFXT-ADC BIAS measurement is done */ + while (!((HWREG(CKMD_BASE + CKMD_O_RIS) & CKMD_RIS_ADCBIASUPD_M) == CKMD_RIS_ADCBIASUPD)) {} + + /* Clear SW override of amplitude ADC */ + + /* Keep PEAKDET on */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~(CKMD_AMPADCCTL_SWOVR_M | CKMD_AMPADCCTL_ADCEN_M); + + /* Start HFXT */ + HWREG(CKMD_BASE + CKMD_O_HFXTCTL) |= CKMD_HFXTCTL_EN; + + /* Disallow standby until AMPSETTLED is true */ + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Enable the AMPSETTLED interrupt. + * Since it is a level status signal, it remains asserted when we are + * running on HFXT and cannot be cleared. + * The oscillator interrupt removes it from the interrupt mask to prevent + * repeated vectoring. + */ + HWREG(CKMD_BASE + CKMD_O_ICLR) = CKMD_ICLR_AMPSETTLED; + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMSET_AMPSETTLED; +} + +/* + * ======== PowerCC23X0_notify ======== + * Send notifications to registered clients. + * Note: Task scheduling is disabled when this function is called. + */ +int_fast16_t PowerCC23X0_notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* If queue is empty, return immediately */ + if (!List_empty(¬ifyList)) + { + /* Point to first client notify object */ + elem = List_head(¬ifyList); + + /* Walk the queue and notify each registered client of the event */ + do + { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) + { + /* Pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* Call the client's notification function */ + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)(eventType, 0, clientArg); + + /* If client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) + { + return Power_EFAIL; + } + } + + /* Get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return Power_SOK; +} + +/* + * ======== PowerCC23X0_setDependencyCount ======== + */ +void PowerCC23X0_setDependencyCount(Power_Resource resourceId, uint8_t count) +{ + uint8_t bitIndex = RESOURCE_BIT_INDEX(resourceId); + uint_fast16_t group = RESOURCE_GROUP(resourceId); + + DebugP_assert(PowerCC23X0_isValidResourceId(resourceId)); + + if (group == PowerCC23X0_PERIPH_GROUP_CLKCTL0) + { + resourceCountsClkctl0[bitIndex] = count; + } + else if (group == PowerCC23X0_PERIPH_GROUP_LRFD) + { + resourceCountsLrfd[bitIndex] = count; + } +} + +/* + * ======== PowerCC23X0_isValidResourceId ======== + */ +bool PowerCC23X0_isValidResourceId(Power_Resource resourceId) +{ + uint8_t bitIndex = RESOURCE_BIT_INDEX(resourceId); + uint_fast16_t group = RESOURCE_GROUP(resourceId); + + if (group == PowerCC23X0_PERIPH_GROUP_CLKCTL0) + { + return bitIndex < PowerCC23X0_NUMRESOURCES_CLKCTL0; + } + else if (group == PowerCC23X0_PERIPH_GROUP_LRFD) + { + return bitIndex < PowerCC23X0_NUMRESOURCES_LRFD; + } + else + { + return false; + } +} + +/* + * ======== PowerCC23X0_temperatureToRatio ======== + */ +static uint32_t PowerCC23X0_temperatureToRatio(int16_t temperature) +{ + /* Calculate unshifted ppm offset. Fixed-point coefficients are assumed to + * be set so that this computation does not overflow 32 bits in the -40, 125 + * degC range. + */ + int32_t hfxtPpmOffset = PowerCC23X0_hfxtCompCoefficients.P3 * temperature * temperature * temperature + + PowerCC23X0_hfxtCompCoefficients.P2 * temperature * temperature + + PowerCC23X0_hfxtCompCoefficients.P1 * temperature + PowerCC23X0_hfxtCompCoefficients.P0; + + /* Calculate correct frequency offset, using shifted hfxtPpmOffset. + * Frequency offset = 48000000 Hz * (hfxtPpmOffset >> shift) / 1000000 + * = 48 Hz * hfxtPpmOffset >> shift + * Do 64-bit multiplication, since this will most likely overflow 32 bits. + * Signed right-shift will result in an arithmetic shift operation. + */ +#if !(defined(__IAR_SYSTEMS_ICC__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__)) + #warning The following signed right-shift operation is implementation-defined +#endif + int32_t hfxtFreqOffset = (int32_t)((48LL * (int64_t)hfxtPpmOffset) >> PowerCC23X0_hfxtCompCoefficients.shift); + + /* Calculate temperature dependent ppm offset of the capacitor array on the + * crystal input pins, modelled as ppm(T) = 0.07 * (T - 25) + 10 + * Input frequency is assumed 48 MHz, and any potential crystal offset is + * neglected and not factored into the cap array offset calculation. + * frequency_offset(T) = 48000000 * (0.07 * (T - 25) + 10) / 1000000 + * = 3.36 * (T - 25) + 480 + * To avoid floating-point multiplication and integer division, 3.36 is + * approximated as 3523215 / 2^20 ~ 3.35999966. The error introduced by + * this approximation is negligable. + */ +#if !(defined(__IAR_SYSTEMS_ICC__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__)) + #warning The following signed right-shift operation is implementation-defined +#endif + int32_t capArrayOffset = ((3523215 * (temperature - 25)) >> 20) + 480; + + /* Calculate the actual reference input frequency to the tracking loop, + * accounting for the HFXT offset and cap array offset + */ + int32_t refFreq = 48000000 + hfxtFreqOffset + capArrayOffset; + + /* Calculate word to write to HFTRACKCTL.RATIO. Expression taken from + * register description: ratio = 24MHz / (2 * reference_frequency) * 2^24 + * 64-bit division is required, which is truncated to 32 bit + */ + uint32_t ratio = (uint32_t)(0xB71B00000000LL / (int64_t)refFreq); + + return ratio; +} + +/* + * ======== PowerCC23X0_updateHFXTRatio ======== + */ +static void PowerCC23X0_updateHFXTRatio(uint32_t ratio) +{ + /* Update HFTRACKCTL atomically */ + uintptr_t key = HwiP_disable(); + uint32_t temp = HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) & ~CKMD_HFTRACKCTL_RATIO_M; + temp |= ratio & CKMD_HFTRACKCTL_RATIO_M; + HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) = temp; + HwiP_restore(key); +} + +/* + * ======== PowerCC23X0_hfxtCompensateFxn ======== + */ +static void PowerCC23X0_hfxtCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject) +{ + uintptr_t key; + uint32_t ratio; + PowerCC23X0_hfxtConfig hfxtConfig; + hfxtConfig.value = (uint32_t)clientArg; + + /* Sanitize current temperature to fall within valid range. This ensures + * that 32-bit overflow does not occur in the ppm calculation below. + */ + if (currentTemperature > HFXT_COMP_MAX_TEMP) + { + currentTemperature = HFXT_COMP_MAX_TEMP; + } + + if (currentTemperature < HFXT_COMP_MIN_TEMP) + { + currentTemperature = HFXT_COMP_MIN_TEMP; + } + + key = HwiP_disable(); + + /* If HFXT compensation has been disabled asynchronously during execution of + * this callback then do not re-register the notification object + */ + if (PowerCC23X0_hfxtCompEnabled) + { + if (currentTemperature > hfxtConfig.temperature.threshold) + { + /* If temperature is above compensation threshold then compute a + * compensated ratio-value and update the ratio register in the + * tracking loop + */ + ratio = PowerCC23X0_temperatureToRatio(currentTemperature); + PowerCC23X0_updateHFXTRatio(ratio); + + /* Register the notification again with updated thresholds. Notification thresholds must be crossed to + * trigger, so the upper and lower limits are decreased by 1 to maintain a range of +/- delta. + */ + Temperature_registerNotifyRange(notifyObject, + currentTemperature + hfxtConfig.temperature.delta - 1, + currentTemperature - hfxtConfig.temperature.delta + 1, + PowerCC23X0_hfxtCompensateFxn, + clientArg); + } + else + { + /* If temperature is at or below compensation threshold then reset + * the tracking loop ratio to remove any compensation, and register + * a new high notification. The new limit should not be lower than + * the compensation threshold. + */ + PowerCC23X0_updateHFXTRatio(CKMD_HFTRACKCTL_RATIO_REF48M); + + Temperature_registerNotifyHigh(notifyObject, + Math_MAX(hfxtConfig.temperature.threshold, + currentTemperature + hfxtConfig.temperature.delta - 1), + PowerCC23X0_hfxtCompensateFxn, + clientArg); + } + } + + HwiP_restore(key); +} + +/* + * ======== PowerLPF3_initHFXTCompensation ======== + */ +void PowerLPF3_initHFXTCompensation(int32_t P0, + int32_t P1, + int32_t P2, + int32_t P3, + uint8_t shift, + __attribute__((unused)) bool fcfgInsertion) +{ + PowerCC23X0_hfxtCompCoefficients.P0 = P0; + PowerCC23X0_hfxtCompCoefficients.P1 = P1; + PowerCC23X0_hfxtCompCoefficients.P2 = P2; + PowerCC23X0_hfxtCompCoefficients.P3 = P3; + PowerCC23X0_hfxtCompCoefficients.shift = shift; + + /* If device offers FCFG insertion data it will be factored in here. + * Currently no device supports this. + */ +} + +/* + * ======== PowerLPF3_enableHFXTCompensation ======== + */ +void PowerLPF3_enableHFXTCompensation(int16_t tempThreshold, int16_t tempDelta) +{ + + if (PowerCC23X0_hfxtCompEnabled == false) + { + PowerCC23X0_hfxtCompEnabled = true; + + Temperature_init(); + + int16_t currentTemperature = Temperature_getTemperature(); + + PowerCC23X0_hfxtConfig config; + config.temperature.threshold = tempThreshold; + config.temperature.delta = tempDelta; + + /* Only perform temperature compensation if the temperature is above the + * set threshold. If it is not, then register a high notification on the + * threshold + */ + if (currentTemperature > tempThreshold) + { + PowerCC23X0_hfxtCompensateFxn(currentTemperature, + 0, + (uintptr_t)config.value, + &PowerCC23X0_hfxtCompNotifyObj); + } + else + { + Temperature_registerNotifyHigh(&PowerCC23X0_hfxtCompNotifyObj, + tempThreshold, + PowerCC23X0_hfxtCompensateFxn, + (uintptr_t)config.value); + } + } +} + +/* + * ======== PowerLPF3_disableHFXTCompensation ======== + */ +void PowerLPF3_disableHFXTCompensation(void) +{ + + uintptr_t key = HwiP_disable(); + if (PowerCC23X0_hfxtCompEnabled == true) + { + PowerCC23X0_hfxtCompEnabled = false; + + Temperature_unregisterNotify(&PowerCC23X0_hfxtCompNotifyObj); + + /* Update HFTRACKCTL.RATIO to reset-value */ + PowerCC23X0_updateHFXTRatio(CKMD_HFTRACKCTL_RATIO_REF48M); + } + HwiP_restore(key); +} diff --git a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h new file mode 100644 index 00000000..6a917c75 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC23X0.h + * + * @brief Power manager interface for CC23X0 devices + * + * The Power header file should be included in an application by including the + * top level header file as follows: + * @code + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This header file defines the power resources, constraints, events, sleep + * states and transition latencies for CC23X0. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC23X0_ +#define ti_drivers_power_PowerCC23X0_ + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_clkctl.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/pmctl.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! The latency to reserve for resume from STANDBY (usec). */ +#define PowerCC23X0_RESUMETIMESTANDBY 400 + +/*! The total latency to reserve for entry to and exit from STANDBY (usec). */ +#define PowerCC23X0_TOTALTIMESTANDBY 500 + +/*! The initial delay when waking from STANDBY (usec). */ +#define PowerCC23X0_WAKEDELAYSTANDBY 185 + +/* Default lower threshold for when HFXT compensation is enabled */ +#define PowerCC23X0_HFXT_THRESHOLD_TEMP_DEFAULT (-40) + +/* \cond */ +/* The control of the peripherals are split between multiple groups. + * These defines are used to differentiate between the groups. + * The bits in the PowerCC23X0_PERIPH_GROUP_M mask is used to store the group id, + * and the bits in the PowerCC23X0_PERIPH_BIT_INDEX_M mask is used to store the + * bit index shift value in the register for the given group. + */ +#define PowerCC23X0_PERIPH_GROUP_M 0xFF00 +#define PowerCC23X0_PERIPH_GROUP_CLKCTL0 0x0000 +#define PowerCC23X0_PERIPH_GROUP_LRFD 0x0100 +#define PowerCC23X0_PERIPH_BIT_INDEX_M 0x00FF + +/* \endcond */ + +/* \cond */ +typedef uint16_t PowerLPF3_Resource; /* Power resource identifier */ +/* \endcond */ + +/* Resource IDs */ + +/*! Resource ID: General Purpose I/O */ +#define PowerLPF3_PERIPH_GPIO (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_GPIO_S) + +/*! Resource ID: UART 0 */ +#define PowerLPF3_PERIPH_UART0 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_UART0_S) + +/*! Resource ID: I2C 0 */ +#define PowerLPF3_PERIPH_I2C0 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_I2C0_S) + +/*! Resource ID: SPI 0 */ +#define PowerLPF3_PERIPH_SPI0 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_SPI0_S) + +/*! Resource ID: ADC */ +#define PowerLPF3_PERIPH_ADC0 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_ADC0_S) + +/*! Resource ID: AES Security Module */ +#define PowerLPF3_PERIPH_AES (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LAES_S) + +/*! Resource ID: uDMA Controller */ +#define PowerLPF3_PERIPH_DMA (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_DMA_S) + +/*! Resource ID: General Purpose Timer 0 */ +#define PowerLPF3_PERIPH_LGPT0 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT0_S) + +/*! Resource ID: General Purpose Timer 1 */ +#define PowerLPF3_PERIPH_LGPT1 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT1_S) + +/* The peripherals below are not available on CC23X0R2 devices */ +#if !defined(DeviceFamily_CC23X0R2) + /*! Resource ID: General Purpose Timer 2 */ + #define PowerLPF3_PERIPH_LGPT2 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT2_S) + + /*! Resource ID: General Purpose Timer 3 */ + #define PowerLPF3_PERIPH_LGPT3 (PowerCC23X0_PERIPH_GROUP_CLKCTL0 | CLKCTL_DESCEX0_LGPT3_S) +#endif + +/*! Resource ID: LRFD Tracer */ +#define PowerLPF3_PERIPH_LFRD_TRC (PowerCC23X0_PERIPH_GROUP_LRFD | LRFDDBELL_CLKCTL_TRC_S) + +/*! Resource ID: LRFD S2R RAM */ +#define PowerLPF3_PERIPH_LFRD_S2RRAM (PowerCC23X0_PERIPH_GROUP_LRFD | LRFDDBELL_CLKCTL_S2RRAM_S) + +/* \cond */ +/* Number of resources in the different resource groups. This is possibly larger + * than the peripheral instance count on various device variants. This is + * because some indexes might not be used for a given variant, resulting in a + * sparse table. + */ +#if defined(DeviceFamily_CC23X0R2) + #define PowerCC23X0_NUMRESOURCES_CLKCTL0 29 +#elif defined(DeviceFamily_CC23X0R5) + #define PowerCC23X0_NUMRESOURCES_CLKCTL0 31 +#else + #error "Unsupported DeviceFamily specified!" +#endif +#define PowerCC23X0_NUMRESOURCES_LRFD 12 +/* \endcond */ + +#define PowerLPF3_STANDBY 0x1 /*!< The STANDBY sleep state */ +/* \cond */ +/* Internal flags for enabling/disabling resources */ +#define PowerLPF3_ENABLE 1 +#define PowerLPF3_DISABLE 0 +/* \endcond */ + +/* Constraints + * + * Constraints restrict a specific system behavior from occurring or guarantee + * a specified effect until released. + */ + +/*! Constraint: Disallow a transition to the SHUTDOWN state */ +#define PowerLPF3_DISALLOW_SHUTDOWN 0 + +/*! Constraint: Disallow a transition to the STANDBY sleep state */ +#define PowerLPF3_DISALLOW_STANDBY 1 + +/*! Constraint: Disallow a transition to the IDLE sleep state */ +#define PowerLPF3_DISALLOW_IDLE 2 + +/*! Constraint: Flash memory needs to enabled during IDLE */ +#define PowerLPF3_NEED_FLASH_IN_IDLE 3 + +/* \cond */ +#define PowerCC23X0_NUMCONSTRAINTS 4 /* Number of constraints supported */ +/* \endcond */ + +/* + * Events + * + * Each event must be a power of two and must be sequential + * without any gaps. + */ + +/*! Power event: The device is entering the STANDBY sleep state */ +#define PowerLPF3_ENTERING_STANDBY (1 << 0) + +/*! Power event: The device is entering the SHUTDOWN state */ +#define PowerLPF3_ENTERING_SHUTDOWN (1 << 1) + +/*! Power event: The device is waking up from the STANDBY sleep state */ +#define PowerLPF3_AWAKE_STANDBY (1 << 2) + +/*! Power event: The high frequency (HF) crystal oscillator is now available + * for use (HFXT) by the digital domain + */ +#define PowerLPF3_HFXT_AVAILABLE (1 << 3) + +/*! Power event: The system has switched to the low frequency clock source + * configured in CCFG + */ +#define PowerLPF3_LFCLK_SWITCHED (1 << 4) + +/* \cond */ +#define PowerCC23X0_NUMEVENTS 5 /* Number of events supported */ +/* \endcond */ + +/*! @brief Global configuration structure */ +typedef struct +{ + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC23X0_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC23X0_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + * + * If not NULL, the policy function will be invoked once for each pass + * of the idle loop. + * + * The power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + Power_PolicyFxn policyFxn; +} PowerCC23X0_Config; + +/*! + * @brief Reasons the device has booted or rebooted. + */ +typedef enum +{ + /*! Device woke up from shutdown due to an IO event */ + PowerLPF3_RESET_SHUTDOWN_IO = PMCTL_RESET_SHUTDOWN_IO, + /*! Device woke up from shutdown due to an SWD event */ + PowerLPF3_RESET_SHUTDOWN_SWD = PMCTL_RESET_SHUTDOWN_SWD, + /*! Device reset because of a watchdog timeout. */ + PowerLPF3_RESET_WATCHDOG = PMCTL_RESET_WATCHDOG, + /*! Device reset trggered by software writing to RSTCTL.SYSRST */ + PowerLPF3_RESET_SYSTEM = PMCTL_RESET_SYSTEM, + /*! Device reset triggered by CPU reset event */ + PowerLPF3_RESET_CPU = PMCTL_RESET_CPU, + /*! Device reset triggered by CPU lockup event */ + PowerLPF3_RESET_LOCKUP = PMCTL_RESET_LOCKUP, + /*! Device woke up from thermal shutdown after temperature drop */ + PowerLPF3_RESET_TSD = PMCTL_RESET_TSD, + /*! Device woke up due to Serial Wire Debug event */ + PowerLPF3_RESET_SWD = PMCTL_RESET_SWD, + /*! Device reset due to LFXT clock loss */ + PowerLPF3_RESET_LFXT = PMCTL_RESET_LFXT, + /*! Device reset due to VDDR brownout event */ + PowerLPF3_RESET_VDDR = PMCTL_RESET_VDDR, + /*! Device reset due to VDDS brownout event */ + PowerLPF3_RESET_VDDS = PMCTL_RESET_VDDS, + /*! Device reset due to pin reset */ + PowerLPF3_RESET_PIN = PMCTL_RESET_PIN, + /*! Device booted due to power on reset */ + PowerLPF3_RESET_POR = PMCTL_RESET_POR, +} PowerLPF3_ResetReason; + +/*! + * @brief The wait for interrupt (WFI) policy + * + * This is a lightweight Power Policy which simply invokes CPU wait for + * interrupt. + * + * This policy can be selected statically via the policyFxn pointer in the + * PowerCC23X0_Config structure, or dynamically at runtime, via + * Power_setPolicy(). + */ +void PowerCC23X0_doWFI(void); + +/*! + * @brief Returns the reason for the most recent reset or wakeup + * + * @return #PowerLPF3_ResetReason + * @pre Power_shutdown() + * @post PowerLPF3_releaseLatches() + */ +static inline PowerLPF3_ResetReason PowerLPF3_getResetReason(void) +{ + return (PowerLPF3_ResetReason)PMCTLGetResetReason(); +} + +/*! + * @brief Unlatch all IOs + * + * This function releases the latches on all frozen IOs. This function should be + * called after waking up from shutdown and reconfiguring the IO state so as not + * to cause glitches. + * + * @note Calling this function will clear the reset reason register if it was + * #PowerLPF3_RESET_SHUTDOWN_IO and PowerLPF3_RESET_SHUTDOWN_SWD and + * cause PowerLPF3_getResetReason() not to return the true reset reason. + * + * @pre Power_shutdown() + * @pre PowerLPF3_getResetReason() + */ +static inline void PowerLPF3_releaseLatches(void) +{ + HWREG(PMCTL_BASE + PMCTL_O_SLPCTL) = PMCTL_SLPCTL_SLPN_DIS; +} + +/*! + * @brief The STANDBY Power Policy + * + * This is an agressive Power Policy, which considers active constraints, + * sleep state transition latencies, and time until the next scheduled + * work, and automatically transitions the device into the deepest sleep state + * possible. + * + * The first goal is to enter STANDBY; if that is not appropriate + * given current conditions (e.g., the sleep transition latency is greater + * greater than the time until the next scheduled Clock event), then + * the secondary goal is the IDLE state; if that is disallowed (e.g., if + * the PowerLPF3_DISALLOW_IDLE constraint is declared), then the policy + * will fallback and simply invoke WFI, to clock gate the CPU until the next + * interrupt. + * + * In order for this policy to run, it must be selected as the Power + * Policy (either by being specified as the 'policyFxn' in the + * PowerCC23X0_Config structure, or specified at runtime with + * Power_setPolicy()), and the Power Policy must be enabled (either via + * 'enablePolicy' in the PowerCC23X0_Config structure, or via a call to + * Power_enablePolicy() at runtime). + */ +void PowerCC23X0_standbyPolicy(void); + +/*! + * @brief Select LFOSC as LFCLK source + * + * Turn on the LFOSC and choose it as LFCLK source. Once LFCLK has switched, the + * #PowerLPF3_LFCLK_SWITCHED notification will be issued and all subscribers to + * this event will be notified. + * + * @warning Dynamic switching between LF clocks is not supported. Once one of + * PowerLPF3_selectLFOSC() or PowerLPF3_selectLFXT() is called in an + * application, the other one may not be invoked thereafter. + * + * @pre Power_init() + * @sa PowerLPF3_selectLFXT() + */ +void PowerLPF3_selectLFOSC(void); + +/*! + * @brief Select LFOSC as LFCLK source + * + * Turn on the LFXT and choose it as LFCLK source. Once LFCLK has switched, + * the #PowerLPF3_LFCLK_SWITCHED notification will be issued and all + * subscribers to this event will be notified. + * + * @warning Dynamic switching between LF clocks is not supported. Once one of + * PowerLPF3_selectLFOSC() or PowerLPF3_selectLFXT() is called in an + * application, the other one may not be invoked thereafter. + * + * @pre Power_init() + * @sa PowerLPF3_selectLFOSC() + */ +void PowerLPF3_selectLFXT(void); + +/*! + * @brief Initialise HFXT temperature compensation coefficients + * + * Initialise the parameters used for HFXT temperature coefficients. They approximate + * the ppm offset of the HFXT frequency with the following polynomial as a function of + * temperature (degC), where P_3 = P3 / 2^shift, P_2 = P2 / 2^shift, etc.. + * ppm(T) = P_3*T^3 + P_2*T^2 + P_1*T + P_0 + * + * @param[in] P0 0th-order coefficient, multiplied by 2^shift + * @param[in] P1 1st-order coefficient, multiplied by 2^shift + * @param[in] P2 2nd-order coefficient, multiplied by 2^shift + * @param[in] P3 3rd-order coefficient, multiplied by 2^shift + * @param[in] shift Shift-value for scaling fixed-point coefficients + * @param[in] fcfgInsertion Boolean used to indicate presence of HFXT FCFG data. + * + * @pre Power_init() + */ +void PowerLPF3_initHFXTCompensation(int32_t P0, int32_t P1, int32_t P2, int32_t P3, uint8_t shift, bool fcfgInsertion); + +/*! + * @brief Enable HFXT temperature compensation + * + * Enable automatic compensation for temperature-based frequency-drift of HFXT + * + * This function should only be called once, but can be invoked again if + * PowerLPF3_enableHFXTCompensation has been called + * + * @param[in] tempThreshold Threshold above which temperature compensation will + * be performed. This can be useful to save power consumption if HFXT + * performance is acceptable at low temperatures, and only required at + * high temperatures. If the threshold is set to for example 80 degrees, then + * the first compensation will occur once the temperature reaches 81 degrees. + * Units in degrees Celsius. + * @param[in] tempDelta Delta describing how much the temperature can drift + * before compensation is applied. If compensation is performed at 81 degrees, + * and the delta is set to 5, then a re-compensation is performed at either + * 76 degrees or 86 degrees, depending on which temperature state occurs first. + * Units in degrees Celsius. + * + * @pre PowerLPF3_initHFXTCompensation() + */ +void PowerLPF3_enableHFXTCompensation(int16_t tempThreshold, int16_t tempDelta); + +/*! + * @brief Disable HFXT temperature compensation + * + * Disable automatic compensation for temperature-based frequency-drift of HFXT + * + * @note Calling this function will also undo any previous temperature compensation that has been + * performed in the past, and HFXT will become uncompensated + * + * @pre PowerLPF3_enableHFXTCompensation() + */ +void PowerLPF3_disableHFXTCompensation(void); + +void PowerCC23X0_schedulerDisable(void); +void PowerCC23X0_schedulerRestore(void); + +#ifdef __cplusplus +} +#endif + +#endif /* POWER_CC23X0_ */ diff --git a/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.c b/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.c new file mode 100644 index 00000000..a9af4d71 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.c @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Includes */ +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_evtull.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_pmud.h) +#include DeviceFamily_constructPath(inc/hw_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +/* Macros */ +/* Offset to apply to all thresholds before programming the hardware. + * + * When the hardware samples the temperature sensor, the returned reading + * is drawn from a probability distribution of measurements for each true + * temperature. In order for a notification to trigger, two separate + * measurements must cross the configured threshold temperature. + * The first is initiated by the hardware in the background to check whether + * to trigger the HWI. The second is triggered by software within the HWI + * function. If the first measurement is part of the long tail of the + * distribution, it is highly probable that the second measurement will not + * cross the threshold. This is effectively a spurrious interrupt that wastes + * energy and CPU cycles. + * If we program the actual hardware registers with an additional offset, we + * effectively shift the distribution up or down such that the first measurement + * triggers on the long tail of the distribution that is DISTRIBUTION_OFFSET + * degrees away from the threshold provided by the application. The second + * measurement then has a much higher probability of crossing the threshold + * and triggering the notification and an update of the thresholds. + * + * The risk is of course that a particular chip has a compressed distribution + * where the long tail does not reach far enough to trigger the HWI with the + * offset applied. + * Additionally, the device does not sample nearly as frequently when in + * standby. + * + * Both of these risks result in a less accurate but overall more useful system. + * If the temperature keeps rising, both scenarios still cause a notification + * to trigger. Given that temperature changes are usually not instantaneous, + * this should be considered an acceptable risk. + */ +#define DISTRIBUTION_OFFSET 2 + +#define BATMON_TEMPERATURE_MAX (255) +#define BATMON_TEMPERATURE_MIN (-256) + +#define INVALID_TEMPERATURE_MAX BATMON_TEMPERATURE_MAX +#define INVALID_TEMPERATURE_MIN BATMON_TEMPERATURE_MIN + +/* Forward declarations */ +static void walkNotifyList(void); +static void setNextThresholds(void); +static void temperatureEventCb(uint32_t eventMask); +static void updateThresholds(int16_t thresholdHigh, int16_t thresholdLow); +static uint32_t degreesToCode(int32_t temperatureDegreesC); +static void setTempLowerLimit(int16_t thresholdLow); +static void setTempUpperLimit(int16_t thresholdHigh); +static void enableTempLowerLimit(void); +static void enableTempUpperLimit(void); +static void disableTempLowerLimit(void); +static void disableTempUpperLimit(void); +static void clearEventFlags(void); +static void thermalShutdownCallback(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); +static int16_t TemperatureLPF3_scaleToRealTemperature(int32_t temperature); +static int16_t TemperatureLPF3_scaleFromRealTemperature(int32_t temperature); + +/* Globals */ + +/* Global list that stores all registered notifications */ +static List_List notificationList; + +/* Current threshold values. These should always reflect the state of the + * batmon registers without the need to read them out, shift down, and sign + * extend the values. + */ +static volatile int16_t currentThresholdHigh = INVALID_TEMPERATURE_MAX; +static volatile int16_t currentThresholdLow = INVALID_TEMPERATURE_MIN; + +static bool isInitialized = false; + +/* + * This object is used to monitor the temperature and trigger thermal shutdown once the threshold is reached. + */ +static Temperature_NotifyObj thermalShutdown; + +/* + * ======== degreesToCode ======== + */ +static uint32_t degreesToCode(int32_t temperatureDegreesC) +{ + /* Adjust for BATMON temperature offset */ + temperatureDegreesC = TemperatureLPF3_scaleFromRealTemperature(temperatureDegreesC); + + uint32_t temperatureCode = (temperatureDegreesC << PMUD_TEMP_INT_S) & PMUD_TEMP_INT_M; + + return temperatureCode; +} + +/* + * ======== setTempLowerLimit ======== + */ +static void setTempLowerLimit(int16_t thresholdLow) +{ + uint32_t temperatureCode = degreesToCode(thresholdLow - DISTRIBUTION_OFFSET); + + HWREG(PMUD_BASE + PMUD_O_TEMPLL) = temperatureCode; + + currentThresholdLow = thresholdLow; +} + +/* + * ======== setTempUpperLimit ======== + */ +static void setTempUpperLimit(int16_t thresholdHigh) +{ + uint32_t temperatureCode = degreesToCode(thresholdHigh + DISTRIBUTION_OFFSET); + + HWREG(PMUD_BASE + PMUD_O_TEMPUL) = temperatureCode; + + currentThresholdHigh = thresholdHigh; +} + +/* + * ======== enableTempLowerLimit ======== + */ +static void enableTempLowerLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) |= PMUD_EVENTMASK_TEMP_BELOW_LL_MASK; +} + +/* + * ======== enableTempUpperLimit ======== + */ +static void enableTempUpperLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) |= PMUD_EVENTMASK_TEMP_OVER_UL_MASK; +} + +/* + * ======== disableTempLowerLimit ======== + */ +static void disableTempLowerLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) &= ~PMUD_EVENTMASK_TEMP_BELOW_LL_MASK; +} + +/* + * ======== disableTempUpperLimit ======== + */ +static void disableTempUpperLimit(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENTMASK) &= ~PMUD_EVENTMASK_TEMP_OVER_UL_MASK; +} + +/* + * ======== clearEventFlags ======== + */ +static void clearEventFlags(void) +{ + HWREG(PMUD_BASE + PMUD_O_EVENT) &= PMUD_EVENT_TEMP_BELOW_LL | PMUD_EVENT_TEMP_OVER_UL; +} + +/* + * ======== setNextThresholds ======== + */ +static void setNextThresholds(void) +{ + List_Elem *notifyLink; + int16_t nextThresholdHigh = INVALID_TEMPERATURE_MAX; + int16_t nextThresholdLow = INVALID_TEMPERATURE_MIN; + uint32_t key; + + key = HwiP_disable(); + + /* Starting with the head of the list, keep track of the smallest high + * threshold and largest low threshold. + */ + notifyLink = List_head(¬ificationList); + + while (notifyLink != NULL) + { + Temperature_NotifyObj *notifyObject = (Temperature_NotifyObj *)notifyLink; + + nextThresholdHigh = Math_MIN(nextThresholdHigh, notifyObject->thresholdHigh); + nextThresholdLow = Math_MAX(nextThresholdLow, notifyObject->thresholdLow); + + notifyLink = List_next(notifyLink); + } + + /* Now that we have found the next upper and lower thresholds, set them. + * These could be INVALID_TEMPERATURE_MAX and/or INVALID_TEMPERATURE_MIN + * if the list is empty or only high/low notifications were registered. + */ + updateThresholds(nextThresholdHigh, nextThresholdLow); + + HwiP_restore(key); +} + +/* + * ======== walkNotifyList ======== + */ +static void walkNotifyList(void) +{ + List_Elem *notifyLink = List_head(¬ificationList); + int16_t currentTemperature = Temperature_getTemperature(); + + /* If the notification list is empty, the head pointer will be + * NULL and the while loop will never execute the statement. + */ + while (notifyLink != NULL) + { + Temperature_NotifyObj *notifyObject = (Temperature_NotifyObj *)notifyLink; + + /* Buffer the next link in case the notification triggers. + * Without buffering, we might skip list entries if the + * notifyObject is freed or reregistered and the notifyObject->link.next + * pointer is altered. + */ + List_Elem *notifyLinkNext = List_next(notifyLink); + + /* If the current temperature is below this notification's low + * threshold or above its high threshold, remove it from the list and + * call the callback fxn + */ + if (currentTemperature <= notifyObject->thresholdLow || currentTemperature >= notifyObject->thresholdHigh) + { + + /* Choose the threshold to provide to the notifyFxn based on the + * thresholds and the current temperature. + */ + int16_t threshold = (currentTemperature <= notifyObject->thresholdLow) ? notifyObject->thresholdLow + : notifyObject->thresholdHigh; + + List_remove(¬ificationList, notifyLink); + notifyObject->isRegistered = false; + + notifyObject->notifyFxn(currentTemperature, threshold, notifyObject->clientArg, notifyObject); + } + + notifyLink = notifyLinkNext; + } +} + +/* + * ======== updateThresholds ======== + */ +static void updateThresholds(int16_t thresholdHigh, int16_t thresholdLow) +{ + if (thresholdHigh < currentThresholdHigh) + { + setTempUpperLimit(thresholdHigh); + enableTempUpperLimit(); + } + + if (thresholdLow > currentThresholdLow) + { + setTempLowerLimit(thresholdLow); + enableTempLowerLimit(); + } +} + +/* + * ======== temperatureEventCb ======== + * + * Batmon interrupt triggered on high or low temperature event + */ +static void temperatureEventCb(uint32_t eventMask) +{ + + setTempUpperLimit(INVALID_TEMPERATURE_MAX); + disableTempUpperLimit(); + + setTempLowerLimit(INVALID_TEMPERATURE_MIN); + disableTempLowerLimit(); + + /* Walk the notification list and issue any callbacks that have triggered + * at the current temperature. + */ + walkNotifyList(); + + /* Walk the queue another time to find and set the next set of thresholds. + * This is faster than making even one extra access to AON_BATMON. + */ + setNextThresholds(); + + /* Clear event flags. They may not immediately clear properly. */ + clearEventFlags(); +} + +/* + * ======== thermalShutdownCallback ======== + * + * Callback function for thermal shutdown notify object + */ +static void thermalShutdownCallback(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject) +{ + /* Immediately bring the device into reset, and enable the thermal shutdown comparator. */ + TemperatureLPF3_triggerThermalShutdown(); +} + +/* + * ======== Temperature_init ======== + */ +void Temperature_init(void) +{ + uint32_t key; + + key = HwiP_disable(); + + if (isInitialized == false) + { + BatMonSupportLPF3_init(); + BatMonSupportLPF3_registerTemperatureCb(PMUD_EVENT_TEMP_BELOW_LL | PMUD_EVENT_TEMP_OVER_UL, temperatureEventCb); + + /* Wait first measurement is ready to prevent Temperature_getTemperature + * returning an invalid value + */ + while ((HWREG(PMUD_BASE + PMUD_O_TEMPUPD) & PMUD_TEMPUPD_STA_M) != PMUD_TEMPUPD_STA_M) {} + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== Temperature_getTemperature ======== + */ +int16_t Temperature_getTemperature(void) +{ + /* The temperature on Low Power F3 devices is stored in a 32-bit register + * containing a 9-bit signed integer part and a 2-bit unsigned fractional + * part. The fractional part is discarded from the returned result, but is + * used in the correction-calculation below. + */ + + int32_t temperature = HWREG(PMUD_BASE + PMUD_O_TEMP); + + /* Mask and shift the integer and fractional parts of the temperature */ + temperature = (temperature & (PMUD_TEMP_INT_M | PMUD_TEMP_FRAC_M)) >> PMUD_TEMP_FRAC_S; + + /* Perform sign extension */ + temperature = (temperature << (32 - (PMUD_TEMP_INT_W + PMUD_TEMP_FRAC_W))) >> + (32 - (PMUD_TEMP_INT_W + PMUD_TEMP_FRAC_W)); + + /* Correct for temperature-dependent error in BATMON sensor */ + temperature = TemperatureLPF3_scaleToRealTemperature(temperature); + + return temperature; +} + +/* + * ======== Temperature_registerNotifyHigh ======== + */ +int_fast16_t Temperature_registerNotifyHigh(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = INVALID_TEMPERATURE_MIN; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_registerNotifyLow ======== + */ +int_fast16_t Temperature_registerNotifyLow(Temperature_NotifyObj *notifyObject, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = INVALID_TEMPERATURE_MAX; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_registerNotifyRange ======== + */ +int_fast16_t Temperature_registerNotifyRange(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_unregisterNotify ======== + */ +int_fast16_t Temperature_unregisterNotify(Temperature_NotifyObj *notifyObject) +{ + uint32_t key; + + key = HwiP_disable(); + + if (notifyObject->isRegistered == true) + { + /* Remove the notification from the list */ + List_remove(¬ificationList, &(notifyObject->link)); + + notifyObject->isRegistered = false; + } + + /* Find the next set of thresholds and update the registers */ + setNextThresholds(); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== TemperatureLPF3_enableTSDMonitoring ======== + */ +void TemperatureLPF3_enableTSDMonitoring(int16_t shutdownThreshold) +{ + /* + * Register a notify object on threshold value, that calls the thermal shutdown callback. + * The callback will immediately trigger a thermal shutdown + */ + Temperature_registerNotifyHigh(&thermalShutdown, shutdownThreshold, thermalShutdownCallback, (uintptr_t)NULL); +} + +/* + * ======== TemperatureLPF3_disableTSDMonitoring ======== + */ +void TemperatureLPF3_disableTSDMonitoring(void) +{ + /* + * Unregister the thermal shutdown notify-object. + */ + Temperature_unregisterNotify(&thermalShutdown); +} + +/* + * ======== TemperatureLPF3_triggerThermalShutdown ======== + */ +void TemperatureLPF3_triggerThermalShutdown(void) +{ + HWREG(PMCTL_BASE + PMCTL_O_RSTCTL) |= PMCTL_RSTCTL_TSDEN_EN; +} + +/* + * ======== TemperatureLPF3_scaleToRealTemperature ======== + */ +static int16_t TemperatureLPF3_scaleToRealTemperature(int32_t temperature) +{ + /* Due to a non-linearity in the BATMON temperature sensor, the temperature + * returned by the hardware should be adjusted to attain a more accurate + * temperature. The transfer function from batmon temperature to real + * temperature is as follows: + * + * T_real(T) = p1*T + p0 + * + * The coefficients account for the input temperature containing two + * fractional bits, and the adjusted temperature will also contain two + * fractional bits. + * + * p1 = 1.04348435 + * p0 = -6.71741627 + * + * Scaled by 2^20 to fixed-point integers: + * + * p1 = 1094173 + * p0 = -7043721 + */ + + int32_t p1 = 1094172; + int32_t p0 = -7043721; + + temperature = (temperature * p1) + p0; + + /* Round to nearest integer. Divide by 2^22 to bring scaled + * temperature with two fractional bits down to temperature with no + * fractional bits. Do division instead of right-shift, since temperature + * is a signed integer. + */ + if (temperature > 0) + { + temperature = (temperature + (1 << 21)) / (1 << 22); + } + else + { + temperature = (temperature - (1 << 21)) / (1 << 22); + } + + return temperature; +} + +static int16_t TemperatureLPF3_scaleFromRealTemperature(int32_t temperature) +{ + /* Due to a non-linearity in the BATMON temperature sensor, the temperature + * programmed in the hardware should be adjusted to reflect a more accruate + * temperature. The transfer function accurate temperature to BATMON + * temperature is as follows: + * + * T_batmon(T) = p1*T + p0 + * + * p1 = 0.95832774109 + * p0 = 6.43748636 + * + * Scaled by 2^20 to fixed-point integers: + * + * p1 = 1004879 + * p0 = 6750194 + */ + int32_t p1 = 1004879; + int32_t p0 = 6750194; + + /* Add two fractional bits */ + temperature *= 4; + + /* Bring temperature from real temperature to BATMON temperature */ + temperature = (temperature * p1) + p0; + + /* Round to nearest integer. Divide by 2^22 to bring scaled + * temperature with two fractional bits down to temperature with no + * fractional bits. Do division instead of right-shift, since temperature + * is a signed integer. + */ + if (temperature > 0) + { + temperature = (temperature + (1 << 21)) / (1 << 22); + } + else + { + temperature = (temperature - (1 << 21)) / (1 << 22); + } + + /* Limit the temperature to valid BATMON temperatures */ + if (temperature > BATMON_TEMPERATURE_MAX) + { + temperature = BATMON_TEMPERATURE_MAX; + } + else if (temperature < BATMON_TEMPERATURE_MIN) + { + temperature = BATMON_TEMPERATURE_MIN; + } + + return temperature; +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.h b/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.h new file mode 100644 index 00000000..637e2875 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/temperature/TemperatureLPF3.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TemperatureLPF3.h + * + * @brief Temperature driver implementation for the Low Power F3 family + * + * The temperature driver on Low Power F3 devices is a part of the battery + * monitoring system in AON (always on). It periodically takes measurements of + * the temperature of the chip and will issue interrupts if the configured + * upper limit or lower limit is crossed. + * + * # Standby Power Mode Behavior # + * The temperature measurement is active while in standby power mode as well. + * The interrupt used by the temperature module is capable of bringing the + * device out of standby and into active mode to handle it. That means that an + * application will not miss a change in temperature just because the device + * has transitioned to standby power mode. While in standby, the temperature + * will only be sampled during a VDDR recharge pulse. This means that the + * sampling frequency in standby will be determined by the temperature as + * leakage increases with temperature and requires more frequent recharging of + * VDDR. + */ + +#ifndef ti_drivers_temperature_TemperatureLPF3__include +#define ti_drivers_temperature_TemperatureLPF3__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Temperature driver configuration struct for Low Power F3 devices + * + * This struct globally controls configuration settings for the Temperature + * driver. + * + * The Low Power F3 Temperature driver implementation links against a structure + * of this type named TemperatureLPF3_config. + * + * This structure must be allocated and configured by the application. If + * SysConfig is used, this struct will be automatically created when the + * Temperature module is used in SysConfig. + */ +typedef struct +{ + /*! @brief Temperature sensor's interrupt priority. + * + * The interrupt line is shared between the temperature sensor and the + * battery voltage monitor on Low Power F3 devices + * + * The Low Power F3 devices use either three or two priority bits, + * depending on the device. That means ~0 has the same effect as (7 << 5) + * or (3 << 6), respectively. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + * interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} TemperatureLPF3_Config; + +/** + * @brief Enable thermal shutdown monitoring + * + * Set threshold for thermal shutdown, in degrees Celsius, and enable thermal shutdown monitoring. Once the + * temperature of the device reaches or goes above @c shutdownThreshold, the driver will invoke + * an internal callback-function that will invoke @ref TemperatureLPF3_triggerThermalShutdown. If a custom shutdown + * procedure is required, one would need to install their own callback using @ref Temperature_registerNotifyHigh, + * and optionally call @ref TemperatureLPF3_triggerThermalShutdown as the last thing in the custom callback. + * + * @param shutdownThreshold Thermal shutdown threshold in degrees Celsius + */ +void TemperatureLPF3_enableTSDMonitoring(int16_t shutdownThreshold); + +/** + * @brief Disable thermal shutdown monitoring + * + * Disable thermal shutdown monitoring. To re-enable, @ref TemperatureLPF3_enableTSDMonitoring must be called again + * with the desired temperature threshold. + */ +void TemperatureLPF3_disableTSDMonitoring(void); + +/** + * @brief Trigger thermal shutdown + * + * Immediately trigger thermal shutdown, and enable the thermal shutdown comparator. The device will remain in + * reset for as long as the comparator is high (i.e for as long as the temperature is above 95 degrees C. + * See technical reference manual for more details. This function is called if TSD monitoring is enabled through + * @ref TemperatureLPF3_enableTSDMonitoring and the given threshold temperature is reached. The threshold should + * always be set to greater than 95, or the device will immediately come back out of reset. Typically, the threshold + * would be set near the maximum operating temperature of 125 degrees C. + * + * @note Calling this function will immediately bring the device into reset + */ +void TemperatureLPF3_triggerThermalShutdown(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_temperature_TemperatureLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/utils/List.c b/simplelink_lpf3/source/ti/drivers/utils/List.c new file mode 100644 index 00000000..970ae162 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/List.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2015, 2017 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== List.c ======== + */ +#include +#include + +#include +#include +#include + +/* + * ======== List_clearList ======== + */ +void List_clearList(List_List *list) +{ + uintptr_t key; + + key = HwiP_disable(); + + list->head = list->tail = NULL; + + HwiP_restore(key); +} + + + +/* + * ======== List_get ======== + */ +List_Elem *List_get(List_List *list) +{ + List_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = list->head; + + /* See if the List was empty */ + if (elem != NULL) { + list->head = elem->next; + if (elem->next != NULL) { + elem->next->prev = NULL; + } + else { + list->tail = NULL; + } + } + + HwiP_restore(key); + + return (elem); +} + + +/* + * ======== List_insert ======== + */ +void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) +{ + uintptr_t key; + + key = HwiP_disable(); + + newElem->next = curElem; + newElem->prev = curElem->prev; + if (curElem->prev != NULL) { + curElem->prev->next = newElem; + } + else { + list->head = newElem; + } + curElem->prev = newElem; + + HwiP_restore(key); +} + + +/* + * ======== List_put ======== + */ +void List_put(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = NULL; + elem->prev = list->tail; + if (list->tail != NULL) { + list->tail->next = elem; + } + else { + list->head = elem; + } + + list->tail = elem; + + HwiP_restore(key); +} + +/* + * ======== List_putHead ======== + */ +void List_putHead(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = list->head; + elem->prev = NULL; + if (list->head != NULL) { + list->head->prev = elem; + } + else { + list->tail = elem; + } + + list->head = elem; + + HwiP_restore(key); +} + +/* + * ======== List_remove ======== + */ +void List_remove(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + /* Handle the case where the elem to remove is the last one */ + if (elem->next == NULL) { + list->tail = elem->prev; + } + else { + elem->next->prev = elem->prev; + } + + /* Handle the case where the elem to remove is the first one */ + if (elem->prev == NULL) { + list->head = elem->next; + } + else { + elem->prev->next = elem->next; + } + + HwiP_restore(key); +} diff --git a/simplelink_lpf3/source/ti/drivers/utils/List.h b/simplelink_lpf3/source/ti/drivers/utils/List.h new file mode 100644 index 00000000..ccba687c --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/List.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file List.h + * + * @brief Linked List interface for use in drivers + * + * This module provides simple doubly-link list implementation. There are two + * main structures: + * - ::List_List: The structure that holds the start of a linked list. There + * is no API to create one. It is up to the driver to provide the structure + * itself. + * - ::List_Elem: The structure that must be in the structure that is placed + * onto a linked list. Generally it is the first field in the structure. For + * example: + * @code + * typedef struct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * @endcode + * + * The following shows how to create a linked list with three elements. + * + * @code + * + denotes null-terminated + * _______ _______ _______ _______ + * |_______|----->|_______|----->|_______|--->|_______|--//---, + * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + + * | List + elem elem elem | + * |_____________________________________________________________| + * @endcode + * + * The APIs ::List_get, ::List_put, and ::List_putHead are + * atomic. The other APIs are not necessarily atomic. In other words, when + * traversing a linked list, it is up to the application to provide + * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). + * + * Initializing and adding an element to the tail and removing it + * @code + * typedef struct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * + * List_List list; + * MyStruct foo; + * MyStruct *bar; + * + * List_clearList(&list); + * List_put(&list, (List_Elem *)&foo); + * bar = (MyStruct *)List_get(&list); + * @endcode + * + * The ::List_put and ::List_get APIs are used to maintain a first-in first-out + * (FIFO) linked list. + * + * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out + * (LIFO) linked list. + * + * Traversing a list from head to tail. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * Traversing a list from tail to head. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_utils_List__include +#define ti_drivers_utils_List__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct List_Elem_ { + struct List_Elem_ *next; + struct List_Elem_ *prev; +} List_Elem; + +typedef struct { + List_Elem *head; + List_Elem *tail; +} List_List; + +/*! + * @brief Function to initialize the contents of a List_List + * + * @param list Pointer to a List_List structure that will be used to + * maintain a linked list + */ +extern void List_clearList(List_List *list); + +/*! + * @brief Function to test whether a linked list is empty + * + * @param list A pointer to a linked list + * + * @return true if empty, false if not empty + */ +static inline bool List_empty(List_List *list) +{ + return (list->head == NULL); +} + +/*! + * @brief Function to atomically get the first elem in a linked list + * + * @param list A pointer to a linked list + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_get(List_List *list); + +/*! + * @brief Function to return the head of a linked list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline List_Elem *List_head(List_List *list) +{ + return (list->head); +} + +/*! + * @brief Function to insert an elem into a linked list + * + * @param list A pointer to the linked list + * + * @param newElem New elem to insert + * + * @param curElem Elem to insert the newElem in front of. + * This value cannot be NULL. + */ +extern void List_insert(List_List *list, List_Elem *newElem, + List_Elem *curElem); + +/*! + * @brief Function to return the next elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline List_Elem *List_next(List_Elem *elem) +{ + return (elem->next); +} + +/*! + * @brief Function to return the prev elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * prev one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the prev elem in linked list or NULL if at the beginning + */ +static inline List_Elem *List_prev(List_Elem *elem) +{ + return (elem->prev); +} + +/*! + * @brief Function to atomically put an elem onto the end of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the end of the linked list + */ +extern void List_put(List_List *list, List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the head of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the beginning of the linked list + */ +extern void List_putHead(List_List *list, List_Elem *elem); + +/*! + * @brief Function to remove an elem from a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to be removed from a linked list + */ +extern void List_remove(List_List *list, List_Elem *elem); + +/*! + * @brief Function to return the tail of a linked list + * + * This function does not remove the tail, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the last elem in the linked list or NULL if empty + */ +static inline List_Elem *List_tail(List_List *list) +{ + return (list->tail); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_List__include */ diff --git a/simplelink_lpf3/source/ti/drivers/utils/Math.c b/simplelink_lpf3/source/ti/drivers/utils/Math.c new file mode 100644 index 00000000..21ae62b3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/Math.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Math.c ======== + */ + +#include + +/* + * ======== Math_divideBy1000 ======== + */ +uint32_t Math_divideBy1000(uint32_t dividend) +{ + uint32_t p1 = (dividend >> 16) * (0x83126E98 >> 16); + uint32_t p2 = (dividend & 0xFFFF) * (0x83126E98 >> 16); + p2 += (dividend >> 16) * (0x83126E98 & 0xFFFF); + p2 >>= 7; + p2 += 222; + p1 += p2 >> 9; + return p1 >> 9; +} diff --git a/simplelink_lpf3/source/ti/drivers/utils/Math.h b/simplelink_lpf3/source/ti/drivers/utils/Math.h new file mode 100644 index 00000000..3893f667 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/Math.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file Math.h + * + * @brief Math utility functions + * + */ + +#ifndef ti_drivers_utils_Math__include +#define ti_drivers_utils_Math__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Macro to determine the minimum of two numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The first number. Either an integer or a floating point type. + * @param y The second number. Must be the same type as @c x. + * + * @return The minimum of @c x and @c y + */ +#define Math_MIN(x, y) (((x) < (y)) ? (x) : (y)) + +/*! + * @brief Macro to determine the maximum of two numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The first number. Either an integer or a floating point type. + * @param y The second number. Must be the same type as @c x. + * + * @return The maximum of @c x and @c y + */ +#define Math_MAX(x, y) (((x) > (y)) ? (x) : (y)) + +/*! + * @brief Macro to calculate the absolute value of a numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The number to calculate the absolute value of. + * Either a signed integer or a floating point type. + * + * @return The absolute value of @c x + */ +#define Math_ABS(x) ((x) < 0 ? -(x) : (x)) + +/*! + * @brief Divide a number by 1000 + * + * This function is intended for devices without a hardware divider (for example CC23X0) + * that must run divisions (that are not a power of 2) in software. + * The generic software division implementations provided by compilers are + * relatively slow. This function only supports dividing by 1000, but + * does so in ~16 cycles vs. ~95 cycles for the generic implementations. + * + * @warning Limitations: The division is only accurate for + * @c dividend < 754515999, and off by 1 for values of + * @c dividend = 754515999 + 1000*n. + * + * @param dividend The dividend to be divided by 1000. Must be below + * 754515999 for division to be accurate. + * + * @return Returns @c dividend / 1000 (see limitations) + */ +extern uint32_t Math_divideBy1000(uint32_t dividend); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_Math__include */ \ No newline at end of file From b118845a1150501b255521a54ea2fab792379445 Mon Sep 17 00:00:00 2001 From: Lars Thalian Morstad Date: Wed, 8 May 2024 13:50:17 +0200 Subject: [PATCH 2/7] hal: drivers: ports EventP, MessageQueueP and TaskP DPL features to Zephyr Ports parts of simplelink's Driver Porting Layer to TI F3 devices on Zephyr. Taking inspiration from already existing DPL features, we allocate kernel objects using slab memory. This means the total number of k_event, k_msgq and k_thread objects is limited by a compile-time configuration. Signed-off-by: Lars Thalian Morstad --- simplelink_lpf3/CMakeLists.txt | 5 + .../kernel/zephyr/dpl/EventP_zephyr.c | 174 ++++++++++ .../kernel/zephyr/dpl/MessageQueueP_zephyr.c | 224 +++++++++++++ .../kernel/zephyr/dpl/TaskP_zephyr.c | 250 +++++++++++++++ simplelink_lpf3/kernel/zephyr/dpl/dpl.h | 9 + .../source/ti/drivers/dpl/ClockP.h | 2 + .../source/ti/drivers/dpl/EventP.h | 222 +++++++++++++ .../source/ti/drivers/dpl/MessageQueueP.h | 302 ++++++++++++++++++ simplelink_lpf3/source/ti/drivers/dpl/TaskP.h | 280 ++++++++++++++++ 9 files changed, 1468 insertions(+) create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/dpl.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/EventP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/MessageQueueP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/TaskP.h diff --git a/simplelink_lpf3/CMakeLists.txt b/simplelink_lpf3/CMakeLists.txt index 0cb416bc..2e8a384d 100644 --- a/simplelink_lpf3/CMakeLists.txt +++ b/simplelink_lpf3/CMakeLists.txt @@ -27,5 +27,10 @@ if(CONFIG_HAS_CC23X0_SDK) # DPL kernel/zephyr/dpl/ClockP_zephyr.c kernel/zephyr/dpl/HwiP_zephyr.c + kernel/zephyr/dpl/TaskP_zephyr.c + kernel/zephyr/dpl/MessageQueueP_zephyr.c ) + if(CONFIG_EVENTS) + zephyr_library_sources(kernel/zephyr/dpl/EventP_zephyr.c) + endif() endif() diff --git a/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c new file mode 100644 index 00000000..ff2b7689 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include +#include + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_DYNAMIC_DPL_OBJECTS +/* We can't easily dynamically allocate kernel objects */ +#define DPL_MAX_EVENTS 5 +K_MEM_SLAB_DEFINE(event_slab, sizeof(struct k_event), DPL_MAX_EVENTS,\ + MEM_ALIGN); + + +static struct k_event *dpl_event_pool_alloc() +{ + struct k_event *event_ptr = NULL; + + if (k_mem_slab_alloc(&event_slab, (void **)&event_ptr, K_NO_WAIT) < 0) { + + __ASSERT(0, "Increase size of DPL event pool"); + } + return event_ptr; +} + +static void dpl_event_pool_free(struct k_event *event) +{ + k_mem_slab_free(&event_slab, (void *)event); + + return; +} + +/* + * ======== EventP_create ======== + */ +EventP_Handle EventP_create(void) +{ + struct k_event *event = dpl_event_pool_alloc(); + k_event_init(event); + return (EventP_Handle) event; +} + +/* + * ======== EventP_delete ======== + */ +void EventP_delete(EventP_Handle handle) +{ + if (handle != NULL) + { + dpl_event_pool_free((struct k_event *) handle); + } +} + +#endif /* CONFIG_DYNAMIC_DPL_OBJECTS */ + +/* + * ======== EventP_construct ======== + */ +EventP_Handle EventP_construct(EventP_Struct *obj) +{ + struct k_event *event; + event = (struct k_event*)obj; + + if (event) { + k_event_init(event); + } + + return (EventP_Handle)event; +} + +/* + * ======== EventP_destruct ======== + */ +void EventP_destruct(EventP_Struct *obj) +{ + struct k_event *event; + + event = (struct k_event *)obj->data; + + k_event_clear(event, 0xFFFFFFFF); +} + +/* + * ======== EventP_pend ======== + */ +uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, uint32_t timeout) +{ + uint32_t eventBits, tickPeriod; + k_timeout_t eventTimeout; + uint64_t timeUS; + + + if (timeout == EventP_WAIT_FOREVER) + { + eventTimeout = K_FOREVER; + } + else if (timeout == EventP_NO_WAIT) + { + eventTimeout = K_NO_WAIT; + } + else + { + /* if necessary, convert ClockP ticks to Zephyr ticks */ + /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ + tickPeriod = CLOCKP_TICK_PERIOD; + eventTimeout = K_TICKS(timeout); + } + + if(waitForAll) + { + /* Wait for all event bits */ + eventBits = k_event_wait_all((struct k_event *) event, eventMask, false, eventTimeout); + } + else + { + /* Wait for any event bits */ + eventBits = k_event_wait((struct k_event *) event, eventMask, false, eventTimeout); + } + + /* Clear the events that caused the return */ + k_event_clear((struct k_event *) event, eventBits); + + /* Check if wait returned because of timeout */ + if (((eventBits == 0)) || ((eventBits != eventMask) && (waitForAll == true))) + { + return 0; + } + else + { + return eventBits; + } +} + +/* + * ======== EventP_post ======== + */ +void EventP_post(EventP_Handle event, uint32_t eventMask) +{ + /* Unpend all tasks waiting for these events, and merge these events with + the ones already tracked by the object + */ + k_event_set((struct k_event *) event, eventMask); +} + +/* + * ======== EventP_clear ======== + */ +void EventP_clear(EventP_Handle event, uint32_t eventMask) +{ + k_event_clear((struct k_event *) event, eventMask); +} + +/* + * ======== EventP_get ======== + */ +uint32_t EventP_get(EventP_Handle event) +{ + uint32_t events = ((struct k_event *)event)->events; + return events; +} \ No newline at end of file diff --git a/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c new file mode 100644 index 00000000..83375a94 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_DYNAMIC_DPL_OBJECTS +/* We can't easily dynamically allocate kernel objects */ +#define DPL_MAX_MSGQS 4 +K_MEM_SLAB_DEFINE(msgq_slab, sizeof(struct k_msgq) , DPL_MAX_MSGQS, MEM_ALIGN); + +static struct k_msgq *dpl_msgq_pool_alloc() +{ + struct k_msgq *msgq_ptr = NULL; + + if (k_mem_slab_alloc(&msgq_slab, (void **)&msgq_ptr, K_NO_WAIT) < 0) { + + __ASSERT(0, "Increase size of DPL message queue pool"); + } + return msgq_ptr; +} + +static void dpl_msgq_pool_free(struct k_msgq *msgq) +{ + + k_mem_slab_free(&msgq_slab, (void *)msgq); + + return; +} + +/* + * ======== MessageQueueP_create ======== + */ +MessageQueueP_Handle MessageQueueP_create(size_t msgSize, size_t msgCount) +{ + struct k_msgq *msgq = dpl_msgq_pool_alloc(); + int status = k_msgq_alloc_init(msgq, msgSize, msgCount); + if(status != 0) + { + return NULL; + } + return (MessageQueueP_Handle) msgq; +} + +/* + * ======== MessageQueueP_delete ======== + */ +void MessageQueueP_delete(MessageQueueP_Handle handle) +{ + if (handle != NULL) + { + struct k_msgq* msgq; + msgq = (struct k_msgq* )handle; + k_msgq_purge(msgq); + k_msgq_cleanup(msgq); + dpl_msgq_pool_free(msgq); + } +} +#endif /* CONFIG_DYNAMIC_DPL_OBJECTS */ + +/* + * ======== MessageQueueP_construct ======== + */ +MessageQueueP_Handle MessageQueueP_construct(MessageQueueP_Struct *msgStruct, + size_t msgSize, + size_t msgCount, + void *msgBuf) +{ + struct k_msgq* msgq; + msgq = (struct k_msgq* )msgStruct; + if (msgq) { + k_msgq_init(msgq, msgBuf, msgSize, msgCount); + } + + return (MessageQueueP_Handle)msgq; +} + +/* + * ======== MessageQueueP_destruct ======== + */ +void MessageQueueP_destruct(MessageQueueP_Handle handle) +{ + k_msgq_purge((struct k_msgq* )handle); +} + +/* + * ======== MessageQueueP_pend ======== + */ +MessageQueueP_Status MessageQueueP_pend(MessageQueueP_Handle handle, void *message, uint32_t timeout) +{ + uint32_t tickPeriod; + k_timeout_t msgTimeout; + + /* Timeout must be K_NO_WAIT if in an ISR */ + if ((timeout == MessageQueueP_NO_WAIT) || k_is_in_isr()) + { + msgTimeout = K_NO_WAIT; + } + else if (timeout == MessageQueueP_WAIT_FOREVER) + { + msgTimeout = K_FOREVER; + } + else + { + /* If necessary, convert ClockP ticks to Zephyr ticks */ + /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ + tickPeriod = CLOCKP_TICK_PERIOD; + msgTimeout = K_TICKS(timeout); + } + int status = k_msgq_get((struct k_msgq*) handle, message, msgTimeout); + if(status == 0) + { + return MessageQueueP_OK; + } + return MessageQueueP_TIMEOUT; +} + +/* + * ======== MessageQueueP_peek ======== + */ +MessageQueueP_Status MessageQueueP_peek(MessageQueueP_Handle handle, void *message, uint32_t timeout) +{ + assert(timeout == MessageQueueP_NO_WAIT); + /* Zephyr peek does not support timeouts*/ + uint32_t status = k_msgq_peek((struct k_msgq*) handle, message); + + if(status == 0) + { + return MessageQueueP_OK; + } + return MessageQueueP_TIMEOUT; +} + +/* + * ======== MessageQueueP_post ======== + */ +MessageQueueP_Status MessageQueueP_post(MessageQueueP_Handle handle, const void *message, uint32_t timeout) +{ + uint32_t tickPeriod; + k_timeout_t msgTimeout; + uint64_t timeUS; + + if (timeout == MessageQueueP_NO_WAIT) + { + msgTimeout = K_NO_WAIT; + } + else if (timeout == MessageQueueP_WAIT_FOREVER) + { + msgTimeout = K_FOREVER; + } + else + { + /* if necessary, convert ClockP ticks to Zephyr ticks */ + /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ + tickPeriod = CLOCKP_TICK_PERIOD; + if (tickPeriod != CONFIG_SYS_CLOCK_TICKS_PER_SEC) + { + timeUS = timeout * (uint64_t)tickPeriod; + msgTimeout = K_USEC(timeUS); + } + else + { + msgTimeout = K_TICKS(timeout); + } + } + + int status = k_msgq_put((struct k_msgq*) handle, message, msgTimeout); + + if(status == 0) + { + return MessageQueueP_OK; + } + return MessageQueueP_TIMEOUT; +} + +/* + * ======== MessageQueueP_postFront ======== + */ +MessageQueueP_Status MessageQueueP_postFront(MessageQueueP_Handle handle, const void *message, uint32_t timeout) +{ + return MessageQueueP_post(handle, message, timeout); +} + +/* + * ======== MessageQueueP_getPendingCount ======== + */ +size_t MessageQueueP_getPendingCount(MessageQueueP_Handle handle) +{ + size_t msgCount = k_msgq_num_used_get((struct k_msgq*) handle); + return msgCount; +} + +/* + * ======== MessageQueueP_getFreeCount ======== + */ +size_t MessageQueueP_getFreeCount(MessageQueueP_Handle handle) +{ + size_t freeMsgCount = k_msgq_num_free_get((struct k_msgq*) handle); + + return freeMsgCount; +} + +/* + * ======== MessageQueueP_getMessageQueueObjectSize ======== + */ +uint32_t MessageQueueP_getMessageQueueObjectSize(void) +{ + return sizeof(struct k_msgq); +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c new file mode 100644 index 00000000..8bec7831 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include +#include + +#include + +#include +#include +#include +#include + +#if (defined(CONFIG_DYNAMIC_DPL_OBJECTS) && defined(CONFIG_DYNAMIC_THREAD) && defined(CONFIG_DYNAMIC_THREAD_ALLOC) && defined(CONFIG_THREAD_STACK_INFO)) + #define DYNAMIC_THREADS +#endif + +#ifdef DYNAMIC_THREADS +/* Space for thread objects */ +K_MEM_SLAB_DEFINE(task_slab, sizeof(struct k_thread), CONFIG_DYNAMIC_THREAD_POOL_SIZE,\ + MEM_ALIGN); + +static struct k_thread *dpl_task_pool_alloc() +{ + struct k_thread *task_ptr = NULL; + + if (k_mem_slab_alloc(&task_slab, (void **)&task_ptr, K_NO_WAIT) < 0) { + + __ASSERT(0, "Increase size of DPL task pool"); + } + printk("Slabs used: %d / %d \n", task_slab.info.num_used, task_slab.info.num_blocks); + return task_ptr; +} + +static void dpl_task_pool_free(struct k_thread *task) +{ + k_mem_slab_free(&task_slab, (void *)task); + return; +} + +#endif /* CONFIG_DYNAMIC_DPL_OBJECTS */ + +/* + * ======== Array for conversion of Zephyr thread state to DPL task state ======== + */ +const TaskP_State taskState[] = {TaskP_State_RUNNING, /*!< Running */ + TaskP_State_READY, /*!< Ready */ + TaskP_State_BLOCKED, /*!< Suspended */ + TaskP_State_INACTIVE, /*!< Suspended */ + TaskP_State_DELETED, /*!< Terminated */ + TaskP_State_INVALID}; /*!< Dummy */ + +/* + * ======== Default TaskP_Params values ======== + */ +static const TaskP_Params TaskP_defaultParams = { + .name = "NAME", + .arg = NULL, + .priority = 1, + .stackSize = TaskP_DEFAULT_STACK_SIZE, + .stack = NULL, +}; + +/* + * ======== TaskP_Params_init ======== + */ +void TaskP_Params_init(TaskP_Params *params) +{ + /* structure copy */ + *params = TaskP_defaultParams; +} + +#ifdef DYNAMIC_THREADS +/* + * ======== TaskP_create ======== + */ +TaskP_Handle TaskP_create(TaskP_Function fxn, const TaskP_Params *params) +{ + k_tid_t task_tid; + struct k_thread *task = dpl_task_pool_alloc(); + + k_thread_stack_t * task_stack = k_thread_stack_alloc(params->stackSize, 0); + + if(task_stack != NULL) + { + + /* TaskP uses inversed priority to Zephyr */ + task_tid = k_thread_create(task, task_stack, + K_THREAD_STACK_SIZEOF(task_stack), + (k_thread_entry_t) fxn, + params->arg, NULL, NULL, + (0 - params->priority), 0, K_NO_WAIT); + if(task_tid != NULL) + { + k_thread_name_set(task_tid, params->name); + } + } + + return ((TaskP_Handle)task); +} + +/* + * ======== TaskP_delete ======== + */ +void TaskP_delete(TaskP_Handle task) +{ + if (task != NULL) + { + TaskP_State state = TaskP_getState(task); + if(state != TaskP_State_INVALID && state != TaskP_State_DELETED) + { + struct k_thread* thread = (struct k_thread* )task; + k_thread_abort((k_tid_t) thread); + + int status = k_thread_stack_free((k_thread_stack_t *) thread->stack_info.start); + if(status == 0) + { + dpl_task_pool_free(thread); + } + } + } +} +#endif +/* + * ======== TaskP_construct ======== + */ +TaskP_Handle TaskP_construct(TaskP_Struct *obj, TaskP_Function fxn, const TaskP_Params *params) +{ + if (params == NULL) + { + /* Set default parameter values */ + params = &TaskP_defaultParams; + } + + /* TaskP uses inversed priority to Zephyr */ + k_tid_t task_tid = k_thread_create((struct k_thread*) obj, (k_thread_stack_t*) params->stack, + params->stackSize, + (k_thread_entry_t) fxn, + params->arg, NULL, NULL, + (0 - params->priority), 0, K_NO_WAIT); + + if(task_tid != NULL) + { + k_thread_name_set(task_tid, params->name); + } + + return ((TaskP_Handle) obj); +} + +/* + * ======== TaskP_destruct ======== + */ +void TaskP_destruct(TaskP_Struct *obj) +{ + if (obj != NULL) + { + TaskP_State state = TaskP_getState((TaskP_Handle) obj); + if(state != TaskP_State_INVALID && state != TaskP_State_DELETED) + { + struct k_thread* thread = (struct k_thread* )obj; + k_thread_abort((k_tid_t) thread); + } + } +} + +/* + * ======== TaskP_getState ======== + */ +TaskP_State TaskP_getState(TaskP_Handle task) +{ + TaskP_State state; + + switch (((struct k_thread*) task)->base.thread_state) { + case _THREAD_DUMMY: + state = TaskP_State_INVALID; + break; + case _THREAD_PRESTART: + state = TaskP_State_INACTIVE; + break; + case _THREAD_DEAD: + state = TaskP_State_DELETED; + break; + case _THREAD_SUSPENDED: + case _THREAD_PENDING: + state = TaskP_State_BLOCKED; + break; + case _THREAD_QUEUED: + state = TaskP_State_READY; + break; + default: + state = TaskP_State_INVALID; + break; + } + + /* Check if we are the currently running thread */ + if (k_current_get() == ((k_tid_t) ((struct k_thread *) task))) { + state = TaskP_State_RUNNING; + } + + return state; +} + +/* + * ======== TaskP_getCurrentTask ======== + */ +TaskP_Handle TaskP_getCurrentTask(void) +{ + return ((TaskP_Handle)k_current_get()); +} + +/* + * ======== TaskP_disableScheduler ======== + */ +uintptr_t TaskP_disableScheduler(void) +{ + k_sched_lock(); + return (0); +} + +/* + * ======== TaskP_restoreScheduler ======== + */ +void TaskP_restoreScheduler(uintptr_t key) +{ + k_sched_unlock(); +} + +/* + * ======== TaskP_yield ======== + */ +void TaskP_yield(void) +{ + k_yield(); +} + +/* + * ======== TaskP_getTaskObjectSize ======== + */ +uint32_t TaskP_getTaskObjectSize(void) +{ + return (sizeof(struct k_thread)); +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/dpl.h b/simplelink_lpf3/kernel/zephyr/dpl/dpl.h new file mode 100644 index 00000000..6d4118f3 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/dpl.h @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define MEM_ALIGN (sizeof(uint32_t)) diff --git a/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h index f701d5b0..e148095a 100644 --- a/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h +++ b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h @@ -67,6 +67,8 @@ extern "C" { #endif +#define CLOCKP_TICK_PERIOD (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) + /*! * @brief Prototype for a ClockP function. */ diff --git a/simplelink_lpf3/source/ti/drivers/dpl/EventP.h b/simplelink_lpf3/source/ti/drivers/dpl/EventP.h new file mode 100644 index 00000000..a1ea5667 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/EventP.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** ============================================================================ + * @file EventP.h + * + * @brief Event Group support + * + * Events are a collection of bits with an application-defined meaning, + * typically used for messaging or synchronisation. A task may check the state + * of a set of bits or pend on an EventP object to react to changes when they + * are posted from another context. + * + * Only one Task may pend on a single EventP object at any given time. + * + * Events are synchronous in nature, meaning that a receiving task will block or + * pend while waiting for the events to occur. When the desired events are + * received, the pending task continues its execution, as it would after a call + * to Semaphore_pend(), for example. + * + * EventP_pend is used to wait for events. The eventMask determine which + * event(s) must occur before returning from EventP_pend. The timeout parameter + * allows the task to wait until a timeout, wait indefinitely, or not wait at + * all. If waitForAll is true, the pend call will not return until all of the + * bits in eventMask are set. If it is false, any of the bits in eventMask will + * be returned. A return value of zero indicates that a timeout has occurred. A + * non-zero return value is the set of events that were active at the time the + * task was unblocked. Event bits that caused a return (either the whole + * eventMask or any individual bit, depending on waitForAll) will be cleared + * when EventP_pend returns. + * + * ============================================================================ + */ + +#ifndef ti_dpl_EventP__include +#define ti_dpl_EventP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Event object. + * + * Zephyr: 16 + */ +#define EventP_STRUCT_SIZE (16) + +/*! + * @brief EventP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific EventP objects. + */ +typedef union EventP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[EventP_STRUCT_SIZE]; +} EventP_Struct; + +/*! + * @brief Wait forever define + */ +#define EventP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define EventP_NO_WAIT (0) + +/*! + * @brief Opaque client reference to an instance of a EventP + * + * A EventP_Handle returned from create or construct represents that instance. + */ +typedef EventP_Struct *EventP_Handle; + +/*! + * @brief Create an EventP, allocating memory on the heap. + * + * EventP_create creates a new event object. EventP_create returns the + * handle of the new task object or NULL if the event could not be created. + * + * + * This API cannot be called from interrupt contexts. + * + * @retval EventP handle (NULL on failure) + */ +extern EventP_Handle EventP_create(void); + +/*! + * @brief Function to delete an EventP. + * + * @param handle A EventP_Handle returned from EventP_create + */ +extern void EventP_delete(EventP_Handle handle); + +/*! + * @brief Construct an EventP, using statically allocated memory. + * + * EventP_construct creates a new event object. EventP_construct returns the + * handle of the new task object or NULL if the event could not be created. + * + * + * This API cannot be called from interrupt contexts. + * + * @retval EventP handle (NULL on failure) + */ +extern EventP_Handle EventP_construct(EventP_Struct *obj); + +/*! + * @brief Function to destruct an EventP + * + * @param obj Pointer to a EventP_Struct object that was passed to + * EventP_construct(). + * + * @return + */ +extern void EventP_destruct(EventP_Struct *obj); + +/*! + * @brief Wait for the events listed in eventMask. + * + * EventP_pend is used to wait for events. The eventMask determine which event(s) + * must occur before returning from EventP_pend. The timeout parameter allows the + * task to wait until a timeout, wait indefinitely, or not wait at all. If + * waitForAll is true, the pend call will not return until all of the bits in + * eventMask are set. If it is false, any of the bits in eventMask will be + * returned. A return value of zero indicates that a timeout has occurred. A + * non-zero return value is the set of events in the eventMask that were active + * at the time the task was unblocked. + * + * Event bits that caused a return (either the whole eventMask or any individual + * bit, depending on waitForAll) will be cleared when EventP_pend returns. + * + * A timeout value of EventP_WAIT_FOREVER causes the task to wait indefinitely + * for matching events to be posted. A timeout value of EventP_NO_WAIT causes + * EventP_pend to return immediately. + * + * This API cannot be called from interrupt contexts. + * + * @param event Event handle + * @param eventMask Match against the events in this bitmask. + * @param waitForAll If true, only return when all matching bits are set + * @param timeout Return after this many ClockP ticks, even if there is no match + * + * @retval A bitmask containing all consumed events, or zero on timeout. + */ +extern uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, uint32_t timeout); + +/*! + * @brief Post events to an event object. + * + * EventP_post() is used to signal events. If a task is waiting for the event + * and the event conditions are met, EventP_post() unblocks the task. If no + * tasks are waiting, EventP_post() simply registers the event with the event + * object and returns. + * + * @param event Event handle + * @param eventMask Mask of eventIds to post (this must be non-zero). + */ +extern void EventP_post(EventP_Handle event, uint32_t eventMask); + +/*! + * @brief Clear events from an event object. + * + * Clears the bits in eventMask from the EventP. + * + * @param event Event handle + * @param eventMask Mask of eventIds to clear (this must be non-zero). + */ +extern void EventP_clear(EventP_Handle event, uint32_t eventMask); + +/*! + * @brief Get the current events from an event object. + * + * Returns the currently active events in an EventP without clearing them. + * + * @param event Event handle + * + * @retval Currently active events + */ +extern uint32_t EventP_get(EventP_Handle event); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_EventP__include */ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/dpl/MessageQueueP.h b/simplelink_lpf3/source/ti/drivers/dpl/MessageQueueP.h new file mode 100644 index 00000000..47aef9e6 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/MessageQueueP.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MessageQueueP.h + * + * @brief MessageQueue module for the RTOS Porting Interface + * + * MessageQueueP objects are RTOS message queues backed by OS-specific queue or + * mailbox objects. + * + * Message queues can be used for intertask communication. They support sending + * messages between tasks, and between interrupts and tasks. + * Message queues can either be allocated statically with + * #MessageQueueP_construct() or dynamically with #MessageQueueP_create(). + * + * ============================================================================ + */ + +#ifndef ti_dpl_MessageQueueP__include +#define ti_dpl_MessageQueueP__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Queue/Mailbox data structure. + * + * Zephyr: 44 + */ +#define MessageQueueP_STRUCT_SIZE (44) + +/*! + * @brief Required number of bytes of a statically allocated message queue buffer. + * + * This macro is defined to support the user in configuring the size of a message queue + * buffer. A pointer to this user defined buffer is one of the arguments of the + * #MessageQueueP_construct() function. + * The macro gives the minimal number of bytes required for the message queue. + */ + +#define MessageQueueP_BUFFER_SIZE(msgSize, msgCount) ((msgCount) * (msgSize)) + +/*! + * @brief MessageQueueP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS specific MessageQueueP objects. + */ +typedef union MessageQueueP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[MessageQueueP_STRUCT_SIZE]; +} MessageQueueP_Struct; + +/*! + * @brief Wait forever define + */ +#define MessageQueueP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define MessageQueueP_NO_WAIT (0) + +/*! + * @brief Status codes for MessageQueueP APIs + */ +typedef enum +{ + /*! API completed successfully */ + MessageQueueP_OK = 0, + /*! API failed because of a timeout */ + MessageQueueP_TIMEOUT = -1 +} MessageQueueP_Status; + +/*! + * @brief Opaque client reference to an instance of a MessageQueueP + * + * A MessageQueueP_Handle returned from #MessageQueueP_create() or + * #MessageQueueP_construct() represents that instance. It is then is used + * in the other instance based functions (e.g. #MessageQueueP_pend(), + * #MessageQueueP_post(), etc.). + */ +typedef void *MessageQueueP_Handle; + +/*! + * @brief Create a MessageQueueP, allocating memory on the heap. + * + * #MessageQueueP_create creates a new message queue object. #MessageQueueP_create + * returns the handle of the new message queue object or NULL if the message queue + * could not be created. + * + * The message queue object will be allocated on the heap - make sure you have a + * sufficiently large heap. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, configSUPPORT_DYNAMIC_ALLOCATION has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @param msgSize The size, in bytes, required to hold each item in the message queue + * @param msgCount The maximum number of items the message queue can hold at any one time + * + * @retval MessageQueueP handle (NULL on failure) + */ +extern MessageQueueP_Handle MessageQueueP_create(size_t msgSize, size_t msgCount); + +/*! + * @brief Construct a MessageQueueP from statically allocated memory. + * + * #MessageQueueP_construct creates a new message queue object. #MessageQueueP_construct + * returns the handle of the new message queue object or NULL if the message queue + * could not be created. + * + * To use #MessageQueueP_construct \a msgBuf must point to a valid preallocated memory + * array that is at least large enough to hold the maximum number of items that can be + * in the message queue at any one time. + * - When used with FreeRTOS the array size must be at least ( \a msgCount * \a msgSize) bytes. + * - When used with TI-RTOS the array size must be at least ( \a msgCount * ( \a msgSize + 8)) bytes. + * - Since the buffer must be a aligned properly, it may be necessary to 'round up' the total size + * of the buffer to the next multiple of the alignment for odd sized messages. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, configSUPPORT_STATIC_ALLOCATION has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @param queueStruct Must point to a variable that holds the message queue's data structure + * @param msgSize The size, in bytes, required to hold each item in the message queue + * @param msgCount The maximum number of items the message queue can hold at any one time + * @param msgBuf Pointer to variable that holds the message queue's data buffer + * + * @retval MessageQueueP handle (NULL on failure) + */ +MessageQueueP_Handle MessageQueueP_construct(MessageQueueP_Struct *queueStruct, + size_t msgSize, + size_t msgCount, + void *msgBuf); + +/*! + * @brief Delete a MessageQueueP. + * + * #MessageQueueP_delete finalizes and frees this previously allocated message queue + * object, setting the referenced handle to NULL. + * This function should be used when the message queue was created by the + * #MessageQueueP_create() function. + * + * \note This API cannot be called from interrupt contexts. + * + * @param handle A handle to the message queue to be deleted + */ +extern void MessageQueueP_delete(MessageQueueP_Handle handle); + +/*! + * @brief Destruct a MessageQueueP. + * + * #MessageQueueP_destruct finalizes the message queue object inside the provided structure. + * This function should be used when the message queue was constructed by the + * #MessageQueueP_construct() function. + * + * \note This API cannot be called from interrupt contexts. + * + * @param handle A handle to the message queue to be destructed + */ +extern void MessageQueueP_destruct(MessageQueueP_Handle handle); + +/*! + * @brief Receive an item from a message queue. + * + * #MessageQueueP_pend receives an item from the provided message queue. + * + * @param handle The handle to the message queue from which the item is to be received + * @param message Pointer to the buffer into which the received item will be copied + * @param timeout The maximum duration in system clock ticks a task should block waiting + * for an item to be received. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item recieved + * - #MessageQueueP_TIMEOUT: Timed out. Item was not recieved. + */ +extern MessageQueueP_Status MessageQueueP_pend(MessageQueueP_Handle handle, void *message, uint32_t timeout); + +/*! + * @brief Receive an item from a message queue without removing the item from the queue. + * + * #MessageQueueP_peek receives an item from the provided message queue without removing the + * item from the queue. + * + * @param handle The handle to the message queue from which the item is to be received + * @param message Pointer to the buffer into which the received item will be copied + * @param timeout The maximum duraton in system clock ticks a task should block waiting + * for an item to be received. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item recieved + * - #MessageQueueP_TIMEOUT: Timed out. Item was not recieved. + */ +extern MessageQueueP_Status MessageQueueP_peek(MessageQueueP_Handle handle, void *message, uint32_t timeout); + +/*! + * @brief Post an item on a message queue. + * + * #MessageQueueP_post posts an item on the provided message queue. + * + * @param handle The handle to the message queue to which the item is to be posted + * @param message Pointer to the buffer from which the item to be posted is copied + * @param timeout The maximum duraton in system clock ticks a task should block waiting + * for an item to be posted. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item posted + * - #MessageQueueP_TIMEOUT: Timed out. Item was not posted. + */ +extern MessageQueueP_Status MessageQueueP_post(MessageQueueP_Handle handle, const void *message, uint32_t timeout); + +/*! + * @brief Post an item in the front of a message queue. + * + * #MessageQueueP_postFront posts an item in the front of the provided message queue. + * + * @param handle The handle to the message queue to which the item is to be posted + * @param message Pointer to the buffer from which the item to be posted is copied + * @param timeout The maximum duration in system clock ticks a task should block waiting + * for an item to be posted. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item posted + * - #MessageQueueP_TIMEOUT: Timed out. Item was not posted. + */ +extern MessageQueueP_Status MessageQueueP_postFront(MessageQueueP_Handle handle, const void *message, uint32_t timeout); + +/*! + * @brief Get the number of messages stored in a message queue. + * + * Returns the number of messages in the specified message queue. + * + * @param handle A MessageQueueP_Handle returned from #MessageQueueP_create() + * or #MessageQueueP_construct() + * + * @retval Number of stored messages in the specified message queue + */ +extern size_t MessageQueueP_getPendingCount(MessageQueueP_Handle handle); + +/*! + * @brief Get the number of free spaces in a message queue. + * + * Returns the number of free spaces in the specified message queue. + * + * @param handle A MessageQueueP_Handle returned from #MessageQueueP_create() + * or #MessageQueueP_construct() + * + * @retval Number of free spaces in the specified message queue + */ +extern size_t MessageQueueP_getFreeCount(MessageQueueP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MessageQueueP__include */ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/dpl/TaskP.h b/simplelink_lpf3/source/ti/drivers/dpl/TaskP.h new file mode 100644 index 00000000..bc383096 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/TaskP.h @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TaskP.h + * + * @brief Task module for the RTOS Porting Interface + * + * TaskP objects are RTOS threads backed by OS-specific thread or task objects. + * Task functions will run according to the rules of the underlying scheduler, + * with higher priority tasks executing first. + * + * Tasks require a stack and a control struct to operate, which can either be + * allocated statically with TaskP_construct or dynamically with TaskP_create. + * The stack should be large enough to contain at least your deepest call stack + * plus an interrupt frame. + * + * Task Functions: + * The void* argument will be NULL by default, but you can set a value using + * TaskP_Params. Task functions should never return, as the behaviour after a + * task has returned is implementation-dependent and TaskP does not provide a + * mechanism for OS-independent task deletion. See your OS documentation for + * details. + * ============================================================================ + */ + +#ifndef ti_dpl_TaskP__include +#define ti_dpl_TaskP__include + +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Task object. + * + * Zephyr: 160 + */ +#define TaskP_STRUCT_SIZE (160) + +/*! + * @brief Number of bytes for the default stack size of any RTOS Task object. + * + */ +#define TaskP_DEFAULT_STACK_SIZE (CONFIG_DYNAMIC_THREAD_STACK_SIZE) + +/*! + * @brief TaskP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS specific TaskP objects. + */ +typedef union TaskP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[TaskP_STRUCT_SIZE]; +} TaskP_Struct; + +/*! + * @brief Enum returned from TaskP_getState(). + */ +typedef enum +{ + /*! This task is actively running */ + TaskP_State_RUNNING, + /*! The task is ready to run, but not currently running */ + TaskP_State_READY, + /*! The task is blocked */ + TaskP_State_BLOCKED, + /*! The task has been deleted */ + TaskP_State_DELETED, + /*! The task is inactive */ + TaskP_State_INACTIVE, + /*! The task is not found or in an otherwise invalid state */ + TaskP_State_INVALID +} TaskP_State; + +/*! + * @brief Opaque client reference to an instance of a TaskP + * + * A TaskP_Handle returned from create or construct represents that instance. + */ +typedef TaskP_Struct *TaskP_Handle; + +typedef struct +{ + /*! Task name. Default: NAME */ + char *name; + /*! Task function argument. Default: NULL */ + void *arg; + /*! Task priority. Higher values represent higher priorities. Default: 0 */ + int priority; + /*! Task stack size. Default: TaskP_DEFAULT_STACK_SIZE */ + size_t stackSize; + /*! @brief Task stack pointer. NULL should be used when calling TaskP_create. + * A pointer to a current stack should be passed for TaskP_construct. Default: NULL + */ + void *stack; +} TaskP_Params; + +/*! + * @brief Task function definition, passed to create and construct + * + * This function should never return. + */ +typedef void (*TaskP_Function)(void *); + +/*! + * @brief Create a TaskP, allocating memory on the heap. + * + * Creates a new TaskP and registers it with the OS scheduler. The task object + * and the entire stack will be allocated on the heap - make sure you have a + * sufficiently large heap. Stack allocation size is controlled by params. + * + * If the program is already executing a task and the new task has a higher + * priority the new task will be scheduled immediately; in this case + * TaskP_create() will not return until the new task blocks. To avoid this (for + * example when creating interdependent tasks at once) use + * TaskP_disableScheduler() and TaskP_restoreScheduler() to prevent the context + * switch. + * + * \note This API cannot be called from interrupt contexts. + * + * @retval TaskP handle (NULL on failure) + */ +extern TaskP_Handle TaskP_create(TaskP_Function fxn, const TaskP_Params *params); + +/*! + * @brief Delete a TaskP. + * + * Deletes a TaskP. + * + * \note This API cannot be called from interrupt contexts. + * + * + */ +extern void TaskP_delete(TaskP_Handle task); + +/*! + * @brief Construct a TaskP from statically allocated memory. + * + * TaskP_construct creates a new task object. TaskP_construct returns the handle + * of the new task object or NULL if the task could not be created. + * + * To use TaskP_construct you must set both point @c params.stack to a valid + * preallocated memory location of at least @c params.stackSize. + * + * \note This API cannot be called from interrupt contexts. + * + * + * @retval TaskP handle (NULL on failure) + */ +extern TaskP_Handle TaskP_construct(TaskP_Struct *obj, TaskP_Function fxn, const TaskP_Params *params); + +/*! + * @brief Destruct a TaskP. + * + * TaskP_destruct destructs a task object. + * + * \note This API cannot be called from interrupt contexts. + */ +extern void TaskP_destruct(TaskP_Struct *obj); + +/*! + * @brief Get the current state of a task handle. + * + * Returns the state of the referenced task at the time this function was + * called. The return value is not guaranteed to match the state of the task + * when the calling function tests the return value. For example, the referenced + * task might have unblocked as a result of an interrupt, but the value may + * still read TaskP_State_BLOCKED. + * + * The conversion of task states between DPL, FreeRTOS and TI-RTOS is: + * DPL: FreeRTOS: TI-RTOS: + * TaskP_State_RUNNING - eRunning - Task_Mode_RUNNING + * TaskP_State_READY - eReady - Task_Mode_READY + * TaskP_State_BLOCKED - eBlocked - Task_Mode_BLOCKED + * TaskP_State_DELETED - eDeleted - Task_Mode_TERMINATED + * TaskP_State_INACTIVE - eSuspended - Task_Mode_INACTIVE + * TaskP_State_INVALID - eInvalid - N.A + * + * + * @retval Current state of the task pointed to by the task parameter + */ +extern TaskP_State TaskP_getState(TaskP_Handle task); + +/*! + * @brief Get the currently executing task handle. + * + * \note Must be called from task context. + * + * + * @retval The handle for the calling task + */ +extern TaskP_Handle TaskP_getCurrentTask(void); + +/*! + * @brief Function to disable task scheduling + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = TaskP_disableScheduler(); + * key2 = TaskP_disableScheduler(); + * TaskP_restoreScheduler(key2); + * TaskP_restoreScheduler(key1); + * @endcode + * + * \note This API cannot be called from interrupt contexts. + * + * @return A key to pass to TaskP_restoreScheduler to re-enable the scheduler. + */ +extern uintptr_t TaskP_disableScheduler(void); + +/*! + * @brief Function to re-enable task scheduling + * + * \note This API cannot be called from interrupt contexts. + * + * @param key returned from TaskP_disableScheduler + */ +extern void TaskP_restoreScheduler(uintptr_t key); + +/*! + * @brief Create a scheduler point, yielding to equal priority tasks. + * + * Task_yield yields the processor to another task of equal priority. A task + * switch occurs when you call Task_yield if there is an equal priority task + * ready to run. + */ +extern void TaskP_yield(void); + +/*! + * @brief Initialize params structure to default values. + * + * Initialize the parameter struct with default values. + * + * @param params pointer to the task parameter struct + * + */ +extern void TaskP_Params_init(TaskP_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_TaskP__include */ \ No newline at end of file From 175878d196b857ceb950e70e0c15cd81ac62f5a7 Mon Sep 17 00:00:00 2001 From: Vebjorn Myklebust Date: Fri, 1 Mar 2024 17:10:04 +0100 Subject: [PATCH 3/7] simplelink: driver: add DPL and crypto drivers Port MutexP, SemaphoreP, SwiP, and QueueP to LPF3. Add support for interrupts of INT_CPUIRQ4, INT_LRFD_IRQ0 and INT_LRFD_IRQ1 used by the RCL (TI's radio driver for F3 devices). Add AES and ECDH SimpleLink drivers and their dependencies. Signed-off-by: Vebjorn Myklebust Signed-off-by: Lars Thalian Morstad Signed-off-by: Min Xu --- simplelink_lpf3/CMakeLists.txt | 32 +- .../kernel/zephyr/dpl/ClockP_zephyr.c | 120 +- .../kernel/zephyr/dpl/EventP_zephyr.c | 18 +- .../kernel/zephyr/dpl/HwiP_zephyr.c | 97 +- .../kernel/zephyr/dpl/MessageQueueP_zephyr.c | 18 +- .../kernel/zephyr/dpl/MutexP_zephyr.c | 94 + simplelink_lpf3/kernel/zephyr/dpl/QueueP.h | 56 + .../kernel/zephyr/dpl/QueueP_zephyr.c | 199 ++ .../kernel/zephyr/dpl/SemaphoreP_zephyr.c | 176 ++ .../kernel/zephyr/dpl/SwiP_zephyr.c | 321 +++ .../kernel/zephyr/dpl/TaskP_zephyr.c | 57 +- .../source/ti/devices/cc23x0r5/CMakeLists.txt | 2 + simplelink_lpf3/source/ti/drivers/AESCCM.c | 115 + simplelink_lpf3/source/ti/drivers/AESCCM.h | 1566 +++++++++++++ simplelink_lpf3/source/ti/drivers/AESCMAC.c | 84 + simplelink_lpf3/source/ti/drivers/AESCMAC.h | 1072 +++++++++ simplelink_lpf3/source/ti/drivers/AESCTR.c | 99 + simplelink_lpf3/source/ti/drivers/AESCTR.h | 959 ++++++++ .../source/ti/drivers/AESCTRDRBG.c | 78 + .../source/ti/drivers/AESCTRDRBG.h | 663 ++++++ simplelink_lpf3/source/ti/drivers/AESCommon.h | 206 ++ simplelink_lpf3/source/ti/drivers/AESECB.c | 83 + simplelink_lpf3/source/ti/drivers/AESECB.h | 919 ++++++++ simplelink_lpf3/source/ti/drivers/ECDH.c | 90 + simplelink_lpf3/source/ti/drivers/ECDH.h | 865 ++++++++ .../source/ti/drivers/aesccm/AESCCMLPF3.c | 1946 +++++++++++++++++ .../source/ti/drivers/aesccm/AESCCMLPF3.h | 125 ++ .../source/ti/drivers/aescmac/AESCMACLPF3.c | 948 ++++++++ .../source/ti/drivers/aescmac/AESCMACLPF3.h | 224 ++ .../source/ti/drivers/aesctr/AESCTRLPF3.c | 886 ++++++++ .../source/ti/drivers/aesctr/AESCTRLPF3.h | 278 +++ .../ti/drivers/aesctrdrbg/AESCTRDRBGXX.c | 602 +++++ .../ti/drivers/aesctrdrbg/AESCTRDRBGXX.h | 146 ++ .../source/ti/drivers/aesecb/AESECBLPF3.c | 732 +++++++ .../source/ti/drivers/aesecb/AESECBLPF3.h | 208 ++ .../source/ti/drivers/config_defaults.c | 221 ++ .../drivers/cryptoutils/aes/AESCommonLPF3.c | 519 +++++ .../drivers/cryptoutils/aes/AESCommonLPF3.h | 340 +++ .../drivers/cryptoutils/cryptokey/CryptoKey.c | 117 + .../drivers/cryptoutils/cryptokey/CryptoKey.h | 283 +++ .../cryptokey/CryptoKeyKeyStore_PSA.c | 172 ++ .../cryptokey/CryptoKeyKeyStore_PSA.h | 1787 +++++++++++++++ .../cryptokey/CryptoKeyKeyStore_PSA_helpers.c | 895 ++++++++ .../cryptokey/CryptoKeyKeyStore_PSA_helpers.h | 138 ++ .../cryptokey/CryptoKeyKeyStore_PSA_init.h | 88 + .../cryptokey/CryptoKeyKeyStore_PSA_ns.c | 277 +++ .../cryptokey/CryptoKeyKeyStore_PSA_s.c | 476 ++++ .../cryptokey/CryptoKeyKeyStore_PSA_s.h | 184 ++ .../cryptokey/CryptoKeyPlaintext.c | 114 + .../cryptokey/CryptoKeyPlaintext.h | 171 ++ .../drivers/cryptoutils/ecc/ECCInitLPF3SW.c | 96 + .../drivers/cryptoutils/ecc/ECCInitLPF3SW.h | 75 + .../ti/drivers/cryptoutils/ecc/ECCParams.h | 539 +++++ .../drivers/cryptoutils/ecc/ECCParamsLPF3SW.c | 267 +++ .../sharedresources/CryptoResourceLPF3.c | 97 + .../sharedresources/CryptoResourceLPF3.h | 69 + .../drivers/cryptoutils/utils/CryptoUtils.c | 572 +++++ .../drivers/cryptoutils/utils/CryptoUtils.h | 264 +++ .../source/ti/drivers/dma/UDMALPF3.c | 119 + .../source/ti/drivers/dma/UDMALPF3.h | 283 +++ simplelink_lpf3/source/ti/drivers/dma/dma.ld | 70 + .../source/ti/drivers/dpl/ClockP.h | 16 +- .../source/ti/drivers/dpl/MutexP.h | 214 ++ .../source/ti/drivers/dpl/SemaphoreP.h | 255 +++ simplelink_lpf3/source/ti/drivers/dpl/SwiP.h | 262 +++ 65 files changed, 23006 insertions(+), 58 deletions(-) create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/MutexP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/QueueP.h create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/QueueP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/SemaphoreP_zephyr.c create mode 100644 simplelink_lpf3/kernel/zephyr/dpl/SwiP_zephyr.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESCCM.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESCCM.h create mode 100644 simplelink_lpf3/source/ti/drivers/AESCMAC.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESCMAC.h create mode 100644 simplelink_lpf3/source/ti/drivers/AESCTR.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESCTR.h create mode 100644 simplelink_lpf3/source/ti/drivers/AESCTRDRBG.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESCTRDRBG.h create mode 100644 simplelink_lpf3/source/ti/drivers/AESCommon.h create mode 100644 simplelink_lpf3/source/ti/drivers/AESECB.c create mode 100644 simplelink_lpf3/source/ti/drivers/AESECB.h create mode 100644 simplelink_lpf3/source/ti/drivers/ECDH.c create mode 100644 simplelink_lpf3/source/ti/drivers/ECDH.h create mode 100644 simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c create mode 100644 simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h create mode 100644 simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/config_defaults.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParamsLPF3SW.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.c create mode 100644 simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.h create mode 100644 simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c create mode 100644 simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/dma/dma.ld create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/MutexP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/SemaphoreP.h create mode 100644 simplelink_lpf3/source/ti/drivers/dpl/SwiP.h diff --git a/simplelink_lpf3/CMakeLists.txt b/simplelink_lpf3/CMakeLists.txt index 2e8a384d..476745a8 100644 --- a/simplelink_lpf3/CMakeLists.txt +++ b/simplelink_lpf3/CMakeLists.txt @@ -14,10 +14,30 @@ if(CONFIG_HAS_CC23X0_SDK) zephyr_library() zephyr_library_compile_definitions(${COMPILER}) zephyr_library_sources( + # Default Simplelink configurations + source/ti/drivers/config_defaults.c + # Utils source/ti/drivers/utils/List.c # Drivers + source/ti/drivers/AESCCM.c + source/ti/drivers/AESCMAC.c + source/ti/drivers/AESCTR.c + source/ti/drivers/AESCTRDRBG.c + source/ti/drivers/AESECB.c + source/ti/drivers/ECDH.c + source/ti/drivers/aesccm/AESCCMLPF3.c + source/ti/drivers/aescmac/AESCMACLPF3.c + source/ti/drivers/aesctr/AESCTRLPF3.c + source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c + source/ti/drivers/aesecb/AESECBLPF3.c + source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c + source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c + source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c + source/ti/drivers/cryptoutils/utils/CryptoUtils.c + source/ti/drivers/dma/UDMALPF3.c + source/ti/drivers/Temperature.c source/ti/drivers/power/PowerCC23X0.c source/ti/drivers/temperature/TemperatureLPF3.c @@ -25,12 +45,18 @@ if(CONFIG_HAS_CC23X0_SDK) source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c # DPL + kernel/zephyr/dpl/MutexP_zephyr.c + kernel/zephyr/dpl/SemaphoreP_zephyr.c kernel/zephyr/dpl/ClockP_zephyr.c kernel/zephyr/dpl/HwiP_zephyr.c + kernel/zephyr/dpl/SwiP_zephyr.c kernel/zephyr/dpl/TaskP_zephyr.c kernel/zephyr/dpl/MessageQueueP_zephyr.c ) - if(CONFIG_EVENTS) - zephyr_library_sources(kernel/zephyr/dpl/EventP_zephyr.c) - endif() + if(CONFIG_EVENTS) + zephyr_library_sources(kernel/zephyr/dpl/EventP_zephyr.c) + endif() + zephyr_linker_sources(RAM_SECTIONS + ${CMAKE_CURRENT_SOURCE_DIR}/source/ti/drivers/dma/dma.ld + ) endif() diff --git a/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c index 8fb7cd5c..78a2afd9 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c @@ -4,10 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ + #include #include -#include +#include #include +#include + +/* Driverlib includes*/ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_systim.h) + +/** Max number of ClockP ticks into the future supported by this ClockP + * implementation. + * + * Under the hood, ClockP uses the SysTimer whose events trigger immediately if + * the compare value is less than 2^22 systimer ticks in the past + * (4.194sec at 1us resolution). Therefore, the max number of SysTimer ticks you + * can schedule into the future is 2^32 - 2^22 - 1 ticks (~= 4290 sec at 1us + * resolution). */ +#define ClockP_PERIOD_MAX (0xFFBFFFFFU / ClockP_TICK_PERIOD) +/** Max number of seconds into the future supported by this ClockP + * implementation. + * + * This limit affects ClockP_sleep() */ +#define ClockP_PERIOD_MAX_SEC 4290U + +/* Get the current ClockP tick value */ +#define getClockPTick() (HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U) / ClockP_TICK_PERIOD) /* * ClockP_STRUCT_SIZE in ClockP.h must be updated to match the size of this @@ -36,6 +62,58 @@ static void expiry_fxn(struct k_timer *timer_id) obj->clock_fxn(obj->arg); } +#ifdef CONFIG_DYNAMIC_DPL_OBJECTS + +/* We can't easily dynamically allocate kernel objects so we use memory slabs */ +#define DPL_MAX_CLOCKS 5 +K_MEM_SLAB_DEFINE(clock_slab, sizeof(ClockP_Obj), DPL_MAX_CLOCKS,\ + MEM_ALIGN); + +static ClockP_Obj *dpl_clock_pool_alloc() +{ + ClockP_Obj *clock_ptr = NULL; + + if (k_mem_slab_alloc(&clock_slab, (void **)&clock_ptr, K_NO_WAIT) < 0) { + + __ASSERT(0, "Increase size of DPL clock pool"); + } + return clock_ptr; +} + +static void dpl_clock_pool_free(ClockP_Obj *clock) +{ + k_mem_slab_free(&clock_slab, (void *)&clock); + + return; +} + +/* + * ======== ClockP_create ======== + */ +ClockP_Handle ClockP_create(ClockP_Fxn clkFxn, uint32_t timeout, ClockP_Params *params) +{ + ClockP_Handle handle; + + handle = (ClockP_Handle)dpl_clock_pool_alloc(); + + /* ClockP_construct will check handle for NULL, no need here */ + handle = ClockP_construct((ClockP_Struct *)handle, clkFxn, timeout, params); + + return (handle); +} + +/* + * ======== ClockP_delete ======== + */ +void ClockP_delete(ClockP_Handle handle) +{ + ClockP_destruct((ClockP_Struct *)handle); + + dpl_clock_pool_free((ClockP_Obj*) handle); +} + +#endif /* CONFIG_DYNAMIC_DPL_OBJECTS */ + /* * ======== ClockP_construct ======== */ @@ -160,6 +238,37 @@ void ClockP_stop(ClockP_Handle handle) obj->active = false; } +/* + * ======== ClockP_setFunc ======== + */ +void ClockP_setFunc(ClockP_Handle handle, ClockP_Fxn clockFxn, uintptr_t arg) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + uintptr_t key = HwiP_disable(); + + obj->clock_fxn = clockFxn; + obj->arg = arg; + + HwiP_restore(key); +} + +/* + * ======== ClockP_sleep ======== + */ +void ClockP_sleep(uint32_t sec) +{ + uint32_t ticksToSleep; + + if (sec > ClockP_PERIOD_MAX_SEC) + { + sec = ClockP_PERIOD_MAX_SEC; + } + /* Convert from seconds to number of ticks */ + ticksToSleep = (sec * USEC_PER_SEC) / ClockP_TICK_PERIOD; + k_sleep(K_TICKS(ticksToSleep)); +} + /* * ======== ClockP_usleep ======== */ @@ -186,6 +295,15 @@ bool ClockP_isActive(ClockP_Handle handle) return obj->active; } +/* + * ======== ClockP_getCpuFreq ======== + */ +void ClockP_getCpuFreq(ClockP_FreqHz *freq) +{ + freq->lo = (uint32_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; + freq->hi = 0; +} + void ClockP_destruct(ClockP_Struct *clockP) { ClockP_Obj *obj = (ClockP_Obj *)clockP->data; diff --git a/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c index ff2b7689..08720d90 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c @@ -23,25 +23,25 @@ /* We can't easily dynamically allocate kernel objects */ #define DPL_MAX_EVENTS 5 K_MEM_SLAB_DEFINE(event_slab, sizeof(struct k_event), DPL_MAX_EVENTS,\ - MEM_ALIGN); + MEM_ALIGN); static struct k_event *dpl_event_pool_alloc() { - struct k_event *event_ptr = NULL; + struct k_event *event_ptr = NULL; - if (k_mem_slab_alloc(&event_slab, (void **)&event_ptr, K_NO_WAIT) < 0) { + if (k_mem_slab_alloc(&event_slab, (void **)&event_ptr, K_NO_WAIT) < 0) { - __ASSERT(0, "Increase size of DPL event pool"); - } - return event_ptr; + __ASSERT(0, "Increase size of DPL event pool"); + } + return event_ptr; } static void dpl_event_pool_free(struct k_event *event) { - k_mem_slab_free(&event_slab, (void *)event); + k_mem_slab_free(&event_slab, (void *)event); - return; + return; } /* @@ -116,7 +116,7 @@ uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, u { /* if necessary, convert ClockP ticks to Zephyr ticks */ /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ - tickPeriod = CLOCKP_TICK_PERIOD; + tickPeriod = ClockP_TICK_PERIOD; eventTimeout = K_TICKS(timeout); } diff --git a/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c index 74f9573a..ba040d34 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c @@ -43,8 +43,15 @@ typedef struct _HwiP_Obj struct sl_isr_args *cb; } HwiP_Obj; +/* interrupt reserved for SwiP */ +int HwiP_swiPIntNum = INT_CPUIRQ1; + +static struct sl_isr_args sl_IRQ01_cb = {NULL, 0}; static struct sl_isr_args sl_IRQ03_cb = {NULL, 0}; +static struct sl_isr_args s1_IRQ04_cb = {NULL, 0}; static struct sl_isr_args sl_IRQ16_cb = {NULL, 0}; +static struct sl_isr_args s1_LRFD_IRQ0_cb = {NULL, 0}; +static struct sl_isr_args s1_LRFD_IRQ1_cb = {NULL, 0}; /* * ======== HwiP_construct ======== @@ -67,10 +74,12 @@ HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, HwiP_Fxn hwiFx } /* - * Currently only support INT_CPUIRQ3 (Oscillator ISR) and INT_CPUIRQ16 - * (Batmon ISR) + * Currently only support INT_CPUIRQ1 (SwiP), INT_CPUIRQ3 (Oscillator ISR), + * INT_CPUIRQ16 (Batmon ISR), INT_CPUIRQ4 (RCL Scheduler ISR), INT_LRFD_IRQ0 + * (RCL Command Handler ISR) and INT_LRFD_IRQ1 (RCL Dispatcher ISR) */ - __ASSERT(INT_CPUIRQ3 == interruptNum || INT_CPUIRQ16 == interruptNum, + __ASSERT((INT_CPUIRQ1 == interruptNum) || (INT_CPUIRQ3 == interruptNum) || (INT_CPUIRQ4 == interruptNum) || + (INT_CPUIRQ16 == interruptNum) || (INT_LRFD_IRQ0 == interruptNum) || (INT_LRFD_IRQ1 == interruptNum), "Unexpected interruptNum: %d\r\n", interruptNum); @@ -95,18 +104,42 @@ HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, HwiP_Fxn hwiFx switch (interruptNum) { + case INT_CPUIRQ1: + sl_IRQ01_cb.cb = hwiFxn; + sl_IRQ01_cb.arg = arg; + obj->cb = &sl_IRQ01_cb; + irq_connect_dynamic(INT_CPUIRQ1 - 16, priority, sl_isr, &sl_IRQ01_cb, 0); + break; case INT_CPUIRQ3: sl_IRQ03_cb.cb = hwiFxn; sl_IRQ03_cb.arg = arg; obj->cb = &sl_IRQ03_cb; irq_connect_dynamic(INT_CPUIRQ3 - 16, priority, sl_isr, &sl_IRQ03_cb, 0); break; + case INT_CPUIRQ4: + s1_IRQ04_cb.cb = hwiFxn; + s1_IRQ04_cb.arg = arg; + obj->cb = &s1_IRQ04_cb; + irq_connect_dynamic(INT_CPUIRQ4 - 16, priority, sl_isr, &s1_IRQ04_cb, 0); + break; case INT_CPUIRQ16: sl_IRQ16_cb.cb = hwiFxn; sl_IRQ16_cb.arg = arg; obj->cb = &sl_IRQ16_cb; irq_connect_dynamic(INT_CPUIRQ16 - 16, priority, sl_isr, &sl_IRQ16_cb, 0); break; + case INT_LRFD_IRQ0: + s1_LRFD_IRQ0_cb.cb = hwiFxn; + s1_LRFD_IRQ0_cb.arg = arg; + obj->cb = &s1_LRFD_IRQ0_cb; + irq_connect_dynamic(INT_LRFD_IRQ0 - 16, priority, sl_isr, &s1_LRFD_IRQ0_cb, 0); + break; + case INT_LRFD_IRQ1: + s1_LRFD_IRQ1_cb.cb = hwiFxn; + s1_LRFD_IRQ1_cb.arg = arg; + obj->cb = &s1_LRFD_IRQ1_cb; + irq_connect_dynamic(INT_LRFD_IRQ1 - 16, priority, sl_isr, &s1_LRFD_IRQ1_cb, 0); + break; default: return (NULL); } @@ -182,3 +215,61 @@ void HwiP_destruct(HwiP_Struct *hwiP) obj->cb->arg = (uintptr_t)NULL; obj->cb = NULL; } + +void HwiP_setPriority(int interruptNum, uint32_t priority) +{ + /* + * On CM0+, dynamically changing priorities is not allowed. In order to + * change priority of an interrupt, after it already has been enabled, the + * following must be done: + * - Disable the interrupt whose priority needs to be updated + * - Set the priority to be at the desired priority level + * - Re-enable the interrupt. + * + * These steps are all handled by IntSetPriority(). + * + * HwiP_disable/enable here serves the purpose of deferring the handling of + * user interrupts until the priority of interruptNum has been changed. This + * prevents another interrupt from changing the global state potentially + * altering the outcome of this function. + */ + + uintptr_t key = HwiP_disable(); + IntSetPriority((uint32_t)interruptNum, (uint8_t)priority); + HwiP_restore(key); +} + +/* + * ======== HwiP_inISR ======== + */ +bool HwiP_inISR(void) +{ + bool stat; + + if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0) + { + /* Not currently in an ISR */ + stat = false; + } + else + { + stat = true; + } + + return (stat); +} + +/* + * ======== HwiP_inSwi ======== + */ +bool HwiP_inSwi(void) +{ + uint32_t intNum = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk; + if (intNum == HwiP_swiPIntNum) + { + /* Currently in a Swi */ + return (true); + } + + return (false); +} \ No newline at end of file diff --git a/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c index 83375a94..58d9d471 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/MessageQueueP_zephyr.c @@ -26,21 +26,21 @@ K_MEM_SLAB_DEFINE(msgq_slab, sizeof(struct k_msgq) , DPL_MAX_MSGQS, MEM_ALIGN); static struct k_msgq *dpl_msgq_pool_alloc() { - struct k_msgq *msgq_ptr = NULL; + struct k_msgq *msgq_ptr = NULL; - if (k_mem_slab_alloc(&msgq_slab, (void **)&msgq_ptr, K_NO_WAIT) < 0) { + if (k_mem_slab_alloc(&msgq_slab, (void **)&msgq_ptr, K_NO_WAIT) < 0) { - __ASSERT(0, "Increase size of DPL message queue pool"); - } - return msgq_ptr; + __ASSERT(0, "Increase size of DPL message queue pool"); + } + return msgq_ptr; } static void dpl_msgq_pool_free(struct k_msgq *msgq) { - k_mem_slab_free(&msgq_slab, (void *)msgq); + k_mem_slab_free(&msgq_slab, (void *)msgq); - return; + return; } /* @@ -119,7 +119,7 @@ MessageQueueP_Status MessageQueueP_pend(MessageQueueP_Handle handle, void *messa { /* If necessary, convert ClockP ticks to Zephyr ticks */ /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ - tickPeriod = CLOCKP_TICK_PERIOD; + tickPeriod = ClockP_TICK_PERIOD; msgTimeout = K_TICKS(timeout); } int status = k_msgq_get((struct k_msgq*) handle, message, msgTimeout); @@ -167,7 +167,7 @@ MessageQueueP_Status MessageQueueP_post(MessageQueueP_Handle handle, const void { /* if necessary, convert ClockP ticks to Zephyr ticks */ /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */ - tickPeriod = CLOCKP_TICK_PERIOD; + tickPeriod = ClockP_TICK_PERIOD; if (tickPeriod != CONFIG_SYS_CLOCK_TICKS_PER_SEC) { timeUS = timeout * (uint64_t)tickPeriod; diff --git a/simplelink_lpf3/kernel/zephyr/dpl/MutexP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/MutexP_zephyr.c new file mode 100644 index 00000000..54456ea5 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/MutexP_zephyr.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/* + * Zephyr kernel object pools: + * + * This bit of code enables the simplelink host driver, which assumes dynamic + * allocation of kernel objects (semaphores, mutexes, hwis), to be + * more easily ported to Zephyr (which supports static allocation). + * + * It leverages the Zephyr memory slab, enabling us to define a mutex object + * pool for use by the SimpleLink host driver. + */ + +/* Define a Mutex pool: */ +#define DPL_MAX_MUTEXES 4 /* From simplelink driver code inspection */ +K_MEM_SLAB_DEFINE(mutex_slab, sizeof(struct k_mutex), DPL_MAX_MUTEXES, MEM_ALIGN); + +static struct k_mutex *dpl_mutex_pool_alloc() +{ + struct k_mutex *mutex_ptr = NULL; + + if (k_mem_slab_alloc(&mutex_slab, (void **)&mutex_ptr, K_NO_WAIT) < 0) + { + /* + * We assert, as this is a logic error, due to a change in # + * of mutexes needed by the simplelink driver. In that case, + * the mutex pool must be increased programmatically to match. + */ + __ASSERT(0, "Increase size of DPL mutex pool"); + } + return mutex_ptr; +} + +static MutexP_Status dpl_mutex_pool_free(struct k_mutex *mutex) +{ + k_mem_slab_free(&mutex_slab, (void **)&mutex); + return MutexP_OK; +} + +MutexP_Handle MutexP_create(MutexP_Params *params) +{ + struct k_mutex *mutex; + + ARG_UNUSED(params); + + mutex = dpl_mutex_pool_alloc(); + __ASSERT(mutex, "MutexP_create failed\r\n"); + + if (mutex) + { + k_mutex_init(mutex); + } + return ((MutexP_Handle)mutex); +} + +void MutexP_delete(MutexP_Handle handle) +{ + /* No way in Zephyr to "reset" the lock, so just re-init: */ + k_mutex_init((struct k_mutex *)handle); + + dpl_mutex_pool_free((struct k_mutex *)handle); +} + +uintptr_t MutexP_lock(MutexP_Handle handle) +{ + unsigned int key = 0; + int retval; + + retval = k_mutex_lock((struct k_mutex *)handle, K_FOREVER); + __ASSERT(retval == 0, "MutexP_lock: retval: %d\r\n", retval); + + return ((uintptr_t)key); +} + +void MutexP_Params_init(MutexP_Params *params) +{ + params->callback = NULL; +} + +void MutexP_unlock(MutexP_Handle handle, uintptr_t key) +{ + ARG_UNUSED(key); + + k_mutex_unlock((struct k_mutex *)handle); +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/QueueP.h b/simplelink_lpf3/kernel/zephyr/dpl/QueueP.h new file mode 100644 index 00000000..844a094e --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/QueueP.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP.h ======== + */ + +typedef struct _QueueP_Elem +{ + struct _QueueP_Elem *volatile next; + struct _QueueP_Elem *volatile prev; +} QueueP_Elem; + +typedef struct _QueueP_Obj +{ + QueueP_Elem elem; +} QueueP_Obj; + +typedef QueueP_Obj *QueueP_Handle; + +void QueueP_init(QueueP_Obj *obj); +uintptr_t QueueP_head(QueueP_Obj *obj); +uintptr_t QueueP_next(QueueP_Elem *qelem); +uintptr_t QueueP_prev(QueueP_Elem *qelem); +uintptr_t QueueP_get(QueueP_Obj *obj); +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem); +void QueueP_remove(QueueP_Elem *qelem); +bool QueueP_empty(QueueP_Obj *obj); diff --git a/simplelink_lpf3/kernel/zephyr/dpl/QueueP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/QueueP_zephyr.c new file mode 100644 index 00000000..a1340ed3 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/QueueP_zephyr.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP_zephyr.c ======== + */ + +#include +#include "QueueP.h" + +/* + * ======== QueueP_init ======== + */ +void QueueP_init(QueueP_Obj *obj) +{ + obj->elem.next = obj->elem.prev = &(obj->elem); +} + +/* + * ======== QueueP_empty ======== + */ +bool QueueP_empty(QueueP_Obj *obj) +{ + return (obj->elem.next == &(obj->elem)); +} + +/* + * ======== QueueP_get ======== + */ +uintptr_t QueueP_get(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.next; + + obj->elem.next = elem->next; + elem->next->prev = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); +} + +/* + * ======== QueueP_getTail ======== + */ +uintptr_t QueueP_getTail(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.prev; + + obj->elem.prev = elem->prev; + elem->prev->next = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); +} + +/* + * ======== QueueP_head ======== + */ +uintptr_t QueueP_head(QueueP_Obj *obj) +{ + return ((uintptr_t)(obj->elem.next)); +} + +/* + * ======== elemClear ======== + */ +void QueueP_elemClear(QueueP_Elem *qelem) +{ + qelem->next = qelem->prev = qelem; +} + +/* + * ======== insert ======== + */ +void QueueP_insert(QueueP_Elem *qelem, QueueP_Elem *elem) +{ + QueueP_put((QueueP_Obj *)qelem, elem); +} + +/* + * ======== next ======== + */ +uintptr_t QueueP_next(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->next); +} + +/* + * ======== QueueP_prev ======== + */ +uintptr_t QueueP_prev(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->prev); +} + +/* + * ======== QueueP_put ======== + */ +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = &(obj->elem); + elem->prev = obj->elem.prev; + obj->elem.prev->next = elem; + obj->elem.prev = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_putHead ======== + */ +void QueueP_putHead(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->prev = &(obj->elem); + elem->next = obj->elem.next; + obj->elem.next->prev = elem; + obj->elem.next = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_remove ======== + */ +void QueueP_remove(QueueP_Elem *qelem) +{ +#if defined(__IAR_SYSTEMS_ICC__) + QueueP_Elem *temp; + temp = qelem->next; + qelem->prev->next = temp; + temp = qelem->prev; + qelem->next->prev = temp; +#else + qelem->prev->next = qelem->next; + qelem->next->prev = qelem->prev; +#endif +} + +/* + * ======== isQueued ======== + */ +bool QueueP_isQueued(QueueP_Elem *qelem) +{ + if ((qelem->prev == qelem) && (qelem->next == qelem)) + { + return (false); + } + else + { + return (true); + } +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/SemaphoreP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/SemaphoreP_zephyr.c new file mode 100644 index 00000000..9ab3c551 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/SemaphoreP_zephyr.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/* + * Zephyr kernel object pools: + * + * This bit of code enables the simplelink host driver, which assumes dynamic + * allocation of kernel objects (semaphores, mutexes, hwis), to be + * more easily ported to Zephyr (which supports static allocation). + * + * It leverages the Zephyr memory slab, enabling us to define a semaphore + * object pool for use by the SimpleLink host driver. + */ +#define DPL_MAX_SEMAPHORES 14 /* (user.h:MAX_CONCURRENT_ACTIONS+4) = 14 */ +K_MEM_SLAB_DEFINE(sem_slab, sizeof(struct k_sem), DPL_MAX_SEMAPHORES, MEM_ALIGN); + +static struct k_sem *dpl_sem_pool_alloc() +{ + struct k_sem *sem_ptr = NULL; + + if (k_mem_slab_alloc(&sem_slab, (void **)&sem_ptr, K_NO_WAIT) < 0) + { + /* + * We assert, as this is a logic error, due to a change in # + * of semaphores needed by the simplelink driver. In that case, + * the sem pool must be increased programmatically to match. + */ + __ASSERT(0, "Increase size of DPL semaphore pool"); + } + return sem_ptr; +} + +static SemaphoreP_Status dpl_sem_pool_free(struct k_sem *sem) +{ + k_mem_slab_free(&sem_slab, (void **)&sem); + + return SemaphoreP_OK; +} + +/* timeout comes in and out in ticks */ +static k_timeout_t dpl_convert_timeout(uint32_t timeout) +{ + switch (timeout) + { + case SemaphoreP_NO_WAIT: + return K_NO_WAIT; + case SemaphoreP_WAIT_FOREVER: + return K_FOREVER; + default: + return K_TICKS(timeout); + } +} + +SemaphoreP_Handle SemaphoreP_create(unsigned int count, SemaphoreP_Params *params) +{ + unsigned int limit = UINT_MAX; + struct k_sem *sem; + + if (params) + { + limit = (params->mode == SemaphoreP_Mode_BINARY) ? 1 : UINT_MAX; + } + + sem = dpl_sem_pool_alloc(); + if (sem) + { + k_sem_init(sem, count, limit); + } + + return (SemaphoreP_Handle)sem; +} + +SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_create(count, ¶ms)); +} + +void SemaphoreP_delete(SemaphoreP_Handle handle) +{ + k_sem_reset((struct k_sem *)handle); + + (void)dpl_sem_pool_free((struct k_sem *)handle); +} + +void SemaphoreP_Params_init(SemaphoreP_Params *params) +{ + params->mode = SemaphoreP_Mode_COUNTING; + params->callback = NULL; +} + +/* + * The SimpleLink driver calls this function with a timeout of 0 to "clear" + * the SyncObject, rather than calling dpl_SyncObjClear() directly. + * See: /source/ti/drivers/net/wifi/source/driver.h + * #define SL_DRV_SYNC_OBJ_CLEAR(pObj) + * (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT); + * + * So, we claim (via simplelink driver code inspection), that SyncObjWait + * will *only* be called with timeout == 0 if the intention is to clear the + * semaphore: in that case, we just call k_sem_reset. + */ +SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) +{ + int retval; + + if (0 == timeout) + { + k_sem_reset((struct k_sem *)handle); + retval = SemaphoreP_OK; + } + else + { + retval = k_sem_take((struct k_sem *)handle, dpl_convert_timeout(timeout)); + __ASSERT_NO_MSG(retval != -EBUSY); + retval = (retval >= 0) ? SemaphoreP_OK : SemaphoreP_TIMEOUT; + } + return retval; +} + +void SemaphoreP_post(SemaphoreP_Handle handle) +{ + k_sem_give((struct k_sem *)handle); +} + +SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, unsigned int count, SemaphoreP_Params *params) +{ + unsigned int limit = UINT_MAX; + struct k_sem *sem; + + if (params) + { + limit = (params->mode == SemaphoreP_Mode_BINARY) ? 1 : UINT_MAX; + } + + sem = (struct k_sem *)handle; + if (sem) + { + k_sem_init(sem, count, limit); + } + + return (SemaphoreP_Handle)sem; +} + +SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, unsigned int count) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_construct(handle, count, ¶ms)); +} + +void SemaphoreP_destruct(SemaphoreP_Struct *semP) +{ + struct k_sem *sem; + + sem = (struct k_sem *)semP->data; + if (sem) + { + k_sem_reset(sem); + } +} diff --git a/simplelink_lpf3/kernel/zephyr/dpl/SwiP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/SwiP_zephyr.c new file mode 100644 index 00000000..35126584 --- /dev/null +++ b/simplelink_lpf3/kernel/zephyr/dpl/SwiP_zephyr.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +#include "QueueP.h" + +/* Lowest priority interrupt for CC23X0 */ +#define INT_PRI_LEVEL7 0x000000C0 + +#define NUMPRI 4 + +typedef enum +{ + SwiP_State_Idle = 0, + SwiP_State_Posted, + SwiP_State_Running, + SwiP_State_Interrupted +} SwiP_State; + +typedef uint32_t SwiP_LockState; + +enum +{ + SwiP_LockState_Locked, + SwiP_LockState_Unlocked +}; + +typedef struct SwiP_Obj +{ + QueueP_Elem elem; + QueueP_Handle readyList; + SwiP_Params params; + SwiP_Fxn fxn; + uint32_t trigger; + uint32_t state; +} SwiP_Obj; + +extern bool HwiP_inSwi(void); + +static void SwiP_handleHwi(); + +static const SwiP_Params SwiP_defaultParams = { + .arg0 = (uintptr_t)NULL, + .arg1 = (uintptr_t)NULL, + .priority = ~0, /* max priority */ + .trigger = 0, +}; + +static volatile int SwiP_readyMask; +static volatile SwiP_LockState SwiP_lockState; +static volatile uint32_t SwiP_currentTrigger; +static volatile bool SwiP_schedulerRunning; +static volatile bool SwiP_initialized = false; +static HwiP_Struct SwiP_hwiStruct; +static QueueP_Obj SwiP_readyList[NUMPRI]; + +/* don't call with n == 0 */ +static int maxbit(int n) +{ + int mask = 1 << (NUMPRI - 1); + int max = NUMPRI - 1; + + while (mask) + { + if (n & mask) + { + return max; + } + max--; + mask >>= 1; + } + + return 0; +} + +/* + * ======== SwiP_Params_init ======== + */ +void SwiP_Params_init(SwiP_Params *params) +{ + /* structure copy */ + *params = SwiP_defaultParams; +} + +/* + * ======== SwiP_construct ======== + */ +SwiP_Handle SwiP_construct(SwiP_Struct *handle, SwiP_Fxn swiFxn, SwiP_Params *params) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + HwiP_Params hwiParams; + uintptr_t hwiKey; + uint32_t priority; + int i; + + if (handle != NULL) + { + hwiKey = HwiP_disable(); + + if (SwiP_initialized == false) + { + for (i = 0; i < NUMPRI; i++) + { + QueueP_init(&SwiP_readyList[i]); + } + SwiP_readyMask = 0; + SwiP_currentTrigger = 0; + SwiP_lockState = SwiP_LockState_Unlocked; + SwiP_schedulerRunning = false; + + HwiP_Params_init(&hwiParams); + hwiParams.priority = INT_PRI_LEVEL7; // use the lowest priority + HwiP_construct(&SwiP_hwiStruct, HwiP_swiPIntNum, SwiP_handleHwi, &hwiParams); + + SwiP_initialized = true; + } + + HwiP_restore(hwiKey); + + if (params == NULL) + { + params = (SwiP_Params *)&SwiP_defaultParams; + } + + if (params->priority == (~0)) + { + priority = NUMPRI - 1; + } + else + { + priority = params->priority; + } + + if (priority >= NUMPRI) + { + return NULL; + } + else + { + QueueP_init((QueueP_Obj *)&swi->elem); + swi->params = *params; + swi->params.priority = priority; + swi->fxn = swiFxn; + swi->trigger = swi->params.trigger; + swi->state = SwiP_State_Idle; + swi->readyList = &SwiP_readyList[priority]; + } + } + + return ((SwiP_Handle)swi); +} + +/* + * ======== SwiP_destruct ======== + */ +void SwiP_destruct(SwiP_Struct *handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* if on SwiP_readyList, remove it */ + QueueP_remove(&swi->elem); + if (QueueP_empty(swi->readyList)) + { + SwiP_readyMask &= ~(1 << swi->params.priority); + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_disable ======== + */ +uintptr_t SwiP_disable(void) +{ + uintptr_t previousHwiState = HwiP_disable(); + + SwiP_LockState previousLockState = SwiP_lockState; + SwiP_lockState = SwiP_LockState_Locked; + + HwiP_restore(previousHwiState); + + return previousLockState; +} + +/* + * This is a non-preemptive fixed-priority scheduler implementation. + * It runs with interrupts disabled, but enables them for each swi. + */ +void SwiP_dispatch(uintptr_t hwiKey) +{ + SwiP_Obj *swi; + int maxpri; + + while (SwiP_readyMask && (SwiP_lockState == SwiP_LockState_Unlocked)) + { + maxpri = maxbit(SwiP_readyMask); + swi = (SwiP_Obj *)QueueP_get(&SwiP_readyList[maxpri]); + + if (QueueP_empty(&SwiP_readyList[maxpri])) + { + SwiP_readyMask &= ~(1 << maxpri); + } + + /* + * Prepare the swi for execution. The trigger has to be saved + * because the swi might re-post itself with another trigger value. + */ + swi->state = SwiP_State_Running; + SwiP_currentTrigger = swi->trigger; + swi->trigger = swi->params.trigger; + + /* run the swi with interrupts enabled */ + HwiP_restore(hwiKey); + swi->fxn(swi->params.arg0, swi->params.arg1); + hwiKey = HwiP_disable(); + + /* If the swi didn't get re-posted, set it to idle now */ + if (swi->state == SwiP_State_Running) + { + swi->state = SwiP_State_Idle; + } + } + + /* Scheduler was set to running immediately after posting the interrupt */ + SwiP_schedulerRunning = false; +} + +static void SwiP_handleHwi() +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_dispatch(hwiKey); + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_getTrigger ======== + */ +uint32_t SwiP_getTrigger() +{ + return (SwiP_currentTrigger); +} + +/* + * ======== SwiP_or ======== + */ +void SwiP_or(SwiP_Handle handle, uint32_t mask) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + swi->trigger |= mask; + + HwiP_restore(hwiKey); + SwiP_post(swi); +} + +/* + * ======== SwiP_post ======== + */ +void SwiP_post(SwiP_Handle handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* (Re-)post an swi only once */ + if (swi->state != SwiP_State_Posted) + { + swi->state = SwiP_State_Posted; + + QueueP_put(&SwiP_readyList[swi->params.priority], (QueueP_Elem *)&swi->elem); + SwiP_readyMask |= 1 << swi->params.priority; + } + + /* Activate the scheduler when not already running */ + if ((SwiP_schedulerRunning == false) && (SwiP_lockState == SwiP_LockState_Unlocked)) + { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_restore ======== + */ +void SwiP_restore(uintptr_t key) +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_lockState = key; + + /* Determine whether the scheduler needs to run */ + if (SwiP_readyMask && (key == SwiP_LockState_Unlocked) && (SwiP_schedulerRunning == false)) + { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_inISR ======== + */ +bool SwiP_inISR(void) +{ + return (HwiP_inSwi()); +} \ No newline at end of file diff --git a/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c index 8bec7831..4ac0a481 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/TaskP_zephyr.c @@ -26,24 +26,24 @@ #ifdef DYNAMIC_THREADS /* Space for thread objects */ K_MEM_SLAB_DEFINE(task_slab, sizeof(struct k_thread), CONFIG_DYNAMIC_THREAD_POOL_SIZE,\ - MEM_ALIGN); + MEM_ALIGN); static struct k_thread *dpl_task_pool_alloc() { - struct k_thread *task_ptr = NULL; + struct k_thread *task_ptr = NULL; - if (k_mem_slab_alloc(&task_slab, (void **)&task_ptr, K_NO_WAIT) < 0) { + if (k_mem_slab_alloc(&task_slab, (void **)&task_ptr, K_NO_WAIT) < 0) { - __ASSERT(0, "Increase size of DPL task pool"); - } + __ASSERT(0, "Increase size of DPL task pool"); + } printk("Slabs used: %d / %d \n", task_slab.info.num_used, task_slab.info.num_blocks); - return task_ptr; + return task_ptr; } static void dpl_task_pool_free(struct k_thread *task) { - k_mem_slab_free(&task_slab, (void *)task); - return; + k_mem_slab_free(&task_slab, (void *)task); + return; } #endif /* CONFIG_DYNAMIC_DPL_OBJECTS */ @@ -179,31 +179,28 @@ TaskP_State TaskP_getState(TaskP_Handle task) TaskP_State state; switch (((struct k_thread*) task)->base.thread_state) { - case _THREAD_DUMMY: - state = TaskP_State_INVALID; - break; - case _THREAD_PRESTART: - state = TaskP_State_INACTIVE; - break; - case _THREAD_DEAD: - state = TaskP_State_DELETED; - break; - case _THREAD_SUSPENDED: - case _THREAD_PENDING: - state = TaskP_State_BLOCKED; - break; - case _THREAD_QUEUED: - state = TaskP_State_READY; - break; - default: - state = TaskP_State_INVALID; - break; - } + case _THREAD_DUMMY: + state = TaskP_State_INVALID; + break; + case _THREAD_DEAD: + state = TaskP_State_DELETED; + break; + case _THREAD_SUSPENDED: + case _THREAD_PENDING: + state = TaskP_State_BLOCKED; + break; + case _THREAD_QUEUED: + state = TaskP_State_READY; + break; + default: + state = TaskP_State_INVALID; + break; + } /* Check if we are the currently running thread */ if (k_current_get() == ((k_tid_t) ((struct k_thread *) task))) { - state = TaskP_State_RUNNING; - } + state = TaskP_State_RUNNING; + } return state; } diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt index f3893b95..95af65df 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt @@ -37,6 +37,8 @@ zephyr_include_directories( zephyr_library() zephyr_library_sources( + driverlib/aes_gcc.s + driverlib/udma.c driverlib/gpio.c driverlib/interrupt.c driverlib/lrfd.c diff --git a/simplelink_lpf3/source/ti/drivers/AESCCM.c b/simplelink_lpf3/source/ti/drivers/AESCCM.c new file mode 100644 index 00000000..f62cf5cb --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCCM.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCCM.c ======== + * + * This file contains default values for the AESCCM_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCCM_Config AESCCM_config[]; +extern const uint_least8_t AESCCM_count; + +const AESCCM_Params AESCCM_defaultParams = { + .returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCCM_Params_init ======== + */ +void AESCCM_Params_init(AESCCM_Params *params) +{ + *params = AESCCM_defaultParams; +} + +/* + * ======== AESCCM_open ======== + */ +__attribute__((weak)) AESCCM_Handle AESCCM_open(uint_least8_t index, const AESCCM_Params *params) +{ + DebugP_assert(index < AESCCM_count); + + AESCCM_Config *config = (AESCCM_Config *)&AESCCM_config[index]; + return AESCCM_construct(config, params); +} + +/* + * ======== AESCCM_Operation_init ======== + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_Operation)); +} + +/* + * ======== AESCCM_OneStepOperation_init ======== + */ +void AESCCM_OneStepOperation_init(AESCCM_OneStepOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_OneStepOperation)); +} + +/* + * ======== AESCCM_SegmentedAADOperation_init ======== + */ +void AESCCM_SegmentedAADOperation_init(AESCCM_SegmentedAADOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedAADOperation)); +} + +/* + * ======== AESCCM_SegmentedDataOperation_init ======== + */ +void AESCCM_SegmentedDataOperation_init(AESCCM_SegmentedDataOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedDataOperation)); +} + +/* + * ======== AESCCM_SegmentedFinalizeOperation_init ======== + */ +void AESCCM_SegmentedFinalizeOperation_init(AESCCM_SegmentedFinalizeOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedFinalizeOperation)); +} diff --git a/simplelink_lpf3/source/ti/drivers/AESCCM.h b/simplelink_lpf3/source/ti/drivers/AESCCM.h new file mode 100644 index 00000000..3cc5d1fb --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCCM.h @@ -0,0 +1,1566 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCCM.h + * + * @brief AESCCM driver header + * + * @anchor ti_drivers_AESCCM_Overview + * # Overview # + * The Counter with CBC-MAC (CCM) mode of operation is a generic + * authenticated encryption block cipher mode. It can be used with + * any block cipher. + * AESCCM combines CBC-MAC with an AES block cipher in CTR mode of operation. + * + * This combination of block cipher modes enables CCM to encrypt messages of any + * length and not only multiples of the block cipher block size. + * + * CTR provides confidentiality. The defined application of CBC-MAC provides + * message integrity and authentication. + * + * AESCCM has the following inputs and outputs: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AES-CCM input and output parameters
EncryptionDecryption
Input
Shared AES key Shared AES key
NonceNonce
CleartextCiphertext
MAC
AAD (optional)AAD (optional)
Output
CiphertextCleartext
MAC
+ * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * The nonce is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the nonce value must be unique. That is, the set of + * nonce values used with any given key must not contain any duplicate + * values. Using the same nonce for two different messages encrypted + * with the same key destroys the security properties. + * + * The length of the nonce determines the maximum number of messages that may + * be encrypted and authenticated before you must regenerate the key. + * Reasonable session key rotation schemes will regenerate the key before reaching + * this limit. + * There is a trade-off between the nonce-length and the maximum length of + * the plaintext to encrypt and authenticate per nonce. This is because + * CTR concatenates the nonce and an internal counter into one 16-byte + * IV. The counter is incremented after generating an AES-block-sized + * pseudo-random bitstream. This bitstream is XOR'd with the plaintext. + * The counter would eventually roll over for a sufficiently long message. + * This is must not happen. Hence, the longer the nonce and the more messages + * you can send before needing to rotate the key, the shorter the + * lengths of individual messages sent may be. The minimum and maximum + * nonce length defined by the CCM standard provide for both a reasonable + * number of messages before key rotation and a reasonable maximum message length. + * Check NIST SP 800-38C for details. + * + * The optional additional authentication data (AAD) is authenticated + * but not encrypted. Thus, the AAD is not included in the AES-CCM output. + * It can be used to authenticate packet headers. + * + * After the encryption operation, the ciphertext contains the encrypted + * data. The message authentication code (MAC) is also provided. + * + * # CCM Variations # + * The AESCCM driver supports both classic CCM as defined by NIST SP 800-38C and + * the CCM* variant used in IEEE 802.15.4. + * CCM* allows for unauthenticated encryption using CCM by permitting a MAC length + * of 0. It also imposes the requirement that the MAC length be embedded in + * the nonce used for each message if the MAC length varies within the protocol + * using CCM*. + * + * @anchor ti_drivers_AESCCM_Usage + * # Usage # + * + * ## Before starting a CCM operation # + * + * Before starting a CCM operation, the application must do the following: + * - Call AESCCM_init() to initialize the driver + * - Call AESCCM_Params_init() to initialize the AESCCM_Params to default values. + * - Modify the AESCCM_Params as desired + * - Call AESCCM_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESCCM API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the appropriate AESCCM operation struct using the relevant + * operation init functions and set all fields. For example, one-step (one-shot + * or single call) operations should initialize AESCCM_Operation or + * AESCCM_OneStepOperation using AESCCM_Operation_init() or + * AESCCM_OneStepOperation_init(). For multi-step (segmented or multiple call) + * operations, AESCCM_SegmentedAADOperation must be initialized and set when + * processing AAD. AESCCM_SegmentedDataOperation must be initialized and set when + * dealing with payload data (plaintext or ciphertext). AESCCM_SegmentedFinalizeOperation + * must be initialized and set when finalizing the segmented operation. + * + * ## Starting a CCM operation # + * + * The AESCCM_oneStepEncrypt and AESCCM_oneStepDecrypt functions do a CCM operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. However, they require all AAD and plaintext or ciphertext data to be + * available to the function at the start of the call. + * All devices support single call operations. + * + * When performing a decryption operation with AESCCM_oneStepDecrypt(), the MAC is + * automatically verified. + * + * ## After the CCM operation completes # + * + * After the CCM operation completes, the application should either start another operation + * or close the driver by calling AESCCM_close() + * + * @anchor ti_drivers_AESCCM_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCCM_Synopsis_Code + * @code + * + * // Import AESCCM Driver definitions + * #include + * + * // Define name for AESCCM channel index + * #define AESCCM_INSTANCE 0 + * + * AESCCM_init(); + * + * handle = AESCCM_open(AESCCM_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCCM_OneStepOperation + * AESCCM_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * AESCCM_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCCM_Examples + * ## Examples + * + * ### Single call CCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t nonce[] = "Thisisanonce"; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * handle = AESCCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation operation; + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * + * ### Single call CCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0}; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESCCM_OneStepOperation operation; + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * decryptionResult = AESCCM_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * + * @endcode + * + * ### Multi-step CCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t keyingMaterial[16] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t aad[8] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t plaintext[23] = {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}; + * uint8_t nonce[13] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t mac[8]; + * uint8_t ciphertext[sizeof(plaintext)]; + * + * // The ciphertext should be the following after the encryption operation: + * // {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * // 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * // 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84} + * + * handle = AESCCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * encryptionResult = AESCCM_setupEncrypt(handle, &cryptoKey, sizeof(aad), sizeof(plaintext), sizeof(mac)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * encryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = plaintext; + * segmentedDataOperation.output = ciphertext; + * // One should pass in data that is a block-sized multiple length + * // until passing in the last segment of data. + * // In that case, the input length simply needs to be a non-zero value. + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * segmentedDataOperation.input = plaintext + AES_BLOCK_SIZE; + * segmentedDataOperation.output = ciphertext + AES_BLOCK_SIZE; + * segmentedDataOperation.inputLength = sizeof(plaintext) - AES_BLOCK_SIZE; + * + * encryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&egmentedFinalizeOperation); + * segmentedFinalizeOperation.input = plaintext; + * segmentedFinalizeOperation.output = ciphertext; + * + * // You can finalize with no new data + * segmentedFinalizeOperation.inputLength = 0; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * encryptionResult = AESCCM_finalizeEncrypt(handle, &segmentedFinalizeOperation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * + * ### Multi-step CCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0}; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * if(operationType == AESCCM_OPERATION_TYPE_DECRYPT || + * operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + * { + * // Callback fxn only used for one-shot operations + * // Use operation->oneStepOperation + * } + * else if(operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + * operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) + * { + * // Callback fxn only used for segmented AAD operations + * // Use operation->segmentedAADOperation + * } + * else if(operationType == AESCCM_OP_TYPE_DATA_DECRYPT || + * operationType == AESCCM_OP_TYPE_DATA_ENCRYPT) + * { + * // Callback fxn only used for segmented data operations + * // Use operation->segmentedDataOperation + * } + * else + * { + * // Callback fxn only used for segmented finalize operations + * // Use operation->segmentedFinalizeOperation + * } + * } + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * decryptionResult = AESCCM_setupDecrypt(handle, &cryptoKey, 0, 0, 0); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // setLengths must be called if the AAD, input, and MAC lengths aren't provided in setupXXXX. + * decryptionResult = AESCCM_setLengths(handle, sizeof(aad), sizeof(ciphertext), sizeof(mac)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * decryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = ciphertext; + * segmentedDataOperation.output = plaintext; + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&egmentedFinalizeOperation); + * segmentedFinalizeOperation.input = ciphertext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.output = plaintext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.inputLength = sizeof(ciphertext) - AES_BLOCK_SIZE; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * + * decryptionResult = AESCCM_finalizeDecrypt(handle, &segmentedFinalizeOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * @endcode + * + * ### Multi-step CCM* decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0}; + * + * // CCM* allows for unauthenticated encryption using CCM by allowing a MAC length of 0 + * uint8_t macLength = 0; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * if(operationType == AESCCM_OPERATION_TYPE_DECRYPT || + * operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + * { + * // Callback fxn only used for one-shot operations + * // Use operation->oneStepOperation + * } + * else if(operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + * operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) + * { + * // Callback fxn only used for segmented AAD operations + * // Use operation->segmentedAADOperation + * } + * else if(operationType == AESCCM_OP_TYPE_DATA_DECRYPT || + * operationType == AESCCM_OP_TYPE_DATA_ENCRYPT) + * { + * // Callback fxn only used for segmented data operations + * // Use operation->segmentedDataOperation + * } + * else + * { + * // Callback fxn only used for segmented finalize operations + * // Use operation->segmentedFinalizeOperation + * } + * } + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * decryptionResult = AESCCM_setupDecrypt(handle, &cryptoKey, 0, 0, 0); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // setLengths must be called if the AAD, input, and MAC lengths aren't provided in setupXXXX. + * decryptionResult = AESCCM_setLengths(handle, sizeof(aad), sizeof(ciphertext), macLength); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * decryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = ciphertext; + * segmentedDataOperation.output = plaintext; + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&egmentedFinalizeOperation); + * segmentedFinalizeOperation.input = ciphertext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.output = plaintext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.inputLength = sizeof(ciphertext) - AES_BLOCK_SIZE; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = macLength; + * + * decryptionResult = AESCCM_finalizeDecrypt(handle, &segmentedFinalizeOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESCCM__include +#define ti_drivers_AESCCM__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCCM status code reservation offset. + * AESCCM driver implementations should offset status codes with + * AESCCM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCCMXYZ_STATUS_ERROR0 AESCCM_STATUS_RESERVED - 0 + * #define AESCCMXYZ_STATUS_ERROR1 AESCCM_STATUS_RESERVED - 1 + * #define AESCCMXYZ_STATUS_ERROR2 AESCCM_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCCM_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return AESCCM_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCCM_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return AESCCM_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCCM_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCCM driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCCM_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCCM_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief An error status code returned if the MAC provided by the application for + * a decryption operation does not match the one calculated during the operation. + * + * This code is returned by AESCCM_oneStepDecrypt() or AESCCM_finalizeDecrypt() + * if the verification of the MAC fails. + */ +#define AESCCM_STATUS_MAC_INVALID AES_STATUS_MAC_INVALID + +/*! + * @brief The operation requested is not supported either by the target hardware + * or the driver implementation. + */ +#define AESCCM_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCCM_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCCM_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCCM driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESCCM Global configuration + * + * The AESCCM_Config structure contains a set of pointers used to characterize + * the AESCCM driver implementation. + * + * This structure needs to be defined before calling AESCCM_init() and it must + * not be changed thereafter. + * + * @sa AESCCM_init() + */ +typedef AESCommon_Config AESCCM_Config; + +/*! + * @brief A handle that is returned from an AESCCM_open() call. + */ +typedef AESCCM_Config *AESCCM_Handle; + +/*! + * @brief The way in which CCM function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all CCM operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCCM functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCCM_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCCM_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCCM_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCCM_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * CCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCCM_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the CCM operation goes + * on in the background. CCM operation results are available + * after the function returns. + */ + AESCCM_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while CCM + * operation goes on in the background. CCM operation results + * are available after the function returns. + */ +} AESCCM_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CCM operation. + */ +typedef enum +{ + AESCCM_MODE_ENCRYPT = 1, + AESCCM_MODE_DECRYPT = 2, +} AESCCM_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and authenticating/verifying a message for one-step operations. + */ +typedef struct +{ + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t *nonce; /*!< A buffer containing a nonce. Nonces must be unique to + * each CCM operation and may not be reused. If + * nonceInternallyGenerated is set, the nonce will be + * generated by #AESCCM_oneStepEncrypt() and copied to this buffer. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of the total \c aad in bytes. Either \c aadLength or + * \c inputLength must be non-zero. Unlike this field in + * AESCCM_SegmentedAADOperation, the length doesn't need to be + * block-aligned. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Either \c aadLength or + * \c inputLength must be non-zero. Unlike this field in + * AESCCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * Max length supported may be limited depending on the return behavior. + */ + uint8_t nonceLength; /*!< Length of \c nonce in bytes. + * Valid nonce lengths are [7, 8, ... 13]. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ + bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into #AESCCM_oneStepEncrypt() + * will be overwritten with a randomly generated nonce. + * Not supported by all implementations. + */ +} AESCCM_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for + * authenticating/verifying additional data in a segmented operation. + * Must be updated for each add AAD step of a segmented operation. + */ +typedef struct +{ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + size_t aadLength; /*!< Length of the \c aad in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of + * AAD is being passed in. In that case, this value doesn't + * need to be an AES block-sized multiple. + */ +} AESCCM_SegmentedAADOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message in a segmented operation. Must be updated between each + * add data step of a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of data is being + * passed in. In that case, this value doesn't need to a block size multiple. + * Max length supported may be limited depending on the return behavior. + */ +} AESCCM_SegmentedDataOperation; + +/*! + * @brief Struct containing the parameters required for finalizing an + * encryption/decryption and authentication/verification of a message + * in a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Can be 0 if finalizing + * without new payload data. Unlike this field in + * AESCCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * Max length supported may be limited depending on the return behavior. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ +} AESCCM_SegmentedFinalizeOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESCCM_Operation. + * Existing code should be refactored to use AESCCM_OneStepOperation. + * This reference may be removed at some point in the future + * + */ +typedef AESCCM_OneStepOperation AESCCM_Operation; + +/*! + * @brief Union containing a reference to a one step, + * segmented AAD, segmented data, or segmented finalize operation. + */ +typedef union AESCCM_OperationUnion +{ + AESCCM_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESCCM_SegmentedAADOperation segmentedAADOperation; /* Segmented AAD operation element of the operation union */ + AESCCM_SegmentedDataOperation segmentedDataOperation; /* Segmented data operation element of the operation union */ + AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; /* Segmented finalize operation element of the + operation union */ +} AESCCM_OperationUnion; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCCM_OPERATION_TYPE_ENCRYPT = 1, /* Fields 1 and 2 are for backward compatibility */ + AESCCM_OPERATION_TYPE_DECRYPT = 2, + AESCCM_OP_TYPE_ONESTEP_ENCRYPT = 1, /* Names changed to _OP_TYPE_ to avoid MISRA deviation from first 31 chars not + being unique */ + AESCCM_OP_TYPE_ONESTEP_DECRYPT = 2, + AESCCM_OP_TYPE_AAD_ENCRYPT = 3, + AESCCM_OP_TYPE_AAD_DECRYPT = 4, + AESCCM_OP_TYPE_DATA_ENCRYPT = 5, + AESCCM_OP_TYPE_DATA_DECRYPT = 6, + AESCCM_OP_TYPE_FINALIZE_ENCRYPT = 7, + AESCCM_OP_TYPE_FINALIZE_DECRYPT = 8, +} AESCCM_OperationType; + +/*! + * @brief The definition of a callback function used by the AESCCM driver + * when used in ::AESCCM_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CCM operation. + * + * @param returnValue The result of the CCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operationUnion A pointer to an operation union. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCCM_CallbackFxn)(AESCCM_Handle handle, + int_fast16_t returnValue, + AESCCM_OperationUnion *operation, + AESCCM_OperationType operationType); + +/*! + * @brief CCM Parameters + * + * CCM Parameters used with the AESCCM_open() call. Default values for + * these parameters are set using AESCCM_Params_init(). + * + * @sa AESCCM_Params_init() + */ +typedef struct +{ + AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCCM_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCCM_Params; + +/*! + * @brief Default AESCCM_Params structure + * + * @sa #AESCCM_Params_init() + */ +extern const AESCCM_Params AESCCM_defaultParams; + +/*! + * @brief This function initializes the CCM module. + * + * @pre The AESCCM_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CCM driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCCM_init(void); + +/*! + * @brief Function to initialize the #AESCCM_Params struct to its defaults + * + * @param params An pointer to #AESCCM_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCCM_Params_init(AESCCM_Params *params); + +/*! + * @brief This function opens a given CCM peripheral. + * + * @pre CCM controller has been initialized using #AESCCM_init() + * + * @param [in] index Logical peripheral number for the CCM indexed into + * the AESCCM_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESCCM_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #AESCCM_init() + * @sa #AESCCM_close() + */ +AESCCM_Handle AESCCM_open(uint_least8_t index, const AESCCM_Params *params); + +/*! + * @brief Function to close a CCM peripheral specified by the CCM handle + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle + * + * @sa #AESCCM_open() + */ +void AESCCM_close(AESCCM_Handle handle); + +/*! + * @brief Function to prepare a segmented AESCCM encryption operation. + * + * This function sets up a segmented AESCCM encryption operation. + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] macLength Size of the MAC in bytes. This value + * can be 0 and later provided by + * #AESCCM_setLengths(). + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); + +/*! + * @brief Function to prepare a segmented AESCCM decryption operation. + * + * This function sets up a segmented AESCCM decryption operation. + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] macLength Size of the MAC in bytes. This value + * can be 0 and later provided by + * #AESCCM_setLengths(). + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); + +/*! + * @brief Function to set the lengths of the message, additional data, and MAC. + * + * This function declares the lengths of the message, + * additional authenticated data (AAD), and MAC. + * + * @note This function doesn't have to be called if the lengths above were + * specified in #AESCCM_setupEncrypt() or #AESCCM_setupDecrypt(). + * + * @pre #AESCCM_setupEncrypt() or #AESCCM_setupDecrypt() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] aadLength Size of the non-encrypted AAD in bytes + * + * @param [in] plaintextLength Size of the plaintext or ciphertext to encrypt or decrypt in bytes + * + * @param [in] macLength Size of the MAC in bytes + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_setNonce() + * @post #AESCCM_generateNonce() + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength); + +/*! + * @brief Function to set the nonce for an AES CCM segmented operation. + * + * @pre #AESCCM_setupEncrypt(), #AESCCM_setupDecrypt(), or #AESCCM_setLengths() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] nonce Pointer to the buffer containing the nonce + * + * @param [in] nonceLength The length of the nonce in bytes + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength); + +/*! + * @brief Function to generate a nonce for an AES CCM segmented encryption operation. + * + * @pre #AESCCM_setupEncrypt() or #AESCCM_setLengths() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] nonce Pointer to the buffer where the generated nonce + * is to be written to + * + * @param [in] nonceSize The length of the nonce buffer in bytes + * + * @param [out] nonceLength The length of the nonce actually written if the + * operation was successful + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength); + +/*! + * @brief Adds a segment of @a aad with a @a length in bytes to the generated MAC. + * The length must be a multiple of a block size, 16 bytes, unless passing in the last + * chunk of AAD. + * + * #AESCCM_addAAD() may be called an arbitrary number of times before continuing the operation with + * #AESCCM_addData(), #AESCCM_finalizeEncrypt() or #AESCCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @note This function must not be called after passing data to encrypt or + * decrypt with #AESCCM_addData(). + * + * @warning When decrypting, do not use the output until + * #AESCCM_finalizeDecrypt() succeeds. + * + * @pre #AESCCM_setNonce() or #AESCCM_generateNonce() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented AAD CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + * @post #AESCCM_finalizeEncrypt() + * @post #AESCCM_finalizeDecrypt() + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation); + +/*! + * @brief Adds a segment of @a data with a @a length in bytes to the plaintext/ciphertext + * output and generated MAC. The length must be a multiple of a block size, 16 bytes, unless + * passing in the last chunk of payload data. + * + * #AESCCM_addData() may be called an arbitrary number of times before finishing the operation + * with #AESCCM_finalizeEncrypt() or #AESCCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @warning When decrypting, do not use the output until + * #AESCCM_finalizeDecrypt() succeeds. + * + * @pre #AESCCM_setNonce() or #AESCCM_generateNonce() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented data CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESCCM_addData() + * @post #AESCCM_finalizeEncrypt() + * @post #AESCCM_finalizeDecrypt() + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation); + +/*! + * @brief Finalize the MAC and ciphertext. + * + * This function finalizes the encryption of a dataset earlier provided + * by calls to #AESCCM_addAAD() and #AESCCM_addData() and creates a message + * authentication code. If additional data needs to be encrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * The resulting output is a message authentication code and ciphertext. + * + * @pre #AESCCM_addAAD() or #AESCCM_addData() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented finalize CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS In ::AESCCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESCCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Finalize the MAC and plaintext and verify it. + * + * This function finalizes the decryption of a dataset earlier provided + * by calls to AESCCM_addAAD() and AESCCM_addData() and verifies a provided message + * authentication code. If additional data needs to be decrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield a corrupted MAC comparison. + * + * The resulting output is a verification return code and plaintext. + * + * @pre #AESCCM_addAAD() or #AESCCM_addData() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented finalize CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS In ::AESCCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESCCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was verified successfully. In ::AESCCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_MAC_INVALID The provided MAC did not match the recomputed one. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Function to initialize an #AESCCM_Operation struct to its defaults + * + * @deprecated This function should be replaced by calls to operation-specific + * init functions. + * + * @param [in] operationStruct A pointer to an #AESCCM_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_OneStepOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_OneStepOperation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCCM_OneStepOperation_init(AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedAADOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedAADOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedAADOperation_init(AESCCM_SegmentedAADOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedDataOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedDataOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedDataOperation_init(AESCCM_SegmentedDataOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedFinalizeOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedFinalizeOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedFinalizeOperation_init(AESCCM_SegmentedFinalizeOperation *operationStruct); + +/*! + * @brief Function to perform an AESCCM encryption + authentication operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre #AESCCM_open() or #AESCCM_construct() and #AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCCM_oneStepDecrypt() + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to perform an AESCCM decryption + verification operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre #AESCCM_open() or #AESCCM_construct() and #AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_MAC_INVALID The provided MAC did not match the recomputed one. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCCM_oneStepEncrypt() + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Cancels an ongoing AESCCM operation. + * + * Asynchronously cancels an AESCCM operation. Only available when using + * AESCCM_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCCM_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCCM_STATUS_SUCCESS The operation was canceled, or the operation had already completed. + * @retval #AESCCM_STATUS_ERROR The driver was not in callback mode, or the operation's output + * and generated MAC weren't properly cleared. + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle); + +/** + * @brief Constructs a new AESCCM object + * + * Unlike #AESCCM_open(), #AESCCM_construct() does not require the hwAttrs and + * object to be allocated in a #AESCCM_Config array that is indexed into. + * Instead, the #AESCCM_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESCCM_Config describing the location of the object and hwAttrs. + * + * @param params #AESCCM_Params to configure the driver instance. + * + * @return Returns a #AESCCM_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCCM__include */ diff --git a/simplelink_lpf3/source/ti/drivers/AESCMAC.c b/simplelink_lpf3/source/ti/drivers/AESCMAC.c new file mode 100644 index 00000000..f9df7fd2 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCMAC.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCMAC.c ======== + * + * This file contains default values for the AESCMAC_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCMAC_Config AESCMAC_config[]; +extern const uint_least8_t AESCMAC_count; + +const AESCMAC_Params AESCMAC_defaultParams = { + .returnBehavior = AESCMAC_RETURN_BEHAVIOR_BLOCKING, + .operationalMode = AESCMAC_OPMODE_CMAC, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCMAC_Params_init ======== + */ +void AESCMAC_Params_init(AESCMAC_Params *params) +{ + *params = AESCMAC_defaultParams; +} + +/* + * ======== AESCMAC_open ======== + */ +__attribute__((weak)) AESCMAC_Handle AESCMAC_open(uint_least8_t index, const AESCMAC_Params *params) +{ + DebugP_assert(index < AESCMAC_count); + + AESCMAC_Config *config = (AESCMAC_Config *)&AESCMAC_config[index]; + return AESCMAC_construct(config, params); +} + +/* + * ======== AESCMAC_Operation_init ======== + */ +void AESCMAC_Operation_init(AESCMAC_Operation *operation) +{ + memset(operation, 0x00, sizeof(AESCMAC_Operation)); +} diff --git a/simplelink_lpf3/source/ti/drivers/AESCMAC.h b/simplelink_lpf3/source/ti/drivers/AESCMAC.h new file mode 100644 index 00000000..af1b179b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCMAC.h @@ -0,0 +1,1072 @@ +/* + * Copyright (c) 2019-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! + * @file AESCMAC.h + * + * @brief AESCMAC (CMAC and CBC-MAC) driver header + * + * @anchor ti_drivers_AESCMAC_Overview + * # Overview # + * The Cipher-based Message Authentication Code (CMAC) and Cipher Block Chaining + * Message Authentication Code (CBC-MAC) are generic block cipher modes of + * operation. They can be used with any block cipher but this driver + * implementation uses AES. + * + * Both CMAC and CBC-MAC create a message authentication code from a message of + * any practical length to provide authenticity and integrity assurances. + * CMAC is recommended over CBC-MAC because CBC-MAC is not secure for variable + * length messages. + * + * ## CBC-MAC Drawbacks # + * CBC-MAC is only secure for fixed-length messages. Any single key must only be + * used for messages of a fixed and known length. The CMAC algorithm, which + * is based on a variation of CBC-MAC at its core, was developed to address that + * security deficiency and is the MAC algorithm recommended by NIST. + * + * @anchor ti_drivers_AESCMAC_Usage + * # CMAC Usage # + * ## Before starting a CMAC operation # + * + * Before starting a CMAC operation, the application must do the following: + * - Call #AESCMAC_init() to initialize the driver + * - Call #AESCMAC_Params_init() to initialize the #AESCMAC_Params to default values. + * - Modify the #AESCMAC_Params as desired + * - Call #AESCMAC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The CMAC API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * + * ## Starting a CMAC operation # + * + * The #AESCMAC_oneStepSign and #AESCMAC_oneStepVerify functions perform a CMAC operation + * in a single call. They will always be the most highly optimized routines with the + * least overhead and the fastest runtime. However, they require all plaintext + * or ciphertext to be available to the function at the start of the call. + * All devices support single call operations. + * + * ## After the CMAC operation completes # + * + * After the CMAC operation completes, the application should either start + * another operation or close the driver by calling #AESCMAC_close(). + * + * @anchor ti_drivers_AESCMAC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCMAC_Synopsis_Code + * @code + * // Import CMAC Driver definitions + * #include + * + * // Define name for CMAC channel index + * #define AESCMAC_INSTANCE 0 + * + * AESCMAC_init(); + * + * handle = AESCMAC_open(AESCMAC_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Initialize the operation + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * AESCMAC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCMAC_Examples + * ## Examples + * + * ### Single call CMAC authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t mac[16]; + * + * ... + * + * CryptoKey cryptoKey; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * AESCMAC_Handle handle = AESCMAC_open(0, NULL); + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * int_fast16_t result = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * // 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C + * + * AESCMAC_close(handle); + * + * @endcode + * + * ### Single call CMAC verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t expectedMac[16] = {0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C}; + * + * void cmacCallback(AESCMAC_Handle handle, + * int_fast16_t returnValue) { + * if (returnValue != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * void cmacStartFunction(void) { + * AESCMAC_Handle handle; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * CryptoKey cryptoKey; + * int_fast16_t verificationResult; + * + * AESCMAC_Params_init(¶ms); + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = cmacCallback; + * handle = AESCMAC_open(0, ¶ms); + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = expectedMac; + * operation.macLength = sizeof(expectedMac); + * verificationResult = AESCMAC_oneStepVerify(handle, &operation, &cryptoKey); + * + * if (verificationResult != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * // do other things while CMAC operation completes in the background + * } + * @endcode + * + * ### Multi-step CMAC signature with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t message[40] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11}; + * uint8_t mac[16]; + * + * CryptoKey cryptoKey; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * AESCMAC_Handle handle = AESCMAC_open(0, NULL); + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * + * // Set up multi-step sign. + * int_fast16_t result = AESCMAC_setupSign(handle, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * size_t initialSegmentSize = AES_BLOCK_SIZE; + * + * // Add first segment of data. + * operation.input = input; + * operation.inputLength = initialSegmentSize; // Must be a non-zero multiple of the block size (16-bytes) unless + * finalizing. result = AESCMAC_addData(handle, &operation); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // Finalize with the last segment of data. + * operation.input = &input[initialSegmentSize]; + * operation.inputLength = sizeof(input) - initialSegmentSize; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * result = AESCMAC_finalize(handle, &operation); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0xaa, 0xf3, 0xd8, 0xf1, 0xde, 0x56, 0x40, 0xc2, + * // 0x32, 0xf5, 0xb1, 0x69, 0xb9, 0xc9, 0x11, 0xe6 + * ... + * + * AESCMAC_close(handle); + * + * @endcode + * + * @anchor ti_drivers_AESCBCMAC_Usage + * # CBC-MAC Usage # + * ## Before starting a CBC-MAC operation # + * + * Before starting a CBC-MAC operation, the application must do the following: + * - Call #AESCMAC_init() to initialize the driver + * - Call #AESCMAC_Params_init() to initialize the #AESCMAC_Params to + * default values. + * - Set #AESCMAC_Params.operationalMode to #AESCMAC_OPMODE_CBCMAC. + * - Modify the #AESCMAC_Params as desired + * - Call #AESCMAC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESCMAC API can handle all types of + * CryptoKey. However, not all device-specific implementations support all + * types of CryptoKey. Devices without a key store will not support + * CryptoKeys with keying material stored in a key store for example. All + * devices support plaintext CryptoKeys. + * - Initialize the #AESCMAC_Operation using #AESCMAC_Operation_init() + * and set all length, key, and buffer fields. + * + * ## Starting a CBC-MAC operation # + * + * The #AESCMAC_oneStepSign and #AESCMAC_oneStepVerify functions perform a + * CBC-MAC operation in a single call. They will always be the most highly + * optimized routines with the least overhead and the fastest runtime. However, + * they require all plaintext or ciphertext to be available to the function at + * the start of the call. All devices support single call operations. + * + * ## After the CBC-MAC operation completes # + * + * After the CBC-MAC operation completes, the application should either start + * another operation or close the driver by calling #AESCMAC_close(). + * + * @anchor ti_drivers_AESCBCMAC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCBCMAC_Synopsis_Code + * @code + * // Import AESCMAC Driver definitions + * #include + * + * // Define name for AESCMAC channel index + * #define AESCMAC_INSTANCE 0 + * + * AESCMAC_init(); + * + * AESCMAC_Params params; + * + * AESCMAC_Params_init(¶ms); + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(AESCMAC_INSTANCE, ¶ms); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCMAC_Operation + * AESCMAC_Operation_init(&operation); + * operation.input = plaintext; + * operation.inputLength = sizeof(plaintext); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation); + * + * AESCMAC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCBCMAC_Examples + * ## Examples + * + * ### One step AES CBC-MAC signature with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t signResult; + * + * // For example purposes only. + * // Test vector derived from RFC 3602 Case #2 + * uint8_t plaintext[32] = {0x56, 0x2F, 0x15, 0x9A, 0x69, 0x0C, 0x3B, 0x2F, + * 0xD5, 0xBA, 0xB0, 0x62, 0x56, 0x23, 0x61, 0x57, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * uint8_t mac[16]; + * uint8_t keyingMaterial[16] = {0xC2, 0x86, 0x69, 0x6D, 0x88, 0x7C, 0x9A, 0xA0, + * 0x61, 0x1B, 0xBB, 0x3E, 0x20, 0x25, 0xA4, 0x5A}; + * + * // The MAC should equal the following after the operation: + * // 0x75, 0x86, 0x60, 0x2D, 0x25, 0x3C, 0xFF, 0xF9, + * // 0x1B, 0x82, 0x66, 0xBE, 0xA6, 0xD6, 0x1A, 0xB1 + * + * AESCMAC_Params_init(¶ms); + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation operation; + * AESCMAC_Operation_init(&operation); // Optional as all struct members will be set before use. + * + * operation.input = plaintext; + * operation.inputLength = sizeof(plaintext); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (signResult == AESCMAC_STATUS_SUCCESS) { + * // signature is available in mac[] buffer. + * } + * else { + * // handle error + * } + * + * AESCMAC_close(handle); + * + * @endcode + * + * + * ### Multi-step AES CBC-MAC verify with plaintext CryptoKey in polling return mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t retVal; + * + * // For example purposes only. + * // Test vector derived from RFC 3602 Case #2 + * uint8_t plaintext[32] = {0x56, 0x2F, 0x15, 0x9A, 0x69, 0x0C, 0x3B, 0x2F, + * 0xD5, 0xBA, 0xB0, 0x62, 0x56, 0x23, 0x61, 0x57, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * uint8_t mac[16] = {0x75, 0x86, 0x60, 0x2D, 0x25, 0x3C, 0xFF, 0xF9, + * 0x1B, 0x82, 0x66, 0xBE, 0xA6, 0xD6, 0x1A, 0xB1} + * uint8_t keyingMaterial[16] = {0xC2, 0x86, 0x69, 0x6D, 0x88, 0x7C, 0x9A, 0xA0, + * 0x61, 0x1B, 0xBB, 0x3E, 0x20, 0x25, 0xA4, 0x5A}; + * + * AESCMAC_Params_init(¶ms) + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_POLLING; + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation operation; + * AESCMAC_Operation_init(&operation); // Optional as all struct members will be set before use. + * + * retVal = AESCMAC_setupVerify(handle, &cryptoKey); + * + * if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext; + * operation.inputLength = AES_BLOCK_SIZE; // Must be a non-zero multiple of the block size (16-bytes) unless + * finalizing. + * // Note: MAC pointer only needs to be set when finalizing operation. + * + * retVal = AESCMAC_addData(handle, &operation); + * + * if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.inputLength = AES_BLOCK_SIZE; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * retVal = AESCMAC_finalize(handle, &operation); + * + * // retVal should be AESCMAC_STATUS_SUCCESS to indicate that the signature + * // verification passed. + * + * if (retVal == AESCMAC_STATUS_MAC_INVALID) { + * // handle invalid MAC + * } + * else if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCMAC_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_AESCMAC__include +#define ti_drivers_AESCMAC__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common CMAC status code reservation offset. + * CMAC driver implementations should offset status codes with + * #AESCMAC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCMACXYZ_STATUS_ERROR0 AESCMAC_STATUS_RESERVED - 0 + * #define AESCMACXYZ_STATUS_ERROR1 AESCMAC_STATUS_RESERVED - 1 + * #define AESCMACXYZ_STATUS_ERROR2 AESCMAC_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCMAC_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCMAC_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCMAC_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCMAC_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCMAC_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * CMAC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCMAC_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The MAC verification failed. + * + * Functions return #AESCMAC_STATUS_MAC_INVALID if the MAC computed + * for the provided (key, message) pair did not match the MAC provided. + */ +#define AESCMAC_STATUS_MAC_INVALID AES_STATUS_MAC_INVALID + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCMAC_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCMAC_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCMAC_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input. + * + * AESCMAC driver implementations may have restrictions on the alignment of + * input data due to performance limitations of the hardware. + */ +#define AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief CMAC Global configuration + * + * The #AESCMAC_Config structure contains a set of pointers used to characterize + * the CMAC driver implementation. + * + * This structure needs to be defined before calling #AESCMAC_init() and it must + * not be changed thereafter. + * + * @sa #AESCMAC_init() + */ +typedef AESCommon_Config AESCMAC_Config; + +/*! + * @brief A handle that is returned from an #AESCMAC_open() call. + */ +typedef AESCMAC_Config *AESCMAC_Handle; + +/*! + * @brief The return behavior of AESCMAC functions + * + * Not all AESCMAC operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCMAC functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |---------------------------------|-------|-------|-------| + * |AESCMAC_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCMAC_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCMAC_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCMAC_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * MAC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCMAC_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the MAC operation goes + * on in the background. MAC operation results are available + * after the function returns. + */ + AESCMAC_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while MAC + * operation goes on in the background. MAC operation results + * are available after the function returns. + */ +} AESCMAC_ReturnBehavior; + +/*! + * @brief Defines the operation modes for the AESCMAC driver. + * + * By default, the driver will use CMAC to sign and verify messages. + * To use CBC-MAC instead of CMAC, set the operationalMode in + * #AESCMAC_Params accordingly before calling #AESCMAC_open or + * #AESCMAC_construct. The operational mode persists throughout + * the existance of the driver instance. + */ +typedef enum +{ + AESCMAC_OPMODE_CMAC = 1, /*!< CMAC operational mode */ + AESCMAC_OPMODE_CBCMAC = 2, /*!< CBC-MAC operational mode */ +} AESCMAC_OperationalMode; + +/*! + * @brief Struct containing the parameters required for signing or verifying a message. + */ +typedef struct +{ + uint8_t *input; /*!< - Sign: Pointer to the input message to + * be authenticated. + * - Verify: Pointer to the input message to be + * verified. + */ + uint8_t *mac; /*!< - Sign: Pointer to the output buffer to write + * the generated MAC. Buffer size must be + * at least equal to @a macLength. + * - Verify: Pointer to the input MAC to be + * used for verification. + */ + size_t inputLength; /*!< Length of the input message in bytes. + * May be zero for CMAC but must be non-zero for CBC-MAC. + * See function descriptions for further restrictions. + * Max length supported may be limited depending on the return behavior. + */ + size_t macLength; /*!< Length of the MAC in bytes. + * Must be <= 16. A length of < 8 is not recommended and + * should severely restrict MAC recomputation attempts. + * See appendix A of NIST SP800-38b for more information. + */ +} AESCMAC_Operation; + +/*! + * @brief Mask for the operation code. + */ +#define AESCMAC_OP_CODE_MASK 0x0F /* bits 0-3 */ + +/*! + * @brief Enum for the operation codes supported by the driver. + */ +typedef enum +{ + AESCMAC_OP_CODE_ONE_STEP = 0, + AESCMAC_OP_CODE_SEGMENTED, + AESCMAC_OP_CODE_FINALIZE +} AESCMAC_OperationCode; + +/*! + * @brief Flag indicating a sign operation. If this bit is not set, then it + * is a verify operation. + */ +#define AESCMAC_OP_FLAG_SIGN 0x10 /* bit 4 */ + +/*! + * @brief Mask for all valid operation flags. + */ +#define AESCMAC_OP_FLAGS_MASK (AESCMAC_OP_FLAG_SIGN | AESCMAC_OP_FLAG_VERIFY) + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCMAC_OP_TYPE_SIGN = AESCMAC_OP_CODE_ONE_STEP | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_VERIFY = AESCMAC_OP_CODE_ONE_STEP, + AESCMAC_OP_TYPE_SEGMENTED_SIGN = AESCMAC_OP_CODE_SEGMENTED | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_SEGMENTED_VERIFY = AESCMAC_OP_CODE_SEGMENTED, + AESCMAC_OP_TYPE_FINALIZE_SIGN = AESCMAC_OP_CODE_FINALIZE | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_FINALIZE_VERIFY = AESCMAC_OP_CODE_FINALIZE +} AESCMAC_OperationType; + +/*! + * @brief The definition of a callback function used by the AESCMAC driver + * when used in ::AESCMAC_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the AESCMAC operation. + * + * @param returnValue The result of the AESCMAC operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation Pointer to an operation struct. + * + * @param operationType Indicates which operation the callback refers to. + */ +typedef void (*AESCMAC_CallbackFxn)(AESCMAC_Handle handle, + int_fast16_t returnValue, + AESCMAC_Operation *operation, + AESCMAC_OperationType operationType); + +/*! + * @brief AESCMAC Parameters + * + * CMAC Parameters are used to with the #AESCMAC_open() or #AESCMAC_construct() call. + * Default values for these parameters are set using #AESCMAC_Params_init(). + * + * @sa #AESCMAC_Params_init() + */ +typedef struct +{ + AESCMAC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCMAC_OperationalMode operationalMode; /*!< CMAC or CBC-MAC operational mode */ + AESCMAC_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCMAC_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCMAC_Params; + +/*! + * @brief Default #AESCMAC_Params structure + * + * @sa #AESCMAC_Params_init() + */ +extern const AESCMAC_Params AESCMAC_defaultParams; + +/*! + * @brief Initializes the CMAC module. + * + * @pre The AESCMAC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CMAC driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCMAC_init(void); + +/*! + * @brief Initializes the #AESCMAC_Params struct to its defaults + * + * @param [in] params Pointer to #AESCMAC_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCMAC_RETURN_BEHAVIOR_BLOCKING + * operationalMode = AESCMAC_OPMODE_CMAC + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCMAC_Params_init(AESCMAC_Params *params); + +/*! + * @brief Initializes an #AESCMAC_Operation struct to its defaults + * + * @param [in] operation Pointer to an #AESCMAC_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCMAC_Operation_init(AESCMAC_Operation *operation); + +/*! + * @brief Opens a given AESCMAC peripheral. + * + * @note #AESCMAC_Params @a operationalMode may be set to enable CBC-MAC + * mode but the default is CMAC mode + * + * @pre AESCMAC driver has been initialized using #AESCMAC_init() + * + * @param [in] index Logical peripheral number for the CMAC indexed into + * the AESCMAC_config table + * + * @param [in] params Pointer to a parameter block, if NULL it will use + * default values + * + * @return An #AESCMAC_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCMAC_init() + * @sa #AESCMAC_close() + */ +AESCMAC_Handle AESCMAC_open(uint_least8_t index, const AESCMAC_Params *params); + +/*! + * @brief Closes a AESCMAC peripheral specified by the CMAC handle + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param handle AESCMAC handle + * + * @sa #AESCMAC_open() + * @sa #AESCMAC_construct() + */ +void AESCMAC_close(AESCMAC_Handle handle); + +/*! + * @brief Prepares a segmented AESCMAC sign operation + * + * This function sets up a segmented AESCMAC sign operation. + * After a segmented operation is setup, it must be completed + * with #AESCMAC_finalize or cancelled with #AESCMAC_cancelOperation + * before another operation can be started. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. Segmented + * data may now be added. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + * + * @sa #AESCMAC_setupVerify() + */ +int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key); + +/*! + * @brief Prepares a segmented AESCMAC verify operation + * + * This function sets up a segmented AESCMAC verify operation. + * After a segmented operation is setup, it must be completed + * with #AESCMAC_finalize or cancelled with #AESCMAC_cancelOperation + * before another operation can be started. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. Segmented + * data may now be added. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + * + * @sa #AESCMAC_setupSign() + */ +int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key); + +/*! + * @brief Adds data to the current segmented operation + * + * The @a inputLength must be a non-zero multiple of the block size (16-bytes). + * #AESCMAC_addData() may be called an arbitrary number of times before + * finishing the operation with #AESCMAC_finalize(). + * + * This function blocks until the final MAC been computed. + * It returns immediately when ::AESCMAC_RETURN_BEHAVIOR_CALLBACK is set. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_setupSign() or #AESCMAC_setupVerify() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to CMAC operation structure() + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + */ +int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +/*! + * @brief Finalizes the current segmented operation + * + * For sign operations: + * This function computes and writes back the final MAC @a mac of length + * @a macLength. + * + * For verify operations: + * This function uses the provided MAC @a mac to authenticate an input message. + * The return value indicates whether the authentication was successful. + * + * @note Finalizing without additional input data is not supported. + * If finalization is attempted with @a inputLength of zero, + * #AESCMAC_STATUS_ERROR will be returned and the caller must either + * retry finalization with data or terminate the segmented operation + * by calling #AESCMAC_cancelOperation. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_addData() or #AESCMAC_setupSign() or #AESCMAC_setupVerify() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to CMAC operation structure() + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_MAC_INVALID The provided MAC did not match the generated MAC. + * This return value is only valid for verify operations. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + */ +int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +/*! + * @brief Performs a AESCMAC signature in one call + * + * This function uses the provided key to authenticate an input message. + * The resulting output is a message authentication code. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to AESCMAC operation structure + * + * @param [in] key Pointer to a previously initialized CryptoKey + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @sa #AESCMAC_oneStepVerify() + */ +int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key); + +/*! + * @brief Performs a AESCMAC verification in one call + * + * This function verifies that the provided message authentication code + * matches the one generated by the provided key and input message. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to AESCMAC operation structure + * + * @param [in] key Pointer to a previously initialized CryptoKey + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was verified successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_MAC_INVALID The provided MAC did not match the generated MAC. + * This return value is only valid for verify operations. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @sa AESCMAC_oneStepSign() + */ +int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key); + +/*! + * @brief Cancels an ongoing AESCMAC operation. + * + * Asynchronously cancels an AESCMAC operation. Only available when using + * AESCMAC_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCMAC_STATUS_CANCELED. + * + * @note Only the same thread that started an operation is permitted to cancel it. + * This function cannot be be called from an interrupt context or callback. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCMAC_STATUS_SUCCESS The operation was canceled or the operation had already completed. + */ +int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle); + +/** + * @brief Constructs a new AESCMAC object + * + * Unlike #AESCMAC_open(), #AESCMAC_construct() does not require the hwAttrs and + * object to be allocated in a #AESCMAC_Config array that is indexed into. + * Instead, the #AESCMAC_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @note #AESCMAC_Params @a operationalMode may be set to + * enable CBC-MAC mode but the default is CMAC mode + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + * + * @param [in] config #AESCMAC_Config describing the location of the object and hwAttrs. + * + * @param [in] params #AESCMAC_Params to configure the driver instance. + * + * @return Returns a #AESCMAC_Handle on success or NULL on failure. + */ +AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCMAC__include */ diff --git a/simplelink_lpf3/source/ti/drivers/AESCTR.c b/simplelink_lpf3/source/ti/drivers/AESCTR.c new file mode 100644 index 00000000..c5cd8dc9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCTR.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTR.c ======== + * + * This file contains default values for the AESCTR_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESCTR_Config AESCTR_config[]; +extern const uint_least8_t AESCTR_count; + +const AESCTR_Params AESCTR_defaultParams = { + .returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCTR_Params_init ======== + */ +void AESCTR_Params_init(AESCTR_Params *params) +{ + *params = AESCTR_defaultParams; +} + +/* + * ======== AESCTR_open ======== + */ +__attribute__((weak)) AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params) +{ + DebugP_assert(index < AESCTR_count); + + AESCTR_Config *config = (AESCTR_Config *)&AESCTR_config[index]; + return AESCTR_construct(config, params); +} + +/* + * ======== AESCTR_Operation_init ======== + */ +void AESCTR_Operation_init(AESCTR_Operation *operation) +{ + AESCTR_OneStepOperation_init(operation); +} + +/* + * ======== AESCTR_Operation_init ======== + */ +void AESCTR_OneStepOperation_init(AESCTR_OneStepOperation *operation) +{ + memset(operation, 0x00, sizeof(AESCTR_OneStepOperation)); +} + +/* + * ======== AESCTR_SegmentedOperation_init ======== + */ +void AESCTR_SegmentedOperation_init(AESCTR_SegmentedOperation *operation) +{ + memset(operation, 0x00, sizeof(AESCTR_SegmentedOperation)); +} diff --git a/simplelink_lpf3/source/ti/drivers/AESCTR.h b/simplelink_lpf3/source/ti/drivers/AESCTR.h new file mode 100644 index 00000000..c61c1097 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCTR.h @@ -0,0 +1,959 @@ +/* + * Copyright (c) 2018-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTR.h + * + * @brief AESCTR driver header + * + * @anchor ti_drivers_AESCTR_Overview + *

Overview

+ * The Counter (CTR) mode of operation is a generic block cipher mode of operation + * that can be used with any block cipher including AES which is used in this + * implementation. + * + * CTR mode encrypts and decrypts messages. It is not required for the message + * length to be evenly divisible by the cipher block size. This also means + * that padding the message is not required. + * + *

Operation

+ * CTR encryption and decryption perform the following steps: + * -# Set the counter value to the initial counter value + * -# Encrypt the counter value under the symmetric key + * -# XOR the encrypted counter value with the input block (plaintext or ciphertext) + * -# Increment the counter value. Interpret the byte array as a big-endian number. + * -# Repeat steps 2 to 4 until the input is completely processed. If the + * input is not evenly divisible by the block size, XOR the last + * (u = input length % block size) input bytes with the most significant + * u bytes of the last encrypted counter value. + * + * CTR performs the same steps regardless of whether it is used to + * encrypt or decrypt a message. The input merely changes. + * + *

Choosing Initial Counter Values

+ * CTR requires that each counter value used to encrypt a block of a message + * is unique for each key used. If this requirement is not kept, the + * confidentiality of that message block may be compromised. + * + * There are two general strategies when choosing the initial counter value + * of a CTR operation to ensure this requirement holds. + * + * The first is to choose an initial counter value for the first message + * and increment the initial counter value for a subsequent message by + * by message length % block length (16-bytes for AES). This effectively + * turns a sequence of messages into one long message. If 0 is chosen + * as the initial counter value, up to 2^128 - 1 blocks may be encrypted before + * key rotation is mandatory. + * + * The second is to split the initial counter value into a nonce and + * counter section. The nonce of length n bits must be unique per message. + * This allows for up to 2^n - 1 messages to be encrypted before + * key rotation is required. The counter section of length c is incremented + * as usual. This limits messages to a length of at most 2^c - 1 blocks. + * n and c must be chosen such that n + c = block length in bits + * (128 bits for AES) holds. + * + * @anchor ti_drivers_AESCTR_Usage + *

Usage

+ *

Before starting a CTR operation

+ * + * Before starting a CTR operation, the application must do the following: + * - Call #AESCTR_init() to initialize the driver + * - Call #AESCTR_Params_init() to initialize the #AESCTR_Params to default values. + * - Modify the #AESCTR_Params as desired + * - Call #AESCTR_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESCTR API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a single-step AESCTR operation using #AESCTR_OneStepOperation_init() + * which is equivalent to the deprecated #AESCTR_Operation_init(). If it's + * a segmented AESCTR operation, use #AESCTR_SegmentedOperation_init() instead. + * Then set all the fields of the one-step or segmented operation struct accordingly. + * + *

Starting a CTR operation

+ * + * The AESCTR_oneStepEncrypt() and AESCTR_oneStepDecrypt() functions perform a CTR operation + * in a single call. + * + *

After the CTR operation completes

+ * + * After the CTR operation completes, the application should either start + * another operation or close the driver by calling #AESCTR_close(). + * + * @anchor ti_drivers_AESCTR_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCTR_Synopsis_Code + * @code + * + * // Import AESCTR Driver definitions + * #include + * + * // Define name for AESCTR channel index + * #define AESCTR_INSTANCE 0 + * + * AESCTR_init(); + * + * handle = AESCTR_open(AESCTR_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCTR_Operation + * AESCTR_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * AESCTR_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTR_Examples + *

Examples

+ * + *
One step CTR encryption with plaintext CryptoKey in blocking return mode
+ * @code + * + * #include + * #include + * + * ... + * + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector from NIST SP 800-38A + * uint8_t initialCounter[16] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + * 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}; + * uint8_t plaintext[64] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, + * 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + * 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, + * 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + * + * handle = AESCTR_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation operation; + * AESCTR_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // The ciphertext should be the following after the encryption operation: + * // 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, + * // 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce, + * // 0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, + * // 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff, + * // 0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, + * // 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab, + * // 0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, + * // 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee + * + * AESCTR_close(handle); + * + * @endcode + * + *
One step CTR decryption with plaintext CryptoKey in callback return mode
+ * @code + * + * #include + * #include + * + * ... + * + * + * void ctrCallback(AESCTR_Handle handle, + * int_fast16_t returnValue, + * AESCTR_OperationUnion *operation, + * AESCTR_OperationType operationType) { + * + * if (returnValue != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * } + * AESCTR_Operation operation; + * + * void ctrStartFunction(void) { + * uint8_t initialCounter[16] = {0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + * 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01}; + * uint8_t ciphertext[] = {0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + * 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + * 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + * 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + * 0x25, 0xB2, 0x07, 0x2F}; + * uint8_t keyingMaterial[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + * 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * AESCTR_Handle handle; + * AESCTR_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCTR_OneStepOperation operation; + * + * AESCTR_Params_init(¶ms); + * params.returnBehavior = AESCTR_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ctrCallback; + * + * handle = AESCTR_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation_init(&operation); // Optional as all struct members will be set before use. + * + * operation.key = &cryptoKey; + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.initialCounter = initialCounter; + * + * decryptionResult = AESCTR_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // do other things while CTR operation completes in the background + * + * // After the operation completes and the callback is invoked, the resultant + * // plaintext should be: + * // 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * // 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + * // 0x20, 0x21, 0x22, 0x23 + * + * AESCTR_close(handle); + * } + * + * @endcode + * + *
Multi-step AES CTR encrypt with plaintext CryptoKey in polling return mode
+ * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * AESCTR_Params params; + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t retVal; + * + * // For example purposes only. + * uint8_t plaintext[36] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + * 0x20, 0x21, 0x22, 0x23}; + * uint8_t initialCounter[] = {0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + * 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01}; + * uint8_t keyingMaterial[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + * 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + * uint8_t ciphertext[sizeof(plaintext)]; + * + * AESCTR_Params_init(¶ms) + * params.returnBehavior = AESCTR_RETURN_BEHAVIOR_POLLING; + * + * handle = AESCTR_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_SegmentedOperation operation; + * AESCTR_SegmentedOperation_init(&operation); // Optional as all struct members will be set before use. + * + * retVal = AESCTR_setupEncrypt(handle, &cryptoKey, initialCounter); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext; + * operation.inputLength = AES_BLOCK_SIZE; // Only block multiple lengths are permitted when adding data. + * operation.output = ciphertext; + * + * retVal = AESCTR_addData(handle, &operation); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.inputLength = sizeof(plaintext) - AES_BLOCK_SIZE; // Non-block multiple length permitted during + * finalization. operation.output = ciphertext + AES_BLOCK_SIZE; + * + * retVal = AESCTR_finalize(handle, &operation); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * // Upon successful return, the resulting ciphertext should be: + * // 0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + * // 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + * // 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + * // 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + * // 0x25, 0xB2, 0x07, 0x2F + * + * AESCTR_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_AESCTR__include +#define ti_drivers_AESCTR__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCTR status code reservation offset. + * AESCTR driver implementations should offset status codes with + * #AESCTR_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRXYZ_STATUS_ERROR0 AESCTR_STATUS_RESERVED - 0 + * #define AESCTRXYZ_STATUS_ERROR1 AESCTR_STATUS_RESERVED - 1 + * #define AESCTRXYZ_STATUS_ERROR2 AESCTR_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTR_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCTR_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTR_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTR_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTR_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTR driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTR_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCTR_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported. + */ +#define AESCTR_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCTR_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCTR_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCTR driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief The way in which CTR function calls return after performing an + * encryption or decryption operation. + * + * Not all CTR operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTR functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCTR_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCTR_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCTR_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCTR_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * CTR operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCTR_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the CTR operation goes + * on in the background. CTR operation results are available + * after the function returns. + */ + AESCTR_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while CTR + * operation goes on in the background. CTR operation results + * are available after the function returns. + */ +} AESCTR_ReturnBehavior; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message using a one-step operation. + * + * The driver may access it at any point during the operation. It must remain + * in scope for the entire duration of the operation. + */ +typedef struct +{ + const CryptoKey *key; /*!< Pointer to a previously initialized CryptoKey. */ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * Size of the output buffer must be greater than + * or equal to the inputLength. + */ + const uint8_t *initialCounter; /*!< A buffer containing an initial counter. Under + * the same key, each counter value may only be + * used to encrypt or decrypt a single input + * block. If NULL, zero will be used for the + * initial counter value. The buffer's size must + * be at least 16-bytes. + */ + size_t inputLength; /*!< Length of the input in bytes. An equal number + * of bytes will be output by the operation. + * Max length supported may be limited depending on + * the return behavior. + */ +} AESCTR_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message using a segmented operation. This struct must be updated + * for each "add data" and "finalize" step. Modifying the structure and any buffers that + * it points to while an operation is in progress is prohibited. + * + * The driver may access it at any point during the operation. It must remain + * in scope for the entire duration of the operation. + */ +typedef struct +{ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * Size of the output buffer must be greater than + * or equal to the inputLength. + */ + size_t inputLength; /*!< Length of the input in bytes. An equal number + * of bytes will be output by the operation. Must + * be a non-zero multiple of block size (16-bytes) when + * calling #AESCTR_addData(). May be zero when calling + * #AESCTR_finalize() to finalize a segmented + * operation without additional data. + */ +} AESCTR_SegmentedOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESCTR_Operation. + * Existing code should be refactored to use AESCTR_OneStepOperation. + * This reference may be removed at some point in the future. + */ +typedef AESCTR_OneStepOperation AESCTR_Operation; + +/*! + * @brief Union containing a reference to a one-step and segmented operation + * structure. + */ +typedef union +{ + AESCTR_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESCTR_SegmentedOperation segmentedOperation; /* Segmented operation element of the operation union */ +} AESCTR_OperationUnion; + +/*! + * @brief Enum for the direction of the CTR operation. + */ +typedef enum +{ + AESCTR_MODE_ENCRYPT = 1, + AESCTR_MODE_DECRYPT = 2, +} AESCTR_Mode; + +/*! + * @brief Mask for the operation mode. + */ +#define AESCTR_OP_MODE_MASK 0x0F + +/*! + * @brief Flag indicating a segmented operation. + */ +#define AESCTR_OP_FLAG_SEGMENTED 0x10 /* bit 4 */ + +/*! + * @brief Flag indicating a finalize operation. + */ +#define AESCTR_OP_FLAG_FINALIZE 0x20 /* bit 5 */ + +/*! + * @brief Mask for all valid operation flags. + */ +#define AESCTR_OP_FLAGS_MASK (AESCTR_OP_FLAG_SEGMENTED | AESCTR_OP_FLAG_FINALIZE) + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCTR_OPERATION_TYPE_ENCRYPT = AESCTR_MODE_ENCRYPT, + AESCTR_OPERATION_TYPE_DECRYPT = AESCTR_MODE_DECRYPT, + AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED = (AESCTR_MODE_ENCRYPT | AESCTR_OP_FLAG_SEGMENTED), + AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED = (AESCTR_MODE_DECRYPT | AESCTR_OP_FLAG_SEGMENTED), + AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE = (AESCTR_MODE_ENCRYPT | AESCTR_OP_FLAG_FINALIZE), + AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE = (AESCTR_MODE_DECRYPT | AESCTR_OP_FLAG_FINALIZE), +} AESCTR_OperationType; + +/*! + * @brief AESCTR Global configuration + * + * The #AESCTR_Config structure contains a set of pointers used to characterize + * the AESCTR driver implementation. + * + * This structure needs to be defined before calling #AESCTR_init() and it must + * not be changed thereafter. + * + * @sa #AESCTR_init() + */ +typedef AESCommon_Config AESCTR_Config; + +/*! + * @brief A handle that is returned from an #AESCTR_open() call. + */ +typedef AESCTR_Config *AESCTR_Handle; + +/*! + * @brief The definition of a callback function used by the AESCTR driver + * when used in ::AESCTR_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CTR operation. + * + * @param returnValue The result of the CTR operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation Pointer to the operation union struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCTR_CallbackFxn)(AESCTR_Handle handle, + int_fast16_t returnValue, + AESCTR_OperationUnion *operation, + AESCTR_OperationType operationType); + +/*! + * @brief CTR Parameters + * + * CTR Parameters are for #AESCTR_open() and #AESCTR_construct() calls. + * Default values for these parameters are set using #AESCTR_Params_init(). + * + * @sa #AESCTR_Params_init() + */ +typedef struct +{ + AESCTR_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCTR_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCTR_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTR_Params; + +/*! + * @brief Default #AESCTR_Params structure + * + * @sa #AESCTR_Params_init() + */ +extern const AESCTR_Params AESCTR_defaultParams; + +/*! + * @brief This function initializes the CTR module. + * + * @pre The AESCTR_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CTR driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTR_init(void); + +/*! + * @brief Function to initialize the #AESCTR_Params struct to its defaults + * + * @param [in] params Pointer to #AESCTR_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCTR_Params_init(AESCTR_Params *params); + +/*! + * @brief This function opens a given AESCTR peripheral. + * + * @pre AESCTR driver has been initialized using #AESCTR_init() + * + * @param [in] index Logical peripheral number for the CTR indexed into + * the AESCTR_config table + * + * @param [in] params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #AESCTR_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTR_init() + * @sa #AESCTR_close() + */ +AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params); + +/*! + * @brief Function to close a CTR peripheral specified by the AESCTR handle + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * + * @sa #AESCTR_open() + */ +void AESCTR_close(AESCTR_Handle handle); + +/*! + * @brief Function to prepare a segmented AESCTR encryption operation. + * + * This function sets up a segmented AESCTR encryption operation. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] key Pointer to a previously initialized CryptoKey + * @param [in] initialCounter Pointer to initial counter value. + * The buffer size must be at least 16-bytes. + * If NULL, zero will be used for the initial counter value. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * + * @post #AESCTR_addData() + */ +int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter); + +/*! + * @brief Function to prepare a segmented AESCTR decryption operation. + * + * This function sets up a segmented AESCTR decryption operation. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] key Pointer to a previously initialized CryptoKey. + * @param [in] initialCounter Pointer to initial counter value. + * The buffer size must be at least 16-bytes. + * If NULL, zero will be used for the initial counter value. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * + * @post #AESCTR_addData() + */ +int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter); + +/*! + * @brief Encrypts or decrypts a segment of @a data with a @a length + * + * The @a inputLength must be a non-zero multiple of the block size (16-bytes). + * #AESCTR_addData() may be called an arbitrary number of times before + * finishing the operation with #AESCTR_finalize(). + * + * This function blocks until the final stream bytes have been computed. + * It returns immediately when ::AESCTR_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre A segmented operation has been setup using #AESCTR_setupEncrypt() or + * #AESCTR_setupDecrypt() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to #AESCTR_SegmentedOperation structure + * containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESCTR_addData() or #AESCTR_finalize() + */ +int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); + +/*! + * @brief Finalize the AES operation. If new data needs to be added, + * @c inputLength will be used to govern how many bytes will be written. + * + * @note To finalize an operation without any additional data, + * set @c inputLength to zero. The input and output buffers + * will not be used in this scenario. + * + * @pre #AESCTR_setupEncrypt() or #AESCTR_setupDecrypt() + * @pre #AESCTR_addData() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to #AESCTR_SegmentedOperation structure + * containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS In ::AESCTR_RETURN_BEHAVIOR_BLOCKING and + * ::AESCTR_RETURN_BEHAVIOR_POLLING, this means the CTR + * was generated successfully. In ::AESCTR_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); + +/*! + * @brief Function to initialize an #AESCTR_Operation struct to its defaults (all zeroes) + * + * @deprecated Use #AESCTR_OneStepOperation_init() or #AESCTR_SegmentedOperation_init() + * based on whether it is a one-step or a segmented AESCTR operation. + * + * @param operation Pointer to an #AESCTR_Operation structure for + * initialization + */ +void AESCTR_Operation_init(AESCTR_Operation *operation); + +/*! + * @brief Function to initialize an #AESCTR_OneStepOperation struct to its defaults (all zeroes) + * + * @param [in] operation Pointer to an #AESCTR_OneStepOperation structure for + * initialization + */ +void AESCTR_OneStepOperation_init(AESCTR_OneStepOperation *operation); + +/*! + * @brief Function to initialize an #AESCTR_SegmentedOperation struct to its defaults (all zeroes) + * + * @param [in] operation Pointer to an #AESCTR_SegmentedOperation structure for + * initialization + */ +void AESCTR_SegmentedOperation_init(AESCTR_SegmentedOperation *operation); + +/*! + * @brief Function to perform an AESCTR encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa #AESCTR_oneStepDecrypt() + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation); + +/*! + * @brief Function to perform an AESCTR decryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCTR_oneStepEncrypt() + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation); + +/*! + * @brief Cancels an ongoing AESCTR operation. + * + * Asynchronously cancels an AESCTR operation. Only available when using + * AESCTR_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCTR_STATUS_CANCELED. + * + * @param [in] handle AESCTR handle + * + * @retval #AESCTR_STATUS_SUCCESS The operation was canceled or the operation had already completed. + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle); + +/** + * @brief Constructs a new AESCTR object + * + * Unlike #AESCTR_open(), #AESCTR_construct() does not require the hwAttrs and + * object to be allocated in a #AESCTR_Config array that is indexed into. + * Instead, the #AESCTR_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may occur. + * + * @param [in] config #AESCTR_Config describing the location of the object and hwAttrs. + * + * @param [in] params #AESCTR_Params to configure the driver instance. + * + * @return Returns a #AESCTR_Handle on success or NULL on failure. + * + + */ +AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTR__include */ diff --git a/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.c b/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.c new file mode 100644 index 00000000..a7273e41 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2019-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTRDRBG.c ======== + * + * This file contains default values for the AESCTRDRBG_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCTRDRBG_Config AESCTRDRBG_config[]; +extern const uint_least8_t AESCTRDRBG_count; + +const AESCTRDRBG_Params AESCTRDRBG_defaultParams = { + .keyLength = AESCTRDRBG_AES_KEY_LENGTH_128, + .reseedInterval = 10000, + .seed = NULL, + .personalizationData = NULL, + .personalizationDataLength = 0, + .returnBehavior = AESCTRDRBG_RETURN_BEHAVIOR_POLLING, + .custom = NULL, +}; + +/* + * ======== AESCTRDRBG_open ======== + */ +__attribute__((weak)) AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params) +{ + DebugP_assert(index < AESCTRDRBG_count); + + AESCTRDRBG_Config *config = (AESCTRDRBG_Config *)&AESCTRDRBG_config[index]; + return AESCTRDRBG_construct(config, params); +} + +/* + * ======== AESCTRDRBG_Params_init ======== + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params) +{ + *params = AESCTRDRBG_defaultParams; +} diff --git a/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.h b/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.h new file mode 100644 index 00000000..e25a99ff --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCTRDRBG.h @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2019-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBG.h + * + * @brief AESCTRDRBG driver header + * + * @anchor ti_drivers_AESCTRDRBG_Overview + *

Overview

+ * AESCTRDRBG is a cryptographically secure deterministic random bit generator + * that is used to efficiently generate random numbers for use in keying material + * or other security related purposes. It is based on the AES block cipher + * operating in Counter (CTR) mode and is defined by NIST SP 800-90A. + * + * AESCTRDRBG derives a sequence of pseudo-random numbers based on an initial + * secret seed and additional, non-secret personalization data provided during + * instantiation. A sequence of random bits generated by AESCTRDRBG will have + * an equivalent entropy content of MIN(sequenceLength, security strength). + * The security strength is based on the seed length and the AES key length used + * in the AESCTRDRBG instance. + * + * | | AES-128 | AES-192 | AES-256 | + * |---------------------------------------|---------|---------|---------| + * | Security Strength (bits) | 128 | 192 | 256 | + * | Seed Length (bits) | 192 | 320 | 384 | + * | Personalization String Length (bits) | <= 192 | <= 320 | <= 384 | + * | Max Requests Between Reseeds | 2^48 | 2^48 | 2^48 | + * | Max Request Length (bits) | 2^19 | 2^19 | 2^19 | + * + *

Security Strength

+ * The seed must be sourced from a cryptographically secure source such as + * a True Random Number Generator and contain seed length bits of entropy. + * Since the seed length is always larger than the security strength for + * any one AES key length, the output of one AESCTRDRBG instance may not + * be used to seed another instance of the same or higher security strength. + * + *

Reseeding

+ * Because of the way AES CTR operates, there are a limited number of output + * bitstreams that may be generated before the AESCTRDRBG instance must be + * reseeded. The reseeding interval is set by the number of random bit + * sequences generated and not by their individual or combined lengths. Each time + * random bits are requested of the AESCTRDRBG instance by the application, + * the reseed counter is incremented by one regardless of how many bits at a + * time are requested. When this counter reaches the configured reseed limit, + * the AESCTRDRBG instance will return #AESCTRDRBG_STATUS_RESEED_REQUIRED + * until it is reseeded. + * + * The maximum permitted number of requests between reseeds is 2^48. + * The default counter is only 2^32 long for ease of implementation. + * A more conservative reseed limit may be configured by the application + * for increased security. + * + * A previously used seed may never be reused to reseed an AESCTRDRBG instance. + * The seed used to instantiate or reseed an instance must be generated by + * an approved entropy source. + * + *

Derivation Function

+ * NIST specifies the the use of an optional derivation function to reduced + * entropy and personalization string lengths longer than the seed + * length down to the seed length. This feature is not presently supported. + * + * @anchor ti_drivers_AESCTRDRBG_Usage + *

Usage

+ * + * This documentation provides a basic @ref ti_drivers_AESCTRDRBG_Synopsis + * "usage summary" and a set of @ref ti_drivers_AESCTRDRBG_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_AESCTRDRBG_Synopsis + *

Synopsis

+ * @anchor ti_drivers_AESCTRDRBG_Synopsis_Code + * @code + * #include + * + * AESCTRDRBG_init(); + * + * // Instantiate the AESCTRDRBG instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * + * result = AESCTRDRBG_generateKey(handle, &resultKey); + * + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * + * AESCTRDRBG_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTRDRBG_Examples + *

Examples

+ * + *

Instantiating an AESCTRDRBG Instance with TRNG

+ * @code + * + * #include + * #include + * #include + * + * ... + * + * AESCTRDRBG_Handle handle; + * AESCTRDRBG_Params params; + * TRNG_Handle trngHandle; + * int_fast16_t result; + * + * uint8_t seedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * // Open a TRNG driver instance + * trngHandle = TRNG_open(0, NULL); + * if (trngHandle == NULL) { + * // Failed to open TRNG instance + * while(1); + * } + * + * // Generate entropy for the seed + * result = TRNG_getRandomBytes(trngHandle, seedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * if (result != TRNG_STATUS_SUCCESS) { + * // Failed to generate entropy + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * // Instantiate the AESCTRDRBG parameters and the driver instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * if (handle == NULL) { + * // Failed to open AESCTRDRBG instance + * while(1); + * } + * @endcode + * + *

Generating random key with Reseeding

+ * + * @code + * + * #include + * #include + * #include + * + * ... + * + * #define RANDOM_KEY_LENGTH_BYTES 32 + * + * AESCTRDRBG_Handle handle; + * TRNG_Handle trngHandle; + * CryptoKey randomKey; + * int_fast16_t result; + * + * uint8_t randomKeyBuffer[RANDOM_KEY_LENGTH_BYTES]; + * + * // Initialise the AESCTRDRBG params and driver instance here + * ... + * + * // Initialize a blank CryptoKey + * CryptoKeyPlaintext_initBlankKey(&randomKey, randomKeyBuffer, RANDOM_KEY_LENGTH_BYTES); + * + * // Generate key-material for the CryptoKey + * result = AESCTRDRBG_generateKey(handle, &randomKey); + * + * // Check return value and reseed if needed. This should happen only after many invocations + * // of AESCTRDRBG_generateKey(). + * if (result == AESCTRDRBG_STATUS_RESEED_REQUIRED) { + * TRNG_Handle trngHandle; + * int_fast16_t reseedResult; + * uint8_t reseedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * reseedResult = TRNG_getRandomBytes(trngHandle, reseedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * if (reseedResult != TRNG_STATUS_SUCCESS) { + * // Failed to generate entropy + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * // Reseed the DRBG instance + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * if (reseedResult != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to reseed the DRBG instance + * while(1); + * } + * + * // If AESCTRDRBG_STATUS_RESEED_REQUIRED was returned from the previous call to + * // AESCTRDRBG_generateKey(), the random key was never generated by that call. + * // So the user must invoke that call again (after reseeding) to get a random key. + * result = AESCTRDRBG_generateKey(handle, &randomKey); + * if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate key-material + * while(1); + * } + * } + * else if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate key-material + * while(1); + * } + * + * @endcode + * + *

Generating random bytes output to an array

+ * + * @code + * + * #include + * #include + * + * ... + * + * #define RANDOM_BYTES_SIZE 16 + * + * AESCTRDRBG_Handle handle; + * TRNG_Handle trngHandle; + * int_fast16_t result; + * uint8_t randomBytesBuffer[RANDOM_BYTES_SIZE]; + * + * // Initialise the AESCTRDRBG params and driver instance here + * ... + * + * // Get random bytes output to the buffer/array + * result = AESCTRDRBG_getRandomBytes(handle, &randomBytesBuffer, RANDOM_BYTES_SIZE); + * + * // Check and reseed if required. This should happen only after many invocations + * // of AESCTRDRBG_getRandomBytes(). + * if (result == AESCTRDRBG_STATUS_RESEED_REQUIRED) { + * // Reseed the DRBG instance using AESCTRDRBG_reseed() + * // and invoke AESCTRDRBG_getRandomBytes() similar to the previous example. + * } + * else if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate random bytes + * while(1); + * } + * + * @endcode + * + */ + +#ifndef ti_drivers_AESCTRDRBG__include +#define ti_drivers_AESCTRDRBG__include + +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCTRDRBG status code reservation offset. + * AESCTRDRBG driver implementations should offset status codes with + * #AESCTRDRBG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRDRBGXYZ_STATUS_ERROR0 AESCTRDRBG_STATUS_RESERVED - 0 + * #define AESCTRDRBGXYZ_STATUS_ERROR1 AESCTRDRBG_STATUS_RESERVED - 1 + * #define AESCTRDRBGXYZ_STATUS_ERROR2 AESCTRDRBG_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTRDRBG_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCTRDRBG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTRDRBG_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTRDRBG_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTRDRBG_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTRDRBG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The AESCTRDRBG instance must be reseeded. + * + * An AESCTRDRBG instance may only service a limited number of bit + * generation requests before reseeding with more entropy is required. + */ +#define AESCTRDRBG_STATUS_RESEED_REQUIRED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 0) + +/*! + * @brief The AESCTRDRBG instance is uninstantiated. Close and reopen + * the instance. + */ +#define AESCTRDRBG_STATUS_UNINSTANTIATED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 1) + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCTR driver implementations used by AESCTRDRBG may have restrictions on the + * alignment of input/output data due to performance limitations of the + * hardware. + */ +#define AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 2) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return AESCTRDRBG_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define AESCTRDRBG_STATUS_KEYSTORE_ERROR (AES_STATUS_KEYSTORE_GENERIC_ERROR) + +/*! + * @brief The AES block size in bytes. + */ +#define AESCTRDRBG_AES_BLOCK_SIZE_BYTES 16 + +/*! + * @brief Length in bytes of the internal AES key used by an instance + */ +typedef enum +{ + AESCTRDRBG_AES_KEY_LENGTH_128 = 16, + AESCTRDRBG_AES_KEY_LENGTH_256 = 32, +} AESCTRDRBG_AES_KEY_LENGTH; + +/*! + * @brief Length in bytes of seed used to instantiate or reseed instance + */ +typedef enum +{ + AESCTRDRBG_SEED_LENGTH_AES_128 = AESCTRDRBG_AES_KEY_LENGTH_128 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, + AESCTRDRBG_SEED_LENGTH_AES_256 = AESCTRDRBG_AES_KEY_LENGTH_256 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, +} AESCTRDRBG_SEED_LENGTH; + +/*! + * @brief The way in which AESCTRDRBG function calls return after generating + * the requested entropy. + * + * Not all AESCTRDRBG operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTRDRBG functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |-------------------------------------|-------|-------|-------| + * |#AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING | X | | | + * |#AESCTRDRBG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + /*!< The function call will block while AESCTRDRBG operation goes + * on in the background. AESCTRDRBG operation results are available + * after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING = AESCTR_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will continuously poll a flag while AESCTRDRBG + * operation goes on in the background. AESCTRDRBG operation results + * are available after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_POLLING = AESCTR_RETURN_BEHAVIOR_POLLING, +} AESCTRDRBG_ReturnBehavior; + +/*! + * @brief AESCTRDRBG Global configuration + * + * The #AESCTRDRBG_Config structure contains a set of pointers used to characterize + * the AESCTRDRBG driver implementation. + * + * This structure needs to be defined before calling #AESCTRDRBG_init() and it must + * not be changed thereafter. + * + * @sa #AESCTRDRBG_init() + */ +typedef AESCommon_Config AESCTRDRBG_Config; + +/*! + * @brief A handle that is returned from an #AESCTRDRBG_open() call. + */ +typedef AESCTRDRBG_Config *AESCTRDRBG_Handle; + +/*! + * @brief AESCTRDRBG Parameters + * + * AESCTRDRBG Parameters are used to with the #AESCTRDRBG_open() call. Default values for + * these parameters are set using #AESCTRDRBG_Params_init(). + * + * @sa #AESCTRDRBG_Params_init() + */ +typedef struct +{ + AESCTRDRBG_AES_KEY_LENGTH keyLength; /*!< Length of the internal AES key + * of the driver instance. + */ + uint32_t reseedInterval; /*!< Number of random number generation + * requests before the application is + * required to reseed the driver. + */ + const void *seed; /*!< Entropy used to seed the internal + * state of the driver. Must be one of + * #AESCTRDRBG_SEED_LENGTH long depending + * on \c keyLength. + */ + const void *personalizationData; /*!< Optional non-secret personalization + * data to mix into the driver's internal + * state. + */ + size_t personalizationDataLength; /*!< Length of the optional + * \c personalizationData. Must satisfy + * 0 <= \c personalizationDataLength <= seed length. + */ + AESCTRDRBG_ReturnBehavior returnBehavior; /*!< Return behavior of the driver instance. + * #AESCTRDRBG_RETURN_BEHAVIOR_POLLING is + * strongly recommended unless requests + * for > 500 bytes with AES-256 or + * 1250 bytes for AES-128 will be common + * use cases for this driver instance. + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTRDRBG_Params; + +/*! + * @brief Default #AESCTRDRBG_Params structure + * + * @sa #AESCTRDRBG_Params_init() + */ +extern const AESCTRDRBG_Params AESCTRDRBG_defaultParams; + +/*! + * @brief This function initializes the AESCTRDRBG driver. + * + * @pre The #AESCTRDRBG_Config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other AESCTRDRBG driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTRDRBG_init(void); + +/*! + * @brief Function to initialize the #AESCTRDRBG_Params struct to its defaults + * + * @param [out] params Pointer to #AESCTRDRBG_Params structure for + * initialization + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params); + +/*! + * @brief This function opens a given AESCTRDRBG instance. + * + * @pre AESCTRDRBG controller has been initialized using #AESCTRDRBG_init() + * + * @param [in] index Logical peripheral number for the AESCTRDRBG indexed into + * the #AESCTRDRBG_Config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESCTRDRBG_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTRDRBG_init() + * @sa #AESCTRDRBG_close() + */ +AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params); + +/*! + * @brief Function to close an AESCTRDRBG instance specified by the #AESCTRDRBG_Handle + * + * @pre #AESCTRDRBG_open() has to be called first. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @sa #AESCTRDRBG_open() + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle); + +/*! + * @brief Generates the requested number of random bytes. + * + * @deprecated This function has been replaced by a pair of new functions. + * See #AESCTRDRBG_generateKey() and #AESCTRDRBG_getRandomBytes(). + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in,out] randomBytes Pointer to a \c CryptoKey object that should be already initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated random bytes will + * be populated. Some implementations may require key-material to be + * word-aligned. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Random bytes not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomBytes key material must be word-aligned. + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes); + +/*! + * @brief Populates the provided \c CryptoKey object's plaintext key-material with random bytes. + * + * @note This function replaces #AESCTRDRBG_getBytes(). + * See #AESCTRDRBG_getRandomBytes() to output random bytes to an array instead. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in,out] randomKey Pointer to a \c CryptoKey object that should be already initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated random bytes will + * be populated. Some implementations may require key-material to be + * word-aligned. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Key-material generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Key-material not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Key-material not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Key-material not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Key-material not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomKey key material must be word-aligned. + */ +int_fast16_t AESCTRDRBG_generateKey(AESCTRDRBG_Handle handle, CryptoKey *randomKey); + +/*! + * @brief Generates the requested number of random bytes and outputs to the given array. + * + * @attention This function should not be confused with the deprecated #AESCTRDRBG_getBytes(). + * #AESCTRDRBG_getBytes() output random bytes to a \c CryptoKey while this new + * function outputs random bytes to an array. + * + * @note See #AESCTRDRBG_generateKey() to output random bytes to a \c CryptoKey instead. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [out] randomBytes A pointer to an array that stores the random bytes + * output by this function. Some implementations may + * require this array to be word-aligned. + * + * @param [in] randomBytesSize The size in bytes of the random data required. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Random bytes not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomBytes array must be word-aligned. + */ +int_fast16_t AESCTRDRBG_getRandomBytes(AESCTRDRBG_Handle handle, void *randomBytes, size_t randomBytesSize); + +/*! + * @brief Reseed an AESCTRDRBG instance. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in] seed Entropy to mix into the AESCTRDRBG instance state + * + * @param [in] additionalData Optional non-secret additional data to mix into the + * instance state. + * + * @param [in] additionalDataLength Length of the optional additional data. + * 0 <= \c additionalDataLength <= seed length of the + * instance. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Reseed successful. Reseed counter reset. + * @retval #AESCTRDRBG_STATUS_ERROR Reseed not successful. Reseed counter not reset. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The requires hardware was unavailable. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh + * seed. + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength); + +/** + * @brief Constructs a new AESCTRDRBG object + * + * Unlike #AESCTRDRBG_open(), #AESCTRDRBG_construct() does not require the hwAttrs and + * object to be allocated in a #AESCTRDRBG_Config array that is indexed into. + * Instead, the #AESCTRDRBG_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESCTRDRBG_Config describing the location of the object and hwAttrs. + * + * @param params #AESCTRDRBG_Params to configure the driver instance. + * + * @return Returns an #AESCTRDRBG_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESCTRDRBG_Handle AESCTRDRBG_construct(AESCTRDRBG_Config *config, const AESCTRDRBG_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTRDRBG__include */ diff --git a/simplelink_lpf3/source/ti/drivers/AESCommon.h b/simplelink_lpf3/source/ti/drivers/AESCommon.h new file mode 100644 index 00000000..0bb4fb87 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESCommon.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!*************************************************************************** + * @file AESCommon.h + * + * @brief AES common module header for all devices + *****************************************************************************/ + +#ifndef ti_drivers_AESCommon_include +#define ti_drivers_AESCommon_include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Successful status code. + * + * Functions return #AES_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AES_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return #AES_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AES_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AES driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ +#define AES_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AES_STATUS_CANCELED ((int_fast16_t)-3) + +/*! + * @brief The MAC verification failed. + * + * Functions return #AES_STATUS_MAC_INVALID if the MAC computed + * for the provided (key, message) pair did not match the MAC provided. + */ +#define AES_STATUS_MAC_INVALID ((int_fast16_t)-4) + +/*! + * @brief The operation tried to load a key from the keystore using + * an invalid key ID. + * + * This code is returned if the provided CryptoKey reference + * is returned as invalid by the key store module. + */ +#define AES_STATUS_KEYSTORE_INVALID_ID ((int_fast16_t)-5) + +/*! + * @brief The key store module returned a generic error. See key store + * documentation for additional details. + */ +#define AES_STATUS_KEYSTORE_GENERIC_ERROR ((int_fast16_t)-6) + +/*! + * @brief The operation requested is not supported. + */ +#define AES_STATUS_FEATURE_NOT_SUPPORTED ((int_fast16_t)-7) + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + */ +#define AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED ((int_fast16_t)-8) + +/*! + * @brief A driver shall use this error code and grow negatively until + * (AES_STATUS_RESERVED + 1) if more driver specific error codes + * are needed beyond the common codes listed above. + * + * @note Not to be confused with #AES_STATUS_RESERVED which is for defining + * device specific codes if needed for a given driver, while + * #AES_STATUS_DRIVER_SPECIFIC_ERROR is for a driver but common across + * all devices for which that driver is implemented. + * + * Example implementation specific status codes: + * @code + * #define AESXYZ_STATUS_ERROR0 AES_STATUS_DRIVER_SPECIFIC_ERROR - 0 + * #define AESXYZ_STATUS_ERROR1 AES_STATUS_DRIVER_SPECIFIC_ERROR - 1 + * #define AESXYZ_STATUS_ERROR2 AES_STATUS_DRIVER_SPECIFIC_ERROR - 2 + * @endcode + */ +#define AES_STATUS_DRIVER_SPECIFIC_ERROR ((int_fast16_t)-16) + +/*! + * Common AES status code reservation offset. + * AES driver implementations should offset status codes with + * #AES_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESXYZCCXXXX_STATUS_ERROR0 AES_STATUS_RESERVED - 0 + * #define AESXYZCCXXXX_STATUS_ERROR1 AES_STATUS_RESERVED - 1 + * #define AESXYZCCXXXX_STATUS_ERROR2 AES_STATUS_RESERVED - 2 + * @endcode + */ +#define AES_STATUS_RESERVED ((int_fast16_t)-32) + +/*! + * @brief AES Global configuration + * + * The #AESCommon_Config structure contains a set of pointers used to + * characterize the AES driver implementation. + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCommon_Config; + +/*! + * @brief The return behavior of AES functions + * + * Not all AES operations exhibit the specified return behavior. Functions + * that do not require significant computation and cannot offload that + * computation to a background thread behave like regular functions. + * Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation + * run on the same CPU as the application will emulate the return behavior + * while not actually offloading the computation to the background thread. + * + * AES functions exhibiting the specified return behavior have restrictions + * on the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |-----------------------------|-------|-------|-------| + * |AES_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AES_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AES_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AES_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AES_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the operation goes + * on in the background. Operation results are available + * after the function returns. + */ + AES_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while + * operation goes on in the background. Operation results + * are available after the function returns. + */ +} AES_ReturnBehavior; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCommon__include */ diff --git a/simplelink_lpf3/source/ti/drivers/AESECB.c b/simplelink_lpf3/source/ti/drivers/AESECB.c new file mode 100644 index 00000000..b02ee5b9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESECB.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESECB.c ======== + * + * This file contains default values for the AESECB_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESECB_Config AESECB_config[]; +extern const uint_least8_t AESECB_count; + +const AESECB_Params AESECB_defaultParams = { + .returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESECB_Params_init ======== + */ +void AESECB_Params_init(AESECB_Params *params) +{ + *params = AESECB_defaultParams; +} + +/* + * ======== AESECB_Operation_init ======== + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESECB_Operation)); +} + +/* + * ======== AESECB_open ======== + */ +__attribute__((weak)) AESECB_Handle AESECB_open(uint_least8_t index, const AESECB_Params *params) +{ + DebugP_assert(index < AESECB_count); + + AESECB_Config *config = (AESECB_Config *)&AESECB_config[index]; + return AESECB_construct(config, params); +} diff --git a/simplelink_lpf3/source/ti/drivers/AESECB.h b/simplelink_lpf3/source/ti/drivers/AESECB.h new file mode 100644 index 00000000..33584e44 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/AESECB.h @@ -0,0 +1,919 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESECB.h + * + * @brief AESECB driver header + * + * @anchor ti_drivers_AESECB_Overview + * # Overview # + * The Electronic Code Book (ECB) mode of operation is a generic + * encryption block cipher mode. It can be used with any block cipher. + * AESECB encrypts or decrypts one or multiple blocks of plaintext or ciphertext + * using the Advanced Encryption Standard (AES) block cipher. + * Each input block is individually encrypted or decrypted. This means that + * blocks of ciphertext can be decrypted individually and out of order. + * Encrypting the same plaintext using the same key yields identical ciphertext. + * This raises several security issues. For this reason, ECB is not recommended + * unless interfacing with legacy systems which cannot be updated + * or where a standard specifies its use. Better alternatives would be an + * authenticated encryption with associated data (AEAD) mode such as + * CCM or GCM. + * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * @anchor ti_drivers_AESECB_Usage + * # Usage # + * + * ## Before starting an ECB operation # + * + * Before starting an ECB operation, the application must do the following: + * - Call AESECB_init() to initialize the driver + * - Call AESECB_Params_init() to initialize the AESECB_Params to default values. + * - Modify the AESECB_Params as desired + * - Call AESECB_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESECB API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the AESECB_Operation using AESECB_Operation_init() and set all + * length, key, and buffer fields. + * + * ## Starting an ECB operation # + * + * The AESECB_oneStepEncrypt and AESECB_oneStepDecrypt functions do an ECB operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. Since ECB plaintext blocks are simply encrypted with the block cipher block by block, + * there is no difference in the ciphertext between encrypting two blocks in one go or encrypting + * each block individually. + * + * ## After the ECB operation completes # + * + * After the ECB operation completes, the application should either start another operation + * or close the driver by calling AESECB_close() + * + * @anchor ti_drivers_AESECB_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESECB_Synopsis_Code + * @code + * // Import AESECB Driver definitions + * #include + * + * AESECB_init(); + * + * // Define name for AESECB channel index + * #define AESECB_INSTANCE 0 + * + * handle = AESECB_open(AESECB_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESECB_Operation + * AESECB_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * AESECB_close(handle); + * @endcode + * + * @anchor ti_drivers_AESECB_Examples + * + * ## Examples + * + * ### Encryption of multiple plaintext blocks in blocking mode # + * @code + * + * #include + * #include + * + * ... + * + * AESECB_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t plaintext[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c} + * + * handle = AESECB_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation operation; + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resultant ciphertext should be: + * // 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, + * // 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97, + * // 0xf5, 0xd3, 0xd5, 0x85, 0x03, 0xb9, 0x69, 0x9d, + * // 0xe7, 0x85, 0x89, 0x5a, 0x96, 0xfd, 0xba, 0xaf + * + * + * AESECB_close(handle); + * + * @endcode + * + * ### One step ECB decryption in callback mode # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t ciphertext[] = {0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, + * 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8}; + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * // 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * + * + * void ecbCallback(AESECB_Handle handle, + * int_fast16_t returnValue, + * AESECB_Operation *operation, + * AESECB_OperationType operationType) { + * + * if (returnValue != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESECB_Operation operation; + * + * void ecbStartFunction(void) { + * AESECB_Handle handle; + * AESECB_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESECB_Params_init(¶ms); + * params.returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ecbCallback; + * + * handle = AESECB_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * decryptionResult = AESECB_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while ECB operation completes in the background + * + * } + * + * @endcode + * + * ### Multi-step ECB encryption in blocking mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * ... + * + * AESECB_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * int_fast16_t setupEncryptionResult; + * int_fast16_t finalizeEncryptionResult; + * uint8_t plaintext[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c} + * + * handle = AESECB_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * setupEncryptionResult = AESECB_setupEncrypt(handle, &cryptoKey); + * if (setupEncryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * AESECB_Operation operation; + * AESECB_Operation_init(&operation); + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) for calling + * // #AESECB_addData(). The user or application should take care of necessary padding + * // if the final block of data is being added for the entire segmented operation. + * operation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESECB_addData(handle, &operation); + * if (encryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.output = ciphertext + AES_BLOCK_SIZE; + * // Input length must either be a non-zero multiple of block-size (16 bytes) + * // for calling #AESECB_finalize(), or it could be zero in case of finalizing without + * // any more data. The user or application should take care of necessary padding + * // for the last block of data. + * operation.inputLength = AES_BLOCK_SIZE; + * + * finalizeEncryptionResult = AESECB_finalize(handle, &operation); + * if (finalizeEncryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resultant ciphertext should be: + * // 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, + * // 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97, + * // 0xf5, 0xd3, 0xd5, 0x85, 0x03, 0xb9, 0x69, 0x9d, + * // 0xe7, 0x85, 0x89, 0x5a, 0x96, 0xfd, 0xba, 0xaf + * + * + * AESECB_close(handle); + * + * } + * + * @endcode + * + * ### Multi-step ECB decryption in callback mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * ... + * uint8_t ciphertext[] = {0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, + * 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8}; + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * // 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * + * + * void ecbCallback(AESECB_Handle handle, + * int_fast16_t returnValue, + * AESECB_Operation *operation, + * AESECB_OperationType operationType) { + * + * if (returnValue != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESECB_Operation operation; + * + * void ecbStartFunction(void) { + * AESECB_Handle handle; + * AESECB_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * int_fast16_t setupDecryptionResult; + * int_fast16_t finalizeDecryptionResult; + * + * AESECB_Params_init(¶ms); + * params.returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ecbCallback; + * + * handle = AESECB_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * setupDecryptionResult = AESECB_setupDecrypt(handle, &cryptoKey); + * if (setupDecryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * AESECB_Operation_init(&operation); + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) for calling + * // #AESECB_addData(). The user or application should take care of necessary padding + * // if the final block of data is being added for the entire segmented operation. + * operation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESECB_addData(handle, &operation); + * if (decryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while ECB operation completes in the background + * + * // Input length must either be a non-zero multiple of block-size (16 bytes) + * // for calling #AESECB_finalize(), or it could be zero in case of finalizing without + * // any more data as shown in this example. There's no more data involved and padding + * // is not applicable for this finalization operation. + * operation.inputLength = 0; + * + * finalizeDecryptionResult = AESECB_finalize(handle, &operation); + * if (finalizeDecryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESECB__include +#define ti_drivers_AESECB__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESECB status code reservation offset. + * AESECB driver implementations should offset status codes with + * AESECB_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESECBXYZ_STATUS_ERROR0 AESECB_STATUS_RESERVED - 0 + * #define AESECBXYZ_STATUS_ERROR1 AESECB_STATUS_RESERVED - 1 + * #define AESECBXYZ_STATUS_ERROR2 AESECB_STATUS_RESERVED - 2 + * @endcode + */ +#define AESECB_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return AESECB_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESECB_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return AESECB_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESECB_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESECB driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESECB_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESECB_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported on the target hardware + * or by the current state of the SW implementation. + */ +#define AESECB_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESECB_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESECB_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESECB driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESECB Global configuration + * + * The AESECB_Config structure contains a set of pointers used to characterize + * the AESECB driver implementation. + * + * This structure needs to be defined before calling AESECB_init() and it must + * not be changed thereafter. + * + * @sa AESECB_init() + */ +typedef AESCommon_Config AESECB_Config; + +/*! + * @brief A handle that is returned from an AESECB_open() call. + */ +typedef AESECB_Config *AESECB_Handle; + +/*! + * @brief The way in which ECB function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECB operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESECB functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESECB_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESECB_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESECB_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESECB_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * ECB operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESECB_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while ECB operation goes + * on in the background. ECB operation results are available + * after the function returns. + */ + AESECB_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while ECB + * operation goes on in the background. ECB operation results + * are available after the function returns. + */ +} AESECB_ReturnBehavior; + +/*! + * @brief Enum for the direction of the ECB operation. + */ +typedef enum +{ + AESECB_MODE_ENCRYPT = 1, + AESECB_MODE_DECRYPT = 2, +} AESECB_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and a message. + */ +typedef struct +{ + CryptoKey *key; /*!< A previously initialized CryptoKey. + * @note: Required for one-step operations only. + * For segmented operations, this pointer is not used + * and may be left uninitialized or set to NULL. + */ + uint8_t *input; /*!< + * - Encryption: A pointer to the plaintext buffer. + * - Decryption: A pointer to the ciphertext buffer. + * + * Both input and output buffers should be of the size + * \c inputLength in bytes each. + */ + uint8_t *output; /*!< + * - Encryption: A pointer to the buffer to store the + * resulting ciphertext. + * - Decryption: A pointer to the buffer to store the + * resulting plaintext. + * + * Both input and output buffers should be of the size + * \c inputLength in bytes each. + */ + size_t inputLength; /*!< + * - One-step operation: Total length of the input in + * bytes. + * - Multi-step / Segmented operation: Length of the + * input in bytes for that #AESECB_addData() + * or #AESECB_finalize() call. + * + * The output will be the same length as the input. + * Max length supported may be limited depending on the + * return behavior. + * + * Must be a non-zero multiple of AES block size (16 bytes). + * May be 0 only when calling #AESECB_finalize() to + * finalize a multi-step operation without additional + * data. + * The user or application should take care of any + * necessary padding. + */ +} AESECB_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESECB_OPERATION_TYPE_ENCRYPT = 1, + AESECB_OPERATION_TYPE_DECRYPT = 2, + AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED = 3, + AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED = 4, + AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED = 5, + AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED = 6 +} AESECB_OperationType; + +/*! + * @brief The definition of a callback function used by the AESECB driver + * when used in ::AESECB_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECB operation. + * + * @param returnValue The result of the ECB operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESECB_CallbackFxn)(AESECB_Handle handle, + int_fast16_t returnValue, + AESECB_Operation *operation, + AESECB_OperationType operationType); + +/*! + * @brief ECB Parameters + * + * ECB Parameters are used with the #AESECB_open() call. Default values for + * these parameters are set using #AESECB_Params_init(). + * + * @sa #AESECB_Params_init() + */ +typedef struct +{ + AESECB_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESECB_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESECB_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESECB_Params; + +/*! + * @brief Default #AESECB_Params structure + * + * @sa #AESECB_Params_init() + */ +extern const AESECB_Params AESECB_defaultParams; + +/*! + * @brief This function initializes the ECB module. + * + * @pre The AESECB_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECB driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESECB_init(void); + +/*! + * @brief Function to initialize the #AESECB_Params struct to its defaults + * + * @param params An pointer to #AESECB_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESECB_Params_init(AESECB_Params *params); + +/*! + * @brief This function opens a given ECB peripheral. + * + * @pre ECB controller has been initialized using #AESECB_init() + * + * @param [in] index Logical peripheral number for the ECB indexed into + * the AESECB_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESECB_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #AESECB_init() + * @sa #AESECB_close() + */ +AESECB_Handle AESECB_open(uint_least8_t index, const AESECB_Params *params); + +/*! + * @brief Function to close an ECB peripheral specified by the ECB handle + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @sa AESECB_open() + */ +void AESECB_close(AESECB_Handle handle); + +/*! + * @brief Function to initialize an #AESECB_Operation struct to its defaults + * + * @param [in] operationStruct An pointer to #AESECB_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct); + +/*! + * @brief Function to perform an AESECB encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre #AESECB_open() or #AESECB_construct(), and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESECB_oneStepDecrypt() + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Function to perform an AESECB decryption in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre #AESECB_open() or #AESECB_construct(), and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESECB_oneStepEncrypt() + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Function to prepare a segmented AESECB encryption operation. + * + * This functions sets up a segmented AESECB encryption operation. + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() + * or #AESECB_construct() + * + * @param [in] key A previously initialized CryptoKey. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * + * @post #AESECB_addData() + */ +int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key); + +/*! + * @brief Function to prepare a segmented AESECB decryption operation. + * + * This functions sets up a segmented AESECB decryption operation. + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() + * or #AESECB_construct() + * + * @param [in] key A previously initialized CryptoKey. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * + * @post #AESECB_addData() + */ +int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key); + +/*! + * @brief Encrypts or decrypts segment of @a data with a @a length + * + * #AESECB_addData() may be called an arbitrary number times before finishing the operation with + * #AESECB_finalize(). Note that this function is called for use with segmented operations. For + * segmented operations, @c inputLength will govern the input/output lengths and + * must be a AES block size multiple (16-bytes). + * + * @pre #AESECB_setupEncrypt() or #AESECB_setupDecrypt() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation Pointer to ECB operation structure() + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESECB_addData() or #AESECB_finalize() + */ +int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Finalize the AES transaction. If new data needs to be added, + * @c inputLength will be used to govern how many bytes will be written. + * + * @pre #AESECB_addData() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation Pointer to ECB operation structure() + * + * @retval #AESECB_STATUS_SUCCESS In ::AESECB_RETURN_BEHAVIOR_BLOCKING and + * ::AESECB_RETURN_BEHAVIOR_POLLING, this means the ECB output + * was generated successfully. In ::AESECB_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Cancels an ongoing AESECB operation. + * + * Asynchronously cancels an AESECB operation. Only available when using + * AESECB_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESECB_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESECB_STATUS_SUCCESS The operation was canceled, or the requested operation had already + * completed. + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle); + +/** + * @brief Constructs a new AESECB object + * + * Unlike #AESECB_open(), #AESECB_construct() does not require the hwAttrs and + * object to be allocated in a #AESECB_Config array that is indexed into. + * Instead, the #AESECB_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESECB_Config describing the location of the object and hwAttrs. + * + * @param params #AESECB_Params to configure the driver instance. + * + * @return Returns a #AESECB_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESECB__include */ diff --git a/simplelink_lpf3/source/ti/drivers/ECDH.c b/simplelink_lpf3/source/ti/drivers/ECDH.c new file mode 100644 index 00000000..8350efcd --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/ECDH.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECDH.c ======== + * + * This file contains default values for the ECDH_Params struct + * + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const ECDH_Config ECDH_config[]; +extern const uint_least8_t ECDH_count; + +const ECDH_Params ECDH_defaultParams = { + .returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECDH_open ======== + */ +__attribute__((weak)) ECDH_Handle ECDH_open(uint_least8_t index, const ECDH_Params *params) +{ + DebugP_assert(index < ECDH_count); + + ECDH_Config *config = (ECDH_Config *)&ECDH_config[index]; + return ECDH_construct(config, params); +} + +/* + * ======== ECDH_OperationGeneratePublicKey_init ======== + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation) +{ + operation->curve = NULL; + operation->myPrivateKey = NULL; + operation->myPublicKey = NULL; + /* Default key material endianness is big endian*/ + operation->keyMaterialEndianness = ECDH_BIG_ENDIAN_KEY; +} +/* + * ======== ECDH_OperationComputeSharedSecret_init ======== + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation) +{ + operation->curve = NULL; + operation->myPrivateKey = NULL; + operation->theirPublicKey = NULL; + operation->sharedSecret = NULL; + /* Default key material endianness is big endian*/ + operation->keyMaterialEndianness = ECDH_BIG_ENDIAN_KEY; +} diff --git a/simplelink_lpf3/source/ti/drivers/ECDH.h b/simplelink_lpf3/source/ti/drivers/ECDH.h new file mode 100644 index 00000000..e6fa1a47 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/ECDH.h @@ -0,0 +1,865 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECDH.h + * + * @brief TI Driver for Elliptic Curve Diffie-Hellman key agreement scheme. + * + * @anchor ti_drivers_ECDH_Overview + * # Overview # + * + * Elliptic Curve Diffie-Hellman (ECDH) is a key agreement scheme between + * two parties based on the Diffie-Hellman key exchange protocol. + * + * It provides a means of generating a shared secret and derived symmetric key + * between the two parties over an insecure channel. + * + * It does not provide authentication. As such, it does not guarantee that the + * party you are exchanging keys with is truly the party you wish to establish a + * secured channel with. + * + * The two parties each generate a private key and a public key. The private key + * is a random integer in the interval [1, n - 1], where n is the order of a + * previously agreed upon curve. The public key is generated + * by multiplying the private key by the generator point of a previously agreed + * upon elliptic curve such as NISTP256 or Curve 25519. The public key is itself + * a point upon the elliptic curve. Each public key is then transmitted to the + * other party over a potentially insecure channel. The other party's public key + * is then multiplied with the private key, generating a shared secret. This + * shared secret is also a point on the curve. However, the entropy in the secret + * is not spread evenly throughout the shared secret. In order to generate one or more + * shared symmetric keys, the shared secret must be run through a key derivation + * function (KDF) that was previously agreed upon. Usually, only the X coordinate + * is processed in this way as it contains all the entropy of the shared secret and + * some curve implementations only provide the X coordinate. The key derivation function + * can take many forms, from simply hashing the X coordinate of the shared secret + * with SHA2 and truncating the result to generating multiple symmetric keys with + * HKDF, an HMAC based KDF. + * + * Key derivation functions in the context of symmetric key generation after + * elliptic curve based key exchange differ from KDFs used to generate keys from + * passwords a user provides in a login. Those KDFs such as bcrypt purposefully + * add additional computation to increase a system's resistance against brute + * force or dictionary attacks. + * + * @anchor ti_drivers_ECDH_Usage + * # Usage # + * + * ## Before starting an ECDH operation # + * + * Before starting an ECDH operation, the application must do the following: + * - Call ECDH_init() to initialize the driver + * - Call ECDH_Params_init() to initialize the ECDH_Params to default values. + * - Modify the ECDH_Params as desired + * - Call ECDH_open() to open an instance of the driver + * + * ## Generating your public-private key pair # + * To generate a public-private key pair for an agreed upon curve, the application + * must do the following: + * - Generate the keying material for the private key. This keying material must + * be an integer in the interval [1, n - 1], where n is the order of the curve. + * It can be stored in big-endian or little-endian format. + * The array should be the same length as the curve parameters of the curve used. + * The driver validates private keys against the provided curve by default. + * - Initialize the private key CryptoKey. CryptoKeys are opaque data structures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The ECDH API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a blank CryptoKey for the public key. The CryptoKey will keep track + * of where the keying material for the public key should be copied and how + * long it is. SEC 1-based big-endian format public keys should have key material twice the length + * of the private key plus one. Little-endian format public keys should have key material the + * length of the private key for Montgomery curve X-only public keys or have key material twice + * the length of the private for other curves + * - Initialize the ECDH_OperationGeneratePublicKey struct and then populate it. By + * default, big-endian public keys will be generated. + * - If using RFC 7748-style public keys, initialize the operation's public key + * data format to be ECDH_LITTLE_ENDIAN_KEY. + * - Call ECDH_generatePublicKey(). The generated keying material will be copied + * according the the CryptoKey passed in as the public key parameter. The CryptoKey + * will no longer be considered 'blank' after the operation. + * + * ## Calculating a shared secret # + * After trading public keys with the other party, the application should do the following + * to calculate the shared secret: + * - Initialize a CryptoKey as public key with the keying material received from the other + * party. + * - Initialize the private key CryptoKey with the key used to generate your + * public key. CryptoKeys are opaque data structures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The ECDH API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a blank CryptoKey with the same size as the previously initialized + * public key. + * - Initialize the ECDH_OperationComputeSharedSecret struct and then populate it. By + * default, big-endian input keys will be assumed and big-endian shared secrets + * will be generated. + * - If importing RFC 7748-style public keys, initialize the operation's key material + * endianess to be ECDH_LITTLE_ENDIAN_KEY. + * - Call ECDH_computeSharedSecret(). The shared secret will be copied to a location + * according to the shared secret CryptoKey passed to the function call. The driver + * will validate the supplied public key and reject invalid ones. + * + * ## Creating one or more symmetric keys from the shared secret # + * After calculating the shared secret between the application and the other party, + * the entropy in the shared secret must be evened out and stretched as needed. There are + * uncountable methods and algorithms to stretch an original seed entropy (the share secret) + * to generate symmetric keys. + * - Run the X coordinate of the resulting entropy through a key derivation function (KDF) + * + * ## After a key exchange # + * After the ECDH key exchange completes, the application should either start another operation + * or close the driver by calling ECDH_close() + * + * ## General usage # + * The API expects elliptic curves as defined in ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECDH documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your device. + * ECDH support for a curve type on a device does not imply curve-type support for + * other ECC schemes. + * + * ## Key Formatting + * By default, the ECDH API expects the private and public keys to be formatted in + * big-endian format. The details of octet string formatting can be found in + * SEC 1: Elliptic Curve Cryptography. + * + * Private keys can be formatted as big-endian or little-endian integers of the same + * length as the curve length. + * + * Public keys and shared secrets are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as an + * X,Y pair. + * This API uses points expressed in uncompressed affine coordinates by default. + * The big-endian format requires a formatting byte in the first byte of the + * public key. When using uncompressed affine coordinates, this is the value + * 0x04. + * The point itself is stored as a concatenated array of X followed by Y. + * X and Y maybe in big-endian or little-endian. Some implementations do not require or + * yield the Y coordinate for ECDH on certain curves. It is recommended that the full + * keying material buffer of twice the curve param length is used to facilitate + * code-reuse. Implementations that do not use the Y coordinate will zero-out + * the Y-coordinate whenever they write a point to the CryptoKey. + * + * If device-supported, Montgomery curves can be stored as their X-only format + * based on the RFC-7748 specification. Here, only the X coordinate is packed + * in little-endian integers of the same length as the curve length. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|----------------------------| + * | Short Weierstrass | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [X] | Curve Param Length | + * | Edwards | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * + * Note: This driver will automatically prune the private key according to + * RFC 7748 for the following curve: + * X25519 + * + * @anchor ti_drivers_ECDH_Synopsis + * ## Synopsis + * @anchor ti_drivers_ECDH_Synopsis_Code + * @code + * // Import ECDH Driver definitions + * #include + * + * ECDH_init(); + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialize their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * // Close the driver + * ECDH_close(ecdhHandle); + * + * @endcode + * + * ## Synopsis for X25519 X-only key exchange + * @anchor ti_drivers_ECDH_X25519_Code + * @code + * // Import ECDH Driver definitions + * #include + * + * ECDH_init(); + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * // Note that the public key size is only 32 bytes + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_Curve25519; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * // If generating public key in little-endian format, we use the following format: + * operationGeneratePublicKey.keyMaterialEndianness = ECDH_LITTLE_ENDIAN_KEY; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialize their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_Curve25519; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * // If receiving and generating keys in little-endian format, we use the following format: + * operationComputeSharedSecret.keyMaterialEndianness = ECDH_LITTLE_ENDIAN_KEY; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * // Close the driver + * ECDH_close(ecdhHandle); + * + * @endcode + * + * @anchor ti_drivers_ECDH_Examples + * # Examples # + * + * ## ECDH exchange with plaintext CryptoKeys # + * + * @code + * + * #include + * #include + * + * #define CURVE_LENGTH 32 + * + * ... + * + * // Our private key is 0x0000000000000000000000000000000000000000000000000000000000000001 + * // In practice, this value should come from a TRNG, PRNG, PUF, or device-specific pre-seeded key + * uint8_t myPrivateKeyingMaterial[CURVE_LENGTH] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; + * uint8_t myPublicKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t theirPublicKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t sharedSecretKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t symmetricKeyingMaterial[16] = {0}; + * + * CryptoKey myPrivateKey; + * CryptoKey myPublicKey; + * CryptoKey theirPublicKey; + * CryptoKey sharedSecret; + * CryptoKey symmetricKey; + * + * ECDH_Handle ecdhHandle; + * + * int_fast16_t operationResult; + * + * ECDH_OperationGeneratePublicKey operationGeneratePublicKey; + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * if (!ecdhHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material and the + * // 0x04 byte to theirPublicKeyingMaterial + * + * // Initialise their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * CryptoKeyPlaintext_initBlankKey(&symmetricKey, symmetricKeyingMaterial, sizeof(symmetricKeyingMaterial)); + * + * // Set up a KDF such as HKDF and open the requisite cryptographic primitive driver to implement it + * // HKDF and SHA2 were chosen as an example and may not be available directly + * + * // At this point, you and the other party have both created the content within symmetricKeyingMaterial without + * // someone else listening to your communication channel being able to do so + * + * @endcode + * + * + */ + +#ifndef ti_drivers_ECDH__include +#define ti_drivers_ECDH__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common ECDH status code reservation offset. + * ECC driver implementations should offset status codes with + * ECDH_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECCXYZ_STATUS_ERROR0 ECDH_STATUS_RESERVED - 0 + * #define ECCXYZ_STATUS_ERROR1 ECDH_STATUS_RESERVED - 1 + * #define ECCXYZ_STATUS_ERROR2 ECDH_STATUS_RESERVED - 2 + * @endcode + */ +#define ECDH_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECDH_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECDH_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECDH_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECDH_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECDH_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The result of the operation is the point at infinity. + * + * The operation yielded the point at infinity on this curve. This point is + * not permitted for further use in ECC operations. + */ +#define ECDH_STATUS_POINT_AT_INFINITY (-3) + +/*! + * @brief The private key passed in is larger or equal to the order of the curve. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER (-4) + +/*! + * @brief The private key passed in is zero. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_ZERO (-5) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-6) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-7) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECDH_STATUS_CANCELED (-8) + +/*! + * @brief The provided CryptoKey does not match the expected size + * + * The driver expects the private key to have the same length as other curve + * parameters and the public key to have a length of twice that plus one. + * If the provided CryptoKeys for the public and private keys do not match this + * scheme, this error will be returned. + */ +#define ECDH_STATUS_INVALID_KEY_SIZE (-9) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return ECDH_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define ECDH_STATUS_KEYSTORE_ERROR (-10) + +/*! + * @brief ECC Global configuration + * + * The ECDH_Config structure contains a set of pointers used to characterize + * the ECC driver implementation. + * + * This structure needs to be defined before calling ECDH_init() and it must + * not be changed thereafter. + * + * @sa ECDH_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECDH_Config; + +/*! + * @brief A handle that is returned from an ECDH_open() call. + */ +typedef ECDH_Config *ECDH_Handle; + +/*! + * @brief The way in which ECDH function calls return after performing a + * public key generation or shared secret compution operation. + * + * Callback return behavior is not supported by software-backed implementations. + * A NULL handle will be returned when attempting to open or construct a driver + * instance with an unsupported return behavior. + * + * Not all ECDH operations exhibit the specified return behavior. Functions that + * do not require significant computation and cannot offload that computation to + * a background thread behave like regular functions. Which functions exhibit + * the specfied return behavior is not implementation dependent. Specifically, a + * software-backed implementation run on the same CPU as the application will + * emulate the return behavior while not actually offloading the computation to + * the background thread. + * + * ECDH functions exhibiting the specified return behavior have restrictions on + * the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |ECDH_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECDH_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECDH_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes + * on in the background. ECC operation results are available + * after the function returns. + */ + ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC + * operation goes on in the background. ECC operation results + * are available after the function returns. + */ +} ECDH_ReturnBehavior; + +typedef enum +{ + ECDH_BIG_ENDIAN_KEY = 0, /*!< All ECDH key material (private key, public key, and shared secret (when used)) + * are in big-endian format + */ + ECDH_LITTLE_ENDIAN_KEY = 1, /*!< All ECDH key material (private key, public key, and shared secret (when used)) + * are in little-endian format + */ +} ECDH_KeyMaterialEndianness; + +/*! + * @brief Struct containing the parameters required to generate a public key. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key from which the new public + * key will be generated. (maybe your static key) + */ + CryptoKey *myPublicKey; /*!< A pointer to a public ECC key which has been initialized blank. + * Newly generated key will be placed in this location. + * The formatting byte will be filled in by the driver if the + * keyMaterialEndianness requires it. + */ + ECDH_KeyMaterialEndianness keyMaterialEndianness; /*!< All keyMaterials, including myPrivate and myPublicKey, + * are either in big-endian (default) or little-endian format + */ +} ECDH_OperationGeneratePublicKey; + +/*! + * @brief Struct containing the parameters required to compute the shared secret. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey. + * If ECDH_generateKey() was used, this should be the same private key. + */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key which will be used in to + * compute the shared secret. + */ + const CryptoKey *theirPublicKey; /*!< A pointer to the public key of the party with whom the + * shared secret will be generated. + */ + CryptoKey *sharedSecret; /*!< A pointer to a CryptoKey which has been initialized blank. + * The shared secret will be placed here. + * The formatting byte will be filled in by the driver if the + * keyMaterialEndianness requires it. + */ + ECDH_KeyMaterialEndianness keyMaterialEndianness; /*!< All keyMaterials, including myPrivate, theirPublicKey, and + * sharedSecret are either in big-endian (default) or little- + * endian format + */ +} ECDH_OperationComputeSharedSecret; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union +{ + ECDH_OperationGeneratePublicKey *generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ + ECDH_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct + */ +} ECDH_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY = 1, + ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET = 2, +} ECDH_OperationType; + +/*! + * @brief The definition of a callback function used by the ECDH driver + * when used in ::ECDH_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECDH operation. + * + * @param returnStatus The result of the ECDH operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECDH_CallbackFxn)(ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); + +/*! + * @brief ECC Parameters + * + * ECC Parameters are used to with the ECDH_open() call. Default values for + * these parameters are set using ECDH_Params_init(). + * + * @sa ECDH_Params_init() + */ +typedef struct +{ + ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout of the operation */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECDH_Params; + +/*! + * @brief Default ECDH_Params structure + * + * @sa ECDH_Params_init() + */ +extern const ECDH_Params ECDH_defaultParams; + +/*! + * @brief This function initializes the ECC module. + * + * @pre The ECDH_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECC driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECDH_init(void); + +/*! + * @brief Function to initialize the ECDH_Params struct to its defaults + * + * @param params An pointer to ECDH_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECDH_Params_init(ECDH_Params *params); + +/*! + * @brief This function opens a given ECC peripheral. + * + * @pre ECC controller has been initialized using ECDH_init() + * + * @param index Logical peripheral number for the ECC indexed into + * the ECDH_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECDH_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ECDH_init() + * @sa ECDH_close() + */ +ECDH_Handle ECDH_open(uint_least8_t index, const ECDH_Params *params); + +/*! + * @brief Function to close an ECC peripheral specified by the ECC handle + * + * @pre ECDH_open() has to be called first. + * + * @param handle An ECC handle returned from ECDH_open() + * + * @sa ECDH_open() + */ +void ECDH_close(ECDH_Handle handle); + +/*! + * @brief Function to initialize an ECDH_OperationGeneratePublicKey struct to its defaults + * + * @param operation A pointer to ECDH_OperationGeneratePublicKey structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Function to initialize an ECDH_OperationComputeSharedSecret struct to its defaults + * + * @param operation A pointer to ECDH_OperationComputeSharedSecret structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Generates a public key for use in key agreement. + * + * This function can be used to generate a public key from a private key. + * + * @param handle A ECDH handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECDH_OperationGeneratePublicKey_init() on @c operation. + * + * @post ECDH_computeSharedSecret() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_POINT_AT_INFINITY The computed public key is the point at infinity. + * @retval #ECDH_STATUS_PRIVATE_KEY_ZERO The provided private key is zero. + * @retval #ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER The provided private key is larger than or equal to the order + * of the curve. + * + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Computes a shared secret + * + * This secret can be used to generate shared keys for encryption and authentication. + * + * @param handle A ECDH handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * + * @pre Call ECDH_OperationComputeSharedSecret_init() on \c operation. + * Generate a shared secret off-chip or using ECDH_generatePublicKey() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE The foreign public key is not a point on the specified curve. + * @retval #ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME One of the public key coordinates is larger the the curve's + * prime. + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Cancels an ongoing ECDH operation. + * + * Asynchronously cancels an ECDH operation. Only available when using + * ECDH_RETURN_BEHAVIOR_CALLBACK or ECDH_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be ECDH_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECDH_STATUS_SUCCESS The operation was canceled. + * @retval #ECDH_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle); + +/** + * @brief Constructs a new ECDH object + * + * Unlike #ECDH_open(), #ECDH_construct() does not require the hwAttrs and + * object to be allocated in a #ECDH_Config array that is indexed into. + * Instead, the #ECDH_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #ECDH_Config describing the location of the object and hwAttrs. + * + * @param params #ECDH_Params to configure the driver instance. + * + * @return Returns a #ECDH_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +ECDH_Handle ECDH_construct(ECDH_Config *config, const ECDH_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECDH__include */ diff --git a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c new file mode 100644 index 00000000..d24ecf60 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c @@ -0,0 +1,1946 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(inc/hw_aes.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) + +#if (defined(__IAR_SYSTEMS_ICC__) || defined(__TI_COMPILER_VERSION__)) + #include + #define REV32 __rev +#else + #define REV32 __builtin_bswap32 +#endif + +/* Note: The AES-CCM one-step polling operations are specifically designed + * to optimize execution speed at the expense of code re-use and size. + */ + +#define B0_FLAGS_CCM_HAS_ADATA 0x40 /* bit 6 in the Flags field of B0 */ + +/** + * This AES CCM implementation limits AAD length to 0xFEFF (65279-bytes) to + * simplify the code and improve execution speed. + */ +/* 0xFEFF bytes, For 0 < l(a) <= (2^16 - 2^8) - 1 */ +#define B1_AAD_LENGTH_SMALL_LIMIT ((1UL << 16) - (1UL << 8) - 1UL) + +#define B1_AAD_LENGTH_SMALL_BYTES 2U /* If 0 < l(a) < (2^16 - 2^8), the length field is encoded as two octets */ +#define B1_AAD_SMALL_BYTES (AES_BLOCK_SIZE - B1_AAD_LENGTH_SMALL_BYTES) + +/** + * The threshold at which blocking and callback mode transfers will utilize DMA. + * For data lengths below this threshold, polling CPU R/W will be used instead + * of DMA. With task switching and interrupt overhead, it is inefficient to + * utilize DMA for shorter length operations. + * The threshold value must be a multiple of AES_BLOCK_SIZE. + */ +#define AESCCMLPF3_DMA_SIZE_THRESHOLD (1U * AES_BLOCK_SIZE) + +/* Forward declarations */ +static int_fast16_t AESCCMLPF3_addData(AESCCM_Handle handle, + AESCCM_OperationType operationType, + AESCCM_OperationUnion *operation, + const uint8_t *input, + uint8_t *output, + size_t inputLength); +static int_fast16_t AESCCMLPF3_addDataDMA(AESCCM_Handle handle, AESCCM_Mode direction, size_t inputLength); +static inline int_fast16_t AESCCMLPF3_finishTag(AESCCMLPF3_Object *object, AESCCM_Mode direction); +static int_fast16_t AESCCMLPF3_oneStepOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType); +static int_fast16_t AESCCMLPF3_performFinalizeChecks(const AESCCMLPF3_Object *object, + const AESCCM_SegmentedFinalizeOperation *operation); +static void AESCCMLPF3_processB0(const uint8_t *nonce, + uint8_t nonceLength, + size_t totalAADLength, + size_t totalDataLength, + uint8_t macLength); +static size_t AESCCMLPF3_processB1withAAD(const uint8_t *aad, size_t aadSegmentLength, size_t aadTotalLength); +static void AESCCMLPF3_processOneStepCBCMACPolling(AESCCM_OneStepOperation *operation, + uint32_t tag[AES_TAG_LENGTH_BYTES / 4U], + AESCCM_Mode direction); +static void AESCCMLPF3_processOneStepCTRPolling(AESCCM_OneStepOperation *operation, + uint32_t tag[AES_TAG_LENGTH_BYTES / 4U]); +static inline int_fast16_t AESCCMLPF3_processOneStepDecryptPolling(AESCCMLPF3_Object *object, + AESCCM_OneStepOperation *operation); +static inline int_fast16_t AESCCMLPF3_processOneStepEncryptPolling(AESCCMLPF3_Object *object, + AESCCM_OneStepOperation *operation); +static int_fast16_t AESCCMLPF3_setupSegmentedOperation(AESCCMLPF3_Object *object, + const CryptoKey *key, + size_t totalAADLength, + size_t totalDataLength, + size_t macLength); +static void AESCCMLPF3_processCBCMACFinalBlock(const uint8_t *input, size_t bytesRemaining); +static void AESCCMLPF3_processCTRCounterBlock(const uint8_t *nonce, uint8_t nonceLength, uint8_t counterVal); +static int_fast16_t AESCCMLPF3_processSegmentedCBCMAC(AESCCMLPF3_Object *object, + size_t aadSegmentLength, + size_t dataSegmentLength, + AESCCM_Mode direction); +static int_fast16_t AESCCMLPF3_processSegmentedCTR(AESCCMLPF3_Object *object, size_t dataSegmentLength); +static void AESCCMLPF3_processTagCTR(AESCCMLPF3_Object *object); +static int_fast16_t AESCCMLPF3_waitForDMA(const AESCCMLPF3_Object *object); + +/* + * ======== AESCCMLPF3_getObject ======== + */ +static inline AESCCMLPF3_Object *AESCCMLPF3_getObject(AESCCM_Handle handle) +{ + AESCCMLPF3_Object *object = (AESCCMLPF3_Object *)handle->object; + DebugP_assert(object); + + return object; +} + +/* + * ======== AESCCMLPF3_hwiFxn ======== + * + * Note: In order to support callback return behavior, there is an undesireable + * amount of processing done within this ISR. If support for callback return + * behavior can be removed in the future, this processing should be moved to + * the thread context to improve IRQ responsiveness. + */ +static void AESCCMLPF3_hwiFxn(uintptr_t arg0) +{ + bool isOpDone = false; + AESCCM_Handle handle = (AESCCM_Handle)arg0; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* For CBC-MAC, only the input channel A interrupt is enabled. + * For CTR, only the output channel B interrupt is enabled. + */ + uint32_t intStatus = AESGetMaskedInterruptStatus(); + + /* Disable DMA, clear interupts, and release power constraint */ + AESCommonLPF3_cleanupHwi(&object->common); + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + + if ((object->operationType == AESCCM_OP_TYPE_ONESTEP_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT)) + { + direction = AESCCM_MODE_DECRYPT; + } + + if ((intStatus & (uint32_t)AES_MIS_CHADONE_M) != (uint32_t)0U) + { + UDMALPF3_clearInterrupt(AESCommonLPF3_DMA_CHA_BITMASK); + + const uint8_t *plainText = object->input; + if (direction == AESCCM_MODE_DECRYPT) + { + plainText = object->output; + } + + /* DMA is used to process full blocks of data but there if there is a + * partial block of data remaining, handle it with CPU R/W. + */ + if (object->inputCBCMACLengthRemaining > 0U) + { + size_t inputCBCMACLengthRemaining = object->inputCBCMACLengthRemaining; + /* Use CPU R/W to complete the CBC-MAC operation */ + AESCCMLPF3_processCBCMACFinalBlock(&plainText[object->inputLength - inputCBCMACLengthRemaining], + inputCBCMACLengthRemaining); + + object->totalCBCMACLengthRemaining -= inputCBCMACLengthRemaining; + object->inputCBCMACLengthRemaining = 0U; + } + + /* Wait for operation to complete and save the intermediate tag */ + AESCMACLPF3_readTag((uint32_t *)&object->intermediateTag[0]); + + if (object->totalCBCMACLengthRemaining == 0U) + { + object->common.returnStatus = AESCCMLPF3_finishTag(object, direction); + } + + if (direction == AESCCM_MODE_DECRYPT) + { + isOpDone = true; + } + else /* Encrypt */ + { + object->common.returnStatus = AESCCMLPF3_processSegmentedCTR(object, object->inputLength); + + /* Operation will be handled without DMA if length less than threshold */ + if (object->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD) + { + isOpDone = true; + } + } + } + + if ((intStatus & (uint32_t)AES_MIS_CHBDONE_M) != (uint32_t)0U) + { + UDMALPF3_clearInterrupt(AESCommonLPF3_DMA_CHB_BITMASK); + + /* DMA is used to process all full blocks of data. If there is a + * partial block of data remaining, process it with CPU R/W. + */ + if (object->inputCTRLengthRemaining > 0U) + { + size_t inputCTRLengthRemaining = object->inputCTRLengthRemaining; + /* Use CPU R/W to complete the CTR operation */ + AESCTRLPF3_processData(&object->input[object->inputLength - inputCTRLengthRemaining], + &object->output[object->inputLength - inputCTRLengthRemaining], + inputCTRLengthRemaining, + true); + + object->totalCTRLengthRemaining -= inputCTRLengthRemaining; + object->inputCTRLengthRemaining = 0U; + } + + if (object->totalCTRLengthRemaining > 0U) + { + /* Store the counter if more input data is expected */ + AESCTRLPF3_readCounter((uint32_t *)&object->intermediateCounter[0]); + } + + if (direction == AESCCM_MODE_ENCRYPT) + { + isOpDone = true; + } + else /* Decrypt */ + { + object->common.returnStatus = AESCCMLPF3_processSegmentedCBCMAC(object, + 0U, + object->inputLength, + AESCCM_MODE_DECRYPT); + + /* Operation is completed without DMA if length < threshold */ + if (object->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD) + { + isOpDone = true; + } + } + } + + if (isOpDone) + { + /* Store sum of AES lengths in a temporary variable to explicitly + * define access order since both fields are volatile. + */ + size_t totalLengthRemaining = object->totalCTRLengthRemaining; + totalLengthRemaining += object->totalCBCMACLengthRemaining; + + if (totalLengthRemaining == 0U) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceLPF3_operationSemaphore); + } + else + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } + } +} + +/* + * ======== AESCCMLPF3_finishTag ======== + */ +static inline int_fast16_t AESCCMLPF3_finishTag(AESCCMLPF3_Object *object, AESCCM_Mode direction) +{ + int_fast16_t status = AESCCM_STATUS_SUCCESS; + + AESCCMLPF3_processTagCTR(object); + + if (object->mac != NULL) + { + if (direction == AESCCM_MODE_ENCRYPT) + { + (void)memcpy((void *)&object->mac[0], (void *)&object->intermediateTag[0], object->macLength); + } + else /* Decrypt */ + { + /* Perform a constant time comparison of the calculated MAC and the decrypted MAC */ + bool macValid = CryptoUtils_buffersMatch(object->intermediateTag, object->mac, (size_t)object->macLength); + + if (!macValid) + { + status = AESCCM_STATUS_MAC_INVALID; + } + } + } + + return status; +} + +/* + * ======== AESCCMLPF3_waitForDMA ======== + */ +static int_fast16_t AESCCMLPF3_waitForDMA(const AESCCMLPF3_Object *object) +{ + int_fast16_t status; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* This function may be called from handler or thread contexts. + * Only block on semaphore when called from thread context + * (i.e. Interrupt Program Status Register is zero) + */ + if ((uint32_t)__get_IPSR() == (uint32_t)0U) + { + /* Ignore return value since timeout is infinite */ + (void)SemaphoreP_pend((SemaphoreP_Handle)&CryptoResourceLPF3_operationSemaphore, + (uint32_t)SemaphoreP_WAIT_FOREVER); + } + + /* Return status stored in ISR */ + status = object->common.returnStatus; + } + else /* AES_RETURN_BEHAVIOR_CALLBACK */ + { + /* Success is always returned in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCCM_init ======== + */ +void AESCCM_init(void) +{ + AESCommonLPF3_init(); +} + +/* + * ======== AESCCM_construct ======== + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params) +{ + DebugP_assert(config); + + int_fast16_t status; + AESCCM_Handle handle = config; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &AESCCM_defaultParams; + } + + DebugP_assert((params->returnBehavior != AESCCM_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->callbackFxn = params->callbackFxn; + + status = AESCommonLPF3_construct(&object->common, (AES_ReturnBehavior)params->returnBehavior, params->timeout); + + if (status != AES_STATUS_SUCCESS) + { + handle = NULL; + } + + return handle; +} + +/* + * ======== AESCCM_close ======== + */ +void AESCCM_close(AESCCM_Handle handle) +{ + DebugP_assert(handle); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + AESCommonLPF3_close(&object->common); +} + +/* + * ======== AESCCMLPF3_processCBCMACFinalBlock ======== + */ +static void AESCCMLPF3_processCBCMACFinalBlock(const uint8_t *input, size_t bytesRemaining) +{ + /* No need to reload the last intermediate tag because it still loaded in + * the AES engine from the previous CBCMAC operation. + */ + + /* Must wait until engine is idle before clearing BUF */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + + /* Zero out the BUF registers */ + AESClearBUF(); + + /* Copy directly to BUF registers. memcpy is safe to use here since the + * order of the writes is not important when writing a partial block. + */ + (void)memcpy((void *)(AES_BASE + AES_O_BUF0), input, bytesRemaining); + +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + AESSetTrigger((uint32_t)AES_TRG_AESOP_TXTXBUF); +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + AESSetTrigger((uint32_t)AES_TRG_ECBOP_TXTXBUF); +#else + #error "Unsupported DeviceFamily_Parent for AESCMACLPF3!" +#endif +} + +#define M_PRIME_OFFSET 3 + +/* + * ======== AESCCMLPF3_processB0 ======== + */ +#if defined(__IAR_SYSTEMS_ICC__) + #pragma inline = forced +#elif defined(__TI_COMPILER_VERSION__) + #pragma FUNC_ALWAYS_INLINE(AESCCMLPF3_processB0) +#else +__attribute__((always_inline)) inline +#endif +static void AESCCMLPF3_processB0(const uint8_t *nonce, + uint8_t nonceLength, + size_t totalAADLength, + size_t totalDataLength, + uint8_t macLength) +{ + AES_BlockWordAligned B0; + + /* ============================================ + * First block B0 formatting per RFC3610: + * Octet Number Contents + * ------------ --------- + * 0 Flags + * 1 ... 15-L Nonce N + * 16-L ... 15 l(m) + * + * Flags in octet 0 of B0: + * Bit Number Contents + * ---------- ---------------------- + * 7 Reserved (always zero) + * 6 Adata + * 5 ... 3 M' + * 2 ... 0 L' + * ============================================ + */ + + /* Set L' + * nonceLength = 15 - L + * L' = L - 1 + * L' = 15 - nonceLength - 1 + * L' = 14 - nonceLength + */ + B0.words[0] = (uint32_t)14U - (uint32_t)nonceLength; + + /* Set M' + * M' = (M - 2) / 2 where M = length of MAC + */ + B0.words[0] |= (((uint32_t)macLength - (uint32_t)2U) >> 1) << M_PRIME_OFFSET; + + if (totalAADLength != 0U) + { + /* Set bit 6 (Adata) */ + B0.words[0] |= (uint32_t)B0_FLAGS_CCM_HAS_ADATA; + } + + /* Set l(m), the length of the message, in most-significant-byte first order. + * + * Do this before copying nonce so word-based write can be utilized and then + * nonce's byte-wise copy will overwrite parts of the word not used for l(m). + */ + B0.words[3] = REV32(totalDataLength); + + /* Copy nonce into B0, clearing bytes first to ensure uncopied bytes are zero. */ + B0.words[1] = (uint32_t)0U; + B0.words[2] = (uint32_t)0U; + + (void)memcpy(&B0.bytes[1], nonce, nonceLength); + + AESWriteBUF32(B0.words); +} + +/* + * ======== AESCCMLPF3_processB1withAAD ======== + */ +static size_t AESCCMLPF3_processB1withAAD(const uint8_t *aad, size_t aadSegmentLength, size_t aadTotalLength) +{ + size_t aadBytesProcessed = aadSegmentLength; + AES_BlockWordAligned B1; + + B1.words[0] = (uint32_t)0U; + B1.words[1] = (uint32_t)0U; + B1.words[2] = (uint32_t)0U; + B1.words[3] = (uint32_t)0U; + + /* Per RFC3610: If 0 < l(a) < (2^16 - 2^8), then the length field + * is encoded as two octets which contain the value l(a) in + * most-significant-byte first order. + * + * Note: Accessing via byte ptr is 5-cycles faster than using bit shift + * and masking. + */ + uint8_t *aadLengthBytePtr = (uint8_t *)&aadTotalLength; + B1.bytes[1] = *(aadLengthBytePtr); + B1.bytes[0] = *(aadLengthBytePtr + 1U); + + /* Append the remaining AAD bytes */ + if (aadSegmentLength == 1U) + { + /* Optimization for BLE stack use case which has 1-byte AAD */ + B1.bytes[2] = aad[0]; + } + else if (aadSegmentLength <= B1_AAD_SMALL_BYTES) + { + (void)memcpy((void *)&B1.bytes[2], (void *)aad, aadSegmentLength); + } + else + { + (void)memcpy((void *)&B1.bytes[2], (void *)aad, B1_AAD_SMALL_BYTES); + aadBytesProcessed = B1_AAD_SMALL_BYTES; + } + + /* B1 can be written to BUF while AES engine is still processing B0 */ + AESWriteBUF32(B1.words); + + return aadBytesProcessed; +} + +/* + * ======== AESCCMLPF3_processCBCMACPolling ======== + */ +static void AESCCMLPF3_processOneStepCBCMACPolling(AESCCM_OneStepOperation *operation, + uint32_t tag[AES_TAG_LENGTH_BYTES / 4U], + AESCCM_Mode direction) +{ + size_t dataBytesRemaining; + size_t aadBytesRemaining; + + AESSetAUTOCFG(AESCMACLPF3_DEFAULT_AUTOCFG); + + /* Set IV to zero */ + AESClearIV(); + + AESCCMLPF3_processB0(operation->nonce, + operation->nonceLength, + operation->aadLength, + operation->inputLength, + operation->macLength); + + /* Process AAD */ + if (operation->aadLength > 0U) + { + aadBytesRemaining = operation->aadLength; + + /* Process B1 with AAD */ + aadBytesRemaining -= AESCCMLPF3_processB1withAAD(operation->aad, operation->aadLength, operation->aadLength); + + /* Process any remaining AAD */ + if (aadBytesRemaining > 0U) + { + size_t blockSizeAlignedAADLength = AES_BLOCK_SIZE_MULTIPLE_LENGTH(aadBytesRemaining); + + if (blockSizeAlignedAADLength > 0U) + { + AESCMACLPF3_processBlocks(&operation->aad[operation->aadLength - aadBytesRemaining], + blockSizeAlignedAADLength); + + aadBytesRemaining -= blockSizeAlignedAADLength; + } + + if (aadBytesRemaining > 0U) + { + AESCCMLPF3_processCBCMACFinalBlock(&operation->aad[operation->aadLength - aadBytesRemaining], + aadBytesRemaining); + } + } + } + + dataBytesRemaining = operation->inputLength; + + if (dataBytesRemaining > 0U) + { + /* Perform CBCMAC on plaintext data, that is, depending on encryption/decryption, + * use input/output data respectively. + */ + + uint8_t *plainText = operation->input; + if (direction != AESCCM_MODE_ENCRYPT) + { + plainText = operation->output; + } + + size_t blockSizeAlignedDataRemaining = AES_BLOCK_SIZE_MULTIPLE_LENGTH(dataBytesRemaining); + + if (blockSizeAlignedDataRemaining > 0U) + { + AESCMACLPF3_processBlocks(plainText, blockSizeAlignedDataRemaining); + + dataBytesRemaining -= blockSizeAlignedDataRemaining; + } + + if (dataBytesRemaining > 0U) + { + AESCCMLPF3_processCBCMACFinalBlock(&plainText[operation->inputLength - dataBytesRemaining], + dataBytesRemaining); + } + } + + /* Wait for operation to complete and save the intermediate tag */ + AESCMACLPF3_readTag(&tag[0]); +} + +/* + * ======== AESCCMLPF3_processOneStepCTRPolling ======== + */ +static void AESCCMLPF3_processOneStepCTRPolling(AESCCM_OneStepOperation *operation, + uint32_t tag[AES_TAG_LENGTH_BYTES / 4U]) +{ + /* Init Counter Mode */ + if (operation->inputLength == 0U) + { + AESSetAUTOCFG(AESCTRLPF3_LAST_BLOCK_AUTOCFG); + } + else + { + AESSetAUTOCFG(AESCTRLPF3_DEFAULT_AUTOCFG); + } + + /* Process counter block with counter value of 0 */ + AESCCMLPF3_processCTRCounterBlock(operation->nonce, operation->nonceLength, (uint8_t)0U); + + /* ===================== + * Process Tag + * ===================== + */ + + /* XOR tag with encrypted counter block to form ciphertext */ + AESWriteTXTXOR32(tag); + + /* Read the tag ciphertext and trigger the encryption of the next counter block */ + AESReadTag32(tag); + + if (operation->inputLength > 0U) + { + /* ================== + * Process input data + * ================== + */ + AESCTRLPF3_processData(operation->input, operation->output, operation->inputLength, true); + } +} + +/* + * ======== AESCCMLPF3_processOneStepEncryptPolling ======== + */ +static inline int_fast16_t AESCCMLPF3_processOneStepEncryptPolling(AESCCMLPF3_Object *object, + AESCCM_OneStepOperation *operation) +{ + /* Calculate the MAC for the AAD and message */ + AESCCMLPF3_processOneStepCBCMACPolling(operation, (uint32_t *)&object->intermediateTag[0], AESCCM_MODE_ENCRYPT); + + /* Encrypt the MAC and the message */ + AESCCMLPF3_processOneStepCTRPolling(operation, (uint32_t *)&object->intermediateTag[0]); + + (void)memcpy((void *)&operation->mac[0], (void *)&object->intermediateTag[0], operation->macLength); + + /* This operation is always successful */ + return AESCCM_STATUS_SUCCESS; +} + +/* + * ======== AESCCMLPF3_processOneStepDecryptPolling ======== + */ +static inline int_fast16_t AESCCMLPF3_processOneStepDecryptPolling(AESCCMLPF3_Object *object, + AESCCM_OneStepOperation *operation) +{ + bool macValid; + int_fast16_t status = AESCCM_STATUS_MAC_INVALID; + uint32_t *mac; + + /* Use the object's intermediateCounter field which is only used for + * segmented operations to store the MAC to save stack space. + */ + mac = (uint32_t *)&object->intermediateCounter[0]; + + /* Create a word-aligned copy of the MAC */ + (void)memcpy((void *)mac, (void *)operation->mac, operation->macLength); + + /* Decrypt the MAC and the message */ + AESCCMLPF3_processOneStepCTRPolling(operation, mac); + + /* Calculate the MAC on the decrypted message and AAD */ + AESCCMLPF3_processOneStepCBCMACPolling(operation, (uint32_t *)&object->intermediateTag[0], AESCCM_MODE_DECRYPT); + + /* Perform a constant time comparision of the calculated MAC and the decrypted MAC */ + macValid = CryptoUtils_buffersMatch(object->intermediateTag, mac, (size_t)operation->macLength); + + if (macValid) + { + status = AESCCM_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCCMLPF3_oneStepOperation ======== + */ +static int_fast16_t AESCCMLPF3_oneStepOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->key); + /* Internally generated nonces aren't supported for now */ + DebugP_assert(!operation->nonceInternallyGenerated); + DebugP_assert(operation->nonce && (operation->nonceLength >= 7U) && (operation->nonceLength <= 13U)); + DebugP_assert((operation->aad && (operation->aadLength > 0U)) || + (operation->input && (operation->inputLength > 0U))); + DebugP_assert(operation->mac && (operation->macLength <= 16U)); + /* Implementation only supports aadLength to 65,279 bytes */ + DebugP_assert(operation->aadLength <= B1_AAD_LENGTH_SMALL_LIMIT) + + bool dmaActive = false; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* The nonce length must be 7 to 13 bytes long */ + if ((operation->nonceLength < (uint8_t)7U) || (operation->nonceLength > (uint8_t)13U)) + { + return AESCCM_STATUS_ERROR; + } + + /* The combined length of AAD and payload data must be non-zero. */ + if ((operation->aadLength + operation->inputLength) == 0U) + { + return AESCCM_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCCM_STATUS_ERROR; + } + + /* Check if there is no operation already in progress for this driver + * instance, and then mark the current operation to be in progress. + */ + status = AESCommonLPF3_setOperationInProgress(&object->common); + + if (status != AES_STATUS_SUCCESS) + { + return status; + } + + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + object->common.returnStatus = AESCCM_STATUS_SUCCESS; + + AESCommonLPF3_loadKey(operation->key); + + /* Process all one-step operations with data length less than the DMA size + * threshold as a polling mode operation. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (operation->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + if (operationType == AESCCM_OP_TYPE_ONESTEP_ENCRYPT) + { + status = AESCCMLPF3_processOneStepEncryptPolling(object, operation); + } + else /* operationType == AESCCM_OP_TYPE_ONESTEP_DECRYPT */ + { + status = AESCCMLPF3_processOneStepDecryptPolling(object, operation); + } + } + else + { + object->operation = (AESCCM_OperationUnion *)operation; + object->operationType = operationType; + + /* Copy data pointers */ + object->input = operation->input; + object->output = operation->output; + object->mac = operation->mac; + object->aad = operation->aad; + object->nonce = operation->nonce; + + /* Copy length info */ + object->nonceLength = operation->nonceLength; + object->totalAADLength = operation->aadLength; + object->totalDataLength = operation->inputLength; + object->totalCBCMACLengthRemaining = operation->inputLength; + object->totalCTRLengthRemaining = operation->inputLength; + object->macLength = operation->macLength; + + /* Init AAD processing vars */ + object->aadBytesProcessed = 0U; + object->bufferedAADLength = (uint8_t)0U; + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + + if (operationType == AESCCM_OP_TYPE_ONESTEP_DECRYPT) + { + direction = AESCCM_MODE_DECRYPT; + } + + if ((operation->aadLength > 0U) && (status == AESCCM_STATUS_SUCCESS)) + { + /* Process the entire AAD using CPU R/W. It is expected that + * the AAD length is relatively short (<= 64-bytes). Therefore, + * using DMA is inefficient after DMA setup, task switching, + * and interrupt overhead are accounted for. + */ + status = AESCCMLPF3_processSegmentedCBCMAC(object, operation->aadLength, 0, direction); + } + + if ((operation->inputLength > 0U) && (status == AESCCM_STATUS_SUCCESS)) + { + /* Process Data with DMA */ + status = AESCCMLPF3_addDataDMA(handle, direction, operation->inputLength); + dmaActive = true; + } + } + + if (!dmaActive) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCCM_oneStepEncrypt ======== + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) +{ + return AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_ENCRYPT); +} + +/* + * ======== AESCCM_oneStepDecrypt ======== + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) +{ + return AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_DECRYPT); +} + +/* + * ======== AESCCMLPF3_setupSegmentedOperation ======== + */ +static int_fast16_t AESCCMLPF3_setupSegmentedOperation(AESCCMLPF3_Object *object, + const CryptoKey *key, + size_t totalAADLength, + size_t totalDataLength, + size_t macLength) +{ + DebugP_assert(key); + + int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + + if (status == AES_STATUS_SUCCESS) + { + /* If the user doesn't provide the total lengths in the setupXXXX() + * calls, they must provide the lengths in setLengths(). + */ + object->totalAADLength = totalAADLength; + object->totalDataLength = totalDataLength; + object->macLength = (uint8_t)macLength; + + object->totalCTRLengthRemaining = totalDataLength; + object->totalCBCMACLengthRemaining = totalDataLength; + object->aadBytesProcessed = 0U; + object->bufferedAADLength = (uint8_t)0U; + + /* Initialize MAC pointer to NULL to avoid premature processing of the + * MAC in the ISR. + */ + object->mac = NULL; + + /* Initialize operation pointer to NULL in case AESCCM_cancelOperation + * is called after AESCCM_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + } + + return status; +} + +/* + * ======== AESCCM_setupEncrypt ======== + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + DebugP_assert(handle); + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + int_fast16_t status = AESCCMLPF3_setupSegmentedOperation(object, + key, + totalAADLength, + totalPlaintextLength, + macLength); + if (status == AES_STATUS_SUCCESS) + { + object->operationType = AESCCM_OPERATION_TYPE_ENCRYPT; + } + + return status; +} + +/* + * ======== AESCCM_setupDecrypt ======== + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + DebugP_assert(handle); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + int_fast16_t status = AESCCMLPF3_setupSegmentedOperation(object, + key, + totalAADLength, + totalPlaintextLength, + macLength); + if (status == AESCCM_STATUS_SUCCESS) + { + object->operationType = AESCCM_OPERATION_TYPE_DECRYPT; + } + + return status; +} + +/* + * ======== AESCCM_setLengths ======== + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength) +{ + DebugP_assert(handle); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* This shouldn't be called after addXXX() or finalizeXXX() */ + DebugP_assert(object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + /* Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + /* The combined length of AAD and payload data must be non-zero. */ + if ((aadLength == 0U) && (plaintextLength == 0U)) + { + return AESCCM_STATUS_ERROR; + } + + object->totalAADLength = aadLength; + object->totalDataLength = plaintextLength; + object->totalCBCMACLengthRemaining = plaintextLength; + object->totalCTRLengthRemaining = plaintextLength; + object->macLength = (uint8_t)macLength; + + return AESCCM_STATUS_SUCCESS; +} + +/* + * ======== AESCCM_setNonce ======== + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength) +{ + DebugP_assert(handle); + DebugP_assert(nonce); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* This function cannot be called after addXXX() or finalizeXXX() */ + DebugP_assert((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT)); + + /* Don't continue the segmented operation if there + * was an error during setup. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + /* The nonce length must be 7 to 13 bytes long */ + if ((nonceLength < 7U) || (nonceLength > 13U)) + { + return AESCCM_STATUS_ERROR; + } + + object->nonce = nonce; + object->nonceLength = (uint8_t)nonceLength; + + return AESCCM_STATUS_SUCCESS; +} + +/* + * ======== AESCCM_generateNonce ======== + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength) +{ + DebugP_assert(handle); + DebugP_assert(nonce); + DebugP_assert(nonceSize > 0U); + DebugP_assert(nonceLength); + + /* This feature is not currently supported */ + return AESCCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESCCMLPF3_processSegmentedCBCMAC ======== + */ +static int_fast16_t AESCCMLPF3_processSegmentedCBCMAC(AESCCMLPF3_Object *object, + size_t aadSegmentLength, + size_t dataSegmentLength, + AESCCM_Mode direction) +{ + bool dmaActive = false; + int_fast16_t status = AESCCM_STATUS_SUCCESS; + size_t aadBytesRemaining = 0U; + size_t dataBytesRemaining = 0U; + + AESSetAUTOCFG(AESCMACLPF3_DEFAULT_AUTOCFG); + + /* Process B0 block if no AAD and no data has been proceeded yet */ + if ((object->aadBytesProcessed == 0U) && (object->totalCBCMACLengthRemaining == object->totalDataLength)) + { + /* Set IV to zero */ + AESClearIV(); + + AESCCMLPF3_processB0(object->nonce, + object->nonceLength, + object->totalAADLength, + object->totalDataLength, + object->macLength); + } + else + { + /* Restore intermediate tag */ + AESWriteTag32((uint32_t *)&object->intermediateTag[0]); + } + + /* =========== + * Process AAD + * =========== + */ + if (aadSegmentLength > 0U) + { + aadBytesRemaining = aadSegmentLength; + + if (object->aadBytesProcessed == 0U) + { + /* Process B1 with AAD */ + object->aadBytesProcessed = AESCCMLPF3_processB1withAAD(object->aad, + aadSegmentLength, + object->totalAADLength); + aadBytesRemaining -= object->aadBytesProcessed; + } + + /* Process any remaining AAD */ + if (aadBytesRemaining > 0U) + { + /* Check for any buffered AAD from the previous transaction. + * Due to the AAD length parameter restrictions on AESCCM_addAAD(), + * there always must be two bytes of buffered AAD if non-zero. + */ + if (object->bufferedAADLength > (uint8_t)0U) + { + AES_BlockWordAligned aadBlock; + + aadBlock.words[0] = (uint32_t)0U; + aadBlock.words[1] = (uint32_t)0U; + aadBlock.words[2] = (uint32_t)0U; + aadBlock.words[3] = (uint32_t)0U; + + /* Copy buffered AAD into the local AAD block */ + aadBlock.bytes[0] = object->bufferedAAD[0]; + aadBlock.bytes[1] = object->bufferedAAD[1]; + + size_t aadBlockBytesAvail = (AES_BLOCK_SIZE - AESCCMLPF3_AAD_BUFFER_SIZE); + const uint8_t *newAAD = &object->aad[aadSegmentLength - aadBytesRemaining]; + + /* Copy the new AAD into the local AAD block */ + if (aadBytesRemaining >= aadBlockBytesAvail) + { + (void)memcpy((void *)&aadBlock.bytes[AESCCMLPF3_AAD_BUFFER_SIZE], + (void *)newAAD, + aadBlockBytesAvail); + + object->aadBytesProcessed += AES_BLOCK_SIZE; + aadBytesRemaining -= aadBlockBytesAvail; + } + else + { + (void)memcpy((void *)&aadBlock.bytes[AESCCMLPF3_AAD_BUFFER_SIZE], + (void *)newAAD, + aadBytesRemaining); + + object->aadBytesProcessed += (aadBytesRemaining + AESCCMLPF3_AAD_BUFFER_SIZE); + aadBytesRemaining = 0U; + } + + AESCMACLPF3_processBlocks(aadBlock.bytes, sizeof(aadBlock)); + + object->bufferedAADLength = (uint8_t)0U; + } + + size_t blockSizeAlignedAADLength = AES_BLOCK_SIZE_MULTIPLE_LENGTH(aadBytesRemaining); + + if (blockSizeAlignedAADLength > 0U) + { + AESCMACLPF3_processBlocks(&object->aad[aadSegmentLength - aadBytesRemaining], + blockSizeAlignedAADLength); + + object->aadBytesProcessed += blockSizeAlignedAADLength; + aadBytesRemaining -= blockSizeAlignedAADLength; + } + + if (aadBytesRemaining > 0U) + { + if ((object->aadBytesProcessed + aadBytesRemaining) == object->totalAADLength) + { + AESCCMLPF3_processCBCMACFinalBlock(&object->aad[aadSegmentLength - aadBytesRemaining], + aadBytesRemaining); + object->aadBytesProcessed += aadBytesRemaining; + } + else if (aadBytesRemaining == AESCCMLPF3_AAD_BUFFER_SIZE) + { + /* Save leftover AAD bytes to process later */ + const uint8_t *aadRemaining = &object->aad[aadSegmentLength - AESCCMLPF3_AAD_BUFFER_SIZE]; + object->bufferedAAD[0] = *aadRemaining; + object->bufferedAAD[1] = *(aadRemaining + 1U); + object->bufferedAADLength = (uint8_t)AESCCMLPF3_AAD_BUFFER_SIZE; + } + else + { + /* This should never happen if API restrictions on AAD length are followed */ + AESAbort(); + return AESCCM_STATUS_ERROR; + } + } + } + } + + /* ============ + * Process Data + * ============ + */ + if (dataSegmentLength > 0U) + { + dataBytesRemaining = dataSegmentLength; + + /* Perform CBC-MAC on plaintext data: + * - For encryption, plaintext data points to object's input. + * - For decryption, plaintext data points to object's output. + */ + const uint8_t *plainText = object->input; + if (direction == AESCCM_MODE_DECRYPT) + { + plainText = object->output; + } + + size_t blockSizeAlignedDataRemaining = AES_BLOCK_SIZE_MULTIPLE_LENGTH(dataBytesRemaining); + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (blockSizeAlignedDataRemaining < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + /* Process all the full blocks of data */ + if (blockSizeAlignedDataRemaining > 0U) + { + AESCMACLPF3_processBlocks(plainText, blockSizeAlignedDataRemaining); + + dataBytesRemaining -= blockSizeAlignedDataRemaining; + } + + if (dataBytesRemaining > 0U) + { + AESCCMLPF3_processCBCMACFinalBlock(&plainText[dataSegmentLength - dataBytesRemaining], + dataBytesRemaining); + } + + object->inputCBCMACLengthRemaining -= dataSegmentLength; + object->totalCBCMACLengthRemaining -= dataSegmentLength; + } + else + { + /* Clear BUSHALT when using DMA */ + AESClearAUTOCFGBusHalt(); + + /* Setup DMA configuration and set power constraint */ + AESCommonLPF3_setupDMA(&object->common, AESCBCMACLPF3_DMA_CONFIG); + + AESCommonLPF3_configInputDMA(plainText, blockSizeAlignedDataRemaining); + + /* Enable interrupt upon input DMA done */ + AESSetIMASK((uint32_t)AES_IMASK_CHADONE_M); + + object->inputCBCMACLengthRemaining -= blockSizeAlignedDataRemaining; + object->totalCBCMACLengthRemaining -= blockSizeAlignedDataRemaining; + + dmaActive = true; + + /* Manually trigger the DMA to start the CBC-MAC operation */ + AESSetTrigger((uint32_t)AES_TRG_DMACHA); + } + } + + if (dmaActive) + { + status = AESCCMLPF3_waitForDMA(object); + } + else + { + /* Wait for operation to complete and save the intermediate tag */ + AESCMACLPF3_readTag((uint32_t *)&object->intermediateTag[0]); + } + + return status; +} + +/* + * ======== AESCCMLPF3_processCTRCounterBlock ======== + */ +static void AESCCMLPF3_processCTRCounterBlock(const uint8_t *nonce, uint8_t nonceLength, uint8_t counterVal) +{ + /* ============================================ + * Initial flags, nonce, and counter formatting per RFC3610: + * Octet Number Contents + * ------------ --------- + * 0 Flags + * 1 ... 15-L Nonce N + * 16-L ... 15 Counter i (most-significant-byte first) + * + * The Flags field is formatted as follows: + * + * Bit Number Contents + * ---------- ---------------------- + * 7 Reserved (always zero) + * 6 Reserved (always zero) + * 5 ... 3 Zero + * 2 ... 0 L' + * + * where L' = 14 - nonceLength + * ============================================ + */ + AES_BlockWordAligned counter; + + counter.words[0] = (uint32_t)0U; + counter.words[1] = (uint32_t)0U; + counter.words[2] = (uint32_t)0U; + counter.words[3] = (uint32_t)0U; + + counter.bytes[0] = (uint8_t)14U - nonceLength; + + (void)memcpy((void *)&counter.bytes[1], (void *)nonce, nonceLength); + + counter.bytes[15] = counterVal; + + /* Initial write to AES_O_BUF3 triggers the encryption */ + AESCTRLPF3_writeCounter(counter.words); + + /* Wait for encryption of counter block to complete */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} +} + +/* + * ======== AESCCMLPF3_processTagCTR ======== + */ +static void AESCCMLPF3_processTagCTR(AESCCMLPF3_Object *object) +{ + /* Use default CTR config without AES_AUTOCFG_TRGAES_RDTXT3 + * to avoid triggering an encryption of the next counter value + * when reading out the encrypted tag. + */ + AESSetAUTOCFG(AESCTRLPF3_LAST_BLOCK_AUTOCFG); + + /* Process counter block with counter value of 0 */ + AESCCMLPF3_processCTRCounterBlock(object->nonce, object->nonceLength, (uint8_t)0U); + + /* XOR tag with encrypted counter block to form ciphertext */ + AESWriteTXTXOR32((uint32_t *)&object->intermediateTag[0]); + + /* Read the tag ciphertext */ + AESReadTag32((uint32_t *)&object->intermediateTag[0]); +} + +/* + * ======== AESCCMLPF3_processSegmentedCTR ======== + */ +static int_fast16_t AESCCMLPF3_processSegmentedCTR(AESCCMLPF3_Object *object, size_t dataSegmentLength) +{ + bool dmaActive = false; + bool firstCounter = false; + int_fast16_t status = AESCCM_STATUS_SUCCESS; + + if (object->totalCTRLengthRemaining == object->totalDataLength) + { + firstCounter = true; + } + + AESSetAUTOCFG(AESCTRLPF3_DEFAULT_AUTOCFG); + + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + (dataSegmentLength >= AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + size_t bytesProcessed; + + bytesProcessed = AESCTRLPF3_configDataDMA(&object->common, object->input, object->output, dataSegmentLength); + + object->totalCTRLengthRemaining -= bytesProcessed; + object->inputCTRLengthRemaining -= bytesProcessed; + + dmaActive = true; + } + + /* Writing the counter value will trigger the first encryption */ + if (firstCounter) + { + /* Process counter block with initial counter value of 1 */ + AESCCMLPF3_processCTRCounterBlock(object->nonce, object->nonceLength, (uint8_t)1U); + } + else + { + /* Restore intermediate counter */ + AESCTRLPF3_writeCounter((uint32_t *)&object->intermediateCounter[0]); + } + + if (dmaActive) + { + status = AESCCMLPF3_waitForDMA(object); + } + else + { + /* Process data with CPU R/W */ + AESCTRLPF3_processData(object->input, object->output, dataSegmentLength, false); + + object->totalCTRLengthRemaining -= dataSegmentLength; + + /* Store the counter */ + AESCTRLPF3_readCounter((uint32_t *)&object->intermediateCounter[0]); + } + + return status; +} + +/* + * ======== AESCCM_addAAD ======== + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + object->operation = (AESCCM_OperationUnion *)operation; + + /* Don't continue the segmented operation if there + * was an error or a cancellation. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + /* This operation can be called after setup or after addAAD again. */ + DebugP_assert((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT)); + + size_t calcAADLen = object->aadBytesProcessed + (size_t)object->bufferedAADLength + operation->aadLength; + + /* The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of AAD. + */ + if ((operation->aadLength == 0U) || + ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->aadLength) > 0U) && (calcAADLen != object->totalAADLength))) + { + return AESCCM_STATUS_ERROR; + } + + /* The total AAD input length must not exceed the total length specified + * in AESCCM_setLengths() or the setupXXXX() call. + */ + if (calcAADLen > object->totalAADLength) + { + return AESCCM_STATUS_ERROR; + } + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + AESCCM_OperationType operationType = AESCCM_OP_TYPE_AAD_ENCRYPT; + + if ((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT)) + { + direction = AESCCM_MODE_DECRYPT; + operationType = AESCCM_OP_TYPE_AAD_DECRYPT; + } + + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + + /* Load only the key into the AES engine now. The AUTOCFG values are loaded as needed + * depending on whether it's a CTR operation or a CBC-MAC operation. + */ + AESCommonLPF3_loadKey(&object->common.key); + + object->operationType = operationType; + object->aad = operation->aad; + + /* AAD is expected to be relatively short in length (< a few AES blocks) + * so DMA is not utilized for blocking and callback modes because the + * interrupt and task switching overhead would outweigh any CPU cycles + * saved using DMA. Code size and complexity is reduced by not supporting + * DMA for AAD. + */ + + status = AESCCMLPF3_processSegmentedCBCMAC(object, operation->aadLength, 0, direction); + + if ((status == AESCCM_STATUS_SUCCESS) && (object->totalDataLength == 0U) && + (object->aadBytesProcessed == object->totalAADLength)) + { + AESCCMLPF3_processTagCTR(object); + } + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + object->common.returnStatus = status; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCCMLPF3_addDataDMA ======== + */ +static int_fast16_t AESCCMLPF3_addDataDMA(AESCCM_Handle handle, AESCCM_Mode direction, size_t inputLength) +{ + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + object->inputLength = inputLength; + object->inputCBCMACLengthRemaining = inputLength; + + object->inputLength = inputLength; + object->inputCTRLengthRemaining = inputLength; + + /* We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + AESCCMLPF3_HWAttrs const *hwAttrs = handle->hwAttrs; + AESCommonLPF3_setupHwi(AESCCMLPF3_hwiFxn, (uintptr_t)handle, hwAttrs->intPriority); + + if (direction == AESCCM_MODE_ENCRYPT) + { + status = AESCCMLPF3_processSegmentedCBCMAC(object, 0U, inputLength, AESCCM_MODE_ENCRYPT); + } + else + { + status = AESCCMLPF3_processSegmentedCTR(object, inputLength); + } + + return status; +} + +/* + * ======== AESCCMLPF3_addData ======== + */ +static int_fast16_t AESCCMLPF3_addData(AESCCM_Handle handle, + AESCCM_OperationType operationType, + AESCCM_OperationUnion *operation, + const uint8_t *input, + uint8_t *output, + size_t inputLength) +{ + int_fast16_t status = AESCCM_STATUS_SUCCESS; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + + /* Load only the key into the AES engine now. The AUTOCFG values are loaded as needed + * depending on whether it's a CTR operation or a CBC-MAC operation. + */ + AESCommonLPF3_loadKey(&object->common.key); + + object->operationType = operationType; + object->operation = operation; + + object->input = input; + object->output = output; + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + + if ((object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT)) + { + direction = AESCCM_MODE_DECRYPT; + } + + /* Process all segmented operations with data length less than the DMA + * size threshold as a polling mode operation. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || (inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + if (direction == AESCCM_MODE_ENCRYPT) + { + status = AESCCMLPF3_processSegmentedCBCMAC(object, 0, inputLength, AESCCM_MODE_ENCRYPT); + } + + if (status == AESCCM_STATUS_SUCCESS) + { + status = AESCCMLPF3_processSegmentedCTR(object, inputLength); + } + + if ((direction == AESCCM_MODE_DECRYPT) && (status == AESCCM_STATUS_SUCCESS)) + { + status = AESCCMLPF3_processSegmentedCBCMAC(object, 0U, inputLength, AESCCM_MODE_DECRYPT); + } + + if ((object->totalCBCMACLengthRemaining == 0U) && (status == AESCCM_STATUS_SUCCESS)) + { + AESCCMLPF3_processTagCTR(object); + } + + object->common.returnStatus = status; + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + } + else + { + status = AESCCMLPF3_addDataDMA(handle, direction, inputLength); + + if (status != AESCCM_STATUS_SUCCESS) + { + object->common.returnStatus = status; + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + } + } + + return status; +} + +/* + * ======== AESCCM_addData ======== + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + /* This operation can be called after setupXXXX, addAAD, or addData */ + DebugP_assert((object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT)); + + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of payload data + */ + if ((operation->inputLength == 0U) || ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U) && + (operation->inputLength != object->totalCBCMACLengthRemaining))) + { + return AESCCM_STATUS_ERROR; + } + + /* The total input length must not exceed the lengths specified in + * AESCCM_setLengths() or setupXXXX(). + */ + if (operation->inputLength > object->totalCBCMACLengthRemaining) + { + return AESCCM_STATUS_ERROR; + } + + /* The AAD input length specified so far must match the total length + * specified in the setLengths() or setupXXXX() calls. + * All AAD input must be processed at this point. + */ + if (object->aadBytesProcessed != object->totalAADLength) + { + return AESCCM_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCCM_STATUS_ERROR; + } + + AESCCM_OperationType operationType = AESCCM_OP_TYPE_DATA_ENCRYPT; + + if ((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) || (object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT)) + { + operationType = AESCCM_OP_TYPE_DATA_DECRYPT; + } + + status = AESCCMLPF3_addData(handle, + operationType, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && + (operation->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCCM_finalizeEncrypt ======== + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + status = AESCCMLPF3_performFinalizeChecks(object, operation); + + if (status != AESCCM_STATUS_SUCCESS) + { + return status; + } + + if (operation->inputLength > 0U) + { + object->mac = operation->mac; + object->macLength = operation->macLength; + + status = AESCCMLPF3_addData(handle, + AESCCM_OP_TYPE_FINALIZE_ENCRYPT, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + } + + /* If the return behavior is polling or the operation is finalized with + * input length less than the DMA size threshold (which includes the case + * of finalizing without any additional data), all data processing will + * be complete at this point. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (operation->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + if (status == AESCCM_STATUS_SUCCESS) + { + (void)memcpy(operation->mac, (uint32_t *)&object->intermediateTag[0], operation->macLength); + } + else + { + object->common.returnStatus = status; + } + + AESCommonLPF3_clearOperationInProgress(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_ENCRYPT); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCCM_finalizeDecrypt ======== + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + status = AESCCMLPF3_performFinalizeChecks(object, operation); + + if (status != AESCCM_STATUS_SUCCESS) + { + return status; + } + + if (operation->inputLength > 0U) + { + object->mac = operation->mac; + object->macLength = operation->macLength; + + status = AESCCMLPF3_addData(handle, + AESCCM_OP_TYPE_FINALIZE_DECRYPT, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + } + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (operation->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) + { + if (status == AESCCM_STATUS_SUCCESS) + { + /* Perform a constant time comparision of the calculated MAC and the decrypted MAC */ + bool macValid = CryptoUtils_buffersMatch(object->intermediateTag, + operation->mac, + (size_t)operation->macLength); + + if (!macValid) + { + status = AESCCM_STATUS_MAC_INVALID; + } + } + else + { + object->common.returnStatus = status; + } + + AESCommonLPF3_clearOperationInProgress(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_DECRYPT); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCCMLPF3_performFinalizeChecks ======== + */ +static int_fast16_t AESCCMLPF3_performFinalizeChecks(const AESCCMLPF3_Object *object, + const AESCCM_SegmentedFinalizeOperation *operation) +{ + /* This operation can be called after setupXXXX, addAAD, or addData */ + DebugP_assert((object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT)); + + /* Don't continue the segmented operation if there + * was an error or a cancellation. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* All AAD should be processed at this point in time. */ + if (object->aadBytesProcessed != object->totalAADLength) + { + return AESCCM_STATUS_ERROR; + } + + /* Additional payload data can be passed in finalize */ + if (operation->inputLength != object->totalCBCMACLengthRemaining) + { + return AESCCM_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCCM_STATUS_ERROR; + } + + return AESCCM_STATUS_SUCCESS; +} + +/* + * ======== AESCCM_cancelOperation ======== + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) +{ + DebugP_assert(handle); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* Cancellation is only supported in callback mode */ + if (object->common.returnBehavior != AES_RETURN_BEHAVIOR_CALLBACK) + { + return AESCCM_STATUS_ERROR; + } + + uintptr_t interruptKey = HwiP_disable(); + + /* Return success if there is no active operation to cancel. + * Do not execute the callback as it would have been executed already + * when the operation completed. + */ + if (!object->common.operationInProgress) + { + HwiP_restore(interruptKey); + } + else + { + HwiP_restore(interruptKey); + + /* Cancel DMA for input and output channels, clear operation in-progress, + * and releases crypto resource if necessary. + */ + AESCommonLPF3_cancelOperation(&object->common, true); + + /* Operation pointer could be NULL if a segmented operation was setup + * but neither AESCCM_addData or AESCCM_finalize was called. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESCCM_STATUS_CANCELED, object->operation, object->operationType); + } + } + + return AESCCM_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h new file mode 100644 index 00000000..fb7491ea --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESCCMLPF3.h + * + * @brief AESCCM driver implementation for the Low Power F3 family + * + * # CCM Specification + * This implementation follows NIST 800-38c - + * https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38c.pdf + * All symbols used in the implementation for identifiers and in the comments including + * but not limited to B0, B1 and S0 are all adopted from this NIST 800-38c. + * + * # Hardware Accelerator # + * The Low Power F3 family of devices has a dedicated AES hardware that can perform + * AES encryption operations with 128-bit keys. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - Maximum AAD length is limited to 65279-bytes. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesccm_AESCCMLPF3__include +#define ti_drivers_aesccm_AESCCMLPF3__include + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +#define AESCCMLPF3_AAD_BUFFER_SIZE 2U + +/*! + * @brief AESCCMLPF3 Hardware Attributes + * + * AESCCMLPF3 hardware attributes should be included in the board file + * and pointed to by the AESCCM_config struct. + */ +typedef AESCommonLPF3_HWAttrs AESCCMLPF3_HWAttrs; + +/*! + * @brief AESCCMLPF3 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* Common member first to allow struct to be cast to the common type */ + AESCommonLPF3_Object common; + const uint8_t *aad; + const uint8_t *input; + uint8_t *output; + const uint8_t *nonce; + uint8_t *mac; + volatile uint32_t intermediateCounter[AES_IV_LENGTH_BYTES / 4]; + volatile uint32_t intermediateTag[AES_TAG_LENGTH_BYTES / 4]; + AESCCM_CallbackFxn callbackFxn; + AESCCM_OperationUnion *operation; + size_t inputLength; + volatile size_t inputCBCMACLengthRemaining; + volatile size_t inputCTRLengthRemaining; + size_t totalAADLength; + size_t totalDataLength; + size_t aadBytesProcessed; + volatile size_t totalCBCMACLengthRemaining; + volatile size_t totalCTRLengthRemaining; + AESCCM_OperationType operationType; + uint8_t bufferedAAD[AESCCMLPF3_AAD_BUFFER_SIZE]; + uint8_t bufferedAADLength; + uint8_t macLength; + uint8_t nonceLength; +} AESCCMLPF3_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c new file mode 100644 index 00000000..a55543ca --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c @@ -0,0 +1,948 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(inc/hw_aes.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/** + * The threshold at which blocking and callback mode transfers will utilize DMA. + * For data lengths below this threshold, polling CPU R/W will be used instead + * of DMA. With task switching and interrupt overhead, it is inefficient to + * utilize DMA for shorter length operations. + * The threshold value must be a multiple of AES_BLOCK_SIZE. + */ +#define AESCMACLPF3_DMA_SIZE_THRESHOLD (1U * AES_BLOCK_SIZE) + +#define AESCMAC_CONST_RB ((uint8_t)0x87U) +#define AESCMAC_MSB_CHECK ((uint8_t)0x80U) +#define AESCMAC_PADDING ((uint8_t)0x80U) + +typedef enum +{ + AESCMAC_SUBKEY1, + AESCMAC_SUBKEY2 +} AESCMAC_SUBKEY_NUM; + +/* Forward declarations */ +static void AESCMACLPF3_deriveSubKey(uint8_t *buffer); +static void AESCMACLPF3_generateSubKey(AESCMAC_SUBKEY_NUM subKeyNum, uint32_t subKey[AES_BLOCK_SIZE_WORDS]); +static void AESCMACLPF3_getResult(AESCMACLPF3_Object *object); +static inline void AESCMACLPF3_prepareFinalInputBlock(AESCMACLPF3_Object *object, size_t *transactionLength); +static int_fast16_t AESCMACLPF3_setupSegmentedOperation(AESCMACLPF3_Object *object, const CryptoKey *key); +static int_fast16_t AESCMACLPF3_oneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + const CryptoKey *key, + AESCMAC_OperationType operationType); +static int_fast16_t AESCMACLPF3_startOperation(AESCMAC_Handle handle); +static inline int_fast16_t AESCMACLPF3_waitForResult(AESCMAC_Handle handle); +static inline void AESCMACLPF3_xorBlock(uint32_t *block1_dst, const uint32_t *block2); + +/* + * ======== AESCMACLPF3_getObject ======== + */ +static inline AESCMACLPF3_Object *AESCMACLPF3_getObject(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = (AESCMACLPF3_Object *)handle->object; + DebugP_assert(object); + + return object; +} + +/* + * ======== AESCMACLPF3_hwiFxn ======== + */ +static void AESCMACLPF3_hwiFxn(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + /* + * Only the input channel A interrupt is enabled. + */ + uint32_t intStatus = AESGetMaskedInterruptStatus(); + + /* Disable DMA, clear interupts, and release power constraint */ + AESCommonLPF3_cleanupHwi(&object->common); + + if ((intStatus & (uint32_t)AES_MIS_CHADONE_M) != (uint32_t)0U) + { + UDMALPF3_clearInterrupt(AESCommonLPF3_DMA_CHA_BITMASK); + + AESCMACLPF3_getResult(object); + + /* Clear operation in-progress if one-step or finalize operation */ + if (object->operationType != AESCMAC_OP_TYPE_SEGMENTED_SIGN && + object->operationType != AESCMAC_OP_TYPE_SEGMENTED_VERIFY) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceLPF3_operationSemaphore); + } + else + { + /* Call the callback function provided by the application */ + object->callbackFxn((AESCMAC_Handle)handle, + object->common.returnStatus, + object->operation, + object->operationType); + } + } +} + +/* + * ======== AESCMAC_init ======== + */ +void AESCMAC_init(void) +{ + AESCommonLPF3_init(); +} + +/* + * ======== AESCMAC_construct ======== + */ +AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *params) +{ + DebugP_assert(config); + + int_fast16_t status; + AESCMAC_Handle handle = config; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &AESCMAC_defaultParams; + } + + DebugP_assert((params->returnBehavior != AES_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->operationalMode = params->operationalMode; + object->callbackFxn = params->callbackFxn; + object->threadSafe = true; + + status = AESCommonLPF3_construct(&object->common, (AES_ReturnBehavior)params->returnBehavior, params->timeout); + + if (status != AES_STATUS_SUCCESS) + { + handle = NULL; + } + + return handle; +} + +/* + * ======== AESCMACLPF3_readTag ======== + */ +void AESCMACLPF3_readTag(uint32_t tagOut[AES_TAG_LENGTH_BYTES / 4U]) +{ + /* Wait until the operation is done */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + + AESReadTag32(&tagOut[0]); +} + +/* + * ======== AESCMACLPF3_getResult ======== + */ +static void AESCMACLPF3_getResult(AESCMACLPF3_Object *object) +{ + AESCMAC_Operation *operation = object->operation; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + + if (object->common.returnStatus == AESCMAC_STATUS_SUCCESS) + { + /* If One-step or Finalize operation, process the final input block */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + AESWriteBUF32(&object->finalInputBlock[0]); + } + + AESCMACLPF3_readTag((uint32_t *)&object->intermediateTag[0]); + + /* If One-step or Finalize operation, verify or copy the MAC */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + if (object->operationType & AESCMAC_OP_FLAG_SIGN) + { + (void)memcpy((void *)operation->mac, (void *)&object->intermediateTag[0], operation->macLength); + } + else + { + /* Constant time comparison of output tag versus provided MAC */ + if (!CryptoUtils_buffersMatch(&object->intermediateTag[0], operation->mac, operation->macLength)) + { + object->common.returnStatus = AESCMAC_STATUS_MAC_INVALID; + } + } + } + } +} + +/* + * ======== AESCMACLPF3_startOperation ======== + */ +static int_fast16_t AESCMACLPF3_startOperation(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + AESCMAC_Operation *operation = object->operation; + + /* Input pointer cannot be NULL if input length is non-zero */ + DebugP_assert((operation->inputLength == 0U) || operation->input); + + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + + /* + * MAC pointer cannot be NULL if performing a one-step operation or + * finalizing a segmented operation + */ + DebugP_assert((opcode == AESCMAC_OP_CODE_SEGMENTED) || (operation->mac)); + + AESCMAC_OperationType operationType; + int_fast16_t status = AESCMAC_STATUS_ERROR; + size_t transactionLength = operation->inputLength; + + /* Load key */ + AESCommonLPF3_loadKey(&object->common.key); + + /* + * If One-step or Finalization operation, prepare the final + * input block and adjust the transaction length accordingly. + */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + AESCMACLPF3_prepareFinalInputBlock(object, &transactionLength); + } + + AESSetAUTOCFG(AESCMACLPF3_DEFAULT_AUTOCFG); + + /* + * Set IV to intermediate tag (initialized to zero at the start + * of a new operation). + */ + AESWriteIV32((uint32_t *)&object->intermediateTag[0]); + + if (transactionLength == 0U) + { + /* + * If transaction length is zero, only the final input block + * of data remains to be processed for CMAC. Call AESCMAC_getResult() + * to process the last block, obtain the result, and store status of + * the operation in object->returnStatus. + */ + AESCMACLPF3_getResult(object); + + /* + * Save the object's data to provide to callback in case it + * is overwritten during by the start of a new operation + * after the operationInProgress flag is cleared or access + * semaphore is posted. + */ + status = object->common.returnStatus; + operationType = object->operationType; + + AESCommonLPF3_clearOperationInProgress(&object->common); + + /* + * Handle clean up of the operation and post access semaphore to allow + * callback to chain operations. + */ + AESCommonLPF3_cleanup(&(object->common)); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, status, operation, operationType); + + /* Always return success in callback mode */ + status = AESCMAC_STATUS_SUCCESS; + } + } + else + { + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (transactionLength < AESCMACLPF3_DMA_SIZE_THRESHOLD)) + { + /* + * Process all data. Transaction length is updated in + * AESCMACLPF3_prepareFinalInputBlock() to be the truncated + * message length (which excludes the final block). + */ + AESCMACLPF3_processBlocks(operation->input, transactionLength); + } + else + { + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + AESCMACLPF3_HWAttrs const *hwAttrs = handle->hwAttrs; + AESCommonLPF3_setupHwi(AESCMACLPF3_hwiFxn, (uintptr_t)handle, hwAttrs->intPriority); + + /* Clear BUSHALT when using DMA */ + AESClearAUTOCFGBusHalt(); + + /* Setup DMA configuration and set power constraint */ + AESCommonLPF3_setupDMA(&object->common, AESCMACLPF3_DMA_CONFIG); + + AESCommonLPF3_configInputDMA(operation->input, transactionLength); + + /* Enable interrupt upon input DMA done */ + AESSetIMASK((uint32_t)AES_IMASK_CHADONE_M); + + /* Manually trigger the DMA to start the ECB operation */ + AESSetTrigger((uint32_t)AES_TRG_DMACHA); + } + + status = AESCMACLPF3_waitForResult(handle); + } + + return status; +} + +/* + * ======== AESCMACLPF3_processBlocks ======== + */ +void AESCMACLPF3_processBlocks(const uint8_t *input, size_t transactionLength) +{ +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + AESProcessAlignedBlocksCMAC((const uint32_t *)input, (uint32_t)AES_GET_NUM_BLOCKS(transactionLength)); +#else + size_t bytesProcessed = 0; + size_t transactionLengthDoubleBlocks = transactionLength & AES_DOUBLE_BLOCK_SIZE_MULTIPLE_MASK; + size_t transactionLengthSingleBlocks = transactionLength & (size_t)~AES_DOUBLE_BLOCK_SIZE_MULTIPLE_MASK; + + /* + * The code below has additional optimizations for word-aligned input data + * to support lower latency AES-CCM operations for BLE stack. + */ + if (IS_WORD_ALIGNED(input)) + { + AESProcessAlignedBlocksCMAC((const uint32_t *)input, (uint32_t)AES_GET_NUM_BLOCKS(transactionLength)); + } + else + { + while (bytesProcessed < transactionLengthDoubleBlocks) + { + AESWriteBUF(&input[bytesProcessed]); + bytesProcessed += AES_BLOCK_SIZE; + + AESWriteBUF(&input[bytesProcessed]); + bytesProcessed += AES_BLOCK_SIZE; + } + + /* Process any remaining single block */ + if (transactionLengthSingleBlocks != 0U) + { + AESWriteBUF(&input[bytesProcessed]); + } + } +#endif +} + +/* + * ======== AESCMACLPF3_xorBlock ======== + * XOR's two 16-byte blocks, storing the result in block1_dst. + */ +static inline void AESCMACLPF3_xorBlock(uint32_t *block1_dst, const uint32_t *block2) +{ + uint_fast8_t i; + + for (i = (uint_fast8_t)0U; i < (uint_fast8_t)AES_BLOCK_SIZE_WORDS; i++) + { + block1_dst[i] = block1_dst[i] ^ block2[i]; + } +} + +/* + * ======== AESCMACLPF3_prepareFinalInputBlock ======== + */ +static inline void AESCMACLPF3_prepareFinalInputBlock(AESCMACLPF3_Object *object, size_t *transactionLength) +{ + AESCMAC_Operation *operation = object->operation; + size_t finalInputLength = 0U; + size_t truncatedInputLength = 0U; + uint32_t subKey[AES_BLOCK_SIZE_WORDS]; + + /* Copy last partial or full block of input into local buffer */ + CryptoUtils_memset((void *)&object->finalInputBlock[0], + sizeof(object->finalInputBlock), + (uint8_t)0U, + sizeof(object->finalInputBlock)); + + if (operation->inputLength != 0U) + { + finalInputLength = AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength); + + if (finalInputLength == 0U) + { + finalInputLength = AES_BLOCK_SIZE; + } + + truncatedInputLength = operation->inputLength - finalInputLength; + + (void)memcpy(object->finalInputBlock, &operation->input[truncatedInputLength], finalInputLength); + } + + /* CMAC requires the final block to be XOR'd with a subkey */ + if (object->operationalMode == AESCMAC_OPMODE_CMAC) + { + /* Check if input message length is a positive block multiple */ + if ((operation->inputLength != 0U) && (finalInputLength == AES_BLOCK_SIZE)) + { + /* Generate subkey1 */ + AESCMACLPF3_generateSubKey(AESCMAC_SUBKEY1, subKey); + } + else + { + /* Generate subkey2 */ + AESCMACLPF3_generateSubKey(AESCMAC_SUBKEY2, subKey); + + /* Set padding byte if partial block */ + ((uint8_t *)&object->finalInputBlock[0])[finalInputLength] = AESCMAC_PADDING; + } + + /* XOR final block with subkey */ + AESCMACLPF3_xorBlock(object->finalInputBlock, subKey); + } + + *transactionLength = truncatedInputLength; +} + +/* + * ======== AESCMACLPF3_oneStepOperation ======== + */ +static int_fast16_t AESCMACLPF3_oneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + const CryptoKey *key, + AESCMAC_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(key); + /* No need to assert operationType since we control it within the driver */ + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + /* CBC-MAC is not permitted for zero length messages */ + if ((object->operationalMode == AESCMAC_OPMODE_CBCMAC) && (operation->inputLength == 0U)) + { + return AESCMAC_STATUS_ERROR; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input pointer */ + if (!IS_WORD_ALIGNED(operation->input)) + { + return AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + if (operation->macLength > sizeof(object->intermediateTag)) + { + return AESCMAC_STATUS_ERROR; + } + + /* + * Check that there is no operation already in progress for this driver + * instance. + */ + int_fast16_t status = AESCommonLPF3_setOperationInProgress(&object->common); + + if (status != AESCMAC_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESCMAC_STATUS_SUCCESS; + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* Zero the intermediate tag because it will be used as the IV */ + CryptoUtils_memset((void *)&object->intermediateTag[0], + sizeof(object->intermediateTag), + (uint8_t)0U, + sizeof(object->intermediateTag)); + + status = AESCMACLPF3_startOperation(handle); + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) + { + CryptoResourceLPF3_releaseLock(); + object->common.cryptoResourceLocked = false; + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + return status; +} + +/* + * ======== AESCMACLPF3_waitForResult ======== + */ +static inline int_fast16_t AESCMACLPF3_waitForResult(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (object->operation->inputLength < AESCMACLPF3_DMA_SIZE_THRESHOLD)) + { + AESCMACLPF3_getResult(object); + + /* + * Save the object's returnStatus before clearing operationInProgress or + * posting the access semaphore in case it is overwritten. + */ + status = object->common.returnStatus; + + /* Mark operation as no longer in progress if one-step or final operation */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + AESCommonLPF3_cleanup(&(object->common)); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, object->operation, object->operationType); + + /* Always return success in callback mode */ + status = AESCMAC_STATUS_SUCCESS; + } + } + else if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend((SemaphoreP_Handle)&CryptoResourceLPF3_operationSemaphore, + (uint32_t)SemaphoreP_WAIT_FOREVER); + + status = object->common.returnStatus; + } + else /* AES_RETURN_BEHAVIOR_CALLBACK */ + { + /* AESCMAC_STATUS_SUCCESS is always returned in callback mode */ + status = AESCMAC_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCMAC_oneStepSign ======== + */ +int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + return AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_SIGN); +} + +/* + * ======== AESCMAC_oneStepVerify ======== + */ +int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + return AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_VERIFY); +} + +/* + * ======== AESCMACLPF3_setupSegmentedOperation ======== + */ +static int_fast16_t AESCMACLPF3_setupSegmentedOperation(AESCMACLPF3_Object *object, const CryptoKey *key) +{ + DebugP_assert(key); + + /* + * Key material pointer and length are not asserted until adding or + * finalizing data. + */ + + int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* + * Initialize operation pointer to NULL in case AESCBC_cancelOperation + * is called after AESCMAC_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + + /* Zero the intermediate tag because it will be used as the IV */ + CryptoUtils_memset((void *)&object->intermediateTag[0], + sizeof(object->intermediateTag), + (uint8_t)0U, + sizeof(object->intermediateTag)); + } + + return status; +} + +/* + * ======== AESCMAC_setupSign ======== + */ +int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + int_fast16_t status = AESCMACLPF3_setupSegmentedOperation(object, key); + + if (status == AESCMAC_STATUS_SUCCESS) + { + object->operationType = AESCMAC_OP_TYPE_SEGMENTED_SIGN; + } + + return status; +} + +/* + * ======== AESCMAC_setupVerify ======== + */ +int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + int_fast16_t status = AESCMACLPF3_setupSegmentedOperation(object, key); + + if (status == AESCMAC_STATUS_SUCCESS) + { + object->operationType = AESCMAC_OP_TYPE_SEGMENTED_VERIFY; + } + + return status; +} + +/* + * ======== AESCMAC_addData ======== + */ +int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status; + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || + (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input pointer */ + if (!IS_WORD_ALIGNED(operation->input)) + { + return AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || (AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U)) + { + return AESCMAC_STATUS_ERROR; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = operation; + status = AESCMACLPF3_startOperation(handle); + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) + { + CryptoResourceLPF3_releaseLock(); + object->common.cryptoResourceLocked = false; + } + + return status; +} + +/* Perform ECB encryption on a block of zeros */ +static inline void AESCMACLPF3_encryptZeroBlockECB(uint32_t output[AES_BLOCK_SIZE_WORDS]) +{ + const uint32_t zeroBlock[AES_BLOCK_SIZE_WORDS] = {0}; + + AESSetAUTOCFG(AESEBCLPF3_SINGLE_BLOCK_AUTOCFG); + + /* Write block of zeros to input */ + AESWriteBUF32(&zeroBlock[0]); + + /* Wait until the operation is done */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + + /* Read output */ + AESReadTXT32(&output[0]); +} + +/* + * ======== AESCMACLPF3_generateSubKey ======== + * Generate AES CMAC subkey based on + * https://tools.ietf.org/html/rfc4493#section-2.3 + */ +static void AESCMACLPF3_generateSubKey(AESCMAC_SUBKEY_NUM subKeyNum, uint32_t subKey[AES_BLOCK_SIZE_WORDS]) +{ + /* Perform ECB encryption on the block of zeros using CPU R/W */ + AESCMACLPF3_encryptZeroBlockECB(&subKey[0]); + + /* + * At this point, subKey buffer only has the ciphertext + * generated by encrypting a block of 0's. + * Derive SubKey1. + */ + AESCMACLPF3_deriveSubKey((uint8_t *)&subKey[0]); + + if (subKeyNum == AESCMAC_SUBKEY2) + { + /* At this point, subKey buffer contains SubKey1. Derive SubKey2. */ + AESCMACLPF3_deriveSubKey((uint8_t *)&subKey[0]); + } +} + +/* + * ======== AESCMACLPF3_deriveSubKey ======== + */ +static void AESCMACLPF3_deriveSubKey(uint8_t *buffer) +{ + uint_fast8_t i; + uint8_t xorMask = (uint8_t)0U; + + if ((buffer[0] & AESCMAC_MSB_CHECK) != (uint8_t)0U) + { + xorMask = AESCMAC_CONST_RB; + } + + for (i = (uint_fast8_t)0U; i < (uint_fast8_t)AES_BLOCK_SIZE; i += (uint_fast8_t)1U) + { + if (i != (uint_fast8_t)0U) + { + buffer[i - (uint_fast8_t)1U] += (buffer[i] >> 7U); + } + + buffer[i] = buffer[i] << 1U; + } + + buffer[AES_BLOCK_SIZE - 1U] ^= xorMask; +} + +/* + * ======== AESCMAC_finalize ======== + */ +int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status; + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || + (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* + * Return the failure status of previous call. + * The callback will not be called. + */ + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input pointer */ + if (!IS_WORD_ALIGNED(operation->input)) + { + return AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + if (operation->macLength > sizeof(object->intermediateTag)) + { + return AESCMAC_STATUS_ERROR; + } + + if (operation->inputLength == 0U) + { + /* + * Finalizing an operation without providing data to process is not + * supported. Return an error. + */ + return AESCMAC_STATUS_ERROR; + } + + /* Try and obtain access to the crypto module */ + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + if (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_SIGN; + } + else + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_VERIFY; + } + + object->operation = operation; + status = AESCMACLPF3_startOperation(handle); + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) + { + CryptoResourceLPF3_releaseLock(); + object->common.cryptoResourceLocked = false; + } + + return status; +} + +/* + * ======== AESCMAC_close ======== + */ +void AESCMAC_close(AESCMAC_Handle handle) +{ + DebugP_assert(handle); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + AESCommonLPF3_close(&object->common); +} + +/* + * ======== AESCMAC_cancelOperation ======== + */ +int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) +{ + DebugP_assert(handle); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Return success if there is no active operation to cancel. + * Do not execute the callback as it would have been executed already + * when the operation completed. + */ + if (!object->common.operationInProgress) + { + HwiP_restore(interruptKey); + return AESCMAC_STATUS_SUCCESS; + } + + HwiP_restore(interruptKey); + + /* + * Cancel DMA for input channel A only, clear operation in-progress, + * and release crypto resource if locked. + */ + AESCommonLPF3_cancelOperation(&object->common, false); + + /* + * Operation pointer could be NULL if a segmented operation was setup + * but neither AESCMAC_addData or AESCMAC_finalize was called. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESCMAC_STATUS_CANCELED, object->operation, object->operationType); + } + + return AESCMAC_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h new file mode 100644 index 00000000..8dff31ac --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESCMACLPF3.h + * + * @brief AESCMAC (CMAC & CBC-MAC) driver implementation for the Low Power F3 family + * + * # Hardware Accelerator # + * The Low Power F3 family of devices has a dedicated AES hardware that can perform + * AES encryption operations with 128-bit keys. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aescmac_AESCMACLPF3__include +#define ti_drivers_aescmac_AESCMACLPF3__include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default AES CMAC & CBC-MAC auto config: + * ECB SRC as TXTXBUF + * Trigger point for auto ECB as WRBUF3 (encryption starts by writing BUF3) + * BUSHALT enabled + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCMACLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_AESSRC_TXTXBUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3 | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCMACLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_ECBSRC_TXTXBUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3 | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#else + #error "Unsupported DeviceFamily_Parent for AESCMACLPF3!" +#endif + +/* + * AES CMAC DMA config: + * - ADRCHA = BUF0 + * - TRGCHA = ECBSTART + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCMACLPF3_DMA_CONFIG ((uint32_t)AES_DMA_ADRCHA_BUF0 | (uint32_t)AES_DMA_TRGCHA_AESSTART) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCMACLPF3_DMA_CONFIG ((uint32_t)AES_DMA_ADRCHA_BUF0 | (uint32_t)AES_DMA_TRGCHA_ECBSTART) +#else + #error "Unsupported DeviceFamily_Parent for AESCMACLPF3!" +#endif + +#define AESCBCMACLPF3_DMA_CONFIG AESCMACLPF3_DMA_CONFIG + +/*! + * @brief AESCMACLPF3 Hardware Attributes + * + * AESCMACLPF3 hardware attributes should be included in the board file + * and pointed to by the AESCMAC_config struct. + */ +typedef AESCommonLPF3_HWAttrs AESCMACLPF3_HWAttrs; + +/*! + * @brief AESCMACLPF3 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* Common member first to allow struct to be cast to the common type */ + AESCommonLPF3_Object common; + volatile uint32_t intermediateTag[AES_TAG_LENGTH_BYTES / 4U]; + uint32_t finalInputBlock[AES_BLOCK_SIZE_WORDS]; + AESCMAC_CallbackFxn callbackFxn; + AESCMAC_Operation *operation; + AESCMAC_OperationType operationType; + AESCMAC_OperationalMode operationalMode; + bool threadSafe; +} AESCMACLPF3_Object; + +/*! @cond NODOC */ + +/*! + * @brief Processes the input blocks to generate the tag + * + * @param [in] input Pointer to the input data + * @param [in] transactionLength Length of the input to process. Should be a block-size multiple. + * + * @return none + */ +void AESCMACLPF3_processBlocks(const uint8_t *input, size_t transactionLength); + +/*! + * @brief Waits for the AES HW computation to complete and reads the tag output + * + * @param [out] tagOut Pointer to a block-sized array where the output tag should be stored. + * + * @return none + */ +void AESCMACLPF3_readTag(uint32_t tagOut[AES_TAG_LENGTH_BYTES / 4U]); + +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Acquire Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESCMAC handle + * @param [in] timeout Timeout (in ClockP ticks) to wait for the semaphore. + * - @ref SemaphoreP_WAIT_FOREVER + * - @ref SemaphoreP_NO_WAIT + * + * @return true - Succeeded acquiring the lock on crypto resource + * false - Failed to acquire the lock on crypto resource + */ +__STATIC_INLINE bool AESCMAC_acquireLock(AESCMAC_Handle handle, uint32_t timeout) +{ + return CryptoResourceLPF3_acquireLock(timeout); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Release Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESCMAC handle + */ +__STATIC_INLINE void AESCMAC_releaseLock(AESCMAC_Handle handle) +{ + CryptoResourceLPF3_releaseLock(); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Enable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESCMAC handle + */ +__STATIC_INLINE void AESCMAC_enableThreadSafety(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = handle->object; + object->threadSafe = true; +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Disable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @note The user is responsible for reenabling thread safety after being + * done with the need for this driver. + * + * @param [in] handle AESCMAC handle + */ +__STATIC_INLINE void AESCMAC_disableThreadSafety(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = handle->object; + object->threadSafe = false; +} +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescmac_AESCMACLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c new file mode 100644 index 00000000..ea78f5c6 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c @@ -0,0 +1,886 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(inc/hw_aes.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/** + * The threshold at which blocking and callback mode transfers will utilize DMA. + * For data lengths below this threshold, polling CPU R/W will be used instead + * of DMA. With task switching and interrupt overhead, it is inefficient to + * utilize DMA for shorter length operations. + * The threshold value must be a multiple of AES_BLOCK_SIZE. + */ +#define AESCTRLPF3_DMA_SIZE_THRESHOLD (1U * AES_BLOCK_SIZE) + +/* + * AES DMA configuration to use when data length is not a block multiple and + * the partial block of input/output remaining will be completed via CPU R/W. + * + * DMA channel A moves m[1:x] into TXTX when ECB completes + * + * ADRCHA = TXTX0 + * TRGCHA = ECBDONE + * + * DMA channel B moves ciphertext[1:x] to memory after channel A has written TXTX3. + * + * ADRCHB = TXT0 + * TRGCHB = WRTXT3 + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCTRLPF3_DMA_CONFIG \ + ((uint32_t)AES_DMA_ADRCHA_TXTX0 | (uint32_t)AES_DMA_TRGCHA_AESDONE | (uint32_t)AES_DMA_ADRCHB_TXT0 | \ + (uint32_t)AES_DMA_TRGCHB_WRTXT3) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCTRLPF3_DMA_CONFIG \ + ((uint32_t)AES_DMA_ADRCHA_TXTX0 | (uint32_t)AES_DMA_TRGCHA_ECBDONE | (uint32_t)AES_DMA_ADRCHB_TXT0 | \ + (uint32_t)AES_DMA_TRGCHB_WRTXT3) +#else + #error "Unsupported DeviceFamily_Parent for AESCTRLPF3!" +#endif + +/* + * AES DMA configuration to use when data length is exactly a block multiple. + * + * DMA channel A moves m[1:x] into TXTX when ECB completes + * + * ADRCHA = TXTX0 + * TRGCHA = ECBDONE + * DONEACT = GATE_TRGECB_ON_CHA (to avoid spurious last ECB using DMA) + * + * DMA channel B moves ciphertext[1:x] to memory after channel A has written TXTX3. + * + * ADRCHB = TXT0 + * TRGCHB = WRTXT3 + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCTRLPF3_GATE_CHA_DMA_CONFIG (AESCTRLPF3_DMA_CONFIG | (uint32_t)AES_DMA_DONEACT_GATE_TRGAES_ON_CHA) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCTRLPF3_GATE_CHA_DMA_CONFIG (AESCTRLPF3_DMA_CONFIG | (uint32_t)AES_DMA_DONEACT_GATE_TRGECB_ON_CHA) +#else + #error "Unsupported DeviceFamily_Parent for AESCTRLPF3!" +#endif + +/* Forward declarations */ +static void AESCTRLPF3_initCounter(AESCTRLPF3_Object *object, const uint8_t initialCounter[AES_BLOCK_SIZE]); +static int_fast16_t AESCTRLPF3_oneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType); +static int_fast16_t AESCTRLPF3_startOperation(AESCTR_Handle handle, bool isOneStepOrFinalOperation); +static int_fast16_t AESCTRLPF3_waitForResult(AESCTR_Handle handle); + +/* + * ======== AESCTRLPF3_getObject ======== + */ +static inline AESCTRLPF3_Object *AESCTRLPF3_getObject(AESCTR_Handle handle) +{ + AESCTRLPF3_Object *object = (AESCTRLPF3_Object *)handle->object; + DebugP_assert(object); + + return object; +} + +/* + * ======== AESCTRLPF3_hwiFxn ======== + */ +static void AESCTRLPF3_hwiFxn(uintptr_t arg0) +{ + AESCTR_Handle handle = (AESCTR_Handle)arg0; + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + /* + * Only the output channel B interrupt is enabled. + */ + uint32_t intStatus = AESGetMaskedInterruptStatus(); + + /* Disable DMA, clear interupts, and release power constraint */ + AESCommonLPF3_cleanupHwi(&object->common); + + if ((intStatus & (uint32_t)AES_MIS_CHBDONE_M) != (uint32_t)0U) + { + UDMALPF3_clearInterrupt(AESCommonLPF3_DMA_CHB_BITMASK); + + if ((object->inputLengthRemaining > 0U) && (object->inputLengthRemaining < AESCTRLPF3_DMA_SIZE_THRESHOLD)) + { + /* Use CPU R/W to complete the CTR operation */ + AESCTRLPF3_processData(&object->input[object->inputLength - object->inputLengthRemaining], + &object->output[object->inputLength - object->inputLengthRemaining], + object->inputLengthRemaining, + true); + + object->inputLengthRemaining = 0U; + } + + if (object->inputLengthRemaining > 0U) + { + /* + * If DMA Ping-Pong mode is supported in the future: + * - Set power contraint + * - Setup next DMA control struct to continue CTR operation + */ + } + + /* Save the last counter value from the AES engine */ + AESCTRLPF3_readCounter((uint32_t *)&object->counter[0]); + + /* Check if one-step or final operation */ + if ((object->operationType & AESCTR_OP_FLAG_SEGMENTED) == 0) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceLPF3_operationSemaphore); + } + else + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } + } +} + +/* + * ======== AESCTR_init ======== + */ +void AESCTR_init(void) +{ + AESCommonLPF3_init(); +} + +/* + * ======== AESCTR_construct ======== + */ +AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *params) +{ + DebugP_assert(config); + + int_fast16_t status; + AESCTR_Handle handle = config; + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &AESCTR_defaultParams; + } + + DebugP_assert((params->returnBehavior != AESCTR_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->callbackFxn = params->callbackFxn; + object->threadSafe = true; + + status = AESCommonLPF3_construct(&object->common, (AES_ReturnBehavior)params->returnBehavior, params->timeout); + + if (status != AES_STATUS_SUCCESS) + { + handle = NULL; + } + + return handle; +} + +/* + * ======== AESCTR_close ======== + */ +void AESCTR_close(AESCTR_Handle handle) +{ + DebugP_assert(handle); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + AESCommonLPF3_close(&object->common); +} + +/* + * ======== AESCTR_oneStepEncrypt ======== + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) +{ + return AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCTR_oneStepDecrypt ======== + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) +{ + return AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCTRLPF3_oneStepOperation ======== + */ +static int_fast16_t AESCTRLPF3_oneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->key); + /* No need to assert operationType since we control it within the driver */ + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + int_fast16_t status; + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCTR_STATUS_ERROR; + } + + /* Verify input length is non-zero */ + if (operation->inputLength == 0U) + { + return AESCTR_STATUS_ERROR; + } + + /* + * Check if there is no operation already in progress for this driver + * instance, and then mark the current operation to be in progress. + */ + status = AESCommonLPF3_setOperationInProgress(&object->common); + + if (status != AESCTR_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = (AESCTR_OperationUnion *)operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESCTR_STATUS_SUCCESS; + + /* Make internal copy of operational params */ + object->common.key = *(operation->key); + object->input = operation->input; + object->inputLength = operation->inputLength; + object->inputLengthRemaining = operation->inputLength; + object->output = operation->output; + + AESCTRLPF3_initCounter(object, &operation->initialCounter[0]); + + status = AESCTRLPF3_startOperation(handle, true); + + return status; +} + +/* + * ======== AESCTRLPF3_initCounter ======== + */ +static void AESCTRLPF3_initCounter(AESCTRLPF3_Object *object, const uint8_t initialCounter[AES_BLOCK_SIZE]) +{ + if (initialCounter != NULL) + { + (void)memcpy((void *)&object->counter[0], (void *)&initialCounter[0], sizeof(object->counter)); + } + else + { + (void)memset((void *)&object->counter[0], 0, sizeof(object->counter)); + } +} + +/* + * ======== AESCTRLPF3_startOperation ======== + */ +static int_fast16_t AESCTRLPF3_startOperation(AESCTR_Handle handle, bool isOneStepOrFinalOperation) +{ + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + int_fast16_t status = AESCTR_STATUS_SUCCESS; + size_t bytesProcessed; + + /* Set up the key and AES engine to begin an operation */ + AESCommonLPF3_setupOperation(&object->common.key, AESCTRLPF3_DEFAULT_AUTOCFG); + + /* + * Process all operations with data length less than the DMA size + * threshold as a polling mode operation. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (object->inputLength < AESCTRLPF3_DMA_SIZE_THRESHOLD)) + { + /* Write the counter value to the AES engine to trigger first encryption */ + AESCTRLPF3_writeCounter((uint32_t *)&object->counter[0]); + + /* Process all blocks with CPU R/W */ + AESCTRLPF3_processData(object->input, object->output, object->inputLength, isOneStepOrFinalOperation); + + object->inputLengthRemaining = 0U; + } + else + { + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + AESCTRLPF3_HWAttrs const *hwAttrs = handle->hwAttrs; + AESCommonLPF3_setupHwi(AESCTRLPF3_hwiFxn, (uintptr_t)handle, hwAttrs->intPriority); + + bytesProcessed = AESCTRLPF3_configDataDMA(&object->common, object->input, object->output, object->inputLength); + + object->inputLengthRemaining -= bytesProcessed; + + /* Write the counter value to the AES engine to trigger first encryption */ + AESCTRLPF3_writeCounter((uint32_t *)&object->counter[0]); + } + + status = AESCTRLPF3_waitForResult(handle); + + return status; +} + +/* + * ======== AESCTRLPF3_configDataDMA ======== + */ +size_t AESCTRLPF3_configDataDMA(AESCommonLPF3_Object *object, const uint8_t *input, uint8_t *output, size_t inputLength) +{ + size_t blockSizeDataLen = AES_BLOCK_SIZE_MULTIPLE_LENGTH(inputLength); + + /* Clear BUSHALT when using DMA */ + AESClearAUTOCFGBusHalt(); + + /* Setup DMA configuration and set power constraint */ + if (blockSizeDataLen == inputLength) + { + AESCommonLPF3_setupDMA(object, AESCTRLPF3_GATE_CHA_DMA_CONFIG); + } + else + { + AESCommonLPF3_setupDMA(object, AESCTRLPF3_DMA_CONFIG); + } + + /* + * Only full blocks of data can be processed with DMA because the trigger + * for DMA channel B (output) is based on channel A (input) writing the + * last word of the TXTX register + */ + AESCommonLPF3_configInputDMA(input, blockSizeDataLen); + AESCommonLPF3_configOutputDMA(output, blockSizeDataLen); + + /* Enable interrupt upon output DMA done */ + AESSetIMASK((uint32_t)AES_IMASK_CHBDONE_M); + + return blockSizeDataLen; +} + +/* + * ======== AESCTRLPF3_processData ======== + */ +void AESCTRLPF3_processData(const uint8_t *input, uint8_t *output, size_t inputLength, bool isOneStepOrFinalOperation) +{ + size_t bytesProcessed = 0; + size_t bytesRemaining = inputLength; + size_t blockSizeAlignedBytesRemaining = AES_BLOCK_SIZE_MULTIPLE_LENGTH(inputLength); + + if (blockSizeAlignedBytesRemaining > 0U) + { + bytesRemaining -= blockSizeAlignedBytesRemaining; + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) + if (!IS_WORD_ALIGNED(input) || !IS_WORD_ALIGNED(output)) + { + do + { + #ifdef AES_BUSHALT_DISABLED + /* Wait for encryption to complete */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + #endif + + if ((blockSizeAlignedBytesRemaining == AES_BLOCK_SIZE) && (bytesRemaining == 0U)) + { + /* + * Do not auto-trigger encrypt and increment of counter + * value for last block of data. + */ + AESSetAUTOCFG(AESCTRLPF3_LAST_BLOCK_AUTOCFG); + } + + /* XOR input data with encrypted counter block to form ciphertext */ + AESWriteTXTXOR(&input[bytesProcessed]); + + /* Read the output ciphertext and trigger the encryption of the next counter block */ + AESReadTXT(&output[bytesProcessed]); + + bytesProcessed += AES_BLOCK_SIZE; + blockSizeAlignedBytesRemaining -= AES_BLOCK_SIZE; + + } while (blockSizeAlignedBytesRemaining > 0U); + } + else +#endif + { + /* + * This optimization for word-aligned input & output is used to improve + * performance for AES-CCM to ensure BLE stack can meet timing + * requirements. + */ + + /* Safe to cast word-aligned input & output pointers */ + const uint32_t *input32 = (const uint32_t *)input; + uint32_t *output32 = (uint32_t *)output; + size_t inputBlocks = AES_GET_NUM_BLOCKS(blockSizeAlignedBytesRemaining); + + if (!isOneStepOrFinalOperation && (bytesRemaining == 0U)) + { + if (inputBlocks > 1U) + { + /* Process all data except the last block */ + AESProcessAlignedBlocksCTR(input32, output32, (uint32_t)inputBlocks - (uint32_t)1U); + + input32 = (const uint32_t *)&input[blockSizeAlignedBytesRemaining - AES_BLOCK_SIZE]; + output32 = (uint32_t *)&output[blockSizeAlignedBytesRemaining - AES_BLOCK_SIZE]; + } + + /* + * Do not auto-trigger encrypt and increment of counter + * value for last block of data. + */ + AESSetAUTOCFG(AESCTRLPF3_LAST_BLOCK_AUTOCFG); + + /* Process last block of data */ + AESProcessAlignedBlocksCTR(input32, output32, (uint32_t)1U); + } + else + { + /* + * Process all the data. This will trigger a spurious encryption + * when reading the final output which will be aborted during cleanup. + */ + AESProcessAlignedBlocksCTR(input32, output32, inputBlocks); + } + + bytesProcessed = blockSizeAlignedBytesRemaining; + } + } + + /* Process any remaining partial blocks of input data */ + if (bytesRemaining > 0U) + { +#ifdef AES_BUSHALT_DISABLED + /* Wait for encryption of counter block to complete */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} +#endif + size_t i; + + /* This code is faster than calling memcpy() twice */ + for (i = 0U; i < bytesRemaining; i++) + { + volatile uint8_t *regTXTX = (volatile uint8_t *)(AES_BASE + AES_O_TXTX0); + volatile uint8_t *regTXT = (volatile uint8_t *)(AES_BASE + AES_O_TXT0); + + /* Write TXTX register to XOR input with previously encrypted counter block */ + regTXTX[i] = input[bytesProcessed + i]; + + /* Read output from TXT register */ + output[bytesProcessed + i] = regTXT[i]; + } + } +} + +/* + * ======== AESCTRLPF3_waitForResult ======== + */ +static int_fast16_t AESCTRLPF3_waitForResult(AESCTR_Handle handle) +{ + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + int_fast16_t status; + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (object->inputLength < AESCTRLPF3_DMA_SIZE_THRESHOLD)) + { + /* Save the last counter value from the AES engine */ + AESCTRLPF3_readCounter((uint32_t *)&object->counter[0]); + + /* + * Save the object's returnStatus before clearing operationInProgress or + * posting the access semaphore in case it is overwritten. + */ + status = object->common.returnStatus; + + if ((object->operationType & AESCTR_OP_FLAG_SEGMENTED) == 0U) + { + /* One-step or finalization operation is complete */ + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, object->operation, object->operationType); + + /* Always return success in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + } + else if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Ignore return value since timeout is infinite */ + (void)SemaphoreP_pend((SemaphoreP_Handle)&CryptoResourceLPF3_operationSemaphore, + (uint32_t)SemaphoreP_WAIT_FOREVER); + + status = object->common.returnStatus; + } + else /* AESCTR_RETURN_BEHAVIOR_CALLBACK */ + { + /* Success is always returned in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCTR_addData ======== + */ +int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + int_fast16_t status; + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCTR_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || ((operation->inputLength & AES_NON_BLOCK_SIZE_MULTIPLE_MASK) != 0U)) + { + return AESCTR_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCTR_STATUS_ERROR; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = (AESCTR_OperationUnion *)operation; + + /* Make internal copy of operational params */ + object->input = operation->input; + object->inputLength = operation->inputLength; + object->inputLengthRemaining = operation->inputLength; + object->output = operation->output; + + status = AESCTRLPF3_startOperation(handle, false); + + return status; +} + +/* + * ======== AESCTR_finalize ======== + */ +int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + AESCTR_OperationType operationType; + int_fast16_t status; + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure of segmented operation */ + if (object->common.returnStatus != AESCTR_STATUS_SUCCESS) + { + /* Return the failure status of previous call. + * The callback will not be called. + */ + return object->common.returnStatus; + } + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && (operation->inputLength > 0U) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESCTR_STATUS_ERROR; + } + + /* + * Determine final operation type but do not save to object until + * we have obtained access to CRYPTO resource or there is no input + * to process. This allows app to retry finalization if the CRYPTO + * resource is unavailable. + */ + if (object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + operationType = AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE; + } + else + { + operationType = AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE; + } + + if (operation->inputLength > 0U) + { + /* Try and obtain access to the crypto module */ + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESCTR_OperationUnion *)operation; + + /* Make internal copy of operational params */ + object->input = operation->input; + object->inputLength = operation->inputLength; + object->inputLengthRemaining = operation->inputLength; + object->output = operation->output; + + status = AESCTRLPF3_startOperation(handle, true); + } + else /* Operation was finalized without additional data to process */ + { + /* + * Save the object's returnStatus in case it is + * overwritten during setup of a new segmented operation + * after the operationInProgress flag is cleared. + */ + status = object->common.returnStatus; + + AESCommonLPF3_clearOperationInProgress(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCTR_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCTRLPF3_setupSegmentedOperation ======== + */ +static int_fast16_t AESCTRLPF3_setupSegmentedOperation(AESCTRLPF3_Object *object, + const CryptoKey *key, + const uint8_t initialCounter[AES_BLOCK_SIZE]) +{ + DebugP_assert(key); + + /* + * Key material pointer and length are not checked until adding or + * finalizing data. + */ + + int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + + if (status == AESCTR_STATUS_SUCCESS) + { + AESCTRLPF3_initCounter(object, &initialCounter[0]); + + /* + * Initialize operation pointer to NULL in case AESCTR_cancelOperation + * is called after AESCTR_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + } + + return status; +} + +/* + * ======== AESCTR_setupEncrypt ======== + */ +int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + DebugP_assert(handle); + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + DebugP_assert(object); + + int_fast16_t status = AESCTRLPF3_setupSegmentedOperation(object, key, initialCounter); + + if (status == AESCTR_STATUS_SUCCESS) + { + object->operationType = AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED; + } + + return status; +} + +/* + * ======== AESCTR_setupDecrypt ======== + */ +int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + DebugP_assert(handle); + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + DebugP_assert(object); + + int_fast16_t status = AESCTRLPF3_setupSegmentedOperation(object, key, initialCounter); + + if (status == AESCTR_STATUS_SUCCESS) + { + object->operationType = AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED; + } + + return status; +} + +/* + * ======== AESCTR_cancelOperation ======== + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) +{ + DebugP_assert(handle); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Return success if there is no active operation to cancel. + * Do not execute the callback as it would have been executed already + * when the operation completed. + */ + if (!object->common.operationInProgress) + { + HwiP_restore(interruptKey); + return AESCTR_STATUS_SUCCESS; + } + + HwiP_restore(interruptKey); + + /* + * Cancel DMA for input and output channels, clear operation in-progress, + * and releases crypto resource if necessary. + */ + AESCommonLPF3_cancelOperation(&object->common, true); + + /* + * Operation pointer could be NULL if a segmented operation was setup + * but neither AESCCM_addData or AESCCM_finalize was called. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESCTR_STATUS_CANCELED, object->operation, object->operationType); + } + + return AESCTR_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h new file mode 100644 index 00000000..dde33a19 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESCTRLPF3.h + * + * @brief AESCTR driver implementation for the Low Power F3 family + * + * # Hardware Accelerator # + * The Low Power F3 family of devices has a dedicated AES hardware that can perform + * AES encryption operations with 128-bit keys. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesctr_AESCTRLPF3__include +#define ti_drivers_aesctr_AESCTRLPF3__include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default AES CTR auto config: + * ECB SRC as BUF + * Trigger points for auto ECB as RDTX3 and WRBUF3S + * (the first encryption starts by writing BUF3, the successive ones by reading TXT3) + * Counter size as 128-bits + * Counter endianness as Big Endian + * BUSHALT enabled + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #define AES_AUTOCFG_CTRENDN_BIGENDIAN AES_AUTOCFG_CTRENDIAN_BIGENDIAN +#endif + +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCTRLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_TRGAES_RDTXT3 | (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | \ + (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCTRLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_TRGECB_RDTXT3 | (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | \ + (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#else + #error "Unsupported DeviceFamily_Parent for AESCTRLPF3!" +#endif + +/* + * AES CTR auto config for handling processing of the last + * block of input to avoid starting encryption of the next counter block and + * incrementing the counter value when the output is read from TXT3. + * + * ECB SRC as BUF + * Trigger for auto ECB as WRBUF3S + * (the first encryption starts by writing BUF3) + * Counter size as 128-bits + * Counter endianness as Big Endian + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESCTRLPF3_LAST_BLOCK_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | \ + (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESCTRLPF3_LAST_BLOCK_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | \ + (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#else + #error "Unsupported DeviceFamily_Parent for AESCTRLPF3!" +#endif + +/*! + * @brief AESCTRLPF3 Hardware Attributes + * + * AESCTRLPF3 hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef AESCommonLPF3_HWAttrs AESCTRLPF3_HWAttrs; + +/*! + * @brief AESCTRLPF3 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* Common member first to allow struct to be cast to the common type */ + AESCommonLPF3_Object common; + volatile uint32_t counter[AES_BLOCK_SIZE_WORDS]; + const uint8_t *input; + uint8_t *output; + size_t inputLength; + size_t inputLengthRemaining; + AESCTR_OperationUnion *operation; + AESCTR_CallbackFxn callbackFxn; + AESCTR_OperationType operationType; + bool threadSafe; +} AESCTRLPF3_Object; + +/*! @cond NODOC */ + +/*! + * @brief Processes the given input data using CPU R/W. + * + * @param [in] input Pointer to the input data + * @param [out] output Pointer to the output data + * @param [in] inputLength Length of input data + * @param [in] isOneStepOrFinalOperation Set to True for one-step or finalization + * operation, False otherwise. + * + */ +void AESCTRLPF3_processData(const uint8_t *input, uint8_t *output, size_t inputLength, bool isOneStepOrFinalOperation); + +/*! + * @brief Configures the DMA to process the given input data. + * #AESCTRLPF3_writeCounter must be called to start the operation + * + * @param [in] object Pointer to an AESCommonLPF3_Object + * @param [in] input Pointer to the input data + * @param [out] output Pointer to the output data + * @param [in] inputLength Length of input data + * + * @return The number of bytes processed - a multiple of AES_BLOCK_SIZE. + */ +size_t AESCTRLPF3_configDataDMA(AESCommonLPF3_Object *object, + const uint8_t *input, + uint8_t *output, + size_t inputLength); + +/*! + * @brief Reads the latest counter value from the AES HW. + * + * @note AES HW must be idle (i.e. no active encryption) when reading the counter value. + * + * @param [out] counterOut Pointer to a block-sized array where the output counter should be stored. + */ +__STATIC_INLINE void AESCTRLPF3_readCounter(uint32_t counterOut[AES_BLOCK_SIZE_WORDS]) +{ + /* Read the latest counter value from the AES engine */ + AESReadBUF32(&counterOut[0]); +} + +/*! + * @brief Writes the given counter into the AES HW + * + * @param [in] counterIn Pointer to a block-sized array of the input counter. + */ +__STATIC_INLINE void AESCTRLPF3_writeCounter(uint32_t counterIn[AES_BLOCK_SIZE_WORDS]) +{ + AESWriteBUF32(&counterIn[0]); +} + +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Acquire Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle An AESCTR handle + * @param [in] timeout Timeout (in ClockP ticks) to wait for the semaphore. + * - @ref SemaphoreP_WAIT_FOREVER + * - @ref SemaphoreP_NO_WAIT + * + * @return true - Succeeded acquiring the lock on crypto resource + * false - Failed to acquire the lock on crypto resource + */ +__STATIC_INLINE bool AESCTR_acquireLock(AESCTR_Handle handle, uint32_t timeout) +{ + return CryptoResourceLPF3_acquireLock(timeout); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Release Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle An AESCTR handle + */ +__STATIC_INLINE void AESCTR_releaseLock(AESCTR_Handle handle) +{ + CryptoResourceLPF3_releaseLock(); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Enable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle An AESCTR handle + */ +__STATIC_INLINE void AESCTR_enableThreadSafety(AESCTR_Handle handle) +{ + AESCTRLPF3_Object *object = handle->object; + object->threadSafe = true; +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Disable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @note The user is responsible for reenabling thread safety after being + * done with the need for this driver. + * + * @param [in] handle An AESCTR handle + */ +__STATIC_INLINE void AESCTR_disableThreadSafety(AESCTR_Handle handle) +{ + AESCTRLPF3_Object *object = handle->object; + object->threadSafe = false; +} +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctr_AESCTRLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c b/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c new file mode 100644 index 00000000..ea9b2626 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#else + #include +#endif + +/* Forward declarations */ +static void AESCTRDRBGXX_addBigendCounter(uint8_t *counter, uint32_t increment); +static int_fast16_t AESCTRDRBGXX_updateState(AESCTRDRBG_Handle handle, + const void *additionalData, + size_t additionalDataLength); +static void AESCTRDRBG_uninstantiate(AESCTRDRBG_Handle handle); + +/* Static globals */ +static bool isInitialized = false; + +#define CEIL(x, y) (1 + (((x)-1) / (y))) + +/* + * ======== AESCTRDRBG_init ======== + */ +void AESCTRDRBG_init(void) +{ + AESCTR_init(); + + isInitialized = true; +} + +/* + * ======== AESCTRDRBGXX_updateState ======== + */ +static int_fast16_t AESCTRDRBGXX_updateState(AESCTRDRBG_Handle handle, + const void *additionalData, + size_t additionalDataLength) +{ + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + /* + * Buffer must be word aligned as some AESCTR implementations require + * word aligned I/O. + */ + uint32_t buf32[(AESCTRDRBG_MAX_SEED_LENGTH + 3) / 4] = {0}; + + object = handle->object; + + /* + * We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + * We do not need to worry about the counter being 1 over afterwards + * as we will replace the global counter with part of the + * encrypted result. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, 1); + + /* + * Wrap the memcpy below in a zero-length check. Do not remove it! + * The explicit check is necessary for klocwork to stop emitting a critical + * warning. Theoretically, memcpy with a length argument of 0 should do + * nothing. However klocwork emits a warning that there is an out + * of bounds array access (underflow) on buf32 if this check is not in place. + */ + if (additionalDataLength > 0) + { + /* + * Copy over any additional data and operate on buf32 in place. This way + * we can have the case where additionalDataLength < seedLength. This is + * useful in AESCTRDRBG_getBytes() to avoid allocating a spare empty + * buffer. + */ + memcpy(buf32, additionalData, additionalDataLength); + } + + operation.key = &object->key; + operation.input = (uint8_t *)buf32; + operation.output = (uint8_t *)buf32; + operation.initialCounter = object->counter; + operation.inputLength = object->key.u.plaintext.keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + + if (AESCTR_oneStepEncrypt(object->ctrHandle, &operation) != AESCTR_STATUS_SUCCESS) + { + return AESCTRDRBG_STATUS_ERROR; + } + + /* Copy the left most keyLength bytes of the computed result */ + memcpy(object->keyingMaterial, buf32, object->key.u.plaintext.keyLength); + + /* + * Copy new counter value as the right most 16 bytes of the computed result. + * The key length is always a word multiple number of bytes so we can divide + * by word size to determine the buf32 index. + */ + memcpy(object->counter, + &buf32[object->key.u.plaintext.keyLength / sizeof(uint32_t)], + AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + /* Wipe the stack buffer */ + memset(buf32, 0, object->seedLength); + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== AESCTRDRBGXX_addBigendCounter ======== + */ +static void AESCTRDRBGXX_addBigendCounter(uint8_t *counter, uint32_t increment) +{ + uint64_t *counter64 = (uint64_t *)counter; + uint64_t prior; + + /* Turn it into a little-endian counter */ + CryptoUtils_reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + prior = counter64[0]; + + /* Increment as a 64-bit number */ + counter64[0] += increment; + + /* Check if we wrapped and need to increment the upper 64 bits */ + if (counter64[0] < prior) + { + counter64[1]++; + } + + /* Turn it back into a big-endian integer */ + CryptoUtils_reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); +} + +/* + * ======== AESCTRDRBG_uninstantiate ======== + * + * Per the NIST Recommendation SP 800-90A Rev. 1 for DRBG, uninstantiate is the operation + * of clearing the internal state {keyingMaterial, counter, reseedCounter} by writing + * all 0's. Once uninstantiated, the DRBG instance shall not be used until it's + * instantiated again with a fresh seed. + * + * This implementation also sets the isInstantiated flag to false. This function + * should be called if any of the AESCTR operations fail so that the DRBG instance + * will never be usable when its internal state is potentially corrupt. + */ +static void AESCTRDRBG_uninstantiate(AESCTRDRBG_Handle handle) +{ + AESCTRDRBGXX_Object *object; + + object = handle->object; + + object->isInstantiated = false; + memset(object->keyingMaterial, 0, object->key.u.plaintext.keyLength); + memset(object->counter, 0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + object->reseedCounter = 0; +} + +/* + * ======== AESCTRDRBG_construct ======== + */ +AESCTRDRBG_Handle AESCTRDRBG_construct(AESCTRDRBG_Config *config, const AESCTRDRBG_Params *params) +{ + AESCTRDRBG_Handle handle = (AESCTRDRBG_Handle)config; + AESCTRDRBGXX_Object *object; + const AESCTRDRBGXX_HWAttrs *hwAttrs; + AESCTR_Params ctrParams; + uintptr_t key; + int_fast16_t status; + + /* There are no valid default params for this driver */ + if (params == NULL) + { + return NULL; + } + + DebugP_assert(handle); + object = handle->object; + hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* + * personalizationDataLength must be within + * [0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES + KeyLength] bytes. + */ + if (params->personalizationDataLength > params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) + { + return NULL; + } + + /* Open the driver's AESCTR instance */ + AESCTR_Params_init(&ctrParams); +#if (TFM_ENABLED == 0) + ctrParams.returnBehavior = (AESCTR_ReturnBehavior)(params->returnBehavior); +#else + /* + * For the secure-only implementation, AESCTRDRBG supports blocking or + * polling return behavior. However, when TF-M is enabled, polling return + * behavior must be forced since drivers cannot block inside the TF-M. + */ + ctrParams.returnBehavior = AESCTR_RETURN_BEHAVIOR_POLLING; +#endif + + /* Zero out the AESCTR object to ensure AESCTR_construct() will not fail */ + memset(&object->aesctrObject, 0, sizeof(object->aesctrObject)); + object->ctrConfig.object = &object->aesctrObject; + object->ctrConfig.hwAttrs = &hwAttrs->aesctrHWAttrs; + + object->ctrHandle = AESCTR_construct(&object->ctrConfig, &ctrParams); + + if (object->ctrHandle == NULL) + { + object->isOpen = false; + + return NULL; + } + + /* Initialize CryptoKey for later use */ + CryptoKeyPlaintext_initKey(&object->key, object->keyingMaterial, params->keyLength); + + /* Zero-out counter and keyingMaterial */ + memset(object->counter, 0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + memset(object->keyingMaterial, 0, params->keyLength); + + /* Store constants for later */ + object->seedLength = params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + object->reseedInterval = params->reseedInterval; + + /* Ideally this should be set only after instantiation is complete. However + * since this implementation uses the reseed function, this flag is set here + * to ensure it doesn't fail with AESCTRDRBG_STATUS_UNINSTANTIATED. + * Note that if reseed fails due to other reasons, the following call to + * uninstantiate will clear this flag. + */ + object->isInstantiated = true; + + /* Reseed the instance to generate the initial (counter, keyingMaterial) pair */ + status = AESCTRDRBG_reseed(handle, params->seed, params->personalizationData, params->personalizationDataLength); + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTR_close(object->ctrHandle); + AESCTRDRBG_uninstantiate(handle); + object->isOpen = false; + + return NULL; + } + + return handle; +} + +/* + * ======== AESCTRDRBG_close ======== + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle) +{ + AESCTRDRBGXX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + AESCTR_close(object->ctrHandle); + + AESCTRDRBG_uninstantiate(handle); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== AESCTRDRBG_getBytes ======== + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes) +{ + return AESCTRDRBG_generateKey(handle, randomBytes); +} + +/* + * ======== AESCTRDRBG_generateKey ======== + */ +int_fast16_t AESCTRDRBG_generateKey(AESCTRDRBG_Handle handle, CryptoKey *randomKey) +{ + int_fast16_t status = AESCTRDRBG_STATUS_ERROR; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + uint8_t KeyStore_keyingMaterial[AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE]; + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyAttributes *attributesPtr; + + attributesPtr = &attributes; + +#endif /* ENABLE_KEY_STORAGE */ + + if (randomKey != NULL) + { + if (randomKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + status = AESCTRDRBG_getRandomBytes(handle, + randomKey->u.plaintext.keyMaterial, + randomKey->u.plaintext.keyLength); + if (status == AESCTRDRBG_STATUS_SUCCESS) + { + randomKey->encoding = CryptoKey_PLAINTEXT; + } + } +#if (ENABLE_KEY_STORAGE == 1) + else if (randomKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + if ((randomKey->u.keyStore.keyLength != 0) && + (randomKey->u.keyStore.keyLength <= AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE)) + { + /* Copy keyAttributes from CryptoKey structure */ + #if (TFM_ENABLED == 0) + attributesPtr = (KeyStore_PSA_KeyAttributes *)randomKey->u.keyStore.keyAttributes; + #else + keyStoreStatus = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *) + randomKey->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #endif + status = AESCTRDRBG_getRandomBytes(handle, KeyStore_keyingMaterial, randomKey->u.keyStore.keyLength); + + if (status == AESCTRDRBG_STATUS_SUCCESS) + { + keyStoreStatus = KeyStore_PSA_importKey(attributesPtr, + KeyStore_keyingMaterial, + randomKey->u.keyStore.keyLength, + &attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id)); + if (keyStoreStatus == KEYSTORE_PSA_STATUS_SUCCESS) + { + if (attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) == + KEYSTORE_PSA_KEY_LIFETIME_VOLATILE) + { + /* Set the keyID of volatile keys provided by KeyStore driver in the cryptokey structure */ + KeyStore_PSA_initKey(randomKey, + attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id), + randomKey->u.keyStore.keyLength, + NULL); + } + else + { + /* Only update the KeyStore encoding for persistent keys */ + randomKey->encoding = CryptoKey_KEYSTORE; + } + status = AESCTRDRBG_STATUS_SUCCESS; + } + else + { + status = AESCTRDRBG_STATUS_KEYSTORE_ERROR; + } + } + } + } +#endif /* ENABLE_KEY_STORAGE */ + } + + return status; +} + +/* + * ======== AESCTRDRBG_getRandomBytes ======== + */ +int_fast16_t AESCTRDRBG_getRandomBytes(AESCTRDRBG_Handle handle, void *randomBytes, size_t randomBytesSize) +{ + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + int_fast16_t status; + bool lockAcquired; + uint32_t lockAcquireTimeout; + + object = handle->object; + + if (object->isInstantiated == false) + { + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + if (object->reseedCounter >= object->reseedInterval) + { + return AESCTRDRBG_STATUS_RESEED_REQUIRED; + } + + if (SwiP_inISR() || HwiP_inISR()) + { + lockAcquireTimeout = SemaphoreP_NO_WAIT; + } + else + { + lockAcquireTimeout = SemaphoreP_WAIT_FOREVER; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle, lockAcquireTimeout); + if (!lockAcquired) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); + + /* Set the keying material of the CryptoKey to 0. + * If we use AESCTR to encrypt a buffer full of zeros, + * the resultant output will be the bitstream of the + * encrypted counters. That is what is used as + * random bits by AESCTRDRBG. + * Zeroing out the keying material and performing + * the AESCTR encryption in place saves us from + * allocating a buffer of the right length full + * of zeros or repeatedly encrypting a 16-byte + * buffer full of zeros. + */ + memset(randomBytes, 0, randomBytesSize); + + /* We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, 1); + + operation.key = &object->key; + operation.input = randomBytes; + operation.output = randomBytes; + operation.initialCounter = object->counter; + operation.inputLength = randomBytesSize; + + status = AESCTR_oneStepEncrypt(object->ctrHandle, &operation); + + if (status != AESCTR_STATUS_SUCCESS) + { + AESCTR_releaseLock(object->ctrHandle); + + if (status == AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED) + { + status = AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } + else + { + AESCTRDRBG_uninstantiate(handle); + status = AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + return status; + } + + /* Add the number of counter blocks we produced to the + * internal counter. We already incremented by one above + * so we increment by one less here. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, CEIL(randomBytesSize, AESCTRDRBG_AES_BLOCK_SIZE_BYTES) - 1); + + status = AESCTRDRBGXX_updateState(handle, NULL, 0); + + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTRDRBG_uninstantiate(handle); + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + object->reseedCounter += 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== AESCTRDRBG_reseed ======== + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength) +{ + AESCTRDRBGXX_Object *object; + int_fast16_t status; + uint8_t tmp[AESCTRDRBG_MAX_SEED_LENGTH]; + uint32_t i; + bool lockAcquired; + uint32_t lockAcquireTimeout; + + object = handle->object; + + if (object->isInstantiated == false) + { + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + if (additionalDataLength > object->seedLength) + { + return AESCTRDRBG_STATUS_ERROR; + } + + if (SwiP_inISR() || HwiP_inISR()) + { + lockAcquireTimeout = SemaphoreP_NO_WAIT; + } + else + { + lockAcquireTimeout = SemaphoreP_WAIT_FOREVER; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle, lockAcquireTimeout); + if (!lockAcquired) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); + + /* Set temporary buffer as additionalData padded with zeros */ + memset(tmp, 0, object->seedLength); + memcpy(tmp, additionalData, additionalDataLength); + + /* XOR-in the seed. It should always be a multiple of 32 bits */ + for (i = 0; i < object->seedLength / sizeof(uint32_t); i++) + { + ((uint32_t *)tmp)[i] ^= ((uint32_t *)seed)[i]; + } + + /* Use the combined seed to generate a new (counter, keyingMaterial) pair */ + status = AESCTRDRBGXX_updateState(handle, tmp, object->seedLength); + + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTRDRBG_uninstantiate(handle); + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + object->reseedCounter = 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h b/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h new file mode 100644 index 00000000..4ccffd3b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBGXX.h + * + * @brief Generic AESCTRDRBG implementation based on the AESCTR driver + * + * This file should only be included in the board file to fill the AESCTR_config + * struct. + * + * # Use of AESCTR # + * This implementation uses the AESCTR driver to generate the random bitstream + * required to mutate the internal AESCTRDRBG state and provide random output + * bits. The driver will construct a dynamic instance of the AESCTR driver. + * Mutual exclusion and hardware access are all handled by the AESCTR driver + * instance. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to them + * are checked (such as whether a driver is already open). Higher input + * parameter validation coverage is achieved by turning on assertions when + * compiling the driver. + */ + +#ifndef ti_drivers_aesctrdrbg_AESCTRDRBGXX__include +#define ti_drivers_aesctrdrbg_AESCTRDRBGXX__include + +#include +#include + +#include +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#else + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @brief Define that specifies the maximum AES key length required + * + * This define defines what the largest AES key length used in an application is. + * Since this implementation needs to support all AES key lengths by default, + * temporary buffers and the internal driver state are sized to accommodate AES-256. + * If only AES-128 is used in an application, the driver can be recompiled + * with a different #AESCTRDRBG_MAX_KEY_LENGTH to save RAM in the #AESCTRDRBGXX_Object + * and reducing stack size requirements. + */ +#ifndef AESCTRDRBG_MAX_KEY_LENGTH + #define AESCTRDRBG_MAX_KEY_LENGTH AESCTRDRBG_AES_KEY_LENGTH_256 +#endif + +/*! @brief Define that specifies the maximum seed length used by the driver */ +#define AESCTRDRBG_MAX_SEED_LENGTH (AESCTRDRBG_MAX_KEY_LENGTH + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) + +#if (ENABLE_KEY_STORAGE == 1) || (TFM_ENABLED == 1) + /*! @brief Maximum output key size in bytes when using KeyStore */ + #define AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE 64 +#endif + +/*! + * @brief AESCTRDRBGXX Hardware Attributes + * + * AESCTR26XX hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef struct +{ + /* + * Priority in HWAttrs will be passed to AESCTR instance upon construct + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + AESCTRLPF3_HWAttrs aesctrHWAttrs; +#else + AESCTRCC26XX_HWAttrs aesctrHWAttrs; +#endif +} AESCTRDRBGXX_HWAttrs; + +/*! + * @brief AESCTRDRBGXX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint8_t keyingMaterial[AESCTRDRBG_AES_KEY_LENGTH_256]; + uint8_t counter[AESCTRDRBG_AES_BLOCK_SIZE_BYTES]; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + AESCTRLPF3_Object aesctrObject; +#else + AESCTRCC26XX_Object aesctrObject; +#endif + AESCTR_Config ctrConfig; + AESCTR_Handle ctrHandle; + CryptoKey key; + size_t seedLength; + uint32_t reseedCounter; + uint32_t reseedInterval; + int_fast16_t returnStatus; + bool isOpen; + bool isInstantiated; +} AESCTRDRBGXX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctrdrbg_AESCTRDRBGXX__include */ diff --git a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c new file mode 100644 index 00000000..d17fbff2 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c @@ -0,0 +1,732 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(inc/hw_aes.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* + * Default AES ECB auto config: + * ECB SRC as BUF + * Trigger points for auto ECB as RDTX3 and WRBUF3S + * (the first encryption starts by writing BUF3, the successive ones by reading TXT3) + * BUSHALT enabled + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESECBLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_TRGAES_RDTXT3 | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESECBLPF3_DEFAULT_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | \ + (uint32_t)AES_AUTOCFG_TRGECB_RDTXT3 | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#else + #error "Unsupported DeviceFamily_Parent for AESECBLPF3!" +#endif + +/* + * AES ECB DMA config: + * - ADRCHA = BUF0 + * - TRGCHA = ECBSTART + * - ADRCHB = TXT0 + * - TRGCHB = ECBDONE + * - DONEACT = GATE_TRGECB_ON_CHA_DEL (to avoid spurious last ECB using DMA + * if data length > 1 block) + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESECBLPF3_DMA_CONFIG \ + ((uint32_t)AES_DMA_ADRCHA_BUF0 | (uint32_t)AES_DMA_TRGCHA_AESSTART | \ + (uint32_t)AES_DMA_DONEACT_GATE_TRGAES_ON_CHA_DEL | (uint32_t)AES_DMA_ADRCHB_TXT0 | \ + (uint32_t)AES_DMA_TRGCHB_AESDONE) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESECBLPF3_DMA_CONFIG \ + ((uint32_t)AES_DMA_ADRCHA_BUF0 | (uint32_t)AES_DMA_TRGCHA_ECBSTART | \ + (uint32_t)AES_DMA_DONEACT_GATE_TRGECB_ON_CHA_DEL | (uint32_t)AES_DMA_ADRCHB_TXT0 | \ + (uint32_t)AES_DMA_TRGCHB_ECBDONE) +#else + #error "Unsupported DeviceFamily_Parent for AESECBLPF3!" +#endif + +/* Forward declarations */ +static int_fast16_t AESECBLPF3_checkOperation(const AESECBLPF3_Object *object, const AESECB_Operation *operation); +static inline void AESECBLPF3_processDataCPU(const uint8_t *input, uint8_t *output, size_t inputLength); +static inline void AESECBLPF3_processDataDMA(AESCommonLPF3_Object *object, + const uint8_t *input, + uint8_t *output, + size_t inputLength); +static inline int_fast16_t AESECBLPF3_oneStepOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType); +static int_fast16_t AESECBLPF3_startOperation(AESECB_Handle handle, AESECB_Operation *operation); +static inline int_fast16_t AESECBLPF3_waitForResult(AESECB_Handle handle); + +/* + * ======== AESEBCLPF3_getObject ======== + */ +static inline AESECBLPF3_Object *AESEBCLPF3_getObject(AESECB_Handle handle) +{ + AESECBLPF3_Object *object = (AESECBLPF3_Object *)handle->object; + DebugP_assert(object); + + return object; +} + +/* + * ======== AESECBLPF3_hwiFxn ======== + */ +static void AESECBLPF3_hwiFxn(uintptr_t arg0) +{ + AESECB_Handle handle = (AESECB_Handle)arg0; + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* + * Only the output channel B interrupt is enabled. + */ + uint32_t intStatus = AESGetMaskedInterruptStatus(); + + /* Disable DMA, clear interupts, and release power constraint */ + AESCommonLPF3_cleanupHwi(&object->common); + + if ((intStatus & (uint32_t)AES_MIS_CHBDONE_M) != (uint32_t)0U) + { + UDMALPF3_clearInterrupt(AESCommonLPF3_DMA_CHB_BITMASK); + + if ((object->operationType == AESECB_OPERATION_TYPE_ENCRYPT) || + (object->operationType == AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED)) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + /* Cleanup and release crypto resource lock */ + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceLPF3_operationSemaphore); + } + else + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } + } +} + +/* + * ======== AESECB_init ======== + */ +void AESECB_init(void) +{ + AESCommonLPF3_init(); +} + +/* + * ======== AESECB_construct ======== + */ +AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *params) +{ + DebugP_assert(config); + + int_fast16_t status; + AESECB_Handle handle = config; + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &AESECB_defaultParams; + } + + DebugP_assert((params->returnBehavior != AESECB_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->callbackFxn = params->callbackFxn; + object->threadSafe = true; + + status = AESCommonLPF3_construct(&object->common, (AES_ReturnBehavior)params->returnBehavior, params->timeout); + + if (status != AES_STATUS_SUCCESS) + { + return NULL; + } + + return handle; +} + +/* + * ======== AESECB_close ======== + */ +void AESECB_close(AESECB_Handle handle) +{ + DebugP_assert(handle); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + AESCommonLPF3_close(&object->common); +} + +/* + * ======== AESECB_oneStepEncrypt ======== + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + return AESECBLPF3_oneStepOperation(handle, operation, AESECB_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESECB_oneStepDecrypt ======== + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + return AESECB_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESECBLPF3_checkOperation ======== + */ +static int_fast16_t AESECBLPF3_checkOperation(const AESECBLPF3_Object *object, const AESECB_Operation *operation) +{ +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Verify input length is a non-zero multiple of the AES block size */ + if ((operation->inputLength == 0UL) || (AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0UL)) + { + return AESECB_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESECB_STATUS_ERROR; + } + + return AESECB_STATUS_SUCCESS; +} + +/* + * ======== AESECBLPF3_oneStepOperation ======== + */ +static inline int_fast16_t AESECBLPF3_oneStepOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + status = AESECBLPF3_checkOperation(object, operation); + + if (status != AESECB_STATUS_SUCCESS) + { + return status; + } + + /* + * Check that there are no operations already in progress. + * If not, mark the current operation to be in progress + */ + status = AESCommonLPF3_setOperationInProgress(&object->common); + + if (status != AESECB_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = operation; + object->operationType = operationType; + + object->common.key = *(operation->key); + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESECB_STATUS_SUCCESS; + + return AESECBLPF3_startOperation(handle, operation); +} + +/* + * ======== AESECBLPF3_startOperation ======== + */ +static int_fast16_t AESECBLPF3_startOperation(AESECB_Handle handle, AESECB_Operation *operation) +{ + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + /* Set up the key and AES engine to begin an operation */ + if (operation->inputLength == AES_BLOCK_SIZE) + { + AESCommonLPF3_setupOperation(&object->common.key, AESEBCLPF3_SINGLE_BLOCK_AUTOCFG); + } + else + { + AESCommonLPF3_setupOperation(&object->common.key, AESECBLPF3_DEFAULT_AUTOCFG); + } + + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + (operation->inputLength >= AESECBLPF3_DMA_SIZE_THRESHOLD)) + { + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + AESECBLPF3_HWAttrs const *hwAttrs = handle->hwAttrs; + AESCommonLPF3_setupHwi(AESECBLPF3_hwiFxn, (uintptr_t)handle, hwAttrs->intPriority); + } + + AESECBLPF3_processData(&object->common, operation->input, operation->output, operation->inputLength); + + status = AESECBLPF3_waitForResult(handle); + + return status; +} + +/* + * ======== AESECBLPF3_processData ======== + */ +void AESECBLPF3_processData(AESCommonLPF3_Object *object, const uint8_t *input, uint8_t *output, size_t inputLength) +{ + /* + * Process all operations with data length less than the DMA size + * threshold as a polling mode operation. + */ + if ((object->returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || (inputLength < AESECBLPF3_DMA_SIZE_THRESHOLD)) + { + /* Process all blocks with CPU R/W */ + AESECBLPF3_processDataCPU(input, output, inputLength); + } + else + { + AESECBLPF3_processDataDMA(object, input, output, inputLength); + } +} + +/* + * ======== AESECBLPF3_processDataCPU ======== + */ +static inline void AESECBLPF3_processDataCPU(const uint8_t *input, uint8_t *output, size_t inputLength) +{ + /* + * For efficiency, the next block of data can be written to AES BUF regs + * while the AES engine is encrypting the previous block. The AES engine + * takes 23-cycles to encrypt a block. If the SW can load blocks faster + * than that, SW must wait until the AES HW is idle after writing two + * blocks consecutively to avoid overwriting data before the AES engine + * can consume it. + */ +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) + size_t inputBytesProcessed = 0; + size_t outputBytesProcessed = 0; + + if (!IS_WORD_ALIGNED(input) || !IS_WORD_ALIGNED(output)) + { + /* Write first block of input to trigger encryption */ + AESWriteBUF(&input[inputBytesProcessed]); + inputBytesProcessed += AES_BLOCK_SIZE; + + while (inputBytesProcessed < inputLength) + { + /* Preload next input block */ + AESWriteBUF(&input[inputBytesProcessed]); + inputBytesProcessed += AES_BLOCK_SIZE; + + #ifdef AES_BUSHALT_DISABLED + /* Wait for encryption of previous input to complete */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + #endif + /* + * Read output and trigger encryption of next input that was + * preloaded at the start of this loop. + */ + AESReadTXT(&output[outputBytesProcessed]); + outputBytesProcessed += AES_BLOCK_SIZE; + } + + /* Avoid triggering a spurious encryption upon reading the final output */ + AESClearAUTOCFGTrigger(); + #ifdef AES_BUSHALT_DISABLED + /* Wait for encryption of final input block */ + while (AESGetStatus() != (uint32_t)AES_STA_STATE_IDLE) {} + #endif + /* Read final output */ + AESReadTXT(&output[outputBytesProcessed]); + } + else +#endif /* (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) */ + { + AESProcessAlignedBlocksECB((const uint32_t *)input, + (uint32_t *)output, + (uint32_t)AES_GET_NUM_BLOCKS(inputLength)); + } +} + +/* + * ======== AESECBLPF3_processDataDMA ======== + */ +static inline void AESECBLPF3_processDataDMA(AESCommonLPF3_Object *object, + const uint8_t *input, + uint8_t *output, + size_t inputLength) +{ + /* Clear BUSHALT when using DMA */ + AESClearAUTOCFGBusHalt(); + + /* Setup DMA configuration and set power constraint */ + AESCommonLPF3_setupDMA(object, AESECBLPF3_DMA_CONFIG); + + AESCommonLPF3_configInputDMA(input, inputLength); + AESCommonLPF3_configOutputDMA(output, inputLength); + + /* Enable interrupt upon output DMA done */ + AESSetIMASK((uint32_t)AES_IMASK_CHBDONE_M); + + /* Manually trigger the DMA to start the ECB operation */ + AESSetTrigger((uint32_t)AES_TRG_DMACHA); +} + +/* + * ======== AESECBLPF3_waitForResult ======== + */ +static inline int_fast16_t AESECBLPF3_waitForResult(AESECB_Handle handle) +{ + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_POLLING) || + (object->operation->inputLength < AESECBLPF3_DMA_SIZE_THRESHOLD)) + { + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten. + */ + status = object->common.returnStatus; + + /* Mark that the current single-step or multi-step operation is done */ + if (object->operationType != AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + AESCommonLPF3_clearOperationInProgress(&object->common); + } + + AESCommonLPF3_cleanup(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, object->operation, object->operationType); + + /* Always return success in callback mode */ + status = AESECB_STATUS_SUCCESS; + } + } + else if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + /* Ignore return value since timeout is infinite */ + (void)SemaphoreP_pend((SemaphoreP_Handle)&CryptoResourceLPF3_operationSemaphore, + (uint32_t)SemaphoreP_WAIT_FOREVER); + + status = object->common.returnStatus; + } + else /* AES_RETURN_BEHAVIOR_CALLBACK */ + { + /* Success is always returned in callback mode */ + status = AESECB_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESECB_setupEncrypt ======== + */ +int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + + if (status == AES_STATUS_SUCCESS) + { + /* + * Initialize operation pointer to NULL in case AESECB_cancelOperation + * is called after AESECB_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + } + + if (status == AES_STATUS_SUCCESS) + { + object->operationType = AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED; + } + + return status; +} + +/* + * ======== AESECB_setupDecrypt ======== + */ +int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + DebugP_assert(key); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* Save the error status in case addData or finalize is called afterward */ + object->common.returnStatus = AESECB_STATUS_FEATURE_NOT_SUPPORTED; + return AESECB_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESECB_addData ======== + */ +int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + /* + * Assert the segmented operation was setup. + * LPF3 only supports ECB encryption. + */ + DebugP_assert(object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESECB_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + status = AESECBLPF3_checkOperation(object, operation); + + if (status != AESECB_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operation = operation; + + return AESECBLPF3_startOperation(handle, operation); +} + +/* + * ======== AESECB_finalize ======== + */ +int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + /* + * Assert the segmented operation was setup. + * LPF3 only supports ECB encryption. + */ + DebugP_assert(object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESECB_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + if (operation->inputLength > 0U) + { +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 0) + /* Check word-alignment of input & output pointers */ + if (!IS_WORD_ALIGNED(operation->input) || !IS_WORD_ALIGNED(operation->output)) + { + return AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } +#endif + + /* Verify input length is a multiple of the AES block size */ + if ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U)) + { + return AESECB_STATUS_ERROR; + } + + /* Check DMA xfer limit for blocking and callback modes */ + if ((object->common.returnBehavior != AES_RETURN_BEHAVIOR_POLLING) && + !AESCommonLPF3_isDMALengthValid(operation->input, operation->output, operation->inputLength)) + { + return AESECB_STATUS_ERROR; + } + } + + AESECB_OperationType operationType = AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED; + + if (operation->inputLength > 0U) + { + /* Try and obtain access to the crypto module */ + if (object->threadSafe) + { + if (!CryptoResourceLPF3_acquireLock(object->common.semaphoreTimeout)) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + object->common.cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = operation; + + status = AESECBLPF3_startOperation(handle, operation); + } + else /* Operation was finalized without additional data to process */ + { + status = object->common.returnStatus; + + AESCommonLPF3_clearOperationInProgress(&object->common); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, operation, operationType); + + /* Always return success in callback mode */ + status = AESECB_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESECB_cancelOperation ======== + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) +{ + DebugP_assert(handle); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* Cancellation is only supported in callback mode */ + if (object->common.returnBehavior != AES_RETURN_BEHAVIOR_CALLBACK) + { + return AESECB_STATUS_ERROR; + } + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Return success if there is no active operation to cancel. + * Do not execute the callback as it would have been executed already + * when the operation completed. + */ + if (!object->common.operationInProgress) + { + HwiP_restore(interruptKey); + return AESECB_STATUS_SUCCESS; + } + + HwiP_restore(interruptKey); + + /* + * Cancel DMA for input and output channels, clear operation in-progress, + * and releases crypto resource if necessary. + */ + AESCommonLPF3_cancelOperation(&object->common, true); + + /* + * Operation pointer could be NULL if a segmented operation was setup + * but neither AESCCM_addData or AESCCM_finalize was called. + */ + if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESECB_STATUS_CANCELED, object->operation, object->operationType); + } + + return AESECB_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h new file mode 100644 index 00000000..71a62f0b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESECBLPF3.h + * + * @brief AESECB driver implementation for the Low Power F3 family + * + * # Hardware Accelerator # + * The Low Power F3 family of devices has a dedicated AES hardware that can perform + * AES encryption operations with 128-bit keys. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers + * relying on the accelerator. It is transparent to the application and only + * noted to ensure sensible access timeouts are set. + * + * # Implementation Limitations + * - Decryption is not supported since the AES HW only supports encryption. + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to + * them are checked (such as whether a driver is already open). Higher input + * parameter validation coverage is achieved by turning on assertions when + * compiling the driver. + */ + +#ifndef ti_drivers_aesecb_AESECBLPF3__include +#define ti_drivers_aesecb_AESECBLPF3__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The threshold at which blocking and callback mode transfers will utilize DMA. + * For data lengths below this threshold, polling CPU R/W will be used instead + * of DMA. With task switching and interrupt overhead, it is inefficient to + * utilize DMA for shorter length operations. + * The threshold value must be a multiple of AES_BLOCK_SIZE. + */ +#define AESECBLPF3_DMA_SIZE_THRESHOLD (1U * AES_BLOCK_SIZE) + +/* + * AES ECB auto config for a single block encryption: + * ECB SRC as BUF + * Trigger points for auto ECB as WRBUF3S (encryption starts by writing BUF3) + * BUSHALT enabled + */ +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 + #define AESEBCLPF3_SINGLE_BLOCK_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#elif DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX + #define AESEBCLPF3_SINGLE_BLOCK_AUTOCFG \ + ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | (uint32_t)AES_AUTOCFG_BUSHALT_EN) +#else + #error "Unsupported DeviceFamily_Parent for AESECBLPF3!" +#endif + +/*! + * @brief AESECBLPF3 Hardware Attributes + * + * AESECBLPF3 hardware attributes should be included in the board file + * and pointed to by the AESECB_config struct. + */ +typedef AESCommonLPF3_HWAttrs AESECBLPF3_HWAttrs; + +/*! + * @brief AESECBLPF3 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* Common member first to allow struct to be cast to the common type */ + AESCommonLPF3_Object common; + AESECB_Operation *operation; + AESECB_CallbackFxn callbackFxn; + AESECB_OperationType operationType; + bool threadSafe; +} AESECBLPF3_Object; + +/*! + * @cond NODOC + * + * @brief Helper function to encrypt plaintext input + * + * Writes the first block of data and calls #AESECBLPF3_processBlock() + * + * @note This will be reused for AES CBC mode which is why it's exposed here. + * + * @param [in] object Pointer to an #AESCommonLPF3_Object to track if + * a HW operation is in progress + * @param [in] input Plaintext input to be encrypted + * @param [out] output Buffer to store the decrypted ciphertext + * @param [in] inputLength Length of input to be encrypted + */ +void AESECBLPF3_processData(AESCommonLPF3_Object *object, const uint8_t *input, uint8_t *output, size_t inputLength); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Acquire Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESECB handle + * @param [in] timeout Timeout (in ClockP ticks) to wait for the semaphore. + * - @ref SemaphoreP_WAIT_FOREVER + * - @ref SemaphoreP_NO_WAIT + * + * @return true - Succeeded acquiring the lock on crypto resource + * false - Failed to acquire the lock on crypto resource + */ +__STATIC_INLINE bool AESECB_acquireLock(AESECB_Handle handle, uint32_t timeout) +{ + return CryptoResourceLPF3_acquireLock(timeout); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Release Lock on Crypto Resource. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESECB handle + */ +__STATIC_INLINE void AESECB_releaseLock(AESECB_Handle handle) +{ + CryptoResourceLPF3_releaseLock(); +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Enable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @param [in] handle AESECB handle + */ +__STATIC_INLINE void AESECB_enableThreadSafety(AESECB_Handle handle) +{ + AESECBLPF3_Object *object = handle->object; + object->threadSafe = true; +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Disable thread safety. This is an internal function that + * that may be called by other drivers to handle thread safety directly. + * + * @note The user is responsible for reenabling thread safety after being + * done with the need for this driver. + * + * @param [in] handle AESECB handle + */ +__STATIC_INLINE void AESECB_disableThreadSafety(AESECB_Handle handle) +{ + AESECBLPF3_Object *object = handle->object; + object->threadSafe = false; +} +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesecb_AESECBLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/config_defaults.c b/simplelink_lpf3/source/ti/drivers/config_defaults.c new file mode 100644 index 00000000..d15face3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/config_defaults.c @@ -0,0 +1,221 @@ +#include +#include + +/* + * ======== AESCCM ======== + */ + +extern const uint_least8_t CONFIG_AESCCM_0_CONST; +#define CONFIG_AESCCM_0 0 +#define CONFIG_TI_DRIVERS_AESCCM_COUNT 1 + + +/* + * ======== AESCMAC ======== + */ + +extern const uint_least8_t CONFIG_AESCMAC_0_CONST; +#define CONFIG_AESCMAC_0 0 +#define CONFIG_TI_DRIVERS_AESCMAC_COUNT 1 + + +/* + * ======== AESCTR ======== + */ + +extern const uint_least8_t CONFIG_AESCTR_0_CONST; +#define CONFIG_AESCTR_0 0 +#define CONFIG_TI_DRIVERS_AESCTR_COUNT 1 + + +/* + * ======== AESCTRDRBG ======== + */ + +extern const uint_least8_t CONFIG_AESCTRDRBG_0_CONST; +#define CONFIG_AESCTRDRBG_0 0 +#define CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT 1 + + +/* + * ======== AESECB ======== + */ + +extern const uint_least8_t CONFIG_AESECB_0_CONST; +#define CONFIG_AESECB_0 0 +#define CONFIG_TI_DRIVERS_AESECB_COUNT 1 + + +/* + * ======== ECDH ======== + */ + +extern const uint_least8_t CONFIG_ECDH_0_CONST; +#define CONFIG_ECDH_0 0 +#define CONFIG_TI_DRIVERS_ECDH_COUNT 1 + +/* + * =============================== AESCCM =============================== + */ + +#include +#include + +#define CONFIG_AESCCM_COUNT 1 +AESCCMLPF3_Object AESCCMLPF3_objects[CONFIG_AESCCM_COUNT]; + +/* + * ======== AESCCMLPF3_hwAttrs ======== + */ +const AESCCMLPF3_HWAttrs AESCCMLPF3_hwAttrs[CONFIG_AESCCM_COUNT] = { + { + .intPriority = (~0), + }, +}; + +const AESCCM_Config AESCCM_config[CONFIG_AESCCM_COUNT] = { + { /* CONFIG_AESCCM_0 */ + .object = &AESCCMLPF3_objects[CONFIG_AESCCM_0], + .hwAttrs = &AESCCMLPF3_hwAttrs[CONFIG_AESCCM_0] + }, +}; + +const uint_least8_t CONFIG_AESCCM_0_CONST = CONFIG_AESCCM_0; +const uint_least8_t AESCCM_count = CONFIG_AESCCM_COUNT; + +/* + * =============================== AESCMAC =============================== + */ + +#include +#include + +#define CONFIG_AESCMAC_COUNT 1 +AESCMACLPF3_Object AESCMACLPF3_objects[CONFIG_AESCMAC_COUNT]; + +/* + * ======== AESCMACLPF3_hwAttrs ======== + */ +const AESCMACLPF3_HWAttrs AESCMACLPF3_hwAttrs[CONFIG_AESCMAC_COUNT] = { + { + .intPriority = (~0), + }, +}; + +const AESCMAC_Config AESCMAC_config[CONFIG_AESCMAC_COUNT] = { + { /* CONFIG_AESCMAC_0 */ + .object = &AESCMACLPF3_objects[CONFIG_AESCMAC_0], + .hwAttrs = &AESCMACLPF3_hwAttrs[CONFIG_AESCMAC_0] + }, +}; + +const uint_least8_t CONFIG_AESCMAC_0_CONST = CONFIG_AESCMAC_0; +const uint_least8_t AESCMAC_count = CONFIG_AESCMAC_COUNT; + +/* + * =============================== AESCTR =============================== + */ + +#include +#include + +#define CONFIG_AESCTR_COUNT 1 +AESCTRLPF3_Object AESCTRLPF3_objects[CONFIG_AESCTR_COUNT]; + +/* + * ======== AESCTRLPF3_hwAttrs ======== + */ +const AESCTRLPF3_HWAttrs AESCTRLPF3_hwAttrs[CONFIG_AESCTR_COUNT] = { + { + .intPriority = (~0), + }, +}; + +const AESCTR_Config AESCTR_config[CONFIG_AESCTR_COUNT] = { + { /* CONFIG_AESCTR_0 */ + .object = &AESCTRLPF3_objects[CONFIG_AESCTR_0], + .hwAttrs = &AESCTRLPF3_hwAttrs[CONFIG_AESCTR_0] + }, +}; + +const uint_least8_t CONFIG_AESCTR_0_CONST = CONFIG_AESCTR_0; +const uint_least8_t AESCTR_count = CONFIG_AESCTR_COUNT; + +/* + * =============================== AESCTRDRBG =============================== + */ + +#include +#include + +#define CONFIG_AESCTRDRBG_COUNT 1 + +/* + * ======== aesctrdrbgXXObjects ======== + */ +AESCTRDRBGXX_Object aesctrdrbgXXObjects[CONFIG_AESCTRDRBG_COUNT]; + +/* + * ======== aesctrdrbgXXHWAttrs ======== + */ +const AESCTRDRBGXX_HWAttrs aesctrdrbgXXHWAttrs[CONFIG_AESCTRDRBG_COUNT] = { + /* CONFIG_AESCTRDRBG_0 */ + { + .aesctrHWAttrs.intPriority = (~0) + }, +}; + +/* + * ======== AESCTRDRBG_config ======== + */ +const AESCTRDRBG_Config AESCTRDRBG_config[CONFIG_AESCTRDRBG_COUNT] = { + /* CONFIG_AESCTRDRBG_0 */ + { + .object = &aesctrdrbgXXObjects[CONFIG_AESCTRDRBG_0], + .hwAttrs = &aesctrdrbgXXHWAttrs[CONFIG_AESCTRDRBG_0] + }, +}; + +const uint_least8_t CONFIG_AESCTRDRBG_0_CONST = CONFIG_AESCTRDRBG_0; +const uint_least8_t AESCTRDRBG_count = CONFIG_AESCTRDRBG_COUNT; + +/* + * =============================== AESECB =============================== + */ + +#include +#include + +#define CONFIG_AESECB_COUNT 1 +AESECBLPF3_Object AESECBLPF3_objects[CONFIG_AESECB_COUNT]; + +/* + * ======== AESECBLPF3_hwAttrs ======== + */ +const AESECBLPF3_HWAttrs AESECBLPF3_hwAttrs[CONFIG_AESECB_COUNT] = { + { + .intPriority = (~0), + }, +}; + +const AESECB_Config AESECB_config[CONFIG_AESECB_COUNT] = { + { /* CONFIG_AESECB_0 */ + .object = &AESECBLPF3_objects[CONFIG_AESECB_0], + .hwAttrs = &AESECBLPF3_hwAttrs[CONFIG_AESECB_0] + }, +}; + + +const uint_least8_t CONFIG_AESECB_0_CONST = CONFIG_AESECB_0; +const uint_least8_t AESECB_count = CONFIG_AESECB_COUNT; + +/* + * =============================== DMA =============================== + */ + +#include +#include + +const UDMALPF3_Config UDMALPF3_config = { + .CtrlBaseAddr = UDMALPF3_CONFIG_BASE, +}; diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c new file mode 100644 index 00000000..7bcce130 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(inc/hw_dma.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) + +/* Static globals */ +static bool AESCommon_isInitialized = false; + +/* DMA Control Table Entries */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaChannel4ControlTableEntry, DMA_CH4); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaChannel5ControlTableEntry, DMA_CH5); + +static volatile uDMAControlTableEntry *dmaPriControlTableEntryChA = &dmaChannel4ControlTableEntry; +static volatile uDMAControlTableEntry *dmaPriControlTableEntryChB = &dmaChannel5ControlTableEntry; + +/* Forward declarations */ +void AESCommonLPF3_setPowerConstraint(AESCommonLPF3_Object *object); +void AESCommonLPF3_releasePowerConstraint(AESCommonLPF3_Object *object); + +/* + * ======== AESCommonLPF3_init ======== + */ +void AESCommonLPF3_init(void) +{ + CryptoResourceLPF3_constructRTOSObjects(); + + UDMALPF3_init(); + + AESCommon_isInitialized = true; +} + +/* + * ======== AESCommonLPF3_construct ======== + */ +int_fast16_t AESCommonLPF3_construct(AESCommonLPF3_Object *object, AES_ReturnBehavior returnBehavior, uint32_t timeout) +{ + DebugP_assert(object); + + uintptr_t interruptKey = HwiP_disable(); + + if (!AESCommon_isInitialized || object->isOpen) + { + HwiP_restore(interruptKey); + + return AES_STATUS_ERROR; + } + + object->isOpen = true; + + HwiP_restore(interruptKey); + + object->returnBehavior = returnBehavior; + + if (returnBehavior == AES_RETURN_BEHAVIOR_BLOCKING) + { + object->semaphoreTimeout = timeout; + } + else + { + object->semaphoreTimeout = SemaphoreP_NO_WAIT; + } + + if (returnBehavior != AES_RETURN_BEHAVIOR_POLLING) + { + /* + * Configure DMA channels 4 & 5 for LAES TRG A & B respectively. + * Channels 4 & 5 are the only channels which can be used with LAES + * because channels 6 & 7 do not support the DMA Done signal. + * + * AES Channel A is used for input and Channel B is used for output. + * + * CMAC and CBC-MAC AES modes use input DMA only. + */ + HWREG(EVTSVT_BASE + EVTSVT_O_DMACH4SEL) = EVTSVT_DMACH4SEL_IPID_LAESTRGA; + HWREG(EVTSVT_BASE + EVTSVT_O_DMACH5SEL) = EVTSVT_DMACH5SEL_IPID_LAESTRGB; + } + + object->cryptoResourceLocked = false; + object->operationInProgress = false; + object->powerConstraintSet = false; + + /* Set power dependency. Power up and enable clock for DMA peripheral */ + Power_setDependency(PowerLPF3_PERIPH_DMA); + + /* Set power dependency. Power up and enable clock for LAES peripheral */ + Power_setDependency(PowerLPF3_PERIPH_AES); + + return AES_STATUS_SUCCESS; +} + +/* + * ======== AESCommonLPF3_close ======== + */ +void AESCommonLPF3_close(AESCommonLPF3_Object *object) +{ + DebugP_assert(object); + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on DMA module */ + Power_releaseDependency(PowerLPF3_PERIPH_DMA); + + /* Release power dependency on LAES module */ + Power_releaseDependency(PowerLPF3_PERIPH_AES); +} + +/* + * ======== AESCommonLPF3_setOperationInProgress ======== + */ +int_fast16_t AESCommonLPF3_setOperationInProgress(AESCommonLPF3_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + + return AES_STATUS_ERROR; + } + + object->operationInProgress = true; + + HwiP_restore(interruptKey); + + return AES_STATUS_SUCCESS; +} + +/* + * ======== AESCommonLPF3_setupOperation ======== + */ +void AESCommonLPF3_setupOperation(CryptoKey *key, uint32_t autoCfgVal) +{ + /* Load Key */ + AESCommonLPF3_loadKey(key); + + /* Set AUTOCFG */ + AESSetAUTOCFG(autoCfgVal); +} + +/* + * ======== AESCommonLPF3_loadKey ======== + */ +void AESCommonLPF3_loadKey(const CryptoKey *key) +{ + const uint8_t *keyMaterial; + + /* Only plaintext CryptoKeys are supported currently */ + DebugP_assert((key->encoding == CryptoKey_PLAINTEXT) || (key->encoding == CryptoKey_BLANK_PLAINTEXT)); + + keyMaterial = key->u.plaintext.keyMaterial; + + DebugP_assert(keyMaterial); + + /* AES engine supports only 128-bit (16-byte) keys. */ + DebugP_assert(key->u.plaintext.keyLength == AES_128_KEY_LENGTH_BYTES); + + /* Write keyMaterial to the AES engine */ + AESWriteKEY(keyMaterial); +} +/* + * ======== AESAESCommonLPF3_cleanup ======== + */ +void AESCommonLPF3_cleanup(AESCommonLPF3_Object *object) +{ + if (object->returnBehavior != AES_RETURN_BEHAVIOR_POLLING) + { + AESSetIMASK((uint32_t)0U); + AESDisableDMA(); + + IntDisable(INT_AES_COMB); + + /* + * Disable DMA channels A & B. Assuming DMA channels are statically + * mapped, this should always be safe to do. This must be done before + * calling AESAbort. + */ + UDMALPF3_channelDisable(AESCommonLPF3_DMA_CHA_BITMASK | AESCommonLPF3_DMA_CHB_BITMASK); + } + + /* + * Abort any spurious encryption and clear TXT, BUF, DMA, AUTOCFG registers. + */ + AESAbort(); + + /* Clear all AES interrupts */ + AESClearInterrupt(AES_ICLR_ALL); + + if (object->cryptoResourceLocked) + { + object->cryptoResourceLocked = false; + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow + * the chaining of operations. + */ + CryptoResourceLPF3_releaseLock(); + } + + AESCommonLPF3_releasePowerConstraint(object); +} + +/* + * ======== AESCommonLPF3_setupSegmentedOperation ======== + */ +int_fast16_t AESCommonLPF3_setupSegmentedOperation(AESCommonLPF3_Object *object, const CryptoKey *key) +{ + int_fast16_t status; + + /* Check that there is no operation in progress for this driver instance */ + status = AESCommonLPF3_setOperationInProgress(object); + + if (status == AES_STATUS_SUCCESS) + { + /* Make internal copy of crypto key */ + object->key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->returnStatus = AES_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCommonLPF3_configInputDMA ======== + */ +void AESCommonLPF3_configInputDMA(const void *input, size_t inputLength) +{ + uint32_t control; + uint32_t numTransfers; + + /* + * Set the source data width and address increment based upon the address + * alignment. Arbitrate after 16-bytes (AES block size). No destination + * address increment. + */ +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) + if (((uintptr_t)input & 0x1U) != 0U) + { + control = UDMA_DST_INC_NONE | UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_ARB_16; + numTransfers = (uint32_t)inputLength; + } + else if (((uintptr_t)input & 0x2U) != 0U) + { + control = UDMA_DST_INC_NONE | UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_ARB_8; + numTransfers = (uint32_t)inputLength >> 1; + } + else +#endif + { + control = UDMA_DST_INC_NONE | UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_ARB_4; + numTransfers = (uint32_t)inputLength >> 2; + } + + /* + * Setup DMA channel A Primary Control Struct: + * - + */ + uDMASetChannelControl(dmaPriControlTableEntryChA, control); + + /* + * Setup DMA channel A Primary Control Struct: + * - Mode = Basic + * - Input & Output end pointers + * - Set n-1, where n = number DMA transfers that the DMA cycle contains. + */ + uDMASetChannelTransfer(dmaPriControlTableEntryChA, + UDMA_MODE_BASIC, + (void *)input, + (void *)(AES_BASE + AES_O_DMACHA), + numTransfers); + + /* Enable the channel for AES input */ + UDMALPF3_channelEnable(AESCommonLPF3_DMA_CHA_BITMASK); +} + +/* + * ======== AESCommonLPF3_isDMALengthValid ======== + */ +bool AESCommonLPF3_isDMALengthValid(const void *input, const void *output, size_t length) +{ + size_t maxLength = 4096; + +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) + uintptr_t alignment = (uintptr_t)input | (uintptr_t)output; + + if (alignment & 0x1U) + { + maxLength = 1024; + } + else if (alignment & 0x2U) + { + maxLength = 2048; + } +#endif + return (length <= maxLength); +} + +/* + * ======== AESCommonLPF3_configOutputDMA ======== + */ +void AESCommonLPF3_configOutputDMA(void *output, size_t outputLength) +{ + uint32_t control; + uint32_t numTransfers; + + /* + * Set the source data width and address increment based upon the address + * alignment. Arbitrate after 16-bytes (AES block size). No source address + * increment. + */ +#if (AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE == 1) + if (((uintptr_t)output & 0x1U) != 0U) + { + control = UDMA_SRC_INC_NONE | UDMA_SIZE_8 | UDMA_DST_INC_8 | UDMA_ARB_16; + numTransfers = outputLength; + } + else if (((uintptr_t)output & 0x2U) != 0U) + { + control = UDMA_SRC_INC_NONE | UDMA_SIZE_16 | UDMA_DST_INC_16 | UDMA_ARB_8; + numTransfers = outputLength >> 1; + } + else +#endif + { + control = UDMA_SRC_INC_NONE | UDMA_SIZE_32 | UDMA_DST_INC_32 | UDMA_ARB_4; + numTransfers = outputLength >> 2; + } + + /* + * Setup DMA channel B Primary Control struct control params: + * - + */ + uDMASetChannelControl(dmaPriControlTableEntryChB, control); + + /* + * Setup DMA channel B Primary Control struct transfer params: + * - Mode = Basic + * - Input & Output end pointers + * - Set n-1, where n = number DMA transfers that the DMA cycle contains. + */ + uDMASetChannelTransfer(dmaPriControlTableEntryChB, + UDMA_MODE_BASIC, + (void *)(AES_BASE + AES_O_DMACHB), + output, + numTransfers); + + /* Enable the channel for AES input */ + UDMALPF3_channelEnable(AESCommonLPF3_DMA_CHB_BITMASK); +} + +/* + * ======== AESCommonLPF3_cancelDMA ======== + */ +void AESCommonLPF3_cancelDMA(bool cancelChannelB) +{ + IntDisable(INT_AES_COMB); + AESSetIMASK((uint32_t)0U); + AESDisableDMA(); + + uint32_t channelBitMask = AESCommonLPF3_DMA_CHA_BITMASK; + if (cancelChannelB) + { + channelBitMask |= AESCommonLPF3_DMA_CHB_BITMASK; + } + + /* Disable DMA channel(s) */ + UDMALPF3_channelDisable(channelBitMask); + + /* Set DMA channels to STOP */ + uDMASetChannelTransfer(dmaPriControlTableEntryChA, UDMA_MODE_STOP, 0, 0, 0); + + if (cancelChannelB) + { + uDMASetChannelTransfer(dmaPriControlTableEntryChB, UDMA_MODE_STOP, 0, 0, 0); + } + + /* Abort must be done after disabling DMA channels according to LAES spec */ + AESAbort(); + + /* Clear all AES interrupts */ + AESClearInterrupt(AES_ICLR_ALL); +} + +/* + * ======== AESCommonLPF3_cancelOperation ======== + */ +void AESCommonLPF3_cancelOperation(AESCommonLPF3_Object *object, bool cancelDMAChannelB) +{ + if (object->returnBehavior != AES_RETURN_BEHAVIOR_POLLING) + { + AESCommonLPF3_cancelDMA(cancelDMAChannelB); + } + + AESCommonLPF3_releasePowerConstraint(object); + + object->returnStatus = AES_STATUS_CANCELED; + + AESCommonLPF3_clearOperationInProgress(object); + + if (object->cryptoResourceLocked) + { + object->cryptoResourceLocked = false; + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow + * the chaining of operations. + */ + CryptoResourceLPF3_releaseLock(); + } +} + +/* + * ======== AESCommonLPF3_setupHwi ======== + */ +void AESCommonLPF3_setupHwi(HwiP_Fxn hwiFxn, uintptr_t hwiFxnArg, uint8_t intPriority) +{ + HwiP_setFunc(&CryptoResourceLPF3_hwi, hwiFxn, hwiFxnArg); + HwiP_setPriority(INT_AES_COMB, (uint32_t)intPriority); + IntEnable((uint32_t)INT_AES_COMB); +} + +/* + * ======== AESCommonLPF3_setPowerConstraint ======== + */ +void AESCommonLPF3_setPowerConstraint(AESCommonLPF3_Object *object) +{ + /* Ignore return value since it always returns Power_SOK */ + (void)Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + object->powerConstraintSet = true; +} + +/* + * ======== AESCommonLPF3_releasePowerConstraint ======== + */ +void AESCommonLPF3_releasePowerConstraint(AESCommonLPF3_Object *object) +{ + if (object->powerConstraintSet) + { + object->powerConstraintSet = false; + /* Ignore return value since it always returns Power_SOK */ + (void)Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } +} + +/* + * ======== AESCommonLPF3_setupDMA ======== + */ +void AESCommonLPF3_setupDMA(AESCommonLPF3_Object *object, uint32_t dmaConfig) +{ + AESSetupDMA(dmaConfig); + + AESCommonLPF3_setPowerConstraint(object); +} + +/* + * ======== AESCommonLPF3_cleanupHwi ======== + */ +void AESCommonLPF3_cleanupHwi(AESCommonLPF3_Object *object) +{ + AESDisableDMA(); + AESSetIMASK((uint32_t)0U); + /* Clear all AES interrupts */ + AESClearInterrupt(AES_ICLR_ALL); + + AESCommonLPF3_releasePowerConstraint(object); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.h new file mode 100644 index 00000000..97165a50 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/aes/AESCommonLPF3.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESCommonLPF3.h + * + * @brief AESCommon driver implementation for the Low Power F3 family + * + * The AESCommonLPF3 module provides common functionality used by the + * AES mode-specific implementations for the Low Power F3 family. + */ + +#ifndef ti_drivers_aescommon_AESCommonLPF3__include +#define ti_drivers_aescommon_AESCommonLPF3__include + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Unaligned input/output pointer arguments are not supported by default + * because the performance will be up to 5x slower. Enabling unaligned I/O + * is strongly discouraged. + */ +#ifndef AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE + #define AESCommonLPF3_UNALIGNED_IO_SUPPORT_ENABLE 0 +#endif + +/* DMA Channel Numbers */ +#define DMA_CH4 4U +#define DMA_CH5 5U + +/* DMA Channel 4 is reserved for AES Channel A (input) */ +#define AESCommonLPF3_DMA_CHA_BITMASK ((uint32_t)1U << DMA_CH4) +/* DMA Channel 5 is reserved for AES Channel B (output) */ +#define AESCommonLPF3_DMA_CHB_BITMASK ((uint32_t)1U << DMA_CH5) + +/*! + * @brief AESCommonLPF3 Hardware Attributes + */ +typedef struct +{ + /*! + * @brief Crypto Peripheral's interrupt priority. + * + * The Low Power F3 devices use either three or two priority bits, + * depending on the device. That means ~0 has the same effect as (7 << 5) + * or (3 << 6), respectively. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + * interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESCommonLPF3_HWAttrs; + +/*! + * @brief AESCommonLPF3 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + CryptoKey key; + volatile int_fast16_t returnStatus; + AES_ReturnBehavior returnBehavior; + bool isOpen; + volatile bool cryptoResourceLocked; + volatile bool operationInProgress; + volatile bool powerConstraintSet; +} AESCommonLPF3_Object; + +/*! + * @cond NODOC + * + * @brief Initializes the common Crypto Resource RTOS objects used by AES drivers. + * + * @note The RTOS objects are common to all AES modes and are initialized + * only once. + */ +void AESCommonLPF3_init(void); + +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Constructs a new driver instance. + * + * @param [in] object #AESCommonLPF3_Object to configure the driver + * instance. + * @param [in] returnBehavior #AES_ReturnBehavior to configure the driver + * instance. + * @param [in] timeout timeout to configure the driver instance. + */ +int_fast16_t AESCommonLPF3_construct(AESCommonLPF3_Object *object, AES_ReturnBehavior returnBehavior, uint32_t timeout); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Loads the Key material into the AES HW + * + * @param [in] key Pointer to the CryptoKey object containing the keyMaterial + */ +void AESCommonLPF3_loadKey(const CryptoKey *key); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Initializes the key and autoCFG values for an AES operation. + * + * @param [in] key Pointer to the CryptoKey object containing the keyMaterial + * @param [in] autoCfgVal The AUTOCFG value to be set. + */ +void AESCommonLPF3_setupOperation(CryptoKey *key, uint32_t autoCfgVal); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Closes a given driver instance. + * + * @param [in] object Pointer to an AESCommonLPF3 object + * + */ +void AESCommonLPF3_close(AESCommonLPF3_Object *object); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Marks an operation to be in progress. + * + * @param [in] object Pointer to an AESCommonLPF3 object + * + * @retval AES_STATUS_SUCCESS Successfully set operation in progress + * @retval AES_STATUS_ERROR Another operation already in progress + */ +int_fast16_t AESCommonLPF3_setOperationInProgress(AESCommonLPF3_Object *object); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Clears an operation to be in progress. + * + * @param [in] object Pointer to an AESCommonLPF3 object + * + */ +__STATIC_INLINE void AESCommonLPF3_clearOperationInProgress(AESCommonLPF3_Object *object) +{ + object->operationInProgress = false; +} +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Cleans up the driver object fields that can be reset + * in common across all AES modes after an operation is done + * and also releases the lock on the crypto resource. + * + * @param [in] object Pointer to an AESCommonLPF3 object + * + * @retval none + */ +void AESCommonLPF3_cleanup(AESCommonLPF3_Object *object); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Sets up a segmented operation. + * + * @param [in] object Pointer to an #AESCommonLPF3_Object + * @param [in] key Pointer to the CryptoKey object to store in object + */ +int_fast16_t AESCommonLPF3_setupSegmentedOperation(AESCommonLPF3_Object *object, const CryptoKey *key); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Checks whether the data length is valid for the given \a input and + * \a output pointers. + * + * @param [in] input Pointer to the input data + * @param [in] output Pointer to the output data + * @param [in] length Length of the data in bytes + * + * @return true if length is valid, false otherwise. + */ +bool AESCommonLPF3_isDMALengthValid(const void *input, const void *output, size_t length); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Configures the AES input DMA channel A for a transfer. + * + * @note Max \a inputLength depends on the alignment of the \a input pointer. + * If \a input is word-aligned, max \a inputLength is 4KB. + * If \a input is halfword-aligned, max \a inputLength is 2KB. + * If \a input is byte-aligned, max \a inputLength is 1KB. + * \a inputLength be a multiple of AES_BLOCK_SIZE for proper triggering. + * + * @param [in] input Pointer to the input data + * @param [in] inputLength Length of the input data in bytes, + * Must be a multiple of AES_BLOCK_SIZE. + */ +void AESCommonLPF3_configInputDMA(const void *input, size_t inputLength); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Configures the AES output DMA channel B for a transfer. + * + * @note Max \a outputLength depends on the alignment of the \a output pointer. + * If \a output is word-aligned, max \a outputLength is 4KB. + * If \a output is halfword-aligned, max \a outputLength is 2KB. + * If \a output is byte-aligned, max \a outputLength is 1KB. + * \a outputLength must match the \a inputLength used to call + * #AESCommonLPF3_configInputDMA. + * + * @param [out] output Pointer to the output data + * @param [in] outputLength Length of the output data in bytes, + * Must be a multiple of AES_BLOCK_SIZE. + */ +void AESCommonLPF3_configOutputDMA(void *output, size_t outputLength); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Cancels the AES input channels A. If \a cancelChannelB is true, + * cancels AES output DMA channel B as well. + * + * @param [in] object Pointer to an #AESCommonLPF3_Object + * @param [out] cancelChannelB Boolean indicating whether DMA Channel B should be cancelled + */ +void AESCommonLPF3_cancelDMA(bool cancelChannelB); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Handles common cancellation operations:
+ * 1) Cancels DMA channel(s)
+ * 2) Sets return status
+ * 3) Clears operation in-progress flag
+ * 4) Releases crypto resource lock + * + * @param [in] object Pointer to an #AESCommonLPF3_Object + * @param [out] cancelDMAChannelB Boolean indicating whether DMA Channel B should be cancelled + */ +void AESCommonLPF3_cancelOperation(AESCommonLPF3_Object *object, bool cancelDMAChannelB); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Sets the callback function, interrupt priority and enables the AES interrupt. + * + * @param [in] hwiFxn Interrupt callback function + * @param [in] hwiFxnArg Interrupt callback function argument + * @param [in] intPriority Interrupt priority + */ +void AESCommonLPF3_setupHwi(HwiP_Fxn hwiFxn, uintptr_t hwiFxnArg, uint8_t intPriority); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Clears and disables AES interrupts and release power constraint if set. + * + * @param [in] object Pointer to an #AESCommonLPF3_Object + */ +void AESCommonLPF3_cleanupHwi(AESCommonLPF3_Object *object); +/*! @endcond */ + +/*! + * @cond NODOC + * + * @brief Sets the AES DMA configuration and sets power constraint. + * + * @param [in] object Pointer to an #AESCommonLPF3_Object + * @param [in] dmaConfig AES DMA configuration + */ +void AESCommonLPF3_setupDMA(AESCommonLPF3_Object *object, uint32_t dmaConfig); +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescommon_AESCommonLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c new file mode 100644 index 00000000..23193b7d --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#if defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + + #include /* TI CMSE helper functions */ + +/* + * ======== CryptoKey_verifySecureKey ======== + */ +static int_fast16_t CryptoKey_verifySecureKey(const CryptoKey *secureKey, bool isWriteable) +{ + int_fast16_t status = CryptoKey_STATUS_ERROR; + void *ptr; + + if ((secureKey->encoding == CryptoKey_PLAINTEXT) || (secureKey->encoding == CryptoKey_BLANK_PLAINTEXT)) + { + /* Verify key material address range */ + if (isWriteable) + { + ptr = cmse_has_unpriv_nonsecure_rw_access(secureKey->u.plaintext.keyMaterial, + secureKey->u.plaintext.keyLength); + } + else + { + ptr = cmse_has_unpriv_nonsecure_read_access(secureKey->u.plaintext.keyMaterial, + secureKey->u.plaintext.keyLength); + } + + if (ptr != NULL) + { + status = CryptoKey_STATUS_SUCCESS; + } + } + else if ((secureKey->encoding == CryptoKey_KEYSTORE) || (secureKey->encoding == CryptoKey_BLANK_KEYSTORE)) + { + status = CryptoKey_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== CryptoKey_verifySecureInputKey ======== + */ +int_fast16_t CryptoKey_verifySecureInputKey(const CryptoKey *secureKey) +{ + return CryptoKey_verifySecureKey(secureKey, false); +} + +/* + * ======== CryptoKey_verifySecureOutputKey ======== + */ +int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey) +{ + return CryptoKey_verifySecureKey(secureKey, true); +} + +#endif /* TFM_BUILD */ + +/* + * ======== CryptoKey_getCryptoKeyType ======== + */ +int_fast16_t CryptoKey_getCryptoKeyType(const CryptoKey *keyHandle, CryptoKey_Encoding *keyType) +{ + *keyType = keyHandle->encoding; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKey_isBlank ======== + */ +int_fast16_t CryptoKey_isBlank(const CryptoKey *keyHandle, bool *isBlank) +{ + if ((keyHandle->encoding == CryptoKey_BLANK_PLAINTEXT) || (keyHandle->encoding == CryptoKey_BLANK_KEYSTORE)) + { + *isBlank = true; + } + else + { + *isBlank = false; + } + + return CryptoKey_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h new file mode 100644 index 00000000..2eca0004 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoKey.h + * + * @brief The CryptoKey type is an opaque representation of a cryptographic key. + * + * @warning This is a beta API. It may change in future releases. + * + * Cryptographic keying material may be stored on an embedded system multiple ways. + * - plaintext: in plaintext in flash or RAM + * - key store: in a dedicated hardware database whose entries can not be directly + * read out. + * + * Each storage option requires different approaches to handling the keying material + * when performing a crypto operation. In order to separate these concerns from + * the API of the various crypto drivers available with TI-RTOS, the CryptoKey + * type abstracts away from these details. It does not contain any cryptographic + * keying material itself but instead contains the details necessary for drivers to use the + * keying material. The driver implementation handles preparing and moving the keying + * material as necessary to perform the desired crypto operation. + * + * The same CryptoKey may be passed to crypto APIs of different modes subject to + * restrictions placed on the key by their storage types. Plaintext keys may be used + * without restriction while key store keys have their permitted uses + * restricted when the keying material is loaded. + * These restrictions are specified in a CryptoKey_SecurityPolicy that is device-specific + * and depends on the hardware capability of the device. + * + * An application should never access a field within a CryptoKey struct itself. + * Where needed, helper functions are provided to do so. + * + * Before using a CryptoKey in another crypto API call, it must be initialized + * with a call to one of the initialization functions. + * - CryptoKeyPlaintext_initKey() + * - CryptoKeyPlaintext_initBlankKey() + * - KeyStore_PSA_initKey() + * - KeyStore_PSA_initBlankKey() + * + * The keystore CryptoKeys may be used to load a key into a key store after + * its respective _init call. + * + * CryptoKeys can be initialized "blank", without keying material but with an empty buffer + * or key store entry, to encode the destination of a key to be created in the + * future. This way, keys may be generated securely within a key store + * for example and never even be stored in RAM temporarily. + * + * Not all devices support all CryptoKey functionality. This is hardware-dependent. + * + */ + +#ifndef ti_drivers_cryptoutils_cyptokey_CryptoKey__include +#define ti_drivers_cryptoutils_cyptokey_CryptoKey__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + + */ + +/** + * @defgroup CryptoKey_CONTROL Status codes + * These CryptoKey macros are reservations for CryptoKey.h + * @{ + */ + +/*! + * Common CryptoKey_control status code reservation offset. + * CryptoKey driver implementations should offset status codes with + * CryptoKey_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define CryptoKeyXYZ_STATUS_ERROR0 CryptoKey_STATUS_RESERVED - 0 + * #define CryptoKeyXYZ_STATUS_ERROR1 CryptoKey_STATUS_RESERVED - 1 + * #define CryptoKeyXYZ_STATUS_ERROR2 CryptoKey_STATUS_RESERVED - 2 + * @endcode + */ +#define CryptoKey_STATUS_RESERVED (-32) + +/** + * @defgroup CryptoKey_STATUS Status Codes + * CryptoKey_STATUS_* macros are general status codes returned by CryptoKey_control() + * @{ + * @ingroup CryptoKey_CONTROL + */ + +/*! + * @brief Successful status code + * + * CryptoKey_control() returns CryptoKey_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define CryptoKey_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_ERROR (-1) + +/*! + * @brief Returned if the encoding of a CryptoKey is not a CryptoKey_Encoding value + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_UNDEFINED_ENCODING (-2) + +/** @}*/ + +/** @}*/ + +/*! + * @brief List of the different types of CryptoKey. + * + */ +typedef uint8_t CryptoKey_Encoding; +static const CryptoKey_Encoding CryptoKey_PLAINTEXT = 0x02U; +static const CryptoKey_Encoding CryptoKey_BLANK_PLAINTEXT = 0x04U; +static const CryptoKey_Encoding CryptoKey_KEYSTORE = 0x08U; +static const CryptoKey_Encoding CryptoKey_BLANK_KEYSTORE = 0x10U; + +/*! + * @brief Plaintext CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in plaintext form in flash or RAM. + */ +typedef struct +{ + uint8_t *keyMaterial; + uint32_t keyLength; +} CryptoKey_Plaintext; + +/*! + * @brief Key store CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in a dedicated key store or key database with memory access controls. + * The application must ensure that the key attributes struct used to initialize the pointer + * #keyAttributes must either be a global variable or it must be available in the context of the + * function that makes the call to import the key associated with the same key attribute. + * Otherwise, the keyAttributes pointer will point to a location in stack that could be deallocated. + */ +typedef struct +{ + uint32_t keyLength; + uint32_t keyID; + void *keyAttributes; +} CryptoKey_KeyStore; + +/*! + * @brief CryptoKey datastructure. + * + * This structure contains a CryptoKey_Encoding and one of + * - CryptoKey_Plaintext + * - CryptoKey_KeyStore + */ +typedef struct +{ + CryptoKey_Encoding encoding; + union + { + CryptoKey_Plaintext plaintext; + CryptoKey_KeyStore keyStore; + } u; +} CryptoKey; + +/*! + * @brief Structure that specifies the restrictions on a CryptoKey + * + * This structure is device-specific and declared here in incomplete form. + * The structure is fully defined in CryptoKeyDEVICE.h. This creates a link-time binding + * when using the structure with key store functions. If the instance + * of the CryptoKey_SecurityPolicy is kept in a device-specific application-file, + * the generic application code may still use references to it despite being + * an incomplete type in the generic application file at compile time. + */ +typedef struct CryptoKey_SecurityPolicy_ CryptoKey_SecurityPolicy; + +/*! + * @brief Gets the key type of the CryptoKey + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] keyType Type of the CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_getCryptoKeyType(const CryptoKey *keyHandle, CryptoKey_Encoding *keyType); + +/*! + * @brief Whether the CryptoKey is 'blank' or represents valid keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] isBlank Whether the CryptoKey is 'blank' or not + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_isBlank(const CryptoKey *keyHandle, bool *isBlank); + +/*! + * @brief Function to initialize the CryptoKey_SecurityPolicy struct to its defaults + * + * This will zero-out all fields that cannot be set to safe defaults + * + * @param [in] policy Pointer to a CryptoKey_SecurityPolicy + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_initSecurityPolicy(CryptoKey_SecurityPolicy *policy); + +/*! + * @brief Function to verify a secure CryptoKey + * + * This will check that the key type is valid and verify plaintext key material + * is located in non-secure read-access memory. + * + * @note This function may not be available in all implementations + * + * @param [in] secureKey Pointer to a CryptoKey struct located in secure memory + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_verifySecureInputKey(const CryptoKey *secureKey); + +/*! + * @brief Function to verify a secure output CryptoKey + * + * This will check that the key type is valid and verify plaintext key material + * is located in non-secure RW-access memory. + * + * @note This function may not be available in all implementations + * + * @param [in] secureKey Pointer to a CryptoKey struct located in secure memory + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cyptokey_CryptoKey__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c new file mode 100644 index 00000000..aee82b53 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* CryptoKey headers */ +#include +#include +#include + +/* + * ======== KeyStore_PSA_initKey ======== + */ +int_fast16_t KeyStore_PSA_initKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_KEYSTORE; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_initBlankKey ======== + */ +int_fast16_t KeyStore_PSA_initBlankKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_BLANK_KEYSTORE; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_setKeyId ======== + */ +void KeyStore_PSA_setKeyId(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyFileId key) +{ + psa_set_key_id(attributes, key); +} + +/* + * ======== KeyStore_PSA_setKeyLifetime ======== + */ +void KeyStore_PSA_setKeyLifetime(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyLifetime lifetime) +{ + psa_set_key_lifetime(attributes, lifetime); +} + +/* + * ======== KeyStore_PSA_getKeyId ======== + */ +KeyStore_PSA_KeyFileId KeyStore_PSA_getKeyId(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_id(attributes); +} + +/* + * ======== KeyStore_PSA_getKeyLifetime ======== + */ +KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_lifetime(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyUsageFlags ======== + */ +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usage_flags) +{ + psa_set_key_usage_flags(attributes, usage_flags); +} + +/* + * ======== KeyStore_PSA_getKeyUsageFlags ======== + */ +KeyStore_PSA_KeyUsage KeyStore_PSA_getKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_usage_flags(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyAlgorithm ======== + */ +void KeyStore_PSA_setKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_Algorithm alg) +{ + psa_set_key_algorithm(attributes, alg); +} + +/* + * ======== KeyStore_PSA_getKeyAlgorithm ======== + */ +KeyStore_PSA_Algorithm KeyStore_PSA_getKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_algorithm(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyType ======== + */ +void KeyStore_PSA_setKeyType(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyType type) +{ + psa_set_key_type(attributes, type); +} + +/* + * ======== KeyStore_PSA_setKeyBits ======== + */ +void KeyStore_PSA_setKeyBits(KeyStore_PSA_KeyAttributes *attributes, size_t bits) +{ + psa_set_key_bits(attributes, bits); +} + +/* + * ======== KeyStore_PSA_getKeyType ======== + */ +KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_type(attributes); +} + +/* + * ======== KeyStore_PSA_getKeyBits ======== + */ +size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_bits(attributes); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h new file mode 100644 index 00000000..61525e2d --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h @@ -0,0 +1,1787 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file CryptoKeyKeyStore_PSA.h + * @brief CryptoKeyKeyStore_PSA driver header + * + * @warning This is a beta API. It may change in future releases. + * + * # Overview # + * This file contains the APIs to import, export, copy, and destroy key store + * CryptoKeys. Key store CryptoKeys reference keying material stored in flash or + * RAM using a key identifier. These CryptoKeys are subject to enforced usage + * restrictions as defined by the key attributes assigned during key import. + * This file provides definitions that are common between the Non-Secure + * Processing Environment (NSPE) and Secure Processing Environment (SPE). + * + * # Usage # + * + * After calling the key store initialization function, a CryptoKey must be + * imported into the key store before it can be used for a crypto operation APIs + * which takes a CryptoKey as an input. + + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_Example + * + * ## Importing and exporting AES-CCM KeyStore keys # + * + * @code + * + * #include + * #include + * .... + * + * uint8_t keyingMaterial[16]; //Assume keying material is already available + * uint8_t keyingMaterial2[16]; + * CryptoKey cryptoKey; + * KeyStore_PSA_KeyFileId keyID; + * int_fast16_t status; + * int_fast16_t returnedLength; + * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * + * // Assign key attributes. + * KeyStore_PSA_setKeyUsageFlags(&attributes, (KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT)); + * KeyStore_PSA_setKeyAlgorithm(&attributes, KEYSTORE_PSA_ALG_CCM); + * KeyStore_PSA_setKeyType(&attributes, KEYSTORE_PSA_KEY_TYPE_AES); + * KeyStore_PSA_setKeyLifetime(&attributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); + * GET_KEY_ID(keyID,KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) + * KeyStore_PSA_setKeyId(&attributes, keyID); + * + * // Import the keyingMaterial + * status = KeyStore_PSA_importKey(&attributes, keyingMaterial, sizeof(keyingMaterial), &keyID); + * + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * + * //Initialize the cryptoKey + * KeyStore_PSA_initKey(&cryptoKey, keyID, sizeof(keyingMaterial), NULL); + * + * // Export the previously imported CryptoKey using keyID + * status = KeyStore_PSA_exportKey(keyID, keyingMaterial2, sizeof(keyingMaterial2), &returnedLength); + * + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * + * // Destroy key after use + * status = KeyStore_PSA_destroyKey(keyID); + * + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * @endcode + * + */ + +#ifndef ti_drivers_CryptoKeyKeyStore_PSA__include +#define ti_drivers_CryptoKeyKeyStore_PSA__include + +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + #include + #include + #include +#else + #include +#endif /* #if (TFM_ENABLED == 0) || defined(TFM_BUILD) */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Encoding of permitted usage on a key. */ +typedef psa_key_usage_t KeyStore_PSA_KeyUsage; + +/** Encoding of key lifetimes. + * + * The lifetime of a key indicates where it is stored and what system + * actions may create and destroy it. + * + * Keys with the lifetime #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE are automatically + * destroyed when the application terminates or on a power reset. + * + * Keys with a lifetime other than #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE are said + * to be _persistent_. + * Persistent keys are preserved if the application or the system restarts. + */ +typedef psa_key_lifetime_t KeyStore_PSA_KeyLifetime; + +/** @defgroup KeyStore_PSA_Statuses Key Store status return values. + */ +/** The action was completed successfully. */ +#define KEYSTORE_PSA_STATUS_SUCCESS ((int_fast16_t)PSA_SUCCESS) + +/** An error occurred that does not correspond to any defined + * failure cause. + * + * Implementations may use this error code if none of the other standard + * error codes are applicable. */ +#define KEYSTORE_PSA_STATUS_GENERIC_ERROR ((int_fast16_t)PSA_ERROR_GENERIC_ERROR) + +/** The requested operation or a parameter is not supported + * by this implementation. + * + * Implementations should return this error code when an enumeration + * parameter such as a key type, algorithm, etc. is not recognized. + * If a combination of parameters is recognized and identified as + * not valid, return #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT instead. */ +#define KEYSTORE_PSA_STATUS_NOT_SUPPORTED ((int_fast16_t)PSA_ERROR_NOT_SUPPORTED) + +/** The requested action is denied by a policy. + * + * Implementations should return this error code when the parameters + * are recognized as valid and supported, and a policy explicitly + * denies the requested operation. + * + * If a subset of the parameters of a function call identify a + * forbidden operation, and another subset of the parameters are + * not valid or not supported, it is unspecified whether the function + * returns #KEYSTORE_PSA_STATUS_NOT_PERMITTED, #KEYSTORE_PSA_STATUS_NOT_SUPPORTED or + * #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT. */ +#define KEYSTORE_PSA_STATUS_NOT_PERMITTED ((int_fast16_t)PSA_ERROR_NOT_PERMITTED) + +/** The key ID is not valid or does not exist. + */ +#define KEYSTORE_PSA_STATUS_INVALID_KEY_ID ((int_fast16_t)PSA_ERROR_INVALID_HANDLE) + +/** An output buffer is too small. + * + * Applications can call the @c PSA_xxx_SIZE macro listed in the function + * description to determine a sufficient buffer size. + * + * Implementations should preferably return this error code only + * in cases when performing the operation with a larger output + * buffer would succeed. However implementations may return this + * error if a function has invalid or unsupported parameters in addition + * to the parameters that determine the necessary output buffer size. */ +#define KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL ((int_fast16_t)PSA_ERROR_BUFFER_TOO_SMALL) + +/** Asking for an item that already exists + * + * Implementations should return this error, when attempting + * to write an item (like a key) that already exists. */ +#define KEYSTORE_PSA_STATUS_ALREADY_EXISTS ((int_fast16_t)PSA_ERROR_ALREADY_EXISTS) + +/** Asking for an item that doesn't exist + * + * Implementations should return this error, if a requested item (like + * a key) does not exist. */ +#define KEYSTORE_PSA_STATUS_DOES_NOT_EXIST ((int_fast16_t)PSA_ERROR_DOES_NOT_EXIST) + +/** The requested action cannot be performed in the current state. + * + * Multipart operations return this error when one of the + * functions is called out of sequence. Refer to the function + * descriptions for permitted sequencing of functions. + * + * Implementations shall not return this error code to indicate that a key + * either exists or not, but shall instead return + * #KEYSTORE_PSA_STATUS_ALREADY_EXISTS or #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST as + * applicable. + * + * Implementations shall not return this error code to indicate that a + * key ID is invalid, but shall return #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * instead. */ +#define KEYSTORE_PSA_STATUS_BAD_STATE ((int_fast16_t)PSA_ERROR_BAD_STATE) + +/** The parameters passed to the function are invalid. + * + * Implementations may return this error any time a parameter or + * combination of parameters are recognized as invalid. + * + * Implementations shall not return this error code to indicate that a + * key ID is invalid, but shall return #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * instead. + */ +#define KEYSTORE_PSA_STATUS_INVALID_ARGUMENT ((int_fast16_t)PSA_ERROR_INVALID_ARGUMENT) + +/** There is not enough runtime memory. + * + * If the action is carried out across multiple security realms, this + * error can refer to available memory in any of the security realms. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY ((int_fast16_t)PSA_ERROR_INSUFFICIENT_MEMORY) + +/** There is not enough persistent storage. + * + * Functions that modify the key storage return this error code if + * there is insufficient storage space on the host media. In addition, + * many functions that do not otherwise access storage may return this + * error code if the implementation requires a mandatory log entry for + * the requested action and the log storage space is full. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE ((int_fast16_t)PSA_ERROR_INSUFFICIENT_STORAGE) + +/** There was a communication failure inside the implementation. + * + * This can indicate a communication failure between the application + * and an external cryptoprocessor or between the cryptoprocessor and + * an external volatile or persistent memory. A communication failure + * may be transient or permanent depending on the cause. + * + * @warning If a function returns this error, it is undetermined + * whether the requested action has completed or not. Implementations + * should return #KEYSTORE_PSA_STATUS_SUCCESS on successful completion + * whenever possible, however functions may return + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE if the requested action was completed + * successfully in an external cryptoprocessor but there was a breakdown of + * communication before the cryptoprocessor could report the status to the + * application. + */ +#define KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE ((int_fast16_t)PSA_ERROR_COMMUNICATION_FAILURE) + +/** There was a storage failure that may have led to data loss. + * + * This error indicates that some persistent storage is corrupted. + * It should not be used for a corruption of volatile memory + * (use #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED), for a communication error + * between the cryptoprocessor and its external storage (use + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE), or when the storage is + * in a valid state but is full (use #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE). + * + * Note that a storage failure does not indicate that any data that was + * previously read is invalid. However this previously read data may no + * longer be readable from storage. + * + * When a storage failure occurs, it is no longer possible to ensure + * the global integrity of the keystore. Depending on the global + * integrity guarantees offered by the implementation, access to other + * data may or may not fail even if the data is still readable but + * its integrity cannot be guaranteed. + * + * Implementations should only use this error code to report a + * permanent storage corruption. However application writers should + * keep in mind that transient errors while reading the storage may be + * reported using this error code. */ +#define KEYSTORE_PSA_STATUS_STORAGE_FAILURE ((int_fast16_t)PSA_ERROR_STORAGE_FAILURE) + +/** A hardware failure was detected. + * + * A hardware failure may be transient or permanent depending on the + * cause. */ +#define KEYSTORE_PSA_STATUS_HARDWARE_FAILURE ((int_fast16_t)PSA_ERROR_HARDWARE_FAILURE) + +/** There is not enough entropy to generate random data needed + * for the requested action. + * + * This error indicates a failure of a hardware random generator. + * Application writers should note that this error can be returned not + * only by functions whose purpose is to generate random data, such + * as key, IV or nonce generation, but also by functions that execute + * an algorithm with a randomized result, as well as functions that + * use randomization of intermediate computations as a countermeasure + * to certain attacks. + * + * Implementations should avoid returning this error after KeyStore_PSA_init() + * has succeeded. Implementations should generate sufficient + * entropy during initialization and subsequently use a cryptographically + * secure pseudorandom generator (PRNG). However implementations may return + * this error at any time if a policy requires the PRNG to be reseeded + * during normal operation. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_ENTROPY ((int_fast16_t)PSA_ERROR_INSUFFICIENT_ENTROPY) + +/** A tampering attempt was detected. + * + * If an application receives this error code, there is no guarantee + * that previously accessed or computed data was correct and remains + * confidential. Applications should not perform any security function + * and should enter a safe failure state. + * + * Implementations may return this error code if they detect an invalid + * state that cannot happen during normal operation and that indicates + * that the implementation's security guarantees no longer hold. Depending + * on the implementation architecture and on its security and safety goals, + * the implementation may forcibly terminate the application. + * + * This error code is intended as a last resort when a security breach + * is detected and it is unsure whether the keystore data is still + * protected. Implementations shall only return this error code + * to report an alarm from a tampering detector, to indicate that + * the confidentiality of stored data can no longer be guaranteed, + * or to indicate that the integrity of previously returned data is now + * considered compromised. Implementations shall not use this error code + * to indicate a hardware failure that merely makes it impossible to + * perform the requested operation (use #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE, + * #KEYSTORE_PSA_STATUS_STORAGE_FAILURE, #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE or other + * applicable error code instead). + * + * This error indicates an attack against the application. Implementations + * shall not return this error code as a consequence of the behavior of + * the application itself. */ +#define KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED ((int_fast16_t)PSA_ERROR_CORRUPTION_DETECTED) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * KeyStore driver implementation may have limitations on how + * many clients can simultaneously perform operations on the same key. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ + +#define KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-250) + +/** @brief Encoding of a key type. + */ +typedef psa_key_type_t KeyStore_PSA_KeyType; + +/** Raw data. + * + * A "key" of this type cannot be used for any cryptographic operation. + * Applications may use this type to store arbitrary data in the keystore. */ +#define KEYSTORE_PSA_KEY_TYPE_RAW_DATA ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RAW_DATA) + +/** HMAC key. + * + * The key policy determines which underlying hash algorithm the key can be + * used for. + * + * HMAC keys should generally have the same size as the underlying hash. */ +#define KEYSTORE_PSA_KEY_TYPE_HMAC ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_HMAC) + +/** A secret for key derivation. + * + * The key policy determines which key derivation algorithm the key + * can be used for. + */ +#define KEYSTORE_PSA_KEY_TYPE_DERIVE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_DERIVE) + +/** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. + * + * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or + * 32 bytes (AES-256). + */ +#define KEYSTORE_PSA_KEY_TYPE_AES ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_AES) + +/** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). + * + * The size of the key can be 64 bits (single DES), 128 bits (2-key 3DES) or + * 192 bits (3-key 3DES). + * + * Note that single DES and 2-key 3DES are weak and strongly + * deprecated and should only be used to decrypt legacy data. 3-key 3DES + * is weak and deprecated and should only be used in legacy protocols. + */ +#define KEYSTORE_PSA_KEY_TYPE_DES ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_DES) + +/** Key for a cipher, AEAD or MAC algorithm based on the + * Camellia block cipher. */ +#define KEYSTORE_PSA_KEY_TYPE_CAMELLIA ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_CAMELLIA) + +/** Key for the RC4 stream cipher. + * + * Note that RC4 is weak and deprecated and should only be used in + * legacy protocols. */ +#define KEYSTORE_PSA_KEY_TYPE_ARC4 ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ARC4) + +/** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. + * + * ChaCha20 and the ChaCha20_Poly1305 construction are defined in RFC 7539. + * + * Implementations must support 12-byte nonces, may support 8-byte nonces, + * and should reject other sizes. + */ +#define KEYSTORE_PSA_KEY_TYPE_CHACHA20 ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_CHACHA20) + +/** RSA public key. + * + * The size of an RSA key is the bit size of the modulus. + */ +#define KEYSTORE_PSA_KEY_TYPE_RSA_PUBLIC_KEY ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RSA_PUBLIC_KEY) +/** RSA key pair (private and public key). + * + * The size of an RSA key is the bit size of the modulus. + */ +#define KEYSTORE_PSA_KEY_TYPE_RSA_KEY_PAIR ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RSA_KEY_PAIR) +/** Whether a key type is an RSA key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_RSA(type) (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) + +#define KEYSTORE_PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) +#define KEYSTORE_PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ECC_KEY_PAIR_BASE) + +/** A low-entropy secret for password hashing or key derivation. + * + * This key type is suitable for passwords and passphrases which are typically + * intended to be memorizable by humans, and have a low entropy relative to + * their size. It can be used for randomly generated or derived keys with + * maximum or near-maximum entropy, but #KEYSTORE_PSA_KEY_TYPE_PASSWORD is more suitable + * for such keys. It is not suitable for passwords with extremely low entropy, + * such as numerical PINs. + * + * The key policy determines which key derivation algorithm the key can be + * used for. + */ +#define KEYSTORE_PSA_KEY_TYPE_PASSWORD ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_PASSWORD) + +/** A secret value that can be used to verify a password hash. + * + * The key policy determines which key derivation algorithm the key + * can be used for, among the same permissible subset as for + * #KEYSTORE_PSA_KEY_TYPE_PASSWORD. + */ +#define KEYSTORE_PSA_KEY_TYPE_PASSWORD_HASH ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_PASSWORD_HASH) + +/** @brief Encoding of a cryptographic algorithm. + * + * For algorithms that can be applied to multiple key types, this type + * does not encode the key type. For example, for symmetric ciphers + * based on a block cipher, #KeyStore_PSA_Algorithm encodes the block cipher + * mode and the padding mode while the block cipher itself is encoded + * via #KeyStore_PSA_KeyType. + */ +typedef psa_algorithm_t KeyStore_PSA_Algorithm; + +/** SHA2-224 */ +#define KEYSTORE_PSA_ALG_SHA_224 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_224) +/** SHA2-256 */ +#define KEYSTORE_PSA_ALG_SHA_256 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_256) +/** SHA2-384 */ +#define KEYSTORE_PSA_ALG_SHA_384 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_384) +/** SHA2-512 */ +#define KEYSTORE_PSA_ALG_SHA_512 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512) +/** SHA2-512/224 */ +#define KEYSTORE_PSA_ALG_SHA_512_224 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512_224) +/** SHA2-512/256 */ +#define KEYSTORE_PSA_ALG_SHA_512_256 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512_256) + +/** The CBC-MAC construction over a block cipher + * + * @warning CBC-MAC is insecure in many cases. + * A more secure mode, such as #KEYSTORE_PSA_ALG_CMAC, is recommended. + */ +#define KEYSTORE_PSA_ALG_CBC_MAC ((KeyStore_PSA_Algorithm)PSA_ALG_CBC_MAC) +/** The CMAC construction over a block cipher */ +#define KEYSTORE_PSA_ALG_CMAC ((KeyStore_PSA_Algorithm)PSA_ALG_CMAC) + +/** The CTR stream cipher mode. + * + * CTR is a stream cipher which is built from a block cipher. + * The underlying block cipher is determined by the key type. + * For example, to use AES-128-CTR, use this algorithm with + * a key of type #KEYSTORE_PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). + */ +#define KEYSTORE_PSA_ALG_CTR ((KeyStore_PSA_Algorithm)PSA_ALG_CTR) + +/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. + * + * \warning ECB mode does not protect the confidentiality of the encrypted data + * except in extremely narrow circumstances. It is recommended that applications + * only use ECB if they need to construct an operating mode that the + * implementation does not provide. Implementations are encouraged to provide + * the modes that applications need in preference to supporting direct access + * to ECB. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths are a + * multiple of the block size of the chosen block cipher. + */ +#define KEYSTORE_PSA_ALG_ECB_NO_PADDING ((KeyStore_PSA_Algorithm)PSA_ALG_ECB_NO_PADDING) + +/** The CBC block cipher chaining mode, with no padding. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths + * are whole number of blocks for the chosen block cipher. + */ +#define KEYSTORE_PSA_ALG_CBC_NO_PADDING ((KeyStore_PSA_Algorithm)PSA_ALG_CBC_NO_PADDING) + +/** The CCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define KEYSTORE_PSA_ALG_CCM ((KeyStore_PSA_Algorithm)PSA_ALG_CCM) + +/** The GCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define KEYSTORE_PSA_ALG_GCM ((KeyStore_PSA_Algorithm)PSA_ALG_GCM) + +/** The Chacha20-Poly1305 AEAD algorithm. + * + * The ChaCha20_Poly1305 construction is defined in RFC 7539. + * + * Implementations must support 12-byte nonces, may support 8-byte nonces, + * and should reject other sizes. + * + * Implementations must support 16-byte tags and should reject other sizes. + */ +#define KEYSTORE_PSA_ALG_CHACHA20_POLY1305 ((KeyStore_PSA_Algorithm)PSA_ALG_CHACHA20_POLY1305) + +/** The elliptic curve Diffie-Hellman (ECDH) key agreement algorithm. + * + * The shared secret produced by key agreement is the x-coordinate of + * the shared secret point. It is always `ceiling(m / 8)` bytes long where + * `m` is the bit size associated with the curve, i.e. the bit size of the + * order of the curve's coordinate field. When `m` is not a multiple of 8, + * the byte containing the most significant bit of the shared secret + * is padded with zero bits. The byte order is either little-endian + * or big-endian depending on the curve type. + * + * - For Montgomery curves (curve types `PSA_ECC_FAMILY_CURVEXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in little-endian byte order. + * The bit size is 448 for Curve448 and 255 for Curve25519. + * - For Weierstrass curves over prime fields (curve types + * `PSA_ECC_FAMILY_SECPXXX` and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m = ceiling(log_2(p))` for the field `F_p`. + * - For Weierstrass curves over binary fields (curve types + * `PSA_ECC_FAMILY_SECTXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m` for the field `F_{2^m}`. + */ +#define KEYSTORE_PSA_ALG_ECDH ((KeyStore_PSA_Algorithm)PSA_ALG_ECDH) + +/** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. */ +#define KEYSTORE_PSA_ALG_PAKE ((KeyStore_PSA_Algorithm)PSA_ALG_JPAKE) + +/* The encoding of curve identifiers is currently aligned with the + * TLS Supported Groups Registry (formerly known as the + * TLS EC Named Curve Registry) + * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 + * The values are defined by RFC 8422 and RFC 7027. */ +#define KEYSTORE_PSA_ECC_CURVE_SECT163K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT163R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT163R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECT193R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT193R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECT233K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT233R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT239K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT283K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT283R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT409K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT409R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT571K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT571R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECP192K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP192R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP224K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP224R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP256K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP256R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP384R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP521R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTRORE_ECC_CURVE_BRAINPOOL_P256R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +#define KEYSTRORE_ECC_CURVE_BRAINPOOL_P384R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +#define KEYSTRORE_ECC_CURVE_BRAINPOOL_P512R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +/** Cur KEYSTRORE_ECC_CURVE_SECPv((KeyStore_PSA_KeyType)e25519. + * + * This is the curve defined in Bernstein et al., + * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. + * The algorithm #KEYSTORE_PSA_ALG_ECDH performs X25519 when used with this curve. + */ +#define KEYSTORE_PSA_ECC_CURVE_CURVE25519 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_MONTGOMERY) +/** Curve448 + * + * This is the curve defined in Hamburg, + * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. + * The algorithm #KEYSTORE_PSA_ALG_ECDH performs X448 when used with this curve. + */ +#define KEYSTORE_PSA_ECC_CURVE_CURVE448 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_MONTGOMERY) + +/** Minimum value for a vendor-defined ECC curve identifier + * + * The range for vendor-defined curve identifiers is a subset of the IANA + * registry private use range, `0xfe00` - `0xfeff`. + */ +#define KEYSTORE_PSA_ECC_CURVE_VENDOR_MIN ((KeyStore_PSA_KeyType)PSA_ECC_CURVE_VENDOR_MIN) +/** Maximum value for a vendor-defined ECC curve identifier + * + * The range for vendor-defined curve identifiers is a subset of the IANA + * registry private use range, `0xfe00` - `0xfeff`. + */ +#define KEYSTORE_PSA_ECC_CURVE_VENDOR_MAX ((KeyStore_PSA_KeyType)PSA_ECC_CURVE_VENDOR_MAX) + +/* Volatile Key Limit [PSA_KEY_ID_VOLATILE_MIN, PSA_KEY_ID_VOLATILE_MAX] + * Upper limit for volatile key ID, PSA_KEY_ID_VOLATILE_MAX, is PSA_KEY_ID_VENDOR_MAX. + * Lower limit for volatile key ID, KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, is the last + * #MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of provided by implementation reserved for vendors. + */ + +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MIN + #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MAX +#else + /* + * PSA_KEY_SLOT_COUNT is not available in TF-M's crypto.h so we must + * hardcode it to match the value in mbedCrypto's header. + */ + #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID (PSA_KEY_ID_VENDOR_MAX - MBEDTLS_PSA_KEY_SLOT_COUNT + 1) + #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VENDOR_MAX +#endif + +/* Macro to obtain size of struct member */ +#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member) + +/** \defgroup key_lifetimes Key lifetimes + * @{ + */ + +/** A volatile key only exists as long as the handle to it is not closed. + * The key material is guaranteed to be erased on a power reset. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_VOLATILE ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_VOLATILE) + +/** The default storage area for persistent keys. + * + * A persistent key remains in storage until it is explicitly destroyed or + * until the corresponding storage area is wiped. This specification does + * not define any mechanism to wipe a storage area, but implementations may + * provide their own mechanism (for example to perform a factory reset, + * to prepare for device refurbishment, or to uninstall an application). + * + * This lifetime value is the default storage area for the calling + * application. Implementations may offer other storage areas designated + * by other lifetime values as implementation-specific extensions. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_PERSISTENT) + +/** The null key identifier. + */ +#define KEYSTORE_PSA_KEY_ID_NULL ((KeyStore_PSA_KeyFileId)0x0) + +/** The minimum value for a key identifier chosen by the application. + */ +#define KEYSTORE_PSA_KEY_ID_USER_MIN ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_USER_MIN) + +/** The minimum value for a persistent key identifier chosen by the application. + */ +#define KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN 0x41 + +/** The maximum value for a persistent key identifier with associated certificate chosen by the application. + * KeyStore uses Bit 29 in KeyID to indicate certificate storage. + * Application may choose any key ID less than 2^29 for persistent keys + * Persistent Key ID limit [KEYSTORE_PSA_MAX_VOLATILE_KEY_ID + 1, KEYSTORE_PSA_KEY_ID_USER_MIN] + * (Setting bit 30 makes KeyID greater than PSA_KEY_ID_USER_MIN which will fall into VENDOR limit) + * (Setting bit 31 makes KeyID greater than PSA_KEY_ID_VENDOR_MAX which is not a valid KeyID) + */ +#define KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX 0x1fffffff + +/** + * @brief Bit mask to set 29th bit to indicate certificate storage + * + */ +#define KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT (1 << 29) + +/** The minimum value for a key identifier chosen by the implementation. + */ +#define KEYSTORE_PSA_KEY_ID_VENDOR_MIN ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_VENDOR_MIN) + +/** The maximum value for a key identifier chosen by the implementation. + */ +#define KEYSTORE_PSA_KEY_ID_VENDOR_MAX ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_VENDOR_MAX) + +/** Default Key Owner + */ +#define KEYSTORE_PSA_DEFAULT_OWNER MBEDTLS_PSA_CRYPTO_KEY_ID_DEFAULT_OWNER + +/**@}*/ + +/** \defgroup key_policies Key policies + * @{ + */ + +/** Whether the key may be exported. + * + * A public key or the public part of a key pair may always be exported + * regardless of the value of this permission flag. + * + * If a key does not have export permission, implementations shall not + * allow the key to be exported in plain form from the cryptoprocessor, + * whether through KeyStore_PSA_exportKey() or through a proprietary interface. + * The key may however be exportable in a wrapped form, i.e. in a form + * where it is encrypted by another key. + */ +#define KEYSTORE_PSA_KEY_USAGE_EXPORT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_EXPORT) + +/** Whether the key may be copied. + * + * This flag allows the use of KeyStore_PSA_copyKey() to make a copy of the key + * with the same policy or a more restrictive policy. + * + * For lifetimes for which the key is located in a secure element which + * enforce the non-exportability of keys, copying a key outside the secure + * element also requires the usage flag #KEYSTORE_PSA_KEY_USAGE_EXPORT. + * Copying the key inside the secure element is permitted with just + * #KEYSTORE_PSA_KEY_USAGE_COPY if the secure element supports it. + * For keys with the lifetime #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE or + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT, the usage flag #KEYSTORE_PSA_KEY_USAGE_COPY + * is sufficient to permit the copy. + */ +#define KEYSTORE_PSA_KEY_USAGE_COPY ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_COPY) + +/** Whether the key may be used to encrypt a message. + * + * This flag allows the key to be used for a symmetric encryption operation, + * for an AEAD encryption-and-authentication operation, + * or for an asymmetric encryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_ENCRYPT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_ENCRYPT) + +/** Whether the key may be used to decrypt a message. + * + * This flag allows the key to be used for a symmetric decryption operation, + * for an AEAD decryption-and-verification operation, + * or for an asymmetric decryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_DECRYPT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_DECRYPT) + +/** Whether the key may be used to sign a message. + * + * This flag allows the key to be used for a MAC calculation operation or for + * an asymmetric message signature operation, if otherwise permitted by the + * keys type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_SIGN_MESSAGE) + +/** Whether the key may be used to verify a message. + * + * This flag allows the key to be used for a MAC verification operation or for + * an asymmetric message signature verification operation, if otherwise + * permitted by the keys type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_VERIFY_MESSAGE) + +/** Whether the key may be used to sign a message hash. + * + * This flag allows the key to be used for an asymmetric signature operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_SIGN_HASH ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_SIGN_HASH) + +/** Whether the key may be used to verify a message hash. + * + * This flag allows the key to be used for an asymmetric signature verification operation, + * if otherwise permitted by by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_VERIFY_HASH) + +/** Whether the key may be used to derive other keys. + */ +#define KEYSTORE_PSA_KEY_USAGE_DERIVE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_DERIVE) +/**@}*/ + +/** \defgroup attributes Key attributes + * @{ + */ +/** The type of a structure containing key attributes. + * + * This is an opaque structure that can represent the metadata of a key + * object. Metadata that can be stored in attributes includes: + * - The location of the key in storage, indicated by its key identifier + * and its lifetime. + * - The key's policy, comprising usage flags and a specification of + * the permitted algorithm(s). + * - Information about the key itself: the key type and its size. + * + * The actual key material is not considered an attribute of a key. + * Key attributes do not contain information that is generally considered + * highly confidential. + * + * An attribute structure can be a simple data structure where each function + * `KeyStore_PSA_setKeyXXX` sets a field and the corresponding function + * `KeyStore_PSA_getKeyXXX` retrieves the value of the corresponding field. + * However, implementations may report values that are equivalent to the + * original one, but have a different encoding. For example, an + * implementation may use a more compact representation for types where + * many bit-patterns are invalid or not supported, and store all values + * that it does not support as a special marker value. In such an + * implementation, after setting an invalid value, the corresponding + * get function returns an invalid value which may not be the one that + * was originally stored. + * + * An attribute structure may contain references to auxiliary resources, + * for example pointers to allocated memory or indirect references to + * pre-calculated values. In order to free such resources, the application + * must call KeyStore_PSA_resetKeyAttributes(). As an exception, calling + * KeyStore_PSA_resetKeyAttributes() on an attribute structure is optional if + * the structure has only been modified by the following functions + * since it was initialized or last reset with + * KeyStore_PSA_resetKeyAttributes(): + * - KeyStore_PSA_setKeyId() + * - KeyStore_PSA_setKeyLifetime() + * - KeyStore_PSA_setKeyType() + * - KeyStore_PSA_setKeyBits() + * - KeyStore_PSA_setKeyUsageFlags() + * - KeyStore_PSA_setKeyAlgorithm() + * + * Before calling any function on a key attribute structure, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * KeyStore_PSA_KeyAttributes attributes; + * memset(&attributes, 0, sizeof(attributes)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * KeyStore_PSA_KeyAttributes attributes = {0}; + * \endcode + * - Initialize the structure to the initializer + * #KEYSTORE_PSA_KEY_ATTRIBUTES_INIT, for example: \code + * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * \endcode + * + * A freshly initialized attribute structure contains the following + * values: + * + * - lifetime: #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE. + * - key identifier: @c 0 (which is not a valid key identifier). + * - type: @c 0 (meaning that the type is unspecified). + * - key size: @c 0 (meaning that the size is unspecified). + * - usage flags: @c 0 (which allows no usage except exporting a public + * key). + * - algorithm: @c 0 (which allows no cryptographic usage, but allows + * exporting). + * + * A typical sequence to create a key is as follows: + * -# Create and initialize an attribute structure. + * -# If the key is persistent, call KeyStore_PSA_setKeyId(). + * Also call KeyStore_PSA_setKeyLifetime() to place the key in a non-default + * location. + * -# Set the key policy with KeyStore_PSA_setKeyUsageFlags() and + * KeyStore_PSA_setKeyAlgorithm(). + * -# Set the key type with KeyStore_PSA_setKeyType(). + * -# When generating a random key with KeyStore_PSA_generateKey() or deriving a + * key with KeyStore_PSA_key_derivation_output_key(), set the desired key size + * with KeyStore_PSA_setKeyBits(). + * -# Call a key creation function: KeyStore_PSA_importKey(), + * KeyStore_PSA_generateKey(), KeyStore_PSA_key_derivation_output_key(). This + * function reads the attribute structure, creates a key with these + * attributes, and outputs a handle to the newly created key. + * -# The attribute structure is now no longer necessary. + * You may call KeyStore_PSA_resetKeyAttributes(), although this is optional + * with the workflow presented here because the attributes currently + * defined in this specification do not require any additional resources + * beyond the structure itself. + * + * A typical sequence to query a key's attributes is as follows: + * -# Call KeyStore_PSA_getKeyAttributes(). + * -# Call `KeyStore_PSA_get_key_xxx` functions to retrieve the attribute(s) + * that you are interested in. + * -# Call KeyStore_PSA_resetKeyAttributes() to free any resources that may be + * used by the attribute structure. + * + * Once a key has been created, it is impossible to change its attributes. + */ +typedef psa_key_attributes_t KeyStore_PSA_KeyAttributes; +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + /** A Key owner is a PSA partition identifier. This definition follow + * 'psa_key_owner_id_t' from crypto_platform.h */ + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) +/* Building for the PSA Crypto service on a PSA platform. */ +/* A key owner is a PSA partition identifier. */ +typedef mbedtls_key_owner_id_t KeyStore_PSA_key_owner_id_t; + +typedef psa_key_id_t KeyStore_PSA_keyID; + #endif /* defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) */ + +typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; + + #define KEYSTORE_PSA_KEY_ATTRIBUTES_INIT PSA_KEY_ATTRIBUTES_INIT + + /** Macro to assign and get keyID + * + * It depends on MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER to assign keyID and + * owner if multiple partition supported by mbedtls + */ + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + #define GET_KEY_ID(keyID, ID) \ + keyID.MBEDTLS_PRIVATE(key_id) = ID; \ + keyID.MBEDTLS_PRIVATE(owner) = KEYSTORE_PSA_DEFAULT_OWNER; + + #define SET_KEY_ID(ID, keyID) ID = keyID.MBEDTLS_PRIVATE(key_id) + #else + #define GET_KEY_ID(keyID, ID) keyID = ID + + #define SET_KEY_ID(ID, keyID) ID = keyID + #endif /* defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) */ + +#else +/** Encoding of identifiers of persistent keys for client side. + * + * - Applications may freely choose key identifiers in the range + * #KEYSTORE_PSA_KEY_ID_USER_MIN to #KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX or + * #KEYSTORE_PSA_KEY_ID_WITHOUT_CERTIFICATE_USER_MAX. + * - Implementations may define additional key identifiers in the range + * #KEYSTORE_PSA_KEY_ID_VENDOR_MIN to #KEYSTORE_PSA_KEY_ID_VENDOR_MAX. + * - 0 is reserved as an invalid key identifier. + * - Key identifiers outside these ranges are reserved for future use. + */ +typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; + + /** Macro to assign and get keyID */ + #define GET_KEY_ID(keyID, ID) keyID = ID + #define SET_KEY_ID(ID, keyID) ID = keyID + + #define KEYSTORE_PSA_KEY_ATTRIBUTES_INIT PSA_CLIENT_KEY_ATTRIBUTES_INIT +#endif /* #if (TFM_ENABLED == 0) || defined(TFM_BUILD) */ +/**@}*/ + +/**@}*/ + +/** + * Starting address of Pre-provisioned keys. + * + * The Immutable platform Root of Trust stores the pre-provisioned key's programmed at + * production. SKS implementation will read this address to obtain the + * KeyStore_PSA_KeyFileId and other relevant meta data of all the pre-provisioned keys stored at this address + */ +#define KEYSTORE_PSA_PREPROVISIONED_AREA_ADDR 0x0000 +/** + * @brief Area size for pre-provisioned keys, 2KB - 256B (reserved for attestation data) + */ +#define KEYSTORE_PSA_PREPROVISIONED_AREA_SIZE (0x700) /* 1792 B */ + +/** + * @brief Exportable pre-provisioned key prefix + * + * Prefix the plaintext key in pre-provisioned key that can be exported to the non-secure application with this flag + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG 0xAAAA +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG)) +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_NO_EXPORT_FLAG 0xA5A5 + +/** + * @brief Macro to indicate empty pre-provisioned key memory + */ +#define KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY 0xFFFF + +/** + * @brief Pre-provisioned key storage magic header. + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER "HUK\0KEY" +#define KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END 0 +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER)) +#define KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END)) +#define KEYSTORE_PSA_MAX_PREPROVISIONED_KEYS 0x10 + +/** + * @brief Pre-provisioned key Lifetime + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_VALID_LIFETIME 0xAAAA +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_INVALID_LIFETIME 0x8888 + +/** + * @brief Admissible key ID range for Pre-provisioned keys + * + * 0x21 - 0x40 is reserved to store pre-provisioned keys. Correspondingly, 0x10000021 - 0x10000040 is reserved for any + * associated certificates. + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX 0x40 +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN 0x21 +#define KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MAX \ + (KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) +#define KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MIN \ + (KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) + +/** + * @brief Reserved pre-provisioned key IDs + * + * Some known pre-provisioned key used by attestation service have reserved key IDs in the admissible range for + * pre-provisioned keys + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PUB_KEY_ID 0x40 +#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PRI_KEY_ID 0X3F +#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_CERTIFICATE_ID \ + (KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PUB_KEY_ID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) + +/** + * @brief Structure for storing pre-provisioned key's meta data + * + * - header : magic header to indicate the start of the pre-provisioned key + * - id : key id (and its owner when applicable) + * - export : Flag that needs to be set with correct string to allow exporting to non-secure application + * - alg : Cryptographic algorithm permitted using this key + * - usage : Usage for the key as described the KeyStore API + * - keyLength : Length of the pre-provisioned key + */ +typedef struct +{ + uint8_t header[KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH]; + uint32_t lifetime; + KeyStore_PSA_KeyFileId id; + uint32_t export; + KeyStore_PSA_Algorithm alg; + KeyStore_PSA_KeyUsage usage; + uint32_t keyLength; +} KeyStore_PreProvisionedKeyMetaData; + +/** + * @brief Size of the meta data associated with the pre-provisoned key + */ +#define KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE sizeof(KeyStore_PreProvisionedKeyMetaData) + +/** + * @brief Structure for storing pre-provisioned keys and its meta data + * + * - meta : Structure to meta data associated with each pre-provisioned key + * - KeyMaterial : A pointer to the plaintext key material + * - fletcher : 32-bit Fletcher checksum over the pre-provisioned key and its meta data + */ +typedef struct +{ + KeyStore_PreProvisionedKeyMetaData meta; + uint8_t *keyMaterial; + uint32_t fletcher; +} KeyStore_preProvisionedKeyStorageFormat; + +/** + * @brief Initialize a KeyStore_preProvisionedKeyStorageFormat struct variable + */ +#define KEYSTORE_PSA_PREPROVISIONED_KEY_FORMAT_INIT \ + { \ + KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER, 0, KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG, 0, 0, 0, 0, \ + KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END, 0 \ + } + +/** + * @brief Structure for storing IDs of pre-provisioned keys + * + * Also stores minimal meta data required to import pre-provisioned keys from persistent memory + * + * - addr : Starting address of the plaintext key material in pre-provisioned key memory + * - id : Key ID (and its owner when applicable) + * - alg : Algorithm the key will be used for + * - usage : Key usage + * - export : Flag to indicate the exportability of of the pre-provisioned key + * - keyLength : Size of the pre-provisioned key + */ +typedef struct +{ + uint8_t *addr; + KeyStore_PSA_KeyFileId id; + KeyStore_PSA_Algorithm alg; + KeyStore_PSA_KeyUsage usage; + uint32_t export; + uint32_t keyLength; +} KeyStore_PSA_preProvisionedKeyIDs; + +/** + * @brief Declare a key as persistent and set its key identifier. + * + * If the attribute structure currently declares the key as volatile (which + * is the default content of an attribute structure), this function sets + * the lifetime attribute to #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * KeyStore_PSA_import_key(), KeyStore_PSA_generate_key(), + * KeyStore_PSA_key_derivation_output_key() or KeyStore_PSA_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param key The persistent identifier for the key. + */ +void KeyStore_PSA_setKeyId(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyFileId key); + +/** + * @brief Set the location of a persistent key. + * + * To make a key persistent, you must give it a persistent key identifier + * with KeyStore_PSA_setKeyId(). By default, a key that has a persistent + * identifier is stored in the default storage area identifier by + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT. Call this function to choose a storage + * area, or to explicitly declare the key as volatile. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * KeyStore_PSA_import_key(), KeyStore_PSA_generate_key(), + * KeyStore_PSA_key_derivation_output_key() or KeyStore_PSA_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param lifetime The lifetime for the key. + * If this is #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE, the + * key will be volatile, and the key identifier + * attribute is reset to 0. + */ +void KeyStore_PSA_setKeyLifetime(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyLifetime lifetime); + +/** + * @brief Retrieve the key identifier from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The persistent identifier stored in the attribute structure. + * This value is unspecified if the attribute structure declares + * the key as volatile. + */ +KeyStore_PSA_KeyFileId KeyStore_PSA_getKeyId(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Retrieve the lifetime from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The lifetime value stored in the attribute structure. + */ +KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare usage flags for a key. + * + * Usage flags are part of a key's usage policy. They encode what + * kind of operations are permitted on the key. For more details, + * refer to the documentation of the type #KeyStore_PSA_KeyUsage. + * + * This function overwrites any usage flags + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param usage_flags The usage flags to write. + */ +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usage_flags); + +/** + * @brief Retrieve the usage flags from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The usage flags stored in the attribute structure. + */ +KeyStore_PSA_KeyUsage KeyStore_PSA_getKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare the permitted algorithm policy for a key. + * + * The permitted algorithm policy of a key encodes which algorithm or + * algorithms are permitted to be used with this key. The following + * algorithm policies are supported: + * - 0 does not allow any cryptographic operation with the key. The key + * may be used for non-cryptographic actions such as exporting (if + * permitted by the usage flags). + * - An algorithm value permits this particular algorithm. + * + * This function overwrites any algorithm policy + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param alg The permitted algorithm policy to write. + */ +void KeyStore_PSA_setKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_Algorithm alg); + +/** + * @brief Retrieve the algorithm policy from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The algorithm stored in the attribute structure. + */ +KeyStore_PSA_Algorithm KeyStore_PSA_getKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare the type of a key. + * + * This function overwrites any key type + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param type The key type to write. + * If this is 0, the key type in @p attributes + * becomes unspecified. + */ +void KeyStore_PSA_setKeyType(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyType type); + +/** + * @brief Declare the size of a key. + * + * This function overwrites any key size previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param bits The key size in bits. + * If this is 0, the key size in @p attributes + * becomes unspecified. Keys of size 0 are + * not supported. + */ +void KeyStore_PSA_setKeyBits(KeyStore_PSA_KeyAttributes *attributes, size_t bits); + +/** + * @brief Retrieve the key type from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The key type stored in the attribute structure. + */ +KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attributes); + +/** @brief Retrieve the key size from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * \return The key size stored in the attribute structure, in bits. + */ +size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes); + +/** @brief Reset a key attribute structure to a freshly initialized state. + * + * You must initialize the attribute structure as described in the + * documentation of the type #KeyStore_PSA_KeyAttributes before calling this + * function. Once the structure has been initialized, you may call this + * function at any time. + * + * This function frees any auxiliary resources that the structure + * may contain. + * + * @param [in,out] attributes The attribute structure to reset. + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Export a certificate in binary format. + * + * The output of this function can be passed to KeyStore_PSA_importCertificate() + * to create an equivalent object. + * + * @param [in] key Key file ID of the key associated with the + * certificate to export. + * @param [out] data Buffer where the certificate data is to be written. + * @param [in] dataSize Size of the @p data buffer in bytes. + * @param [out] dataLength On success, the number + * of bytes that make up the certificate data. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL + * The size of the @p data buffer is too small. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength); + +/** + * @brief Export a public key or the public part of a key pair in binary + * format. + * + * The output of this function can be passed to KeyStore_PSA_importKey() to + * create an object that is equivalent to the public key. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * - For elliptic curve public keys, the format for: + * - Montgomery curves (curve types `PSA_ECC_CURVE_CURVEXXX`), is + * - `x_P` as a `ceiling(m/8)`-byte string, little-endian; + * - Weierstrass curves (curve types `PSA_ECC_CURVE_SECTXXX`, + * `PSA_ECC_CURVE_SECPXXX` and `PSA_ECC_CURVE_BRAINPOOL_PXXX`), is the + * uncompressed representation defined by SEC1 §2.3.3 as the content of + * an ECPoint. Let `m` be the bit size associated with the curve, i.e. the + * bit size of `q` for a curve over `F_q`. The representation consists of: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. + * - For Diffie-Hellman key exchange public keys, + * the format is the representation of the public key `y = g^x mod p` as a + * big-endian byte string. The length of the byte string is the length of + * the base prime `p` in bytes. + * + * Exporting a public key object or the public part of a key pair is + * always permitted, regardless of the key's usage flags. + * + * @param [in] key Key file ID of the key to export. + * @param [out] data Buffer where the key data is to be written. + * @param [in] dataSize Size of the @p data buffer in bytes. + * @param [out] dataLength On success, the number of bytes + * that make up the key data. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT + * The key is neither a public key nor a key pair. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL + * The size of the @p data buffer is too small. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength); + +/** + * @brief Export a key in binary format. + * + * The key must designated as exportable. The output of this function can be + * passed to KeyStore_PSA_importKey() to create an equivalent object. + * + * If the implementation of KeyStore_PSA_importKey() supports other formats + * beyond the format specified here, the output from KeyStore_PSA_exportKey() + * must use the representation specified here, not the original + * representation. + * + * For standard key types, the output format is as follows: + * + * - For symmetric keys (including MAC keys), the format is the + * raw bytes of the key. + * + * - For elliptic curve key pairs, the format is + * a representation of the private value as a `ceiling(m/8)`-byte string + * where `m` is the bit size associated with the curve, i.e. the bit size + * of the order of the curve's coordinate field. This byte string is + * in little-endian order for Montgomery curves (curve types + * `PSA_ECC_CURVE_CURVEXXX`), and in big-endian order for Weierstrass + * curves (curve types `PSA_ECC_CURVE_SECTXXX`, `PSA_ECC_CURVE_SECPXXX` + * and `PSA_ECC_CURVE_BRAINPOOL_PXXX`). + * This is the content of the `privateKey` field of the `ECPrivateKey` + * format defined by RFC 5915. + * - For Diffie-Hellman key exchange key pairs, the + * format is the representation of the private key `x` as a big-endian + * byte string. The length of the byte string is the private key size in + * bytes (leading zeroes are not stripped). + * - For public keys, the format is the same as for KeyStore_PSA_exportPublicKey(). + * + * The policy on the key must have the usage flag #KEYSTORE_PSA_KEY_USAGE_EXPORT + * set. + * + * @param [in] key Key file ID of the key to export. + * @param [out] data Buffer where the key data is to be written. + * @param [in] dataSize Size of the @p data buffer in bytes. + * @param [out] dataLength On success, the number of bytes + * that make up the key data. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key does not have the #KEYSTORE_PSA_KEY_USAGE_EXPORT flag. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL + * The size of the @p data buffer is too small. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength); + +/** + * @brief Import a certificate in binary format. + * + * This function supports the output from KeyStore_PSA_exportCertificate(). + * + * Multiple certificates cannot be imported for the same key ID. If an + * additional certificate needs to be associated with a particular key pair + * or public key, that key data must be imported again with a different key + * ID. Additionally, the key store does not interpret the contents of the + * certificate and cannot verify that the key embedded within the + * certificate matches the associated key. + * + * Implementations must reject an attempt to import a certificate of size 0. + * + * @param [in] attributes The attributes for the new certificate. + * The certificate size is always determined from + * the @p data buffer. If the certificate size in @p attributes is nonzero, + * it must be equal to the size from @p data. + * @param [out] key On success, the key file ID of the previously imported + * key associated with the certificate. @c 0 on failure. + * @param [in] data Buffer containing the certificate data in binary format. + * @param [in] dataLength Size of the @p data buffer in bytes. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the certificate is persistent, the certificate material and + * the certificate's metadata have been saved to persistent storage. + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_ALREADY_EXISTS This is an attempt to create a + * certificate, and there is already a certificate with the given + * identifier. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED The certificate type + * or certificate size is not supported, either by the implementation in + * general or in this particular persistent location. + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The certificate attributes, as a whole, + * are invalid. + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The certificate + * data is not correctly formatted. + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The size in @p attributes is nonzero + * and does not match the size of the certificate data. + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, + KeyStore_PSA_KeyFileId *key, + uint8_t *data, + size_t dataLength); + +/** + * @brief Import a key in binary format. + * + * This function supports any output from KeyStore_PSA_exportKey(). Refer to the + * documentation of KeyStore_PSA_exportPublicKey() for the format of public keys + * and to the documentation of KeyStore_PSA_exportKey() for the format for + * other key types. + * + * The dataLength determines the key size. The attributes may optionally + * specify a key size; in this case it must match the dataLength. A key + * size of 0 in @p attributes indicates that the key size is solely + * determined by the key data. + * + * Implementations must reject an attempt to import a key of size 0. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * @param [in] attributes The attributes for the new key. + * The key size is always determined from the + * @p data buffer. + * If the key size in @p attributes is nonzero, + * it must be equal to the size from @p data. + * @param [in] data Buffer containing the key data. The content of this + * buffer is interpreted according to the type declared + * in @p attributes. + * All implementations must support at least the format + * described in the documentation + * of KeyStore_PSA_exportKey() or KeyStore_PSA_exportPublicKey() + * for the chosen type. Implementations may allow other formats, but should + * be conservative: implementations should err on the side of rejecting + * content if it may be erroneous (e.g. wrong type or truncated data). + * @param [in] dataLength Size of the @p data buffer in bytes. + * @param [out] key On success, the key file ID of the newly created key. + * @c 0 on failure. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the key is persistent, the key material and the key's metadata + * have been saved to persistent storage. + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_ALREADY_EXISTS + * This is an attempt to create a key, and there is + * already a key with the given key file identifier. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * The key type or key size is not supported, either by the + * implementation in general or in this particular persistent + * location. @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The key attributes, + * as a whole, are invalid. @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The + * key data is not correctly formatted. @retval + * #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The size in @p attributes is nonzero + * and does not match the size of the key data. @retval + * #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY @retval + * #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE @retval + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE @retval + * #KEYSTORE_PSA_STATUS_STORAGE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key); + +/** @brief Retrieve the attributes of a key. + * + * This function first resets the attribute structure as with + * KeyStore_PSA_resetKeyAttributes(). It then copies the attributes of + * the given key into the given attribute structure. + * + * @note This function may allocate memory or other resources. + * Once you have called this function on an attribute structure, + * you must call KeyStore_PSA_resetKeyAttributes() to free these + * resources. + * + * @param [in] key Identifier of the key to query. + * @param [in,out] attributes On success, the attributes of the key. + * On failure, equivalent to a + * freshly-initialized structure. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_crypto_init(). It is implementation-dependent whether a failure + * to initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Remove non-essential copies of key material from memory. + * + * An implementation is permitted to make additional copies of key material + * for keys that have been created with the cache policy, an implementation + * is permitted to make additional copies of the key material that are not + * in storage and not for the purpose of ongoing operations. This function + * will remove these extra copies of the key material from memory. + * + * This function is not required to remove key material from memory in any + * of the following situations: + * - The key is currently in use in a cryptographic operation. + * - The key is volatile + * + * @param [in] key Key handle to close. . + * If this is @c 0, do nothing and return @c + * KEYSTORE_PSA_STATUS_SUCCESS. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @p Handle was valid and the key material that it + * referred to has been closed. + * Alternatively, @p Handle is @c 0. + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @p handle is not a valid handle nor @c 0. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * There was an failure in communication with the cryptoprocessor. + * The key material may still be present in the cryptoprocessor. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * The storage is corrupted. Implementations shall make a best + * effort to erase key material even in this stage, however applications + * should be aware that it may be impossible to guarantee that the + * key material is not recoverable in such cases. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * An unexpected condition which is not a storage corruption or + * a communication failure occurred. The cryptoprocessor may have + * been compromised. + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key); + +/** + * @brief Destroy a certificate associated with a key. + * + * This function destroys a certificate from both volatile + * memory and, if applicable, non-volatile storage. + * + * This function also erases any metadata such as policies and frees + * resources associated with the certificate. + * + * @param [in] key Key file ID of the key associated with certificate to + * erase. If key ID portion is @c 0, do nothing and return @c + * KEYSTORE_PSA_STATUS_SUCCESS. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @p ID was a valid ID and the certificate material that it + * referred to has been erased. + * Alternatively, @p ID is @c 0. + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The certificate cannot be erased because it is + * read-only, either due to a policy or due to physical + * restrictions. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID @p ID is not a validI D. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE There was an failure + * in communication with the cryptoprocessor. The certificate material may + * still be present in the cryptoprocessor. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE The storage is corrupted. + * Implementations shall make a best effort to erase certificate material + * even in this stage, however applications should be aware that it may be + * impossible to guarantee that the certificate material is not recoverable + * in such cases. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED An unexpected + * condition which is not a storage corruption or a communication failure + * occurred. The cryptoprocessor may have been compromised. + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE The library has not been previously + * initialized by KeyStore_PSA_init(). It is implementation-dependent whether a + * failure to initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key); + +/** + * @brief Destroy a key. + * + * This function destroys a key from both volatile memory and, if + * applicable, non-volatile storage. Implementations shall make a best + * effort to ensure that that the key material cannot be recovered. + * + * If the key has an associated certificate, KeyStore_PSA_destroyCertificate() + * must be called to destroy the certificate before destroying the key. + * + * This function also erases any metadata such as policies and frees + * resources associated with the key. + * + * Destroying the key makes the ID invalid, and the key ID must not be used + * again by the application. + * + * If a key is currently in use in a multipart operation, then destroying + * the key will cause the multipart operation to fail. + * + * After a volatile key is destroyed, it is recommended that the + * implementation does not immediately reuse the same key ID value for a + * different key. This reduces the risk of an attack that is able to exploit + * a key identifier reuse vulnerability within an application. + * + * @param [in] key Key file ID of the key to erase. + * If key ID portion is @c 0, do nothing and return @c + * KEYSTORE_PSA_STATUS_SUCCESS. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @p ID was a valid ID and the key material that it + * referred to has been erased. + * Alternatively, @p ID is @c 0. + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key cannot be erased because it has an associated certificate + * or is read-only, either due to a policy or due to physical restrictions. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @p ID is not a valid ID. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * There was an failure in communication with the cryptoprocessor. + * The key material may still be present in the cryptoprocessor. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * The storage is corrupted. Implementations shall make a best + * effort to erase key material even in this stage, however applications + * should be aware that it may be impossible to guarantee that the + * key material is not recoverable in such cases. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * An unexpected condition which is not a storage corruption or + * a communication failure occurred. The cryptoprocessor may have + * been compromised. + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_KeyStore_PSA__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c new file mode 100644 index 00000000..ec6feb4c --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c @@ -0,0 +1,895 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include /* tfm_its_init() */ + +#include +#include +#include + +/* Static buffer for alloc/free. The buffer size is allocated based on + * assumption of 16 largest symmetric keys (32B) and 16 largest asymmetric + * public keys (133B) that can be supported by KeyStore, with surplus bytes for + * additional calloc calls within mbedTLS. + */ +uint8_t allocBuffer[3072]; + +extern psa_status_t psa_get_and_lock_key_slot_with_policy(mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg); + +KeyStore_accessSemaphoreObject KeyStore_semaphoreObject = {.isAcquired = false, .isInitialized = false}; + +/** @brief Key handle identifier from mbedTLS 'psa_key_handle_t'. */ +typedef psa_key_handle_t KeyStore_PSA_KeyHandle; + +/** + * @brief Counter to keep track of the number of pre-provisioned keys available during KeyStore_PSA_init() + * + * preProvisionedKeyCount is set to the empty macro to indicate no provisioned keys and later initialized to the length + * of pre-provisioned key memory if pre-provisioned keys are available during initialization of the KeyStore driver. + */ +static uint32_t preProvisionedKeyCount; + +/** + * @brief Global array of pre-provisioned key IDs + * + * During KeyStore_PSA_init(), the pre-provisioned key memory is checked for the existence of pre-provisioned keys. If + * they exist, pre-provisioned key memory is parsed to copy the necessary information in the the preProvisionedKeyIds + * including the key ID, algorithm, usage, exportability, address of the plaintext material, and the key length. This + * array is later used to check the availability of a key in pre-provisioned key memory when an application or requests + * for the key using key ID. + */ +static KeyStore_PSA_preProvisionedKeyIDs preProvisionedKeyIds[KEYSTORE_PSA_MAX_PREPROVISIONED_KEYS]; + +/* Flag to prevent multiple initialization of KeyStore driver */ +static bool isKeyStoreInitialized = false; + +/** + * @brief Obtain pre-provisioned KeyStore_PSA_KeyFileId if any. + * + * This function is called by KeyStore_PSA_init() to parse the pre-provisioned key memory + * area and identify available key IDs and store the key IDs and other information along + * with the starting address of the key in pre-provisioned key memory in a global array. The application + * must provide the necessary key ID and owner information from this array to retrieve the key. + * + * \retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * \retval #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST + * No pre-provisioned key available in pre-provisioned key memory + */ +/* + * ======== KeyStore_PSA_getPreProvisionedKeyIDs ======== + */ +static int_fast16_t KeyStore_PSA_getPreProvisionedKeyIDs(void) +{ + uint8_t *currentKey; + uint32_t keySize; + uint32_t lifetime; + uint32_t keyLength; + uint32_t end; + + currentKey = (uint8_t *)(KEYSTORE_PSA_PREPROVISIONED_AREA_ADDR); + + /* Check for magic header to identify if pre-provisioned keys were programmed */ + if (memcmp(currentKey, + KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER, + KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH) != 0) + { + return KEYSTORE_PSA_STATUS_DOES_NOT_EXIST; + } + + /* Rest keySize (size of each key) and preProvisionedKeyCount (length of the pre-provisioned key array) */ + keySize = 0; + preProvisionedKeyCount = 0; + + /* + * Parse the pre-provisioned key memory until reaching the final end pattern for PP keys or empty pattern which + * allows further addition of pre-provisioned keys to create a local copy of the key ID, size, and starting address + * to be used by the application + */ + do + { + /* Skip the Magic Header */ + keySize = KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH; + + /* Copy Lifetime */ + memcpy(&lifetime, (currentKey + keySize), MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, lifetime)); + keySize += MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, lifetime); + + if (lifetime == KEYSTORE_PSA_PRE_PROVISIONED_KEY_VALID_LIFETIME) + { + /* Copy the Key_file_id_t */ + memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].id), + (currentKey + keySize), + sizeof(KeyStore_PSA_KeyFileId)); + keySize += sizeof(KeyStore_PSA_KeyFileId); + + /* Copy the export flag */ + memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].export), + (currentKey + keySize), + sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG)); + keySize += sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG); + + /* Copy the Algorithm */ + memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].alg), + (currentKey + keySize), + sizeof(KeyStore_PSA_Algorithm)); + keySize += sizeof(KeyStore_PSA_Algorithm); + + /* Copy the Usage */ + memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].usage), + (currentKey + keySize), + sizeof(KeyStore_PSA_KeyUsage)); + keySize += sizeof(KeyStore_PSA_KeyUsage); + + /* Copy the key length */ + memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].keyLength), + (currentKey + keySize), + MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength)); + keySize += MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength); + + /* Copy the starting addr of pre-provisioned key psa_key */ + preProvisionedKeyIds[preProvisionedKeyCount].addr = currentKey + keySize; + + keySize += (preProvisionedKeyIds[preProvisionedKeyCount].keyLength + + MEMBER_SIZE(KeyStore_preProvisionedKeyStorageFormat, fletcher)); + + /* Increment the count of PP keys available in pre-provisioned key memory */ + preProvisionedKeyCount++; + } + else + { + /* Skip over the invalid key */ + keySize += (sizeof(KeyStore_PSA_KeyFileId) + sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG) + + sizeof(KeyStore_PSA_Algorithm) + sizeof(KeyStore_PSA_KeyUsage)); + + memcpy(&keyLength, (currentKey + keySize), MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength)); + + keySize += (MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength) + keyLength + + MEMBER_SIZE(KeyStore_preProvisionedKeyStorageFormat, fletcher)); + } + + /* Set to pre-provisioned key address tracking to the next PP key, if available, after the key and checksum */ + currentKey += keySize; + + /* Reset pre-provisioned key size tracking for the next PP key */ + keySize = 0; + + memcpy(&end, currentKey, sizeof(end)); + } while ((end != KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END) && (end != KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY)); + + return KEYSTORE_PSA_STATUS_SUCCESS; +} + +/** + * @brief Compute Fletcher Checksum-32 + * + * \param[in] addr - Starting address of data used for checksum + * \param[in] len - Length of data that requires checksum + * \param[out] checksum - Computed 32-bit checksum + */ +/* + * ======== KeyStore_PSA_computeFletcherChecksum ======== + */ +static uint32_t KeyStore_PSA_computeFletcherChecksum(uint8_t *addr, uint32_t len) +{ + uint32_t sum1, sum2, i, checksum; + uint16_t mod; + mod = (2 ^ (FLETCHER_CHECKSUM_ALGORITHM / 2)) - 1; + + /* Initialize both sums to zero*/ + sum1 = 0; + sum2 = 0; + for (i = 0; i < len; i++) + { + sum1 += *addr++; + if (sum1 >= mod) + { + sum1 -= mod; + } + sum2 += sum1; + if (sum2 >= mod) + { + sum2 -= mod; + } + } + checksum = sum2 << mod | sum1; + + return checksum; +} + +/** + * @brief Verify the fletcher checksum of the give pre-provisioned key ID + * + * \param[in] preProvisionedKey - Structure to the pre-provisioned key ID to be verified + * + * \retval #KEYSTORE_PSA_STATUS_SUCCESS + * Successfully verified checksum + * \retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * Fletched checksum verification failed + * \retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * Insufficient memory in heap to create a copy of pre-provisioned key + * from persistent memory to compute checksum + */ +/* + * ======== KeyStore_PSA_verifyFletcherChecksum ======== + */ +static int_fast16_t KeyStore_PSA_verifyFletcherChecksum(KeyStore_PSA_preProvisionedKeyIDs *preProvisionedKey) +{ + uint32_t expectedChecksum, computedChecksum; + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + uint8_t keySize = KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE + preProvisionedKey->keyLength; + + memcpy(&expectedChecksum, (preProvisionedKey->addr + preProvisionedKey->keyLength), sizeof(expectedChecksum)); + + computedChecksum = KeyStore_PSA_computeFletcherChecksum(preProvisionedKey->addr - + (KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE), + keySize); + + if (expectedChecksum == computedChecksum) + { + status = KEYSTORE_PSA_STATUS_SUCCESS; + } + else + { + status = KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED; + } + + return status; +} + +/* Copy the pre-provisioned key from persistent memory to the provided data buffer and set the dataLength */ +/* + * ======== KeyStore_PSA_copyKeyDataFromFlash ======== + */ +static int_fast16_t KeyStore_PSA_copyKeyDataFromFlash(KeyStore_PSA_preProvisionedKeyIDs *preProvisionedKey, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (dataSize == preProvisionedKey->keyLength) + { + memcpy(data, preProvisionedKey->addr, preProvisionedKey->keyLength); + *dataLength = preProvisionedKey->keyLength; + status = KEYSTORE_PSA_STATUS_SUCCESS; + } + else + { + status = KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL; + } + return status; +} + +/* + * Copy the pre-provisioned key and its length in the provided buffers after verifying fletcher checksum and key + * properties + */ +/* + * ======== KeyStore_PSA_fetchPreProvisionedData ======== + */ +static int_fast16_t KeyStore_PSA_fetchPreProvisionedData(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + bool export, + KeyStore_PSA_Algorithm alg, + KeyStore_PSA_KeyUsage usage) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_DOES_NOT_EXIST; + + if (preProvisionedKeyCount != KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY) + { + /* Check if Key ID matches pre-provisioned key */ + uint32_t i; + for (i = 0; i <= preProvisionedKeyCount; i++) + { + if ((key.MBEDTLS_PRIVATE(owner) == preProvisionedKeyIds[i].id.MBEDTLS_PRIVATE(owner)) && + (key.MBEDTLS_PRIVATE(key_id) == preProvisionedKeyIds[i].id.MBEDTLS_PRIVATE(key_id))) + { + status = KeyStore_PSA_verifyFletcherChecksum(&preProvisionedKeyIds[i]); + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + if (export) + { + if (preProvisionedKeyIds[i].export == KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG) + { + status = KeyStore_PSA_copyKeyDataFromFlash(&preProvisionedKeyIds[i], + data, + dataSize, + dataLength); + } + else + { + status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; + } + } + else + { + if (preProvisionedKeyIds->alg == alg && preProvisionedKeyIds->usage == usage) + { + status = KeyStore_PSA_copyKeyDataFromFlash(&preProvisionedKeyIds[i], + data, + dataSize, + dataLength); + } + else + { + status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; + } + } + } + + /* Exit for loop since matching key ID & owner was found */ + break; + } + } + } + + return status; +} + +/*! + * @cond NODOC + * @brief Non-public functions required by other drivers + * + * The functions may be required by other drivers and are required to + * ensure thread-safe behavior across multiple calls. + * @endcond + */ + +/* + * ======== KeyStore_acquireLock ======== + */ +static inline bool KeyStore_acquireLock(void) +{ + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the KeyStore module */ + resourceAcquired = SemaphoreP_pend(&KeyStore_semaphoreObject.KeyStore_accessSemaphore, SemaphoreP_WAIT_FOREVER); + + return resourceAcquired == SemaphoreP_OK; +} + +/* + * ======== KeyStore_releaseLock ======== + */ +static inline void KeyStore_releaseLock(void) +{ + SemaphoreP_post(&KeyStore_semaphoreObject.KeyStore_accessSemaphore); +} + +/** \defgroup key_management Key management + * @{ + */ + +/* + * ======== KeyStore_PSA_purgeKey ======== + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_semaphoreObject.isAcquired) + { + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + } + + /* + * Only purge persistent keys, volatile keys do not have to be purged. + * Both type of keys will be destroyed after use by the application using + * KeyStore_PSA_destroyKey() + */ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + if (key.MBEDTLS_PRIVATE(key_id) > KEYSTORE_PSA_MAX_VOLATILE_KEY_ID) +#else + if (key > KEYSTORE_PSA_MAX_VOLATILE_KEY_ID) +#endif + { + status = psa_purge_key(key); + } + + if (!KeyStore_semaphoreObject.isAcquired && (status != KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE)) + { + KeyStore_releaseLock(); + } + return status; +} + +/* + * ======== KeyStore_cleanUp ======== + */ +static int_fast16_t KeyStore_cleanUp(int_fast16_t status) +{ + KeyStore_semaphoreObject.isAcquired = false; + if (status != KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE) + { + KeyStore_releaseLock(); + } + + return status; +} + +/* + * ======== KeyStore_PSA_init ======== + */ +int_fast16_t KeyStore_PSA_init(void) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!isKeyStoreInitialized) + { + mbedtls_memory_buffer_alloc_init(allocBuffer, sizeof(allocBuffer)); + /* + * Applications may call psa_crypto_init() function more than once, + * for example in Key Store and TF-M. Once a call succeeds, + * subsequent calls are guaranteed to succeed. + */ + status = psa_crypto_init(); + + if (status != PSA_SUCCESS) + { + return status; + } + + status = tfm_its_init(); + + if (status != PSA_SUCCESS) + { + psa_wipe_all_key_slots(); + return KEYSTORE_PSA_STATUS_GENERIC_ERROR; + } + + if (!KeyStore_semaphoreObject.isInitialized) + { + SemaphoreP_constructBinary(&KeyStore_semaphoreObject.KeyStore_accessSemaphore, 1); + KeyStore_semaphoreObject.isInitialized = true; + } + + status = KeyStore_PSA_getPreProvisionedKeyIDs(); + + if (status == KEYSTORE_PSA_STATUS_DOES_NOT_EXIST) + { + preProvisionedKeyCount = KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY; + status = KEYSTORE_PSA_STATUS_SUCCESS; + } + + isKeyStoreInitialized = true; + } + else + { + status = KEYSTORE_PSA_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== KeyStore_PSA_getKey ======== + */ +int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + KeyStore_PSA_Algorithm alg, + KeyStore_PSA_KeyUsage usage) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + psa_key_slot_t *slot; + uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* Check if Key is in pre-provisioned key memory before checking in ITS */ + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, false, alg, usage); + return KeyStore_cleanUp(status); + } + + /* + * Reject a zero-length output buffer now, since this can never be a + * valid key representation. This way we know that data must be a valid + * pointer and we can do things like memset(data, ..., dataSize). */ + if (dataSize == 0) + { + status = PSA_ERROR_BUFFER_TOO_SMALL; + return KeyStore_cleanUp(status); + } + + /* + * Set the key to empty now, so that even when there are errors, we always + * set dataLength to a value between 0 and dataSize. On error, setting + * the key to empty is a good choice because an empty key representation is + * unlikely to be accepted anywhere. */ + *dataLength = 0; + + /* Fetch key material from key storage. */ + status = psa_get_and_lock_key_slot_with_policy(key, &slot, usage, alg); + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + /* Ignore return value for decrement of lock counter, the return value from attempting to fetch key is apt for + * application + */ + (void)psa_unlock_key_slot(slot); + return KeyStore_cleanUp(status); + } + + psa_key_attributes_t attributes = {.MBEDTLS_PRIVATE(core) = slot->attr}; + + status = psa_export_key_internal(&attributes, slot->key.data, slot->key.bytes, data, dataSize, dataLength); + + /* Decrement lock counter on key slot after accessing the key material */ + status = psa_unlock_key_slot(slot); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_importKey ======== + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + /* Check if the persistent keyID is already used by the pre-provisioned keys or less than the min persistent key IDs + */ + if (attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) == KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT) + { +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + if (key->MBEDTLS_PRIVATE(key_id) < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) +#else + if (*key < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) +#endif + { + return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; + } + } + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_import_key(attributes, data, dataLength, key); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_exportKey ======== + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* Check if Key is in pre-provisioned key memory before checking in ITS */ + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, true, 0, 0); + return KeyStore_cleanUp(status); + } + + status = psa_export_key(key, data, dataSize, dataLength); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_exportPublicKey ======== + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* Check if Key is in pre-provisioned key memory before checking in ITS */ + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, true, 0, 0); + return KeyStore_cleanUp(status); + } + + status = psa_export_public_key(key, data, dataSize, dataLength); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_importCertificate ======== + */ +int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, + KeyStore_PSA_KeyFileId *key, + uint8_t *data, + size_t dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + uint32_t keyID; + KeyStore_PSA_KeyFileId certificateID; +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + keyID = key->MBEDTLS_PRIVATE(key_id); +#else + keyID = *key; +#endif + + /* Compute certificate ID from associated public key ID */ + GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); + + /* + * Only support persistent certificates with TF-M 1.1 + */ + if (attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) != KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT) + { + status = KEYSTORE_PSA_STATUS_INVALID_ARGUMENT; + return status; + } + + /* Check if key ID is within the allowed persistent key ID range for keys with associated certificates */ + if ((keyID > KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX) || (keyID < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN)) + { + return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; + } + + /* Check if a certificate already exists with the same ID in pre-provisioned keys storage */ + if (((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX))) + { + return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; + } + + /* Compute certificate ID from associated public key ID */ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = key->MBEDTLS_PRIVATE(key_id) | + KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT; + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = key->MBEDTLS_PRIVATE(owner); +#else + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = *key | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT; +#endif + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* + * Import certificate into key slot, this will return + * KEYSTORE_PSA_STATUS_ALREADY_EXISTS if a certificate is associated with + * the provided keyID. + */ + status = psa_import_key(attributes, data, dataLength, &certificateID); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_exportCertificate ======== + */ +int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + KeyStore_PSA_KeyFileId certificateID; + uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if (keyID > KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX) + { + return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; + } + + /* Compute certificate ID from associated public key ID */ + GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); + + /* Check if Certificate is in pre-provisioned key memory before checking in ITS */ + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + status = KeyStore_PSA_fetchPreProvisionedData(certificateID, data, dataSize, dataLength, true, 0, 0); + return KeyStore_cleanUp(status); + } + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_export_key(certificateID, data, dataSize, dataLength); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_destroyCertificate ======== + */ +int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if (keyID >= KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MIN && + keyID <= KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MAX) + { + return KEYSTORE_PSA_STATUS_NOT_SUPPORTED; + } + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_destroy_key(key); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_destroyKey ======== + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + KeyStore_PSA_KeyFileId certificateID; + volatile uint32_t keyID; + KeyStore_PSA_KeyHandle handle; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + return KEYSTORE_PSA_STATUS_NOT_SUPPORTED; + } + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* Only check for associated certificates for persistent key IDs */ + if (!(psa_key_id_is_volatile(keyID))) + { + /* Check that there is no associated certificate with the given keyID */ + /* Compute certificate ID from associated public key ID */ + GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); + + /* Attempt to open certificateID, if it exists */ + status = psa_open_key(certificateID, &handle); + + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + /* Cannot delete keys with associated certificates, the application must first delete the certificate */ + status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; + + /* Decrement lock counter on certificate slot */ + (void)psa_close_key(handle); + + return KeyStore_cleanUp(status); + } + } + + status = psa_destroy_key(key); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_getKeyAttributes ======== + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes) + +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_get_key_attributes(key, attributes); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_resetKeyAttributes ======== + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes) +{ + mbedtls_free(attributes->MBEDTLS_PRIVATE(domain_parameters)); + memset(attributes, 0, sizeof(*attributes)); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h new file mode 100644 index 00000000..98cc7864 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file CryptoKeyKeyStore_PSA_helpers.h + * @brief CryptoKeyKeyStore driver header + * + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers_Overview + * # Overview + * The CryptoKeyKeyStore driver provides API to initialize keys and get plaintext + * keys from KeyStore. This file provides definitions that are only available to the + * the secure side, in both TF-M disabled and TF-M enabled environments. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include + +#include +#include + +#include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** KeyStore driver semaphore used to synchronize accesses to the keyStore + * + * isAcquired: used by openKey() and purgeKey() to check if the KeyStore semaphore is acquired by + * other KeyStore functions before opening and closing key handles passed to mbedcrypto functions. + */ +typedef struct +{ + SemaphoreP_Struct KeyStore_accessSemaphore; + bool isInitialized; + bool isAcquired; +} KeyStore_accessSemaphoreObject; + +extern KeyStore_accessSemaphoreObject KeyStore_semaphoreObject; + +#define FLETCHER_CHECKSUM_ALGORITHM 32 /* FLETCHER-32 */ + +/** + * @brief Get the plaintext key in binary format. + * + * This function can only be called on secure side of SPM. It is used by SL crypto drivers + * to obtain plaintext keys, using keyIDs provided by non-secure application, which will be loaded onto crypto engine + * + * Implementations must reject an attempt to import a certificate of size 0. + * + * @param [in] key The key ID for the key in keystore. + * @param [out] data On success, the buffer contains the plaintext key + * @param [in] dataSize Size of the @p data buffer in bytes. It must be + * greater than or equal to the plaintext key material + * @param [out] dataLength Size of the returned key material in bytes. + * @param [in] alg Algorithm the key will be used for, it should match the orignal @p alg used to import the key. + * @param [in] usage Key usage, it must match the original @p usage used to import the key. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the key ID exists, matches the @p alg and @p usage , and the @p dataSize is sufficient + * the key is returned in @p data + * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key does not have matching @p alg and @p usage + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + KeyStore_PSA_Algorithm alg, + KeyStore_PSA_KeyUsage usage); + +/** + * @brief Initialize the Key Store. + * + * Applications must call this function before calling any other + * function in this module. This function will initialize key + * slot memory and load the key IDs of any preprovisioned keys. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * @retval #KEYSTORE_PSA_STATUS_GENERIC_ERROR + * tfm_its_init() failed + * @retval #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST + * KeyStore_PSA_getPreProvisionedKeyIDs() failed + * + */ +int_fast16_t KeyStore_PSA_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h new file mode 100644 index 00000000..acfb7727 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h @@ -0,0 +1,88 @@ + +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_CryptoKeyKeyStore_PSA_init__include +#define ti_drivers_CryptoKeyKeyStore_PSA_init__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_KEYSTORE + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + void *keyAttributes); + +/*! + * @brief Initializes a Blank CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_BLANK_KEYSTORE + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initBlankKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + void *keyAttributes); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_KeyStore_PSA_init__include */ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c new file mode 100644 index 00000000..6768f83d --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +/* CryptoKey headers */ +#include +#include +#include + +/* PSA headers from TF-M interface */ +#include +#include + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* + * ======== KeyStore_PSA_exportCommon ======== + */ +static int_fast16_t KeyStore_PSA_exportCommon(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + int32_t type) +{ + KeyStore_s_ExportMsg exportCommonMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + exportCommonMsg.key = key; + exportCommonMsg.data = data; + exportCommonMsg.dataSize = dataSize; + exportCommonMsg.dataLength = dataLength; + + invecs[0].base = &exportCommonMsg; + invecs[0].len = sizeof(exportCommonMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * if statement returns from secure driver can be ignored by the non-secure driver, + * the secure KeyStore driver returns are handled by the application using outvecs (ret) + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_exportCertificate ======== + */ +int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE); +} + +/* + * ======== KeyStore_PSA_exportPublicKey ======== + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY); +} + +/* + * ======== KeyStore_PSA_exportKey ======== + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength) +{ + return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY); +} + +/* + * ======== KeyStore_PSA_destroyCommon ======== + */ +static int_fast16_t KeyStore_PSA_destroyCommon(KeyStore_PSA_KeyFileId key, int32_t type) +{ + KeyStore_s_DestroyPurgeKeyCertificateMsg destroyCommonMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + destroyCommonMsg.key = key; + + invecs[0].base = &destroyCommonMsg; + invecs[0].len = sizeof(destroyCommonMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_destroyKey ======== + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) +{ + return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY); +} + +/* + * ======== KeyStore_PSA_destroyCertificate ======== + */ +int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key) +{ + return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE); +} + +/* + * ======== KeyStore_PSA_importCertificate ======== + */ +int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, + KeyStore_PSA_KeyFileId *key, + uint8_t *data, + size_t dataLength) + +{ + KeyStore_s_ImportCertificateMsg importCertificateMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + importCertificateMsg.attributes = &attributes->client; + importCertificateMsg.key = key; + importCertificateMsg.data = data; + importCertificateMsg.dataLength = dataLength; + + invecs[0].base = &importCertificateMsg; + invecs[0].len = sizeof(importCertificateMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_importKey ======== + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key) +{ + KeyStore_s_ImportKeyMsg importKeyMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + importKeyMsg.attributes = &attributes->client; + importKeyMsg.key = key; + importKeyMsg.data = data; + importKeyMsg.dataLength = dataLength; + + invecs[0].base = &importKeyMsg; + invecs[0].len = sizeof(importKeyMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_purgeKey ======== + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key) +{ + return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY); +} + +/* + * ======== KeyStore_PSA_getKeyAttributes ======== + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes) +{ + KeyStore_s_GetKeyAttributesMsg getKeyAttributesMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + getKeyAttributesMsg.attributes = &attributes->client; + getKeyAttributesMsg.key = key; + + invecs[0].base = &getKeyAttributesMsg; + invecs[0].len = sizeof(getKeyAttributesMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_resetKeyAttributes ======== + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes) +{ + KeyStore_s_ResetKeyAttributesMsg resetKeyAttributeMsg; + + resetKeyAttributeMsg.attributes = &attributes->client; + + invecs[0].base = &resetKeyAttributeMsg; + invecs[0].len = sizeof(resetKeyAttributeMsg); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES, invecs, outvecs); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c new file mode 100644 index 00000000..25a7fc83 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * ======== KeyStore_s_copyKeyAttributesFromClient ======== + */ +psa_status_t KeyStore_s_copyKeyAttributesFromClient(struct psa_client_key_attributes_s *clientKeyAttr, + int32_t clientId, + psa_key_attributes_t *keyAttributes) +{ + if (clientKeyAttr == NULL || keyAttributes == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + *keyAttributes = psa_key_attributes_init(); + + /* Copy core key attributes from the client core key attributes */ + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = clientKeyAttr->type; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = clientKeyAttr->lifetime; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage) = clientKeyAttr->usage; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg) = clientKeyAttr->alg; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = clientKeyAttr->bits; + + /* Use the client key id as the key_id and its partition id as the owner */ + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = clientKeyAttr->id; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = clientId; + + return PSA_SUCCESS; +} + +/** + * \brief Converts key attributes to client key attributes. + * Follows tfm_crypto_key_attributes_to_client() + * + * \param[in] keyAttributes Key attributes, no address verification necessary as this is always in secure side + * \param[out] clientKeyAttr Client key attributes, address location must be verified to be in non-secure memory by + * calling functions + * + * \return Return values as described in \ref psa_status_t + */ +/* + * ======== KeyStore_s_copyKeyAttributesToClient ======== + */ +static psa_status_t KeyStore_s_copyKeyAttributesToClient(const psa_key_attributes_t *keyAttributes, + struct psa_client_key_attributes_s *clientKeyAttr) +{ + if (clientKeyAttr == NULL || keyAttributes == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + struct psa_client_key_attributes_s v = {0, 0, 0, 0, 0, 0}; + *clientKeyAttr = v; + + /* Copy core key attributes from the client core key attributes */ + clientKeyAttr->type = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type); + clientKeyAttr->lifetime = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); + clientKeyAttr->usage = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage); + clientKeyAttr->alg = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg); + clientKeyAttr->bits = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits); + + /* Return the key_id as the client key id, do not return the owner */ + clientKeyAttr->id = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id); + + return PSA_SUCCESS; +} + +/** + * \brief Copies key ID from secure side to client key ID + * + * \param[in] keyID Key ID, no address verification necessary as this is always in secure side + * \param[out] clientKeyID Client key ID, address location must be verified to be in non-secure memory by + * calling functions + * + */ +/* + * ======== KeyStore_s_copyKeyIDtoClient ======== + */ +static void KeyStore_s_copyKeyIDtoClient(KeyStore_PSA_KeyFileId *keyID, uint32_t *clientKeyID) +{ + /* Copy the keyID output from the KeyStore driver to client keyID */ + *clientKeyID = keyID->MBEDTLS_PRIVATE(key_id); +} + +/* + * ======== KeyStore_s_copyKeyIDFromClient ======== + */ +void KeyStore_s_copyKeyIDFromClient(KeyStore_PSA_KeyFileId *keyID, int32_t clientId, uint32_t *clientKeyID) +{ + /* Copy keyID from client to KeyStore driver and set the owner to the caller's ID */ + keyID->MBEDTLS_PRIVATE(key_id) = *clientKeyID; + keyID->MBEDTLS_PRIVATE(owner) = clientId; +} + +/* + * ======== KeyStore_s_getKeyAttributes ======== + */ +psa_status_t KeyStore_s_getKeyAttributes(psa_msg_t *msg) +{ + KeyStore_s_GetKeyAttributesMsg getKeyAttributesMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(getKeyAttributesMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getKeyAttributesMsg, sizeof(getKeyAttributesMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (cmse_has_unpriv_nonsecure_rw_access(getKeyAttributesMsg.attributes, + sizeof(struct psa_client_key_attributes_s)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &getKeyAttributesMsg.key); + + ret = KeyStore_PSA_getKeyAttributes(keyID, &keyAttributes); + + if (ret == KEYSTORE_PSA_STATUS_SUCCESS) + { + ret = KeyStore_s_copyKeyAttributesToClient(&keyAttributes, + (struct psa_client_key_attributes_s *) + getKeyAttributesMsg.attributes); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_importKey ======== + */ +psa_status_t KeyStore_s_importKey(psa_msg_t *msg) +{ + KeyStore_s_ImportKeyMsg importKeyMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(importKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &importKeyMsg, sizeof(importKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Validate input address range */ + if ((cmse_has_unpriv_nonsecure_rw_access(importKeyMsg.key, sizeof(KeyStore_PSA_KeyFileId)) == NULL) || + (cmse_has_unpriv_nonsecure_read_access(importKeyMsg.attributes, sizeof(KeyStore_PSA_KeyAttributes)) == + NULL) || + (cmse_has_unpriv_nonsecure_read_access(importKeyMsg.data, importKeyMsg.dataLength) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* Copy keyID from application for persistent keys */ + if (importKeyMsg.attributes->lifetime) + { + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, importKeyMsg.key); + } + + ret = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)importKeyMsg.attributes, + msg->client_id, + &keyAttributes); + + if (ret == PSA_SUCCESS) + { + ret = KeyStore_PSA_importKey(&keyAttributes, importKeyMsg.data, importKeyMsg.dataLength, &keyID); + + KeyStore_s_copyKeyIDtoClient(&keyID, importKeyMsg.key); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_importCertificate ======== + */ +psa_status_t KeyStore_s_importCertificate(psa_msg_t *msg) +{ + KeyStore_s_ImportCertificateMsg importCertificateMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(importCertificateMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &importCertificateMsg, sizeof(importCertificateMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Validate input address range */ + if ((cmse_has_unpriv_nonsecure_rw_access(importCertificateMsg.key, sizeof(KeyStore_PSA_KeyFileId)) == NULL) || + (cmse_has_unpriv_nonsecure_read_access(importCertificateMsg.attributes, + sizeof(KeyStore_PSA_KeyAttributes)) == NULL) || + (cmse_has_unpriv_nonsecure_read_access(importCertificateMsg.data, importCertificateMsg.dataLength) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* Copy keyID from application for certificates */ + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, importCertificateMsg.key); + + ret = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)importCertificateMsg.attributes, + msg->client_id, + &keyAttributes); + + if (ret == PSA_SUCCESS) + { + ret = KeyStore_PSA_importCertificate(&keyAttributes, + &keyID, + importCertificateMsg.data, + importCertificateMsg.dataLength); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_destroyCertificateKey ======== + */ +psa_status_t KeyStore_s_destroyCertificateKey(psa_msg_t *msg, int32_t msgType) +{ + KeyStore_s_DestroyPurgeKeyCertificateMsg destroyMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(destroyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &destroyMsg, sizeof(destroyMsg)); + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &destroyMsg.key); + + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE) + { + ret = KeyStore_PSA_destroyCertificate(keyID); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY) + { + ret = KeyStore_PSA_destroyKey(keyID); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY) + { + ret = KeyStore_PSA_purgeKey(keyID); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_exportCertificateKey ======== + */ +psa_status_t KeyStore_s_exportCertificateKey(psa_msg_t *msg, int32_t msgType) +{ + KeyStore_s_ExportMsg exportMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(exportMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &exportMsg, sizeof(exportMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Validate input address range */ + if (cmse_has_unpriv_nonsecure_rw_access(exportMsg.data, exportMsg.dataSize) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &exportMsg.key); + + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE) + { + ret = KeyStore_PSA_exportCertificate(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY) + { + ret = KeyStore_PSA_exportKey(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY) + { + ret = KeyStore_PSA_exportPublicKey(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_resetKeyAttributes ======== + */ +psa_status_t KeyStore_s_resetKeyAttributes(psa_msg_t *msg) +{ + KeyStore_s_ResetKeyAttributesMsg resetKeyAttributeMsg; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + + if ((msg->in_size[0] != sizeof(resetKeyAttributeMsg))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &resetKeyAttributeMsg, sizeof(resetKeyAttributeMsg)); + + KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)resetKeyAttributeMsg.attributes, + msg->client_id, + &keyAttributes); + + /* + * Following TF-M's implementation of psa_reset_key_attributes(), KeyStore_PSA_resetKeyAttributes() cannot be + * directly called from non-secure application. KeyStore S/NS interface makes a PSA call to reset the attributes + * using the function in secure partition + */ + KeyStore_PSA_resetKeyAttributes(&keyAttributes); + + KeyStore_s_copyKeyAttributesToClient(&keyAttributes, resetKeyAttributeMsg.attributes); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_getKey ======== + */ +psa_status_t KeyStore_s_getKey(psa_msg_t *msg) +{ + KeyStore_s_GetKeyMsg getKeyMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(getKeyMsg)) || (msg->out_size[0] != sizeof(ret)) || + TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getKeyMsg, sizeof(getKeyMsg)); + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &getKeyMsg.key); + + ret = KeyStore_PSA_getKey(keyID, + getKeyMsg.data, + getKeyMsg.dataSize, + getKeyMsg.dataLength, + getKeyMsg.alg, + getKeyMsg.usage); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_handlePsaMsg ======== + */ +psa_status_t KeyStore_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + switch (msg->type) + { + case KEYSTORE_PSA_S_MSG_TYPE_GET_KEY: + status = KeyStore_s_getKey(msg); + break; + /* Fall through for exporting */ + case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE: + case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY: + case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY: + status = KeyStore_s_exportCertificateKey(msg, msg->type); + break; + /* Fall through for destroying */ + case KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE: + case KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY: + case KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY: + status = KeyStore_s_destroyCertificateKey(msg, msg->type); + break; + case KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE: + status = KeyStore_s_importCertificate(msg); + break; + case KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY: + status = KeyStore_s_importKey(msg); + break; + case KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES: + status = KeyStore_s_getKeyAttributes(msg); + break; + case KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES: + status = KeyStore_s_resetKeyAttributes(msg); + break; + default: + /* Unkown PSA message type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== KeyStore_s_init ======== + */ +void KeyStore_s_init(void) +{ + KeyStore_PSA_init(); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h new file mode 100644 index 00000000..1f063910 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file CryptoKeyKeyStore_PSA_s.h + * @brief Secure Crypto Service + * + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s_Overview + * # Overview + * The Secure KeyStore driver is used to access all KeyStore functions + * when using the TF-M. + * + ******************************************************************************* + */ +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include + +#include + +#include +#include + +#include +#include + +/* For client side key attribute structure */ +#include + +/* + * Crypto Key Store secure message types + */ +#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY KEYSTORE_PSA_S_MSG_TYPE(0U) +#define KEYSTORE_PSA_S_MSG_TYPE_GENERATE_KEY KEYSTORE_PSA_S_MSG_TYPE(1U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(2U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY KEYSTORE_PSA_S_MSG_TYPE(3U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(4U) +#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(5U) +#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY KEYSTORE_PSA_S_MSG_TYPE(6U) +#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(7U) +#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(8U) +#define KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY KEYSTORE_PSA_S_MSG_TYPE(9U) +#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(10U) +#define KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(11U) + +/* + * ============ KeyStore driver Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * KeyStore secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + uint32_t key; + uint8_t *data; + size_t dataSize; + size_t *dataLength; + KeyStore_PSA_Algorithm alg; + KeyStore_PSA_KeyUsage usage; +} KeyStore_s_GetKeyMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; + KeyStore_PSA_KeyFileId *key; +} KeyStore_s_GenerateKeyMsg; + +/* Msg for KeyStore_PSA_exportKey(), KeyStore_PSA_exportCertificate(), and KeyStore_PSA_exportPublicKey() */ +typedef struct +{ + uint32_t key; + uint8_t *data; + size_t dataSize; + size_t *dataLength; +} KeyStore_s_ExportMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; + uint32_t *key; + uint8_t *data; + size_t dataLength; +} KeyStore_s_ImportCertificateMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; + uint8_t *data; + size_t dataLength; + uint32_t *key; +} KeyStore_s_ImportKeyMsg; + +/* Msg for KeyStore_PSA_destroyKey(), KeyStore_PSA_destroyCertificate(), and KeyStore_PSA_purgeKey() */ +typedef struct +{ + uint32_t key; +} KeyStore_s_DestroyPurgeKeyCertificateMsg; + +typedef struct +{ + uint32_t key; + struct psa_client_key_attributes_s *attributes; +} KeyStore_s_GetKeyAttributesMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; +} KeyStore_s_ResetKeyAttributesMsg; + +/*! + * @brief Handles PSA messages for KeyStore secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t KeyStore_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the KeyStore secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void KeyStore_s_init(void); + +/** + * @brief Gets key attributes from client key attributes. + * Follows tfm_crypto_key_attributes_from_client() + * + * @param[in] clientKeyAttr Client key attributes, address location must be verified to be in non-secure memory by + * calling functions + * @param[in] clientId Partition ID of the calling client + * @param[out] keyAttributes Key attributes, no address verification necessary as this is always in secure side + * + * @return Always return #KEYSTORE_PSA_STATUS_SUCCESS + */ +psa_status_t KeyStore_s_copyKeyAttributesFromClient(struct psa_client_key_attributes_s *clientKeyAttr, + int32_t clientId, + psa_key_attributes_t *keyAttributes); + +/** + * @brief Copies client key ID from non-secure side to secure side + * + * @param[out] keyID Key ID, no address verification necessary as this is always in secure side + * @param[in] clientKeyID Client key ID, address location must be verified to be in non-secure memory by + * calling functions + * @param[in] clientId Client ID, partition ID from PSA call + */ +void KeyStore_s_copyKeyIDFromClient(KeyStore_PSA_KeyFileId *keyID, int32_t clientId, uint32_t *clientKeyID); +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c new file mode 100644 index 00000000..f1acde89 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include + +/* + * ======== CryptoKeyPlaintext_markAsBlank ======== + */ +int_fast16_t CryptoKeyPlaintext_markAsBlank(CryptoKey *keyHandle) +{ + keyHandle->encoding = CryptoKey_BLANK_PLAINTEXT; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_initKey ======== + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength) +{ + keyHandle->encoding = CryptoKey_PLAINTEXT; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_initBlankKey ======== + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength) +{ + + keyHandle->encoding = CryptoKey_BLANK_PLAINTEXT; + keyHandle->u.plaintext.keyMaterial = keyLocation; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLocation ======== + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location) +{ + keyHandle->u.plaintext.keyMaterial = location; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLocation ======== + */ +int_fast16_t CryptoKeyPlaintext_getKeyLocation(CryptoKey *keyHandle, uint8_t **location) +{ + *location = keyHandle->u.plaintext.keyMaterial; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_getKeyLength ======== + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length) +{ + *length = keyHandle->u.plaintext.keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLength ======== + */ +int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length) +{ + keyHandle->u.plaintext.keyLength = length; + + return CryptoKey_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h new file mode 100644 index 00000000..3ff5c9e9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoKeyPlaintext.h + * + * @warning This is a beta API. It may change in future releases. + * + * # Overview # + * This file contains the APIs to initialize and access plaintext CryptoKeys. + * Plaintext CryptoKeys point to keying material stored in flash or RAM and + * are not subject to enforced usage restrictions. That only means that calling + * a function that requires an assymmetric public key with a symmetric key will + * not return an error. It will likely not yield the desired results. + * + * # Usage # + * + * Plaintext keys are the simplest of the CryptoKeys. All they do is store the + * length of and a pointer to the keying material. Their use is hence simple as + * well. After calling the initialization function, the CryptoKey may be used in + * any of the crypto operation APIs that take a CryptoKey as an input. + * + * @code + * + * uint8_t keyingMaterial[16]; + * CryptoKey cryptoKey; + * + * // Initialise the CryptoKey + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Use the CryptoKey in another crypto operation + * + * @endcode + * + */ + +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Marks a CryptoKey as 'blank'. + * + * The CryptoKey will be unlinked from any previously connected keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKeyPlaintext_markAsBlank(CryptoKey *keyHandle); + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_PLAINTEXT + * and ready for use + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); + +/*! + * @brief Initializes an empty plaintext CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be + * initialized to type + * CryptoKey_BLANK_PLAINTEXT + * + * @param [in] keyLocation Pointer to location where plaintext keying + * material can be stored + * + * @param [in] keyLength Length of keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength); + +/*! + * @brief Sets the CryptoKey keyMaterial pointer + * + * Updates the key location for a plaintext CryptoKey. + * Does not modify data at the pointer location. + * + * @param [out] keyHandle Pointer to a plaintext CryptoKey who's key + * data pointer will be modified + * + * @param [in] location Pointer to key data location + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location); + +/*! + * @brief Gets the CryptoKey keyMaterial pointer + * + * @param [in] keyHandle Pointer to an initialized plaintext CryptoKey + * + * @param [out] location Pointer to key data location + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLocation(CryptoKey *keyHandle, uint8_t **location); + +/*! + * @brief Gets the length of a plaintext key + * + * @param [in] keyHandle Pointer to a plaintext CryptoKey + * + * @param [out] length Length of the keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length); +/*! + * @brief Sets the length of a plaintext key + * + * @param [out] keyHandle Pointer to a CryptoKey + * + * @param [in] length Length value in bytes to update + * @c keyHandle with + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.c new file mode 100644 index 00000000..6f927063 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include + +/* + * ======== ECCInitLPF3SW_NISTP256 ======== + */ +void ECCInitLPF3SW_NISTP256(ECC_State *state, uint8_t windowSize, uint32_t *workZone) +{ + state->data_Gx = ECC_NISTP256_generatorX.word; + state->data_Gy = ECC_NISTP256_generatorY.word; + state->data_p = ECC_NISTP256_prime.word; + state->data_r = ECC_NISTP256_order.word; + state->data_a = ECC_NISTP256_a.word; + state->data_b = ECC_NISTP256_b.word; + state->data_a_mont = ECC_NISTP256_a_mont.word; + state->data_b_mont = ECC_NISTP256_b_mont.word; + state->data_k_mont = ECC_NISTP256_k_mont.word; + state->win = windowSize; + + state->workzone = workZone; +} + +/* + * ======== ECCInitLPF3SW_NISTP224 ======== + */ +void ECCInitLPF3SW_NISTP224(ECC_State *state, uint8_t windowSize, uint32_t *workZone) +{ + state->data_Gx = ECC_NISTP224_generatorX.word; + state->data_Gy = ECC_NISTP224_generatorY.word; + state->data_p = ECC_NISTP224_prime.word; + state->data_r = ECC_NISTP224_order.word; + state->data_a = ECC_NISTP224_a.word; + state->data_b = ECC_NISTP224_b.word; + state->data_a_mont = ECC_NISTP224_a_mont.word; + state->data_b_mont = ECC_NISTP224_b_mont.word; + state->data_k_mont = ECC_NISTP224_k_mont.word; + state->win = windowSize; + + state->workzone = workZone; +} + +/* + * ======== ECCInitLPF3SW_Curve25519 ======== + */ +void ECCInitLPF3SW_Curve25519(ECC_State *state, uint8_t windowSize, uint32_t *workZone) +{ + state->data_Gx = ECC_Curve25519_generatorX.word; + state->data_Gy = ECC_Curve25519_generatorY.word; + state->data_p = ECC_Curve25519_prime.word; + state->data_r = ECC_Curve25519_order.word; + state->data_a = ECC_Curve25519_a.word; + state->data_b = ECC_Curve25519_b.word; + /* The following montgomery curve params are not used for any Curve25519 functions */ + state->data_a_mont = NULL; + state->data_b_mont = NULL; + state->data_k_mont = NULL; + state->win = windowSize; + + state->workzone = workZone; +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.h new file mode 100644 index 00000000..e5e5b056 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCInitLPF3SW.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCInitLPF3SW__include +#define ti_drivers_cryptoutils_ecc_ECCInitLPF3SW__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initializes the ECC state with NIST P256 curve params. + * + * @param state Points to ECC state. + * @param windowSize ECC SW window size used for computations. + * @param workZone Points to ECC workzone buffer. + */ +void ECCInitLPF3SW_NISTP256(ECC_State *state, uint8_t windowSize, uint32_t *workZone); + +/*! + * @brief Initializes the ECC state with NIST P224 curve params. + * + * @param state Points to ECC state. + * @param windowSize ECC SW window size used for computations. + * @param workZone Points to ECC workzone buffer. + */ +void ECCInitLPF3SW_NISTP224(ECC_State *state, uint8_t windowSize, uint32_t *workZone); + +/*! + * @brief Initializes the ECC state with Curve25519 curve params. + * + * @param state Points to ECC state. + * @param windowSize ECC SW window size used for computations. + * @param workZone Points to ECC workzone buffer. + */ +void ECCInitLPF3SW_Curve25519(ECC_State *state, uint8_t windowSize, uint32_t *workZone); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCInitLPF3SW__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h new file mode 100644 index 00000000..fcd5f7b8 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h @@ -0,0 +1,539 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECCParams.h + * + * This file contains a common definition for elliptic curve structures used + * throughout the ECC based drivers. Not all devices support every curve. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCParams__include +#define ti_drivers_cryptoutils_ecc_ECCParams__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error status codes for the utility functions */ + +/*! + * @brief Successful status code. + * + * Function return ECCParams_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define ECCParams_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECCParams_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ECCParams_STATUS_ERROR (-1) + +/*! + * @brief Enumeration of curve equations supported. + * + * Elliptic curves can be expressed using multiple equations of polynomials over + * finite fields. + * All forms can be converted to one another using parameter substitution. + * Each curve has a default curve equations it was designed to use. + * + * Some curve implementations have restrictions on which algorithms and schemes + * they work with. For example, Curve25519 was explicitely designed with ECDH in mind. + * It only uses and yields the X coordinate of a point on the elliptic curve in common + * implementations. Some implementations do provide X and Y affine coordinates but most + * do not. + * Therefore, ECDSA and ECJPAKE do not have compatible implementations + * for Curve25519 on some devices as the Y coordinate is required by them. + * + * Check the header files of each device-specific implementation for information + * regarding curve-support for specific schemes on a device. + * + * | Name | Equation | + * |-------------------|-------------------------------| + * | Short Weierstrass | y^2 = x^3 + a*x + b mod p | + * | Montgomery | By^2 = x^3 + Ax^2 + x mod p | + * | Edwards | x^2 + y^2 = 1 + dx^2y^2 mod p | + * + */ +typedef uint32_t ECCParams_CurveType; + +#define ECCParams_CURVE_TYPE_NONE 0U +#define ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3 1U +#define ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_GEN 2U +#define ECCParams_CURVE_TYPE_MONTGOMERY 3U +#define ECCParams_CURVE_TYPE_EDWARDS 4U + +/*! + * @brief Enumeration of ECC curve names supported by TF-M. + */ +typedef enum +{ + /* + * WARNING: Do not alter the order or contents of this enum without updating + * the corresponding curveParamTable array in ECCParamCC26X4_s.c + */ + ECCParams_SecureCurve_NISTP224 = 0, + ECCParams_SecureCurve_NISTP256, + ECCParams_SecureCurve_NISTP384, + ECCParams_SecureCurve_NISTP521, + ECCParams_SecureCurve_BrainpoolP256R1, + ECCParams_SecureCurve_BrainpoolP384R1, + ECCParams_SecureCurve_BrainpoolP512R1, + ECCParams_SecureCurve_Curve25519, + ECCParams_SecureCurve_Ed25519, + ECCParams_SecureCurve_Wei25519, + ECCParams_SecureCurve_COUNT /* This element denotes the max enum value and is not a valid curve */ +} ECCParams_SecureCurve; + +/* + * ECCParams_CurveParams have different struct members depending on the context + * of the build (Secure-only, Non-secure, or Secure) + */ +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + +/*! + * @brief A structure containing the parameters of an elliptic curve. + * + * Elliptical Curve Cryptography (ECC) prime curve parameters. + */ + +typedef struct ECCParams_CurveParams +{ + const ECCParams_CurveType curveType; + const uint8_t *prime; + const uint8_t *a; + const uint8_t *b; + const uint8_t *order; + const uint8_t cofactor; + const size_t length; + const uint8_t *generatorX; + const uint8_t *generatorY; +} ECCParams_CurveParams; + +#else + +/*! + * @brief A structure containing the curve name to reference elliptic curve + * parameters stored in secure memory. + */ +typedef struct ECCParams_CurveParams +{ + ECCParams_SecureCurve secureCurve; +} ECCParams_CurveParams; + +#endif /* (TFM_ENABLED == 0) || defined(TFM_BUILD) */ + +#if defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + +/*! + * @brief A structure containing the curve name to reference elliptic curve + * parameters stored in secure memory. + */ +/* This must match the ECCParams_CurveParams struct definition directly above */ +typedef struct ECCParams_ns_CurveParams +{ + ECCParams_SecureCurve secureCurve; +} ECCParams_ns_CurveParams; + +#endif /* defined(TFM_BUILD) */ + +/* Short Weierstrass curves */ + +/*! + * + * @brief The NISTP224 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP224; + +/*! + * + * @brief The NISTP256 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP256; + +/*! + * + * @brief The NISTP384 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP384; + +/*! + * + * @brief The NISTP521 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP521; + +/*! + * + * @brief The BrainpoolP256R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP256R1; + +/*! + * + * @brief The BrainpoolP384R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP384R1; + +/*! + * + * @brief The BrainpoolP512R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP512R1; + +/*! + * @brief A short Weierstrass equivalent representation of Ed25519. + */ +extern const ECCParams_CurveParams ECCParams_Wei25519; + +/* Montgomery curves */ + +/*! + * @brief The Curve25519 curve in Montgomery form. + */ +extern const ECCParams_CurveParams ECCParams_Curve25519; + +/* Edwards curves */ + +/*! + * @brief The Ed25519 curve in Edwards form. + */ +extern const ECCParams_CurveParams ECCParams_Ed25519; + +/*! + * @brief Number of bytes for the length word prepended before all parameters + * passed into the ECC SW library functions. + */ +#define ECC_LENGTH_PREFIX_BYTES 4 + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + + /*! + * @defgroup nistp256_params NIST P256 curve params to be used with ECC SW library + * Note: CC26X1 uses NIST P256 curve params defined in driverlib/rom_ecc.h + * @{ + */ + + /*! + * @brief Length of NIST P256 curve parameters in bytes + */ + #define ECCParams_NISTP256_LENGTH 32 + + /*! + * @brief Length in bytes of NISTP256 curve parameters including the prepended + * length word. + */ + #define ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES (ECCParams_NISTP256_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_NISTP256 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_NISTP256_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_prime; + +/*! + * @brief 'a' constant of the ECC_NISTP256 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP256_Param ECC_NISTP256_a; + +/*! + * @brief 'b' constant of the ECC_NISTP256 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP256_Param ECC_NISTP256_b; + +/*! + * @brief Order of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_order; + +/*! + * @brief 'k' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_k_mont; + +/*! + * @brief 'a' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_a_mont; + +/*! + * @brief 'b' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_b_mont; + + /*! @} */ /* end of nistp256_params */ + + /*! + * @defgroup nistp224_params NIST P224 curve params to be used with ECC SW library + * @{ + */ + + /*! + * @brief Length of NIST P224 curve parameters in bytes + */ + #define ECCParams_NISTP224_LENGTH 28 + + /*! + * @brief Length in bytes of NISTP256 curve parameters including the prepended + * length word. + */ + #define ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES (ECCParams_NISTP224_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_NISTP256 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_NISTP224_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_prime; + +/*! + * @brief 'a' constant of the ECC_NISTP224 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP224_Param ECC_NISTP224_a; + +/*! + * @brief 'b' constant of the ECC_NISTP224 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP224_Param ECC_NISTP224_b; + +/*! + * @brief Order of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_order; + +/*! + * @brief 'k' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_k_mont; + +/*! + * @brief 'a' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_a_mont; + +/*! + * @brief 'b' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_b_mont; + + /*! @} */ /* end of nistp224_params */ + + /* Octet string format requires an extra byte at the start of the public key */ + #define OCTET_STRING_OFFSET 1 + + /* Length of offset in bytes */ + #define ECC_LENGTH_OFFSET_BYTES 4 + + /* Param length needs to be equal to the length of the largest curve supported plus length offset bytes */ + #define ECC_PARAM_LENGTH_WITH_OFFSET_BYTES (ECCParams_NISTP256_LENGTH + ECC_LENGTH_OFFSET_BYTES) + +/*! + * @brief Union to format inputs to ECC library. + */ +typedef union +{ + uint32_t word[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES / sizeof(uint32_t)]; + uint8_t byte[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES]; +} ECC_Param; + +#endif /* DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 */ + +/*! + * @brief Length of Curve25519 curve parameters in bytes + */ +#define ECCParams_CURVE25519_LENGTH 32 + +/*! + * @defgroup curve25519_params Curve25519 curve params to be used with ECC SW library + * @{ + */ + +/*! + * @brief Length in bytes of Curve25519 curve parameters including the prepended + * length word. + */ +#define ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES (ECCParams_CURVE25519_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_Curve25519 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_Curve25519_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_prime; + +/*! + * @brief 'a' constant of the ECC_Curve25519 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_Curve25519_Param ECC_Curve25519_a; + +/*! + * @brief 'b' constant of the ECC_Curve25519 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_Curve25519_Param ECC_Curve25519_b; + +/*! + * @brief Order of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_order; + +/*! @} */ /* end of curve25519_params */ + +/* Utility functions */ + +/* #define used for backwards compatibility */ +#define ECCParams_FormatCurve25519PrivateKey ECCParams_formatCurve25519PrivateKey + +/*! + * @brief Formats a CryptoKey to conform to Curve25519 private key requirements. + * + * Curve25519 has specific private key requirements specified by the curve definition. + * Specifically, the bottom three and the top bit may not be set and the second to + * last bit must be set. + * + * @param myPrivateKey An initialized CryptoKey describing the entropy for a + * Curve25519 private key. Platform-specific restrictions + * for the location of the keying material apply. Some + * implementations do not support modifying keying material + * in flash for example. + * + * @pre Initialize the CryptoKey with a 32-byte buffer in a compliant location. + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey); + +/*! + * @brief Extracts the curve generator point from an ecliptic curve description. + * + * The curve parameters #ECCParams_CurveParams::generatorX and + * #ECCParams_CurveParams::generatorY are extracted from \c curveParams and + * written as a concatenated octet string in big endian order to + * \c buffer. The format is defined in SEC 1: Elliptic Curve Cryptography section + * 2.3.3. + * + * The curve point has the format ``0x04 || X || Y`` and the length is + * ``2 * size_of_x_or_y + 1`` where ``0x04`` specifies octet string format. + * If the buffer \c length exceeds the curve point length, the remaining + * buffer space is zeroed. + * + * @param curveParams Points to the input curve parameters + * @param buffer Points to the destination where the generator point will + * be written to. Make sure that \c buffer is large enough to + * hold + * @param length Maximum length of \c buffer in bytes. + * + * @retval #ECCParams_STATUS_SUCCESS on success, #ECCParams_STATUS_ERROR if the + * provided buffer \c length is insufficient to hold the curve point. + * + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCParams__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParamsLPF3SW.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParamsLPF3SW.c new file mode 100644 index 00000000..ca43bda8 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParamsLPF3SW.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsLPF3SW.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on L devices. + */ + +#include +#include +#include + +#include +#include + +/* + * Curve parameters are formatted as little-endian integers with a prepended + * length word in words as required by the ECC SW library. + */ + +/* + * NIST P256 curve params in little endian format. + * byte[0-3] are the param length word as required by the ECC SW library. + * byte[4] is the least significant byte of the curve parameter. + */ +const ECC_NISTP256_Param ECC_NISTP256_generatorX = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}; + +const ECC_NISTP256_Param ECC_NISTP256_generatorY = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}; + +const ECC_NISTP256_Param ECC_NISTP256_prime = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const ECC_NISTP256_Param ECC_NISTP256_a = {.byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const ECC_NISTP256_Param ECC_NISTP256_b = {.byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, 0xf6, 0xb0, 0x53, + 0xcc, 0xb0, 0x06, 0x1d, 0x65, 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, + 0xeb, 0xb3, 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const ECC_NISTP256_Param ECC_NISTP256_order = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +/* + * Curve params in Montgomery domain are used for public key validation only + * and are not prefixed with a length word. + */ +/* Invert of square of Montgomery constant, k = 2^(256) mod p, p is the curve prime */ +const ECC_NISTP256_Param ECC_NISTP256_k_mont = { + .byte = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00}}; + +/* Converted to Montgomery domain by modular multiplication of ECC_NISTP256_a with ECC_NISTP224_k_mont */ +const ECC_NISTP256_Param ECC_NISTP256_a_mont = { + .byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff}}; + +/* Converted to Montgomery domain by modular multiplication of ECC_NISTP256_b with ECC_NISTP224_k_mont */ +const ECC_NISTP256_Param ECC_NISTP256_b_mont = { + .byte = {0xdf, 0xbd, 0xc4, 0x29, 0x62, 0xdf, 0x9c, 0xd8, 0x90, 0x30, 0x84, 0x78, 0xcd, 0x05, 0xf0, 0xac, + 0xd6, 0x2e, 0x21, 0xf7, 0xab, 0x20, 0xa2, 0xe5, 0x34, 0x48, 0x87, 0x04, 0x1d, 0x06, 0x30, 0xdc}}; + +const ECCParams_CurveParams ECCParams_NISTP256 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = ECCParams_NISTP256_LENGTH, + .prime = ECC_NISTP256_prime.byte, + .order = ECC_NISTP256_order.byte, + .a = ECC_NISTP256_a.byte, + .b = ECC_NISTP256_b.byte, + .generatorX = ECC_NISTP256_generatorX.byte, + .generatorY = ECC_NISTP256_generatorY.byte, + .cofactor = 1}; + +/* + * NIST P224 curve params in little endian format. + * byte[0-3] are the param length word as required by the ECC SW library. + * byte[4] is the least significant byte of the curve parameter. + */ +const ECC_NISTP224_Param ECC_NISTP224_generatorX = {.byte = {0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x21, 0x1d, 0x5c, 0x11, 0xd6, 0x80, 0x32, 0x34, 0x22, 0x11, + 0xc2, 0x56, 0xd3, 0xc1, 0x03, 0x4a, 0xb9, 0x90, 0x13, 0x32, + 0x7f, 0xbf, 0xb4, 0x6b, 0xbd, 0x0c, 0x0e, 0xb7}}; + +const ECC_NISTP224_Param ECC_NISTP224_generatorY = {.byte = { + 0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x34, 0x7e, 0x00, 0x85, 0x99, 0x81, 0xd5, 0x44, 0x64, 0x47, + 0x07, 0x5a, 0xa0, 0x75, 0x43, 0xcd, 0xe6, 0xdf, 0x22, 0x4c, + 0xfb, 0x23, 0xf7, 0xb5, 0x88, 0x63, 0x37, 0xbd, + }}; + +const ECC_NISTP224_Param ECC_NISTP224_prime = {.byte = {0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const ECC_NISTP224_Param ECC_NISTP224_a = {.byte = {0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const ECC_NISTP224_Param ECC_NISTP224_b = {.byte = {0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xb4, 0xff, 0x55, 0x23, 0x43, 0x39, 0x0b, 0x27, 0xba, 0xd8, + 0xbf, 0xd7, 0xb7, 0xb0, 0x44, 0x50, 0x56, 0x32, 0x41, 0xf5, + 0xab, 0xb3, 0x04, 0x0c, 0x85, 0x0a, 0x05, 0xb4}}; + +const ECC_NISTP224_Param ECC_NISTP224_order = {.byte = {0x07, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x3d, 0x2a, 0x5c, 0x5c, 0x45, 0x29, 0xdd, 0x13, 0x3e, 0xf0, + 0xb8, 0xe0, 0xa2, 0x16, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +/* + * Curve params in Montgomery domain are used for public key validation only + * and are not prefixed with a length word. + */ +/* Invert of square of Montgomery constant, k = 2^(224) mod p, p is the curve prime */ +const ECC_NISTP224_Param ECC_NISTP224_k_mont = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00}}; + +/* Converted to Montgomery domain by modular multiplication of ECC_NISTP224_a with ECC_NISTP224_k_mont */ +const ECC_NISTP224_Param ECC_NISTP224_a_mont = {.byte = {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}}; + +/* Converted to Montgomery domain by modular multiplication of ECC_NISTP224_b with ECC_NISTP224_k_mont */ +const ECC_NISTP224_Param ECC_NISTP224_b_mont = {.byte = {0xF7, 0xCD, 0x68, 0xE7, 0x10, 0x13, 0xF0, 0xCC, 0xC0, 0x1C, + 0x3B, 0x74, 0x50, 0x81, 0x52, 0xC8, 0x98, 0xBA, 0xCE, 0x3D, + 0x93, 0x2F, 0xC0, 0x7F, 0x33, 0xA6, 0x3F, 0x9C}}; + +const ECCParams_CurveParams ECCParams_NISTP224 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = ECCParams_NISTP224_LENGTH, + .prime = ECC_NISTP224_prime.byte, + .order = ECC_NISTP224_order.byte, + .a = ECC_NISTP224_a.byte, + .b = ECC_NISTP224_b.byte, + .generatorX = ECC_NISTP224_generatorX.byte, + .generatorY = ECC_NISTP224_generatorY.byte, + .cofactor = 1}; + +/* + * Curve25519 curve params in little endian format. + * byte[0-3] are the param length word as required by the ECC SW library. + * byte[4] is the least significant byte of the curve parameter. + */ +const ECC_Curve25519_Param ECC_Curve25519_generatorX = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_generatorY = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}; + +const ECC_Curve25519_Param ECC_Curve25519_prime = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const ECC_Curve25519_Param ECC_Curve25519_a = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_b = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_order = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECCParams_CurveParams ECCParams_Curve25519 = {.curveType = ECCParams_CURVE_TYPE_MONTGOMERY, + .length = ECCParams_CURVE25519_LENGTH, + .prime = ECC_Curve25519_prime.byte, + .order = ECC_Curve25519_order.byte, + .a = ECC_Curve25519_a.byte, + .b = ECC_Curve25519_b.byte, + .generatorX = ECC_Curve25519_generatorX.byte, + .generatorY = ECC_Curve25519_generatorY.byte, + .cofactor = 1}; + +/* + * ======== ECCParams_formatCurve25519PrivateKey ======== + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey) +{ + myPrivateKey->u.plaintext.keyMaterial[31] &= 0xF8; + myPrivateKey->u.plaintext.keyMaterial[0] &= 0x7F; + myPrivateKey->u.plaintext.keyMaterial[0] |= 0x40; + + return ECCParams_STATUS_SUCCESS; +} + +/* + * ======== ECCParams_getUncompressedGeneratorPoint ======== + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length) +{ + + size_t paramLength = curveParams->length; + size_t pointLength = (paramLength * 2) + 1; + + if (length < pointLength) + { + return ECCParams_STATUS_ERROR; + } + + /* Reverse and concatenate x and y */ + uint32_t i = 0; + for (i = 0; i < paramLength; i++) + { + buffer[i + 1] = curveParams->generatorX[paramLength + ECC_LENGTH_PREFIX_BYTES - i - 1]; + buffer[i + 1 + paramLength] = curveParams->generatorY[paramLength + ECC_LENGTH_PREFIX_BYTES - i - 1]; + } + + buffer[0] = 0x04; + /* Fill the remaining buffer with 0 if needed */ + memset(buffer + pointLength, 0, length - pointLength); + + return ECCParams_STATUS_SUCCESS; +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c new file mode 100644 index 00000000..1fefad19 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* Crypto driver semaphore used to control access to the AES engine */ +SemaphoreP_Struct CryptoResourceLPF3_accessSemaphore; +SemaphoreP_Struct CryptoResourceLPF3_operationSemaphore; + +HwiP_Struct CryptoResourceLPF3_hwi; + +static bool CryptoResourceLPF3_isInitialized = false; + +static void errorSpin(uintptr_t arg) +{ + while (1) {} +} + +void CryptoResourceLPF3_constructRTOSObjects(void) +{ + HwiP_Params hwiParams; + uintptr_t key; + + key = HwiP_disable(); + + if (!CryptoResourceLPF3_isInitialized) + { + /* + * Construct the common Hwi with a dummy ISR function. This should not + * matter as the function is set whenever we start an operation after + * pending on CryptoResourceLPF3_accessSemaphore. + */ + HwiP_Params_init(&hwiParams); + hwiParams.priority = (uint32_t)~0U; + hwiParams.enableInt = false; + (void)HwiP_construct(&CryptoResourceLPF3_hwi, INT_AES_COMB, errorSpin, &hwiParams); + + (void)SemaphoreP_constructBinary(&CryptoResourceLPF3_accessSemaphore, 1U); + (void)SemaphoreP_constructBinary(&CryptoResourceLPF3_operationSemaphore, 0U); + + CryptoResourceLPF3_isInitialized = true; + } + + HwiP_restore(key); +} + +bool CryptoResourceLPF3_acquireLock(uint32_t timeout) +{ + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceLPF3_accessSemaphore, timeout); + + return (resourceAcquired == SemaphoreP_OK); +} + +void CryptoResourceLPF3_releaseLock(void) +{ + SemaphoreP_post(&CryptoResourceLPF3_accessSemaphore); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.h new file mode 100644 index 00000000..576e888d --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoResourceLPF3.h + * + * @brief Shared resources to arbitrate access to the AES engine + * + */ + +#ifndef ti_drivers_cryptoutils_sharedresources_CryptoResourceLPF3__include +#define ti_drivers_cryptoutils_sharedresources_CryptoResourceLPF3__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Crypto driver semaphore used to synchronize accesses to the AES engine */ +extern SemaphoreP_Struct CryptoResourceLPF3_accessSemaphore; +extern SemaphoreP_Struct CryptoResourceLPF3_operationSemaphore; + +extern volatile bool CryptoResourceLPF3_pollingFlag; + +extern HwiP_Struct CryptoResourceLPF3_hwi; + +void CryptoResourceLPF3_constructRTOSObjects(void); +void CryptoResourceLPF3_destructRTOSObjects(void); +bool CryptoResourceLPF3_acquireLock(uint32_t timeout); +void CryptoResourceLPF3_releaseLock(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_sharedresources_CryptoResourceLPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.c new file mode 100644 index 00000000..83f7ffc4 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.c @@ -0,0 +1,572 @@ +/* + * Copyright (c) 2019-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include + +#if defined(__GNUC__) || defined(__clang__) + #define CRYPTOUTILS_NOINLINE __attribute__((noinline)) +#else + #define CRYPTOUTILS_NOINLINE +#endif + +#define CryptoUtils_LIMIT_MASK (0xFFFFFFFEu) + +/* + * These constants take values at the very top of the memory map where it is unreasonable + * for an application to have stored a different number value. + */ +#define CryptoUtils_LIMIT_ZERO 0xFFFFFFFEu +#define CryptoUtils_LIMIT_ONE 0xFFFFFFFFu + +const uint8_t *CryptoUtils_limitZero = (uint8_t *)CryptoUtils_LIMIT_ZERO; +const uint8_t *CryptoUtils_limitOne = (uint8_t *)CryptoUtils_LIMIT_ONE; + +/* + * ======== CryptoUtils_buffersMatch ======== + */ +#if defined(__IAR_SYSTEMS_ICC__) + #pragma inline = never +#elif defined(__TI_COMPILER_VERSION__) && !defined(__cplusplus) + #pragma FUNC_CANNOT_INLINE(CryptoUtils_buffersMatch) +#elif defined(__TI_COMPILER_VERSION__) + #pragma FUNC_CANNOT_INLINE +#endif +CRYPTOUTILS_NOINLINE bool CryptoUtils_buffersMatch(const volatile void *volatile buffer0, + const volatile void *volatile buffer1, + size_t bufferByteLength) +{ + volatile uint8_t tempResult = 0; + uint8_t byte0; + uint8_t byte1; + size_t i; + + /* XOR each byte of the buffer together and OR the results. + * If the OR'd result is non-zero, the buffers do not match. + * There is no branch based on the content of the buffers here to avoid + * timing attacks. + */ + for (i = 0; i < bufferByteLength; i++) + { + byte0 = ((uint8_t *)buffer0)[i]; + byte1 = ((uint8_t *)buffer1)[i]; + + tempResult |= byte0 ^ byte1; + } + + return tempResult == 0; +} + +/* + * ======== CryptoUtils_buffersMatchWordAligned ======== + */ +#if defined(__IAR_SYSTEMS_ICC__) + #pragma inline = never +#elif defined(__TI_COMPILER_VERSION__) && !defined(__cplusplus) + #pragma FUNC_CANNOT_INLINE(CryptoUtils_buffersMatchWordAligned) +#elif defined(__TI_COMPILER_VERSION__) + #pragma FUNC_CANNOT_INLINE +#endif +CRYPTOUTILS_NOINLINE bool CryptoUtils_buffersMatchWordAligned(const volatile uint32_t *volatile buffer0, + const volatile uint32_t *volatile buffer1, + size_t bufferByteLength) +{ + volatile uint32_t tempResult = 0; + uint32_t word0; + uint32_t word1; + size_t i; + + /* We could skip the branch and just set tempResult equal to the + * statement below for the same effect but this is more explicit. + */ + if (bufferByteLength % sizeof(uint32_t) != 0) + { + return false; + } + + /* XOR each 32-bit word of the buffer together and OR the results. + * If the OR'd result is non-zero, the buffers do not match. + * There is no branch based on the content of the buffers here to avoid + * timing attacks. + */ + for (i = 0; i < bufferByteLength / sizeof(uint32_t); i++) + { + word0 = buffer0[i]; + word1 = buffer1[i]; + + tempResult |= word0 ^ word1; + } + + return tempResult == 0; +} + +/* + * ======== CryptoUtils_reverseBufferBytewise ======== + */ +void CryptoUtils_reverseBufferBytewise(void *buffer, size_t bufferByteLength) +{ + uint8_t *bufferLow = buffer; + uint8_t *bufferHigh = bufferLow + bufferByteLength - 1; + uint8_t tmp; + + while (bufferLow < bufferHigh) + { + tmp = *bufferLow; + *bufferLow = *bufferHigh; + *bufferHigh = tmp; + bufferLow++; + bufferHigh--; + } +} + +/* + * ======== CryptoUtils_isBufferAllZeros ======== + */ +bool CryptoUtils_isBufferAllZeros(const void *buffer, size_t bufferByteLength) +{ + uint32_t i; + uint8_t bufferBits = 0; + + for (i = 0; i < bufferByteLength; i++) + { + bufferBits |= ((uint8_t *)buffer)[i]; + } + + return bufferBits == 0; +} + +/* + * ======== CryptoUtils_memset ======== + */ +void CryptoUtils_memset(void *dest, size_t destSize, uint8_t val, size_t count) +{ + DebugP_assert(dest); + DebugP_assert(count <= destSize); + + volatile uint8_t *volatile p = (volatile uint8_t *)dest; + + while (destSize-- && count--) + { + *p++ = val; + } +} + +/* + * ======== CryptoUtils_copyPad ======== + */ +void CryptoUtils_copyPad(const void *source, uint32_t *destination, size_t sourceLength) +{ + uint32_t i; + uint8_t remainder; + uint32_t temp; + uint8_t *tempBytePointer; + const uint8_t *sourceBytePointer; + + remainder = sourceLength % sizeof(uint32_t); + temp = 0; + tempBytePointer = (uint8_t *)&temp; + sourceBytePointer = (uint8_t *)source; + + /* Copy source to destination starting at the end of source and the + * beginning of destination. + * We assemble each word in normal order and write one word at a + * time since the PKA_RAM requires word-aligned reads and writes. + */ + + for (i = 0; i < sourceLength / sizeof(uint32_t); i++) + { + uint32_t sourceOffset = sizeof(uint32_t) * i; + + tempBytePointer[0] = sourceBytePointer[sourceOffset + 0]; + tempBytePointer[1] = sourceBytePointer[sourceOffset + 1]; + tempBytePointer[2] = sourceBytePointer[sourceOffset + 2]; + tempBytePointer[3] = sourceBytePointer[sourceOffset + 3]; + + *(destination + i) = temp; + } + + /* Reset to 0 so we do not have to zero-out individual bytes */ + temp = 0; + + /* If sourceLength is not a word-multiple, we need to copy over the + * remaining bytes and zero pad the word we are writing to PKA_RAM. + */ + if (remainder == 1) + { + + tempBytePointer[0] = sourceBytePointer[0]; + + /* i is reused from the loop above. This write zero-pads the + * destination buffer to word-length. + */ + *(destination + i) = temp; + } + else if (remainder == 2) + { + + tempBytePointer[0] = sourceBytePointer[0]; + tempBytePointer[1] = sourceBytePointer[1]; + + *(destination + i) = temp; + } + else if (remainder == 3) + { + + tempBytePointer[0] = sourceBytePointer[0]; + tempBytePointer[1] = sourceBytePointer[1]; + tempBytePointer[2] = sourceBytePointer[2]; + + *(destination + i) = temp; + } +} + +/* + * ======== CryptoUtils_reverseCopyPad ======== + */ +void CryptoUtils_reverseCopyPad(const void *source, uint32_t *destination, size_t sourceLength) +{ + uint32_t i; + uint8_t remainder; + uint32_t temp; + uint8_t *tempBytePointer; + const uint8_t *sourceBytePointer; + + remainder = sourceLength % sizeof(uint32_t); + temp = 0; + tempBytePointer = (uint8_t *)&temp; + sourceBytePointer = (uint8_t *)source; + + /* Copy source to destination starting at the end of source and the + * beginning of destination. + * We assemble each word in byte-reversed order and write one word at a + * time since the PKA_RAM requires word-aligned reads and writes. + */ + + for (i = 0; i < sourceLength / sizeof(uint32_t); i++) + { + uint32_t sourceOffset = sourceLength - 1 - sizeof(uint32_t) * i; + + tempBytePointer[3] = sourceBytePointer[sourceOffset - 3]; + tempBytePointer[2] = sourceBytePointer[sourceOffset - 2]; + tempBytePointer[1] = sourceBytePointer[sourceOffset - 1]; + tempBytePointer[0] = sourceBytePointer[sourceOffset - 0]; + + *(destination + i) = temp; + } + + /* Reset to 0 so we do not have to zero-out individual bytes */ + temp = 0; + + /* If sourceLength is not a word-multiple, we need to copy over the + * remaining bytes and zero pad the word we are writing to PKA_RAM. + */ + if (remainder == 1) + { + + tempBytePointer[0] = sourceBytePointer[0]; + + /* i is reused from the loop above. This write zero-pads the + * destination buffer to word-length. + */ + *(destination + i) = temp; + } + else if (remainder == 2) + { + + tempBytePointer[0] = sourceBytePointer[1]; + tempBytePointer[1] = sourceBytePointer[0]; + + *(destination + i) = temp; + } + else if (remainder == 3) + { + + tempBytePointer[0] = sourceBytePointer[2]; + tempBytePointer[1] = sourceBytePointer[1]; + tempBytePointer[2] = sourceBytePointer[0]; + + *(destination + i) = temp; + } +} + +/* + * ======== CryptoUtils_reverseCopy ======== + */ +void CryptoUtils_reverseCopy(const void *source, void *destination, size_t sourceLength) +{ + /* + * If destination address is word-aligned and source length is a word-multiple, + * use CryptoUtils_reverseCopyPad() for better efficiency. + */ + if ((((uint32_t)destination | sourceLength) & 0x3) == 0) + { + CryptoUtils_reverseCopyPad(source, (uint32_t *)destination, sourceLength); + } + else + { + const uint8_t *sourceBytePtr = (const uint8_t *)source; + uint8_t *dstBytePtr = (uint8_t *)destination + sourceLength - 1; + + /* + * Copy source to destination starting at the end of source and the + * beginning of destination. + */ + while (sourceLength--) + { + *dstBytePtr-- = *sourceBytePtr++; + } + } +} + +/* limitValue must be either CryptoUtils_LIMIT_ZERO or CryptoUtils_LIMIT_ONE */ +static int16_t CryptoUtils_convertLimitValueToInt(const void *limitValue) +{ + int16_t value = 0; + + if (limitValue == CryptoUtils_limitOne) + { + value = 1; + } + + return value; +} + +/* + * Returns number1[offset] - number2[offset]. + * + * Can handle one of number1 or number2 (but not both) being one of the special limit values of + * CryptoUtils_LIMIT_ZERO or CryptoUtils_LIMIT_ONE. + * + * All pointer parameters must be non-NULL. + */ +static int16_t CryptoUtils_diffAtOffset(const uint8_t number1[], + const uint8_t number2[], + size_t offset, + size_t lsbOffset) +{ + + int16_t diff; + + /* Look at number2 first, as it will be more common for number2 to be one of the limit values. */ + if (number2 == CryptoUtils_limitZero) + { + diff = (int16_t)number1[offset]; + } + else if (number2 == CryptoUtils_limitOne) + { + if (offset == lsbOffset) + { + diff = (int16_t)number1[offset] - 1; + } + else + { + diff = (int16_t)number1[offset]; + } + } + else if (number1 == CryptoUtils_limitZero) + { + diff = 0 - (int16_t)number1[offset]; + } + else if (number1 == CryptoUtils_limitOne) + { + if (offset == lsbOffset) + { + diff = 1 - (int16_t)number1[offset]; + } + else + { + diff = 0 - (int16_t)number1[offset]; + } + } + else + { + diff = (int16_t)number1[offset] - (int16_t)number2[offset]; + } + + return diff; +} + +/* Uses a timing constant algorithm to return 0 if value is 0 and return 1 otherwise. */ +static uint16_t CryptoUtils_valueNonZeroTimingConstantCheck(int16_t value) +{ + uint16_t valueNonZero; + + /* Mask and shift bits such that if any bit in value is '1' then the + lsb of valueNonZero is 1 and otherwise valueNonZero is 0. */ + valueNonZero = (((uint16_t)value & 0xFF00u) >> 8u) | ((uint8_t)value & 0xFFu); + valueNonZero = ((valueNonZero & 0xF0u) >> 4u) | (valueNonZero & 0x0Fu); + valueNonZero = ((valueNonZero & 0x0Cu) >> 2u) | (valueNonZero & 0x03u); + valueNonZero = ((valueNonZero & 0x02u) >> 1u) | (valueNonZero & 0x01u); + + return valueNonZero; +} + +/* + * Returns sign of number1 - number2: + * negative value if number2 is larger, positive value if number1 is larger and zero if numbers are equal. + * + * Note that the magnitude of the return value has no meaning. + * + * The comparison is performed with a time-constant algorithm with respect to either of the number + * arguments (number1, number2) when those inputs are not CryptoUtils_limitZero or CryptoUtils_limitOne. + * + * All pointer parameters must be non-NULL. + */ +static int16_t CryptoUtils_compareNumbers(const uint8_t number1[], + const uint8_t number2[], + size_t byteLength, + CryptoUtils_Endianess endianess) +{ + int16_t result = 0x0; + int16_t diff; + uint16_t diffNonZero; + uint16_t diffResultMask; + uint16_t resultUnknown = 0xFFFFu; + uintptr_t number1Address; + uintptr_t number2Address; + size_t i; + + number1Address = (uintptr_t)number1; + number2Address = (uintptr_t)number2; + + /* + * Check if special RNG_limit values are being used for both values. + * This is not expected, but is handled for completeness. + */ + if (((number1Address & CryptoUtils_LIMIT_MASK) == CryptoUtils_LIMIT_MASK) && + ((number2Address & CryptoUtils_LIMIT_MASK) == CryptoUtils_LIMIT_MASK)) + { + + result = CryptoUtils_convertLimitValueToInt(number1) - CryptoUtils_convertLimitValueToInt(number2); + } + else if (number1 != number2) + { + if (endianess == CryptoUtils_ENDIANESS_BIG) + { + i = 0u; + while (i < byteLength) + { + diff = CryptoUtils_diffAtOffset(number1, number2, i, byteLength - 1); + + /* Update result only if result was not known and is thus currently set to 0. */ + result = (int16_t)((uint16_t)result | (resultUnknown & (uint16_t)diff)); + + /* + * Determine if result is now known and update resultUnknown + */ + + diffNonZero = CryptoUtils_valueNonZeroTimingConstantCheck(diff); + + /* Create mask where mask value is 0 if bytes were equal, otherwise mask is all 1s. */ + diffResultMask = diffNonZero - 1u; + + /* Set resultUnknown to 0 (indicating result is known) if bytes were not equal. */ + resultUnknown &= diffResultMask; + + i++; + } + } + else + { + i = byteLength; + while (i > 0u) + { + i--; + + diff = CryptoUtils_diffAtOffset(number1, number2, i, 0); + + /* Update result only if result was not known and is thus currently set to 0. */ + result = (int16_t)((uint16_t)result | (resultUnknown & (uint16_t)diff)); + + /* + * Determine if result is now known and update resultUnknown + */ + diffNonZero = CryptoUtils_valueNonZeroTimingConstantCheck(diff); + + /* Create mask where mask value is 0 if bytes were equal, otherwise mask is all 1s. */ + diffResultMask = diffNonZero - 1u; + + /* Set resultUnknown to 0 (indicating result is known) if bytes were not equal. */ + resultUnknown &= diffResultMask; + } + } + } + else + { + result = 0; + } + + return result; +} + +/* + * ======== CryptoUtils_isNumberInRange ======== + */ +bool CryptoUtils_isNumberInRange(const void *number, + size_t bitLength, + CryptoUtils_Endianess endianess, + const void *lowerLimit, + const void *upperLimit) +{ + int16_t upperResult; + int16_t lowerResult; + bool inUpperLimit = true; + bool inLowerLimit = true; + size_t byteLength; + + byteLength = (bitLength + 7u) >> 3u; + + if (upperLimit != NULL) + { + upperResult = CryptoUtils_compareNumbers(number, upperLimit, byteLength, endianess); + if (upperResult >= 0) + { + inUpperLimit = false; + } + } + + if (lowerLimit != NULL) + { + lowerResult = CryptoUtils_compareNumbers(number, lowerLimit, byteLength, endianess); + if (lowerResult < 0) + { + inLowerLimit = false; + } + } + + return (inUpperLimit && inLowerLimit); +} diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.h new file mode 100644 index 00000000..0b2350f5 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/utils/CryptoUtils.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoUtils.h + * + * @brief A collection of utility functions for cryptographic purposes + * + */ + +#ifndef ti_drivers_cryptoutils_utils_CryptoUtils__include +#define ti_drivers_cryptoutils_utils_CryptoUtils__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Indicates the endianess (byte order) of a multi-byte value. + */ +typedef enum +{ + CryptoUtils_ENDIANESS_BIG = 0u, /*!< MSB at lowest address. */ + CryptoUtils_ENDIANESS_LITTLE = 1u, /*!< LSB at highest address. */ +} CryptoUtils_Endianess; + +/*! + * @brief Limit value of 0 + * + * This is a value provided for convenience when checking a value + * against a range. + * + * @sa CryptoUtils_limitOne + * @sa CryptoUtils_isNumberInRange + */ +extern const uint8_t *CryptoUtils_limitZero; + +/*! + * @brief Limit value of 1 + * + * This is a value provided for convenience when checking a value + * against a range. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_isNumberInRange + */ +extern const uint8_t *CryptoUtils_limitOne; + +/** + * @brief Compares two buffers for equality without branching + * + * @note This is not a drop-in replacement for memcmp! + * + * Most memcmp implementations break out of their comparison loop immediately + * once a mismatch is detected to save execution time. For cryptographic + * purposes, this is a flaw. + * + * This function compares two buffers without branching thus requiring a + * an amount of time that does not vary with the content of @c buffer0 and + * @c buffer1. + * + * @param buffer0 Buffer to compare against @c buffer1. + * @param buffer1 Buffer tp compare against @c buffer0 + * @param bufferByteLength Length in bytes of @c buffer0 and @c buffer1. + * @retval true The contents of the buffers match. + * @retval false The contents of the buffers do not match. + */ +bool CryptoUtils_buffersMatch(const volatile void *volatile buffer0, + const volatile void *volatile buffer1, + size_t bufferByteLength); + +/** + * @brief Compares two buffers for equality word-by-word without branching + * + * @note This is not a drop-in replacement for memcmp! + * + * Most memcmp implementations break out of their comparison loop immediately + * once a mismatch is detected to save execution time. For cryptographic + * purposes, this is a flaw. + * + * This function compares two buffers without branching thus requiring a + * an amount of time that does not vary with the content of @c buffer0 and + * @c buffer1. + * + * Unlike #CryptoUtils_buffersMatch(), this function expects @c buffer0 and + * @c buffer1 to be 32-bit aligned. It will only perform 32-bit aligned + * accesses to memory. This is needed to access the registers of certain + * peripherals. + * + * @param buffer0 Buffer to compare against @c buffer1. + * @param buffer1 Buffer tp compare against @c buffer0 + * @param bufferByteLength Length in bytes of @c buffer0 and @c buffer1. + * Must be evenly divisible by sizeof(uint32_t). + * This function will return false if @c + * bufferByteLength is not evenly divisible by + * sizeof(uin32_t). + * @retval true The contents of the buffers match. + * @retval false The contents of the buffers do not match. + */ +bool CryptoUtils_buffersMatchWordAligned(const volatile uint32_t *volatile buffer0, + const volatile uint32_t *volatile buffer1, + size_t bufferByteLength); + +/** + * @brief Check whether the provided buffer only contains 0x00 bytes + * + * @param buffer Buffer to search for non-zero bytes + * @param bufferByteLength Length of @c buffer in bytes + * + * @retval true The buffer contained only bytes with value 0x00 + * @retval false The buffer contained at least one non-zero byte + */ +bool CryptoUtils_isBufferAllZeros(const void *buffer, size_t bufferByteLength); + +/** + * @brief Copies @c val into the first @c count bytes of the buffer + * pointed to by @c dest. + * + * @param dest Pointer to destination buffer + * @param destSize Size of destination buffer in bytes + * @param val Fill byte value + * @param count Number of bytes to fill + * + */ +void CryptoUtils_memset(void *dest, size_t destSize, uint8_t val, size_t count); + +/** + * @brief Reverses the byte order in a buffer of a given length + * + * The left-most byte will become the right-most byte and vice versa. + * + * @param buffer Buffer containing the data to be reversed. + * @param bufferByteLength Length in bytes of @c buffer. + */ +void CryptoUtils_reverseBufferBytewise(void *buffer, size_t bufferByteLength); + +/** + * @brief Copies and pads an array of words. + * + * The \c source array is copied into the \c destination + * array. Writes are done word-wise. If \c sourceLength is not a multiple of 4, + * any remaining bytes up to the next word boundary are padded with 0. + * + * The length of the destination array must be a multiple of 4, rounded up to the + * padded \c sourceLength if required. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_copyPad(const void *source, uint32_t *destination, size_t sourceLength); + +/** + * @brief Reverses, copies, and pads an array of words. + * + * The \c source array is reversed byte-wise and copied into the \c destination + * array. Writes are done word-wise. If \c sourceLength is not a multiple of 4, + * any remaining bytes up to the next word boundary are padded with 0. + * + * The length of the destination array must be a multiple of 4, rounded up to the + * padded \c sourceLength if required. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_reverseCopyPad(const void *source, uint32_t *destination, size_t sourceLength); + +/** + * @brief Reverses and copies an array of bytes. + * + * The \c source array is reversed byte-wise and copied into the \c destination + * array. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_reverseCopy(const void *source, void *destination, size_t sourceLength); + +/** + * @brief Checks if number is within the range [lowerLimit, upperLimit) + * + * Checks if the specified number is at greater than or equal to + * the lower limit and less than the upper limit. Note that the boundary + * set by the upper limit is not inclusive. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the @c lowerLimit. + * (These values can also be used for the @c upperLimit but their use for + * the upperLimit has no practical use.) + * + * If @c lowerLimit is NULL then the lower limit is taken as 0. + * If @c upperLimit is NULL then the upper limit is taken as + * 2(@c bitLength + 1). + * + * The implemented algorithm is timing-constant when the following parameters + * are held constant: @c lowerLimit, @c upperLimit, @c bitLength, + * and @c endianess. Thus, the @c number being checked may change and + * timing will not leak its relation to the limits. However, timing may leak + * the bitLength, the endianess, and the use of #CryptoUtils_limitZero, + * #CryptoUtils_limitOne, and NULL for the limit values. + * + * @param number Pointer to number to check + * @param bitLength Length in bits of @c number, @c lowerLimit, and + * @c upperLimit. + * @param endianess The endianess of @c number, @c lowerLimit, and + * @c upperLimit. + * @param lowerLimit Pointer to lower limit value. + * @param upperLimit Pointer to upper limit value. + * @retval true The randomNumber is within + * [@c lowerLimit, @c upperLimit). + * @retval false The randomNumber is not within + * [@c lowerLimit, @c upperLimit). + */ +bool CryptoUtils_isNumberInRange(const void *number, + size_t bitLength, + CryptoUtils_Endianess endianess, + const void *lowerLimit, + const void *upperLimit); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_utils_CryptoUtils__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c new file mode 100644 index 00000000..f72d67e0 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021 - 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/udma.h) + +/* Externs */ +extern const UDMALPF3_Config UDMALPF3_config; + +static void UDMALPF3_initHw(void); +static int UDMALPF3_postNotifyFxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +static bool isOpen = false; +static Power_NotifyObj postNotify; + +/* + * ======== UDMACC26XX_init ======== + * + */ +void UDMALPF3_init(void) +{ + /* Init the DMA HW only once */ + if (!isOpen) + { + isOpen = true; + + /* Register power notification function */ + Power_registerNotify(&postNotify, PowerLPF3_AWAKE_STANDBY, UDMALPF3_postNotifyFxn, (uintptr_t)NULL); + + /* Power up and enable clocks for uDMA. */ + Power_setDependency(PowerLPF3_PERIPH_DMA); + + /* initialize the UDMALPF3 hardware */ + UDMALPF3_initHw(); + + /* Disable clock on the DMA peripheral */ + Power_releaseDependency(PowerLPF3_PERIPH_DMA); + } +} + +/* + * ======== UDMACC26XX_initHw ======== + * This functions initializes the UDMACC26XX hardware module. + * + */ +static void UDMALPF3_initHw(void) +{ + /* Disable all channels */ + UDMALPF3_channelDisable(0xFF); + + /* clear the error register */ + uDMAClearErrorStatus(); + + /* Set the base for the channel control table. */ + uDMASetControlBase((void *)UDMALPF3_config.CtrlBaseAddr); + + /* Enable uDMA. */ + uDMAEnable(); +} + +/* + * ======== UDMALPF3_postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int UDMALPF3_postNotifyFxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + /* Reconfigure the hardware if returning from sleep */ + if (eventType == PowerLPF3_AWAKE_STANDBY) + { + /* Power up and enable clocks for uDMA. */ + Power_setDependency(PowerLPF3_PERIPH_DMA); + + /* initialize the UDMACC26XX hardware */ + UDMALPF3_initHw(); + + /* Disable clock on the DMA peripheral */ + Power_releaseDependency(PowerLPF3_PERIPH_DMA); + } + + return (Power_NOTIFYDONE); +} \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h new file mode 100644 index 00000000..43f68ce6 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UDMALPF3.h + * + * @brief UDMALPF3 driver implementation. + * + * # Driver include # + * The UDMALPF3 header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The UDMALPF3 driver currently only supports internal use by the drivers + * that use the uDMA peripheral (e.g., SPILPF3DMA). + * In other words, the application should never call any of the functions in this + * file. + * + * # General Behavior # + * This driver is used implicitly by other drivers (e.g., the SPILPF3DMA + * driver) so users should not have to interface to this driver from the + * application. + * The uDMA hardware makes use of a control table in RAM which must be 1024 bytes + * aligned. The default base address of this control table is 0x20000400, however + * this can be changed simply by defining UDMALPF3_CONFIG_BASE. + * The SPILPF3DMA.h supports SPI0, and uses both TX and RX DMA channels. + * Each control table entry is 16 bytes, so if an application uses SPI0 + * the total RAM usage will be 2*16=32 bytes. Please see [Use cases] (@ref + * UDMA_23XX_USE_CASES) for example. + * + * # Error handling # + * Error handling is handled by the overlying driver which uses the DMA. + * + * # Power management # + * Power management is handled by the overlying driver which uses the DMA. + * + * # Supported functions # + * Note that these functions should never be called from the application, they + * are only called from other drivers. They are however included here for completeness: + * + * | API function | Description | + * |------------------------- |------------------------------------------------| + * | UDMALPF3_init() | Initialize the uDMA HW. | + * + * @note These functions should not be called by code. These functions are called + * by drivers using the DMA. + * + * # Unsupported Functionality # + * No known limitations + * + * # Use Cases @anchor UDMA_23XX_USE_CASES # + * In a system that has available SPI and UART peripherals, the following + * scenarios are possible: + * @code + * #define UDMALPF3_CONFIG_BASE 0x20000400 + * @endcode + * - If only SPI0 is used (with TX mapped on channel 0 and RX mapped on channel + * 1), this will allocate 2*16=32 RAM bytes at address:\n + * [0x20000400-0x2000041F] = SPI0 RX/TX DMA channels + * - If only UART0 (with TX mapped on channel 2 and RX mapped on channel 3) is + * used, this will allocate 2*16=32 RAM bytes at address:\n + * [0x20000420-0x2000043F] = UART0 RX/TX DMA channels + * - If both SPI0 and UART0 are used, this will allocate 4*16=64 RAM bytes at addresses:\n + * [0x20000400-0x2000041F] = SPI0 RX/TX DMA channels\n + * [0x20000420-0x2000043F] = UART0 RX/TX DMA channels + * + * ============================================================================ + */ + +#ifndef ti_drivers_UDMALPF3__include +#define ti_drivers_UDMALPF3__include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/udma.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Base address for the DMA control table, must be 1024 bytes aligned */ +#if !defined(UDMALPF3_CONFIG_BASE) + #define UDMALPF3_CONFIG_BASE 0x20000400 +#endif + +/*! Make sure DMA control table base address is 1024 bytes aligned */ +#if (UDMALPF3_CONFIG_BASE & 0x3FF) + #error "Base address for DMA control table 'UDMALPF3_CONFIG_BASE' must be 1024 bytes aligned." +#endif + +/*! Compiler specific macros to allocate DMA control table entries */ +#if defined(__IAR_SYSTEMS_ICC__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + __no_init __root static volatile uDMAControlTableEntry ENTRY_NAME @UDMALPF3_CONFIG_BASE + \ + (CHANNEL_INDEX) * sizeof(uDMAControlTableEntry) +#elif defined(__TI_COMPILER_VERSION__) || defined(__clang__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + static volatile uDMAControlTableEntry ENTRY_NAME \ + __attribute__((retain, \ + location((UDMALPF3_CONFIG_BASE) + (CHANNEL_INDEX) * sizeof(uDMAControlTableEntry)))) +#elif defined(__GNUC__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + extern int UDMALPF3_##ENTRY_NAME##_is_placed; \ + __attribute__((section("." #ENTRY_NAME), used)) static volatile uDMAControlTableEntry ENTRY_NAME = { \ + &UDMALPF3_##ENTRY_NAME##_is_placed} +#else + #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain" +#endif + +/*! Sets the DMA transfer size in number of items */ +#define UDMALPF3_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) +/*! Gets the DMA transfer size in number of items*/ +#define UDMALPF3_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1) + +/*! + * @brief UDMALPF3 Global configuration + */ +typedef struct +{ + uint32_t CtrlBaseAddr; /*!< Base adddress for UDMALPF3 control table*/ +} UDMALPF3_Config; + +/* Externs from ti_drivers_config.c */ +extern const UDMALPF3_Config UDMALPF3_config; + +/*! + * @brief Function to initialize the LPF3 DMA driver and peripheral + * + * The function will initialize the DMA peripheral and set the Control table + * base address. The call powers up and clocks the DMA module only during + * initialization. Each driver using DMA must set a power dependency + * on the module before starting to use it (e.g. when opening the driver) and + * release that dependency when DMA is no longer needed (e.g. when closing the + * driver). + * + * @pre Calling context: Hwi, Swi, Task + * + * @return none + * + * @sa + */ +extern void UDMALPF3_init(void); + +/*! + * @internal + * @brief Function to enable the given DMA channel(s) + * + * @pre UDMALPF3_init() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param channelBitMask A bitmask of the channels to be enabled. + * + * @sa UDMALPF3_channelDisable + */ +__STATIC_INLINE void UDMALPF3_channelEnable(uint32_t channelBitMask) +{ + /* Enable DMA channel */ + uDMAEnableChannel(channelBitMask); +} + +/*! + * @internal + * @brief Function to check if a given DMA channel is done. + * + * Will read the request done signal for the given channels + * and return true if all channels are done, otherwise false. + * + * @pre UDMALPF3_init() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param channelBitMask A bitmask of the channels to be checked. + * + * @return True if the channels are done, false otherwise. + * + * @sa UDMALPF3_channelDisable + */ +__STATIC_INLINE bool UDMALPF3_channelDone(uint32_t channelBitMask) +{ + /* Check if REQDONE is set for the specified channels */ + return (uDMAIntStatus() & channelBitMask) ? true : false; +} + +/*! + * @internal + * @brief Function to clear a given DMA channel interrupt. + * + * Will clear the DMA interrupt(s) for the given bitmask provided. + * + * @pre Calling context: Hwi, Swi, Task + * + * @param channelBitMask A bitmask of the channels to clear interrupts for. + * + * @return none + */ +__STATIC_INLINE void UDMALPF3_clearInterrupt(uint32_t channelBitMask) +{ + /* Clear UDMA done interrupt */ + uDMAClearInt(channelBitMask); +} + +/*! + * @internal + * @brief Function to disable one or more DMA channels. + * + * Will disable the channel(s) for the given bitmask provided. + * + * @pre Calling context: Hwi, Swi, Task + * + * @param channelBitMask A bitmask of the channels to be disabled. + * + * @return none + * + * @sa UDMALPF3_channelEnable + */ +__STATIC_INLINE void UDMALPF3_channelDisable(uint32_t channelBitMask) +{ + /* Disable provided channels(s) */ + uDMADisableChannel(channelBitMask); +} + +/*! + * @internal + * @brief Function to disable a DMA channel's attributes. + * + * Will disable a channel's attributes. + * + * @pre Calling context: Hwi, Swi, Task + * + * @param channelBitMask A bitmask of the channels to configure. + * + * @param attr Channel attribute to disable. + * + * + * @return none + * + * @sa UDMALPF3_channelEnable + */ +__STATIC_INLINE void UDMALPF3_disableAttribute(uint32_t channelBitMask, uint32_t attr) +{ + /* disable provided attribute for the given channel */ + uDMADisableChannelAttribute(channelBitMask, attr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UDMALPF3__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dma/dma.ld b/simplelink_lpf3/source/ti/drivers/dma/dma.ld new file mode 100644 index 00000000..98bb1dc0 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dma/dma.ld @@ -0,0 +1,70 @@ +/* + * UDMALPF3_CONFIG_BASE below must match UDMALPF3_CONFIG_BASE defined + * by ti/drivers/dma/UDMALPF3.h + * The user is allowed to change UDMALPF3_CONFIG_BASE to move it away from + * the default address 0x2000_0400, but remember it must be 1024 bytes aligned. + */ + UDMALPF3_CONFIG_BASE = 0x20000400; + + /* + * Define absolute addresses for the DMA channels. + * DMA channels must always be allocated at a fixed offset from the DMA base address. + * --------- DO NOT MODIFY ----------- + */ + DMA_CHANNEL0_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x00); + DMA_CHANNEL1_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x10); + DMA_CHANNEL2_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x20); + DMA_CHANNEL3_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x30); + DMA_CHANNEL4_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x40); + DMA_CHANNEL5_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x50); + DMA_CHANNEL6_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x60); + DMA_CHANNEL7_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x70); + + /* Device has 8 DMA channels => the alt. control table is at offset 0x80 */ + DMA_CHANNEL0_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x80); + DMA_CHANNEL1_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0x90); + DMA_CHANNEL2_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xA0); + DMA_CHANNEL3_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xB0); + DMA_CHANNEL4_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xC0); + DMA_CHANNEL5_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xD0); + DMA_CHANNEL6_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xE0); + DMA_CHANNEL7_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMALPF3_CONFIG_BASE + 0xF0); + + + /* + * Allocate Channel n descriptors at absolute addresses. + * --------- DO NOT MODIFY ----------- + */ + UDMALPF3_channel0ControlTableEntry_is_placed = 0; + .dmaChannel0ControlTableEntry DMA_CHANNEL0_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL0_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel0ControlTableEntry)} > RAM + UDMALPF3_channel1ControlTableEntry_is_placed = 0; + .dmaChannel1ControlTableEntry DMA_CHANNEL1_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL1_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel1ControlTableEntry)} > RAM + UDMALPF3_channel2ControlTableEntry_is_placed = 0; + .dmaChannel2ControlTableEntry DMA_CHANNEL2_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL2_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel2ControlTableEntry)} > RAM + UDMALPF3_channel3ControlTableEntry_is_placed = 0; + .dmaChannel3ControlTableEntry DMA_CHANNEL3_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL3_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel3ControlTableEntry)} > RAM + UDMALPF3_channel4ControlTableEntry_is_placed = 0; + .dmaChannel4ControlTableEntry DMA_CHANNEL4_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL4_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel4ControlTableEntry)} > RAM + UDMALPF3_channel5ControlTableEntry_is_placed = 0; + .dmaChannel5ControlTableEntry DMA_CHANNEL5_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL5_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel5ControlTableEntry)} > RAM + UDMALPF3_channel6ControlTableEntry_is_placed = 0; + .dmaChannel6ControlTableEntry DMA_CHANNEL6_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL6_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel6ControlTableEntry)} > RAM + UDMALPF3_channel7ControlTableEntry_is_placed = 0; + .dmaChannel7ControlTableEntry DMA_CHANNEL7_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL7_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel7ControlTableEntry)} > RAM + + UDMALPF3_channel0AltControlTableEntry_is_placed = 0; + .dmaChannel0AltControlTableEntry DMA_CHANNEL0_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL0_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel0AltControlTableEntry)} > RAM + UDMALPF3_channel1AltControlTableEntry_is_placed = 0; + .dmaChannel1AltControlTableEntry DMA_CHANNEL1_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL1_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel1AltControlTableEntry)} > RAM + UDMALPF3_channel2AltControlTableEntry_is_placed = 0; + .dmaChannel2AltControlTableEntry DMA_CHANNEL2_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL2_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel2AltControlTableEntry)} > RAM + UDMALPF3_channel3AltControlTableEntry_is_placed = 0; + .dmaChannel3AltControlTableEntry DMA_CHANNEL3_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL3_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel3AltControlTableEntry)} > RAM + UDMALPF3_channel4AltControlTableEntry_is_placed = 0; + .dmaChannel4AltControlTableEntry DMA_CHANNEL4_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL4_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel4AltControlTableEntry)} > RAM + UDMALPF3_channel5AltControlTableEntry_is_placed = 0; + .dmaChannel5AltControlTableEntry DMA_CHANNEL5_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL5_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel5AltControlTableEntry)} > RAM + UDMALPF3_channel6AltControlTableEntry_is_placed = 0; + .dmaChannel6AltControlTableEntry DMA_CHANNEL6_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL6_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel6AltControlTableEntry)} > RAM + UDMALPF3_channel7AltControlTableEntry_is_placed = 0; + .dmaChannel7AltControlTableEntry DMA_CHANNEL7_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_CHANNEL7_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaChannel7AltControlTableEntry)} > RAM diff --git a/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h index e148095a..b5e3b9f0 100644 --- a/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h +++ b/simplelink_lpf3/source/ti/drivers/dpl/ClockP.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, Texas Instruments Incorporated + * Copyright (c) 2016-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -67,7 +67,7 @@ extern "C" { #endif -#define CLOCKP_TICK_PERIOD (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) +#define ClockP_TICK_PERIOD (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) /*! * @brief Prototype for a ClockP function. @@ -230,7 +230,7 @@ extern uint32_t ClockP_getSystemTicks(); * @brief Get number of ClockP tick periods expected to expire between * now and the next interrupt from the timer peripheral * - * Returns the number of ClockP tick periods that are expected to expore + * Returns the number of ClockP tick periods that are expected to expire * between now and the next interrupt from the timer peripheral. * * Used internally by PowerCC26XX module @@ -273,6 +273,16 @@ extern bool ClockP_isActive(ClockP_Handle handle); */ extern void ClockP_Params_init(ClockP_Params *params); +/*! + * @brief Function to overwrite ClockP callback function and arg + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * @param clockFxn Function called when timeout or period expires. + * @param arg Argument passed to \c clockFxn + */ +extern void ClockP_setFunc(ClockP_Handle handle, ClockP_Fxn clockFxn, uintptr_t arg); + /*! * @brief Set the initial timeout * diff --git a/simplelink_lpf3/source/ti/drivers/dpl/MutexP.h b/simplelink_lpf3/source/ti/drivers/dpl/MutexP.h new file mode 100644 index 00000000..7bc978bb --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/MutexP.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MutexP.h + * + * @brief Mutex module for the RTOS Porting Interface + * + * The MutexP module allows task to maintain critical region segments. The + * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. + * + * The MutexP module supports recursive calls to the MutexP_lock API by a + * single task. The same number of MutexP_unlock calls must be done for the + * mutex to be release. Note: the returned key must be provided in the LIFO + * order. For example: + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_MutexP__include +#define ti_dpl_MutexP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * MutexP object. + * + * nortos: 12 + * SysBIOS: 40 + */ +#define MutexP_STRUCT_SIZE (40) + +/*! + * @brief MutexP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific MutexP objects. + */ +typedef union MutexP_Struct { + uint32_t dummy; /*!< Align object */ + char data[MutexP_STRUCT_SIZE]; +} MutexP_Struct; + +/*! + * @brief Status codes for MutexP APIs + */ +typedef enum { + /*! API completed successfully */ + MutexP_OK = 0, + /*! API failed */ + MutexP_FAILURE = -1 +} MutexP_Status; + +/*! + * @brief Opaque client reference to an instance of a MutexP + * + * A MutexP_Handle returned from the ::MutexP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::MutexP_lock, + * ::MutexP_unlock, etc.). + */ +typedef void *MutexP_Handle; + +/*! + * @brief Basic MutexP Parameters + * + * Structure that contains the parameters are passed into ::MutexP_create + * when creating a MutexP instance. The ::MutexP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The MutexP default parameters are noted in + * ::MutexP_Params_init. + */ +typedef struct { + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ +} MutexP_Params; + + +/*! + * @brief Function to construct a mutex. + * + * @param handle Pointer to a MutexP_Struct object + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (MutexP default + * parameters as noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, + MutexP_Params *params); + +/*! + * @brief Function to destruct a mutex object + * + * @param mutexP Pointer to a MutexP_Struct object that was passed to + * MutexP_construct(). + * + * @return + */ +extern void MutexP_destruct(MutexP_Struct *mutexP); + +/*! + * @brief Function to create a mutex. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The MutexP default + * parameters are noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_create(MutexP_Params *params); + +/*! + * @brief Function to delete a mutex. + * + * @param handle A MutexP_Handle returned from MutexP_create + */ +extern void MutexP_delete(MutexP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * callback - NULL. + * + * @param params Pointer to the instance configuration parameters. + */ +extern void MutexP_Params_init(MutexP_Params *params); + +/*! + * @brief Function to lock a mutex. + * + * This function can only be called from a Task. It cannot be called from + * an interrupt. The lock will block until the mutex is available. + * + * Users of a mutex should make every attempt to minimize the duration that + * that they have it locked. This is to minimize latency. It is recommended + * that the users of the mutex do not block while they have the mutex locked. + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @return A key is returned. This key must be passed into ::MutexP_unlock. + */ +extern uintptr_t MutexP_lock(MutexP_Handle handle); + +/*! + * @brief Function to unlock a mutex + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. The order of + * the keys must be reversed. For example + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @param key Return from ::MutexP_lock. + */ +extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MutexP__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dpl/SemaphoreP.h b/simplelink_lpf3/source/ti/drivers/dpl/SemaphoreP.h new file mode 100644 index 00000000..6866fb92 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/SemaphoreP.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SemaphoreP.h + * + * @brief Semaphore module for the RTOS Porting Interface + * + * Semaphores can be counting semaphores or binary semaphores. Counting + * semaphores keep track of the number of times the semaphore has been posted + * with post functions. This is useful, for example, if you have a group of + * resources that are shared between tasks. Such tasks might call pend() to see + * if a resource is available before using one. A count of zero for a counting + * semaphore denotes that it is not available. A positive count denotes + * how many times a SemaphoreP_pend can be called before it is blocked (or + * returns SemaphoreP_TIMEOUT). + * + * Binary semaphores can have only two states: available (count = 1) and + * unavailable (count = 0). They can be used to share a single resource + * between tasks. They can also be used for a basic signalling mechanism, where + * the semaphore can be posted multiple times. Binary semaphores do not keep + * track of the count; they simply track whether the semaphore has been posted + * or not. + * + * ============================================================================ + */ + +#ifndef ti_dpl_SemaphoreP__include +#define ti_dpl_SemaphoreP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SemaphoreP object. + * + * nortos: 16 + * SysBIOS: 28 + */ +#define SemaphoreP_STRUCT_SIZE (28) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SemaphoreP objects. + */ +typedef union SemaphoreP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SemaphoreP_STRUCT_SIZE]; +} SemaphoreP_Struct; + +/*! + * @brief Wait forever define + */ +#define SemaphoreP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define SemaphoreP_NO_WAIT (0) + +/*! + * @brief Status codes for SemaphoreP APIs (for backwards compatibility) + */ +typedef enum { + /*! API completed successfully */ + SemaphoreP_OK = 0, + /*! API failed because of a timeout */ + SemaphoreP_TIMEOUT = -1 +} SemaphoreP_Status; + +/*! + * @brief Opaque client reference to an instance of a SemaphoreP + * + * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that + * instance and is used in the other instance based functions (e.g. + * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). + */ +typedef void *SemaphoreP_Handle; + +/*! + * @brief Mode of the semaphore + */ +typedef enum { + SemaphoreP_Mode_COUNTING = 0x0, + SemaphoreP_Mode_BINARY = 0x1 +} SemaphoreP_Mode; + +/*! + * @brief Basic SemaphoreP Parameters + * + * Structure that contains the parameters are passed into ::SemaphoreP_create + * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function + * should be used to initialize the fields to default values before the + * application sets the fields manually. The SemaphoreP default parameters are + * noted in SemaphoreP_Params_init. + */ +typedef struct { + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ +} SemaphoreP_Params; + +/*! + * @brief Default SemaphoreP instance parameters + * + * SemaphoreP_defaultParams represents the default parameters that are + * used when creating or constructing a SemaphoreP instance. + * SemaphoreP_Params_init() will use the contents of this structure for + * initializing the SemaphoreP_Params instance. + * + * SemaphoreP_defaultParams is exposed to the application for the purpose + * of allowing the application to change the default parameters for all + * SemaphoreP instances created thereafter. The main intent for allowing + * the default parameters to be changed is for setting a semaphore's + * callback function to Power_idleFunc(), so that the SOC can enter low + * power mode when pending on a semaphore. + */ +extern SemaphoreP_Params SemaphoreP_defaultParams; + + +/* + * SemaphoreP construct APIs can only be used if one of the OS's + * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also + * has to be set to 1 in FreeRTOSConfig.h. + */ +extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, + unsigned int count, SemaphoreP_Params *params); + +extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, + unsigned int count); + +extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); + +/*! + * @brief Function to create a semaphore. + * + * @param count Initial count of the semaphore. For binary semaphores, + * only values of 0 or 1 are valid. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (SemaphoreP default + * parameters as noted in ::SemaphoreP_Params_init. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, + void (*callback)(void)); + +/*! + * @brief Function to delete a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_delete(SemaphoreP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - mode: SemaphoreP_Mode_COUNTING + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SemaphoreP_Params_init(SemaphoreP_Params *params); + +/*! + * @brief Function to pend (wait) on a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to + * be posted (signalled). + * + * @return Status of the functions + * - SemaphoreP_OK: Obtained the semaphore + * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. + */ +extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, + uint32_t timeout); + +/*! + * @brief Function to post (signal) a semaphore from task of ISR context. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_post(SemaphoreP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/simplelink_lpf3/source/ti/drivers/dpl/SwiP.h b/simplelink_lpf3/source/ti/drivers/dpl/SwiP.h new file mode 100644 index 00000000..da4fca5d --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/dpl/SwiP.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SwiP.h + * + * @brief Software Interrupt module for the RTOS Porting Interface + * + * ============================================================================ + */ + +#ifndef ti_dpl_SwiP__include +#define ti_dpl_SwiP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SwiP object. + * + * nortos: 40 + * SysBIOS: 52 + */ +#define SwiP_STRUCT_SIZE (52) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SwiP objects. + */ +typedef union SwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SwiP_STRUCT_SIZE]; +} SwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a SwiP + * + * A SwiP_Handle returned from the ::SwiP_create represents that instance. + */ +typedef void *SwiP_Handle; + +/*! + * @brief Status codes for SwiP APIs + * TODO: See if we need more error codes. + */ +typedef enum { + SwiP_OK = 0, + SwiP_FAILURE = -1 +} SwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); + +/*! + * @brief Basic SwiP Parameters + * + * Structure that contains the parameters passed into ::SwiP_create + * and ::SwiP_construct when creating or constructing a SwiP instance. + * The ::SwiP_Params_init function should be used to initialize the + * fields to default values before the application sets the fields + * manually. The SwiP default parameters are noted in ::SwiP_Params_init. + * + * Each SwiP object has a "trigger" used either to determine whether to + * post the SwiP or as a value that can be evaluated within the SwiP's + * function. + * + * The SwiP_andn and SwiP_dec functions post the SwiP + * if the trigger value transitions to 0. The SwiP_or and + * SwiP_inc functions also modify the trigger value. SwiP_or + * sets bits, and SwiP_andn clears bits. + */ +typedef struct { + uintptr_t arg0; /*!< Argument passed into the SwiP function. */ + uintptr_t arg1; /*!< Argument passed into the SwiP function. */ + uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ + uint32_t trigger; /*!< Initial SwiP trigger value. */ +} SwiP_Params; + +/*! + * @brief Function to construct a software interrupt object. + * + * @param swiP Pointer to SwiP_Struct object. + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to destruct a software interrupt object + * + * @param swiP Pointer to a SwiP_Struct object that was passed to + * SwiP_construct(). + * + * @return + */ +extern void SwiP_destruct(SwiP_Struct *swiP); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SwiP_Params_init(SwiP_Params *params); + +/*! + * @brief Function to create a software interrupt object. + * + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to delete a software interrupt object + * + * @param handle returned from the SwiP_create call + * + */ +extern void SwiP_delete(SwiP_Handle handle); + +/*! + * @brief Function to disable software interrupts + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = SwiP_disable(); + * key2 = SwiP_disable(); + * SwiP_restore(key2); + * SwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to SwiP_restore to re-enable interrupts. + */ +extern uintptr_t SwiP_disable(void); + +/*! + * @brief Function to get the trigger value of the currently running SwiP. + * + */ +extern uint32_t SwiP_getTrigger(); + +/*! + * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask inverse value to be ANDed + */ +extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_dec(SwiP_Handle handle); + +/*! + * @brief Increment the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_inc(SwiP_Handle handle); + +/*! + * @brief Function to return a status based on whether it is in a + * software interrupt context. + * + * @return A status: indicating whether the function was called in a + * software interrupt routine (true) or not (false). + */ +extern bool SwiP_inISR(void); + +/*! + * @brief Or the mask with the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask value to be ORed + */ +extern void SwiP_or(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Unconditionally post a software interrupt. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_post(SwiP_Handle handle); + +/*! + * @brief Function to restore software interrupts + * + * @param key return from SwiP_disable + */ +extern void SwiP_restore(uintptr_t key); + +/*! + * @brief Function to set the priority of a software interrupt + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param priority new priority + */ +extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SwiP__include */ From 8b66188a4378a6dd2aa9197e081f08b214f5a75e Mon Sep 17 00:00:00 2001 From: Vebjorn Myklebust Date: Thu, 30 May 2024 12:48:16 +0200 Subject: [PATCH 4/7] simplelink: update hal to LPF3 SDK 8.10.00.55 Update simplelink lpf3 hal to the simplelink LPF3 SDK version 8.10.00.55. Signed-off-by: Vebjorn Myklebust --- simplelink_lpf3/CMakeLists.txt | 3 + .../kernel/zephyr/dpl/EventP_zephyr.c | 1 - .../ti/devices/cc23x0r5/driverlib/ckmd.h | 34 +- .../ti/devices/cc23x0r5/driverlib/cpu.c | 55 +- .../ti/devices/cc23x0r5/driverlib/cpu.h | 30 +- .../ti/devices/cc23x0r5/driverlib/hapi.h | 8 +- .../ti/devices/cc23x0r5/driverlib/lrfd.c | 30 +- .../ti/devices/cc23x0r5/driverlib/pmctl.h | 44 +- .../ti/devices/cc23x0r5/driverlib/tempdiode.c | 244 +++- .../ti/devices/cc23x0r5/driverlib/ull.h | 112 ++ .../source/ti/devices/cc23x0r5/inc/hw_ccfg.h | 29 +- .../ti/devices/cc23x0r5/inc/hw_device.h | 2 +- .../source/ti/devices/cc23x0r5/inc/hw_fcfg.h | 23 +- .../source/ti/devices/cc23x0r5/inc/hw_pmud.h | 147 +++ .../source/ti/devices/cc23x0r5/inc/hw_spi.h | 22 +- .../source/ti/devices/cc23x0r5/inc/hw_sys0.h | 3 + .../source/ti/devices/cc23x0r5/inc/hw_types.h | 26 +- simplelink_lpf3/source/ti/drivers/AESCCM.h | 75 +- simplelink_lpf3/source/ti/drivers/AESCMAC.h | 58 +- simplelink_lpf3/source/ti/drivers/AESCTR.h | 72 +- simplelink_lpf3/source/ti/drivers/ECDH.h | 13 +- simplelink_lpf3/source/ti/drivers/GPIO.h | 728 +++++++++++ simplelink_lpf3/source/ti/drivers/Power.h | 33 +- simplelink_lpf3/source/ti/drivers/RNG.c | 62 + simplelink_lpf3/source/ti/drivers/RNG.h | 994 ++++++++++++++ .../source/ti/drivers/Temperature.c | 19 +- .../source/ti/drivers/Temperature.h | 51 +- .../source/ti/drivers/aesccm/AESCCMLPF3.c | 1157 ++++++++++++++++- .../source/ti/drivers/aesccm/AESCCMLPF3.h | 66 +- .../source/ti/drivers/aescmac/AESCMACLPF3.c | 915 ++++++++++++- .../source/ti/drivers/aescmac/AESCMACLPF3.h | 38 +- .../source/ti/drivers/aesctr/AESCTRLPF3.c | 401 +++++- .../source/ti/drivers/aesctr/AESCTRLPF3.h | 28 +- .../source/ti/drivers/aesecb/AESECBLPF3.c | 418 +++++- .../source/ti/drivers/aesecb/AESECBLPF3.h | 33 +- .../batterymonitor/BatMonSupportLPF3.c | 15 +- .../source/ti/drivers/config_defaults.c | 15 + .../drivers/cryptoutils/cryptokey/CryptoKey.c | 53 + .../drivers/cryptoutils/cryptokey/CryptoKey.h | 60 +- .../cryptokey/CryptoKeyKeyStore_PSA.c | 6 +- .../cryptokey/CryptoKeyKeyStore_PSA.h | 641 +++++---- .../cryptokey/CryptoKeyKeyStore_PSA_helpers.c | 526 +------- .../cryptokey/CryptoKeyKeyStore_PSA_helpers.h | 4 +- .../cryptokey/CryptoKeyKeyStore_PSA_ns.c | 57 +- .../cryptokey/CryptoKeyKeyStore_PSA_s.c | 84 +- .../cryptokey/CryptoKeyKeyStore_PSA_s.h | 33 +- .../cryptokey/CryptoKeyPlaintext.c | 16 + .../cryptokey/CryptoKeyPlaintext.h | 21 +- .../ti/drivers/cryptoutils/ecc/ECCParams.h | 19 +- .../source/ti/drivers/dma/UDMALPF3.c | 8 +- .../source/ti/drivers/dma/UDMALPF3.h | 2 +- .../source/ti/drivers/gpio/GPIOLPF3.h | 161 +++ .../source/ti/drivers/power/PowerCC23X0.c | 696 ++++++++-- .../source/ti/drivers/power/PowerCC23X0.h | 148 ++- .../source/ti/drivers/rng/RNGLPF3RF.c | 824 ++++++++++++ .../source/ti/drivers/rng/RNGLPF3RF.h | 121 ++ .../source/ti/drivers/utils/List.c | 43 +- .../source/ti/drivers/utils/List.h | 9 +- .../source/ti/drivers/utils/Random.c | 237 ++++ .../source/ti/drivers/utils/Random.h | 172 +++ simplelink_lpf3/source/ti/log/Log.h | 1045 +++++++++++++++ 61 files changed, 9519 insertions(+), 1471 deletions(-) create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ull.h create mode 100644 simplelink_lpf3/source/ti/drivers/GPIO.h create mode 100644 simplelink_lpf3/source/ti/drivers/RNG.c create mode 100644 simplelink_lpf3/source/ti/drivers/RNG.h create mode 100644 simplelink_lpf3/source/ti/drivers/gpio/GPIOLPF3.h create mode 100644 simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.c create mode 100644 simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.h create mode 100644 simplelink_lpf3/source/ti/drivers/utils/Random.c create mode 100644 simplelink_lpf3/source/ti/drivers/utils/Random.h create mode 100644 simplelink_lpf3/source/ti/log/Log.h diff --git a/simplelink_lpf3/CMakeLists.txt b/simplelink_lpf3/CMakeLists.txt index 476745a8..969bc57a 100644 --- a/simplelink_lpf3/CMakeLists.txt +++ b/simplelink_lpf3/CMakeLists.txt @@ -19,6 +19,7 @@ if(CONFIG_HAS_CC23X0_SDK) # Utils source/ti/drivers/utils/List.c + source/ti/drivers/utils/Random.c # Drivers source/ti/drivers/AESCCM.c @@ -27,6 +28,7 @@ if(CONFIG_HAS_CC23X0_SDK) source/ti/drivers/AESCTRDRBG.c source/ti/drivers/AESECB.c source/ti/drivers/ECDH.c + source/ti/drivers/RNG.c source/ti/drivers/aesccm/AESCCMLPF3.c source/ti/drivers/aescmac/AESCMACLPF3.c source/ti/drivers/aesctr/AESCTRLPF3.c @@ -37,6 +39,7 @@ if(CONFIG_HAS_CC23X0_SDK) source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c source/ti/drivers/cryptoutils/utils/CryptoUtils.c source/ti/drivers/dma/UDMALPF3.c + source/ti/drivers/rng/RNGLPF3RF.c source/ti/drivers/Temperature.c source/ti/drivers/power/PowerCC23X0.c diff --git a/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c index 08720d90..9dd993f2 100644 --- a/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c +++ b/simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c @@ -101,7 +101,6 @@ uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, u { uint32_t eventBits, tickPeriod; k_timeout_t eventTimeout; - uint64_t timeUS; if (timeout == EventP_WAIT_FOREVER) diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h index 3433bbad..5cb872e0 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ckmd.h @@ -560,65 +560,77 @@ __STATIC_INLINE uint32_t CKMDGetTargetAmplitudeThresholdTrim(void) //***************************************************************************** // -//! \brief Gets the worst case LFOSC frequency jump due to RTN. +//! \brief Gets the worst-case LFOSC frequency jump due to RTN. //! -//! \return The absolute value of the worst case jump due to RTN in ppm. +//! \return The absolute value of the worst-case jump due to RTN in ppm. // //***************************************************************************** __STATIC_INLINE uint_least16_t CKMDGetLfoscRtnPpm(void) { - uint8_t ppmRtn = 0x14; + // Only App trims revision 5 and newer has a ppmRtn field. For older + // revisions use a default value of 20 (equivalent to 600ppm) + uint8_t ppmRtn = 20; if (fcfg->appTrims.revision >= 0x5) { ppmRtn = fcfg->appTrims.cc23x0r5.lfOscParams.ppmRtn; } + + // The ppmTempMid field uses units of 30ppm, convert to ppm return ppmRtn * 30; } //***************************************************************************** // -//! \brief Gets the the worst case LFOSC temperature coefficient in the "middle" +//! \brief Gets the the worst-case LFOSC temperature coefficient in the "middle" //! temperature range. //! -//! This function can be used to determine the the worst case LFOSC temperature +//! This function can be used to determine the the worst-case LFOSC temperature //! coefficient in units of ppm/C in the temperature range [ //! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN, //! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX ]. //! -//! \return The absolute value of worst case temperature coefficient in ppm/C. +//! \return The absolute value of worst-case temperature coefficient in ppm/C. // //***************************************************************************** __STATIC_INLINE uint_least16_t CKMDGetLfoscMidTempCoefficientPpmPerC(void) { - uint8_t ppmTempMid = 0x14; + // Only App trims revision 5 and newer has a ppmTempMid field. For older + // revisions use a default value of 20 (equivalent to 260ppm/C) + uint8_t ppmTempMid = 20; if (fcfg->appTrims.revision >= 0x5) { ppmTempMid = fcfg->appTrims.cc23x0r5.lfOscParams.ppmTempMid; } + + // The ppmTempMid field uses units of 13ppm/C, convert to ppm/C return ppmTempMid * 13; } //***************************************************************************** // -//! \brief Gets the the worst case LFOSC temperature coefficient in the +//! \brief Gets the the worst-case LFOSC temperature coefficient in the //! "extended" temperature range. //! -//! This function can be used to determine the the worst case LFOSC temperature +//! This function can be used to determine the the worst-case LFOSC temperature //! coefficient in units of ppm/C when the temperature is outside of the //! temperature range [ //! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MIN, //! \ref CKMD_LFOSC_MID_TEMP_COEFFICIENT_RANGE_MAX ]. //! -//! \return The absolute value of worst case temperature coefficient in ppm/C. +//! \return The absolute value of worst-case temperature coefficient in ppm/C. // //***************************************************************************** __STATIC_INLINE uint_least16_t CKMDGetLfoscExtTempCoefficientPpmPerC(void) { - uint8_t ppmTempExt = 0x14; + // Only App trims revision 5 and newer has a ppmTempExt field. For older + // revisions use a default value of 20 (equivalent to 700ppm/C) + uint8_t ppmTempExt = 20; if (fcfg->appTrims.revision >= 0x5) { ppmTempExt = fcfg->appTrims.cc23x0r5.lfOscParams.ppmTempExt; } + + // The ppmTempExt field uses units of 35ppm/C, convert to ppm/C return ppmTempExt * 35; } diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c index e402609f..ddcc26ba 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.c @@ -4,7 +4,7 @@ * Description: Instruction wrappers for special CPU instructions needed by * the drivers. * - * Copyright (c) 2022 Texas Instruments Incorporated + * Copyright (c) 2022-2023 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -57,41 +57,36 @@ void CPUDelay(uint32_t count) #pragma diag_suppress = Pe940 } #pragma diag_default = Pe940 - -#elif defined(__TI_COMPILER_VERSION__) -// For CCS implement this function in pure assembly. This prevents the TI -// compiler from doing funny things with the optimizer. - -// Loop the specified number of times -__asm(" .sect \".text:CPUDelay\"\n" - " .clink\n" - " .thumbfunc CPUDelay\n" - " .thumb\n" - " .global CPUDelay\n" - "CPUDelay:\n" - " subs r0, #1\n" - " bne.n CPUDelay\n" - " bx lr\n"); - #elif defined(__clang__) -void CPUDelay(uint32_t count) +void __attribute__((naked)) CPUDelay(uint32_t count) { - (void)count; // Linter does not see the use of r0 in asm. - // Loop the specified number of times - __asm(" subs r0, #1\n" - " bne.n CPUDelay\n" - " bx lr"); + // Loop the specified number of times. + // The naked attribute tells the compiler that the function is effectively + // hand-coded assembly implemented using inlined assembly without operands. + // As such, it assumes that the C calling conventions are obeyed, and we can + // assume count is in R0. + __asm volatile("CPUdel%=:\n" + " subs r0, #1\n" + " bne CPUdel%=\n" + " bx lr\n" + : /* No output */ + : /* No input */ + : "r0", "cc" /* Clobbers. "cc" is the flags */ + ); } -#else -// GCC +#elif defined(__GNUC__) void __attribute__((naked)) CPUDelay(uint32_t count) { // Loop the specified number of times __asm volatile(".syntax unified\n" - "%=: subs %0, #1\n" - " bne %=b\n" - " bx lr\n" - : /* No output */ - : "r"(count)); + "CPUdel%=:\n" + " subs %0, #1\n" + " bne CPUdel%=\n" + " bx lr\n" + : /* No output */ + : "r"(count) /* Input */ + ); } +#else + #error "Unsupported toolchain!" #endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h index 3681d8a1..36eadc79 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/cpu.h @@ -4,7 +4,7 @@ * Description: Defines and prototypes for the CPU instruction wrapper * functions. * - * Copyright (c) 2022 Texas Instruments Incorporated + * Copyright (c) 2022-2023 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -69,31 +69,25 @@ extern "C" { // //! \brief Provide a small non-zero delay using a simple loop counter. //! -//! This function provides means for generating a constant length delay. It -//! is written in assembly to keep the delay consistent across tool chains, +//! This function provides means for generating a constant length delay. It is +//! written in assembly to keep the delay consistent across tool chains, //! avoiding the need to tune the delay based on the tool chain in use. //! -//! \note It is not recommended using this function for long delays. -//! -//! Notice that interrupts can affect the delay if not manually disabled in advance. -//! -//! The delay depends on where code resides and the path for code fetching: -//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) -//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop -//! - Code in flash, cache disabled : 7 cycles per loop -//! - Code in SRAM : 6 cycles per loop -//! - Code in GPRAM : 3 cycles per loop +//! \note It is not recommended using this function for long delays. For longer +//! delays, consider using ROM function \ref HapiWaitUs(). //! //! \note If using an RTOS, consider using RTOS provided delay functions because //! these will not block task scheduling and will potentially save power. //! -//! Calculate delay count based on the wanted delay in microseconds (us): -//! - count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! \note Interrupts can affect the delay if not manually disabled in advance. +//! +//! \note The delay depends on where code resides and the path for code +//! fetching, consider using ROM function \ref HapiWaitUs(). //! -//! Example: 250 us delay with code in flash and with cache and prefetch enabled: -//! - count = 250 * 48 / 4 = 3000 +//! \param count is the number of delay loop iterations to perform. Number must +//! be greater than zero. //! -//! \param count is the number of delay loop iterations to perform. Number must be greater than zero. +//! \sa HapiWaitUs() //! //! \return None // diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h index a7c178df..d197c1bd 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/hapi.h @@ -86,7 +86,7 @@ typedef struct // 16: SHA256: Round constants const uint32_t (*sha256SW_K256)[64]; // 17: SHA256: Initial constants - const uint32_t (*sha256SW_initialDigest256)[8]; + const uint32_t (*sha256Sw_initialDigest256)[8]; // 18: Busy loop that waits for nUs microseconds void (*waitUs)(uint32_t nUs); // 19: Count leading zeros @@ -456,13 +456,13 @@ typedef struct #define HapiResetDevice() HAPI_TABLE_POINTER->resetDevice() // HAPI entry used for internal purposes -#define HapiSha256SWProcessBlock(d, w) HAPI_TABLE_POINTER->pSHA256SWProcessBlock((d), (w)) +#define HapiSha256SwProcessBlock(d, w) HAPI_TABLE_POINTER->sha256SwProcessBlock((d), (w)) // HAPI entry used for internal purposes -#define HapiSha256SW_K256 (*HAPI_TABLE_POINTER->sha256SW_K256) +#define HapiSha256Sw_K256 (*HAPI_TABLE_POINTER->sha256SW_K256) // HAPI entry used for internal purposes -#define HapiSha256SW_initialDigest256 (*HAPI_TABLE_POINTER->sha256SW_initialDigest256) +#define HapiSha256Sw_initialDigest256 (*HAPI_TABLE_POINTER->sha256Sw_initialDigest256) // void HapiWaitUs(uint32_t nUs) /***************************************************************************** diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c index 22ddc46c..e4c1a0d1 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/lrfd.c @@ -3,7 +3,7 @@ * * Description: Driver for LRFD * - * Copyright (c) 2023 Texas Instruments Incorporated + * Copyright (c) 2023-2024 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -44,7 +44,6 @@ #include "../driverlib/interrupt.h" static uint16_t lrfdClockDependencySets[LRFD_NUM_CLK_DEP]; -static bool lrfdClocked = false; //***************************************************************************** // @@ -81,7 +80,8 @@ void LRFDReleaseClockDependency(uint16_t mask, uint8_t dependencySetId) //***************************************************************************** void LRFDApplyClockDependencies(void) { - uint16_t clkctl = 0; + uint16_t clkctl = 0; + bool lrfdClocked = (HWREG(CLKCTL_BASE + CLKCTL_O_CLKCFG0) & CLKCTL_CLKCFG0_LRFD_M) == CLKCTL_CLKCFG0_LRFD_CLK_EN; for (int i = 0; i < LRFD_NUM_CLK_DEP; i++) { clkctl |= lrfdClockDependencySets[i]; @@ -89,13 +89,14 @@ void LRFDApplyClockDependencies(void) if (lrfdClocked) { - /* BRIDGE bit should not be needed, as hardware will automatically enable the clock when - needed. The bit should be always be 0 in the HW, and is thus cleared. */ + // BRIDGE bit should not be needed, as hardware will automatically + // enable the clock when needed. The bit should be always be 0 in the + // HW, and is thus cleared. HWREG(LRFDDBELL_BASE + LRFDDBELL_O_CLKCTL) = clkctl & ~LRFDDBELL_CLKCTL_BRIDGE_M; if (clkctl == 0) { - /* Disable LRFD module clock */ + // Disable LRFD module clock HWREG( CLKCTL_BASE + CLKCTL_O_CLKENCLR0 ) = CLKCTL_CLKENCLR0_LRFD; lrfdClocked = false; } @@ -104,14 +105,19 @@ void LRFDApplyClockDependencies(void) { if (clkctl != 0) { - /* Enable LRFD module clock */ + // Enable LRFD module clock HWREG( CLKCTL_BASE + CLKCTL_O_CLKENSET0 ) = CLKCTL_CLKENSET0_LRFD; - lrfdClocked = true; - /* BRIDGE bit should not be needed, as hardware will automatically enable the clock when - needed. The bit should be always be 0 in the HW, and is thus cleared. The bit can be - used in the input to indicate the need for the LRFD module clock to be enabled, but no - internal LRFD clocks. */ + // Wait for LRFD clock to be enabled. It is not expected that the + // LRFD clock will ever not be enabled, but this will add sufficient + // delay before enabling the internal LRFD clocks below. + while ((HWREG(CLKCTL_BASE + CLKCTL_O_CLKCFG0) & CLKCTL_CLKCFG0_LRFD_M) != CLKCTL_CLKCFG0_LRFD_CLK_EN) {} + + // BRIDGE bit should not be needed, as hardware will automatically + // enable the clock when needed. The bit should be always be 0 in + // the HW, and is thus cleared. The bit can be used in the input to + // indicate the need for the LRFD module clock to be enabled, but no + // internal LRFD clocks. HWREG(LRFDDBELL_BASE + LRFDDBELL_O_CLKCTL) = clkctl & ~LRFDDBELL_CLKCTL_BRIDGE_M; } } diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h index dc614449..b01e5b21 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/pmctl.h @@ -3,7 +3,7 @@ * * Description: Defines and prototypes for the PMCTL module. * - * Copyright (c) 2022 Texas Instruments Incorporated + * Copyright (c) 2022-2024 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -76,31 +76,37 @@ extern "C" { //@{ //***************************************************************************** //! Device woke up from shutdown due to an IO event -#define PMCTL_RESET_SHUTDOWN_IO (PMCTL_RSTSTA_SDDET | PMCTL_RSTSTA_IOWUSD) +#define PMCTL_RESET_SHUTDOWN_IO (PMCTL_RSTSTA_SDDET | PMCTL_RSTSTA_IOWUSD) //! Device woke up from shutdown due to an SWD event -#define PMCTL_RESET_SHUTDOWN_SWD PMCTL_RSTSTA_SDDET +#define PMCTL_RESET_SHUTDOWN_SWD PMCTL_RSTSTA_SDDET //! Device reset because of a watchdog timeout. -#define PMCTL_RESET_WATCHDOG (PMCTL_RSTSTA_SYSSRC_WDTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) -//! Device reset trggered by software writing to RSTCTL.SYSRST -#define PMCTL_RESET_SYSTEM (PMCTL_RSTSTA_SYSSRC_SYSRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +#define PMCTL_RESET_WATCHDOG (PMCTL_RSTSTA_SYSSRC_WDTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by software writing to RSTCTL.SYSRST +#define PMCTL_RESET_SYSTEM (PMCTL_RSTSTA_SYSSRC_SYSRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) //! Device reset triggered by CPU reset event -#define PMCTL_RESET_CPU (PMCTL_RSTSTA_SYSSRC_CPURSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +#define PMCTL_RESET_CPU (PMCTL_RSTSTA_SYSSRC_CPURSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) //! Device reset triggered by CPU lockup event -#define PMCTL_RESET_LOCKUP (PMCTL_RSTSTA_SYSSRC_LOCKUPEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) -//! Device woke up due to Serial Wire Debug event -#define PMCTL_RESET_SWD (PMCTL_RSTSTA_SYSSRC_SWDRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +#define PMCTL_RESET_LOCKUP (PMCTL_RSTSTA_SYSSRC_LOCKUPEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by Analog FSM timeout event +#define PMCTL_RESET_ANALOG_FSM_TIMEOUT (PMCTL_RSTSTA_SYSSRC_AFSMEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by Analog Error reset event +#define PMCTL_RESET_ANALOG_ERROR (PMCTL_RSTSTA_SYSSRC_AERREV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by Digital Error reset event +#define PMCTL_RESET_DIGITAL_ERROR (PMCTL_RSTSTA_SYSSRC_DERREV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +//! Device reset triggered by Serial Wire Debug reset event +#define PMCTL_RESET_SWD (PMCTL_RSTSTA_SYSSRC_SWDRSTEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) //! Device reset due to LFXT clock loss -#define PMCTL_RESET_LFXT (PMCTL_RSTSTA_SYSSRC_LFLOSSEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) +#define PMCTL_RESET_LFXT (PMCTL_RSTSTA_SYSSRC_LFLOSSEV | PMCTL_RSTSTA_RESETSRC_SYSRESET) //! Device woke up from thermal shutdown after temperature drop -#define PMCTL_RESET_TSD (PMCTL_RSTSTA_TSDEV | PMCTL_RSTSTA_RESETSRC_PINRESET) +#define PMCTL_RESET_TSD (PMCTL_RSTSTA_TSDEV | PMCTL_RSTSTA_RESETSRC_PINRESET) //! Device reset due to VDDR brownout event -#define PMCTL_RESET_VDDR PMCTL_RSTSTA_RESETSRC_VDDRLOSS +#define PMCTL_RESET_VDDR PMCTL_RSTSTA_RESETSRC_VDDRLOSS //! Device reset due to VDDS brownout event -#define PMCTL_RESET_VDDS PMCTL_RSTSTA_RESETSRC_VDDSLOSS +#define PMCTL_RESET_VDDS PMCTL_RSTSTA_RESETSRC_VDDSLOSS //! Device reset due to pin reset -#define PMCTL_RESET_PIN PMCTL_RSTSTA_RESETSRC_PINRESET +#define PMCTL_RESET_PIN PMCTL_RSTSTA_RESETSRC_PINRESET //! Device booted due to power on reset -#define PMCTL_RESET_POR PMCTL_RSTSTA_RESETSRC_PWRON +#define PMCTL_RESET_POR PMCTL_RSTSTA_RESETSRC_PWRON //@} //***************************************************************************** @@ -123,11 +129,15 @@ extern "C" { //! - \ref PMCTL_RESET_SHUTDOWN_IO //! - \ref PMCTL_RESET_SHUTDOWN_SWD //! - \ref PMCTL_RESET_WATCHDOG +//! - \ref PMCTL_RESET_SYSTEM //! - \ref PMCTL_RESET_CPU //! - \ref PMCTL_RESET_LOCKUP -//! - \ref PMCTL_RESET_TSD +//! - \ref PMCTL_RESET_ANALOG_FSM_TIMEOUT +//! - \ref PMCTL_RESET_ANALOG_ERROR +//! - \ref PMCTL_RESET_DIGITAL_ERROR //! - \ref PMCTL_RESET_SWD //! - \ref PMCTL_RESET_LFXT +//! - \ref PMCTL_RESET_TSD //! - \ref PMCTL_RESET_VDDR //! - \ref PMCTL_RESET_VDDS //! - \ref PMCTL_RESET_PIN diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c index 29381fbb..914971d4 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/tempdiode.c @@ -56,17 +56,14 @@ static uint32_t TempDiodeRamHWREG(uint32_t address, uint32_t data) __attribute__ #error Unsupported Compiler #endif +extern int32_t voltageToTempHardcoded(uint32_t microVolts); static void enableADC(void); static int32_t voltageToTemp(uint32_t microVolts); -static int64_t int_sqrt(uint64_t n); +static uint64_t isqrt(uint64_t n); -/* Temporary PMUD PREFSYS register definition. */ -#ifdef PMUD_O_PREFSYS - #error "PMUD_O_PREFSYS defined in DOC release! Remove definitition below." -#endif - -#define PMUD_O_PREFSYS 0x00000080U -#define PMUD_PREFSYS_TEST2 0x00000004U +/* Macros for finding minimum between two and three numbers */ +#define MIN2(a, b) ((a) < (b) ? (a) : (b)) +#define MIN3(a, b, c) MIN2(MIN2((a), (b)), (c)) //***************************************************************************** // @@ -126,49 +123,51 @@ static void enableADC(void) //***************************************************************************** // // Converts a voltage (uV) measured across the diode to temperature (degC), -// with 4 fractional bits. +// with 4 fractional bits, using hardcoded coefficients. If the device has +// coefficients available in FCFG, or if different hardcoded values are needed, +// then this function can be overridden. // //***************************************************************************** -static int32_t voltageToTemp(uint32_t microVolts) +int32_t __attribute__((weak)) voltageToTempHardcoded(uint32_t microVolts) { /* The tempsense diode voltage (mV) as a function of temperature (degC) can * be modeled as mV(T) = a*T^2 + b*T + c, where the coefficients are: - * a = -0.000324 - * b = -1.432931 - * c = 833.729920 + * a = -0.000327 + * b = -1.435965 + * c = 835.584465 * * To improve the performance we find the delta between the curve fit, and * the measured FCFG value. The FCFG temperature is not precisely 30 degC, - * but 28.3 degC instead. - * We calculate mV(28.3) = 792.918484 mV. + * but 29.5 degC instead. + * We calculate mV(29.5) = 792.938926 mV. * * The device-specific curve fit function then becomes - * mV(T) = a*T^2 + b*T + c + delta, where delta = (FCFG_value - mV(28.3)) + * mV(T) = a*T^2 + b*T + c + delta, where delta = (FCFG_value - mV(29.5)) * - * mV(T) = -0.000324*T^2 - 1.432931*T + 833.729920 + FCFG_value - 792.918484 + * mV(T) = -0.000327*T^2 - 1.435965*T + 835.584465 + FCFG_value - 792.938926 * * To bring all constants from floating-point to fixed-point integers we * multiply the entire equation by a factor 2^24. This gives good enough * resolution, and leaves a margin before overflowing 64 bit calculations. * The shifted coefficients become as follows: * - * aScaled = a * 2^24 = -5436 - * bScaled = b * 2^24 = -24040593 - * cScaled = c * 2^24 = 13987666953 - * mV(28.s)Scaled = 792.918484 * 2^24 = 13302964682 + * aScaled = a * 2^24 = -5486 + * bScaled = b * 2^24 = -24091495 + * cScaled = c * 2^24 = 14018781056 + * mV(29.5)Scaled = 792.938926 * 2^24 = 13303307632 * */ - int64_t aScaled = -5436LL; /* -0.000324 * 2^24 */ - int64_t bScaled = -24040593LL; /* -1.432931 * 2^24 */ - int64_t cScaled = 13987666953LL; /* 833.729920 * 2^24 */ - int64_t mV28Scaled = 13302964682LL; /* mV(28.3) * 2^24 */ + int64_t aScaled = -5486LL; /* -0.000327 * 2^24 */ + int64_t bScaled = -24091495LL; /* -1.435965 * 2^24 */ + int64_t cScaled = 14018781056LL; /* 835.584465 * 2^24 */ + int64_t mV28Scaled = 13303307632LL; /* mV(29.5) * 2^24 */ /* To find the temperature T, we solve the equation * 0 = p2*T^2 + p1*T + p0, using the quadratic formula, where * p2 = aScaled * p1 = bScaled - * p0 = cScaled + fcfg_valueScaled - mV(28.s)Scaled - inputVoltageScaled + * p0 = cScaled + fcfg_valueScaled - mV(29.5)Scaled - inputVoltageScaled * * T = (-p1 - sqrt(p1*p1 - 4*p2*p0)) / (2*p2) */ @@ -191,7 +190,129 @@ static int32_t voltageToTemp(uint32_t microVolts) /* Apply quadratic formula, but scale numerator by a factor 16 to get 4 * fractional bits in the temperature result. */ - int32_t temperature = ((-p1 - int_sqrt(p1 * p1 - (4 * p2 * p0))) << 4) / (2 * p2); + int32_t temperature = ((-p1 - (int64_t)isqrt(p1 * p1 - (4 * p2 * p0))) << 4) / (2 * p2); + + return temperature; +} + +//***************************************************************************** +// +// Converts a voltage (uV) measured across the diode to temperature (degC), +// with 4 fractional bits. +// +//***************************************************************************** +static int32_t voltageToTemp(uint32_t microVolts) +{ + /* Check if coefficients are directly available in FCFG. If not, fall back + * on function using hardcoded values. Coefficients were only introduced in + * FCFG layout revision 6. + */ + uint8_t fcfgRevision = fcfg->appTrims.revision; + + if (fcfgRevision < 0x06) + { + return voltageToTempHardcoded(microVolts); + } + + /* The tempsense diode voltage (mV) as a function of temperature (degC) can + * be modeled as mV(T) = a*T^2 + b*T + c, where the coefficients are: + * a = a_fcfg >> a_fcfg_shift + * b = b_fcfg >> b_fcfg_shift + * c = c_fcfg >> c_fcfg_shift + */ + + int64_t aScaled = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP2; + int64_t bScaled = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP1; + int64_t cScaled = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP0; + + uint8_t aShiftFactor = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP2Shift; + uint8_t bShiftFactor = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP1Shift; + uint8_t cShiftFactor = fcfg->appTrims.cc23x0r5.auxDiodeCoeff.coeffP0Shift; + + /* Bring coefficients to the same scale. Try to shift towards the + * numerically highest coefficient (the one with the largest shift) in + * order to maintain highest possible resolution. Since coefficients are + * 16-bit, they should be scaled maximum by 16, otherwise two coefficients + * would overflow 64-bit when multiplied. If some coefficients need to be + * shifted more than 16 bits, a middle ground must be found and some + * coefficients must be shifted down instead. + */ + uint8_t minShiftFactor = MIN3(aShiftFactor, bShiftFactor, cShiftFactor); + + /* Always shift up at least 16 bits */ + uint8_t commonShiftFactor = minShiftFactor + 16; + + int64_t *coefficients[3] = {&aScaled, &bScaled, &cScaled}; + uint8_t shiftFactors[3] = {aShiftFactor, bShiftFactor, cShiftFactor}; + + /* Loop over all three coefficients and scale each one. */ + for (int i = 0; i < 3; i++) + { + if (shiftFactors[i] < commonShiftFactor) + { + /* Scale this coefficient up towards the common scale factor */ + *coefficients[i] <<= (commonShiftFactor - shiftFactors[i]); + } + else if (shiftFactors[i] > commonShiftFactor) + { + /* Scale this coefficient down towards the common scale factor */ + *coefficients[i] >>= (shiftFactors[i] - commonShiftFactor); + } + else + { + /* Do nothing. Scale neither up nor down */ + } + } + + /* Convert input voltage (microvolts) to scaled millivolts. The common + * shift factor can be maximum 31 + 16 = 47, and microvolts can be maximum + * 1,400,000, which means that (microvolts << commonShiftFactor) can in + * theory overflow. Practically, the characteristics of the tempsense diode + * tell us this will never happen, but we add a check just in case. + */ + int64_t inputVoltageScaled; + + if (commonShiftFactor >= 42) + { + /* If shitfting up by more than 42, this value might overflow. Divide + * by 1000 to convert to millivolts before shifting. + */ + inputVoltageScaled = (int64_t)(microVolts / 1000) << commonShiftFactor; + } + else + { + inputVoltageScaled = (((int64_t)microVolts << commonShiftFactor) + 500) / 1000; + } + + /* To find the temperature T, we solve the equation + * 0 = p2*T^2 + p1*T + p0, using the quadratic formula, where + * p2 = aScaled + * p1 = bScaled + * p0 = cScaled - inputVoltageScaled + * + * T = (-p1 - sqrt(p1*p1 - 4*p2*p0)) / (2*p2) + */ + int64_t p2 = aScaled; + int64_t p1 = bScaled; + int64_t p0 = cScaled - inputVoltageScaled; + + /* Apply quadratic formula, but scale numerator by a factor 16 to get 4 + * fractional bits in the temperature result. Round to nearest integer. + */ + int64_t dividend = (-p1 - (int64_t)isqrt(p1 * p1 - (4 * p2 * p0))) << 4; + int64_t divisor = 2 * p2; + int32_t temperature; + + if ((dividend < 0LL) == (divisor < 0LL)) + { + /* If dividend has same sign as divisor */ + temperature = (dividend + (divisor / 2)) / divisor; + } + else + { + /* If dividend has opposite sign as divisor */ + temperature = (dividend - (divisor / 2)) / divisor; + } return temperature; } @@ -233,6 +354,11 @@ int32_t TempDiodeGetTemp(void) /* Measure the high side of the diode */ HWREG(SYS0_BASE + SYS0_O_TSENSCFG) = SYS0_TSENSCFG_SEL_VALUE; + /* Perform a dummy-read of the ADC for better settling */ + ADCManualTrigger(); + CPUDelay(3); + ADCReadResult(0); + /* Do 4 ADC conversions for averaging */ for (uint32_t i = 0; i < 4; i++) { @@ -244,6 +370,11 @@ int32_t TempDiodeGetTemp(void) /* Measure ground (low side of the diode) */ HWREG(SYS0_BASE + SYS0_O_TSENSCFG) = SYS0_TSENSCFG_SEL_GND; + /* Perform a dummy-read of the ADC for better settling */ + ADCManualTrigger(); + CPUDelay(3); + ADCReadResult(0); + /* Do 4 ADC conversions for averaging */ for (uint32_t i = 0; i < 4; i++) { @@ -284,40 +415,53 @@ int32_t TempDiodeGetTemp(void) //***************************************************************************** // -// Compute the integer square root of a number n. Method taken from: -// https://en.wikipedia.org/wiki/Methods_of_computing_square_roots#Binary_numeral_system_(base_2) +// Compute the integer square root of a number n. This function returns the +// largest integer whose square is equal to or less than n. // //***************************************************************************** -static int64_t int_sqrt(uint64_t n) +static uint64_t isqrt(uint64_t n) { - /* X_n+1 */ - int64_t x = n; - - /* c_n */ - int64_t c = 0; + uint64_t remainder, root; - /* d_n which starts at the highest power of four <= n */ - int64_t d = 0x4000000000000000LL; + /* Initialize the remainder and root to zero */ + remainder = 0; + root = 0; - while (d > n) + /* Loop over the 32 bits in the root */ + for (uint32_t index = 0; index < 32; index++) { - d >>= 2; - } + /* + * Shift the root up by a bit to make room for the new bit that is + * about to be computed. + */ + root <<= 1; - /* for d_n ... d_0 */ - while (d != 0) - { - if (x >= (c + d)) - { /* if X_m+1 ≥ Y_m then a_m = 2^m */ - x -= c + d; /* X_m = X_m+1 - Y_m */ - c = (c >> 1) + d; /* c_m-1 = c_m/2 + d_m (a_m is 2^m) */ + /* Get two more bits from the input into the remainder */ + remainder = ((remainder << 2) + (n >> 62)); + n <<= 2; + + /* Make the test root be 2n + 1 */ + root++; + + /* See if the root is greater than the remainder */ + if (root <= remainder) + { + /* Subtract the test root from the remainder */ + remainder -= root; + + /* Increment the root, setting the second LSB */ + root++; } else { - c >>= 1; /* c_m-1 = c_m/2. (a_m is 0) */ + /* + * The root is greater than the remainder, so the new bit of the + * root is actually zero + */ + root--; } - d >>= 2; /* d_m-1 = d_m/4 */ } - return c; /* c_-1 */ + /* Return the computed root */ + return root >> 1; } \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ull.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ull.h new file mode 100644 index 00000000..be26c13f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/ull.h @@ -0,0 +1,112 @@ +/****************************************************************************** + * Filename: ull.h + * + * Description: Defines and prototypes for the ULL instruction wrapper + * functions. + * + * Copyright (c) 2024 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ULL_H__ +#define __ULL_H__ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ull_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rtc.h" + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sync all writes to registers in the ULL domain +//! +//! The SVT and ULL domains are not fully synchronised. If software issues a +//! write to a ULL register followed be a read or write access to an SVT +//! register, the accesses may take effect out of order. That is, the SVT access +//! may happen before the ULL write. +//! +//! This function explicitly synchronises the domains by reading from the ULL +//! domain. When this function returns, all writes to ULL registers are +//! guaranteed to have propagated to hardware. +//! +//! \return None +//! +// +//***************************************************************************** +__STATIC_INLINE void ULLSync(void) +{ + // Read an RTC register to ensure that previous ULL writes have taken effect + HWREG(RTC_BASE + RTC_O_DESC); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __ULL_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h index 217aa5f6..2b79c23a 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_ccfg.h @@ -125,12 +125,8 @@ typedef struct { struct { // Sticky-0 bits written to VIMS.WEPRA (sectors 0-31, 1/bit) uint32_t mainSectors0_31; - union { - // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) - uint32_t mainSectors32_255; - // Dummy symbol to allow code to remain the same across devices - uint32_t mainSectors256_511; - }; + // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) + uint32_t mainSectors32_255; // Sticky-0 bit written to VIMS.WEPRAUX union { uint32_t auxSectors; @@ -146,12 +142,8 @@ typedef struct { struct { // Set bits (sectors 0-31, 1/bit) define what a chip erase command can optionally retain uint32_t mainSectors0_31; - union { - // Set bits (sectors 32-255, 8/bit) define what a chip erase command can optionally retain - uint32_t mainSectors32_255; - // Dummy field to allow code to remain same across devices - uint32_t mainSectors256_511; - }; + // Set bits (sectors 32-255, 8/bit) define what a chip erase command can optionally retain + uint32_t mainSectors32_255; } chipEraseRetain; // Reserved for future flash increases uint32_t res0[2]; @@ -185,13 +177,14 @@ typedef struct { // User record size is fixed at 128 B. Last word assumed to be CRC over first 124 B (optional) #define CCFG_USER_RECORD_SIZE 128 union { // [End-176]: length 128B - // Generic 32b record layout - uint32_t val32[(CCFG_USER_RECORD_SIZE/4)]; - // Generic 8b record layout - uint8_t val8[CCFG_USER_RECORD_SIZE]; - // CRC field in last word struct { - uint32_t res0[CCFG_USER_RECORD_SIZE/4-1]; + union { + // Generic 32b record layout + uint32_t val32[(CCFG_USER_RECORD_SIZE/4)-1]; + // Generic 8b record layout + uint8_t val8[CCFG_USER_RECORD_SIZE-4]; + }; + // CRC field across first 124B of userRecord (supported by SACI verifyCcfg command) uint32_t crc32; }; } userRecord; diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h index c9fdc25b..2633e621 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_device.h @@ -41,7 +41,7 @@ // --- ROM definitions --- /// Size of the call stack used in ROM, in number of bytes -#define BOOT_CSTACK_SIZE (1024-CCFG_USER_RECORD_SIZE) +#define BOOT_CSTACK_SIZE (1024-sizeof(fcfg_appTrims_t)) // --- FLASH definitions --- /// Size of a 1T flash sector, in number of bytes diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h index aea73249..1f5d5494 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_fcfg.h @@ -215,12 +215,8 @@ typedef struct { struct { // Sticky-0 bits written to VIMS.WEPRA (sectors 0-31, 1/bit) uint32_t mainSectors0_31; - union { - // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) - uint32_t mainSectors32_255; - // Dummy symbol to allow code to remain the same across devices - uint32_t mainSectors256_511; - }; + // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) + uint32_t mainSectors32_255; // Sticky-0 bit written to VIMS.WEPRAUX union { uint32_t auxSectors; @@ -589,8 +585,18 @@ typedef struct { uint32_t adcGainIntref2P5V : 16; uint32_t adcGainIntref1P4V : 16; } adcGainWord1; + // Coefficients for AUX Diode temperature to voltage + struct { // length: 8B + int16_t coeffP2; + int16_t coeffP1; + int16_t coeffP0; + uint16_t coeffP2Shift :5; + uint16_t coeffP1Shift :5; + uint16_t coeffP0Shift :5; + uint16_t res0 :1; + } auxDiodeCoeff; // Unused space - uint8_t res3[28]; + uint8_t res3[20]; // Measured I2V resistor error values struct { // length: 4B uint32_t i2v20k : 8; @@ -650,4 +656,7 @@ typedef struct { */ #define fcfg ((const fcfg_t *)FCFG_BASE) +/* Define type used by hw_device.h */ +typedef struct appTrims_struct fcfg_appTrims_t; + #endif // __HW_FCFG_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h index 58c83efd..f98d2d1e 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_pmud.h @@ -75,6 +75,9 @@ // Temperature Lower Limit #define PMUD_O_TEMPLL 0x0000005CU +// Internal. Only to be used through TI provided API. +#define PMUD_O_PREFSYS 0x00000080U + // Internal. Only to be used through TI provided API. #define PMUD_O_PREG0 0x00000090U @@ -557,6 +560,150 @@ #define PMUD_TEMPLL_FRAC_M 0x000000C0U #define PMUD_TEMPLL_FRAC_S 6U +//***************************************************************************** +// +// Register: PMUD_O_PREFSYS +// +//***************************************************************************** +// Field: [15:11] SPARE +// +// Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_SPARE_W 5U +#define PMUD_PREFSYS_SPARE_M 0x0000F800U +#define PMUD_PREFSYS_SPARE_S 11U + +// Field: [10] TEST10 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST10 0x00000400U +#define PMUD_PREFSYS_TEST10_M 0x00000400U +#define PMUD_PREFSYS_TEST10_S 10U +#define PMUD_PREFSYS_TEST10_SET 0x00000400U +#define PMUD_PREFSYS_TEST10_CLR 0x00000000U + +// Field: [9] TEST9 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST9 0x00000200U +#define PMUD_PREFSYS_TEST9_M 0x00000200U +#define PMUD_PREFSYS_TEST9_S 9U +#define PMUD_PREFSYS_TEST9_SET 0x00000200U +#define PMUD_PREFSYS_TEST9_CLR 0x00000000U + +// Field: [8] TEST8 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST8 0x00000100U +#define PMUD_PREFSYS_TEST8_M 0x00000100U +#define PMUD_PREFSYS_TEST8_S 8U +#define PMUD_PREFSYS_TEST8_SET 0x00000100U +#define PMUD_PREFSYS_TEST8_CLR 0x00000000U + +// Field: [7] TEST7 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST7 0x00000080U +#define PMUD_PREFSYS_TEST7_M 0x00000080U +#define PMUD_PREFSYS_TEST7_S 7U +#define PMUD_PREFSYS_TEST7_SET 0x00000080U +#define PMUD_PREFSYS_TEST7_CLR 0x00000000U + +// Field: [6] TEST6 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST6 0x00000040U +#define PMUD_PREFSYS_TEST6_M 0x00000040U +#define PMUD_PREFSYS_TEST6_S 6U +#define PMUD_PREFSYS_TEST6_SET 0x00000040U +#define PMUD_PREFSYS_TEST6_CLR 0x00000000U + +// Field: [5] TEST5 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST5 0x00000020U +#define PMUD_PREFSYS_TEST5_M 0x00000020U +#define PMUD_PREFSYS_TEST5_S 5U +#define PMUD_PREFSYS_TEST5_SET 0x00000020U +#define PMUD_PREFSYS_TEST5_CLR 0x00000000U + +// Field: [4] TEST4 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST4 0x00000010U +#define PMUD_PREFSYS_TEST4_M 0x00000010U +#define PMUD_PREFSYS_TEST4_S 4U +#define PMUD_PREFSYS_TEST4_SET 0x00000010U +#define PMUD_PREFSYS_TEST4_CLR 0x00000000U + +// Field: [3] TEST3 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST3 0x00000008U +#define PMUD_PREFSYS_TEST3_M 0x00000008U +#define PMUD_PREFSYS_TEST3_S 3U +#define PMUD_PREFSYS_TEST3_SET 0x00000008U +#define PMUD_PREFSYS_TEST3_CLR 0x00000000U + +// Field: [2] TEST2 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST2 0x00000004U +#define PMUD_PREFSYS_TEST2_M 0x00000004U +#define PMUD_PREFSYS_TEST2_S 2U +#define PMUD_PREFSYS_TEST2_SET 0x00000004U +#define PMUD_PREFSYS_TEST2_CLR 0x00000000U + +// Field: [1] TEST1 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST1 0x00000002U +#define PMUD_PREFSYS_TEST1_M 0x00000002U +#define PMUD_PREFSYS_TEST1_S 1U +#define PMUD_PREFSYS_TEST1_SET 0x00000002U +#define PMUD_PREFSYS_TEST1_CLR 0x00000000U + +// Field: [0] TEST0 +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SET Internal. Only to be used through TI provided API. +// CLR Internal. Only to be used through TI provided API. +#define PMUD_PREFSYS_TEST0 0x00000001U +#define PMUD_PREFSYS_TEST0_M 0x00000001U +#define PMUD_PREFSYS_TEST0_S 0U +#define PMUD_PREFSYS_TEST0_SET 0x00000001U +#define PMUD_PREFSYS_TEST0_CLR 0x00000000U + //***************************************************************************** // // Register: PMUD_O_PREG0 diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h index ed6ac46c..e8a487a1 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_spi.h @@ -170,7 +170,7 @@ // // DMA Done TX event mask. // ENUMs: -// SET Set Interrrupt Mask +// SET Set Interrupt Mask // CLR Clear Interrupt Mask #define SPI_IMASK_DMATX 0x00000100U #define SPI_IMASK_DMATX_M 0x00000100U @@ -463,7 +463,7 @@ // Field: [3] RX // -// Masked receive FIFO event. +// Masked Receive FIFO event. // ENUMs: // SET Interrupt occurred // CLR Interrupt did not occur @@ -590,7 +590,7 @@ // // Set SPI Receive Time-Out Event. // ENUMs: -// SET Set Interrrupt Mask +// SET Set Interrupt Mask // NOEFF Writing 0 has no effect #define SPI_ISET_RTOUT 0x00000004U #define SPI_ISET_RTOUT_M 0x00000004U @@ -703,7 +703,7 @@ // // Clear SPI Receive Time-Out Event. // ENUMs: -// CLR Set Interrrupt Mask +// CLR Set Interrupt Mask // NOEFF Writing 0 has no effect #define SPI_ICLR_RTOUT 0x00000004U #define SPI_ICLR_RTOUT_M 0x00000004U @@ -1218,7 +1218,7 @@ // Field: [15:12] CDMODE // -// Commnd Data Mode. This bit field value determines the behavior of C/D or CS +// Command Data Mode. This bit field value determines the behavior of C/D or CS // signal when CDEN = 1. CS pin held low indicates command phase and CS pin // held high indicates data phase. // When CDMODE = 0x0, the CS pin is always held high during transfer indicating @@ -1415,8 +1415,8 @@ // // Serial clock divider. This is used to generate the transmit and receive bit // rate of the SPI. -// The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value -// can be from 0 to 1023. +// The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*PRESC). SCR +// value can be from 0 to 1023. #define SPI_CLKCFG1_SCR_W 10U #define SPI_CLKCFG1_SCR_M 0x000003FFU #define SPI_CLKCFG1_SCR_S 0U @@ -1483,7 +1483,7 @@ //***************************************************************************** // Field: [8] TXEN // -// Transmit DMA enable. If this bit is set to 1, DMA for the trasmit FIFO is +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. // ENUMs: // EN Enable TX DMA @@ -1515,8 +1515,8 @@ // Field: [15:0] DATA // // CRC value -// SW should read RXCRC register at the end of data transmission to reinitiaze -// the seed value to all ones +// SW should read RXCRC register at the end of data transmission to +// reinitialize the seed value to all ones #define SPI_RXCRC_DATA_W 16U #define SPI_RXCRC_DATA_M 0x0000FFFFU #define SPI_RXCRC_DATA_S 0U @@ -1761,7 +1761,7 @@ // // SPI Busy status // ENUMs: -// ACTIVE SPI is currently transmitting and/or recieving +// ACTIVE SPI is currently transmitting and/or receiving // data, or transmit FIFO is not empty. // IDLE SPI is in idle mode. #define SPI_STA_BUSY 0x00000010U diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h index 82e77e70..7e27a2aa 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_sys0.h @@ -777,6 +777,9 @@ // Field: [10:8] IPEAK // // DCDC: Set inductor peak current +// Min = 0x0 +// Max = 0x7 +// DCDC load support increases from 0x0 to 0x7 #define SYS0_TMUTE4_IPEAK_W 3U #define SYS0_TMUTE4_IPEAK_M 0x00000700U #define SYS0_TMUTE4_IPEAK_S 8U diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h index c6849804..68e45404 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_types.h @@ -3,7 +3,7 @@ * * Description: Common types and macros. * -* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* Copyright (c) 2015 - 2023, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -91,4 +91,28 @@ typedef unsigned int __UINT32; #define HWREGB(x) \ (*((volatile unsigned char *)(x))) +// Word (32 bit) read to address x in the LRF module +// This define is present for cross-device compatibility. Do not use! +#define HWREG_READ_LRF(x) HWREG(x) + +// Half word (16 bit) read to address x in the LRF module +// This define is present for cross-device compatibility. Do not use! +#define HWREGH_READ_LRF(x) HWREGH(x) + +// Byte (8 bit) access to address x +// This define is present for cross-device compatibility. Do not use! +#define HWREGB_READ_LRF(x) HWREGB(x) + +// Word (32 bit) write to address x in the LRF module. +// This define is present for cross-device compatibility. Do not use! +#define HWREG_WRITE_LRF(x) HWREG(x) + +// Half word (16 bit) write to address x in the LRF module. +// This define is present for cross-device compatibility. Do not use! +#define HWREGH_WRITE_LRF(x) HWREGH(x) + +// Byte (8 bit) write to address x in the LRF module. +// This define is present for cross-device compatibility. Do not use! +#define HWREGB_WRITE_LRF(x) HWREGB(x) + #endif // __HW_TYPES_H__ diff --git a/simplelink_lpf3/source/ti/drivers/AESCCM.h b/simplelink_lpf3/source/ti/drivers/AESCCM.h index 3cc5d1fb..ca952bbd 100644 --- a/simplelink_lpf3/source/ti/drivers/AESCCM.h +++ b/simplelink_lpf3/source/ti/drivers/AESCCM.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, Texas Instruments Incorporated + * Copyright (c) 2017-2023, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -241,6 +241,65 @@ * AESCCM_close(handle); * * @endcode + * ### The following code snippet is for CC27XX devices only and leverages the HSM + * which is a seperate Hardware Accelerator ### + * ### Single call CCM encryption + authentication with plaintext HSM CryptoKey in Polling Mode ### + * + * @code + * + * #include + * #include + * + * ... + * + * AESCCM_Params params; + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t nonce[] = "Thisisanonce"; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * AESCCM_Params_init(¶ms) + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_POLLING; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation operation; + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode * * ### Single call CCM decryption + verification with plaintext CryptoKey in callback return mode # * @code @@ -365,6 +424,7 @@ * * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); * + * * encryptionResult = AESCCM_setupEncrypt(handle, &cryptoKey, sizeof(aad), sizeof(plaintext), sizeof(mac)); * if (decryptionResult != AESCCM_STATUS_SUCCESS) { * // handle error @@ -375,6 +435,19 @@ * // handle error * } * + * #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) // and the HSM is the engine of choice + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // You will also need to populate the mac in handle->object->mac because HSM needs the mac to construct each + * // segmented token. + * encryptionResult = AESCCMLPF3HSM_setMac(handle, &mac[0], 8); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * #endif + * * AESCCM_SegmentedAADOperation segmentedAADOperation; * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); * segmentedAADOperation.aad = aad; diff --git a/simplelink_lpf3/source/ti/drivers/AESCMAC.h b/simplelink_lpf3/source/ti/drivers/AESCMAC.h index af1b179b..dba56c90 100644 --- a/simplelink_lpf3/source/ti/drivers/AESCMAC.h +++ b/simplelink_lpf3/source/ti/drivers/AESCMAC.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Texas Instruments Incorporated + * Copyright (c) 2019-2023, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -161,6 +161,56 @@ * * @endcode * + * ### Single call CMAC authentication with plaintext CryptoKey in polling return mode and using HSM engine # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t mac[16]; + * + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * AESCMAC_Params_init(¶ms) + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_POLLING; + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * handle = AESCMAC_open(0, ¶ms); + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * int_fast16_t result = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * // 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C + * + * AESCMAC_close(handle); + * + * @endcode + * * ### Single call CMAC verification with plaintext CryptoKey in callback return mode # * @code * @@ -562,6 +612,12 @@ extern "C" { */ #define AESCMAC_STATUS_CANCELED AES_STATUS_CANCELED +/*! + * @brief The operation requested is not supported either by the target hardware + * or the driver implementation. + */ +#define AESCMAC_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + /*! * @brief The operation tried to load a key from the keystore using an invalid key ID. */ diff --git a/simplelink_lpf3/source/ti/drivers/AESCTR.h b/simplelink_lpf3/source/ti/drivers/AESCTR.h index c61c1097..7a1bde90 100644 --- a/simplelink_lpf3/source/ti/drivers/AESCTR.h +++ b/simplelink_lpf3/source/ti/drivers/AESCTR.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Texas Instruments Incorporated + * Copyright (c) 2018-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -215,6 +215,76 @@ * * @endcode * + *

The following code snippet is for CC27XX devices only and leverages the HSM which is a seperate Hardware + * Accelerator

+ * + *
One step CTR encryption with plaintext CryptoKey in blocking return mode using the HSM accelerator
+ * @code + * + * #include + * #include + * + * ... + * + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector from NIST SP 800-38A + * uint8_t initialCounter[16] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + * 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}; + * uint8_t plaintext[64] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, + * 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + * 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, + * 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + * + * handle = AESCTR_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation operation; + * AESCTR_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // The ciphertext should be the following after the encryption operation: + * // 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, + * // 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce, + * // 0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, + * // 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff, + * // 0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, + * // 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab, + * // 0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, + * // 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee + * + * AESCTR_close(handle); + * + * @endcode + * *
One step CTR decryption with plaintext CryptoKey in callback return mode
* @code * diff --git a/simplelink_lpf3/source/ti/drivers/ECDH.h b/simplelink_lpf3/source/ti/drivers/ECDH.h index e6fa1a47..42216170 100644 --- a/simplelink_lpf3/source/ti/drivers/ECDH.h +++ b/simplelink_lpf3/source/ti/drivers/ECDH.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, Texas Instruments Incorporated + * Copyright (c) 2017-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -252,6 +252,14 @@ * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. * ecdhHandle = ECDH_open(0, NULL); * + * // For CC27XX devices only, + * // Since the ECDH driver for CC27XX relies on one HW engine (the HSM) for all of its operations + * // If the HSM boot up sequence fails, ECDH_open() will return NULL. + * if (!ecdhHandle) { + * // Handle error + * } + * + * * // Initialize myPrivateKey and myPublicKey * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); * // Note that the public key size is only 32 bytes @@ -633,7 +641,8 @@ typedef struct typedef union { ECDH_OperationGeneratePublicKey *generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ - ECDH_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct + ECDH_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECDH_OperationComputeSharedSecret + * struct */ } ECDH_Operation; diff --git a/simplelink_lpf3/source/ti/drivers/GPIO.h b/simplelink_lpf3/source/ti/drivers/GPIO.h new file mode 100644 index 00000000..142dedc9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/GPIO.h @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file GPIO.h + * + * @brief General Purpose I/O driver interface. + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The GPIO module allows you to manage General Purpose I/O pins via simple + * and portable APIs. GPIO pin behavior is usually configured statically, + * but can also be configured or reconfigured at runtime. + * + * Because of its simplicity, the GPIO driver does not follow the model of + * other TI-RTOS drivers in which a driver application interface has + * separate device-specific implementations. This difference is most + * apparent in the GPIOxxx_Config structure, which does not require you to + * specify a particular function table or object. + * + * # Usage # + * This section provides a basic \ref ti_drivers_GPIO_Synopsis + * "usage summary" and a set of \ref ti_drivers_GPIO_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * GPIO APIs and their effect are provided in subsequent sections. + * + * @anchor ti_drivers_GPIO_Synopsis + * ### Synopsis # + * @anchor ti_drivers_GPIO_Synopsis_Code + * @code + * // Import GPIO Driver definitions + * #include + * + * // Define names for GPIO pin indexes + * #define BUTTON 0 + * #define LED 1 + * + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Read GPIO pin + * unsigned int state = GPIO_read(BUTTON); + * + * // Write to GPIO pin + * GPIO_write(LED, state); + * @endcode + * + * @anchor ti_drivers_GPIO_Examples + * ### Examples # + * * @ref ti_drivers_GPIO_Example_callback "Creating an input callback" + * * @ref ti_drivers_GPIO_Example_reconfigure "Runtime pin configuration" + * + * @anchor ti_drivers_GPIO_Example_callback + * **Creating an input callback**: The following example demonstrates how + * to configure a GPIO pin to generate an interrupt and how to toggle an + * an LED on and off within the registered interrupt callback function. Pin + * configuration is handled within Sysconfig for this example. + * @code + * // Driver header file + * #include + * + * // TI Drivers Configuration + * #include "ti_drivers_config.h" + * + * // GPIO button call back function + * void gpioButton0Fxn(uint_least8_t index); + * + * main() + * { + * // Turn on user LED + * GPIO_write(CONFIG_GPIO_LED0, CONFIG_GPIO_LED_ON); + * + * // install Button callback and enable interrupts + * GPIO_setCallback(CONFIG_GPIO_BUTTON0, gpioButton0Fxn); + * GPIO_enableInt(CONFIG_GPIO_BUTTON0); + * } + * + * // + * // ======== gpioButton0Fxn ======== + * // Callback function for the GPIO interrupt on CONFIG_GPIO_BUTTON0 + * // + * // Note: index is the GPIO id for the button which is not used here + * // + * void gpioButton0Fxn(uint_least8_t index) + * { + * // Toggle the LED + * GPIO_toggle(CONFIG_GPIO_LED0); + * } + * @endcode + * + * @anchor ti_drivers_GPIO_Example_reconfigure + * **Runtime pin configuration**: The following example demonstrates how + * to (re)configure GPIO pins. + * @code + * // Driver header file + * #include + * + * // TI Driver configuration + * #include "ti_drivers_config.h" + * + * void main() + * { + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Configure a button pin as input and configure its interrupt + * // Passing INT_ENABLE means you do not need to also call GPIO_enableInt() + * GPIO_setConfig( + * CONFIG_GPIO_BUTTON0, + * GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING | GPIO_CFG_INT_ENABLE + * ); + * + * // Configure an LED output pin + * GPIO_setConfig(CONFIG_GPIO_LED0, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + * } + * @endcode + * + * ### GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the ti_drivers_config.c file: + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin on the device. A pin is then + * referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and + * device specific pin identification are configured in each element + * of this array (see @ref GPIO_PinConfigSettings). + * Below is a device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // + * GPIO_PinConfig gpioPinConfigs[31] = { + * GPIO_CFG_INPUT, // DIO_0 + * GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_NONE, // CONFIG_GPIO_LP19 + * GPIO_CFG_INPUT, // DIO_2 + * GPIO_CFG_INPUT, // DIO_3 + * ... + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins. The indexes for these array + * elements correspond to the pins defined in the GPIO_pinConfig array. + * These function pointers can be defined statically by referencing the + * callback function name in the array element, or dynamically, by setting + * the array element to NULL and using GPIO_setCallback() at runtime to + * plug the callback entry. The callback function syntax should match the + * following: + * @code + * void (*GPIO_CallbackFxn)(uint_least8_t index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * @remark Callback functions are called in the context of an interrupt + * service routine and should be designed accordingly. + * + * When an interrupt is triggered, the interrupt status of all + * (interrupt enabled) pins on a port will be read, cleared, and the + * respective callbacks will be executed. Callbacks will be called in order + * from least significant bit to most significant bit. + * Below is a device specific example of the GPIO_CallbackFxn array: + * @code + * // + * // Array of callback function pointers + * // + * GPIO_CallbackFxn gpioCallbackFunctions[31] = { + * NULL, // DIO_0 + * NULL, // DIO_1 + * myGpioCallback, // CONFIG_GPIO_LP19 + * NULL, // DIO_3 + * ... + * }; + * @endcode + * + * 3. A device specific GPIO_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is a device specific example of a GPIO_Config structure: + * @code + * // + * // ======== GPIO_config ======== + * // + * const GPIO_Config GPIO_config = { + * .configs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .intPriority = (~0) + * }; + * @endcode + * + * ### Initializing the GPIO Driver # + * + * GPIO_init() must be called before any other GPIO APIs. This function + * configures each GPIO pin in the user-provided @ref GPIO_PinConfig + * array according to the defined settings. The user can also reconfigure + * a pin dynamically after GPIO_init() is called by using the + * GPIO_setConfig(), and GPIO_setCallback() APIs. + * + * GPIO_init() is called from Board_init() by default. Calling GPIO_init() + * multiple times is safe. + * + * # Implementation # + * + * Unlike most other TI-RTOS drivers, there is no notion of an instance + * 'handle' with the GPIO driver. This allows lightweight pin control with + * minimal runtime and memory overhead. + * + * GPIO pins are always referenced by device DIO index. + * + ****************************************************************************** + */ + +#ifndef ti_drivers_GPIO__include +#define ti_drivers_GPIO__include + +#include + +#include + +/* The device-specific header is used to map GPIO_CFG_X_INTERNAL definitions + * directly to device-specific configuration values, allowing efficient runtime + * reconfiguration without the need for bit twiddling. + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 || DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + #include +#endif + +/* Generic functions for converting pin indexes to and from masks. Internal use + * only. CLZ is an ARM instruction for `count leading zeroes`, so if multiple + * bits in the pinmask are set MASK_TO_PIN will only return the highest set + * bit. PIN_TO_MASK is used for setting registers. + */ +#if defined(__IAR_SYSTEMS_ICC__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __CLZ(pinmask)) +#elif defined(__TI_COMPILER_VERSION__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __clz(pinmask)) +#elif defined(__GNUC__) && !defined(__TI_COMPILER_VERSION__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __builtin_clz(pinmask)) +#endif + +#define GPIO_PIN_TO_MASK(pin) (1 << (pin)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs. + * @{ + */ + +/*! + * @brief Successful status code returned by GPIO_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define GPIO_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by GPIO_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed + * successfully. + */ +#define GPIO_STATUS_ERROR (-1) +/** @}*/ + +/*! + * @brief GPIO pin configuration settings + * + * The meaning of the bits within PinConfig are entirely device-specific + * and are typically one-to-one with the hardware register controlling pin + * configuration. + * + * Only create and manipulate these values using GPIO_CFG_* defines. + */ +typedef uint32_t GPIO_PinConfig; + +/*! + * @brief Dummy value for "this pin is not assigned to a GPIO". + * + * Not for use in customer software. Some drivers use this value to manage the + * behaviour of optional pins (e.g. UART flow control, SPI chip select). If you + * pass this value to any GPIO methods, it will return immediately and no + * register writes will be performed. + */ +#define GPIO_INVALID_INDEX 0xFF + +/*! + * \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins + * @{ + */ +/** @name GPIO_PinConfig output pin configuration macros + * @{ + */ +/*! @hideinitializer Pin is an output. Equivalent to OUT_STD. */ +#define GPIO_CFG_OUTPUT GPIO_CFG_OUTPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is actively driven high and low */ +#define GPIO_CFG_OUT_STD GPIO_CFG_OUTPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is Open Drain */ +#define GPIO_CFG_OUT_OD_NOPULL GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is Open Drain w/ pull up */ +#define GPIO_CFG_OUT_OD_PU GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_UP_INTERNAL +/*! @hideinitializer Output pin is Open Drain w/ pull dn */ +#define GPIO_CFG_OUT_OD_PD GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_DOWN_INTERNAL + +/*! @hideinitializer Set output pin strength to low */ +#define GPIO_CFG_OUT_STR_LOW GPIO_CFG_DRVSTR_LOW_INTERNAL +/*! @hideinitializer Set output pin strength to medium */ +#define GPIO_CFG_OUT_STR_MED GPIO_CFG_DRVSTR_MED_INTERNAL +/*! @hideinitializer Set output pin strength to high */ +#define GPIO_CFG_OUT_STR_HIGH GPIO_CFG_DRVSTR_HIGH_INTERNAL + +/*! @hideinitializer Set pin's output to 1. */ +#define GPIO_CFG_OUT_HIGH GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL +/*! @hideinitializer Set pin's output to 0. */ +#define GPIO_CFG_OUT_LOW GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig input pin configuration macros + * @{ + */ +/*! @hideinitializer Pin is an input. */ +#define GPIO_CFG_INPUT GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Input pin with no internal PU/PD */ +#define GPIO_CFG_IN_NOPULL GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Input pin with internal PU */ +#define GPIO_CFG_IN_PU GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_UP_INTERNAL +/*! @hideinitializer Input pin with internal PD */ +#define GPIO_CFG_IN_PD GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_DOWN_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig nondirectional pin configuration macros + * @{ + */ +/*! @hideinitializer Input and output are both disabled. Primarily useful for disabling muxed pins. */ +#define GPIO_CFG_NO_DIR GPIO_CFG_NO_DIR_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig pin inversion configuration macros + * @{ + */ +/*! @hideinitializer Input/output values are normal (default) */ +#define GPIO_CFG_INVERT_OFF GPIO_CFG_INVERT_OFF_INTERNAL +/*! @hideinitializer Input/output values are inverted */ +#define GPIO_CFG_INVERT_ON GPIO_CFG_INVERT_ON_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig pin hysteresis configuration macros + * @{ + */ +/*! @hideinitializer Input hysteresis is disabled (default) */ +#define GPIO_CFG_HYSTERESIS_OFF GPIO_CFG_HYSTERESIS_OFF_INTERNAL +/*! @hideinitializer Input hysteresis is enabled */ +#define GPIO_CFG_HYSTERESIS_ON GPIO_CFG_HYSTERESIS_ON_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig slew rate configuration macros + * @{ + */ +/*! @hideinitializer Output slew rate is unchanged (default) */ +#define GPIO_CFG_SLEW_NORMAL GPIO_CFG_SLEW_NORMAL_INTERNAL +/*! @hideinitializer Output slew rate is reduced */ +#define GPIO_CFG_SLEW_REDUCED GPIO_CFG_SLEW_REDUCED_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig interrupt configuration macros + * @{ + */ +/*! @hideinitializer No Interrupt (default) */ +#define GPIO_CFG_IN_INT_NONE GPIO_CFG_INT_NONE_INTERNAL +/*! @hideinitializer Interrupt on falling edge */ +#define GPIO_CFG_IN_INT_FALLING GPIO_CFG_INT_FALLING_INTERNAL +/*! @hideinitializer Interrupt on rising edge */ +#define GPIO_CFG_IN_INT_RISING GPIO_CFG_INT_RISING_INTERNAL +/*! @hideinitializer Interrupt on both edges */ +#define GPIO_CFG_IN_INT_BOTH_EDGES GPIO_CFG_INT_BOTH_EDGES_INTERNAL +/*! @hideinitializer Interrupt on low level */ +#define GPIO_CFG_IN_INT_LOW GPIO_CFG_INT_LOW_INTERNAL +/*! @hideinitializer Interrupt on high level */ +#define GPIO_CFG_IN_INT_HIGH GPIO_CFG_INT_HIGH_INTERNAL + +/*! @hideinitializer Interrupt disabled (default) */ +#define GPIO_CFG_INT_DISABLE GPIO_CFG_INT_DISABLE_INTERNAL +/*! @hideinitializer Interrupt enabled */ +#define GPIO_CFG_INT_ENABLE GPIO_CFG_INT_ENABLE_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig power mode configuration macros + * @brief For devices that support low power modes, standard GPIO interrupts + * may be disabled in some modes. These defines allow configuring individual + * pins as wake-up sources. The GPIO module's wake up configuration is always + * enabled if it exists, so there is no module-level configuration. + * See the device-specific header files for details. + * @{ + */ +/*! @hideinitializer This pin will not wake the device up */ +#define GPIO_CFG_SHUTDOWN_WAKE_OFF GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL +/*! @hideinitializer A high value will wake the device from shutdown */ +#define GPIO_CFG_SHUTDOWN_WAKE_HIGH GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL +/*! @hideinitializer A low value will wake the device from shutdown */ +#define GPIO_CFG_SHUTDOWN_WAKE_LOW GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL +/** @} */ + +/** @name GPIO_pinconfig macro preventing configuration + * @brief Should be used if a pin is configured before the first GPIO_init() + * call, and should not be overwritten + * @{ + */ +/*! @hideinitializer Prevent this GPIO from being configured + * by the GPIO driver */ +#define GPIO_CFG_DO_NOT_CONFIG GPIO_CFG_DO_NOT_CONFIG_INTERNAL +/** @} */ + +/** @name GPIO_Mux configuration macros + * @brief For additional muxing options, see the directions in the + * device-specific GPIO driver. + * @{ + */ +/*! @hideinitializer Set this pin to be a GPIO (the default) */ +#define GPIO_MUX_GPIO GPIO_MUX_GPIO_INTERNAL +/** @} */ +/** @} end of GPIO_PinConfigSettings group */ + +/*! + * @brief GPIO callback function type + * + * @param index GPIO index. This is the same index that + * was passed to GPIO_setCallback(). This allows + * you to use the same callback function for multiple + * GPIO interrupts, by using the index to identify + * the GPIO that caused the interrupt. + */ +typedef void (*GPIO_CallbackFxn)(uint_least8_t index); + +/*! + * @brief GPIO driver configuration structure + * + * The GPIO_Config struct contains the defaults for pin configuration. + * + * The interrupt priority of all pins configured to generate interrupts + * is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + */ +typedef struct +{ + GPIO_PinConfig *configs; + GPIO_CallbackFxn *callbacks; + void **userArgs; + uint32_t intPriority; +} GPIO_Config; + +/*! + * @brief Clear a GPIO pin interrupt flag + * + * Clears the GPIO interrupt for the specified index. + * + * Note: It is not necessary to call this API within a callback assigned + * to a pin. The driver clears interrupt flags before dispatching callbacks. + * + * @param index GPIO index + */ +extern void GPIO_clearInt(uint_least8_t index); + +/*! + * @brief Disable a GPIO pin interrupt + * + * Disables interrupts for the specified GPIO index. + * + * @param index GPIO index + */ +extern void GPIO_disableInt(uint_least8_t index); + +/*! + * @brief Enable a GPIO pin interrupt + * + * Enables GPIO interrupts for the selected index to occur. + * + * Note: Prior to enabling a GPIO pin interrupt, make sure + * that a corresponding callback function has been provided. + * Use the GPIO_setCallback() API for this purpose at runtime. + * Alternatively, the callback function can be statically + * configured in the GPIO_CallbackFxn array provided. + * + * @param index GPIO index + */ +extern void GPIO_enableInt(uint_least8_t index); + +/*! + * @brief Initializes the GPIO module + * + * The pins defined in the application-provided *GPIO_config* structure + * are initialized accordingly. + * + * @pre The GPIO_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GPIO driver APIs. + */ +extern void GPIO_init(void); + +/*! + * @brief Reads the value of a GPIO pin + * + * The value returned will either be zero or one depending on the + * state of the pin. + * + * @param index GPIO index + * + * @return 0 or 1, depending on the state of the pin. + */ +extern uint_fast8_t GPIO_read(uint_least8_t index); + +/*! + * @brief Toggles the current state of a GPIO + * + * @param index GPIO index + */ +extern void GPIO_toggle(uint_least8_t index); + +/*! + * @brief Writes the value to a GPIO pin + * + * @param index GPIO index + * @param value must be either 0 or 1 + */ +extern void GPIO_write(uint_least8_t index, unsigned int value); + +/*! + * @brief Bind a callback function to a GPIO pin interrupt + * + * Associate a callback function with a particular GPIO pin interrupt. + * + * Callbacks can be changed at any time, making it easy to switch between + * efficient, state-specific interrupt handlers. + * + * Note: The callback function is called within the context of an interrupt + * handler. + * + * Note: This API does not enable the GPIO pin interrupt. + * Use GPIO_enableInt() and GPIO_disableInt() to enable and disable the pin + * interrupt as necessary, or use GPIO_CFG_INT_ENABLE when calling setConfig. + * + * Note: it is not necessary to call GPIO_clearInt() within a callback. + * That operation is performed internally before the callback is invoked. + * + * @param index GPIO index + * @param callback address of the callback function + */ +extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback); + +/*! + * @brief Gets the callback associated with a GPIO pin. + * + * @param index GPIO index + * + * @return The callback function for the pin or NULL. + */ +extern GPIO_CallbackFxn GPIO_getCallback(uint_least8_t index); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For input pins with interrupt configurations, a corresponding interrupt + * object will be created as needed. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + * + * @return GPIO_STATUS_SUCCESS or an error if the pin cannot be configured + */ +extern int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * This variant only allows configuring the interrupt settings (rising edge, + * falling edge, etc.) and enabling or disabling interrupts. + * + * Only GPIO_CFG_IN_INT_XXX macros and GPIO_CFG_INT_ENABLE/DISABLE may be + * passed to the config parameter for this function. If you do not pass + * GPIO_CFG_INT_ENABLE, this function will disable interrupts. + * + * @param index GPIO index + * @param config pin configuration settings + */ +extern void GPIO_setInterruptConfig(uint_least8_t index, GPIO_PinConfig config); + +/*! + * @brief Get the current configuration for a gpio pin + * + * GPIO_getConfig() gets the current pin configuration. + * + * This value may not be identical to the value used in setConfig, as some + * configuration options are applied directly to hardware on some devices and + * not saved in order to save memory. + * + * @param index GPIO index + * @param pinConfig Location to store device specific pin + * configuration settings + */ +extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig); + +/*! + * @brief Resets the configuration for a gpio pin to the default value + * + * The default pin configuration is provided in the static GPIO_PinConfig + * array, defined by sysconfig or the board file at compile time. Also clears + * the callback and user argument. + * + * @param index GPIO index + */ +extern void GPIO_resetConfig(uint_least8_t index); + +/*! + * @brief Get the current mux for a gpio pin + * + * For details and valid mux options, see the device-specific header file. + * + * @param index GPIO index + * + * @return A device-specific mux value or GPIO_MUX_GPIO. + */ +extern uint32_t GPIO_getMux(uint_least8_t index); + +/*! + * @brief Configure the gpio pin's config and mux in a single write + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For some devices, configuring the pin and then muxing it can create a small + * drop on the line, which is enough to trigger some communication protocols. + * This helper function sets the pin configuration and the mux in a single access. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + * @param mux Device-specific mux value to use a special mode, + * or GPIO_MUX_GPIO to reset the pin to standard IO. + * + * @return GPIO_STATUS_SUCCESS or an error if the pin cannot be configured + */ +extern int_fast16_t GPIO_setConfigAndMux(uint_least8_t index, GPIO_PinConfig pinConfig, uint32_t mux); + +/*! + * @brief Set the user argument for a gpio pin + * + * This can be retrieved using GPIO_getUserArg() and can be helpful to share + * callback logic across different pins. + * + * @param index GPIO index + * @param arg Pointer to a user object + */ +void GPIO_setUserArg(uint_least8_t index, void *arg); + +/*! + * @brief Get the user argument for a gpio pin + * + * @param index GPIO index + * + * @return Pointer to a user object set by GPIO_setUserArg() + */ +void *GPIO_getUserArg(uint_least8_t index); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIO__include */ diff --git a/simplelink_lpf3/source/ti/drivers/Power.h b/simplelink_lpf3/source/ti/drivers/Power.h index 2048c614..9789f81c 100644 --- a/simplelink_lpf3/source/ti/drivers/Power.h +++ b/simplelink_lpf3/source/ti/drivers/Power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, Texas Instruments Incorporated + * Copyright (c) 2015-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -524,8 +524,7 @@ uint_fast32_t Power_getConstraintMask(void); * declared upon a resource. * * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. + * device-specific Power include file. * * @param[in] resourceId resource id * @@ -571,8 +570,7 @@ int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId); * notifications. * * Sleep states are device specific, and defined in the device-specific Power - * include file. For example, the sleep states for CC32XX are defined in - * PowerCC32XX.h. + * include file. * * This function is typically called by the power policy function. The latency * is reported in units of microseconds. @@ -746,8 +744,7 @@ int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); * a resource (by a call to Power_setDependency()). * * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. + * device-specific Power include file. * * @param[in] resourceId resource id * @@ -825,8 +822,7 @@ int_fast16_t Power_setConstraint(uint_fast16_t constraintId); * released. * * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. + * device-specific Power include file. * * @param[in] resourceId resource id * @@ -855,14 +851,12 @@ void Power_setPolicy(Power_PolicyFxn policy); /*! * @brief Put the device into a shutdown state * - * This function will transition the device into a shutdown state. - * Before the actual transition is initiated, notifications will be sent to - * any clients who've registered (with Power_registerNotify()) for an - * 'entering shutdown' event. The event name is device specific, and defined - * in the device-specific Power include file. For example, for CC32XX, the - * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in - * PowerCC32XX.h. Once notifications have been completed, the device shutdown - * will commence. + * This function will transition the device into a shutdown state. Before the + * actual transition is initiated, notifications will be sent to any clients + * who've registered (with Power_registerNotify()) for an 'entering shutdown' + * event. The event name is device specific, and defined in the + * device-specific Power include file. Once notifications have been completed, + * the device shutdown will commence. * * If the device is successfully transitioned to shutdown, this function * call will never return. Upon wakeup, the device and application will @@ -879,8 +873,7 @@ void Power_setPolicy(Power_PolicyFxn policy); * be ignored.) If the specified shutdownTime is zero, or otherwise less than * the total shutdown latency for the device, the shutdownTime parameter will * be ignored. The shutdown latency for the device can be found in the - * device-specific Power include file. For example, for the CC32XX, this - * latency is defined in PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) + * device-specific Power include file. * * @param[in] shutdownState the device-specific shutdown state * @@ -948,8 +941,6 @@ void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) #include -#elif (DeviceFamily_ID == DeviceFamily_ID_CC3220 || DeviceFamily_ID == DeviceFamily_ID_CC3200) - #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) #include #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) diff --git a/simplelink_lpf3/source/ti/drivers/RNG.c b/simplelink_lpf3/source/ti/drivers/RNG.c new file mode 100644 index 00000000..6f9ca3e6 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/RNG.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RNG.c ======== + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const RNG_Config RNG_config[]; +extern const uint_least8_t RNG_count; + +const RNG_Params RNG_defaultParams = {.returnBehavior = RNG_RETURN_BEHAVIOR_BLOCKING, + .cryptoKeyCallbackFxn = NULL, + .randomBitsCallbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER}; + +/* + * ======== RNG_open ======== + */ +RNG_Handle RNG_open(uint_least8_t index, const RNG_Params *params) +{ + DebugP_assert(index <= RNG_count); + + const RNG_Config *config = (const RNG_Config *)&RNG_config[index]; + + return RNG_construct(config, params); +} diff --git a/simplelink_lpf3/source/ti/drivers/RNG.h b/simplelink_lpf3/source/ti/drivers/RNG.h new file mode 100644 index 00000000..369073c1 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/RNG.h @@ -0,0 +1,994 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file RNG.h + * + * @brief RNG driver header + * + * @anchor ti_drivers_RNG_Overview + * # Overview # + * The Random Number Generator (RNG) module generates random data of variable + * lengths from a pool of entropy. The pool of entropy is maintained by the + * driver using implementation-specific sources of entropy. + * The output is suitable for applications requiring cryptographically + * random data such as keying material for private or symmetric keys. + * + * @anchor ti_drivers_RNG_Usage + * # Usage # + * + * ## Initialization ## + * Unlike most drivers, there is a global instance of RNG driver data + * that is always available once #RNG_init() is called. This data will contain + * the entropy pool and any needed state information required to refill the + * pool. #RNG_init() should be called once before using other RNG + * driver APIs. + * + * @note Some implementations restrict when RNG_init() may be called. + * Check the implementation's documentation for more information. + * + * For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps prior to the use of the Radio because CC23X0 uses the ADC samples + * from radio as noise that is conditioned using CBC MAC to generate the seed for RNG driver + * + * ### Step 1: Required header file ### + * + * @code + * + * #include // required for external syscfg variable RNGLPF3RF_noiseInputWordLen + * + * @endcode + * + * ### Step 2: External APIs ### + * + * @code + * + * // Use the function provided by RCL to read noise input // + * extern int_fast16_t RCL_AdcNoise_get_samples_blocking(uint32_t *buffer, uint32_t numWords); + * + * @endcode + * + * ### Step 3: Read noise input from RCL using RCL_AdcNoise_get_samples_blocking() ### + * + * @code + * + * int_fast16_t rclStatus, result; + + * // User's global array for noise input based on size provided in syscfg // + * uint32_t localNoiseInput[]; //Minimum array size 80 words + * + * // Clear noise input // + * memset(localNoiseInput, 0, sizeof(localNoiseInput)); + * + * // Fill noise input from RCL // + * //RNGLPF3RF_noiseInputWordLen is external variable from RNGLPF3RF.h + * rclStatus = RCL_AdcNoise_get_samples_blocking(localNoiseInput, RNGLPF3RF_noiseInputWordLen); + * + * if (rclStatus != 0) + * { + * //Handle error; + * } + * + * // Initialize the RNG driver noise input pointer with global noise input array from user // + * result = RNGLPF3RF_conditionNoiseToGenerateSeed(localNoiseInput); + * if ( rclStatus != 0) + * { + * //Handle error; + * } + * + * @endcode + * + * + * ## Before starting a RNG operation ## + * + * Before starting a RNG operation, the application must do the following: + * - Call RNG_init() to initialize the driver's global instance data. + * - Call RNG_Params_init() to initialize the RNG_Params to default values. + * - Modify the RNG_Params as desired. + * - Call RNG_open() to open an instance of the driver. + * + * @note Some implementations restrict when RNG_init() may be called. + * Check the implementation's documentation for more information. + * + * ## Entropy Pool Management ## + * + * At any time after calling RNG_init(), the application may call + * RNG_fillPoolIfLessThan() to add entropy to the pool which will then make + * future requests for entropy execute faster. Note that the driver never + * automatically refills the pool. However, if the pool is empty, the RNG + * driver will still generate entropy upon request (for example when + * RNG_getRandomBits() is called). + * + * The application is responsible for deciding when it is appropriate to + * spend the time and energy to refill the pool. One suggested location + * to do so is the idle thread. + * + * ## RNG operations ## + * + * Use RNG_getRandomBits() to obtain random bits from the entropy pool and + * copy them to a buffer/array. The caller must allocate memory sufficient + * to hold at least the number of bits of random data requested. + * + * ## After the RNG operation completes ## + * + * After the RNG operation completes, the application should either start + * another operation or close the driver by calling RNG_close(). Note that the + * singleton instance of the driver, along with its associated pool of entropy + * will still exist and will be used by any future RNG_open() calls. Note that + * closing the driver instance may not be strictly required, but is good + * practice. + * + * ## Security ## + * + * ### Data Protection ### + * + * The entropy pool and any required state to generate more entropy is + * maintained in memory, in the driver's global instance data. The entirety of + * this data is stored in two global variables called RNG_instanceData and + * RNG_instancePool. It is up to the system to provide adequate + * protection (primarily confidentiality and integrity) of these in-memory + * assets. + * + * ### Timing Side Channels ### + * + * Functions which provide for generation of a value within a range use + * an algorithm which is timing-constant when the following parameters + * are held constant: lowerLimit, upperLimit, bitLength, + * and endianess. Thus, while the driver may create multiple candidates for the + * value to find one within the range, timing will not leak the final + * value's relation to the limits. However, timing may leak the bitLength, + * the endianess, and the use of #CryptoUtils_limitZero, #CryptoUtils_limitOne, + * or NULL for the limit values. + * + * @anchor ti_drivers_RNG_Synopsis + * ## Synopsis + * @anchor ti_drivers_RNG_Synopsis_Code + * ### Generate random bytes to a user provided buffer # + * + * @code + * + * #include + * #include "ti_drivers_config.h" + * + * // Setup RNG + * RNG_Init(); + * RNG_fillPoolIfLessThan(RNG_POOL_BYTE_SIZE); + * + * // Use RNG + * #define RANDOM_BYTES_SIZE 16u + * RNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * result = RNG_getRandomBits(handle, randomBytesArray, RANDOM_BYTES_SIZE * 8); + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * // Refill RNG Pool when convenient + * RNG_fillPoolIfLessThan(RNG_POOL_BYTE_SIZE); + * @endcode + * + * @anchor ti_drivers_RNG_Examples + * ## Examples + * + * The following examples do not show the process of initializing the RNG + * module and refilling the pool. + * See @ref ti_drivers_RNG_Synopsis RNG Driver Synopsis for an example + * showing those parts of RNG operation. * + * + * ### Generate a number within a range ### + * + * @code + * + * #include + * + * #define RANDOM_BIT_SIZE 15u + * #define RANDOM_BYTE_SIZE ((RANDOM_BIT_SIZE + 7u)/8u) + * + * RNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * uint8_t upperLimit[RANDOM_BYTES_SIZE] = {0xA9, 0x61}; // 25,001, LE format + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * // Generate a number from 1 to 25,000 (inclusive) + * // Note that lowerLimit parameter is inclusive and upperLimit is + * // exclusive. Thus, upperLimit is set to 25,001. + * result = RNG_getLERandomNumberInRange(RNG_Handle handle, RNG_limitOne, + * upperLimit, randomBytesArray, + * RANDOM_BIT_SIZE); + * + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * @endcode + * + * + * ### Generate an ECC private key ### + * + * @code + * + * #include + * #include + * + * // Values are chosen to generate a NIST 256 bit key. + * CryptoKey privateKey; + * uint8_t privateKeyingMaterial[NISTP256_PARAM_SIZE_BYTES]; + * RNG_Handle handle; + * int_fast16_t result; + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initBlankKey(&privateKey, privateKeyingMaterial, + * ECCParams_NISTP256.length); + * + * // Generate NIST 256 bit key in BE format. + * result = RNG_generateBEKeyInRange(RNG_Handle handle, RNG_limitOne, + * ECCParams_NISTP256.order, privateKey, + * 256); + * + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * @endcode + * + */ + +#ifndef ti_drivers_RNG__include +#define ti_drivers_RNG__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common RNG status code reservation offset. + * RNG driver implementations should offset status codes with + * RNG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define RNGXYZ_STATUS_ERROR0 ((int_fast16_t) (RNG_STATUS_RESERVED - 0)) + * #define RNGXYZ_STATUS_ERROR1 ((int_fast16_t) (RNG_STATUS_RESERVED - 1)) + * #define RNGXYZ_STATUS_ERROR2 ((int_fast16_t) (RNG_STATUS_RESERVED - 2)) + * @endcode + */ +#define RNG_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return RNG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define RNG_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return RNG_STATUS_ERROR if the function was not executed + * successfully. + */ +#define RNG_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * RNG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ +#define RNG_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief Operation failed due to invalid inputs. + * + * Functions return RNG_STATUS_INVALID_INPUTS if input validation fails. + */ +#define RNG_STATUS_INVALID_INPUTS ((int_fast16_t)-3) + +/*! + * @brief The ongoing operation was canceled. + */ +#define RNG_STATUS_CANCELED ((int_fast16_t)-4) + +/*! + * @brief The pool of entropy has been exhausted and additional entropy cannot + * be generated. A reset of the system may be required to generate more + * entropy. + */ +#define RNG_ENTROPY_EXHAUSTED ((int_fast16_t)-5) + +/*! + * @brief Some implementations have restrictions on how often or when + * RNG_init may be called. See the documentation for the implementation + * for more information. + */ +#define RNG_STATUS_INIT_NOT_ALLOWED ((int_fast16_t)-6) + +/*! + * @brief Some implementations require a noise input during initialization + * which is conditioned to seed the RNG driver. RNG_init() will return this + * error if the noise input pointer is not intialized with valid information. + * See documentation for the implementation for more information. + */ +#define RNG_STATUS_NOISE_INPUT_INVALID ((int_fast16_t)-7) + +/*! + * @brief RNG driver not intialized. + * + * @note Some implementations restrict when RNG_init() may be called. + * Refer to #RNG_init() for more information. + */ +#define RNG_STATUS_NOT_INITIALIZED ((int_fast16_t)-7) + +/*! + * @brief Maximum number of bits that may be requested in a single call + */ +#define RNG_MAX_BIT_LENGTH ((size_t)1u << 20u) /* 1 MiB */ + +/*! + * @brief RNG Global configuration + * + * The RNG_Config structure contains a set of pointers used to characterize + * the RNG driver implementation. + * + * This structure needs to be defined before calling RNG_init() and it must + * not be changed thereafter. + * + * @sa RNG_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} RNG_Config; + +/*! + * @brief A handle that is returned from a RNG_open() call. + */ +typedef const RNG_Config *RNG_Handle; + +/*! + * @brief The way in which RNG function calls return after generating + * the requested entropy. + * + * Not all RNG implementations support all of the return behavior options. + * + * Not all RNG operations exhibit the specified return behavior. Functions that + * do not require significant computation and cannot offload that computation to + * a background thread behave like regular functions. Which functions exhibit + * the specified return behavior is not implementation dependent. Specifically, + * a software-backed implementation run on the same CPU as the application will + * emulate the return behavior while not actually offloading the computation to + * the background thread. + * + * RNG functions exhibiting the specified return behavior have restrictions on + * the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |------------------------------|-------|-------|-------| + * | RNG_RETURN_BEHAVIOR_CALLBACK | X | | | + * | RNG_RETURN_BEHAVIOR_BLOCKING | X | | | + * | RNG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + RNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * RNG operation goes on in the background. The + * registered callback function is called after the + * operation completes. The context the callback + * function is called (task, HWI, SWI) is + * implementation-dependent. + */ + RNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while RNG operation + * goes on in the background. RNG operation results + * are available after the function returns. + */ + RNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag + * while RNG operation goes on in the background. RNG + * operation results are available after the function + * returns. + */ +} RNG_ReturnBehavior; + +/*! + * @brief The definition of a callback function used by the RNG driver + * when RNG_generateKey(), RNG_generateLEKeyInRange(), or + * RNG_generateBEKeyInRange() is called with ::RNG_RETURN_BEHAVIOR_CALLBACK + * + * @warning Attempting to make calls to the RNG driver from the callback + * may result in deadlock. + * + * @param handle Handle of the client that started the RNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param key The CryptoKey that describes the location the generated + * entropy will be copied to. + */ +typedef void (*RNG_CryptoKeyCallbackFxn)(RNG_Handle handle, int_fast16_t returnValue, CryptoKey *key); + +/*! + * @brief The definition of a callback function used by the RNG driver + * when RNG_getRandomBits(), RNG_getLERandomNumberInRange(), + * or RNG_getBERandomNumberInRange is called with + * ::RNG_RETURN_BEHAVIOR_CALLBACK + * + * @warning Attempting to make calls to the RNG driver from the callback + * may result in deadlock. + * + * @param handle Handle of the client that started the RNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param randomBits Pointer to an array that stores the random bits + * output by this function. + * + * @param randomBitsLength The length of the random data generated, in bits. + */ +typedef void (*RNG_RandomBitsCallbackFxn)(RNG_Handle handle, + int_fast16_t returnValue, + uint8_t *randomBits, + size_t randomBitsLength); + +/*! + * @brief RNG Parameters + * + * RNG Parameters are used with the RNG_open() call. Default values for + * these parameters are set using RNG_Params_init(). + * + * @attention When using the driver in #RNG_RETURN_BEHAVIOR_CALLBACK, + * set the appropriate callback function field to point to a + * valid callback function and set the other one to NULL. + * + * @sa RNG_Params_init() + */ +typedef struct +{ + RNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + RNG_CryptoKeyCallbackFxn cryptoKeyCallbackFxn; /*!< Callback function to use with RNG_generateKey() + * and RNG_generateKeyInRange(). + * Set randomBitsCallbackFxn to NULL if using this. + */ + RNG_RandomBitsCallbackFxn randomBitsCallbackFxn; /*!< Callback function to use with RNG_getRandomBits(), + * RNG_getLERandomNumberInRange(), and + * RNG_getBERandomNumberInRange(). + * Set cryptoKeyCallbackFxn to NULL if using this. + */ + uint32_t timeout; /*!< Timeout (in ClockP ticks) before the driver + * returns an error in ::RNG_RETURN_BEHAVIOR_BLOCKING + */ +} RNG_Params; + +/*! + * @brief Default RNG_Params structure + * + * @sa RNG_Params_init() + */ +extern const RNG_Params RNG_defaultParams; + +/*! + * @brief The byte size of the pool + */ +extern const size_t RNG_poolByteSize; + +/*! + * @brief This function initializes the RNG module. + * + * @pre The RNG_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other RNG driver APIs. This function call does not modify any + * peripheral registers. + * For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps prior to the use of the Radio because CC23X0 uses the ADC samples + * from radio as noise that is conditioned using CBC MAC + * to generate the seed for RNG driver + * 1. Read radio noise using RCL_AdcNoise_get_samples_blocking(). This RCL function must + * be called from a task context with interrupts enabled and therefore cannot be called + * by startup code. This must be executed prior to the use of the radio. + * 2. Condition the noise to seed the RNG using RNGLPF3RF_conditionNoiseToGenerateSeed(). + * 3. Initialize the RNG from the application with RNG_init() + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + */ +int_fast16_t RNG_init(void); + +/*! + * @brief Fills the pool with entropy if the number of bytes with entropy in + * the pool is less than the value specified. + * + * @note This function does not take in a handle and the implementation + * may run in either blocking or polling mode. + * + * @pre RNG_init() has to be called first. + * + * @param bytes Pool will be filled if current level is less than this number. + * Use RNG_POOL_BYTE_SIZE (from ti_drivers_config.h) to always fill. + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_ENTROPY_EXHAUSTED Pool could not be refilled, device + * may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_fillPoolIfLessThan(size_t bytes); + +/*! + * @brief Function to initialize the RNG_Params struct to its defaults + * + * @param params An pointer to RNG_Params structure for + * initialization + * + * Default values are:
+ * returnBehavior = RNG_RETURN_BEHAVIOR_BLOCKING
+ * cryptoKeyCallbackFxn = NULL
+ * randomBitsCallbackFxn = NULL
+ * timeout = SemaphoreP_WAIT_FOREVER
+ * custom = NULL
+ */ +void RNG_Params_init(RNG_Params *params); + +/*! + * @brief This function opens a given RNG peripheral. + * + * @pre RNG controller has been initialized using RNG_init() + * + * @param index Logical peripheral number for the RNG indexed into + * the RNG_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A RNG_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa RNG_init() + * @sa RNG_close() + */ +RNG_Handle RNG_open(uint_least8_t index, const RNG_Params *params); + +/*! + * @brief Function to close a RNG peripheral specified by the RNG handle + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open() + * + * @sa RNG_open() + */ +void RNG_close(RNG_Handle handle); + +/*! + * @brief Generate random bits and output to the given array. + * + * Generates random a random number of bits with length of \c randomBitsLength. + * The output length in bytes will be the minimum number of bytes needed + * to contain \c randomBitsLength. The output will be placed at the address + * pointed to by \c randomBits. The user shall be responsible for allocating + * sufficient memory starting at the address pointed at by \c randomBits to + * hold the number of bytes output. + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a + * callback function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateKey() to output random bytes to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param randomBits Pointer to an array that stores the random bits + * output by this function. + * + * @param randomBitsLength The length of the random data required, in bits. + * A maximum of 1MiB is allowed. + * + * @sa RNG_getLERandomNumberInRange + * @sa RNG_getBERandomNumberInRange + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_getRandomBits(RNG_Handle handle, void *randomBits, size_t randomBitsLength); + +/*! + * @brief Generate random number, stored in little-endian (LE) format, where + * the number is within the specified range. + * + * Generates random a random number within the range [lowerLimit, upperLimit) + * of bit size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed at the address pointed to by \c randomNumber. The user + * shall be responsible for allocating sufficient memory starting at the + * address pointed at by \c randomNumber to hold the number of bytes output. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateLEKeyInRange() to output a ranged number to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in LE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in LE format for the generated number. + * + * @param randomNumber Pointer to an array that stores the random number + * output by this function. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_getLERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength); + +/*! + * @brief Generate random number, stored in big-endian (BE) format, where + * the number is within the specified range. + * + * Generates random a random number within the range [lowerLimit, upperLimit) + * of bit size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed at the address pointed to by \c randomNumber. The user + * shall be responsible for allocating sufficient memory starting at the address + * pointed at by \c randomNumber to hold the number of bytes output. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateBEKeyInRange() to output a ranged number to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in BE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in BE format for the generated number. + * + * @param randomNumber Pointer to an array that stores the random number + * output by this function. + * + * @param randomNumberBitLength The length, in bits, of both the limit value + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_getBERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength); + +/*! + * @brief Generate random bits and output them to the given \c CryptoKey object. + * + * Generates a random bitstream of the size defined in the \c key + * CryptoKey in the range 0 <= \c key buffer < 2 ^ (entropy length * 8). + * The entropy will be generated and stored according to the storage + * requirements defined in the CryptoKey. The length of the entropy + * generated will be the same as the key length. + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a + * callback function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @sa RNG_generateLEKeyInRange + * @sa RNG_generateBEKeyInRange + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_generateKey(RNG_Handle handle, CryptoKey *key); + +/*! + * @brief Generate random number, in little-endian (LE) format, where the + * number is within the specified range. Store the random number in + * the given \c CryptoKey object. + * + * Generates a random number within the range [lowerLimit, upperLimit) of bit + * size \c randomNumberBitLength. The output length in bytes will be the minimum + * number of bytes needed to contain \c randomNumberBitLength. The output will + * be placed as specified by the members of \c key. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in LE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in LE format for the generated number. + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_generateLEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength); + +/*! + * @brief Generate random number, stored in big-endian (BE) format, where the + * number is within the specified range. Store the random number in + * the given \c CryptoKey object. + * + * Generates a random number within the range [lowerLimit, upperLimit) of bit + * size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed as specified by the members of \c key. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in BE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in BE format for the generated number. + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not intialized. + */ +int_fast16_t RNG_generateBEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength); + +/** + * @brief Constructs a new RNG object + * + * Unlike #RNG_open(), #RNG_construct() does not require the hwAttrs and + * object to be allocated in a #RNG_Config array that is indexed into. + * Instead, the #RNG_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #RNG_Config describing the location of the object and hwAttrs. + * + * @param params #RNG_Params to configure the driver instance. + * + * @return Returns a #RNG_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +RNG_Handle RNG_construct(const RNG_Config *config, const RNG_Params *params); + +/*! + * @brief Aborts an ongoing RNG operation and clears internal buffers. + * + * Aborts an operation to generate random bytes/entropy. The operation will + * terminate as though an error occurred and the status code of the operation + * will be #RNG_STATUS_CANCELED in this case. + * + * Any entropy already copied out of the pool will have already been removed + * from the pool and will not be reused for later requests. + * + * Canceling an operation may be delayed if the entropy pool is below its + * minimum fill mark as the driver will refill the pool before finishing + * the cancelled operation. + * + * @param handle A #RNG_Handle returned from #RNG_open() + * + * @retval #RNG_STATUS_SUCCESS The operation was canceled or there was no + * operation in progress to be canceled. + */ +int_fast16_t RNG_cancelOperation(RNG_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_RNG__include */ diff --git a/simplelink_lpf3/source/ti/drivers/Temperature.c b/simplelink_lpf3/source/ti/drivers/Temperature.c index e73147db..68c73162 100644 --- a/simplelink_lpf3/source/ti/drivers/Temperature.c +++ b/simplelink_lpf3/source/ti/drivers/Temperature.c @@ -43,37 +43,40 @@ /* * ======== Temperature_getThresholdHigh ======== */ -int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject) { +int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject) +{ return notifyObject->thresholdHigh; } /* * ======== Temperature_getThresholdLow ======== */ -int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject) { +int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject) +{ return notifyObject->thresholdLow; } /* * ======== Temperature_getThresholdRange ======== */ -void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, - int16_t *thresholdHigh, - int16_t *thresholdLow) { +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, int16_t *thresholdHigh, int16_t *thresholdLow) +{ *thresholdHigh = notifyObject->thresholdHigh; - *thresholdLow = notifyObject->thresholdLow; + *thresholdLow = notifyObject->thresholdLow; } /* * ======== Temperature_getClientArg ======== */ -uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject) { +uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject) +{ return notifyObject->clientArg; } /* * ======== Temperature_getNotifyFxn ======== */ -Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject) { +Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject) +{ return notifyObject->notifyFxn; } diff --git a/simplelink_lpf3/source/ti/drivers/Temperature.h b/simplelink_lpf3/source/ti/drivers/Temperature.h index 99c40700..2e60ac55 100644 --- a/simplelink_lpf3/source/ti/drivers/Temperature.h +++ b/simplelink_lpf3/source/ti/drivers/Temperature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Texas Instruments Incorporated + * Copyright (c) 2020-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -50,7 +50,8 @@ * Unlike most drivers, there is only a single instance of the temperature * driver that is always available once #Temperature_init() is called. * #Temperature_init() should be called once before using other Temperature - * driver APIs. Subsequent #Temperature_init() calls will have no effect. + * driver APIs. It is not called automatically via SysConfig generated code. + * Subsequent #Temperature_init() calls will have no effect. * * ## Getting the Current Temperature # * The most basic function of the driver is to provide the current temperature @@ -96,7 +97,7 @@ * the list of registered notifications and thus are no longer registered. * Their callback function is then invoked. * - * If an application wishes to reregister a notification that just triggered + * If an application wishes to re-register a notification that just triggered * and was unregistered, it may register it again from within the notification * callback or another context. * @@ -191,7 +192,7 @@ * * @endcode * - * ## Register a Range Threshold Notification and Reregister in Callback # + * ## Register a Range Threshold Notification and Re-register in Callback # * * @code * @@ -258,7 +259,7 @@ extern "C" { * #define TemperatureXYZ_STATUS_ERROR2 Temperature_STATUS_RESERVED - 2 * @endcode */ -#define Temperature_STATUS_RESERVED (-32) +#define Temperature_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -266,7 +267,7 @@ extern "C" { * Functions return Temperature_STATUS_SUCCESS if the function was executed * successfully. */ -#define Temperature_STATUS_SUCCESS (0) +#define Temperature_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -274,8 +275,7 @@ extern "C" { * Functions return Temperature_STATUS_ERROR if the function was not executed * successfully. */ -#define Temperature_STATUS_ERROR (-1) - +#define Temperature_STATUS_ERROR (-1) /* @cond * @@ -304,10 +304,10 @@ typedef struct Temperature_NotifyObj Temperature_NotifyObj; * inputs from within the notification * callback. */ -typedef void (*Temperature_NotifyFxn) (int16_t currentTemperature, - int16_t thresholdTemperature, - uintptr_t clientArg, - Temperature_NotifyObj *notifyObject); +typedef void (*Temperature_NotifyFxn)(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); /*! * @brief Temperature notify object structure. @@ -318,24 +318,27 @@ typedef void (*Temperature_NotifyFxn) (int16_t currentTemperature, * or #Temperature_registerNotifyRange() will take care initializing the * internal elements appropriately. */ -struct Temperature_NotifyObj { - List_Elem link; /*!< For placing on the notify list */ - Temperature_NotifyFxn notifyFxn; /*!< Application callback function */ - int16_t thresholdHigh; /*!< High threshold in degrees C */ - int16_t thresholdLow; /*!< Low threshold in degrees C */ - uintptr_t clientArg; /*!< Application provided arg */ - bool isRegistered; /*!< Is the notification active */ +struct Temperature_NotifyObj +{ + List_Elem link; /*!< For placing on the notify list */ + Temperature_NotifyFxn notifyFxn; /*!< Application callback function */ + int16_t thresholdHigh; /*!< High threshold in degrees C */ + int16_t thresholdLow; /*!< Low threshold in degrees C */ + uintptr_t clientArg; /*!< Application provided arg */ + bool isRegistered; /*!< Is the notification active */ }; - /*! * @brief This function initializes the Temperature driver. * * This function initializes the internal state of the Temperature driver. * It must be called before calling any other Temperature functions. Calling * this function multiple times will only have an effect the first time. + * + * @note This function should be called manually before using the temperature API. + * It will not be called automatically via SysConfig generated code. */ -void Temperature_init(); +void Temperature_init(void); /*! * @brief Gets the current temperature in degrees C. @@ -445,7 +448,6 @@ int_fast16_t Temperature_registerNotifyRange(Temperature_NotifyObj *notifyObject Temperature_NotifyFxn notifyFxn, uintptr_t clientArg); - /*! * @brief Unregisters a currently registered notification. * @@ -514,9 +516,7 @@ int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject); * * @pre Register @c notifyObject with #Temperature_registerNotifyRange() */ -void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, - int16_t *thresholdHigh, - int16_t *thresholdLow); +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, int16_t *thresholdHigh, int16_t *thresholdLow); /*! * @brief Get the application-provided clientArg of a notification. @@ -542,7 +542,6 @@ uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject); */ Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject); - #ifdef __cplusplus } #endif diff --git a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c index d24ecf60..2fa575a6 100644 --- a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c +++ b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -54,6 +54,12 @@ #include DeviceFamily_constructPath(inc/hw_aes.h) #include DeviceFamily_constructPath(inc/hw_ints.h) +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include + #include + #include +#endif + #if (defined(__IAR_SYSTEMS_ICC__) || defined(__TI_COMPILER_VERSION__)) #include #define REV32 __rev @@ -61,6 +67,13 @@ #define REV32 __builtin_bswap32 #endif +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #define PSA_SYM_MODE_GCM_NONE 0U + + /* Size of state asset for GCM/CCM continuation */ + #define KEY_TEMP_ASSET_SIZE 48U +#endif + /* Note: The AES-CCM one-step polling operations are specifically designed * to optimize execution speed at the expense of code re-use and size. */ @@ -130,6 +143,41 @@ static int_fast16_t AESCCMLPF3_processSegmentedCTR(AESCCMLPF3_Object *object, si static void AESCCMLPF3_processTagCTR(AESCCMLPF3_Object *object); static int_fast16_t AESCCMLPF3_waitForDMA(const AESCCMLPF3_Object *object); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +static int_fast16_t AESCCMLPF3HSM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); +static int_fast16_t AESCCMLPF3HSM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); +static int_fast16_t AESCCMLPF3HSM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation); +static int_fast16_t AESCCMLPF3HSM_addData(AESCCM_Handle handle, + AESCCM_OperationType operationType, + AESCCM_OperationUnion *operation, + const uint8_t *input, + uint8_t *output, + size_t inputLength); +static int_fast16_t AESCCMLPF3HSM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); +static int_fast16_t AESCCMLPF3HSM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); +static int_fast16_t AESCCMLPF3HSM_oneStepOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType); +static int_fast16_t AESCCMLPF3HSM_performFinalizeChecks(const AESCCMLPF3_Object *object, + const AESCCM_SegmentedFinalizeOperation *operation); +static int_fast16_t AESCCMLPF3HSM_setupSegmentedOperation(AESCCMLPF3_Object *object, + const CryptoKey *key, + size_t totalAADLength, + size_t totalDataLength, + size_t macLength); +static int_fast16_t AESCCMLPF3HSM_createTempAssetID(AESCCM_Handle handle, AESCCM_Mode direction); +static inline int_fast16_t AESCCMLPF3HSM_processOneStepOperation(AESCCM_Handle handle); +static int_fast16_t AESCCMLPF3HSM_freeTempAssetID(AESCCM_Handle handle); +#endif + /* * ======== AESCCMLPF3_getObject ======== */ @@ -361,6 +409,9 @@ static int_fast16_t AESCCMLPF3_waitForDMA(const AESCCMLPF3_Object *object) */ void AESCCM_init(void) { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + HSMLPF3_constructRTOSObjects(); +#endif AESCommonLPF3_init(); } @@ -375,6 +426,24 @@ AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *param AESCCM_Handle handle = config; AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Initialize and boot HSM */ + if (HSMLPF3_init() != HSMLPF3_STATUS_SUCCESS) + { + /* Upon HSM Boot failure, the AES-CCM Driver stores the failure status in the object + * This is done so that users of the AES-CCM Driver do not get a NULL handle and still can use + * the driver in LAES mode. + */ + object->hsmStatus = HSMLPF3_STATUS_ERROR; + } + else + { + object->hsmStatus = HSMLPF3_STATUS_SUCCESS; + + object->segmentedOperationInProgress = false; + } +#endif + /* If params are NULL, use defaults */ if (params == NULL) { @@ -422,7 +491,7 @@ static void AESCCMLPF3_processCBCMACFinalBlock(const uint8_t *input, size_t byte /* Zero out the BUF registers */ AESClearBUF(); - /* Copy directly to BUF registers. memcpy is safe to use here since the + /* Copy directly to BUF registers. (void)memcpy is safe to use here since the * order of the writes is not important when writing a partial block. */ (void)memcpy((void *)(AES_BASE + AES_O_BUF0), input, bytesRemaining); @@ -891,7 +960,23 @@ static int_fast16_t AESCCMLPF3_oneStepOperation(AESCCM_Handle handle, */ int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) { - return AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_ENCRYPT); + int_fast16_t status = AESCCM_STATUS_SUCCESS; + + if (operation->key->encoding == CryptoKey_PLAINTEXT || operation->key->encoding == CryptoKey_KEYSTORE) + { + status = AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_ENCRYPT); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCCMLPF3HSM_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_ENCRYPT); + } +#endif + else + { + status = AESCCM_STATUS_ERROR; + } + return status; } /* @@ -899,7 +984,23 @@ int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation */ int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) { - return AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_DECRYPT); + int_fast16_t status = AESCCM_STATUS_SUCCESS; + + if (operation->key->encoding == CryptoKey_PLAINTEXT || operation->key->encoding == CryptoKey_KEYSTORE) + { + status = AESCCMLPF3_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_DECRYPT); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCCMLPF3HSM_oneStepOperation(handle, operation, AESCCM_OP_TYPE_ONESTEP_DECRYPT); + } +#endif + else + { + status = AESCCM_STATUS_ERROR; + } + return status; } /* @@ -955,6 +1056,13 @@ int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, DebugP_assert(handle); AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCCMLPF3HSM_setupEncrypt(handle, key, totalAADLength, totalPlaintextLength, macLength); + } +#endif + int_fast16_t status = AESCCMLPF3_setupSegmentedOperation(object, key, totalAADLength, @@ -981,6 +1089,13 @@ int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCCMLPF3HSM_setupDecrypt(handle, key, totalAADLength, totalPlaintextLength, macLength); + } +#endif + int_fast16_t status = AESCCMLPF3_setupSegmentedOperation(object, key, totalAADLength, @@ -1423,6 +1538,14 @@ int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *o DebugP_assert(operation); AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCCMLPF3HSM_addAAD(handle, operation); + } +#endif + int_fast16_t status; object->operation = (AESCCM_OperationUnion *)operation; @@ -1644,7 +1767,7 @@ int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation DebugP_assert(operation); AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); - int_fast16_t status; + int_fast16_t status = AESCCM_STATUS_ERROR; /* This operation can be called after setupXXXX, addAAD, or addData */ DebugP_assert((object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) || @@ -1663,28 +1786,56 @@ int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation } #endif - /* The input length must be a non-zero multiple of an AES block size - * unless you are dealing with the last chunk of payload data - */ - if ((operation->inputLength == 0U) || ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U) && - (operation->inputLength != object->totalCBCMACLengthRemaining))) +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) { - return AESCCM_STATUS_ERROR; - } + /* The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of payload data + */ + if ((operation->inputLength == 0U) || ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U) && + (operation->inputLength != object->totalDataLengthRemaining))) + { + return AESCCM_STATUS_ERROR; + } - /* The total input length must not exceed the lengths specified in - * AESCCM_setLengths() or setupXXXX(). - */ - if (operation->inputLength > object->totalCBCMACLengthRemaining) + /* The total input length must not exceed the lengths specified in + * AESCCM_setLengths() or setupXXXX(). + */ + if (operation->inputLength > object->totalDataLengthRemaining) + { + return AESCCM_STATUS_ERROR; + } + } + else +#endif { - return AESCCM_STATUS_ERROR; + /* The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of payload data + */ + if ((operation->inputLength == 0U) || ((AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U) && + (operation->inputLength != object->totalCBCMACLengthRemaining))) + { + return AESCCM_STATUS_ERROR; + } + + /* The total input length must not exceed the lengths specified in + * AESCCM_setLengths() or setupXXXX(). + */ + if (operation->inputLength > object->totalCBCMACLengthRemaining) + { + return AESCCM_STATUS_ERROR; + } } /* The AAD input length specified so far must match the total length * specified in the setLengths() or setupXXXX() calls. * All AAD input must be processed at this point. */ - if (object->aadBytesProcessed != object->totalAADLength) + if (object->aadBytesProcessed != object->totalAADLength +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + && (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) +#endif + ) { return AESCCM_STATUS_ERROR; } @@ -1704,12 +1855,31 @@ int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation operationType = AESCCM_OP_TYPE_DATA_DECRYPT; } - status = AESCCMLPF3_addData(handle, - operationType, - (AESCCM_OperationUnion *)operation, - operation->input, - operation->output, - operation->inputLength); + if (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) + { + status = AESCCMLPF3_addData(handle, + operationType, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCCMLPF3HSM_addData(handle, + operationType, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + return status; + } +#endif + else + { + status = AESCCM_STATUS_ERROR; + } if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (operation->inputLength < AESCCMLPF3_DMA_SIZE_THRESHOLD)) @@ -1732,6 +1902,14 @@ int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinali DebugP_assert(operation); AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCCMLPF3HSM_finalizeEncrypt(handle, operation); + } +#endif + int_fast16_t status; status = AESCCMLPF3_performFinalizeChecks(object, operation); @@ -1794,6 +1972,14 @@ int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinali DebugP_assert(operation); AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCCMLPF3HSM_finalizeDecrypt(handle, operation); + } +#endif + int_fast16_t status; status = AESCCMLPF3_performFinalizeChecks(object, operation); @@ -1919,7 +2105,11 @@ int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) * Do not execute the callback as it would have been executed already * when the operation completed. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (((object->common.key.encoding & CRYPTOKEY_HSM) == 0) && (!object->common.operationInProgress)) +#else if (!object->common.operationInProgress) +#endif { HwiP_restore(interruptKey); } @@ -1932,6 +2122,21 @@ int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) */ AESCommonLPF3_cancelOperation(&object->common, true); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Since the HSM cannot cancel an in-progress token, we must wait for the result to allow for + * subsequent token submissions to succeed. + */ + (void)HSMLPF3_cancelOperation(); + + object->segmentedOperationInProgress = false; + + int_fast16_t status = AESCCMLPF3HSM_freeTempAssetID(handle); + if (status != AESCCM_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } +#endif + /* Operation pointer could be NULL if a segmented operation was setup * but neither AESCCM_addData or AESCCM_finalize was called. */ @@ -1942,5 +2147,909 @@ int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) } } + (void)memset(object->output, 0, object->totalDataLength); + + object->aad = NULL; + object->input = NULL; + object->output = NULL; + object->nonce = NULL; + object->mac = NULL; + object->operation = NULL; + + object->inputLength = 0; + object->totalCBCMACLengthRemaining = 0; + object->totalCTRLengthRemaining = 0; + object->totalAADLength = 0; + object->totalDataLength = 0; + object->aadBytesProcessed = 0; + + object->macLength = 0; + object->nonceLength = 0; + + return AESCCM_STATUS_SUCCESS; +} + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/* + * ======== AESCCMLPF3HSM_setMac ======== + */ +int_fast16_t AESCCMLPF3HSM_setMac(AESCCM_Handle handle, const uint8_t *mac, size_t macLength) +{ + DebugP_assert(handle); + DebugP_assert(nonce); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* This function cannot be called after addXXX() or finalizeXXX() */ + DebugP_assert((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT)); + + /* Don't continue the segmented operation if there + * was an error during setup. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + object->mac = (uint8_t *)mac; + object->macLength = (uint8_t)macLength; + return AESCCM_STATUS_SUCCESS; } + +/* + * ======== AESCCMLPF3HSM_createAssetPostProcessing ======== + */ +static inline void AESCCMLPF3HSM_createAssetPostProcessing(uintptr_t arg0) +{ + AESCCM_Handle handle = (AESCCM_Handle)arg0; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status = AESCCM_STATUS_ERROR; + int8_t tokenResult = HSMLPF3_getResultCode() & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->tempAssetID = HSMLPF3_getResultAssetID(); + status = AESCCM_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== AESCCMLPF3HSM_createTempAssetID ======== + */ +static int_fast16_t AESCCMLPF3HSM_createTempAssetID(AESCCM_Handle handle, AESCCM_Mode direction) +{ + int_fast16_t status = AESCCM_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + uint64_t assetPolicy = 0U; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Lower 16-bit */ + assetPolicy |= EIP130_ASSET_POLICY_MODIFIABLE; + assetPolicy |= EIP130_ASSET_POLICY_SOURCESECURE; + assetPolicy |= EIP130_ASSET_POLICY_NOTCROSSDOMAIN; + assetPolicy |= EIP130_ASSET_POLICY_PRIVATEDATA; + assetPolicy |= EIP130_ASSET_POLICY_TEMPORARY; + assetPolicy |= EIP130_ASSET_POLICY_SYMCRYPTO; + + /* Upper 16-bit */ + assetPolicy |= EIP130_ASSET_POLICY_SCUICIPHERAUTH; + if (direction == AESCCM_MODE_DECRYPT) + { + assetPolicy |= EIP130_ASSET_POLICY_SCDIRDECVRFY; + } + else + { + assetPolicy |= EIP130_ASSET_POLICY_SCDIRENCGEN; + } + assetPolicy |= EIP130_ASSET_POLICY_SCACAES; + + HSMLPF3_constructCreateAssetToken(assetPolicy, KEY_TEMP_ASSET_SIZE); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCCMLPF3HSM_createAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + return status; +} + +/* + * ======== AESCCMLPF3HSM_oneStepPostProcessing ======== + */ +static inline void AESCCMLPF3HSM_oneStepPostProcessing(uintptr_t arg0) +{ + AESCCM_Handle handle = (AESCCM_Handle)arg0; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + AESCCM_OneStepOperation *oneStepOperation = (AESCCM_OneStepOperation *)object->operation; + int_fast16_t status = AESCCM_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + /* The HSM IP will throw an error when operation->macLength is zero despite it producing a correct + * ciphertext/plaintext for both encrypt/decrypt operations and will compute a mac anyways. + */ + if ((tokenResult == EIP130TOKEN_RESULT_INVALID_LENGTH) && (oneStepOperation->macLength == 0U)) + { + tokenResult = EIP130TOKEN_RESULT_SUCCESS; + } + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + if (object->operationType == AESCCM_OP_TYPE_ONESTEP_ENCRYPT) + { + HSMLPF3_getAESEncryptTag((void *)&oneStepOperation->mac[0]); + } + + status = AESCCM_STATUS_SUCCESS; + } + else if ((object->operationType == AESCCM_OP_TYPE_ONESTEP_DECRYPT) || + (tokenResult == EIP130TOKEN_RESULT_VERIFY_ERROR)) + { + status = AESCCM_STATUS_MAC_INVALID; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCCLPF3HSM_processOneStepHSM ======== + */ +static inline int_fast16_t AESCCMLPF3HSM_processOneStepOperation(AESCCM_Handle handle) +{ + int_fast16_t status = AESCCM_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_constructAESCCMOneStepPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCCMLPF3HSM_oneStepPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_oneStepOperation ======== + */ +static int_fast16_t AESCCMLPF3HSM_oneStepOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->key); + /* Internally generated nonces aren't supported for now */ + DebugP_assert(!operation->nonceInternallyGenerated); + DebugP_assert(operation->nonce && (operation->nonceLength >= 7U) && (operation->nonceLength <= 13U)); + DebugP_assert((operation->aad && (operation->aadLength > 0U)) || + (operation->input && (operation->inputLength > 0U))); + DebugP_assert(operation->mac && (operation->macLength <= 16U)); + /* Implementation only supports aadLength to 65,279 bytes */ + DebugP_assert(operation->aadLength <= B1_AAD_LENGTH_SMALL_LIMIT); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + /* The nonce length must be 7 to 13 bytes long */ + if ((operation->nonceLength < (uint8_t)7U) || (operation->nonceLength > (uint8_t)13U)) + { + return AESCCM_STATUS_ERROR; + } + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } + + /* The combined length of AAD and payload data must be non-zero. */ + if ((operation->aadLength + operation->inputLength) == 0U) + { + return AESCCM_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCCM_STATUS_ERROR; + } + + object->common.returnStatus = AESCCM_STATUS_SUCCESS; + + object->operation = (AESCCM_OperationUnion *)operation; + object->operationType = operationType; + + object->common.key = *(operation->key); + object->input = operation->input; + object->output = operation->output; + object->mac = operation->mac; + object->aad = operation->aad; + object->nonce = operation->nonce; + + object->inputLength = operation->inputLength; + object->totalDataLength = operation->inputLength; + object->macLength = operation->macLength; + object->aadLength = object->totalAADLength; + object->totalAADLength = operation->aadLength; + object->nonceLength = operation->nonceLength; + + object->totalDataLengthRemaining = object->totalDataLength; + object->totalAADLengthRemaining = object->totalAADLength; + + object->tempAssetID = 0U; + + /* Process all one-step operations with data length less than the DMA size + * threshold as a polling mode operation. + */ + return AESCCMLPF3HSM_processOneStepOperation(handle); +} + +/* + * ======== AESCCMLPF3HSM_setupSegmentedOperation ======== + */ +static int_fast16_t AESCCMLPF3HSM_setupSegmentedOperation(AESCCMLPF3_Object *object, + const CryptoKey *key, + size_t totalAADLength, + size_t totalDataLength, + size_t macLength) +{ + DebugP_assert(key); + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCCM_STATUS_ERROR; + } + + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->common.returnStatus = AES_STATUS_SUCCESS; + + object->segmentedOperationInProgress = true; + + /* If the user doesn't provide the total lengths in the setupXXXX() + * calls, they must provide the lengths in setLengths(). + */ + object->totalAADLength = totalAADLength; + object->totalDataLength = totalDataLength; + object->macLength = (uint8_t)macLength; + + object->totalCTRLengthRemaining = totalDataLength; + object->totalCBCMACLengthRemaining = totalDataLength; + object->aadBytesProcessed = 0U; + object->bufferedAADLength = (uint8_t)0U; + + object->totalDataLengthRemaining = totalDataLength; + object->totalAADLengthRemaining = totalAADLength; + object->inputLength = 0U; + object->aadLength = 0U; + + /* Initialize MAC pointer to NULL to avoid premature processing of the + * MAC in the ISR. + */ + object->mac = NULL; + + /* Initialize operation pointer to NULL in case AESCCM_cancelOperation + * is called after AESCCM_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + + return AESCCM_STATUS_SUCCESS; +} + +/* + * ======== AESCCMLPF3HSM_setupEncrypt ======== + */ +int_fast16_t AESCCMLPF3HSM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + DebugP_assert(handle); + int_fast16_t status = AESCCM_STATUS_ERROR; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + status = AESCCMLPF3HSM_setupSegmentedOperation(object, key, totalAADLength, totalPlaintextLength, macLength); + if (status == AESCCM_STATUS_SUCCESS) + { + object->operationType = AESCCM_OPERATION_TYPE_ENCRYPT; + status = AESCCMLPF3HSM_createTempAssetID(handle, AESCCM_MODE_ENCRYPT); + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_setupDecrypt ======== + */ +int_fast16_t AESCCMLPF3HSM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + DebugP_assert(handle); + int_fast16_t status = AESCCM_STATUS_ERROR; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + + status = AESCCMLPF3HSM_setupSegmentedOperation(object, key, totalAADLength, totalPlaintextLength, macLength); + if (status == AESCCM_STATUS_SUCCESS) + { + object->operationType = AESCCM_OPERATION_TYPE_DECRYPT; + status = AESCCMLPF3HSM_createTempAssetID(handle, AESCCM_MODE_DECRYPT); + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_SegmentedPostProcessing ======== + */ +static inline void AESCCMLPF3HSM_SegmentedPostProcessing(uintptr_t arg0) +{ + AESCCM_Handle handle = (AESCCM_Handle)arg0; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status = AESCCM_STATUS_ERROR; + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + /* The HSM IP will throw an error when operation->macLength is zero despite it producing a correct + * ciphertext/plaintext for both encrypt/decrypt operations and will compute a mac anyways. + */ + if ((tokenResult == EIP130TOKEN_RESULT_INVALID_LENGTH) && (object->macLength == 0U)) + { + tokenResult = EIP130TOKEN_RESULT_SUCCESS; + } + + if ((object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT)) + { + direction = AESCCM_MODE_DECRYPT; + } + + if ((object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) || (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT)) + { + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->totalAADLengthRemaining -= object->aadLength; + object->aadLength = 0U; + + status = AESCCM_STATUS_SUCCESS; + } + } + else + { + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->totalAADLengthRemaining -= object->aadLength; + object->totalDataLengthRemaining -= object->inputLength; + + if (direction == AESCCM_MODE_ENCRYPT) + { + HSMLPF3_getAESEncryptTag((uint8_t *)&object->intermediateTag[0]); + + if ((object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT) && + ((object->totalDataLengthRemaining == 0U) && (object->totalAADLengthRemaining == 0U))) + { + (void)memcpy((void *)&object->mac[0], (void *)&object->intermediateTag[0], object->macLength); + } + } + + status = AESCCM_STATUS_SUCCESS; + } + else if ((tokenResult == EIP130TOKEN_RESULT_VERIFY_ERROR) && + (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT)) + { + object->totalAADLengthRemaining -= object->aadLength; + object->totalDataLengthRemaining -= object->inputLength; + + status = AESCCM_STATUS_MAC_INVALID; + } + } + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + + if ((object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT)) + { + status = AESCCMLPF3HSM_freeTempAssetID(handle); + + object->segmentedOperationInProgress = false; + } + + object->common.returnStatus = status; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, object->operation, object->operationType); + } +} + +/* + * ======== AESCCMLPF3HSM_addAAD ======== + */ +int_fast16_t AESCCMLPF3HSM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status = AESCCM_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + + object->operation = (AESCCM_OperationUnion *)operation; + + if (object->totalAADLengthRemaining == object->totalAADLength) + { + object->aad = operation->aad; + } + + /* Don't continue the segmented operation if there + * was an error or a cancellation. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* This operation can be called after setup or after addAAD again. */ + DebugP_assert((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT)); + + uint8_t aadBytesProcessed = object->totalAADLength - object->totalAADLengthRemaining; + size_t calcAADLen = aadBytesProcessed + operation->aadLength; + + /* The total AAD input length must not exceed the total length specified + * in AESCCM_setLengths() or the setupXXXX() call. + */ + if (calcAADLen > object->totalAADLength) + { + status = AESCCM_STATUS_ERROR; + } + + if (status == AESCCM_STATUS_ERROR) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + + return status; + } + + AESCCM_OperationType operationType = AESCCM_OP_TYPE_AAD_ENCRYPT; + + if ((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) || + (object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT)) + { + operationType = AESCCM_OP_TYPE_AAD_DECRYPT; + } + + object->operationType = operationType; + + uint8_t aadBytesToProcess = operation->aadLength; + uint8_t inputRemainder = aadBytesToProcess % AES_BLOCK_SIZE; + + if (inputRemainder > 0U) + { + aadBytesToProcess -= inputRemainder; + } + + if (aadBytesProcessed + aadBytesToProcess == object->totalAADLength) + { + aadBytesToProcess -= AES_BLOCK_SIZE; + } + + object->aadLength = aadBytesToProcess; + object->inputLength = 0U; + + if (aadBytesToProcess > 0U) + { + HSMLPF3_constructAESCCMSegmentedAADPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCCMLPF3HSM_SegmentedPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + object->common.returnStatus = status; + } + else + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + + object->common.returnStatus = status; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCCM_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_addData ======== + */ +static int_fast16_t AESCCMLPF3HSM_addData(AESCCM_Handle handle, + AESCCM_OperationType operationType, + AESCCM_OperationUnion *operation, + const uint8_t *input, + uint8_t *output, + size_t inputLength) +{ + int_fast16_t status = AESCCM_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + AESCCM_SegmentedDataOperation *segmentedOperation = (AESCCM_SegmentedDataOperation *)operation; + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + object->operationType = operationType; + object->operation = operation; + + if (object->totalDataLengthRemaining == object->totalDataLength) + { + object->input = segmentedOperation->input; + object->output = segmentedOperation->output; + } + + object->aadLength = object->totalAADLengthRemaining; + object->inputLength = inputLength; + + HSMLPF3_constructAESCCMSegmentedDataPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCCMLPF3HSM_SegmentedPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + object->common.returnStatus = status; + + return status; +} + +/* + * ======== AESCCMLPF3HSM_freeAssetPostProcessing ======== + */ +static inline void AESCCMLPF3HSM_freeAssetPostProcessing(uintptr_t arg0) +{ + AESCCM_Handle handle = (AESCCM_Handle)arg0; + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status = AESCCM_STATUS_ERROR; + int8_t tokenResult = HSMLPF3_getResultCode() & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->tempAssetID = 0; + status = AESCCM_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + if ((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } +} + +/* + * ======== AESCCMLPF3HSM_freeTempAssetID ======== + */ +static int_fast16_t AESCCMLPF3HSM_freeTempAssetID(AESCCM_Handle handle) +{ + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status = AESCCM_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + + if (object->tempAssetID != 0) + { + if ((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) + { + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + HSMLPF3_constructDeleteAssetToken(object->tempAssetID); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCCMLPF3HSM_freeAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + } + + if (((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) && + (hsmRetval != HSMLPF3_STATUS_SUCCESS)) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_finalizeEncrypt ======== + */ +int_fast16_t AESCCMLPF3HSM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + status = AESCCMLPF3HSM_performFinalizeChecks(object, operation); + + if (status != AESCCM_STATUS_SUCCESS) + { + return status; + } + + if (object->totalDataLengthRemaining == object->totalDataLength) + { + object->input = operation->input; + object->output = operation->output; + } + + object->mac = operation->mac; + object->macLength = operation->macLength; + + if ((operation->inputLength > 0U) || (object->totalAADLengthRemaining > 0)) + { + status = AESCCMLPF3HSM_addData(handle, + AESCCM_OP_TYPE_FINALIZE_ENCRYPT, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + } + else + { + (void)memcpy(operation->mac, (uint32_t *)&object->intermediateTag[0], operation->macLength); + + status = AESCCMLPF3HSM_freeTempAssetID(handle); + + object->segmentedOperationInProgress = false; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_ENCRYPT); + } + } + return status; +} + +/* + * ======== AESCCMLPF3HSM_finalizeDecrypt ======== + */ +int_fast16_t AESCCMLPF3HSM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMLPF3_Object *object = AESCCMLPF3_getObject(handle); + int_fast16_t status; + + status = AESCCMLPF3HSM_performFinalizeChecks(object, operation); + + if (status != AESCCM_STATUS_SUCCESS) + { + return status; + } + + if (object->totalDataLengthRemaining == object->totalDataLength) + { + object->input = operation->input; + object->output = operation->output; + } + + object->mac = operation->mac; + object->macLength = operation->macLength; + + if ((operation->inputLength > 0U) || (object->totalAADLengthRemaining > 0U)) + { + status = AESCCMLPF3HSM_addData(handle, + AESCCM_OP_TYPE_FINALIZE_DECRYPT, + (AESCCM_OperationUnion *)operation, + operation->input, + operation->output, + operation->inputLength); + } + else + { + status = AESCCMLPF3HSM_freeTempAssetID(handle); + + object->segmentedOperationInProgress = false; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_DECRYPT); + } + } + + return status; +} + +/* + * ======== AESCCMLPF3HSM_performFinalizeChecks ======== + */ +static int_fast16_t AESCCMLPF3HSM_performFinalizeChecks(const AESCCMLPF3_Object *object, + const AESCCM_SegmentedFinalizeOperation *operation) +{ + /* This operation can be called after setupXXXX, addAAD, or addData */ + DebugP_assert((object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) || + (object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT)); + + /* Don't continue the segmented operation if there + * was an error or a cancellation. + */ + if (object->common.returnStatus != AESCCM_STATUS_SUCCESS) + { + return object->common.returnStatus; + } + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCCM_STATUS_ERROR; + } + + /* Additional payload data can be passed in finalize */ + if (operation->inputLength != object->totalDataLengthRemaining) + { + return AESCCM_STATUS_ERROR; + } + + return AESCCM_STATUS_SUCCESS; +} + +#endif \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h index fb7491ea..a53393cc 100644 --- a/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h +++ b/simplelink_lpf3/source/ti/drivers/aesccm/AESCCMLPF3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -40,18 +40,26 @@ * All symbols used in the implementation for identifiers and in the comments including * but not limited to B0, B1 and S0 are all adopted from this NIST 800-38c. * - * # Hardware Accelerator # - * The Low Power F3 family of devices has a dedicated AES hardware that can perform - * AES encryption operations with 128-bit keys. Only one operation - * can be carried out on the accelerator at a time. Mutual exclusion is - * implemented at the driver level and coordinated between all drivers relying on - * the accelerator. It is transparent to the application and only noted to ensure - * sensible access timeouts are set. + * # Hardware Accelerator # + * The Low Power F3 family of devices has dedicated hardware accelerators. + * CC23XX devices have one dedicated accelerator whereas CC27XX devices have two + * (Primary and Secondary). Combined they can perform AES encryption operations with + * 128-bit, 192-bit and 256-bit keys. Only one operation can be carried out on the + * accelerator at a time. Mutual exclusion is implemented at the driver level and + * coordinated between all drivers relying on the accelerator. It is transparent to + * the application and only noted to ensure sensible access timeouts are set. * * # Implementation Limitations * - Only plaintext CryptoKeys are supported by this implementation. * - Maximum AAD length is limited to 65279-bytes. * + * The following limitations apply to the AESCCMLPF3 Driver for CC27xx device family only: + * - The CryptoKey input must have the correct encoding, @ref CryptoKey.h. + * - The application can only use one handle per driver. + * Concurrent dynamic instances will be supported in the future. + * - CCM driver only supports polling return behaviour. + * Blocking and callback return behaviours will be supported in the future. + * * # Runtime Parameter Validation # * The driver implementation does not perform runtime checks for most input parameters. * Only values that are likely to have a stochastic element to them are checked (such @@ -116,8 +124,50 @@ typedef struct uint8_t bufferedAADLength; uint8_t macLength; uint8_t nonceLength; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + size_t aadLength; + volatile size_t totalDataLengthRemaining; + volatile size_t totalAADLengthRemaining; + /*! + * @brief The staus of the HSM Boot up process + * if HSMLPF3_STATUS_SUCCESS, the HSM booted properly. + * if HSMLPF3_STATUS_ERROR, the HSM did not boot properly. + */ + int_fast16_t hsmStatus; + uint32_t tempAssetID; + /* To indicate whether a segmented operation is in progress + */ + bool segmentedOperationInProgress; +#endif } AESCCMLPF3_Object; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/*! + * @brief Function to set the mac for an AES CCM segmented operation. + * This API needs to be called only when the subsequent #AESCCM_addData() operation is processing all of the + * remaining data in a single call. + * + * @note This API is only concerned with segmented decryption operations. + * + * @pre #AESCCM_setupDecrypt(), #AESCCM_setLengths(), or #AESCCM_addAAD() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] mac Pointer to the buffer containing the mac + * + * @param [in] macLength The length of the mac in bytes + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESCCM_addData() + */ +int_fast16_t AESCCMLPF3HSM_setMac(AESCCM_Handle handle, const uint8_t *mac, size_t macLength); +#endif + #ifdef __cplusplus } #endif diff --git a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c index a55543ca..0a95a2ec 100644 --- a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c +++ b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,12 @@ #include #include +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include + #include + #include +#endif + #include #include #include @@ -87,6 +93,24 @@ static int_fast16_t AESCMACLPF3_startOperation(AESCMAC_Handle handle); static inline int_fast16_t AESCMACLPF3_waitForResult(AESCMAC_Handle handle); static inline void AESCMACLPF3_xorBlock(uint32_t *block1_dst, const uint32_t *block2); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +static int_fast16_t AESCMACLPF3HSM_oneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + const CryptoKey *key, + AESCMAC_OperationType operationType); +static int_fast16_t AESCMACLPF3HSM_SegmentedOperation(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +static int_fast16_t AESCMACLPF3HSM_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +static int_fast16_t AESCMACLPF3HSM_processOneStepAndFinalizeOperation(AESCMAC_Handle handle); +static int_fast16_t AESCMACLPF3HSM_processSegmentedOperation(AESCMAC_Handle handle); + +static int_fast16_t AESCMACLPF3HSM_createAndLoadKeyAssetID(AESCMAC_Handle handle); +static int_fast16_t AESCMACLPF3HSM_CreateTempAssetID(AESCMAC_Handle handle); +static int_fast16_t AESCMACLPF3HSM_freeAssets(AESCMAC_Handle handle); +static int_fast16_t AESCMACLPF3HSM_freeAssetID(AESCMAC_Handle handle, uint32_t AssetID); +#endif + /* * ======== AESCMACLPF3_getObject ======== */ @@ -151,6 +175,9 @@ static void AESCMACLPF3_hwiFxn(uintptr_t arg0) */ void AESCMAC_init(void) { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + HSMLPF3_constructRTOSObjects(); +#endif AESCommonLPF3_init(); } @@ -165,6 +192,24 @@ AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *p AESCMAC_Handle handle = config; AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Initialize and boot HSM */ + if (HSMLPF3_init() != HSMLPF3_STATUS_SUCCESS) + { + /* Upon HSM Boot failure, the AES-CCM Driver stores the failure status in the object + * This is done so that users of the AES-CCM Driver do not get a NULL handle and still can use + * the driver in LAES mode. + */ + object->hsmStatus = HSMLPF3_STATUS_ERROR; + } + else + { + object->hsmStatus = HSMLPF3_STATUS_SUCCESS; + } + + object->segmentedOperationInProgress = false; +#endif + /* If params are NULL, use defaults */ if (params == NULL) { @@ -208,13 +253,22 @@ static void AESCMACLPF3_getResult(AESCMACLPF3_Object *object) if (object->common.returnStatus == AESCMAC_STATUS_SUCCESS) { - /* If One-step or Finalize operation, process the final input block */ - if (opcode != AESCMAC_OP_CODE_SEGMENTED) + if (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) { - AESWriteBUF32(&object->finalInputBlock[0]); - } + /* If One-step or Finalize operation, process the final input block */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + AESWriteBUF32(&object->finalInputBlock[0]); + } - AESCMACLPF3_readTag((uint32_t *)&object->intermediateTag[0]); + AESCMACLPF3_readTag((uint32_t *)&object->intermediateTag[0]); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + /* Do nothing as HSM does not rely on AES engine */ + } +#endif /* If One-step or Finalize operation, verify or copy the MAC */ if (opcode != AESCMAC_OP_CODE_SEGMENTED) @@ -536,7 +590,14 @@ static int_fast16_t AESCMACLPF3_oneStepOperation(AESCMAC_Handle handle, (uint8_t)0U, sizeof(object->intermediateTag)); - status = AESCMACLPF3_startOperation(handle); + if (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) + { + status = AESCMACLPF3_startOperation(handle); + } + else + { + status = AESCMAC_STATUS_ERROR; + } if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) { @@ -605,7 +666,23 @@ static inline int_fast16_t AESCMACLPF3_waitForResult(AESCMAC_Handle handle) */ int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) { - return AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_SIGN); + int_fast16_t status; + + if (key->encoding == CryptoKey_PLAINTEXT || key->encoding == CryptoKey_KEYSTORE) + { + status = AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_SIGN); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCMACLPF3HSM_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_SIGN); + } +#endif + else + { + status = AESCMAC_STATUS_ERROR; + } + return status; } /* @@ -613,7 +690,23 @@ int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *opera */ int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) { - return AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_VERIFY); + int_fast16_t status; + + if (key->encoding == CryptoKey_PLAINTEXT || key->encoding == CryptoKey_KEYSTORE) + { + status = AESCMACLPF3_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_VERIFY); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCMACLPF3HSM_oneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_VERIFY); + } +#endif + else + { + status = AESCMAC_STATUS_ERROR; + } + return status; } /* @@ -623,12 +716,39 @@ static int_fast16_t AESCMACLPF3_setupSegmentedOperation(AESCMACLPF3_Object *obje { DebugP_assert(key); + int_fast16_t status = AESCMAC_STATUS_SUCCESS; + /* * Key material pointer and length are not asserted until adding or * finalizing data. */ + if (key->encoding == CryptoKey_PLAINTEXT) + { + /* When using the AES driver with the LAES engine */ + status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCMAC_STATUS_ERROR; + } + + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->common.returnStatus = AES_STATUS_SUCCESS; - int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + object->segmentedOperationInProgress = true; + } +#endif + else + { + status = AESCMAC_STATUS_ERROR; + } if (status == AESCMAC_STATUS_SUCCESS) { @@ -662,6 +782,17 @@ int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key) if (status == AESCMAC_STATUS_SUCCESS) { object->operationType = AESCMAC_OP_TYPE_SEGMENTED_SIGN; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus == AESCMAC_STATUS_ERROR) + { + return AESCMAC_STATUS_ERROR; + } + status = AESCMACLPF3HSM_createAndLoadKeyAssetID(handle); + } +#endif } return status; @@ -681,6 +812,17 @@ int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key) if (status == AESCMAC_STATUS_SUCCESS) { object->operationType = AESCMAC_OP_TYPE_SEGMENTED_VERIFY; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus == AESCMAC_STATUS_ERROR) + { + return AESCMAC_STATUS_ERROR; + } + status = AESCMACLPF3HSM_createAndLoadKeyAssetID(handle); + } +#endif } return status; @@ -695,7 +837,14 @@ int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation DebugP_assert(operation); AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); - int_fast16_t status; + int_fast16_t status = AESCMAC_STATUS_ERROR; + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCMACLPF3HSM_SegmentedOperation(handle, operation); + } +#endif /* Assert the segmented operation was setup */ DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || @@ -735,7 +884,14 @@ int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation } object->operation = operation; - status = AESCMACLPF3_startOperation(handle); + if (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) + { + status = AESCMACLPF3_startOperation(handle); + } + else + { + status = AESCMAC_STATUS_ERROR; + } if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) { @@ -822,7 +978,14 @@ int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operatio DebugP_assert(operation); AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); - int_fast16_t status; + int_fast16_t status = AESCMAC_STATUS_ERROR; + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCMACLPF3HSM_finalize(handle, operation); + } +#endif /* Assert the segmented operation was setup */ DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || @@ -881,7 +1044,14 @@ int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operatio } object->operation = operation; - status = AESCMACLPF3_startOperation(handle); + if (object->common.key.encoding == CryptoKey_PLAINTEXT || object->common.key.encoding == CryptoKey_KEYSTORE) + { + status = AESCMACLPF3_startOperation(handle); + } + else + { + status = AESCMAC_STATUS_ERROR; + } if ((status != AESCMAC_STATUS_SUCCESS) && (object->common.cryptoResourceLocked)) { @@ -901,6 +1071,14 @@ void AESCMAC_close(AESCMAC_Handle handle) AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM && + AESCMACLPF3HSM_freeAssets(handle) != AESCMAC_STATUS_SUCCESS) + { + /* empty */ + } +#endif + AESCommonLPF3_close(&object->common); } @@ -915,12 +1093,19 @@ int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) uintptr_t interruptKey = HwiP_disable(); - /* - * Return success if there is no active operation to cancel. + /* Return success if there is no active operation to cancel. * Do not execute the callback as it would have been executed already * when the operation completed. */ + + /* If the operation is in _HSM mode, then the driver does not rely on 'object->common' metadata + * and instead relies on HSM metadata. The check below insures that. + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (((object->common.key.encoding & CRYPTOKEY_HSM) == 0U) && (!object->common.operationInProgress)) +#else if (!object->common.operationInProgress) +#endif { HwiP_restore(interruptKey); return AESCMAC_STATUS_SUCCESS; @@ -928,14 +1113,27 @@ int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) HwiP_restore(interruptKey); - /* - * Cancel DMA for input channel A only, clear operation in-progress, +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Since the HSM cannot cancel an in-progress token, we must wait for the result to allow for + * subsequent token submissions to succeed. + */ + (void)HSMLPF3_cancelOperation(); + + object->segmentedOperationInProgress = false; + + if ((object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) && + (AESCMACLPF3HSM_freeAssets(handle) != AESCMAC_STATUS_SUCCESS)) + { + return AESCMAC_STATUS_ERROR; + } +#endif + + /* Cancel DMA for input channel A only, clear operation in-progress, * and release crypto resource if locked. */ AESCommonLPF3_cancelOperation(&object->common, false); - /* - * Operation pointer could be NULL if a segmented operation was setup + /* Operation pointer could be NULL if a segmented operation was setup * but neither AESCMAC_addData or AESCMAC_finalize was called. */ if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) @@ -946,3 +1144,680 @@ int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) return AESCMAC_STATUS_SUCCESS; } + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/* + * ======== AESCMACLPF3HSM_oneStepOperation ======== + */ +static int_fast16_t AESCMACLPF3HSM_oneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + const CryptoKey *key, + AESCMAC_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(key); + /* No need to assert operationType since we control it within the driver */ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_SUCCESS; + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus == HSMLPF3_STATUS_ERROR) + { + return HSMLPF3_STATUS_ERROR; + } + + /* CBC-MAC is not permitted for zero length messages */ + if ((object->operationalMode == AESCMAC_OPMODE_CBCMAC) && (operation->inputLength == 0U)) + { + return AESCMAC_STATUS_ERROR; + } + + if (operation->macLength > sizeof(object->intermediateTag)) + { + return AESCMAC_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCMAC_STATUS_ERROR; + } + + object->operation = operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESCMAC_STATUS_SUCCESS; + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* Zero the intermediate tag because it will be used as the IV */ + CryptoUtils_memset((void *)&object->intermediateTag[0], + sizeof(object->intermediateTag), + (uint8_t)0U, + sizeof(object->intermediateTag)); + + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCMACLPF3HSM_createAndLoadKeyAssetID(handle); + + if (status == AESCMAC_STATUS_SUCCESS) + { + status = AESCMACLPF3HSM_processOneStepAndFinalizeOperation(handle); + } + } + else + { + status = AESCMAC_STATUS_ERROR; + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_finalize ======== + */ +static int_fast16_t AESCMACLPF3HSM_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + + if (object->hsmStatus == HSMLPF3_STATUS_ERROR) + { + return HSMLPF3_STATUS_ERROR; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || + (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + if (operation->inputLength == 0U) + { + /* + * Finalizing an operation without providing data to process is not + * supported. Return an error. + */ + return AESCMAC_STATUS_ERROR; + } + + object->operation = operation; + + if (object->operationType & AESCMAC_OP_FLAG_SIGN) + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_SIGN; + } + else + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_VERIFY; + } + + status = AESCMACLPF3HSM_processOneStepAndFinalizeOperation(handle); + + return status; +} + +/* + * ======== AESCMACLPF3HSM_CreateKeyAssetPostProcessing ======== + */ +static inline void AESCMACLPF3HSM_CreateKeyAssetPostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->keyAssetID = HSMLPF3_getResultAssetID(); + status = AESCMAC_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== AESCMACLPF3HSM_createKeyAssetID ======== + */ +static int_fast16_t AESCMACLPF3HSM_createKeyAsset(AESCMAC_Handle handle) +{ + int_fast16_t status = AESCMAC_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + uint64_t assetPolicy = 0U; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Operation (Lower 16-bits + general Operation) + Direction + Mode */ + assetPolicy = EIP130_ASSET_POLICY_SYM_BASE | EIP130_ASSET_POLICY_SCUIMACCIPHER | EIP130_ASSET_POLICY_SCACAES | + EIP130_ASSET_POLICY_SCDIRENCGEN; + + if (object->operationalMode == AESCMAC_OPMODE_CMAC) + { + assetPolicy |= EIP130_ASSET_POLICY_SCMCMCMAC; + } + else + { + assetPolicy |= EIP130_ASSET_POLICY_SCMCMCBCMAC; + } + + HSMLPF3_constructCreateAssetToken(assetPolicy, (uint32_t)object->common.key.u.plaintext.keyLength); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCMACLPF3HSM_CreateKeyAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_LoadKeyAssetPostProcessing ======== + */ +static inline void AESCMACLPF3HSM_LoadKeyAssetPostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESCMAC_STATUS_SUCCESS; + } + + object->hsmStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== AESCMACLPF3HSM_createKeyAssetID ======== + */ +static int_fast16_t AESCMACLPF3HSM_LoadKeyAsset(AESCMAC_Handle handle) +{ + int_fast16_t status = AESCMAC_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_constructLoadPlaintextAssetToken(object->common.key.u.plaintext.keyMaterial, + object->common.key.u.plaintext.keyLength, + object->keyAssetID); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCMACLPF3HSM_LoadKeyAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_createAndLoadKeyAssetID ======== + */ +static int_fast16_t AESCMACLPF3HSM_createAndLoadKeyAssetID(AESCMAC_Handle handle) +{ + int_fast16_t status = AESCMAC_STATUS_ERROR; + + status = AESCMACLPF3HSM_createKeyAsset(handle); + if (status == AESCMAC_STATUS_SUCCESS) + { + status = AESCMACLPF3HSM_LoadKeyAsset(handle); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_CreateTempAssetPostProcessing ======== + */ +static inline void AESCMACLPF3HSM_CreateTempAssetPostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + object->tempAssetID = HSMLPF3_getResultAssetID(); + status = AESCMAC_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +static int_fast16_t AESCMACLPF3HSM_CreateTempAssetID(AESCMAC_Handle handle) +{ + int_fast16_t status = AESCMAC_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + uint64_t assetPolicy = 0U; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Operation (Lower 16-bits + general Operation) + Direction + Mode */ + assetPolicy = EIP130_ASSET_POLICY_SYM_TEMP | EIP130_ASSET_POLICY_SCUIMACCIPHER | EIP130_ASSET_POLICY_SCACAES | + EIP130_ASSET_POLICY_SCDIRENCGEN; + + if (object->operationalMode == AESCMAC_OPMODE_CMAC) + { + assetPolicy |= EIP130_ASSET_POLICY_SCMCMCMAC; + } + else + { + assetPolicy |= EIP130_ASSET_POLICY_SCMCMCBCMAC; + } + + HSMLPF3_constructCreateAssetToken(assetPolicy, AES_BLOCK_SIZE); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCMACLPF3HSM_CreateTempAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_oneStepAndFinalizePostProcessing ======== + */ +static inline void AESCMACLPF3HSM_oneStepAndFinalizePostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + AESCMAC_Operation *operation = object->operation; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + HSMLPF3_getAESCMACSignMac((void *)&object->intermediateTag[0], operation->macLength); + + object->common.returnStatus = AESCMAC_STATUS_SUCCESS; + + AESCMACLPF3_getResult(object); + } + else + { + object->common.returnStatus = AESCMAC_STATUS_ERROR; + } + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + if (AESCMACLPF3HSM_freeAssets(handle) == AESCMAC_STATUS_ERROR) + { + object->common.returnStatus = AESCMAC_STATUS_ERROR; + } + + object->segmentedOperationInProgress = false; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCMACLPF3HSM_processOneStepAndFinalizeOperation ======== + */ +static int_fast16_t AESCMACLPF3HSM_processOneStepAndFinalizeOperation(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_constructAESCMACOneStepPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCMACLPF3HSM_oneStepAndFinalizePostProcessing, + (uintptr_t)handle); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_freeAssets ======== + */ +static int_fast16_t AESCMACLPF3HSM_freeAssets(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + + object->common.cryptoResourceLocked = true; + + if (object->keyAssetID != 0U) + { + status = AESCMACLPF3HSM_freeAssetID(handle, object->keyAssetID); + if (status != AESCMAC_STATUS_ERROR) + { + object->keyAssetID = 0U; + } + } + + if (object->tempAssetID != 0) + { + status = AESCMACLPF3HSM_freeAssetID(handle, object->tempAssetID); + if (status != AESCMAC_STATUS_ERROR) + { + object->tempAssetID = 0U; + } + } + + object->common.cryptoResourceLocked = false; + + return status; +} + +/* + * ======== AESCMACLPF3HSM_FreeAssetPostProcessing ======== + */ +static inline void AESCMACLPF3HSM_FreeAssetPostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int8_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESCMAC_STATUS_SUCCESS; + } + + if (status == AESCMAC_STATUS_ERROR) + { + object->common.returnStatus = status; + } + + if ((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + if (status == AESCMAC_STATUS_ERROR && object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCMACLPF3HSM_freeAssetID ======== + */ +static int_fast16_t AESCMACLPF3HSM_freeAssetID(AESCMAC_Handle handle, uint32_t AssetID) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + + if ((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) + { + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + HSMLPF3_constructDeleteAssetToken(AssetID); + + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, + AESCMACLPF3HSM_FreeAssetPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (((HSMLPF3_ReturnBehavior)object->common.returnBehavior == HSMLPF3_RETURN_BEHAVIOR_POLLING) && + (hsmRetval != HSMLPF3_STATUS_SUCCESS)) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +/* + * ======== AESCMACLPF3HSM_SegmentedOperation ======== + */ +static int_fast16_t AESCMACLPF3HSM_SegmentedOperation(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus == AESCMAC_STATUS_ERROR) + { + return AESCMAC_STATUS_ERROR; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || + (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + if ((operation->inputLength == 0U) || (AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(operation->inputLength) > 0U)) + { + return AESCMAC_STATUS_ERROR; + } + + object->operation = operation; + + status = AESCMACLPF3HSM_processSegmentedOperation(handle); + + return status; +} + +/* + * ======== AESCMACLPF3HSM_segmentedPostProcessing ======== + */ +static inline void AESCMACLPF3HSM_segmentedPostProcessing(uintptr_t arg0) +{ + AESCMAC_Handle handle = (AESCMAC_Handle)arg0; + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + + if (physicalResult == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESCMAC_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +static int_fast16_t AESCMACLPF3HSM_processSegmentedOperation(AESCMAC_Handle handle) +{ + AESCMACLPF3_Object *object = AESCMACLPF3_getObject(handle); + int_fast16_t status = AESCMAC_STATUS_SUCCESS; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + bool isInitWithDefault = true; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + if (object->tempAssetID == 0U) + { + HSMLPF3_releaseLock(); + status = AESCMACLPF3HSM_CreateTempAssetID(handle); + } + else + { + isInitWithDefault = false; + } + + HSMLPF3_constructAESCMACUpdatePhysicalToken(object, isInitWithDefault); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCMACLPF3HSM_segmentedPostProcessing, + (uintptr_t)handle); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} + +#endif \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h index 8dff31ac..500d98ec 100644 --- a/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h +++ b/simplelink_lpf3/source/ti/drivers/aescmac/AESCMACLPF3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,17 +34,25 @@ * * @brief AESCMAC (CMAC & CBC-MAC) driver implementation for the Low Power F3 family * - * # Hardware Accelerator # - * The Low Power F3 family of devices has a dedicated AES hardware that can perform - * AES encryption operations with 128-bit keys. Only one operation - * can be carried out on the accelerator at a time. Mutual exclusion is - * implemented at the driver level and coordinated between all drivers relying on - * the accelerator. It is transparent to the application and only noted to ensure - * sensible access timeouts are set. + * # Hardware Accelerator # + * The Low Power F3 family of devices has dedicated hardware accelerators. + * CC23XX devices have one dedicated accelerator whereas CC27XX devices have two + * (Primary and Secondary). Combined they can perform AES encryption operations with + * 128-bit, 192-bit and 256-bit keys. Only one operation can be carried out on the + * accelerator at a time. Mutual exclusion is implemented at the driver level and + * coordinated between all drivers relying on the accelerator. It is transparent to + * the application and only noted to ensure sensible access timeouts are set. * * # Implementation Limitations * - Only plaintext CryptoKeys are supported by this implementation. * + * The following limitations apply to the AESCCMLPF3 Driver for CC27xx device family only: + * - The CryptoKey input must have the correct encoding, @ref CryptoKey.h. + * - The application can only use one handle per driver. + * Concurrent dynamic instances will be supported in the future. + * - CCM driver only supports polling return behaviour. + * Blocking and callback return behaviours will be supported in the future. + * * # Runtime Parameter Validation # * The driver implementation does not perform runtime checks for most input parameters. * Only values that are likely to have a stochastic element to them are checked (such @@ -125,6 +133,20 @@ typedef struct AESCMAC_OperationType operationType; AESCMAC_OperationalMode operationalMode; bool threadSafe; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + size_t inputLength; + /*! + * @brief The staus of the HSM Boot up process + * if HSMLPF3_STATUS_SUCCESS, the HSM booted properly. + * if HSMLPF3_STATUS_ERROR, the HSM did not boot properly. + */ + int_fast16_t hsmStatus; + uint32_t tempAssetID; + uint32_t keyAssetID; + /* To indicate whether a segmented operation is in progress + */ + bool segmentedOperationInProgress; +#endif } AESCMACLPF3_Object; /*! @cond NODOC */ diff --git a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c index ea78f5c6..3ad6cd91 100644 --- a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c +++ b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -41,6 +41,16 @@ #include #include +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include + #include + #include + #include + #include + #include + #include +#endif + #include #include #include @@ -115,6 +125,17 @@ static int_fast16_t AESCTRLPF3_oneStepOperation(AESCTR_Handle handle, static int_fast16_t AESCTRLPF3_startOperation(AESCTR_Handle handle, bool isOneStepOrFinalOperation); static int_fast16_t AESCTRLPF3_waitForResult(AESCTR_Handle handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +static int_fast16_t AESCTRLPF3HSM_oneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType); +static int_fast16_t AESCTRLPF3HSM_processOneStepOperation(AESCTR_Handle handle); + +int_fast16_t AESCTRLPF3HSM_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); + +int_fast16_t AESCTRLPF3HSM_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); +#endif + /* * ======== AESCTRLPF3_getObject ======== */ @@ -196,6 +217,9 @@ static void AESCTRLPF3_hwiFxn(uintptr_t arg0) */ void AESCTR_init(void) { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + HSMLPF3_constructRTOSObjects(); +#endif AESCommonLPF3_init(); } @@ -210,6 +234,24 @@ AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *param AESCTR_Handle handle = config; AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Initialize and boot HSM */ + if (HSMLPF3_init() != HSMLPF3_STATUS_SUCCESS) + { + /* Upon HSM Boot failure, the AES-CCM Driver stores the failure status in the object + * This is done so that users of the AES-CCM Driver do not get a NULL handle and still can use + * the driver in LAES mode. + */ + object->hsmStatus = HSMLPF3_STATUS_ERROR; + } + else + { + object->hsmStatus = HSMLPF3_STATUS_SUCCESS; + } + + object->segmentedOperationInProgress = false; +#endif + /* If params are NULL, use defaults */ if (params == NULL) { @@ -248,7 +290,23 @@ void AESCTR_close(AESCTR_Handle handle) */ int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) { - return AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); + int_fast16_t status; + + if (operationStruct->key->encoding == CryptoKey_PLAINTEXT || operationStruct->key->encoding == CryptoKey_KEYSTORE) + { + status = AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operationStruct->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCTRLPF3HSM_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); + } +#endif + else + { + status = AESCTR_STATUS_ERROR; + } + return status; } /* @@ -256,7 +314,23 @@ int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation */ int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) { - return AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); + int_fast16_t status; + + if (operationStruct->key->encoding == CryptoKey_PLAINTEXT || operationStruct->key->encoding == CryptoKey_KEYSTORE) + { + status = AESCTRLPF3_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operationStruct->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESCTRLPF3HSM_oneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); + } +#endif + else + { + status = AESCTR_STATUS_ERROR; + } + return status; } /* @@ -614,6 +688,13 @@ int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *ope AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); int_fast16_t status; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCTRLPF3HSM_addData(handle, operation); + } +#endif + /* Assert the segmented operation was setup */ DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); @@ -684,6 +765,13 @@ int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *op AESCTR_OperationType operationType; int_fast16_t status; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (object->common.key.encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESCTRLPF3HSM_finalize(handle, operation); + } +#endif + /* Assert the segmented operation was setup */ DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); @@ -783,12 +871,39 @@ static int_fast16_t AESCTRLPF3_setupSegmentedOperation(AESCTRLPF3_Object *object { DebugP_assert(key); + int_fast16_t status = AESCTR_STATUS_SUCCESS; + /* * Key material pointer and length are not checked until adding or * finalizing data. */ + if (key->encoding == CryptoKey_PLAINTEXT) + { + /* When using the AES driver with the LAES engine */ + status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCTR_STATUS_ERROR; + } - int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->common.returnStatus = AES_STATUS_SUCCESS; + + object->segmentedOperationInProgress = true; + } +#endif + else + { + status = AESCTR_STATUS_ERROR; + } if (status == AESCTR_STATUS_SUCCESS) { @@ -813,6 +928,14 @@ int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, con AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); DebugP_assert(object); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if ((key->encoding == CryptoKey_PLAINTEXT_HSM) && (object->hsmStatus != HSMLPF3_STATUS_SUCCESS)) + { + return AESCTR_STATUS_ERROR; + } +#endif + int_fast16_t status = AESCTRLPF3_setupSegmentedOperation(object, key, initialCounter); if (status == AESCTR_STATUS_SUCCESS) @@ -832,6 +955,14 @@ int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, con AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); DebugP_assert(object); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if ((key->encoding == CryptoKey_PLAINTEXT_HSM) && (object->hsmStatus != HSMLPF3_STATUS_SUCCESS)) + { + return AESCTR_STATUS_ERROR; + } +#endif + int_fast16_t status = AESCTRLPF3_setupSegmentedOperation(object, key, initialCounter); if (status == AESCTR_STATUS_SUCCESS) @@ -858,7 +989,11 @@ int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) * Do not execute the callback as it would have been executed already * when the operation completed. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (((object->common.key.encoding & CRYPTOKEY_HSM) == 0) && (!object->common.operationInProgress)) +#else if (!object->common.operationInProgress) +#endif { HwiP_restore(interruptKey); return AESCTR_STATUS_SUCCESS; @@ -872,9 +1007,21 @@ int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) */ AESCommonLPF3_cancelOperation(&object->common, true); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if ((object->common.key.encoding & CRYPTOKEY_HSM)) + { + /* Since the HSM cannot cancel an in-progress token, we must wait for the result to allow for + * subsequent token submissions to succeed. + */ + (void)HSMLPF3_cancelOperation(); + + object->segmentedOperationInProgress = false; + } +#endif + /* * Operation pointer could be NULL if a segmented operation was setup - * but neither AESCCM_addData or AESCCM_finalize was called. + * but neither AESCTR_addData or AESCTR_finalize was called. */ if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) { @@ -884,3 +1031,247 @@ int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) return AESCTR_STATUS_SUCCESS; } + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/* + * ======== AESCTRLPF3HSM_oneStepOperation ======== + */ +static int_fast16_t AESCTRLPF3HSM_oneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->key); + /* No need to assert operationType since we control it within the driver */ + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCTR_STATUS_ERROR; + } + + /* Verify input length is non-zero */ + if (operation->inputLength == 0U) + { + return AESCTR_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESCTR_STATUS_ERROR; + } + + object->operation = (AESCTR_OperationUnion *)operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESCTR_STATUS_SUCCESS; + + /* Make internal copy of operational params */ + object->common.key = *(operation->key); + + object->input = operation->input; + object->output = operation->output; + object->inputLength = operation->inputLength; + + AESCTRLPF3_initCounter(object, &operation->initialCounter[0]); + + return AESCTRLPF3HSM_processOneStepOperation(handle); +} + +/* + * ======== AESCTRLPF3HSM_OneStepOperationPostProcessing ======== + */ +static inline void AESCTRLPF3HSM_OneStepOperationPostProcessing(uintptr_t arg0) +{ + AESCTR_Handle handle = (AESCTR_Handle)arg0; + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + int_fast16_t status = AESCTR_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int32_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESCTR_STATUS_SUCCESS; + + HSMLPF3_getAESIV((void *)&object->counter[0]); + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + if ((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE) || + (object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT)) + { + object->segmentedOperationInProgress = false; + } + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCTRLPF3HSM_processOneStepOperation ======== + */ +static int_fast16_t AESCTRLPF3HSM_processOneStepOperation(AESCTR_Handle handle) +{ + int_fast16_t status = AESCTR_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_constructAESCTROneStepPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESCTRLPF3HSM_OneStepOperationPostProcessing, + (uintptr_t)handle); + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + return status; +} + +int_fast16_t AESCTRLPF3HSM_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCTR_STATUS_ERROR; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESCTR_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || ((operation->inputLength & AES_NON_BLOCK_SIZE_MULTIPLE_MASK) != 0U)) + { + return AESCTR_STATUS_ERROR; + } + + object->operation = (AESCTR_OperationUnion *)operation; + + object->input = operation->input; + object->output = operation->output; + object->inputLength = operation->inputLength; + + return AESCTRLPF3HSM_processOneStepOperation(handle); +} + +int_fast16_t AESCTRLPF3HSM_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRLPF3_Object *object = AESCTRLPF3_getObject(handle); + AESCTR_OperationType operationType; + int_fast16_t status; + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESCTR_STATUS_ERROR; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure of segmented operation */ + if (object->common.returnStatus != AESCTR_STATUS_SUCCESS) + { + /* Return the failure status of previous call. + * The callback will not be called. + */ + return object->common.returnStatus; + } + + if (object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + operationType = AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE; + } + else + { + operationType = AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE; + } + + if (operation->inputLength > 0U) + { + object->operationType = operationType; + object->operation = (AESCTR_OperationUnion *)operation; + + object->input = operation->input; + object->output = operation->output; + object->inputLength = operation->inputLength; + + status = AESCTRLPF3HSM_processOneStepOperation(handle); + } + else /* Operation was finalized without additional data to process */ + { + /* Save the object's returnStatus in case it is + * overwritten during setup of a new segmented operation + * after the operationInProgress flag is cleared. + */ + status = object->common.returnStatus; + + object->segmentedOperationInProgress = false; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, (AESCTR_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + } + + return status; +} + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h index dde33a19..a7ca3e06 100644 --- a/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h +++ b/simplelink_lpf3/source/ti/drivers/aesctr/AESCTRLPF3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,13 +34,14 @@ * * @brief AESCTR driver implementation for the Low Power F3 family * - * # Hardware Accelerator # - * The Low Power F3 family of devices has a dedicated AES hardware that can perform - * AES encryption operations with 128-bit keys. Only one operation - * can be carried out on the accelerator at a time. Mutual exclusion is - * implemented at the driver level and coordinated between all drivers relying on - * the accelerator. It is transparent to the application and only noted to ensure - * sensible access timeouts are set. + * # Hardware Accelerator # + * The Low Power F3 family of devices has dedicated hardware accelerators. + * CC23XX devices have one dedicated accelerator whereas CC27XX devices have two + * (Primary and Secondary). Combined they can perform AES encryption operations with + * 128-bit, 192-bit and 256-bit keys. Only one operation can be carried out on the + * accelerator at a time. Mutual exclusion is implemented at the driver level and + * coordinated between all drivers relying on the accelerator. It is transparent to + * the application and only noted to ensure sensible access timeouts are set. * * # Implementation Limitations * - Only plaintext CryptoKeys are supported by this implementation. @@ -147,6 +148,17 @@ typedef struct AESCTR_CallbackFxn callbackFxn; AESCTR_OperationType operationType; bool threadSafe; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /*! + * @brief The staus of the HSM Boot up process + * if HSMLPF3_STATUS_SUCCESS, the HSM booted properly. + * if HSMLPF3_STATUS_ERROR, the HSM did not boot properly. + */ + int_fast16_t hsmStatus; + /* To indicate whether a segmented operation is in progress + */ + bool segmentedOperationInProgress; +#endif } AESCTRLPF3_Object; /*! @cond NODOC */ diff --git a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c index d17fbff2..6e5a0868 100644 --- a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c +++ b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -41,6 +42,10 @@ #include #include +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#endif + #include #include #include @@ -69,6 +74,13 @@ #error "Unsupported DeviceFamily_Parent for AESECBLPF3!" #endif +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #define PSA_SYM_MODE_GCM_NONE 0U + + /* Size of state asset for GCM/CCM continuation */ + #define PSA_SYM_STATE_ASSET_SIZE 48U +#endif + /* * AES ECB DMA config: * - ADRCHA = BUF0 @@ -105,6 +117,18 @@ static inline int_fast16_t AESECBLPF3_oneStepOperation(AESECB_Handle handle, static int_fast16_t AESECBLPF3_startOperation(AESECB_Handle handle, AESECB_Operation *operation); static inline int_fast16_t AESECBLPF3_waitForResult(AESECB_Handle handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +static int_fast16_t AESECBLPF3HSM_oneStepOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType); +static int_fast16_t AESECBLPF3HSM_processOneStep(AESECB_Handle handle); + +static int_fast16_t AESECBLPF3HSM_addData(AESECB_Handle handle, AESECB_Operation *operation); + +static int_fast16_t AESECBLPF3HSM_finalize(AESECB_Handle handle, AESECB_Operation *operation); + +#endif + /* * ======== AESEBCLPF3_getObject ======== */ @@ -163,6 +187,9 @@ static void AESECBLPF3_hwiFxn(uintptr_t arg0) */ void AESECB_init(void) { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + HSMLPF3_constructRTOSObjects(); +#endif AESCommonLPF3_init(); } @@ -177,6 +204,24 @@ AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *param AESECB_Handle handle = config; AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* Initialize and boot HSM */ + if (HSMLPF3_init() != HSMLPF3_STATUS_SUCCESS) + { + /* Upon HSM Boot failure, the AES-CCM Driver stores the failure status in the object + * This is done so that users of the AES-CCM Driver do not get a NULL handle and still can use + * the driver in LAES mode. + */ + object->hsmStatus = HSMLPF3_STATUS_ERROR; + } + else + { + object->hsmStatus = HSMLPF3_STATUS_SUCCESS; + } + + object->segmentedOperationInProgress = false; +#endif + /* If params are NULL, use defaults */ if (params == NULL) { @@ -215,7 +260,23 @@ void AESECB_close(AESECB_Handle handle) */ int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation) { - return AESECBLPF3_oneStepOperation(handle, operation, AESECB_OPERATION_TYPE_ENCRYPT); + int_fast16_t status = AESECB_STATUS_SUCCESS; + + if (operation->key->encoding == CryptoKey_PLAINTEXT || operation->key->encoding == CryptoKey_KEYSTORE) + { + status = AESECBLPF3_oneStepOperation(handle, operation, AESECB_OPERATION_TYPE_ENCRYPT); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESECBLPF3HSM_oneStepOperation(handle, operation, AESECB_OPERATION_TYPE_ENCRYPT); + } +#endif + else + { + status = AESECB_STATUS_ERROR; + } + return status; } /* @@ -226,7 +287,24 @@ int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *opera DebugP_assert(handle); DebugP_assert(operation); - return AESECB_STATUS_FEATURE_NOT_SUPPORTED; + int_fast16_t status = AESECB_STATUS_SUCCESS; + + if (operation->key->encoding == CryptoKey_PLAINTEXT || operation->key->encoding == CryptoKey_KEYSTORE) + { + status = AESECB_STATUS_FEATURE_NOT_SUPPORTED; + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + status = AESECBLPF3HSM_oneStepOperation(handle, operation, AESECB_OPERATION_TYPE_DECRYPT); + } +#endif + else + { + status = AESECB_STATUS_ERROR; + } + + return status; } /* @@ -507,10 +585,45 @@ static inline int_fast16_t AESECBLPF3_waitForResult(AESECB_Handle handle) int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key) { DebugP_assert(handle); - + int_fast16_t status = AESECB_STATUS_SUCCESS; AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); - int_fast16_t status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + /* + * Key material pointer and length are not checked until adding or + * finalizing data. + */ + if (key->encoding == CryptoKey_PLAINTEXT) + { + /* When using the AES driver with the LAES engine */ + status = AESCommonLPF3_setupSegmentedOperation(&object->common, key); + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + else if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESECB_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESECB_STATUS_ERROR; + } + + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->common.returnStatus = AES_STATUS_SUCCESS; + + object->segmentedOperationInProgress = true; + } +#endif + else + { + status = AESECB_STATUS_ERROR; + } if (status == AES_STATUS_SUCCESS) { @@ -521,10 +634,7 @@ int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key) object->operation = NULL; } - if (status == AES_STATUS_SUCCESS) - { - object->operationType = AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED; - } + object->operationType = AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED; return status; } @@ -538,10 +648,48 @@ int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key) DebugP_assert(key); AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status = AESECB_STATUS_SUCCESS; + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (key->encoding == CryptoKey_PLAINTEXT_HSM) + { + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESECB_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESECB_STATUS_ERROR; + } + + /* Make internal copy of crypto key */ + object->common.key = *key; + + /* returnStatus is only changed in the case of an error or cancellation */ + object->common.returnStatus = AES_STATUS_SUCCESS; + + /* Initialize operation pointer to NULL in case AESECB_cancelOperation + * is called after AESECB_setupXXXX and callback should be skipped. + */ + object->operation = NULL; + + object->operationType = AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED; + + object->segmentedOperationInProgress = true; + } + else +#endif + { + object->common.returnStatus = AESECB_STATUS_FEATURE_NOT_SUPPORTED; + status = AESECB_STATUS_FEATURE_NOT_SUPPORTED; + } /* Save the error status in case addData or finalize is called afterward */ - object->common.returnStatus = AESECB_STATUS_FEATURE_NOT_SUPPORTED; - return AESECB_STATUS_FEATURE_NOT_SUPPORTED; + + return status; } /* @@ -555,6 +703,13 @@ int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation) AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); int_fast16_t status; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESECBLPF3HSM_addData(handle, operation); + } +#endif + /* * Assert the segmented operation was setup. * LPF3 only supports ECB encryption. @@ -604,6 +759,13 @@ int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation) AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); int_fast16_t status; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (operation->key->encoding == CryptoKey_PLAINTEXT_HSM) + { + return AESECBLPF3HSM_finalize(handle, operation); + } +#endif + /* * Assert the segmented operation was setup. * LPF3 only supports ECB encryption. @@ -704,7 +866,11 @@ int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) * Do not execute the callback as it would have been executed already * when the operation completed. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if (((object->common.key.encoding & CRYPTOKEY_HSM) == 0) && (!object->common.operationInProgress)) +#else if (!object->common.operationInProgress) +#endif { HwiP_restore(interruptKey); return AESECB_STATUS_SUCCESS; @@ -718,9 +884,21 @@ int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) */ AESCommonLPF3_cancelOperation(&object->common, true); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + if ((object->common.key.encoding & CRYPTOKEY_HSM)) + { + /* Since the HSM cannot cancel an in-progress token, we must wait for the result to allow for + * subsequent token submissions to succeed. + */ + (void)HSMLPF3_cancelOperation(); + + object->segmentedOperationInProgress = false; + } +#endif + /* * Operation pointer could be NULL if a segmented operation was setup - * but neither AESCCM_addData or AESCCM_finalize was called. + * but neither AESECB_addData or AESECB_finalize was called. */ if ((object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) && (object->operation != NULL)) { @@ -730,3 +908,219 @@ int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) return AESECB_STATUS_SUCCESS; } + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/* + * ======== AESECBLPF3HSM_oneStepOperation ======== + */ +static int_fast16_t AESECBLPF3HSM_oneStepOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return HSMLPF3_STATUS_ERROR; + } + + /* A segmented operation may have been started but not finalized yet */ + if (object->segmentedOperationInProgress) + { + return AESECB_STATUS_ERROR; + } + + object->operation = operation; + object->operationType = operationType; + + object->common.key = *(operation->key); + /* We will only change the returnStatus if there is an error or cancellation */ + object->common.returnStatus = AESECB_STATUS_SUCCESS; + + return AESECBLPF3HSM_processOneStep(handle); +} + +/* + * ======== AESECBLPF3HSM_OneStepPostProcessing ======== + */ +static inline void AESECBLPF3HSM_OneStepPostProcessing(uintptr_t arg0) +{ + AESECB_Handle handle = (AESECB_Handle)arg0; + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status = AESECB_STATUS_ERROR; + int32_t physicalResult = HSMLPF3_getResultCode(); + int32_t tokenResult = physicalResult & HSMLPF3_RETVAL_MASK; + + if (tokenResult == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESECB_STATUS_SUCCESS; + } + + object->common.returnStatus = status; + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + if ((object->operationType == AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED) || + (object->operationType == AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED) || + (object->operationType == AESECB_OPERATION_TYPE_ENCRYPT) || + (object->operationType == AESECB_OPERATION_TYPE_DECRYPT)) + { + object->segmentedOperationInProgress = false; + } + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, object->common.returnStatus, object->operation, object->operationType); + } +} + +static int_fast16_t AESECBLPF3HSM_processOneStep(AESECB_Handle handle) +{ + int_fast16_t status = AESECB_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)handle)) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_constructAESECBOneStepPhysicalToken(object); + + hsmRetval = HSMLPF3_submitToken((HSMLPF3_ReturnBehavior)object->common.returnBehavior, + AESECBLPF3HSM_OneStepPostProcessing, + (uintptr_t)handle); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = object->common.returnStatus; + } + } + + if (hsmRetval != HSMLPF3_STATUS_SUCCESS) + { + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + HSMLPF3_releaseLock(); + } + + return status; +} + +static int_fast16_t AESECBLPF3HSM_addData(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESECB_STATUS_ERROR; + } + + /* + * Assert the segmented operation was setup. + * LPF3 only supports ECB encryption. + */ + DebugP_assert((object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESECB_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + object->operation = operation; + + return AESECBLPF3HSM_processOneStep(handle); +} + +static int_fast16_t AESECBLPF3HSM_finalize(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBLPF3_Object *object = AESEBCLPF3_getObject(handle); + int_fast16_t status; + + /* If the HSM IP and/or HSMSAL failed to boot then we cannot perform any HSM-related operation */ + if (object->hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return AESECB_STATUS_ERROR; + } + + /* + * Assert the segmented operation was setup. + * LPF3 only supports ECB encryption. + */ + DebugP_assert((object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Check for previous failure or cancellation of segmented operation */ + if (object->common.returnStatus != AESECB_STATUS_SUCCESS) + { + /* + * Return the status of the previous call. + * The callback function will not be executed. + */ + return object->common.returnStatus; + } + + if (object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + object->operationType = AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED; + } + else if (object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED) + { + object->operationType = AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED; + } + + if (operation->inputLength > 0U) + { + object->operation = operation; + + status = AESECBLPF3HSM_processOneStep(handle); + } + else /* Operation was finalized without additional data to process */ + { + /* Save the object's returnStatus in case it is + * overwritten during setup of a new segmented operation + * after the operationInProgress flag is cleared. + */ + status = object->common.returnStatus; + + object->segmentedOperationInProgress = false; + + if (object->common.returnBehavior == AES_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, status, operation, object->operationType); + + /* Always return success in callback mode */ + status = AESECB_STATUS_SUCCESS; + } + } + + return status; +} + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h index 71a62f0b..e39ec24e 100644 --- a/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h +++ b/simplelink_lpf3/source/ti/drivers/aesecb/AESECBLPF3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,13 +34,14 @@ * * @brief AESECB driver implementation for the Low Power F3 family * - * # Hardware Accelerator # - * The Low Power F3 family of devices has a dedicated AES hardware that can perform - * AES encryption operations with 128-bit keys. Only one operation - * can be carried out on the accelerator at a time. Mutual exclusion is - * implemented at the driver level and coordinated between all drivers - * relying on the accelerator. It is transparent to the application and only - * noted to ensure sensible access timeouts are set. + * # Hardware Accelerator # + * The Low Power F3 family of devices has dedicated hardware accelerators. + * CC23XX devices have one dedicated accelerator whereas CC27XX devices have two + * (Primary and Secondary). Combined they can perform AES encryption operations with + * 128-bit, 192-bit and 256-bit keys. Only one operation can be carried out on the + * accelerator at a time. Mutual exclusion is implemented at the driver level and + * coordinated between all drivers relying on the accelerator. It is transparent to + * the application and only noted to ensure sensible access timeouts are set. * * # Implementation Limitations * - Decryption is not supported since the AES HW only supports encryption. @@ -114,6 +115,22 @@ typedef struct AESECB_CallbackFxn callbackFxn; AESECB_OperationType operationType; bool threadSafe; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + const uint8_t *input; + uint8_t *output; + size_t inputLength; + size_t totalDataLength; + volatile size_t totalDataLengthRemaining; + /*! + * @brief The staus of the HSM Boot up process + * if HSMLPF3_STATUS_SUCCESS, the HSM booted properly. + * if HSMLPF3_STATUS_ERROR, the HSM did not boot properly. + */ + int_fast16_t hsmStatus; + /* To indicate whether a segmented operation is in progress + */ + bool segmentedOperationInProgress; +#endif } AESECBLPF3_Object; /*! diff --git a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c index 29a6e496..1e380ec3 100644 --- a/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c +++ b/simplelink_lpf3/source/ti/drivers/batterymonitor/BatMonSupportLPF3.c @@ -67,14 +67,7 @@ static uint32_t batteryEventMask = 0; static bool isInitialized = false; -//extern const BatMonSupportLPF3_Config BatMonSupportLPF3_config; - -// TODO: make this configurable -const BatMonSupportLPF3_Config BatMonSupportLPF3_config = { - .intNum = INT_CPUIRQ0, - .intPriority = (~0), - .intMux = EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB -}; +extern const BatMonSupportLPF3_Config BatMonSupportLPF3_config; /* * ======== batMonHwiFxn ======== @@ -124,8 +117,10 @@ void BatMonSupportLPF3_init(void) /* Disable all events */ HWREG(PMUD_BASE + PMUD_O_EVENTMASK) = 0; - /* Enable BATMON */ - HWREG(PMUD_BASE + PMUD_O_CTL) |= (PMUD_CTL_CALC_EN | PMUD_CTL_MEAS_EN); + /* Enable BATMON. Explicitly disable HW hysteresis to avoid HW bug + * causing poor temperature measurement accuracy. + */ + HWREG(PMUD_BASE + PMUD_O_CTL) = PMUD_CTL_CALC_EN | PMUD_CTL_MEAS_EN | PMUD_CTL_HYST_EN_DIS; /* Set the combined BATMON interrupt as a wakeup source. This means the * BATMON can bring the device out of standby when an event is diff --git a/simplelink_lpf3/source/ti/drivers/config_defaults.c b/simplelink_lpf3/source/ti/drivers/config_defaults.c index d15face3..de9c0330 100644 --- a/simplelink_lpf3/source/ti/drivers/config_defaults.c +++ b/simplelink_lpf3/source/ti/drivers/config_defaults.c @@ -219,3 +219,18 @@ const uint_least8_t AESECB_count = CONFIG_AESECB_COUNT; const UDMALPF3_Config UDMALPF3_config = { .CtrlBaseAddr = UDMALPF3_CONFIG_BASE, }; + +/* + * =============================== BatMon Support =============================== + */ +#include + +#include +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) + +const BatMonSupportLPF3_Config BatMonSupportLPF3_config = { + .intNum = INT_CPUIRQ0, + .intPriority = (~0), + .intMux = EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB +}; diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c index 23193b7d..fb729df3 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c @@ -35,6 +35,7 @@ #if defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ #include /* TI CMSE helper functions */ + #include /* * ======== CryptoKey_verifySecureKey ======== @@ -87,6 +88,58 @@ int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey) return CryptoKey_verifySecureKey(secureKey, true); } +/* + * ======== CryptoKey_copySecureInputKey ======== + */ +int_fast16_t CryptoKey_copySecureInputKey(CryptoKey *dst, const CryptoKey **src) +{ + /* Validate source key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)*src, sizeof(CryptoKey)) == NULL) + { + return CryptoKey_STATUS_ERROR; + } + + /* Make a secure copy of the key */ + (void)spm_memcpy(dst, *src, sizeof(CryptoKey)); + + /* Validate the key material address range */ + if (CryptoKey_verifySecureInputKey(dst) != CryptoKey_STATUS_SUCCESS) + { + return CryptoKey_STATUS_ERROR; + } + + /* Update the src pointer to point to secure key copy */ + *src = dst; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKey_copySecureOutputKey ======== + */ +int_fast16_t CryptoKey_copySecureOutputKey(CryptoKey *dst, CryptoKey **src) +{ + /* Validate source key struct address range */ + if (cmse_has_unpriv_nonsecure_rw_access(*src, sizeof(CryptoKey)) == NULL) + { + return CryptoKey_STATUS_ERROR; + } + + /* Make a secure copy of the key */ + (void)spm_memcpy(dst, *src, sizeof(CryptoKey)); + + /* Validate the key material address range */ + if (CryptoKey_verifySecureOutputKey(dst) != CryptoKey_STATUS_SUCCESS) + { + return CryptoKey_STATUS_ERROR; + } + + /* Update the src pointer to point to secure key copy */ + *src = dst; + + return CryptoKey_STATUS_SUCCESS; +} + #endif /* TFM_BUILD */ /* diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h index 2eca0004..8de56e97 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h @@ -147,15 +147,27 @@ extern "C" { /** @}*/ +/* + * CRYPTOKEY_HSM is being used to mask bit 6 which determines which accelerator to use. + * Any encoding that is ORed with CRYPTOKEY_HSM indicates that the HSM is the engine of choice for the operation + */ +#define CRYPTOKEY_HSM 0x20U + +#define CRYPTOKEY_PLAINTEXT 0x02U +#define CRYPTOKEY_BLANK_PLAINTEXT 0x04U +#define CRYPTOKEY_KEYSTORE 0x08U +#define CRYPTOKEY_BLANK_KEYSTORE 0x10U + /*! * @brief List of the different types of CryptoKey. - * + * _HSM encodings are only available for select devices, CC27XX. */ typedef uint8_t CryptoKey_Encoding; -static const CryptoKey_Encoding CryptoKey_PLAINTEXT = 0x02U; -static const CryptoKey_Encoding CryptoKey_BLANK_PLAINTEXT = 0x04U; -static const CryptoKey_Encoding CryptoKey_KEYSTORE = 0x08U; -static const CryptoKey_Encoding CryptoKey_BLANK_KEYSTORE = 0x10U; +static const CryptoKey_Encoding CryptoKey_PLAINTEXT = CRYPTOKEY_PLAINTEXT; +static const CryptoKey_Encoding CryptoKey_BLANK_PLAINTEXT = CRYPTOKEY_BLANK_PLAINTEXT; +static const CryptoKey_Encoding CryptoKey_KEYSTORE = CRYPTOKEY_KEYSTORE; +static const CryptoKey_Encoding CryptoKey_BLANK_KEYSTORE = CRYPTOKEY_BLANK_KEYSTORE; +static const CryptoKey_Encoding CryptoKey_PLAINTEXT_HSM = CRYPTOKEY_PLAINTEXT | CRYPTOKEY_HSM; /*! * @brief Plaintext CryptoKey datastructure. @@ -276,6 +288,44 @@ int_fast16_t CryptoKey_verifySecureInputKey(const CryptoKey *secureKey); */ int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey); +/*! + * @brief Function to copy and verify a secure input CryptoKey + * + * This will check that the source CryptoKey struct is located in non-secure + * read-access memory, copy the CryptoKey struct from the src to dst, and check + * that the key type is valid and verify plaintext key material is located in + * non-secure read-access memory. + * + * @note This function may not be available in all implementations + * + * @param [out] dst Pointer to the destination CryptoKey struct located in secure memory + * @param [in,out] src Pointer to a source CryptoKey struct pointer located in secure memory + * which will be updated to point to the destination CryptoKey struct + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_copySecureInputKey(CryptoKey *dst, const CryptoKey **src); + +/*! + * @brief Function to copy and verify a secure output CryptoKey + * + * This will check that the source CryptoKey struct is located in non-secure + * RW-access memory, copy the CryptoKey struct from the src to dst, and check + * that the key type is valid and verify plaintext key material is located in + * non-secure RW-access memory. + * + * @note This function may not be available in all implementations + * + * @param [out] dst Pointer to the destination CryptoKey struct located in secure memory + * @param [in,out] src Pointer to a source CryptoKey struct pointer located in secure memory + * which will be updated to point to the destination CryptoKey struct + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_copySecureOutputKey(CryptoKey *dst, CryptoKey **src); + #ifdef __cplusplus } #endif diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c index aee82b53..404a51c5 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2022-2024 Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -110,9 +110,9 @@ KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes /* * ======== KeyStore_PSA_setKeyUsageFlags ======== */ -void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usage_flags) +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usageFlags) { - psa_set_key_usage_flags(attributes, usage_flags); + psa_set_key_usage_flags(attributes, usageFlags); } /* diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h index 61525e2d..d03c2919 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated + * Copyright (c) 2022-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,75 +34,70 @@ * @file CryptoKeyKeyStore_PSA.h * @brief CryptoKeyKeyStore_PSA driver header * - * @warning This is a beta API. It may change in future releases. + * @warning This is a beta API. It may change in future releases. * - * # Overview # - * This file contains the APIs to import, export, copy, and destroy key store - * CryptoKeys. Key store CryptoKeys reference keying material stored in flash or - * RAM using a key identifier. These CryptoKeys are subject to enforced usage - * restrictions as defined by the key attributes assigned during key import. - * This file provides definitions that are common between the Non-Secure - * Processing Environment (NSPE) and Secure Processing Environment (SPE). + * # Overview # + * This file contains the APIs to import, export, copy, and destroy key store + * CryptoKeys. Key store CryptoKeys reference keying material stored in flash or + * RAM using a key identifier. These CryptoKeys are subject to enforced usage + * restrictions as defined by the key attributes assigned during key import. + * This file provides definitions that are common between the Non-Secure + * Processing Environment (NSPE) and Secure Processing Environment (SPE). * - * # Usage # + * # Usage # * - * After calling the key store initialization function, a CryptoKey must be - * imported into the key store before it can be used for a crypto operation APIs - * which takes a CryptoKey as an input. + * After calling the key store initialization function, a CryptoKey must be + * imported into the key store before it can be used for a crypto operation APIs + * which takes a CryptoKey as an input. - * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_Example + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_Example * - * ## Importing and exporting AES-CCM KeyStore keys # + * ## Importing and destroying a persistent AES-CCM KeyStore key # * - * @code + * @code * - * #include - * #include - * .... + * #include + * #include + * .... * - * uint8_t keyingMaterial[16]; //Assume keying material is already available - * uint8_t keyingMaterial2[16]; - * CryptoKey cryptoKey; - * KeyStore_PSA_KeyFileId keyID; - * int_fast16_t status; - * int_fast16_t returnedLength; - * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * CryptoKey cryptoKey; + * KeyStore_PSA_KeyFileId keyID; + * int_fast16_t status; + * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; * - * // Assign key attributes. - * KeyStore_PSA_setKeyUsageFlags(&attributes, (KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT)); - * KeyStore_PSA_setKeyAlgorithm(&attributes, KEYSTORE_PSA_ALG_CCM); - * KeyStore_PSA_setKeyType(&attributes, KEYSTORE_PSA_KEY_TYPE_AES); - * KeyStore_PSA_setKeyLifetime(&attributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); - * GET_KEY_ID(keyID,KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) - * KeyStore_PSA_setKeyId(&attributes, keyID); + * // Assign key attributes + * KeyStore_PSA_setKeyUsageFlags(&attributes, (KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT)); + * KeyStore_PSA_setKeyAlgorithm(&attributes, KEYSTORE_PSA_ALG_CCM); + * KeyStore_PSA_setKeyType(&attributes, KEYSTORE_PSA_KEY_TYPE_AES); + * KeyStore_PSA_setKeyLifetime(&attributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); * - * // Import the keyingMaterial - * status = KeyStore_PSA_importKey(&attributes, keyingMaterial, sizeof(keyingMaterial), &keyID); + * // Set key ID + * GET_KEY_ID(keyID, KEYSTORE_PSA_KEY_ID_USER_MIN); + * KeyStore_PSA_setKeyId(&attributes, keyID); * - * if (status != KEYSTORE_PSA_STATUS_SUCCESS) - * { - * // Handle error - * } + * // Import the keyingMaterial + * status = KeyStore_PSA_importKey(&attributes, keyingMaterial, sizeof(keyingMaterial), &keyID); * - * //Initialize the cryptoKey - * KeyStore_PSA_initKey(&cryptoKey, keyID, sizeof(keyingMaterial), NULL); + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } * - * // Export the previously imported CryptoKey using keyID - * status = KeyStore_PSA_exportKey(keyID, keyingMaterial2, sizeof(keyingMaterial2), &returnedLength); + * // Initialize cryptoKey for crypto operations + * KeyStore_PSA_initKey(&cryptoKey, keyID, sizeof(keyingMaterial), NULL); * - * if (status != KEYSTORE_PSA_STATUS_SUCCESS) - * { - * // Handle error - * } + * // Use the cryptoKey for AESCCM operations * - * // Destroy key after use - * status = KeyStore_PSA_destroyKey(keyID); + * // Destroy key after use + * status = KeyStore_PSA_destroyKey(keyID); * - * if (status != KEYSTORE_PSA_STATUS_SUCCESS) - * { - * // Handle error - * } - * @endcode + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * @endcode * */ @@ -111,8 +106,10 @@ #if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ #include + #include #include #include + #include #else #include #endif /* #if (TFM_ENABLED == 0) || defined(TFM_BUILD) */ @@ -129,15 +126,119 @@ typedef psa_key_usage_t KeyStore_PSA_KeyUsage; * The lifetime of a key indicates where it is stored and what system * actions may create and destroy it. * - * Keys with the lifetime #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE are automatically - * destroyed when the application terminates or on a power reset. - * - * Keys with a lifetime other than #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE are said - * to be _persistent_. - * Persistent keys are preserved if the application or the system restarts. + * Lifetime values have the following structure: + * - Bits 0-7 (#KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(\c lifetime)): + * persistence level. This value indicates what device management + * actions can cause it to be destroyed. In particular, it indicates + * whether the key is _volatile_ or _persistent_. + * See ::KeyStore_PSA_KeyPersistence for more information. + * - Bits 8-31 (#KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(\c lifetime)): + * location indicator. This value indicates which part of the system + * has access to the key material and can perform operations using the key. + * See ::KeyStore_PSA_KeyLocation for more information. + * + * Volatile keys are automatically destroyed when the application instance + * terminates or on a power reset of the device. Persistent keys are + * preserved until the application explicitly destroys them or until an + * integration-specific device management event occurs (for example, + * a factory reset). + * + * Persistent keys have a key identifier of type #KeyStore_PSA_KeyFileId. + * This identifier remains valid throughout the lifetime of the key, + * even if the application instance that created the key terminates. + * + * The default lifetime of a key is #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE. The lifetime + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT is supported if persistent storage is + * available. Other lifetime values may be supported depending on the + * library configuration. + * + * Values of this type are generally constructed by macros called + * `KEYSTORE_PSA_KEY_LIFETIME_xxx`. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. */ typedef psa_key_lifetime_t KeyStore_PSA_KeyLifetime; +/** Encoding of key persistence levels. + * + * What distinguishes different persistence levels is what device management + * events may cause keys to be destroyed. _Volatile_ keys are destroyed + * by a power reset. Persistent keys may be destroyed by events such as + * a transfer of ownership or a factory reset. What management events + * actually affect persistent keys at different levels is outside the + * scope of the PSA Cryptography specification. + * + * The PSA Cryptography specification defines the following values of + * persistence levels: + * - \c 0 = #KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE: volatile key. + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * - \c 1 = #KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT: + * persistent key with a default lifetime. + * - \c 2-254: currently not supported by Mbed TLS. + * - \c 255 = #KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY: + * read-only or write-once key. + * A key with this persistence level cannot be destroyed. + * Mbed TLS does not currently offer a way to create such keys, but + * integrations of Mbed TLS can use it for built-in keys that the + * application cannot modify (for example, a hardware unique key (HUK)). + * + * @note Key persistence levels are 8-bit values. Key management + * interfaces operate on lifetimes (type ::KeyStore_PSA_KeyLifetime) which + * encode the persistence as the lower 8 bits of a 32-bit value. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef psa_key_persistence_t KeyStore_PSA_KeyPersistence; + +/** Encoding of key location indicators. + * + * If an application can make calls to external + * cryptoprocessors such as secure elements, the location of a key + * indicates which secure element performs the operations on the key. + * Depending on the design of the secure element, the key + * material may be stored either in the secure element, or + * in wrapped (encrypted) form alongside the key metadata in the + * primary local storage. + * + * The PSA Cryptography API specification defines the following values of + * location indicators: + * - \c 0: primary local storage. + * This location is always available. + * The primary local storage is typically the same storage area that + * contains the key metadata. + * - \c 1: primary secure element. + * Integrations of Mbed TLS should support this value if there is a secure + * element attached to the operating environment. + * As a guideline, secure elements may provide higher resistance against + * side channel and physical attacks than the primary local storage, but may + * have restrictions on supported key types, sizes, policies and operations + * and may have different performance characteristics. + * - \c 2-0x7fffff: other locations defined by a PSA specification. + * The PSA Cryptography API does not currently assign any meaning to these + * locations, but future versions of that specification or other PSA + * specifications may do so. + * - \c 0x800000-0xffffff: vendor-defined locations. + * No PSA specification will assign a meaning to locations in this range. + * + * @note Key location indicators are 24-bit values. Key management + * interfaces operate on lifetimes (type ::KeyStore_PSA_KeyLifetime) which + * encode the location as the upper 24 bits of a 32-bit value. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef psa_key_location_t KeyStore_PSA_KeyLocation; + /** @defgroup KeyStore_PSA_Statuses Key Store status return values. */ /** The action was completed successfully. */ @@ -568,9 +669,34 @@ typedef psa_algorithm_t KeyStore_PSA_Algorithm; */ #define KEYSTORE_PSA_ALG_ECDH ((KeyStore_PSA_Algorithm)PSA_ALG_ECDH) +/** ECDSA signature without hashing. + * + * This is the same signature scheme without specifying a hash algorithm. + * This algorithm may only be used to sign or verify a sequence of bytes + * that should be an pre-calculated hash. + */ +#define KEYSTORE_PSA_ALG_ECDSA ((KeyStore_PSA_Algorithm)PSA_ALG_ECDSA_ANY) + /** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. */ #define KEYSTORE_PSA_ALG_PAKE ((KeyStore_PSA_Algorithm)PSA_ALG_JPAKE) +/** Edwards-curve digital signature algorithm without prehashing (PureEdDSA), + * using standard parameters. + * + * PureEdDSA requires an elliptic curve key on a twisted Edwards curve. + * In this specification, the following curves are supported: + * - PSA_ECC_FAMILY_TWISTED_EDWARDS, 255-bit: Ed25519 as specified + * in RFC 8032. + * The curve is Edwards25519. + * The hash function used internally is SHA-512. + * + * This algorithm can be used with #KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE and + * #KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE. Since there is no prehashing, it cannot be used + * with #KEYSTORE_PSA_KEY_USAGE_SIGN_HASH and #KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH. + * + */ +#define KEYSTORE_PSA_ALG_PURE_EDDSA ((KeyStore_PSA_Algorithm)PSA_ALG_PURE_EDDSA) + /* The encoding of curve identifiers is currently aligned with the * TLS Supported Groups Registry (formerly known as the * TLS EC Named Curve Registry) @@ -632,19 +758,18 @@ typedef psa_algorithm_t KeyStore_PSA_Algorithm; */ #define KEYSTORE_PSA_ECC_CURVE_VENDOR_MAX ((KeyStore_PSA_KeyType)PSA_ECC_CURVE_VENDOR_MAX) -/* Volatile Key Limit [PSA_KEY_ID_VOLATILE_MIN, PSA_KEY_ID_VOLATILE_MAX] - * Upper limit for volatile key ID, PSA_KEY_ID_VOLATILE_MAX, is PSA_KEY_ID_VENDOR_MAX. +/** Volatile Key Limit [KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, KEYSTORE_PSA_MAX_VOLATILE_KEY_ID] + * + * Upper limit for volatile key ID, KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, is KEYSTORE_PSA_KEY_ID_VENDOR_MAX. * Lower limit for volatile key ID, KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, is the last - * #MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of provided by implementation reserved for vendors. + * MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of provided by implementation reserved for vendors. */ - #if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MIN #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MAX #else - /* - * PSA_KEY_SLOT_COUNT is not available in TF-M's crypto.h so we must - * hardcode it to match the value in mbedCrypto's header. + /* PSA_KEY_SLOT_COUNT is not available in TF-M's crypto.h so we must + * hardcode it to match the value in Mbed TLS's header. */ #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID (PSA_KEY_ID_VENDOR_MAX - MBEDTLS_PSA_KEY_SLOT_COUNT + 1) #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VENDOR_MAX @@ -657,12 +782,20 @@ typedef psa_algorithm_t KeyStore_PSA_Algorithm; * @{ */ -/** A volatile key only exists as long as the handle to it is not closed. +/** The default lifetime for volatile keys. + * + * A volatile key only exists as long as the identifier to it is not destroyed. * The key material is guaranteed to be erased on a power reset. + * + * A key with this lifetime is stored in RAM. + * + * Equivalent to + * #KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(#KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE, + * #KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE) */ #define KEYSTORE_PSA_KEY_LIFETIME_VOLATILE ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_VOLATILE) -/** The default storage area for persistent keys. +/** The default lifetime for persistent keys. * * A persistent key remains in storage until it is explicitly destroyed or * until the corresponding storage area is wiped. This specification does @@ -673,43 +806,110 @@ typedef psa_algorithm_t KeyStore_PSA_Algorithm; * This lifetime value is the default storage area for the calling * application. Implementations may offer other storage areas designated * by other lifetime values as implementation-specific extensions. + * + * Equivalent to + * #KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(#KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT, + * #KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE) */ #define KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_PERSISTENT) -/** The null key identifier. +/** The persistence level of volatile keys. + * + * See ::KeyStore_PSA_KeyPersistence for more information. */ -#define KEYSTORE_PSA_KEY_ID_NULL ((KeyStore_PSA_KeyFileId)0x0) +#define KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_VOLATILE) -/** The minimum value for a key identifier chosen by the application. +/** The default persistence level for persistent keys. + * + * See ::KeyStore_PSA_KeyPersistence for more information. */ -#define KEYSTORE_PSA_KEY_ID_USER_MIN ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_USER_MIN) +#define KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_DEFAULT) -/** The minimum value for a persistent key identifier chosen by the application. +/** A persistence level indicating that a key is never destroyed. + * + * See ::KeyStore_PSA_KeyPersistence for more information. */ -#define KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN 0x41 +#define KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_READ_ONLY) + +#define KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) ((KeyStore_PSA_KeyPersistence)((lifetime)&0x000000ff)) -/** The maximum value for a persistent key identifier with associated certificate chosen by the application. - * KeyStore uses Bit 29 in KeyID to indicate certificate storage. - * Application may choose any key ID less than 2^29 for persistent keys - * Persistent Key ID limit [KEYSTORE_PSA_MAX_VOLATILE_KEY_ID + 1, KEYSTORE_PSA_KEY_ID_USER_MIN] - * (Setting bit 30 makes KeyID greater than PSA_KEY_ID_USER_MIN which will fall into VENDOR limit) - * (Setting bit 31 makes KeyID greater than PSA_KEY_ID_VENDOR_MAX which is not a valid KeyID) +#define KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(lifetime) ((KeyStore_PSA_KeyLocation)((lifetime) >> 8)) + +/** Whether a key lifetime indicates that the key is volatile. + * + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * + * A key that is not volatile is persistent. Persistent keys are + * preserved until the application explicitly destroys them or until an + * implementation-specific device management event occurs (for example, + * a factory reset). + * + * @param lifetime The lifetime value to query (value of type + * ::KeyStore_PSA_KeyLifetime). + * + * @return \c 1 if the key is volatile, otherwise \c 0. */ -#define KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX 0x1fffffff +#define KEYSTORE_PSA_KEY_LIFETIME_IS_VOLATILE(lifetime) \ + (KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE) -/** - * @brief Bit mask to set 29th bit to indicate certificate storage +/** Whether a key lifetime indicates that the key is read-only. + * + * Read-only keys cannot be created or destroyed through the PSA Crypto API. + * They must be created through platform-specific means that bypass the API. + * + * Some platforms may offer ways to destroy read-only keys. For example, + * consider a platform with multiple levels of privilege, where a + * low-privilege application can use a key but is not allowed to destroy + * it, and the platform exposes the key to the application with a read-only + * lifetime. High-privilege code can destroy the key even though the + * application sees the key as read-only. + * + * @param lifetime The lifetime value to query (value of type + * ::KeyStore_PSA_KeyLifetime). + * + * @return \c 1 if the key is read-only, otherwise \c 0. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime) \ + (KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY) + +/** Construct a lifetime from a persistence level and a location. + * + * @param persistence The persistence level + * (value of type ::KeyStore_PSA_KeyPersistence). + * @param location The location indicator + * (value of type ::KeyStore_PSA_KeyLocation). + * + * @return The constructed lifetime value. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location) \ + (PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location)) + +/** The local storage area for persistent keys. * + * This storage area is available on all systems that can store persistent + * keys without delegating the storage to a third-party cryptoprocessor. + * + * See ::KeyStore_PSA_KeyLocation for more information. + */ +#define KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE ((KeyStore_PSA_KeyLocation)PSA_KEY_LOCATION_LOCAL_STORAGE) + +/** The null key identifier. + */ +#define KEYSTORE_PSA_KEY_ID_NULL ((KeyStore_PSA_keyID)0x0) + +/** The minimum value for a key identifier chosen by the application. */ -#define KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT (1 << 29) +#define KEYSTORE_PSA_KEY_ID_USER_MIN ((KeyStore_PSA_keyID)PSA_KEY_ID_USER_MIN) /** The minimum value for a key identifier chosen by the implementation. */ -#define KEYSTORE_PSA_KEY_ID_VENDOR_MIN ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_VENDOR_MIN) +#define KEYSTORE_PSA_KEY_ID_VENDOR_MIN ((KeyStore_PSA_keyID)PSA_KEY_ID_VENDOR_MIN) /** The maximum value for a key identifier chosen by the implementation. */ -#define KEYSTORE_PSA_KEY_ID_VENDOR_MAX ((KeyStore_PSA_KeyFileId)PSA_KEY_ID_VENDOR_MAX) +#define KEYSTORE_PSA_KEY_ID_VENDOR_MAX ((KeyStore_PSA_keyID)PSA_KEY_ID_VENDOR_MAX) /** Default Key Owner */ @@ -951,11 +1151,13 @@ typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; #endif /* defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) */ #else + +typedef psa_key_id_t KeyStore_PSA_keyID; + /** Encoding of identifiers of persistent keys for client side. * * - Applications may freely choose key identifiers in the range - * #KEYSTORE_PSA_KEY_ID_USER_MIN to #KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX or - * #KEYSTORE_PSA_KEY_ID_WITHOUT_CERTIFICATE_USER_MAX. + * #KEYSTORE_PSA_KEY_ID_USER_MIN to #KEYSTORE_PSA_KEY_ID_USER_MAX * - Implementations may define additional key identifiers in the range * #KEYSTORE_PSA_KEY_ID_VENDOR_MIN to #KEYSTORE_PSA_KEY_ID_VENDOR_MAX. * - 0 is reserved as an invalid key identifier. @@ -986,15 +1188,6 @@ typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; */ #define KEYSTORE_PSA_PREPROVISIONED_AREA_SIZE (0x700) /* 1792 B */ -/** - * @brief Exportable pre-provisioned key prefix - * - * Prefix the plaintext key in pre-provisioned key that can be exported to the non-secure application with this flag - */ -#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG 0xAAAA -#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG)) -#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_NO_EXPORT_FLAG 0xA5A5 - /** * @brief Macro to indicate empty pre-provisioned key memory */ @@ -1018,97 +1211,10 @@ typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; /** * @brief Admissible key ID range for Pre-provisioned keys * - * 0x21 - 0x40 is reserved to store pre-provisioned keys. Correspondingly, 0x10000021 - 0x10000040 is reserved for any - * associated certificates. - */ -#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX 0x40 -#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN 0x21 -#define KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MAX \ - (KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) -#define KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MIN \ - (KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) - -/** - * @brief Reserved pre-provisioned key IDs - * - * Some known pre-provisioned key used by attestation service have reserved key IDs in the admissible range for - * pre-provisioned keys + * 0x7fff0000 - 0x7fffefff is reserved to store pre-provisioned keys. */ -#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PUB_KEY_ID 0x40 -#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PRI_KEY_ID 0X3F -#define KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_CERTIFICATE_ID \ - (KEYSTORE_PSA_PRE_PROVISIONED_ATTESTATION_PUB_KEY_ID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT) - -/** - * @brief Structure for storing pre-provisioned key's meta data - * - * - header : magic header to indicate the start of the pre-provisioned key - * - id : key id (and its owner when applicable) - * - export : Flag that needs to be set with correct string to allow exporting to non-secure application - * - alg : Cryptographic algorithm permitted using this key - * - usage : Usage for the key as described the KeyStore API - * - keyLength : Length of the pre-provisioned key - */ -typedef struct -{ - uint8_t header[KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH]; - uint32_t lifetime; - KeyStore_PSA_KeyFileId id; - uint32_t export; - KeyStore_PSA_Algorithm alg; - KeyStore_PSA_KeyUsage usage; - uint32_t keyLength; -} KeyStore_PreProvisionedKeyMetaData; - -/** - * @brief Size of the meta data associated with the pre-provisoned key - */ -#define KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE sizeof(KeyStore_PreProvisionedKeyMetaData) - -/** - * @brief Structure for storing pre-provisioned keys and its meta data - * - * - meta : Structure to meta data associated with each pre-provisioned key - * - KeyMaterial : A pointer to the plaintext key material - * - fletcher : 32-bit Fletcher checksum over the pre-provisioned key and its meta data - */ -typedef struct -{ - KeyStore_PreProvisionedKeyMetaData meta; - uint8_t *keyMaterial; - uint32_t fletcher; -} KeyStore_preProvisionedKeyStorageFormat; - -/** - * @brief Initialize a KeyStore_preProvisionedKeyStorageFormat struct variable - */ -#define KEYSTORE_PSA_PREPROVISIONED_KEY_FORMAT_INIT \ - { \ - KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER, 0, KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG, 0, 0, 0, 0, \ - KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END, 0 \ - } - -/** - * @brief Structure for storing IDs of pre-provisioned keys - * - * Also stores minimal meta data required to import pre-provisioned keys from persistent memory - * - * - addr : Starting address of the plaintext key material in pre-provisioned key memory - * - id : Key ID (and its owner when applicable) - * - alg : Algorithm the key will be used for - * - usage : Key usage - * - export : Flag to indicate the exportability of of the pre-provisioned key - * - keyLength : Size of the pre-provisioned key - */ -typedef struct -{ - uint8_t *addr; - KeyStore_PSA_KeyFileId id; - KeyStore_PSA_Algorithm alg; - KeyStore_PSA_KeyUsage usage; - uint32_t export; - uint32_t keyLength; -} KeyStore_PSA_preProvisionedKeyIDs; +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX MBEDTLS_PSA_KEY_ID_BUILTIN_MAX +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN MBEDTLS_PSA_KEY_ID_BUILTIN_MIN /** * @brief Declare a key as persistent and set its key identifier. @@ -1170,7 +1276,7 @@ void KeyStore_PSA_setKeyLifetime(KeyStore_PSA_KeyAttributes *attributes, KeyStor * * @param [in] attributes The key attribute structure to query. * - * \return The persistent identifier stored in the attribute structure. + * @return The persistent identifier stored in the attribute structure. * This value is unspecified if the attribute structure declares * the key as volatile. */ @@ -1185,7 +1291,7 @@ KeyStore_PSA_KeyFileId KeyStore_PSA_getKeyId(KeyStore_PSA_KeyAttributes *attribu * * @param [in] attributes The key attribute structure to query. * - * \return The lifetime value stored in the attribute structure. + * @return The lifetime value stored in the attribute structure. */ KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes *attributes); @@ -1204,9 +1310,9 @@ KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes * but in this case it must evaluate each of its arguments exactly once. * * @param [out] attributes The attribute structure to write to. - * @param usage_flags The usage flags to write. + * @param usageFlags The usage flags to write. */ -void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usage_flags); +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usageFlags); /** * @brief Retrieve the usage flags from key attributes. @@ -1217,7 +1323,7 @@ void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeySt * * @param [in] attributes The key attribute structure to query. * - * \return The usage flags stored in the attribute structure. + * @return The usage flags stored in the attribute structure. */ KeyStore_PSA_KeyUsage KeyStore_PSA_getKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes); @@ -1253,7 +1359,7 @@ void KeyStore_PSA_setKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes, KeySto * * @param [in] attributes The key attribute structure to query. * - * \return The algorithm stored in the attribute structure. + * @return The algorithm stored in the attribute structure. */ KeyStore_PSA_Algorithm KeyStore_PSA_getKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes); @@ -1300,7 +1406,7 @@ void KeyStore_PSA_setKeyBits(KeyStore_PSA_KeyAttributes *attributes, size_t bits * * @param [in] attributes The key attribute structure to query. * - * \return The key type stored in the attribute structure. + * @return The key type stored in the attribute structure. */ KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attributes); @@ -1312,7 +1418,7 @@ KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attribu * * @param [in] attributes The key attribute structure to query. * - * \return The key size stored in the attribute structure, in bits. + * @return The key size stored in the attribute structure, in bits. */ size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes); @@ -1330,38 +1436,6 @@ size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes); */ void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes); -/** - * @brief Export a certificate in binary format. - * - * The output of this function can be passed to KeyStore_PSA_importCertificate() - * to create an equivalent object. - * - * @param [in] key Key file ID of the key associated with the - * certificate to export. - * @param [out] data Buffer where the certificate data is to be written. - * @param [in] dataSize Size of the @p data buffer in bytes. - * @param [out] dataLength On success, the number - * of bytes that make up the certificate data. - * - * @retval #KEYSTORE_PSA_STATUS_SUCCESS - * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE - * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID - * The key identifier does not exist. - * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED - * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL - * The size of the @p data buffer is too small. - * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE - * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY - * @retval #KEYSTORE_PSA_STATUS_BAD_STATE - * The library has not been previously initialized by - * KeyStore_PSA_init(). It is implementation-dependent whether a failure to - * initialize results in this error code. - */ -int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, - uint8_t *data, - size_t dataSize, - size_t *dataLength); - /** * @brief Export a public key or the public part of a key pair in binary * format. @@ -1456,6 +1530,9 @@ int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, * bytes (leading zeroes are not stripped). * - For public keys, the format is the same as for KeyStore_PSA_exportPublicKey(). * + * This function can also be used to export other sensitive data, such as + * certificates using its corresponding key file ID. + * * The policy on the key must have the usage flag #KEYSTORE_PSA_KEY_USAGE_EXPORT * set. * @@ -1483,61 +1560,6 @@ int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, */ int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength); -/** - * @brief Import a certificate in binary format. - * - * This function supports the output from KeyStore_PSA_exportCertificate(). - * - * Multiple certificates cannot be imported for the same key ID. If an - * additional certificate needs to be associated with a particular key pair - * or public key, that key data must be imported again with a different key - * ID. Additionally, the key store does not interpret the contents of the - * certificate and cannot verify that the key embedded within the - * certificate matches the associated key. - * - * Implementations must reject an attempt to import a certificate of size 0. - * - * @param [in] attributes The attributes for the new certificate. - * The certificate size is always determined from - * the @p data buffer. If the certificate size in @p attributes is nonzero, - * it must be equal to the size from @p data. - * @param [out] key On success, the key file ID of the previously imported - * key associated with the certificate. @c 0 on failure. - * @param [in] data Buffer containing the certificate data in binary format. - * @param [in] dataLength Size of the @p data buffer in bytes. - * - * @retval #KEYSTORE_PSA_STATUS_SUCCESS - * Success. - * If the certificate is persistent, the certificate material and - * the certificate's metadata have been saved to persistent storage. - * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE - * @retval #KEYSTORE_PSA_STATUS_ALREADY_EXISTS This is an attempt to create a - * certificate, and there is already a certificate with the given - * identifier. - * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED The certificate type - * or certificate size is not supported, either by the implementation in - * general or in this particular persistent location. - * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The certificate attributes, as a whole, - * are invalid. - * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The certificate - * data is not correctly formatted. - * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The size in @p attributes is nonzero - * and does not match the size of the certificate data. - * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY - * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE - * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE - * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE @retval - * #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE @retval - * #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED @retval #KEYSTORE_PSA_STATUS_BAD_STATE - * The library has not been previously initialized by - * KeyStore_PSA_init(). It is implementation-dependent whether a failure to - * initialize results in this error code. - */ -int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, - KeyStore_PSA_KeyFileId *key, - uint8_t *data, - size_t dataLength); - /** * @brief Import a key in binary format. * @@ -1560,6 +1582,9 @@ int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attribut * minimize the risk that an invalid input is accidentally interpreted * according to a different format. * + * This function can also be used to store other sensitive data, such as + * certificate using key type #KEYSTORE_PSA_KEY_TYPE_RAW_DATA. + * * @param [in] attributes The attributes for the new key. * The key size is always determined from the * @p data buffer. @@ -1683,46 +1708,6 @@ int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_ */ int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key); -/** - * @brief Destroy a certificate associated with a key. - * - * This function destroys a certificate from both volatile - * memory and, if applicable, non-volatile storage. - * - * This function also erases any metadata such as policies and frees - * resources associated with the certificate. - * - * @param [in] key Key file ID of the key associated with certificate to - * erase. If key ID portion is @c 0, do nothing and return @c - * KEYSTORE_PSA_STATUS_SUCCESS. - * - * @retval #KEYSTORE_PSA_STATUS_SUCCESS - * @p ID was a valid ID and the certificate material that it - * referred to has been erased. - * Alternatively, @p ID is @c 0. - * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE - * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED - * The certificate cannot be erased because it is - * read-only, either due to a policy or due to physical - * restrictions. - * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID @p ID is not a validI D. - * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE There was an failure - * in communication with the cryptoprocessor. The certificate material may - * still be present in the cryptoprocessor. - * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE The storage is corrupted. - * Implementations shall make a best effort to erase certificate material - * even in this stage, however applications should be aware that it may be - * impossible to guarantee that the certificate material is not recoverable - * in such cases. - * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED An unexpected - * condition which is not a storage corruption or a communication failure - * occurred. The cryptoprocessor may have been compromised. - * @retval #KEYSTORE_PSA_STATUS_BAD_STATE The library has not been previously - * initialized by KeyStore_PSA_init(). It is implementation-dependent whether a - * failure to initialize results in this error code. - */ -int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key); - /** * @brief Destroy a key. * @@ -1730,9 +1715,6 @@ int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key); * applicable, non-volatile storage. Implementations shall make a best * effort to ensure that that the key material cannot be recovered. * - * If the key has an associated certificate, KeyStore_PSA_destroyCertificate() - * must be called to destroy the certificate before destroying the key. - * * This function also erases any metadata such as policies and frees * resources associated with the key. * @@ -1747,6 +1729,9 @@ int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key); * different key. This reduces the risk of an attack that is able to exploit * a key identifier reuse vulnerability within an application. * + * This function can also be used to destroy other sensitive data, such as + * certificates using its corresponding key file ID. + * * @param [in] key Key file ID of the key to erase. * If key ID portion is @c 0, do nothing and return @c * KEYSTORE_PSA_STATUS_SUCCESS. @@ -1757,8 +1742,8 @@ int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key); * Alternatively, @p ID is @c 0. * @retval KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED - * The key cannot be erased because it has an associated certificate - * or is read-only, either due to a policy or due to physical restrictions. + * The key cannot be erased because it is read-only, + * either due to a policy or due to physical restrictions. * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID * @p ID is not a valid ID. * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c index ec6feb4c..77f6a44b 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated + * Copyright (c) 2022-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -57,315 +57,9 @@ KeyStore_accessSemaphoreObject KeyStore_semaphoreObject = {.isAcquired = false, /** @brief Key handle identifier from mbedTLS 'psa_key_handle_t'. */ typedef psa_key_handle_t KeyStore_PSA_KeyHandle; -/** - * @brief Counter to keep track of the number of pre-provisioned keys available during KeyStore_PSA_init() - * - * preProvisionedKeyCount is set to the empty macro to indicate no provisioned keys and later initialized to the length - * of pre-provisioned key memory if pre-provisioned keys are available during initialization of the KeyStore driver. - */ -static uint32_t preProvisionedKeyCount; - -/** - * @brief Global array of pre-provisioned key IDs - * - * During KeyStore_PSA_init(), the pre-provisioned key memory is checked for the existence of pre-provisioned keys. If - * they exist, pre-provisioned key memory is parsed to copy the necessary information in the the preProvisionedKeyIds - * including the key ID, algorithm, usage, exportability, address of the plaintext material, and the key length. This - * array is later used to check the availability of a key in pre-provisioned key memory when an application or requests - * for the key using key ID. - */ -static KeyStore_PSA_preProvisionedKeyIDs preProvisionedKeyIds[KEYSTORE_PSA_MAX_PREPROVISIONED_KEYS]; - /* Flag to prevent multiple initialization of KeyStore driver */ static bool isKeyStoreInitialized = false; -/** - * @brief Obtain pre-provisioned KeyStore_PSA_KeyFileId if any. - * - * This function is called by KeyStore_PSA_init() to parse the pre-provisioned key memory - * area and identify available key IDs and store the key IDs and other information along - * with the starting address of the key in pre-provisioned key memory in a global array. The application - * must provide the necessary key ID and owner information from this array to retrieve the key. - * - * \retval #KEYSTORE_PSA_STATUS_SUCCESS - * Success. - * \retval #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST - * No pre-provisioned key available in pre-provisioned key memory - */ -/* - * ======== KeyStore_PSA_getPreProvisionedKeyIDs ======== - */ -static int_fast16_t KeyStore_PSA_getPreProvisionedKeyIDs(void) -{ - uint8_t *currentKey; - uint32_t keySize; - uint32_t lifetime; - uint32_t keyLength; - uint32_t end; - - currentKey = (uint8_t *)(KEYSTORE_PSA_PREPROVISIONED_AREA_ADDR); - - /* Check for magic header to identify if pre-provisioned keys were programmed */ - if (memcmp(currentKey, - KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER, - KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH) != 0) - { - return KEYSTORE_PSA_STATUS_DOES_NOT_EXIST; - } - - /* Rest keySize (size of each key) and preProvisionedKeyCount (length of the pre-provisioned key array) */ - keySize = 0; - preProvisionedKeyCount = 0; - - /* - * Parse the pre-provisioned key memory until reaching the final end pattern for PP keys or empty pattern which - * allows further addition of pre-provisioned keys to create a local copy of the key ID, size, and starting address - * to be used by the application - */ - do - { - /* Skip the Magic Header */ - keySize = KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH; - - /* Copy Lifetime */ - memcpy(&lifetime, (currentKey + keySize), MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, lifetime)); - keySize += MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, lifetime); - - if (lifetime == KEYSTORE_PSA_PRE_PROVISIONED_KEY_VALID_LIFETIME) - { - /* Copy the Key_file_id_t */ - memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].id), - (currentKey + keySize), - sizeof(KeyStore_PSA_KeyFileId)); - keySize += sizeof(KeyStore_PSA_KeyFileId); - - /* Copy the export flag */ - memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].export), - (currentKey + keySize), - sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG)); - keySize += sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG); - - /* Copy the Algorithm */ - memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].alg), - (currentKey + keySize), - sizeof(KeyStore_PSA_Algorithm)); - keySize += sizeof(KeyStore_PSA_Algorithm); - - /* Copy the Usage */ - memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].usage), - (currentKey + keySize), - sizeof(KeyStore_PSA_KeyUsage)); - keySize += sizeof(KeyStore_PSA_KeyUsage); - - /* Copy the key length */ - memcpy(&(preProvisionedKeyIds[preProvisionedKeyCount].keyLength), - (currentKey + keySize), - MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength)); - keySize += MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength); - - /* Copy the starting addr of pre-provisioned key psa_key */ - preProvisionedKeyIds[preProvisionedKeyCount].addr = currentKey + keySize; - - keySize += (preProvisionedKeyIds[preProvisionedKeyCount].keyLength + - MEMBER_SIZE(KeyStore_preProvisionedKeyStorageFormat, fletcher)); - - /* Increment the count of PP keys available in pre-provisioned key memory */ - preProvisionedKeyCount++; - } - else - { - /* Skip over the invalid key */ - keySize += (sizeof(KeyStore_PSA_KeyFileId) + sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG) + - sizeof(KeyStore_PSA_Algorithm) + sizeof(KeyStore_PSA_KeyUsage)); - - memcpy(&keyLength, (currentKey + keySize), MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength)); - - keySize += (MEMBER_SIZE(KeyStore_PreProvisionedKeyMetaData, keyLength) + keyLength + - MEMBER_SIZE(KeyStore_preProvisionedKeyStorageFormat, fletcher)); - } - - /* Set to pre-provisioned key address tracking to the next PP key, if available, after the key and checksum */ - currentKey += keySize; - - /* Reset pre-provisioned key size tracking for the next PP key */ - keySize = 0; - - memcpy(&end, currentKey, sizeof(end)); - } while ((end != KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END) && (end != KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY)); - - return KEYSTORE_PSA_STATUS_SUCCESS; -} - -/** - * @brief Compute Fletcher Checksum-32 - * - * \param[in] addr - Starting address of data used for checksum - * \param[in] len - Length of data that requires checksum - * \param[out] checksum - Computed 32-bit checksum - */ -/* - * ======== KeyStore_PSA_computeFletcherChecksum ======== - */ -static uint32_t KeyStore_PSA_computeFletcherChecksum(uint8_t *addr, uint32_t len) -{ - uint32_t sum1, sum2, i, checksum; - uint16_t mod; - mod = (2 ^ (FLETCHER_CHECKSUM_ALGORITHM / 2)) - 1; - - /* Initialize both sums to zero*/ - sum1 = 0; - sum2 = 0; - for (i = 0; i < len; i++) - { - sum1 += *addr++; - if (sum1 >= mod) - { - sum1 -= mod; - } - sum2 += sum1; - if (sum2 >= mod) - { - sum2 -= mod; - } - } - checksum = sum2 << mod | sum1; - - return checksum; -} - -/** - * @brief Verify the fletcher checksum of the give pre-provisioned key ID - * - * \param[in] preProvisionedKey - Structure to the pre-provisioned key ID to be verified - * - * \retval #KEYSTORE_PSA_STATUS_SUCCESS - * Successfully verified checksum - * \retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED - * Fletched checksum verification failed - * \retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY - * Insufficient memory in heap to create a copy of pre-provisioned key - * from persistent memory to compute checksum - */ -/* - * ======== KeyStore_PSA_verifyFletcherChecksum ======== - */ -static int_fast16_t KeyStore_PSA_verifyFletcherChecksum(KeyStore_PSA_preProvisionedKeyIDs *preProvisionedKey) -{ - uint32_t expectedChecksum, computedChecksum; - int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - - uint8_t keySize = KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE + preProvisionedKey->keyLength; - - memcpy(&expectedChecksum, (preProvisionedKey->addr + preProvisionedKey->keyLength), sizeof(expectedChecksum)); - - computedChecksum = KeyStore_PSA_computeFletcherChecksum(preProvisionedKey->addr - - (KEYSTORE_PRE_PROVISIONED_KEY_METADATA_SIZE), - keySize); - - if (expectedChecksum == computedChecksum) - { - status = KEYSTORE_PSA_STATUS_SUCCESS; - } - else - { - status = KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED; - } - - return status; -} - -/* Copy the pre-provisioned key from persistent memory to the provided data buffer and set the dataLength */ -/* - * ======== KeyStore_PSA_copyKeyDataFromFlash ======== - */ -static int_fast16_t KeyStore_PSA_copyKeyDataFromFlash(KeyStore_PSA_preProvisionedKeyIDs *preProvisionedKey, - uint8_t *data, - size_t dataSize, - size_t *dataLength) -{ - int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - - if (dataSize == preProvisionedKey->keyLength) - { - memcpy(data, preProvisionedKey->addr, preProvisionedKey->keyLength); - *dataLength = preProvisionedKey->keyLength; - status = KEYSTORE_PSA_STATUS_SUCCESS; - } - else - { - status = KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL; - } - return status; -} - -/* - * Copy the pre-provisioned key and its length in the provided buffers after verifying fletcher checksum and key - * properties - */ -/* - * ======== KeyStore_PSA_fetchPreProvisionedData ======== - */ -static int_fast16_t KeyStore_PSA_fetchPreProvisionedData(KeyStore_PSA_KeyFileId key, - uint8_t *data, - size_t dataSize, - size_t *dataLength, - bool export, - KeyStore_PSA_Algorithm alg, - KeyStore_PSA_KeyUsage usage) -{ - int_fast16_t status = KEYSTORE_PSA_STATUS_DOES_NOT_EXIST; - - if (preProvisionedKeyCount != KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY) - { - /* Check if Key ID matches pre-provisioned key */ - uint32_t i; - for (i = 0; i <= preProvisionedKeyCount; i++) - { - if ((key.MBEDTLS_PRIVATE(owner) == preProvisionedKeyIds[i].id.MBEDTLS_PRIVATE(owner)) && - (key.MBEDTLS_PRIVATE(key_id) == preProvisionedKeyIds[i].id.MBEDTLS_PRIVATE(key_id))) - { - status = KeyStore_PSA_verifyFletcherChecksum(&preProvisionedKeyIds[i]); - if (status == KEYSTORE_PSA_STATUS_SUCCESS) - { - if (export) - { - if (preProvisionedKeyIds[i].export == KEYSTORE_PSA_PRE_PROVISIONED_KEY_EXPORT_FLAG) - { - status = KeyStore_PSA_copyKeyDataFromFlash(&preProvisionedKeyIds[i], - data, - dataSize, - dataLength); - } - else - { - status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; - } - } - else - { - if (preProvisionedKeyIds->alg == alg && preProvisionedKeyIds->usage == usage) - { - status = KeyStore_PSA_copyKeyDataFromFlash(&preProvisionedKeyIds[i], - data, - dataSize, - dataLength); - } - else - { - status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; - } - } - } - - /* Exit for loop since matching key ID & owner was found */ - break; - } - } - } - - return status; -} - /*! * @cond NODOC * @brief Non-public functions required by other drivers @@ -487,14 +181,6 @@ int_fast16_t KeyStore_PSA_init(void) KeyStore_semaphoreObject.isInitialized = true; } - status = KeyStore_PSA_getPreProvisionedKeyIDs(); - - if (status == KEYSTORE_PSA_STATUS_DOES_NOT_EXIST) - { - preProvisionedKeyCount = KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY; - status = KEYSTORE_PSA_STATUS_SUCCESS; - } - isKeyStoreInitialized = true; } else @@ -517,10 +203,6 @@ int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, { psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; psa_key_slot_t *slot; - uint32_t keyID; - - /* Create a copy of the key ID */ - SET_KEY_ID(keyID, key); if (!KeyStore_acquireLock()) { @@ -529,13 +211,6 @@ int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, } KeyStore_semaphoreObject.isAcquired = true; - /* Check if Key is in pre-provisioned key memory before checking in ITS */ - if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) - { - status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, false, alg, usage); - return KeyStore_cleanUp(status); - } - /* * Reject a zero-length output buffer now, since this can never be a * valid key representation. This way we know that data must be a valid @@ -585,20 +260,6 @@ int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, { int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - /* Check if the persistent keyID is already used by the pre-provisioned keys or less than the min persistent key IDs - */ - if (attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) == KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT) - { -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - if (key->MBEDTLS_PRIVATE(key_id) < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) -#else - if (*key < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN) -#endif - { - return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; - } - } - if (!KeyStore_acquireLock()) { status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; @@ -617,10 +278,6 @@ int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength) { int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - uint32_t keyID; - - /* Create a copy of the key ID */ - SET_KEY_ID(keyID, key); if (!KeyStore_acquireLock()) { @@ -629,13 +286,6 @@ int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, s } KeyStore_semaphoreObject.isAcquired = true; - /* Check if Key is in pre-provisioned key memory before checking in ITS */ - if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) - { - status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, true, 0, 0); - return KeyStore_cleanUp(status); - } - status = psa_export_key(key, data, dataSize, dataLength); return KeyStore_cleanUp(status); @@ -650,10 +300,6 @@ int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, size_t *dataLength) { int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - uint32_t keyID; - - /* Create a copy of the key ID */ - SET_KEY_ID(keyID, key); if (!KeyStore_acquireLock()) { @@ -662,166 +308,18 @@ int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, } KeyStore_semaphoreObject.isAcquired = true; - /* Check if Key is in pre-provisioned key memory before checking in ITS */ - if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) - { - status = KeyStore_PSA_fetchPreProvisionedData(key, data, dataSize, dataLength, true, 0, 0); - return KeyStore_cleanUp(status); - } - status = psa_export_public_key(key, data, dataSize, dataLength); return KeyStore_cleanUp(status); } -/* - * ======== KeyStore_PSA_importCertificate ======== - */ -int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, - KeyStore_PSA_KeyFileId *key, - uint8_t *data, - size_t dataLength) -{ - int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - - uint32_t keyID; - KeyStore_PSA_KeyFileId certificateID; -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - keyID = key->MBEDTLS_PRIVATE(key_id); -#else - keyID = *key; -#endif - - /* Compute certificate ID from associated public key ID */ - GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); - - /* - * Only support persistent certificates with TF-M 1.1 - */ - if (attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) != KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT) - { - status = KEYSTORE_PSA_STATUS_INVALID_ARGUMENT; - return status; - } - - /* Check if key ID is within the allowed persistent key ID range for keys with associated certificates */ - if ((keyID > KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX) || (keyID < KEYSTORE_PSA_KEY_ID_PERSISTENT_USER_MIN)) - { - return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; - } - - /* Check if a certificate already exists with the same ID in pre-provisioned keys storage */ - if (((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX))) - { - return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; - } - - /* Compute certificate ID from associated public key ID */ -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = key->MBEDTLS_PRIVATE(key_id) | - KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT; - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = key->MBEDTLS_PRIVATE(owner); -#else - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = *key | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT; -#endif - - if (!KeyStore_acquireLock()) - { - status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; - return status; - } - KeyStore_semaphoreObject.isAcquired = true; - - /* - * Import certificate into key slot, this will return - * KEYSTORE_PSA_STATUS_ALREADY_EXISTS if a certificate is associated with - * the provided keyID. - */ - status = psa_import_key(attributes, data, dataLength, &certificateID); - - return KeyStore_cleanUp(status); -} - -/* - * ======== KeyStore_PSA_exportCertificate ======== - */ -int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, - uint8_t *data, - size_t dataSize, - size_t *dataLength) -{ - int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - KeyStore_PSA_KeyFileId certificateID; - uint32_t keyID; - - /* Create a copy of the key ID */ - SET_KEY_ID(keyID, key); - - if (keyID > KEYSTORE_PSA_KEY_ID_WITH_CERTIFICATE_USER_MAX) - { - return KEYSTORE_PSA_STATUS_INVALID_KEY_ID; - } - - /* Compute certificate ID from associated public key ID */ - GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); - - /* Check if Certificate is in pre-provisioned key memory before checking in ITS */ - if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) - { - status = KeyStore_PSA_fetchPreProvisionedData(certificateID, data, dataSize, dataLength, true, 0, 0); - return KeyStore_cleanUp(status); - } - - if (!KeyStore_acquireLock()) - { - status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; - return status; - } - KeyStore_semaphoreObject.isAcquired = true; - - status = psa_export_key(certificateID, data, dataSize, dataLength); - - return KeyStore_cleanUp(status); -} - -/* - * ======== KeyStore_PSA_destroyCertificate ======== - */ -int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key) -{ - int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - uint32_t keyID; - - /* Create a copy of the key ID */ - SET_KEY_ID(keyID, key); - - if (keyID >= KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MIN && - keyID <= KEYSTORE_PSA_PRE_PROVISIONED_CERTIFICATE_ID_MAX) - { - return KEYSTORE_PSA_STATUS_NOT_SUPPORTED; - } - - if (!KeyStore_acquireLock()) - { - status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; - return status; - } - KeyStore_semaphoreObject.isAcquired = true; - - status = psa_destroy_key(key); - - return KeyStore_cleanUp(status); -} - /* * ======== KeyStore_PSA_destroyKey ======== */ int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) { int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - KeyStore_PSA_KeyFileId certificateID; volatile uint32_t keyID; - KeyStore_PSA_KeyHandle handle; /* Create a copy of the key ID */ SET_KEY_ID(keyID, key); @@ -838,28 +336,6 @@ int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) } KeyStore_semaphoreObject.isAcquired = true; - /* Only check for associated certificates for persistent key IDs */ - if (!(psa_key_id_is_volatile(keyID))) - { - /* Check that there is no associated certificate with the given keyID */ - /* Compute certificate ID from associated public key ID */ - GET_KEY_ID(certificateID, keyID | KEYSTORE_PSA_KEY_ID_CERTIFICATE_BIT); - - /* Attempt to open certificateID, if it exists */ - status = psa_open_key(certificateID, &handle); - - if (status == KEYSTORE_PSA_STATUS_SUCCESS) - { - /* Cannot delete keys with associated certificates, the application must first delete the certificate */ - status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; - - /* Decrement lock counter on certificate slot */ - (void)psa_close_key(handle); - - return KeyStore_cleanUp(status); - } - } - status = psa_destroy_key(key); return KeyStore_cleanUp(status); diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h index 98cc7864..2fe16705 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated + * Copyright (c) 2022-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -64,7 +64,7 @@ extern "C" { /** KeyStore driver semaphore used to synchronize accesses to the keyStore * * isAcquired: used by openKey() and purgeKey() to check if the KeyStore semaphore is acquired by - * other KeyStore functions before opening and closing key handles passed to mbedcrypto functions. + * other KeyStore functions before opening and closing key handles passed to mbedTLS functions. */ typedef struct { diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c index 6768f83d..889e53b5 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -79,17 +79,6 @@ static int_fast16_t KeyStore_PSA_exportCommon(KeyStore_PSA_KeyFileId key, return ret; } -/* - * ======== KeyStore_PSA_exportCertificate ======== - */ -int_fast16_t KeyStore_PSA_exportCertificate(KeyStore_PSA_KeyFileId key, - uint8_t *data, - size_t dataSize, - size_t *dataLength) -{ - return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE); -} - /* * ======== KeyStore_PSA_exportPublicKey ======== */ @@ -114,7 +103,7 @@ int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, s */ static int_fast16_t KeyStore_PSA_destroyCommon(KeyStore_PSA_KeyFileId key, int32_t type) { - KeyStore_s_DestroyPurgeKeyCertificateMsg destroyCommonMsg; + KeyStore_s_DestroyPurgeKeyMsg destroyCommonMsg; int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; destroyCommonMsg.key = key; @@ -144,48 +133,6 @@ int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY); } -/* - * ======== KeyStore_PSA_destroyCertificate ======== - */ -int_fast16_t KeyStore_PSA_destroyCertificate(KeyStore_PSA_KeyFileId key) -{ - return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE); -} - -/* - * ======== KeyStore_PSA_importCertificate ======== - */ -int_fast16_t KeyStore_PSA_importCertificate(KeyStore_PSA_KeyAttributes *attributes, - KeyStore_PSA_KeyFileId *key, - uint8_t *data, - size_t dataLength) - -{ - KeyStore_s_ImportCertificateMsg importCertificateMsg; - int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; - - importCertificateMsg.attributes = &attributes->client; - importCertificateMsg.key = key; - importCertificateMsg.data = data; - importCertificateMsg.dataLength = dataLength; - - invecs[0].base = &importCertificateMsg; - invecs[0].len = sizeof(importCertificateMsg); - - outvecs[0].base = &ret; - outvecs[0].len = sizeof(ret); - - /* - * PSA call to secure driver: - * - * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and - * will only be updated if the PSA call is successful. - */ - (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE, invecs, outvecs); - - return ret; -} - /* * ======== KeyStore_PSA_importKey ======== */ diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c index 25a7fc83..c77d8cc3 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include #include @@ -231,60 +231,11 @@ psa_status_t KeyStore_s_importKey(psa_msg_t *msg) } /* - * ======== KeyStore_s_importCertificate ======== + * ======== KeyStore_s_destroyPurgeKey ======== */ -psa_status_t KeyStore_s_importCertificate(psa_msg_t *msg) +psa_status_t KeyStore_s_destroyPurgeKey(psa_msg_t *msg, int32_t msgType) { - KeyStore_s_ImportCertificateMsg importCertificateMsg; - int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; - KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; - KeyStore_PSA_KeyFileId keyID; - - if ((msg->in_size[0] != sizeof(importCertificateMsg)) || (msg->out_size[0] != sizeof(ret))) - { - return PSA_ERROR_PROGRAMMER_ERROR; - } - - psa_read(msg->handle, 0, &importCertificateMsg, sizeof(importCertificateMsg)); - - if (TFM_CLIENT_ID_IS_NS(msg->client_id)) - { - /* Validate input address range */ - if ((cmse_has_unpriv_nonsecure_rw_access(importCertificateMsg.key, sizeof(KeyStore_PSA_KeyFileId)) == NULL) || - (cmse_has_unpriv_nonsecure_read_access(importCertificateMsg.attributes, - sizeof(KeyStore_PSA_KeyAttributes)) == NULL) || - (cmse_has_unpriv_nonsecure_read_access(importCertificateMsg.data, importCertificateMsg.dataLength) == NULL)) - { - return PSA_ERROR_PROGRAMMER_ERROR; - } - } - - /* Copy keyID from application for certificates */ - KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, importCertificateMsg.key); - - ret = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)importCertificateMsg.attributes, - msg->client_id, - &keyAttributes); - - if (ret == PSA_SUCCESS) - { - ret = KeyStore_PSA_importCertificate(&keyAttributes, - &keyID, - importCertificateMsg.data, - importCertificateMsg.dataLength); - } - - psa_write(msg->handle, 0, &ret, sizeof(ret)); - - return PSA_SUCCESS; -} - -/* - * ======== KeyStore_s_destroyCertificateKey ======== - */ -psa_status_t KeyStore_s_destroyCertificateKey(psa_msg_t *msg, int32_t msgType) -{ - KeyStore_s_DestroyPurgeKeyCertificateMsg destroyMsg; + KeyStore_s_DestroyPurgeKeyMsg destroyMsg; int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; KeyStore_PSA_KeyFileId keyID; @@ -297,11 +248,7 @@ psa_status_t KeyStore_s_destroyCertificateKey(psa_msg_t *msg, int32_t msgType) KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &destroyMsg.key); - if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE) - { - ret = KeyStore_PSA_destroyCertificate(keyID); - } - else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY) + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY) { ret = KeyStore_PSA_destroyKey(keyID); } @@ -316,9 +263,9 @@ psa_status_t KeyStore_s_destroyCertificateKey(psa_msg_t *msg, int32_t msgType) } /* - * ======== KeyStore_s_exportCertificateKey ======== + * ======== KeyStore_s_exportKey ======== */ -psa_status_t KeyStore_s_exportCertificateKey(psa_msg_t *msg, int32_t msgType) +psa_status_t KeyStore_s_exportKey(psa_msg_t *msg, int32_t msgType) { KeyStore_s_ExportMsg exportMsg; int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; @@ -342,11 +289,7 @@ psa_status_t KeyStore_s_exportCertificateKey(psa_msg_t *msg, int32_t msgType) KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &exportMsg.key); - if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE) - { - ret = KeyStore_PSA_exportCertificate(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); - } - else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY) + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY) { ret = KeyStore_PSA_exportKey(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); } @@ -435,19 +378,14 @@ psa_status_t KeyStore_s_handlePsaMsg(psa_msg_t *msg) status = KeyStore_s_getKey(msg); break; /* Fall through for exporting */ - case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE: case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY: case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY: - status = KeyStore_s_exportCertificateKey(msg, msg->type); + status = KeyStore_s_exportKey(msg, msg->type); break; /* Fall through for destroying */ - case KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE: case KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY: case KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY: - status = KeyStore_s_destroyCertificateKey(msg, msg->type); - break; - case KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE: - status = KeyStore_s_importCertificate(msg); + status = KeyStore_s_destroyPurgeKey(msg, msg->type); break; case KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY: status = KeyStore_s_importKey(msg); diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h index 1f063910..23d5f822 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -60,16 +60,13 @@ */ #define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY KEYSTORE_PSA_S_MSG_TYPE(0U) #define KEYSTORE_PSA_S_MSG_TYPE_GENERATE_KEY KEYSTORE_PSA_S_MSG_TYPE(1U) -#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(2U) -#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY KEYSTORE_PSA_S_MSG_TYPE(3U) -#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(4U) -#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(5U) -#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY KEYSTORE_PSA_S_MSG_TYPE(6U) -#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_CERTIFICATE KEYSTORE_PSA_S_MSG_TYPE(7U) -#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(8U) -#define KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY KEYSTORE_PSA_S_MSG_TYPE(9U) -#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(10U) -#define KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(11U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY KEYSTORE_PSA_S_MSG_TYPE(2U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(3U) +#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY KEYSTORE_PSA_S_MSG_TYPE(4U) +#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(5U) +#define KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY KEYSTORE_PSA_S_MSG_TYPE(6U) +#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(7U) +#define KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(8U) /* * ============ KeyStore driver Secure Message Structs ========= @@ -96,7 +93,7 @@ typedef struct KeyStore_PSA_KeyFileId *key; } KeyStore_s_GenerateKeyMsg; -/* Msg for KeyStore_PSA_exportKey(), KeyStore_PSA_exportCertificate(), and KeyStore_PSA_exportPublicKey() */ +/* Msg for KeyStore_PSA_exportKey() and KeyStore_PSA_exportPublicKey() */ typedef struct { uint32_t key; @@ -105,14 +102,6 @@ typedef struct size_t *dataLength; } KeyStore_s_ExportMsg; -typedef struct -{ - struct psa_client_key_attributes_s *attributes; - uint32_t *key; - uint8_t *data; - size_t dataLength; -} KeyStore_s_ImportCertificateMsg; - typedef struct { struct psa_client_key_attributes_s *attributes; @@ -121,11 +110,11 @@ typedef struct uint32_t *key; } KeyStore_s_ImportKeyMsg; -/* Msg for KeyStore_PSA_destroyKey(), KeyStore_PSA_destroyCertificate(), and KeyStore_PSA_purgeKey() */ +/* Msg for KeyStore_PSA_destroyKey() and KeyStore_PSA_purgeKey() */ typedef struct { uint32_t key; -} KeyStore_s_DestroyPurgeKeyCertificateMsg; +} KeyStore_s_DestroyPurgeKeyMsg; typedef struct { diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c index f1acde89..44ae1801 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c @@ -112,3 +112,19 @@ int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length return CryptoKey_STATUS_SUCCESS; } + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/* + * ======== CryptoKeyPlaintext_initKey ======== + */ +int_fast16_t CryptoKeyPlaintextHSM_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength) +{ + keyHandle->encoding = CryptoKey_PLAINTEXT_HSM; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +#endif \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h index 3ff5c9e9..e153981c 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Texas Instruments Incorporated + * Copyright (c) 2017-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,6 +29,7 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + /** ============================================================================ * @file CryptoKeyPlaintext.h * @@ -38,7 +39,7 @@ * This file contains the APIs to initialize and access plaintext CryptoKeys. * Plaintext CryptoKeys point to keying material stored in flash or RAM and * are not subject to enforced usage restrictions. That only means that calling - * a function that requires an assymmetric public key with a symmetric key will + * a function that requires an asymmetric public key with a symmetric key will * not return an error. It will likely not yield the desired results. * * # Usage # @@ -164,6 +165,22 @@ int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *lengt */ int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length); +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_PLAINTEXT_HSM + * and ready for use + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintextHSM_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); +#endif + #ifdef __cplusplus } #endif diff --git a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h index fcd5f7b8..5439c4dc 100644 --- a/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h +++ b/simplelink_lpf3/source/ti/drivers/cryptoutils/ecc/ECCParams.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Texas Instruments Incorporated + * Copyright (c) 2017-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -46,6 +46,10 @@ #include #include +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#endif + #ifdef __cplusplus extern "C" { #endif @@ -178,6 +182,13 @@ typedef struct ECCParams_ns_CurveParams /* Short Weierstrass curves */ +/*! + * + * @brief The NISTP192 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP192; + /*! * * @brief The NISTP224 curve in short Weierstrass form. @@ -406,6 +417,9 @@ extern const ECC_NISTP224_Param ECC_NISTP224_b_mont; /* Octet string format requires an extra byte at the start of the public key */ #define OCTET_STRING_OFFSET 1 + /* Octet string format requires this value in the first byte of the public key */ + #define OCTET_STRING_PREFIX 0x04 + /* Length of offset in bytes */ #define ECC_LENGTH_OFFSET_BYTES 4 @@ -421,7 +435,8 @@ typedef union uint8_t byte[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES]; } ECC_Param; -#endif /* DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 */ +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) \ + */ /*! * @brief Length of Curve25519 curve parameters in bytes diff --git a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c index f72d67e0..6c491eed 100644 --- a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c +++ b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.c @@ -52,7 +52,7 @@ static bool isOpen = false; static Power_NotifyObj postNotify; /* - * ======== UDMACC26XX_init ======== + * ======== UDMALPF3_init ======== * */ void UDMALPF3_init(void) @@ -77,8 +77,8 @@ void UDMALPF3_init(void) } /* - * ======== UDMACC26XX_initHw ======== - * This functions initializes the UDMACC26XX hardware module. + * ======== UDMALPF3_initHw ======== + * This functions initializes the UDMALPF3 hardware module. * */ static void UDMALPF3_initHw(void) @@ -108,7 +108,7 @@ static int UDMALPF3_postNotifyFxn(unsigned int eventType, uintptr_t eventArg, ui /* Power up and enable clocks for uDMA. */ Power_setDependency(PowerLPF3_PERIPH_DMA); - /* initialize the UDMACC26XX hardware */ + /* initialize the UDMALPF3 hardware */ UDMALPF3_initHw(); /* Disable clock on the DMA peripheral */ diff --git a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h index 43f68ce6..44389dab 100644 --- a/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h +++ b/simplelink_lpf3/source/ti/drivers/dma/UDMALPF3.h @@ -152,7 +152,7 @@ extern "C" { */ typedef struct { - uint32_t CtrlBaseAddr; /*!< Base adddress for UDMALPF3 control table*/ + uint32_t CtrlBaseAddr; /*!< Base address for UDMALPF3 control table */ } UDMALPF3_Config; /* Externs from ti_drivers_config.c */ diff --git a/simplelink_lpf3/source/ti/drivers/gpio/GPIOLPF3.h b/simplelink_lpf3/source/ti/drivers/gpio/GPIOLPF3.h new file mode 100644 index 00000000..ac4ffc0a --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/gpio/GPIOLPF3.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file GPIOLPF3.h + * + * @brief GPIO driver implementation for Low Power F3 devices + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref GPIO.h for a complete description of the GPIO + * driver APIs provided and examples of their use. + * + * The definitions in this file should not be used directly. All GPIO_CFG + * macros should be used as-is from GPIO.h. + * + * There are no additional configuration values or platform-specific + * functions for GPIOLPF3. + */ + +#ifndef ti_drivers_GPIOLPF3__include +#define ti_drivers_GPIOLPF3__include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ioc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* Do not configure this pin. */ +#define GPIO_CFG_DO_NOT_CONFIG_INTERNAL 0x80000000 + +/* Re-map IOC PORTCFG defines from hw_ioc.h to GPIO defines*/ +#define GPIO_MUX_PORTCFG_PFUNC7 IOC_IOC3_PORTCFG_DTB +#define GPIO_MUX_PORTCFG_PFUNC6 IOC_IOC3_PORTCFG_ANA +#define GPIO_MUX_PORTCFG_PFUNC5 IOC_IOC3_PORTCFG_PFUNC5 +#define GPIO_MUX_PORTCFG_PFUNC4 IOC_IOC3_PORTCFG_PFUNC4 +#define GPIO_MUX_PORTCFG_PFUNC3 IOC_IOC3_PORTCFG_PFUNC3 +#define GPIO_MUX_PORTCFG_PFUNC2 IOC_IOC3_PORTCFG_PFUNC2 +#define GPIO_MUX_PORTCFG_PFUNC1 IOC_IOC3_PORTCFG_PFUNC1 +#define GPIO_MUX_GPIO_INTERNAL IOC_IOC3_PORTCFG_BASE + +/* We don't define this value on purpose - any unsupported values will cause a + * compile-time error. If your compiler tells you that this macro is missing, + * you are trying to use an unsupported option. + * + * See below for which options are unsupported. + */ +#undef GPIOLPF3_CFG_OPTION_NOT_SUPPORTED + +/* Most configuration values are directly mapped to fields in the IOCn + * registers, but the mux bits are reserved for configuration options that + * cannot be directly mapped to the IOCn registers. The define below is the + * mask used by the GPIO driver to mask off the non-IOC configuration values. + */ +#define GPIOLPF3_CFG_IOC_M 0xFFFFFFF8 + +/* Low and high value interrupts are not available on Low Power F3 devices */ +#define GPIO_CFG_INT_LOW_INTERNAL GPIOLPF3_CFG_OPTION_NOT_SUPPORTED +#define GPIO_CFG_INT_HIGH_INTERNAL GPIOLPF3_CFG_OPTION_NOT_SUPPORTED + +/* General options */ +#define GPIO_CFG_NO_DIR_INTERNAL (IOC_IOC3_IOMODE_NORMAL | GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL) +/* Hysteresis is enabled by default for all input pins due to hardware changes on these devices. + * This may impact pin response by 1-2ns, but creates significantly more stable environments for + * high-speed use cases like SPI. + */ +#define GPIO_CFG_INPUT_INTERNAL \ + (IOC_IOC3_IOMODE_NORMAL | IOC_IOC3_INPEN | IOC_IOC3_WUENSB | IOC_IOC3_HYSTEN | GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL) +#define GPIO_CFG_OUTPUT_INTERNAL (IOC_IOC3_IOMODE_NORMAL | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) +#define GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL \ + (IOC_IOC3_IOMODE_OPEND | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) +#define GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL (IOC_IOC3_IOMODE_OPENS | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) + +#define GPIO_CFG_PULL_NONE_INTERNAL IOC_IOC3_PULLCTL_PULL_DIS +#define GPIO_CFG_PULL_UP_INTERNAL IOC_IOC3_PULLCTL_PULL_UP +#define GPIO_CFG_PULL_DOWN_INTERNAL IOC_IOC3_PULLCTL_PULL_DOWN + +#define GPIO_CFG_INT_NONE_INTERNAL IOC_IOC3_EDGEDET_EDGE_DIS +#define GPIO_CFG_INT_FALLING_INTERNAL IOC_IOC3_EDGEDET_EDGE_NEG +#define GPIO_CFG_INT_RISING_INTERNAL IOC_IOC3_EDGEDET_EDGE_POS +#define GPIO_CFG_INT_BOTH_EDGES_INTERNAL IOC_IOC3_EDGEDET_EDGE_BOTH + +/* We can feed this into the low bit of IOMODE, and it can then be ORed with output/input/OD/OS */ +#define GPIO_CFG_INVERT_OFF_INTERNAL 0 +#define GPIO_CFG_INVERT_ON_INTERNAL IOC_IOC3_IOMODE_INVERTED + +#define GPIO_CFG_HYSTERESIS_OFF_INTERNAL 0 +#define GPIO_CFG_HYSTERESIS_ON_INTERNAL IOC_IOC3_HYSTEN + +#define GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL 0 +#define GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL IOC_IOC3_WUCFGSD_WAKE_HIGH +#define GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL IOC_IOC3_WUCFGSD_WAKE_LOW + +/* Slew limits and drive strength are only supported on specific pins: pin 12, pins 16-19, and pin 24 */ +#define GPIO_CFG_SLEW_NORMAL_INTERNAL IOC_IOC17_SLEWRED_NORMAL +#define GPIO_CFG_SLEW_REDUCED_INTERNAL IOC_IOC17_SLEWRED_REDUCED + +#define GPIO_CFG_DRVSTR_LOW_INTERNAL IOC_IOC17_IOCURR_CUR_2MA +#define GPIO_CFG_DRVSTR_MED_INTERNAL IOC_IOC17_IOCURR_CUR_4MA +#define GPIO_CFG_DRVSTR_HIGH_INTERNAL IOC_IOC17_IOCURR_CUR_8MA + +/* Configuration values stored in mux bits. Any configuration options not + * directly handled by IOC need to be stored inside the mux bits (lowest 3 bits + * on Low Power F3 devices). These are masked out by GPIO_init(), + * GPIO_setConfig(), GPIO_setConfigAndMux() and GPIO_getConfig() using + * GPIOLPF3_CFG_IOC_M. + */ + +/* Default output value */ +#define GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL 0x1 +#define GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL 0 + +/* Whether GPIO hardware should have the output enable bit set for this pin */ +#define GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL 0x2 +#define GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL 0 + +/* Interrupt enable is in the GPIO module */ +#define GPIO_CFG_INT_ENABLE_INTERNAL 0x4 +#define GPIO_CFG_INT_DISABLE_INTERNAL 0 + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIOCC26XX__include */ \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c index 47f5fa0e..be7fb780 100644 --- a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c +++ b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -41,9 +41,12 @@ #include #include +#include #include +#include + #include #include DeviceFamily_constructPath(inc/hw_types.h) #include DeviceFamily_constructPath(inc/hw_memmap.h) @@ -59,6 +62,7 @@ #include DeviceFamily_constructPath(inc/hw_sys0.h) #include DeviceFamily_constructPath(inc/hw_ioc.h) #include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/ckmd.h) #include DeviceFamily_constructPath(driverlib/hapi.h) #include DeviceFamily_constructPath(driverlib/gpio.h) #include DeviceFamily_constructPath(driverlib/lrfd.h) @@ -79,10 +83,22 @@ static void PowerCC23X0_hfxtCompensateFxn(int16_t currentTemperature, static uint32_t PowerCC23X0_temperatureToRatio(int16_t temperature); static void PowerCC23X0_updateHFXTRatio(uint32_t ratio); +static void PowerCC23X0_hfxtAmpsettledTimeout(uintptr_t arg); +static void PowerCC23X0_initialHfxtAmpCompClockCb(uintptr_t searchDone); +static void PowerCC23X0_forceHfxtFsmToRamp1(void); +static void PowerCC23X0_startContHfxtAmpMeasurements(void); +static void PowerCC23X0_stopContHfxtAmpMeasurements(void); +static uint32_t PowerCC23X0_getHfxtAmpMeasurement(void); + /* Externs */ extern const PowerCC23X0_Config PowerCC23X0_config; extern const uint_least8_t GPIO_pinLowerBound; extern const uint_least8_t GPIO_pinUpperBound; +extern const uint_least8_t PowerLPF3_extlfPin; +extern const uint_least8_t PowerLPF3_extlfPinMux; + +/* Macro for weak definition of the Power Log module */ +Log_MODULE_DEFINE_WEAK(LogModule_Power, {0}); /* Function Macros */ @@ -101,6 +117,20 @@ extern const uint_least8_t GPIO_pinUpperBound; #define HFXT_COMP_MAX_TEMP (125) #define HFXT_COMP_MIN_TEMP (-40) +/* Timeout value used to detect if HFXT FSM is stuck in RAMP0 state */ +#define HFXT_AMP_COMP_START_TIMEOUT_US 500 + +/* Time to wait after changing HFXTTARG.IREF and measuring the resulting + * HFXT amplitude + */ +#define HFXT_AMP_COMP_MEASUREMENT_US 1000 + +/* The limits for the allowed target IREF values to be passed to + * CKMDSetTargetIrefTrim() + */ +#define HFXT_TARGET_IREF_MAX 8 +#define HFXT_TARGET_IREF_MIN 3 + /* Type definitions */ /*! Type used for passing configuration information to HFXT temperature @@ -170,6 +200,42 @@ static List_List notifyList; /* Interrupt for handling clock switching */ static HwiP_Struct ckmHwi; +/* Function to be called to start the initial HFXT Amplitude compensation on the + * next AMPSETTLED interrupt. + * Will be NULL if initial compensation should not be + * be performed. I.e. if it has already been performed or if it is not enabled. + */ +static PowerLPF3_StartInitialHfxtAmpCompFxn startInitialHfxtAmpCompFxn = NULL; + +/* Clock object used by HFXT amplitude compensation. It is reused for multiple + * purposes. The callback function of the ClockP object will be changed + * dynamically, depending on the use case. The different use cases are described + * below: + * - Currently waiting for the AMPSETTLED interrupt, after starting HFXT + * - Callback function: PowerCC23X0_hfxtAmpsettledTimeout + * - Used for timeout to detect if HFXT FSM gets stuck in RAMP0 state + * - Currently performing the initial HFXT amplitude compensation, where we are + * doing a full search for the optimal HFXTTARG.IREF value, + * after the AMPSETTLED signal and before the PowerLPF3_HFXT_AVAILABLE + * notification. + * - Callback function: PowerCC23X0_initialHfxtAmpCompClockCb + * - The clock is used to schedule measurements and evaluations of the HFXT + * amplitude. + * - After PowerLPF3_HFXT_AVAILABLE notification: + * - Callback function: NULL + * - Currently not used. Could potentially be used to periodically check if + * amplitude adjustments are needed. + * + * Dynamically changing the callback function is done instead of having a common + * callback function, to be able to only link the functions that are actually + * used. For example, if the initial HFXT amplitude compensation at boot is not + * enabled, then there will be no reference to + * PowerLPF3_startInitialHfxtAmpComp() which is the only place that references + * PowerCC23X0_initialHfxtAmpCompClockCb(), and therefore neither functions + * will be linked in the application. + */ +static ClockP_Struct hfxtAmpCompClock; + /* Non-static Globals */ /* Interrupt for ClockP and Power policy */ @@ -194,6 +260,8 @@ int_fast16_t Power_init() policyFxn = PowerCC23X0_config.policyFxn; + startInitialHfxtAmpCompFxn = PowerCC23X0_config.startInitialHfxtAmpCompFxn; + /* Construct the CKM hwi responsible for oscillator related events. * Since there is no dedicated CKM interrupt line, we need to mux one of * the configurable lines to the CKM. @@ -204,17 +272,19 @@ int_fast16_t Power_init() HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ3SEL) = EVTSVT_CPUIRQ3SEL_PUBID_AON_CKM_COMB; /* Enable a selection of CKM signals as interrupt sources. For now, - * we will stick to LKCLKGOOD and AMPSETTLED since those are related to existing - * notifications. + * we will stick to AMPSETTLED since it is related to existing notification + * and HFXTFAULT and TRACKREFLOSS to be able to handle HFXT clock loss. + * TRACKREFLOSS may occur when entering and exiting fake standby with the + * debugger attached. */ - HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_AMPSETTLED | CKMD_IMASK_HFXTFAULT; + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMSET_AMPSETTLED | CKMD_IMSET_HFXTFAULT | CKMD_IMSET_TRACKREFLOSS; HwiP_enableInterrupt(INT_CPUIRQ3); /* Use RTC channel 0 in compare mode. Channel 1 could be used for other * purposes. */ - HWREG(RTC_BASE + RTC_O_IMSET) = RTC_IMSET_EV0_M; + HWREG(RTC_BASE + RTC_O_IMSET) = RTC_IMSET_EV0_SET; /* Configure RTC to halt when CPU stopped during debug */ HWREG(RTC_BASE + RTC_O_EMU) = RTC_EMU_HALT_STOP; @@ -224,9 +294,38 @@ int_fast16_t Power_init() */ HWREG(SYSTIM_BASE + SYSTIM_O_EMU) = SYSTIM_EMU_HALT_STOP; + /* Disable automatic periodic adjustments of HFXT amplitude. It will instead + * be done in SW. + * With this setting it is not necessary to restart HFXT after changing + * IREF. + */ + HWREG(CKMD_BASE + CKMD_O_AMPCFG1) &= ~CKMD_AMPCFG1_INTERVAL_M; + + /* Set target HFXT IREF to the max value, to ensure it is high enough. + * It will be gradually updated as needed later, as part of the HFXT + * amplitude compensation. + */ + CKMDSetTargetIrefTrim(HFXT_TARGET_IREF_MAX); + + /* Construct HFXT amplitude compensation clock. + * At boot, the clock is used to detect if the HFXT FSM gets stuck in the + * RAMP0 state. + */ + ClockP_construct(&hfxtAmpCompClock, + PowerCC23X0_hfxtAmpsettledTimeout, + HFXT_AMP_COMP_START_TIMEOUT_US / ClockP_getSystemTickPeriod(), + NULL); + /* Start HFXT */ PowerCC23X0_startHFXT(); + /* Start timeout clock. + * Note, interrupts are guaranteed to be disabled during Power_init(), so + * there is no risk of the AMPSETTLED callback stopping the clock before it + * is started. + */ + ClockP_start(&hfxtAmpCompClock); + /* Enable tracking loop with HFXT as reference. This will automatically * calibrate LFOSC against HFXT whenever HFXT is enabled; usually after * waking up from standby. @@ -386,6 +485,10 @@ int_fast16_t Power_registerNotify(Power_NotifyObj *notifyObj, /* Check for NULL pointers */ if ((notifyObj == NULL) || (notifyFxn == NULL)) { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_registerNotify: Notify registration failed due to NULL pointer"); + status = Power_EINVALIDPOINTER; } else @@ -394,6 +497,13 @@ int_fast16_t Power_registerNotify(Power_NotifyObj *notifyObj, notifyObj->notifyFxn = notifyFxn; notifyObj->clientArg = clientArg; + Log_printf(LogModule_Power, + Log_INFO, + "Power_registerNotify: Register fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + notifyFxn, + eventTypes, + clientArg); + /* Place notify object on event notification queue. Assume that * List_Elem struct member is the first struct member in * Power_NotifyObj. @@ -411,6 +521,13 @@ int_fast16_t Power_registerNotify(Power_NotifyObj *notifyObj, */ void Power_unregisterNotify(Power_NotifyObj *notifyObj) { + Log_printf(LogModule_Power, + Log_INFO, + "Power_unregisterNotify: Unregister fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + notifyObj->notifyFxn, + notifyObj->eventTypes, + notifyObj->clientArg); + /* Remove notify object from its event queue */ List_remove(¬ifyList, (List_Elem *)notifyObj); } @@ -503,6 +620,11 @@ int_fast16_t Power_setDependency(Power_Resource resourceId) } } + Log_printf(LogModule_Power, + Log_INFO, + "Power_setDependency: Updated resource counter = %d for resource ID = 0x%x", + Power_getDependencyCount(resourceId), resourceId); + HwiP_restore(key); return Power_SOK; @@ -548,6 +670,11 @@ int_fast16_t Power_releaseDependency(Power_Resource resourceId) } } + Log_printf(LogModule_Power, + Log_INFO, + "Power_releaseDependency: Updated resource counter = %d for resource ID = 0x%x", + Power_getDependencyCount(resourceId), resourceId); + HwiP_restore(key); return Power_SOK; @@ -629,9 +756,35 @@ int_fast16_t Power_sleep(uint_fast16_t sleepState) if (status != Power_SOK) { powerState = Power_ACTIVE; + + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed with status = 0x%x", + status); + return status; } + /* Adjust HFXT amplitude if needed */ + int_fast8_t adjustment = PowerLPF3_getHfxtAmpAdjustment(); + if (adjustment != 0) + { + PowerLPF3_adjustHfxtAmp(adjustment); + + /* Explicitly turn off HFXT before entering standby. This is to ensure + * that the HFXT is actually re-started with the new amplitude. In + * some cases the HFXT will not be turned off when entering standby. For + * example when entering fake standby with the debugger attached. + */ + HWREG(CKMD_BASE + CKMD_O_HFXTCTL) &= ~CKMD_HFXTCTL_EN_M; + } + + /* Stop continuous measurements of HFXT amplitude before entering standby, + * since the same hardware is needed to start the HFXT when waking up from + * standby. + */ + PowerCC23X0_stopContHfxtAmpMeasurements(); + /* Call wrapper function to ensure that R0-R3 are saved and restored before * and after this function call. Otherwise, compilers will attempt to stash * values on the stack while on the PSP and then restore them just after @@ -730,16 +883,16 @@ void PowerLPF3_selectLFOSC(void) /* Disable LFINC filter settling preventing standby */ HWREG(CKMD_BASE + CKMD_O_LFINCCTL) &= ~CKMD_LFINCCTL_PREVENTSTBY_M; - /* Enable LFCLKGOOD and TRACKREFLOSS. TRACKREFLOSS may occur when entering - * and exiting fake standby with the debugger attached. - */ - HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_LFCLKGOOD | CKMD_MIS_TRACKREFLOSS_M; + /* Enable LFCLKGOOD */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMSET_LFCLKGOOD; /* Disallow standby until LF clock is running. Otherwise, we will only * vector to the ISR after we wake up from standby the next time since the * CKM interrupt is purposefully not configured as a wakeup source. */ Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + Log_printf(LogModule_Power, Log_INFO, "PowerLPF3_selectLFOSC: LFOSC selected"); } /* @@ -747,11 +900,15 @@ void PowerLPF3_selectLFOSC(void) */ void PowerLPF3_selectLFXT(void) { - /* Set LFINC override to 32.768 kHz. - * Will not impact RTC since the fake LF ticks will have a higher priority - * than LFINCOVR. + /* Set LFINC override to 32.768 kHz. Will not impact RTC since the fake LF + * ticks will have a higher priority than LFINCOVR. + * + * The value is calculated as period in microseconds with 16 fractional + * bits. + * The LFXT runs at 32.768 kHz -> 1 / 32768 Hz = 30.5176 us. + * 30.5176 * 2^16 = 2000000 = 0x001E8480 */ - HWREG(CKMD_BASE + CKMD_O_LFINCOVR) = 0x001E8480 | CKMD_LFINCOVR_OVERRIDE_M; + HWREG(CKMD_BASE + CKMD_O_LFINCOVR) = 0x001E8480 | CKMD_LFINCOVR_OVERRIDE; /* Set LFCLK */ HWREG(CKMD_BASE + CKMD_O_LFCLKSEL) = CKMD_LFCLKSEL_MAIN_LFXT; @@ -767,6 +924,40 @@ void PowerLPF3_selectLFXT(void) * CKM interrupt is purposefully not configured as a wakeup source. */ Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + Log_printf(LogModule_Power, Log_INFO, "PowerLPF3_selectLFXT: LFXT selected"); +} + +/* + * ======== PowerLPF3_selectEXTLF ======== + */ +void PowerLPF3_selectEXTLF(void) +{ + /* Set LFINC override to 31.25 kHz. + * + * The value is calculated as period in microseconds with 16 fractional + * bits. + * The EXTLF runs at 31.25 kHz -> 1 / 31250 Hz = 32 us. + * 32 * 2^16 = 2097152 = 0x00200000 + */ + HWREG(CKMD_BASE + CKMD_O_LFINCOVR) = 0x00200000 | CKMD_LFINCOVR_OVERRIDE; + + /* Set LFCLK to EXTLF */ + HWREG(CKMD_BASE + CKMD_O_LFCLKSEL) = CKMD_LFCLKSEL_MAIN_EXTLF; + + /* Configure EXTLF to the right mux */ + GPIO_setConfigAndMux(PowerLPF3_extlfPin, GPIO_CFG_INPUT, PowerLPF3_extlfPinMux); + + /* Enable LFCLKGOOD */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMASK_LFCLKGOOD; + + /* Disallow standby until LF clock is running. Otherwise, we will only + * vector to the ISR after we wake up from standby the next time since the + * CKM interrupt is purposefully not configured as a wakeup source. + */ + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + Log_printf(LogModule_Power, Log_INFO, "PowerLPF3_selectEXTLF: EXTLF selected"); } /* @@ -785,45 +976,74 @@ static void PowerCC23X0_oscillatorISR(uintptr_t arg) if (maskedStatus & CKMD_MIS_AMPSETTLED_M) { - PowerCC23X0_notify(PowerLPF3_HFXT_AVAILABLE); + /* Stop AMPSETTLED timeout clock and change callback function of clock + * object (NULL: not used) + */ + ClockP_stop(&hfxtAmpCompClock); + ClockP_setFunc(&hfxtAmpCompClock, NULL, 0); - /* Allow standby again now that HFXT has finished starting */ - Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + /* Start continuous measurements of HFXT amplitude */ + PowerCC23X0_startContHfxtAmpMeasurements(); + + /* If enabled, start the initial HFXT amplitude compensation */ + if (startInitialHfxtAmpCompFxn != NULL) + { + /* Start the asynchronous initial HFXT amplitude compensation. + * When the HFXT amplitude compensation is done the + * PowerLPF3_HFXT_AVAILABLE notification will be posted, and the + * PowerLPF3_DISALLOW_STANDBY constraint will be released. + */ + startInitialHfxtAmpCompFxn(); + + /* Only do the initial HFXT amplitude compensation once */ + startInitialHfxtAmpCompFxn = NULL; + } + else + { + Log_printf(LogModule_Power, Log_INFO, "PowerCC23X0_oscillatorISR: HFXT is available"); + + PowerCC23X0_notify(PowerLPF3_HFXT_AVAILABLE); + + /* Allow standby again now that HFXT has finished starting */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } } - else if (maskedStatus & CKMD_MIS_HFXTFAULT_M) + + if (maskedStatus & (CKMD_MIS_HFXTFAULT_M | CKMD_MIS_TRACKREFLOSS_M)) { - /* If there was a fault, restart HFXT. Consider issuing a notification - * to allow logging. If we keep it like this, we could get stuck in an - * infinite loop restarting a faulty oscillator. Then again, it is not - * like there is a great way to recover from that. + Log_printf(LogModule_Power, Log_WARNING, "PowerCC23X0_oscillatorISR: HFXT fault and/or TRACKREFLOSS, restarting HFXT"); + + /* If there was a HFXTFAULT or TRACKREFLOSS, restart HFXT. Consider + * issuing a notification to allow logging. If we keep it like this, we + * could get stuck in an infinite loop restarting a faulty oscillator. + * Then again, it is not like there is a great way to recover from that. */ HWREG(CKMD_BASE + CKMD_O_HFXTCTL) &= ~CKMD_HFXTCTL_EN_M; + /* Stop continuous measurements of HFXT amplitude. The hardware used is + * needed to start HFXT. + */ + PowerCC23X0_stopContHfxtAmpMeasurements(); + + /* Max out IREF */ + CKMDSetTargetIrefTrim(HFXT_TARGET_IREF_MAX); + /* Start up the HFXT using the workaround for the HFXT amplitude control ADC * bias point */ PowerCC23X0_startHFXT(); - } - - if (maskedStatus & CKMD_MIS_LFCLKGOOD_M) - { - /* Enable LF clock monitoring */ - HWREG(CKMD_BASE + CKMD_O_LFMONCTL) = CKMD_LFMONCTL_EN; - - /* Enable LF clock loss reset while in standby */ - HWREG(PMCTL_BASE + PMCTL_O_RSTCTL) |= PMCTL_RSTCTL_LFLOSS_ARMED; - - /* Send out notification for LF clock switch */ - PowerCC23X0_notify(PowerLPF3_LFCLK_SWITCHED); - /* Allow standby again now that we have sent out the notification */ - Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + /* Re-enable interrupts */ + HWREG(CKMD_BASE + CKMD_O_IMSET) = maskedStatus & (CKMD_MIS_HFXTFAULT_M | CKMD_MIS_TRACKREFLOSS_M); } if (maskedStatus & CKMD_MIS_TRACKREFLOSS_M) { - /* Disable interrupts as HFXT SWTCXO may interrupt and modify HFTRACKCTL - * with a higher priority depending on user interrupt priorities. + Log_printf(LogModule_Power, Log_WARNING, "PowerCC23X0_oscillatorISR: TRACKREFLOSS, re-enable tracking"); + + /* Disable interrupts as HFXT SWTCXO may interrupt and modify + * HFTRACKCTL with a higher priority depending on user interrupt + * priorities. */ uintptr_t key = HwiP_disable(); @@ -836,7 +1056,24 @@ static void PowerCC23X0_oscillatorISR(uintptr_t arg) HwiP_restore(key); /* Re-enable TRACKREFLOSS */ - HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_MIS_TRACKREFLOSS_M; + HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMSET_TRACKREFLOSS_M; + } + + if (maskedStatus & CKMD_MIS_LFCLKGOOD_M) + { + Log_printf(LogModule_Power, Log_INFO, "PowerCC23X0_oscillatorISR: LFCLK is ready"); + + /* Enable LF clock monitoring */ + HWREG(CKMD_BASE + CKMD_O_LFMONCTL) = CKMD_LFMONCTL_EN; + + /* Enable LF clock loss reset while in standby */ + HWREG(PMCTL_BASE + PMCTL_O_RSTCTL) |= PMCTL_RSTCTL_LFLOSS_ARMED; + + /* Send out notification for LF clock switch */ + PowerCC23X0_notify(PowerLPF3_LFCLK_SWITCHED); + + /* Allow standby again now that we have sent out the notification */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); } } @@ -848,11 +1085,19 @@ static void PowerCC23X0_oscillatorISR(uintptr_t arg) * Not manually starting HFXT can lead to: * - HFXT never becoming available * - Poor phase noise in the radio + * + * It should be ensured that the system does not vector to the CKMD interrupt + * (PowerCC23X0_oscillatorISR) while this function is executing. + * Meaning any of the following must be true: + * - Interrupts are disabled, or + * - This function is called from PowerCC23X0_oscillatorISR(), since nested + * vectoring to the same interrupt is not possible. */ static void PowerCC23X0_startHFXT(void) { - /* Return immediately if HFXT is already enabled. Not doing so will cause - * TRACKREFLOSS when starting the LDO. This situation can arise when: + /* Only start HFXT if it is not already enabled. Trying to start the HFXT + * if it is already enabled will cause TRACKREFLOSS when starting the LDO. + * This situation can arise when: * - Waking up from fake standby. Fake standby does not shut down the HFXT, * unlike real standby. * - Waking up without actually entering real standby. If a wakeup source is @@ -860,53 +1105,52 @@ static void PowerCC23X0_startHFXT(void) * turn that into a NOP instead and not run through the regular state * machine. */ - if ((HWREG(CKMD_BASE + CKMD_O_HFXTCTL) & CKMD_HFXTCTL_EN_M) == CKMD_HFXTCTL_EN) + if ((HWREG(CKMD_BASE + CKMD_O_HFXTCTL) & CKMD_HFXTCTL_EN_M) != CKMD_HFXTCTL_EN) { - return; - } - - /* Start LDO */ - HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_STARTCTL | CKMD_LDOCTL_START | CKMD_LDOCTL_EN); + /* Start LDO */ + HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_STARTCTL | CKMD_LDOCTL_START | + CKMD_LDOCTL_EN); - /* Bypass a lowpass filter that is connected to the reference voltage for - * 66us to ensure that reference has settled - */ - HapiWaitUs(66); + /* Bypass a lowpass filter that is connected to the reference voltage + * for 66us to ensure that reference has settled. + */ + HapiWaitUs(66); - /* Clear START bits */ - HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_HFXTLVLEN | CKMD_LDOCTL_EN); + /* Clear START bits */ + HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_HFXTLVLEN | CKMD_LDOCTL_EN); - /* Force bias measurement before enabling HFXT - Set SRCSEL = BIAS. - * Enable the peak detector in the HFXT amplitude control loop to control - * RF phase jumps. - */ - HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_PEAKDETEN_ENABLE | - CKMD_AMPADCCTL_ADCEN_ENABLE); + /* Force bias measurement before enabling HFXT - Set SRCSEL = BIAS. + * Enable the peak detector in the HFXT amplitude control loop to + * control RF phase jumps. + */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_PEAKDETEN_ENABLE | + CKMD_AMPADCCTL_ADCEN_ENABLE); - /* Delay to settle PEAKDET + ADC */ - HapiWaitUs(6); + /* Delay to settle PEAKDET + ADC */ + HapiWaitUs(6); - /* Clear raw interrupt for ADCBIASUPD */ - HWREG(CKMD_BASE + CKMD_O_ICLR) = CKMD_ICLR_ADCBIASUPD; + /* Clear raw interrupt for ADCBIASUPD */ + HWREG(CKMD_BASE + CKMD_O_ICLR) = CKMD_ICLR_ADCBIASUPD; - /* Start an SAR conversion */ - HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) |= CKMD_AMPADCCTL_SARSTRT; + /* Start an SAR conversion */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) |= CKMD_AMPADCCTL_SARSTRT; - /* Immediately prevent any SAR new conversions from starting. The one - * started above will complete though. - */ - HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SARSTRT; + /* Immediately prevent any SAR new conversions from starting. The one + * started above will complete though. + */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SARSTRT; - /* Wait until HFXT-ADC BIAS measurement is done */ - while (!((HWREG(CKMD_BASE + CKMD_O_RIS) & CKMD_RIS_ADCBIASUPD_M) == CKMD_RIS_ADCBIASUPD)) {} + /* Wait until HFXT-ADC BIAS measurement is done */ + while (!((HWREG(CKMD_BASE + CKMD_O_RIS) & CKMD_RIS_ADCBIASUPD_M) == CKMD_RIS_ADCBIASUPD)) {} - /* Clear SW override of amplitude ADC */ + /* Clear SW override of amplitude ADC */ - /* Keep PEAKDET on */ - HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~(CKMD_AMPADCCTL_SWOVR_M | CKMD_AMPADCCTL_ADCEN_M); + /* Keep PEAKDET on */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~(CKMD_AMPADCCTL_SWOVR_M | CKMD_AMPADCCTL_ADCEN_M); - /* Start HFXT */ - HWREG(CKMD_BASE + CKMD_O_HFXTCTL) |= CKMD_HFXTCTL_EN; + /* Start HFXT */ + HWREG(CKMD_BASE + CKMD_O_HFXTCTL) |= CKMD_HFXTCTL_EN; + } /* Disallow standby until AMPSETTLED is true */ Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); @@ -949,11 +1193,25 @@ int_fast16_t PowerCC23X0_notify(uint_fast16_t eventType) clientArg = ((Power_NotifyObj *)elem)->clientArg; /* Call the client's notification function */ + Log_printf(LogModule_Power, + Log_VERBOSE, + "PowerCC23X0_notify: Invoking notification fxn at address 0x%x with event type 0x%x and clientArg 0x%x", + notifyFxn, + eventType, + clientArg); + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)(eventType, 0, clientArg); /* If client declared error stop all further notifications */ if (notifyStatus != Power_NOTIFYDONE) { + Log_printf(LogModule_Power, + Log_WARNING, + "PowerCC23X0_notify: Notification fxn reported error, fxn at address 0x%x with event type 0x%x and notifyStatus 0x%x", + notifyFxn, + eventType, + notifyStatus); + return Power_EFAIL; } } @@ -1108,6 +1366,12 @@ static void PowerCC23X0_hfxtCompensateFxn(int16_t currentTemperature, */ if (PowerCC23X0_hfxtCompEnabled) { + Log_printf(LogModule_Power, + Log_INFO, + "PowerCC23X0_hfxtCompensateFxn: Registering notification. Temp = %d, Temp threshold = %d", + currentTemperature, + hfxtConfig.temperature.threshold); + if (currentTemperature > hfxtConfig.temperature.threshold) { /* If temperature is above compensation threshold then compute a @@ -1203,6 +1467,12 @@ void PowerLPF3_enableHFXTCompensation(int16_t tempThreshold, int16_t tempDelta) PowerCC23X0_hfxtCompensateFxn, (uintptr_t)config.value); } + + Log_printf(LogModule_Power, + Log_INFO, + "PowerLPF3_enableHFXTCompensation: Compensation enabled. Temp = %d, Temp threshold = %d", + currentTemperature, + tempThreshold); } } @@ -1223,4 +1493,280 @@ void PowerLPF3_disableHFXTCompensation(void) PowerCC23X0_updateHFXTRatio(CKMD_HFTRACKCTL_RATIO_REF48M); } HwiP_restore(key); + + Log_printf(LogModule_Power, + Log_INFO, + "PowerLPF3_disableHFXTCompensation: Compensation disabled"); +} + +/* + * ======== PowerLPF3_startInitialHfxtAmpComp ======== + * Function to start the initial HFXT amplitude compensation. + * If initial HFXT compensation is to be performed, this function is to be + * called in the interrupt handler for the AMPSETTLED interrupt instead of + * posting a PowerLPF3_HFXT_AVAILABLE notification and releasing the + * PowerLPF3_DISALLOW_STANDBY constraint. + * + * The initial HFXT amplitude compensation assumes that the HFXTTARG.IREF value + * is set to the max value (HFXT_TARGET_IREF_MAX) when this function is called. + * The IREF value will then be updated in steps until the optimal IREF + * value has been found. This is the steps taken: + * 1. Wait HFXT_AMP_COMP_MEASUREMENT_US us, to let the HFXT amplitude settle + * before measuring it. + * 2. Measure the HFXT amplitude. + * 3. If amplitude is above 16, decrement IREF, but never lower than + * HFXT_TARGET_IREF_MIN. + * 4. If an adjustment was made, go to step 1. + * 5. If amplitude is below 10, increment IREF back to previous value. No new + * measurement is required. + * 6. If an adjustment was made, wait HFXT_AMP_COMP_MEASUREMENT_US us, to let + * the HFXT amplitude settle. + * 7. Post PowerLPF3_HFXT_AVAILABLE notification and release + * PowerLPF3_DISALLOW_STANDBY constraint. + * + * The waits mentioned in step 1 and 6 will be done asynchronously using + * hfxtAmpCompClock, and most of above logic is handled in the callback function + * for the clock (PowerCC23X0_initialHfxtAmpCompClockCb). + * + * This function is only responsible for starting the process by starting the + * clock to perform the first iteration of step 1. + * + * In the worst case (in terms of how long the process takes), the IREF value + * will be decremented to HFXT_TARGET_IREF_MIN and then incremented back to + * (HFXT_TARGET_IREF_MIN + 1). This means that the IREF will be changed + * ((HFXT_TARGET_IREF_MAX - HFXT_TARGET_IREF_MIN) + 1) times. After each change + * we need to wait for HFXT_AMP_COMP_MEASUREMENT_US, and including waiting + * before the first measurement it means that the initial HFXT amplitude + * compensation will take up to + * ((HFXT_TARGET_IREF_MAX - HFXT_TARGET_IREF_MIN) + 2)*HFXT_AMP_COMP_MEASUREMENT_US us + * plus aditional processing time. + */ +void PowerLPF3_startInitialHfxtAmpComp(void) +{ + /* Update hfxtAmpCompClock callback function */ + ClockP_setFunc(&hfxtAmpCompClock, PowerCC23X0_initialHfxtAmpCompClockCb, 0); + + /* Set timeout for the first HFXT amplitude measurement */ + ClockP_setTimeout(&hfxtAmpCompClock, HFXT_AMP_COMP_MEASUREMENT_US / ClockP_getSystemTickPeriod()); + + /* Start clock */ + ClockP_start(&hfxtAmpCompClock); +} + +/* + * ======== PowerLPF3_getHfxtAmpAdjustment ======== + */ +int_fast8_t PowerLPF3_getHfxtAmpAdjustment(void) +{ + uint32_t hfxtAmplitude = PowerCC23X0_getHfxtAmpMeasurement(); + uint32_t currentIrefTrim = CKMDGetTargetIrefTrim(); + + if (hfxtAmplitude < 10 && currentIrefTrim < HFXT_TARGET_IREF_MAX) + { + /* Increase amplitude if the amplitude is too small */ + return +1; + } + else if (hfxtAmplitude > 16 && currentIrefTrim > HFXT_TARGET_IREF_MIN) + { + /* Decrease the amplitude if the amplitude is too big */ + return -1; + } + else + { + /* No adjustment is needed */ + return 0; + } +} + +/* + * ======== PowerLPF3_adjustHfxtAmp ======== + */ +void PowerLPF3_adjustHfxtAmp(int_fast8_t adjustment) +{ + uint32_t newTargetIref = CKMDGetTargetIrefTrim() + adjustment; + CKMDSetTargetIrefTrim(newTargetIref); +} + +/* + * ======== PowerCC23X0_initialHfxtAmpCompClockCb ======== + * Callback function for the hfxtAmpCompClock object when it is used for the + * initial HFXT amplitude compensation. + * + * params: + * - searchDone: If true (non-zero), the search for the optimal IREF value has + * already been found. + */ +static void PowerCC23X0_initialHfxtAmpCompClockCb(uintptr_t searchDone) +{ + + /* Has the optimal IREF value been found? + * Might be updated below. + */ + bool optimalIref = (bool)searchDone; + + /* Has the IREF value been changed? + * Will be updated below if the IREF value is changed. + */ + bool irefChanged = false; + + /* Continue search if the optimal IREF has not yet been found */ + if (optimalIref == false) + { + /* Measure amplitude */ + uint32_t hfxtAmplitude = PowerCC23X0_getHfxtAmpMeasurement(); + + /* Get current IREF value */ + uint32_t currentIrefTrim = CKMDGetTargetIrefTrim(); + + /* Determine if IREF needs to be changed. + * Note, PowerLPF3_getHfxtAmpAdjustment() is not used here, because the + * amplitude limits used here are different. + */ + if (hfxtAmplitude < 10 && currentIrefTrim < HFXT_TARGET_IREF_MAX) + { + /* Increase amplitude if the amplitude is too small */ + CKMDSetTargetIrefTrim(currentIrefTrim + 1); + irefChanged = true; + + /* No new measurement is required, because we know + * that IREF = currentIrefTrim + 1 causes an amplitude above 10, + * otherwise IREF would not have been decreased. + */ + optimalIref = true; + } + else if (hfxtAmplitude > 16 && currentIrefTrim > HFXT_TARGET_IREF_MIN) + { + /* Decrease amplitude if the amplitude is too big */ + CKMDSetTargetIrefTrim(currentIrefTrim - 1); + irefChanged = true; + } + else + { + /* IREF is optimal since since the HFXT amplitude is already in + * the optimal range (10-16) + */ + optimalIref = true; + } + } + + if (irefChanged) + { + /* If IREF has changed, start the clock again. If the optimal IREF + * value has been found, then the search is done, so in the next clock + * callback no measurements are needed (searchDone is true). + */ + ClockP_setFunc(&hfxtAmpCompClock, PowerCC23X0_initialHfxtAmpCompClockCb, optimalIref); + + /* Set timeout */ + ClockP_setTimeout(&hfxtAmpCompClock, HFXT_AMP_COMP_MEASUREMENT_US / ClockP_getSystemTickPeriod()); + + /* Start clock */ + ClockP_start(&hfxtAmpCompClock); + } + else + { + /* Update hfxtAmpCompClock callback function (NULL because the clock is + * no longer used) + */ + ClockP_setFunc(&hfxtAmpCompClock, NULL, 0); + + Log_printf(LogModule_Power, Log_INFO, "PowerCC23X0_initialHfxtAmpCompClockCb: HFXT is available"); + + /* Send HFXT available notification */ + PowerCC23X0_notify(PowerLPF3_HFXT_AVAILABLE); + + /* Allow standby again now that the optimal IREF value has been found */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } +} + +/* + * ======== PowerCC23X0_hfxtAmpsettledTimeout ======== + * Callback function for the hfxtAmpCompClock object when it is used as a + * timeout for the AMPSETTLED signal. If the timeout occurs (i.e. if this + * function is called), and if the HFXT FSM is stuck in the RAMP0 state, + * it will be forced to the RAMP1 state. + */ +static void PowerCC23X0_hfxtAmpsettledTimeout(uintptr_t arg) +{ + /* Disable interrupts */ + uintptr_t key = HwiP_disable(); + + /* Timeout occured while waiting for AMPSETTLED */ + if ((HWREG(CKMD_BASE + CKMD_O_AMPSTAT) & CKMD_AMPSTAT_STATE_M) == CKMD_AMPSTAT_STATE_RAMP0) + { + PowerCC23X0_forceHfxtFsmToRamp1(); + } + + HwiP_restore(key); +} + +/* + * ======== PowerCC23X0_forceHfxtFsmToRamp1 ======== + * Force HFXT FSM to RAMP1 state. This function should only be called if the + * HFXT FSM is stuck in RAMP0 state. + */ +static void PowerCC23X0_forceHfxtFsmToRamp1(void) +{ + /* Max out IREF */ + CKMDSetTargetIrefTrim(HFXT_TARGET_IREF_MAX); + + /* Force a transition to RAMP1 state */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_SRCSEL_PEAK | + CKMD_AMPADCCTL_ADCEN_ENABLE | CKMD_AMPADCCTL_COMPSTRT); + + /* Wait until state changes */ + while ((HWREG(CKMD_BASE + CKMD_O_AMPSTAT) & CKMD_AMPSTAT_STATE_M) == CKMD_AMPSTAT_STATE_RAMP0) {} + + /* Disable AMPADCCTL.SWOVR and let the FSM take control again */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SWOVR; +} + +/* + * ======== PowerCC23X0_startContHfxtAmpMeasurements ======== + * Start continuous measurements of the HFXT amplitude. + * This is done to quickly be able to read the amplitude using + * PowerCC23X0_getHfxtAmpMeasurement() when a measurement is needed. + */ +static void PowerCC23X0_startContHfxtAmpMeasurements(void) +{ + /* Force amplitude measurement - Set SRCSEL = PEAK */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_PEAKDETEN_ENABLE | + CKMD_AMPADCCTL_ADCEN_ENABLE | CKMD_AMPADCCTL_SRCSEL_PEAK | + CKMD_AMPADCCTL_SARSTRT); +} + +/* + * ======== PowerCC23X0_stopContHfxtAmpMeasurements ======== + * Stop the continuous HFXT amplitude measurements started by + * PowerCC23X0_startContHfxtAmpMeasurements(). + */ +static void PowerCC23X0_stopContHfxtAmpMeasurements(void) +{ + /* Clear SW override of Amplitude ADC */ + HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SWOVR; +} + +/* + * ======== PowerCC23X0_getHfxtAmpMeasurement ======== + * Read the the latest HFXT amplitude measurement. + * Continuous measurements must have been started using + * PowerCC23X0_startContHfxtAmpMeasurements(). + */ +static uint32_t PowerCC23X0_getHfxtAmpMeasurement(void) +{ + + /* Read result in AMPADCSTAT */ + uint32_t ampAdcStat = HWREG(CKMD_BASE + CKMD_O_AMPADCSTAT); + uint32_t peakRaw = (ampAdcStat & CKMD_AMPADCSTAT_PEAKRAW_M) >> CKMD_AMPADCSTAT_PEAKRAW_S; + uint32_t bias = (ampAdcStat & CKMD_AMPADCSTAT_BIAS_M) >> CKMD_AMPADCSTAT_BIAS_S; + + /* Compute the PEAK value in SW to be able to handle negative values, which + * can occur for small amplitudes. + * In case of negative values, the result will be capped at 0. + * According to the register descriptions PEAK = 2*PEAKRAW - BIAS + */ + uint32_t result = 2 * peakRaw > bias ? 2 * peakRaw - bias : 0; + + return result; } diff --git a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h index 6a917c75..56a66eed 100644 --- a/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h +++ b/simplelink_lpf3/source/ti/drivers/power/PowerCC23X0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Texas Instruments Incorporated + * Copyright (c) 2021-2024, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -42,10 +42,42 @@ * * Refer to @ref Power.h for a complete description of APIs. * - * ## Implementation # + * ## Implementation ## * This header file defines the power resources, constraints, events, sleep * states and transition latencies for CC23X0. * + * @anchor ti_drivers_PowerCC23X0_HFXT_Amplitude_Compensation + * ## HFXT Amplitude Compensation ## + * The CC23X0 Power driver will configure the HFXT amplitude to the highest + * possible value at boot (in #Power_init()). Each time the device + * enters standby the HFXT amplitude will be updated to ensure the optimal + * amplitude is used. It will take up to 5 iterations (5 standby entries) + * after boot until the optimal amplitude has been found. This process will + * ensure that the amplitude is kept in an optimal range if the operating + * conditions change, as long as the device regularly enters standby. + * + * ### Applications that rarely enters standby ### + * The amplitude adjustments done at standby entry is sufficient for + * applications that regularly enters standby, but if the application does not + * regularly enter standby, then #PowerLPF3_getHfxtAmpAdjustment() and + * #PowerLPF3_adjustHfxtAmp() can be used to check if an adjustment is needed, + * and perform the adjustment if needed. + * + * @anchor ti_drivers_PowerCC23X0_Initial_HFXT_Amplitude_Compensation + * ### Initial HFXT Amplitude Compensation ### + * If the application requires that the HFXT amplitude is already in the + * optimal range after boot, then Initial HFXT Amplitude Compensation can be + * enabled with #PowerCC23X0_Config.startInitialHfxtAmpCompFxn. + * If initial HFXT amplitude compensation is enabled, the optimal amplitude + * will be found at/after boot, meaning it will take longer before HFXT is + * ready after boot, but when it is ready the amplitude will already be in the + * optimal range. This process is done asynchronously, so the application can + * do other stuff while waiting for HFXT to be ready. + * + * Enabling initial HFXT amplitude compensation will result in more flash usage + * and longer time from boot to the first RF operation. + * + * * ============================================================================ */ @@ -150,7 +182,7 @@ typedef uint16_t PowerLPF3_Resource; /* Power resource identifier */ */ #if defined(DeviceFamily_CC23X0R2) #define PowerCC23X0_NUMRESOURCES_CLKCTL0 29 -#elif defined(DeviceFamily_CC23X0R5) +#elif (defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R22)) #define PowerCC23X0_NUMRESOURCES_CLKCTL0 31 #else #error "Unsupported DeviceFamily specified!" @@ -217,6 +249,14 @@ typedef uint16_t PowerLPF3_Resource; /* Power resource identifier */ #define PowerCC23X0_NUMEVENTS 5 /* Number of events supported */ /* \endcond */ +/*! + * @brief Function pointer to #PowerLPF3_startInitialHfxtAmpComp() or NULL. + * + * This type is only allowed to have the value NULL or be a + * pointer to #PowerLPF3_startInitialHfxtAmpComp(). + */ +typedef void (*PowerLPF3_StartInitialHfxtAmpCompFxn)(void); + /*! @brief Global configuration structure */ typedef struct { @@ -256,6 +296,22 @@ typedef struct * Power_disablePolicy() functions, respectively. */ Power_PolicyFxn policyFxn; + + /*! + * @brief Pointer to the function to start the initial HFXT amplitude + compensation. + * + * This is used to enable/disable the initial HFXT amplitude compensation + * feature. + * + * The allowed values for this field is: + * - NULL: Initial HFXT amplitude compensation is disabled. + * - Pointer to #PowerLPF3_startInitialHfxtAmpComp(): Initial HFXT + * amplitude compensation is disabled. + * + * @sa @ref ti_drivers_PowerCC23X0_Initial_HFXT_Amplitude_Compensation "Initial HFXT Amplitude Compensation" + */ + PowerLPF3_StartInitialHfxtAmpCompFxn startInitialHfxtAmpCompFxn; } PowerCC23X0_Config; /*! @@ -269,7 +325,7 @@ typedef enum PowerLPF3_RESET_SHUTDOWN_SWD = PMCTL_RESET_SHUTDOWN_SWD, /*! Device reset because of a watchdog timeout. */ PowerLPF3_RESET_WATCHDOG = PMCTL_RESET_WATCHDOG, - /*! Device reset trggered by software writing to RSTCTL.SYSRST */ + /*! Device reset triggered by software writing to RSTCTL.SYSRST */ PowerLPF3_RESET_SYSTEM = PMCTL_RESET_SYSTEM, /*! Device reset triggered by CPU reset event */ PowerLPF3_RESET_CPU = PMCTL_RESET_CPU, @@ -367,30 +423,54 @@ void PowerCC23X0_standbyPolicy(void); * this event will be notified. * * @warning Dynamic switching between LF clocks is not supported. Once one of - * PowerLPF3_selectLFOSC() or PowerLPF3_selectLFXT() is called in an - * application, the other one may not be invoked thereafter. + * PowerLPF3_selectLFOSC(), PowerLPF3_selectLFXT() or PowerLPF3_selectEXTLF() + * is called in an application, the other two may not be invoked thereafter. * * @pre Power_init() * @sa PowerLPF3_selectLFXT() + * @sa PowerLPF3_selectEXTLF() */ void PowerLPF3_selectLFOSC(void); /*! - * @brief Select LFOSC as LFCLK source + * @brief Select LFXT as LFCLK source * * Turn on the LFXT and choose it as LFCLK source. Once LFCLK has switched, * the #PowerLPF3_LFCLK_SWITCHED notification will be issued and all * subscribers to this event will be notified. * * @warning Dynamic switching between LF clocks is not supported. Once one of - * PowerLPF3_selectLFOSC() or PowerLPF3_selectLFXT() is called in an - * application, the other one may not be invoked thereafter. + * PowerLPF3_selectLFOSC(), PowerLPF3_selectLFXT() or PowerLPF3_selectEXTLF() + * is called in an application, the other two may not be invoked thereafter. * * @pre Power_init() * @sa PowerLPF3_selectLFOSC() + * @sa PowerLPF3_selectEXTLF() */ void PowerLPF3_selectLFXT(void); +/*! + * @brief Select EXTLF as LFCLK source + * + * Choose an external 31.25 kHz square wave as the LFCLK source as input. + * Once LFCLK has switched, the #PowerLPF3_LFCLK_SWITCHED notification + * will be issued and all subscribers to this event will be notified. + * + * This function requires the following symbols to be defined. + * - \c PowerLPF3_extlfPin (uint8_t): The DIO number of the pin to be used as the EXTLF pin. + * - \c PowerLPf3_extlfPinMux (uint8_t): Mux value used to mux the EXTLF signal to \c PowerLPF3_extlfPin. + * If using SysConfig, the symbols will be defined in ti_drivers_config.c. + * + * @warning Dynamic switching between LF clocks is not supported. Once one of + * PowerLPF3_selectLFOSC(), PowerLPF3_selectLFXT() or PowerLPF3_selectEXTLF() + * is called in an application, the other two may not be invoked thereafter. + * + * @pre Power_init() + * @sa PowerLPF3_selectLFOSC() + * @sa PowerLPF3_selectLFXT() + */ +void PowerLPF3_selectEXTLF(void); + /*! * @brief Initialise HFXT temperature compensation coefficients * @@ -408,6 +488,7 @@ void PowerLPF3_selectLFXT(void); * * @pre Power_init() */ + void PowerLPF3_initHFXTCompensation(int32_t P0, int32_t P1, int32_t P2, int32_t P3, uint8_t shift, bool fcfgInsertion); /*! @@ -446,6 +527,55 @@ void PowerLPF3_enableHFXTCompensation(int16_t tempThreshold, int16_t tempDelta); */ void PowerLPF3_disableHFXTCompensation(void); +/*! + * @brief Start initial compensation of the HFXT amplitude + * + * @warning This function must not be called by the application. It is only + * intended to be specified for #PowerCC23X0_Config.startInitialHfxtAmpCompFxn + */ +void PowerLPF3_startInitialHfxtAmpComp(void); + +/*! + * @brief Check if HFXT amplitude needs to be adjusted + * + * The HFXT amplitude needs to regularly be checked and if needed adjusted. + * The Power driver will check the amplitude and adjust it when the device + * enters standby. However if the device does not enter standby often enough, + * then additional checks and adjustments are needed. + * + * This function can be used to check if adjustment of the amplitude is needed, + * and #PowerLPF3_adjustHfxtAmp() can be used to adjust the amplitude if needed. + * + * @return + * - +1: The amplitude needs to be increased + * - 0: No adjustments are needed + * - -1: The amplitude needs to be decreased + * + * @sa #PowerLPF3_adjustHfxtAmp() + */ +int_fast8_t PowerLPF3_getHfxtAmpAdjustment(void); + +/*! + * @brief Adjust the HFXT amplitude + * + * This function is to be used to adjust the HFXT amplitude if an adjustment is + * needed according to #PowerLPF3_getHfxtAmpAdjustment(). Please refer to the + * documentation of #PowerLPF3_getHfxtAmpAdjustment() for more details. + * + * @note The radio must be disabled when adjusting the HFXT amplitude, and while + * the amplitude is settling. + * After this function returns, the caller must wait until the HFXT amplitude + * has settled. + * + * @param adjustment the value returned by #PowerLPF3_getHfxtAmpAdjustment(). + * No other value is allowed. + * + * @pre #PowerLPF3_getHfxtAmpAdjustment() must be called, and it must return + * a non-zero value (indicating that adjustment is needed) + * @sa #PowerLPF3_getHfxtAmpAdjustment() + */ +void PowerLPF3_adjustHfxtAmp(int_fast8_t adjustment); + void PowerCC23X0_schedulerDisable(void); void PowerCC23X0_schedulerRestore(void); diff --git a/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.c b/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.c new file mode 100644 index 00000000..7c30ca48 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.c @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RNGLPF3RF.c ======== + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) + +extern const RNGLPF3RF_HWAttrs RNGLPF3RF_hwAttrs; +extern uint8_t RNG_instancePool[]; + +extern const RNG_ReturnBehavior RNGLPF3RF_returnBehavior; + +/* CBC MAC key words used to compute RNG seed */ +extern uint32_t RNGLPF3RF_noiseConditioningKeyWord0; +extern uint32_t RNGLPF3RF_noiseConditioningKeyWord1; +extern uint32_t RNGLPF3RF_noiseConditioningKeyWord2; +extern uint32_t RNGLPF3RF_noiseConditioningKeyWord3; + +typedef struct RNGLPF3RF_OperationParameters_ RNGLPF3RF_OperationParameters; + +typedef bool (*RNGLPF3RF_validator)(RNGLPF3RF_OperationParameters *opParams); + +/* Mask used to extract the upper or lower byte of a word */ +#define BYTE_MASK 0xff + +/* + * These values are used with the validator function prototype to provide potentially relevant parameters + * for validation after a candidate number has been generated. + */ +struct RNGLPF3RF_OperationParameters_ +{ + uint8_t *output; + size_t outputBitLength; + CryptoUtils_Endianess endianess; + const uint8_t *lowerLimit; + const uint8_t *upperLimit; +}; + +typedef struct +{ + /* No data in the structure should be read or written without first taking this semaphore. */ + SemaphoreP_Struct accessSemaphore; + size_t poolLevel; + AESCTRDRBG_Config drbgConfig; + AESCTRDRBGXX_Object drbgObject; + AESCTRDRBGXX_HWAttrs drbgHWattrs; +} RNGLPF3RF_Instance; + +RNGLPF3RF_Instance RNGLPF3RF_instanceData; + +static bool RNGLPF3RF_isInitialized = false; +static bool RNGLPF3RF_isSeeded = false; + +/*** Prototypes ***/ +static int_fast16_t RNGLPF3RF_translateDRBGStatus(int_fast16_t drbgStatus); +static int_fast16_t RNGLPF3RF_generateEntropy(AESCTRDRBG_Handle drbgHandle, uint8_t *byteDest, size_t byteSize); +static int_fast16_t RNGLPF3RF_fillPoolIfLessThan(size_t bytes); +static int_fast16_t RNGLPF3RF_getEntropyFromPool(void *dest, size_t byteSize, size_t *bytesRemaining); +static bool RNGLPF3RF_checkRange(RNGLPF3RF_OperationParameters *opParams); +static int_fast16_t RNGLPF3RF_getValidatedNumber(RNG_Handle handle, + void *randomNumber, + size_t randomNumberBitLength, + CryptoUtils_Endianess endianess, + RNGLPF3RF_validator validator, + const void *lowerLimit, + const void *upperLimit); +static int_fast16_t RNGLPF3RF_createDRBGInstance(void); +static int_fast16_t RNGLPF3RF_conditionNoise(uint32_t *noiseInput, uint32_t *seed); + +/* + * ======== RNGLPF3RF_translateDRBGStatus ======== + */ +static int_fast16_t RNGLPF3RF_translateDRBGStatus(int_fast16_t drbgStatus) +{ + int_fast16_t returnValue; + + switch (drbgStatus) + { + case AESCTRDRBG_STATUS_SUCCESS: + returnValue = RNG_STATUS_SUCCESS; + break; + case AESCTRDRBG_STATUS_ERROR: + returnValue = RNG_STATUS_ERROR; + break; + case AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE: + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + break; + case AESCTRDRBG_STATUS_RESEED_REQUIRED: + /* Map to RNG_ENTROPY_EXHAUSTED, reboot required for recovery. */ + returnValue = RNG_ENTROPY_EXHAUSTED; + break; + case AESCTRDRBG_STATUS_UNINSTANTIATED: + /* Map to RNG_ENTROPY_EXHAUSTED, reboot required for recovery. */ + returnValue = RNG_ENTROPY_EXHAUSTED; + break; + default: + returnValue = RNG_STATUS_ERROR; + break; + } + + return returnValue; +} + +/* + * ======== RNGLPF3RF_generateEntropy ======== + */ +int_fast16_t RNGLPF3RF_generateEntropy(AESCTRDRBG_Handle drbgHandle, uint8_t *byteDest, size_t byteSize) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + int_fast16_t drbgResult; + + if (!RNGLPF3RF_isInitialized) + { + returnValue = RNG_STATUS_NOT_INITIALIZED; + } + + if (returnValue != RNG_STATUS_NOT_INITIALIZED) + { + drbgResult = AESCTRDRBG_getRandomBytes(drbgHandle, byteDest, byteSize); + + returnValue = RNGLPF3RF_translateDRBGStatus(drbgResult); + } + + return returnValue; +} + +/* + * ======== RNGLPF3RF_fillPoolIfLessThan ======== + */ +static int_fast16_t RNGLPF3RF_fillPoolIfLessThan(size_t bytes) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + size_t bytesNeeded; + + if (RNGLPF3RF_instanceData.poolLevel < bytes) + { + /* + * Adjust poolLevel to ensure word alignment as underlying AES + * driver may only support output to word aligned addresses. + */ + RNGLPF3RF_instanceData.poolLevel = (RNGLPF3RF_instanceData.poolLevel >> 2u) << 2u; + + bytesNeeded = RNG_poolByteSize - RNGLPF3RF_instanceData.poolLevel; + + returnValue = RNGLPF3RF_generateEntropy((AESCTRDRBG_Handle)&RNGLPF3RF_instanceData.drbgConfig, + &RNG_instancePool[RNGLPF3RF_instanceData.poolLevel], + bytesNeeded); + + if (returnValue == RNG_STATUS_SUCCESS) + { + RNGLPF3RF_instanceData.poolLevel = RNG_poolByteSize; + } + } + + return returnValue; +} + +/* + * Precondition: RNGLPF3RF_instanceData.accessSemaphore has been taken. + * + * Updates bytesRemaining to fulfill the total request (rounded up from number of bits remaining.) + * These will have to be generated since these additional bytes could not be copied from the pool. + * + * Postcondition: If dest is not word aligned, then bytesRemaining will either be 0 or dest[byteSize-bytesRemaining] + * will be word aligned. + */ +/* + * ======== RNGLPF3RF_getEntropyFromPool ======== + */ +static int_fast16_t RNGLPF3RF_getEntropyFromPool(void *dest, size_t byteSize, size_t *bytesRemaining) +{ + + uint8_t *byteDest = (uint8_t *)dest; + size_t bytesToCopy = byteSize; + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + + if (RNGLPF3RF_instanceData.poolLevel < byteSize && ((uintptr_t)dest & 0x3u) != 0u && + RNGLPF3RF_instanceData.poolLevel < (4 - ((uintptr_t)dest & 0x3u))) + { + /* Fill pool so there will be enough entropy to get to an aligned address within dest[]. */ + returnValue = RNGLPF3RF_fillPoolIfLessThan(RNG_poolByteSize); + } + + if (RNGLPF3RF_instanceData.poolLevel < byteSize) + { + /* + * Cap number of bytes taken from pool to ensure next byte of entropy to generate into dest + * is at a word-aligned address. + */ + bytesToCopy = (4 - ((uintptr_t)dest & 0x3u)); + bytesToCopy = bytesToCopy + (((RNGLPF3RF_instanceData.poolLevel - bytesToCopy) >> 2u) << 2u); + } + + /* Get entropy from pool */ + if ((bytesToCopy > 0u) && (RNGLPF3RF_instanceData.poolLevel > 0u)) + { + (void)memcpy(byteDest, &RNG_instancePool[RNGLPF3RF_instanceData.poolLevel - bytesToCopy], bytesToCopy); + CryptoUtils_memset(&RNG_instancePool[RNGLPF3RF_instanceData.poolLevel - bytesToCopy], + RNG_poolByteSize, + 0, + bytesToCopy); + RNGLPF3RF_instanceData.poolLevel -= bytesToCopy; + } + + *bytesRemaining = byteSize - bytesToCopy; + + return returnValue; +} + +/* + * ======== RNGLPF3RF_checkRange ======== + */ +static bool RNGLPF3RF_checkRange(RNGLPF3RF_OperationParameters *opParams) +{ + return CryptoUtils_isNumberInRange(opParams->output, + opParams->outputBitLength, + opParams->endianess, + opParams->lowerLimit, + opParams->upperLimit); +} + +/* + * ======== RNGLPF3RF_getValidatedNumber ======== + */ +static int_fast16_t RNGLPF3RF_getValidatedNumber(RNG_Handle handle, + void *randomNumber, + size_t randomNumberBitLength, + CryptoUtils_Endianess endianess, + RNGLPF3RF_validator validator, + const void *lowerLimit, + const void *upperLimit) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + RNGLPF3RF_Object *object; + size_t bytesToGenerate = 0; + size_t byteSize = 0; + uint8_t *byteDestination = NULL; + uint8_t bitMask = 0; + bool isValid = false; + RNGLPF3RF_OperationParameters opParams; + + if ((handle == NULL) || (randomNumber == NULL) || (randomNumberBitLength >= RNG_MAX_BIT_LENGTH)) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + object = (RNGLPF3RF_Object *)handle->object; + + if (SemaphoreP_pend(&RNGLPF3RF_instanceData.accessSemaphore, object->timeout) != SemaphoreP_OK) + { + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + } + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + /* + * Convert bit length to byte size by rounding up the number of bytes. + * Mask the extra bits from rounding up written in the destination buffer. + */ + byteSize = (randomNumberBitLength + 7u) >> 3u; + byteDestination = (uint8_t *)randomNumber; + bitMask = (2u << (((randomNumberBitLength + 7u) % 8u))) - 1u; + } + + while ((returnValue == RNG_STATUS_SUCCESS) && !isValid) + { + + returnValue = RNGLPF3RF_getEntropyFromPool(byteDestination, byteSize, &bytesToGenerate); + + if (returnValue == RNG_STATUS_SUCCESS && bytesToGenerate > 0u) + { + returnValue = RNGLPF3RF_generateEntropy((AESCTRDRBG_Handle)&RNGLPF3RF_instanceData.drbgConfig, + &byteDestination[byteSize - bytesToGenerate], + bytesToGenerate); + } + + /* Mask off extra bits in MSB */ + if (endianess == CryptoUtils_ENDIANESS_BIG) + { + byteDestination[0] &= bitMask; + } + else + { + byteDestination[byteSize - 1u] &= bitMask; + } + + if (validator != NULL) + { + opParams.outputBitLength = randomNumberBitLength; + opParams.output = randomNumber; + opParams.endianess = endianess; + opParams.lowerLimit = lowerLimit; + opParams.upperLimit = upperLimit; + + isValid = validator(&opParams); + } + else + { + isValid = true; + } + } + + SemaphoreP_post(&RNGLPF3RF_instanceData.accessSemaphore); + + return returnValue; +} + +/* + * ======== RNGLPF3RF_createDRBGInstance ======== + */ +static int_fast16_t RNGLPF3RF_createDRBGInstance(void) +{ + int_fast16_t returnValue = RNG_STATUS_ERROR; + AESCTRDRBG_Handle drbgHandle; + AESCTRDRBG_Params drbgParams; + + AESCTRDRBG_init(); + + /* Copy RNG interrupt priority (set in syscfg) to AES CTR interrupt priority */ + RNGLPF3RF_instanceData.drbgHWattrs.aesctrHWAttrs.intPriority = RNGLPF3RF_hwAttrs.intPriority; + + RNGLPF3RF_instanceData.drbgConfig.object = &RNGLPF3RF_instanceData.drbgObject; + RNGLPF3RF_instanceData.drbgConfig.hwAttrs = &RNGLPF3RF_instanceData.drbgHWattrs; + RNGLPF3RF_instanceData.drbgObject.isOpen = false; + + AESCTRDRBG_Params_init(&drbgParams); + /* Ensure seed length will be 32 bytes long. (Seed length = key length + AES block length.) */ + drbgParams.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + drbgParams.returnBehavior = (AESCTRDRBG_ReturnBehavior)RNGLPF3RF_returnBehavior; + + drbgHandle = AESCTRDRBG_construct((AESCTRDRBG_Handle)&RNGLPF3RF_instanceData.drbgConfig, &drbgParams); + + if (drbgHandle != NULL) + { + returnValue = RNG_STATUS_SUCCESS; + } + + return returnValue; +} + +/* Store a 32-bit unsigned integer as bytes in big-endian order in memory. */ +/* + * ======== RNGLPF3RF_storeUint32InArray ======== + */ +static void RNGLPF3RF_storeUint32InArray(uint8_t *dst, uint32_t x) +{ + uint8_t *buf; + + buf = dst; + buf[0] = (uint8_t)(x >> 24U) & BYTE_MASK; + buf[1] = (uint8_t)(x >> 16U) & BYTE_MASK; + buf[2] = (uint8_t)(x >> 8U) & BYTE_MASK; + buf[3] = (uint8_t)x; +} + +/* Condition the noise input using CBC MAC to generate the seed */ +/* + * ======== RNGLPF3RF_conditionNoise ======== + */ +static int_fast16_t RNGLPF3RF_conditionNoise(uint32_t *noiseInput, uint32_t *seed) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + uint8_t *rawData; + size_t rawDataLength; + + /* CBC MAC variables */ + uint8_t keyMaterial[AES_BLOCK_SIZE]; + CryptoKey cryptoKey; + int_fast16_t cbcMacResult; + AESCMAC_Operation cbcmacOperation; + AESCMAC_Handle dynHandle; + AESCMAC_Config dynConfig; + AESCMACLPF3_Object dynObject; + const AESCMACLPF3_HWAttrs dynHWAttrs = {.intPriority = (~0)}; + AESCMAC_Params params; + + RNGLPF3RF_storeUint32InArray(keyMaterial, RNGLPF3RF_noiseConditioningKeyWord0); + RNGLPF3RF_storeUint32InArray(keyMaterial + 4, RNGLPF3RF_noiseConditioningKeyWord1); + RNGLPF3RF_storeUint32InArray(keyMaterial + 8, RNGLPF3RF_noiseConditioningKeyWord2); + RNGLPF3RF_storeUint32InArray(keyMaterial + 12, RNGLPF3RF_noiseConditioningKeyWord3); + + /* Check if the Noise input pointer was initialized */ + if (noiseInput == NULL) + { + return RNG_STATUS_NOISE_INPUT_INVALID; + } + /* Check if noise input was populated by user before calling RNG_init() */ + bool noiseFilled = CryptoUtils_isBufferAllZeros(noiseInput, AES_BLOCK_SIZE); + if (noiseFilled) + { + return RNG_STATUS_NOISE_INPUT_INVALID; + } + + rawData = (uint8_t *)noiseInput; + rawDataLength = RNGLPF3RF_noiseInputWordLen * 4; + + memset(&dynObject, 0x00, sizeof(dynObject)); + + dynConfig.object = &dynObject; + dynConfig.hwAttrs = &dynHWAttrs; + + AESCMAC_init(); + AESCMAC_Params_init(¶ms); + + params.operationalMode = AESCMAC_OPMODE_CBCMAC; + params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_POLLING; + + dynHandle = AESCMAC_construct(&dynConfig, ¶ms); + + if (dynHandle == NULL) + { + return RNG_STATUS_ERROR; + } + + /* Setup Entropy Conditioning Key */ + CryptoKeyPlaintext_initKey(&cryptoKey, keyMaterial, sizeof(keyMaterial)); + + AESCMAC_Operation_init(&cbcmacOperation); + + /* Generate 16B of seed using half the entropy*/ + cbcmacOperation.input = rawData; + cbcmacOperation.inputLength = rawDataLength / 2; + cbcmacOperation.macLength = 16; + cbcmacOperation.mac = (uint8_t *)seed; + cbcMacResult = AESCMAC_oneStepSign(dynHandle, &cbcmacOperation, &cryptoKey); + + if (cbcMacResult != AESCMAC_STATUS_SUCCESS) + { + returnValue = RNG_STATUS_ERROR; + } + + if (cbcMacResult == AESCMAC_STATUS_SUCCESS) + { + /* Generate another 16B of seed using the rest of the entropy */ + cbcmacOperation.input = rawData + rawDataLength / 2; + cbcmacOperation.mac = (uint8_t *)seed + 16; + cbcMacResult = AESCMAC_oneStepSign(dynHandle, &cbcmacOperation, &cryptoKey); + + if (cbcMacResult != AESCMAC_STATUS_SUCCESS) + { + returnValue = RNG_STATUS_ERROR; + } + } + + /* Clear noise input after conditioning */ + memset(noiseInput, 0, RNGLPF3RF_noiseInputWordLen * sizeof(uint32_t)); + + /* Destroy dynamic instance */ + AESCMAC_close(dynHandle); + + return returnValue; +} + +/* + * ======== RNG_Params_init ======== + */ +void RNG_Params_init(RNG_Params *params) +{ + *params = RNG_defaultParams; + params->returnBehavior = RNGLPF3RF_returnBehavior; +} + +/* + * ======== RNGLPF3RF_conditionNoiseToGenerateSeed ======== + */ +int_fast16_t RNGLPF3RF_conditionNoiseToGenerateSeed(uint32_t *noisePtr) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + int_fast16_t drbgResult; + uint32_t seed[256 / 32]; /* Seed is SHA256 Digest: 256 bits */ + if (RNGLPF3RF_isSeeded == false) + { + RNGLPF3RF_instanceData.poolLevel = 0; + + if (SemaphoreP_constructBinary(&RNGLPF3RF_instanceData.accessSemaphore, 1) == NULL) + { + returnValue = RNG_STATUS_ERROR; + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + returnValue = RNGLPF3RF_conditionNoise(noisePtr, seed); + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + + returnValue = RNGLPF3RF_createDRBGInstance(); + + if (returnValue == RNG_STATUS_SUCCESS) + { + drbgResult = AESCTRDRBG_reseed((AESCTRDRBG_Handle)&RNGLPF3RF_instanceData.drbgConfig, seed, NULL, 0); + returnValue = RNGLPF3RF_translateDRBGStatus(drbgResult); + CryptoUtils_memset(seed, sizeof(seed), 0, sizeof(seed)); + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + RNGLPF3RF_isSeeded = true; + } + } + } + + return returnValue; +} + +/* + * ======== RNG_init ======== + */ +int_fast16_t RNG_init(void) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + + if (RNGLPF3RF_isInitialized == false) + { + /* If the RNG driver was seeded, initialization was successful */ + if (RNGLPF3RF_isSeeded == true) + { + RNGLPF3RF_isInitialized = true; + } + } + + return returnValue; +} + +/* + * ======== RNG_construct ======== + */ +RNG_Handle RNG_construct(const RNG_Config *config, const RNG_Params *params) +{ + RNG_Handle handle; + RNGLPF3RF_Object *object; + uintptr_t key; + + handle = (RNG_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(key); + handle = NULL; + } + + if (handle != NULL) + { + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + object->timeout = RNG_defaultParams.timeout; + } + else + { + /* + * Return behavior is set statically for all instances and on open the requesting setting must + * match the static setting. + */ + if (params->returnBehavior != RNGLPF3RF_returnBehavior) + { + handle = NULL; + } + + /* + * Callback return behavior is not supported. + */ + if (params->returnBehavior == RNG_RETURN_BEHAVIOR_CALLBACK) + { + handle = NULL; + } + } + } + + return handle; +} + +/* + * ======== RNG_close ======== + */ +void RNG_close(RNG_Handle handle) +{ + RNGLPF3RF_Object *object; + + if (handle != NULL) + { + object = (RNGLPF3RF_Object *)handle->object; + object->isOpen = false; + } +} + +/* + * ======== RNG_getRandomBits ======== + */ +int_fast16_t RNG_getRandomBits(RNG_Handle handle, void *randomBits, size_t randomBitsLength) +{ + + return RNGLPF3RF_getValidatedNumber(handle, + randomBits, + randomBitsLength, + CryptoUtils_ENDIANESS_LITTLE, + NULL, + NULL, + NULL); +} + +/* + * ======== RNG_getLERandomNumberInRange ======== + */ +int_fast16_t RNG_getLERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength) +{ + + return RNGLPF3RF_getValidatedNumber(handle, + randomNumber, + randomNumberBitLength, + CryptoUtils_ENDIANESS_LITTLE, + &RNGLPF3RF_checkRange, + lowerLimit, + upperLimit); +} + +/* + * ======== RNG_getBERandomNumberInRange ======== + */ +int_fast16_t RNG_getBERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength) +{ + + return RNGLPF3RF_getValidatedNumber(handle, + randomNumber, + randomNumberBitLength, + CryptoUtils_ENDIANESS_BIG, + &RNGLPF3RF_checkRange, + lowerLimit, + upperLimit); +} + +/* + * ======== RNG_generateKey ======== + */ +int_fast16_t RNG_generateKey(RNG_Handle handle, CryptoKey *key) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + uint8_t *randomBits; + size_t randomBitsLength; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (key->u.plaintext.keyLength > (RNG_MAX_BIT_LENGTH >> 3u)) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + randomBits = key->u.plaintext.keyMaterial; + randomBitsLength = key->u.plaintext.keyLength << 3u; /* Bytes to bits */ + + returnValue = RNGLPF3RF_getValidatedNumber(handle, + randomBits, + randomBitsLength, + CryptoUtils_ENDIANESS_LITTLE, + NULL, + NULL, + NULL); + } + + return returnValue; +} + +/* + * ======== RNG_generateLEKeyInRange ======== + */ +int_fast16_t RNG_generateLEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength) +{ + int_fast16_t returnValue; + uint8_t *randomBits; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + else + { + + randomBits = key->u.plaintext.keyMaterial; + + returnValue = RNGLPF3RF_getValidatedNumber(handle, + randomBits, + randomNumberBitLength, + CryptoUtils_ENDIANESS_LITTLE, + &RNGLPF3RF_checkRange, + lowerLimit, + upperLimit); + } + + return returnValue; +} + +/* + * ======== RNG_generateBEKeyInRange ======== + */ +int_fast16_t RNG_generateBEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength) +{ + int_fast16_t returnValue; + uint8_t *randomBits; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + else + { + randomBits = key->u.plaintext.keyMaterial; + + returnValue = RNGLPF3RF_getValidatedNumber(handle, + randomBits, + randomNumberBitLength, + CryptoUtils_ENDIANESS_BIG, + &RNGLPF3RF_checkRange, + lowerLimit, + upperLimit); + } + + return returnValue; +} + +/* + * ======== RNG_fillPoolIfLessThan ======== + */ +int_fast16_t RNG_fillPoolIfLessThan(size_t bytes) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + + if (SemaphoreP_pend(&RNGLPF3RF_instanceData.accessSemaphore, SemaphoreP_WAIT_FOREVER) != SemaphoreP_OK) + { + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + returnValue = RNGLPF3RF_fillPoolIfLessThan(bytes); + + SemaphoreP_post(&RNGLPF3RF_instanceData.accessSemaphore); + } + + return returnValue; +} + +/* + * ======== RNG_cancelOperation ======== + */ +int_fast16_t RNG_cancelOperation(RNG_Handle handle) +{ + /* Cancel not supported in this implementation since AESCTRDRBG driver does not support cancellation. */ + return RNG_STATUS_ERROR; +} diff --git a/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.h b/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.h new file mode 100644 index 00000000..3f6dd580 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rng/RNGLPF3RF.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file RNGLPF3RF.h + * + * @brief RNG driver implementation for the CC23X0 family + * + * This file should only be included in the board file to fill the RNG_config + * structure. + * + * The CC23X0 family does not have a general purpose TRNG. However, it can + * collect radio noise when the radio is not being used (such as during boot) + * and use that noise as a source for a seed for an AES CTR DRBG. + * + * The radio noise is first processed using AES CBC MAC in order to compress + * the entropy of the noise into a 256 bit value with close to 256 bits of + * entropy. That 256 bit value is then used as the seed value for the AES CTR + * DRBG. + * + * The RNG driver then uses the AES CTR DRBG to fulfill any requests for + * entropy. + * + * In order to ensure proper operation, RNG_init() must be called prior to to + * any other use of the radio. Because other drivers may be using the RNG + * driver, it is recommended that RNG_init() be called as part of the + * application's startup routines. + * + * @note This implementation does not support the RNG_RETURN_BEHAVIOR_CALLBACK + * return mode. + * + * @note This implementation treats RNG_RETURN_BEHAVIOR_POLLING as + * RNG_RETURN_BEHAVIOR_BLOCKING. + */ + +#ifndef ti_drivers_rng_RNGLPF3RF__include +#define ti_drivers_rng_RNGLPF3RF__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Word length of the noise input from RCL */ +extern const uint32_t RNGLPF3RF_noiseInputWordLen; + +/*! \cond Internal APIs */ + +/*! + * @brief RNGLPF3RF Object + * + * \note The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + uint32_t timeout; +} RNGLPF3RF_Object; + +typedef struct +{ + uint8_t intPriority; +} RNGLPF3RF_HWAttrs; + +/*! + * @brief Conditions the noise buffer from RCL and seed the RNG. + * + * This function conditions the provided RCL (Radio) noise + * using CBC MAC to generate a 256-bit seed which is used seed the RNG driver. + * + * The noise input is read from RCL using RCL_AdcNoise_get_samples_blocking(). + * The minimum word length of the noise input is 80 words to generate a 256-bit seed. + * The user must ensure #RNGLPF3RF_conditionNoiseToGenerateSeed() is called before #RNG_init(), otherwise + * RNG driver initialization will fail. + * + * @param noisePtr A pointer to the buffer containing noise input from RCL + * + * @retval #RNG_STATUS_SUCCESS RNG driver was successfully seeded. + * @retval #RNG_STATUS_NOISE_INPUT_INVALID RNG driver was not seeded as the noise input was invalid + */ +int_fast16_t RNGLPF3RF_conditionNoiseToGenerateSeed(uint32_t *noisePtr); + +/*! \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_rng_RNGLPF3RF__include */ diff --git a/simplelink_lpf3/source/ti/drivers/utils/List.c b/simplelink_lpf3/source/ti/drivers/utils/List.c index 970ae162..7e7ca480 100644 --- a/simplelink_lpf3/source/ti/drivers/utils/List.c +++ b/simplelink_lpf3/source/ti/drivers/utils/List.c @@ -53,8 +53,6 @@ void List_clearList(List_List *list) HwiP_restore(key); } - - /* * ======== List_get ======== */ @@ -68,12 +66,15 @@ List_Elem *List_get(List_List *list) elem = list->head; /* See if the List was empty */ - if (elem != NULL) { + if (elem != NULL) + { list->head = elem->next; - if (elem->next != NULL) { + if (elem->next != NULL) + { elem->next->prev = NULL; } - else { + else + { list->tail = NULL; } } @@ -83,7 +84,6 @@ List_Elem *List_get(List_List *list) return (elem); } - /* * ======== List_insert ======== */ @@ -95,10 +95,12 @@ void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) newElem->next = curElem; newElem->prev = curElem->prev; - if (curElem->prev != NULL) { + if (curElem->prev != NULL) + { curElem->prev->next = newElem; } - else { + else + { list->head = newElem; } curElem->prev = newElem; @@ -106,7 +108,6 @@ void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) HwiP_restore(key); } - /* * ======== List_put ======== */ @@ -118,10 +119,12 @@ void List_put(List_List *list, List_Elem *elem) elem->next = NULL; elem->prev = list->tail; - if (list->tail != NULL) { + if (list->tail != NULL) + { list->tail->next = elem; } - else { + else + { list->head = elem; } @@ -141,10 +144,12 @@ void List_putHead(List_List *list, List_Elem *elem) elem->next = list->head; elem->prev = NULL; - if (list->head != NULL) { + if (list->head != NULL) + { list->head->prev = elem; } - else { + else + { list->tail = elem; } @@ -163,18 +168,22 @@ void List_remove(List_List *list, List_Elem *elem) key = HwiP_disable(); /* Handle the case where the elem to remove is the last one */ - if (elem->next == NULL) { + if (elem->next == NULL) + { list->tail = elem->prev; } - else { + else + { elem->next->prev = elem->prev; } /* Handle the case where the elem to remove is the first one */ - if (elem->prev == NULL) { + if (elem->prev == NULL) + { list->head = elem->next; } - else { + else + { elem->prev->next = elem->next; } diff --git a/simplelink_lpf3/source/ti/drivers/utils/List.h b/simplelink_lpf3/source/ti/drivers/utils/List.h index ccba687c..8baf0dbd 100644 --- a/simplelink_lpf3/source/ti/drivers/utils/List.h +++ b/simplelink_lpf3/source/ti/drivers/utils/List.h @@ -123,12 +123,14 @@ extern "C" { #endif -typedef struct List_Elem_ { +typedef struct List_Elem_ +{ struct List_Elem_ *next; struct List_Elem_ *prev; } List_Elem; -typedef struct { +typedef struct +{ List_Elem *head; List_Elem *tail; } List_List; @@ -187,8 +189,7 @@ static inline List_Elem *List_head(List_List *list) * @param curElem Elem to insert the newElem in front of. * This value cannot be NULL. */ -extern void List_insert(List_List *list, List_Elem *newElem, - List_Elem *curElem); +extern void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem); /*! * @brief Function to return the next elem in a linked list diff --git a/simplelink_lpf3/source/ti/drivers/utils/Random.c b/simplelink_lpf3/source/ti/drivers/utils/Random.c new file mode 100644 index 00000000..1d45e4d9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/Random.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Random.c ======== + */ + +#include +#include + +#include +#include +#include +#include + +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + #include + #include + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + #include + #include +#endif + +#define STATE_SIZE_IN_WORDS 5 + +static uint32_t state[STATE_SIZE_IN_WORDS]; + +/* + * ======== Random_seedAutomatic ======== + */ +int_fast16_t Random_seedAutomatic(void) +{ + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + TRNGCC26XX_Object object = {0}; + TRNG_Params params; + CryptoKey seedKey; + int_fast16_t status; + + /* Use minimum TRNGCC26XX_SAMPLES_PER_CYCLE_MIN since + * we do not need the full amount of entropy and only need + * to kickstart the PRNG. + */ + const TRNGCC26XX_HWAttrs hwAttrs = { + .samplesPerCycle = TRNGCC26XX_SAMPLES_PER_CYCLE_MIN, + .intPriority = ~0, + }; + + /* Allocate TRNG instance on the stack since we will not need it + * hereafter. This also helps avoid problems with hardcoded indexes. + */ + TRNG_Config config = {.object = &object, .hwAttrs = &hwAttrs}; + + params.returnBehavior = TRNG_RETURN_BEHAVIOR_POLLING; + + TRNG_init(); + + TRNG_Handle handle = TRNG_construct(&config, ¶ms); + + if (!handle) + { + return Random_STATUS_ERROR; + } + + CryptoKeyPlaintext_initBlankKey(&seedKey, (uint8_t *)state, sizeof(state)); + + status = TRNG_generateEntropy(handle, &seedKey); + + TRNG_close(handle); + + if (status != TRNG_STATUS_SUCCESS) + { + return Random_STATUS_ERROR; + } + + return Random_STATUS_SUCCESS; + +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + RNG_Config rngConfig; + RNG_Handle rngHandle; + RNG_Params rngParams; + RNGLPF3RF_Object rngObject = {0}; + + int_fast16_t status; + + /* + * Note: For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps, before using Random_seedAutomatic() and prior to the use of the Radio. + * 1. Read radio noise using RCL_AdcNoise_get_samples_blocking(). This RCL function must + * be called from a task context with interrupts enabled and therefore cannot be called + * by startup code. This must be executed prior to the use of the radio. + * 2. Condition the noise to seed the RNG using RNGLPF3RF_conditionNoiseToGenerateSeed(). + * 3. Initialize the RNG from the application with RNG_init() + * RNG_init() need not be called again here or by any other code. + */ + rngConfig.object = &rngObject; + rngConfig.hwAttrs = NULL; + + RNG_Params_init(&rngParams); + + rngHandle = RNG_construct(&rngConfig, &rngParams); + + if (!rngHandle) + { + return Random_STATUS_ERROR; + } + + status = RNG_getRandomBits(rngHandle, &state, sizeof(state) * 8); + + RNG_close(rngHandle); + + if (status != RNG_STATUS_SUCCESS) + { + return Random_STATUS_ERROR; + } + + return Random_STATUS_SUCCESS; +#else + + /* If neither a TRNG nor a unique ID are available, use a constant */ + state[0] = 0x00000001; + state[1] = 0x00000002; + state[2] = 0x00000003; + state[3] = 0x00000004; + state[4] = 0x00000005; + + return Random_STATUS_SUCCESS; +#endif +} + +/* + * ======== Random_seedManual ======== + */ +void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]) +{ + uintptr_t key; + + key = HwiP_disable(); + + memcpy(state, seed, sizeof(state)); + + HwiP_restore(key); +} + +/* + * ======== Random_getNumber ======== + */ +uint32_t Random_getNumber(void) +{ + uintptr_t key; + uint32_t s; + uint32_t v; + uint32_t result; + + key = HwiP_disable(); + + /* "xorwow" XOR shift PRNG from section 3.1 of Marsaglia's "Xorshift RNGs" paper */ + v = state[3]; + + v ^= v >> 2; + v ^= v << 1; + + state[3] = state[2]; + state[2] = state[1]; + state[1] = state[0]; + s = state[0]; + + v ^= s; + v ^= s << 4; + + state[0] = v; + + state[4] += 362437; + + result = v + state[4]; + + HwiP_restore(key); + + return result; +} + +/* + * ======== Random_getBytes ======== + */ +void Random_getBytes(void *buffer, size_t bufferSize) +{ + uint32_t i; + uint32_t randomNumber; + + for (i = 0; i < bufferSize / sizeof(uint32_t); i++) + { + ((uint32_t *)buffer)[i] = Random_getNumber(); + } + + randomNumber = Random_getNumber(); + + memcpy((uint32_t *)buffer + bufferSize / sizeof(uint32_t), &randomNumber, bufferSize % sizeof(uint32_t)); +} diff --git a/simplelink_lpf3/source/ti/drivers/utils/Random.h b/simplelink_lpf3/source/ti/drivers/utils/Random.h new file mode 100644 index 00000000..d2e452a3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/utils/Random.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file Random.h + * + * @brief Interface to generate pseudo-random numbers + * + * @warning The numbers generated by this module are not crpytographically-secure! + * Do not use this module to generate keying material or for other + * security-related purposes! + * + * This module generates non-cryptographically-secure random numbers in an + * easy to use and fast way. + * + * There is a single global state that must be initialised by calling + * Random_seedAutomatic() or Random_seedManual(). Afterwards, you can call + * Random_getNumber() or Random_getBytes() as desired. Both are thread-safe + * and protect the internal state. + * + * The pseudo-random number generator used is the "xorwow" algorithm specified in + * Marsaglia's "Xorshift RNGs" paper. It keeps 20 bytes of state that must be + * seeded and has a period of 2^160 - 2^32 before a sequence wraps. + * + * Generating a random number with this algorithm is quite fast. Random_getNumber() + * only requires 82 instructions which is 1.7us on a 48MHz Cortex M4. That includes + * disabling interrupts. + * + * @code + * + * int_fast16_t status; + * uint32_t randomNumber; + * + * status = Random_seedAutomatic(); + * + * if (status != Random_STATUS_SUCCESS) { + * while(1); + * } + * + * randomNumber = Random_getNumber(); + * + * @endcode + * + * + */ + +#ifndef ti_drivers_utils_Random__include +#define ti_drivers_utils_Random__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define Random_STATUS_SUCCESS (0) +#define Random_STATUS_ERROR (-1) + +/*! @brief Length of the seed in bytes */ +#define Random_SEED_LENGTH (20) + +/** + * @brief Seed internal state automatically + * + * This function seeds or reseeds the internal state. + * The method for generating the seed is device dependent. + * + * If a TRNG is available, it will be used to generate the seed. + * + * If a TRNG is not available, information unique to the device running + * the code will be used. This may be a unique device identifier or other + * information such as a MAC address. + * Since the seed is constant per device for devices without a TRNG, the + * number sequence will restart after each call to Random_seedAutomatic(). + * This will usually occur after rebooting the device. + * + * For CC23X0, RNG will be used to generate the seed, where the application needs to + * perform additional steps for initializing the RNG driver. + * + * If neither a TRNG nor a unique device identifier is available, + * a constant will be used. + * + * @return Returns a status code + * + * @sa Random_seedManual() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern int_fast16_t Random_seedAutomatic(void); + +/** + * @brief Set the internal state to a specified seed + * + * This function sets the internal state to the seed specified + * by the application. + * + * @param seed Seed to set the internal state to + * + * @sa Random_seedAutomatic() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]); + +/** + * @brief Returns a random number + * + * This function returns a random number and updates the + * internal state. + * + * @return Returns random number + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern uint32_t Random_getNumber(void); + +/** + * Returns a number of random bytes + * + * This is a convenience function that fills the specified + * array with random bytes by repeatedly calling Random_getNumber(). + * + * @param buffer Buffer to fill with random bytes + * + * @param bufferSize Size of buffer. Any value is permitted, including + * those that are not multiples of sizeof(uint32_t). + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern void Random_getBytes(void *buffer, size_t bufferSize); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_Random__include */ diff --git a/simplelink_lpf3/source/ti/log/Log.h b/simplelink_lpf3/source/ti/log/Log.h new file mode 100644 index 00000000..c0bef508 --- /dev/null +++ b/simplelink_lpf3/source/ti/log/Log.h @@ -0,0 +1,1045 @@ +/* + * Copyright (c) 2019-2024 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file ti/log/Log.h + * + * @addtogroup ti_log_LOG Log Interface + * + * @brief The Log module provides APIs to instrument source code + * + * To access the LOG APIs, the application should include its header file as + * follows: + * @code + * #include + * @endcode + * + * ## Beta Disclaimer ## + * The logging ecosystem are to be considered beta quality. They are not + * recommended for use in production code by TI. APIs and behaviour will change + * in future releases. Please report issues or feedback to [__E2E__][e2e]. + * + * [e2e]: https://e2e.ti.com/ + * + * ## Definitions ## + * + * The following terms are used throughout the log documentation. + * + * | Term | Definition | + * |---------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| + * | `LogModule` | A parameter passed to Log APIs to indicate which software module the log statement originated from. Modules also control the routing of logs to sinks. | + * | `LogLevel` | The severity or importance of a given log statement. | + * | `Sink` | Also simply called a logger. This is a transport specific logger implementation.
The Logging framework is flexible such that multiple sinks may exist in a single firmware image. | + * | `CallSite` | A specific invocation of a Log API in a given file or program. | + * | `Record` | The binary representation of a log when it is stored or transported by a given sink. The log record format varies slightly with each sink depending on their implementation and needs. However, they all convey the same information. | + * | Link Time Optimization (LTO) | A feature of some toolchains that can significantly reduce the code overhead of the log statements through a process called dead code elimination. In order to maximize the benefits of this, all static libraries and application files should have LTO enabled. | + * + * ## Summary ## + * + * The following sections describe the usage of the TI logging system + * implementation. This document will focus on the target (i.e. code that runs) + * on the embedded device. For associated PC tooling, please see the + * [README](../../../tools/log/tiutils/Readme.html) in the tools/log/tiutils/ + * folder. + * + * Design Philosophy: + * + * * Logs target code should be as efficient as possible. + * * This means that Log APIs should minimize FLASH, RAM, and execution + * overhead. + * * Complexity should be pushed to host side tooling where possible. + * * Even if this means that PC setup/tooling requirements are more complex. + * * Multiple log sink implementations shall be able to exist in a system. + * * Where applicable, multiple instances should be supported (e.g. multiple + * circular buffers to collect logs) + * * It shall be possible to remove logging entirely using the preprocessor + * * Configuration of logging should be deferred to application compile and + * link time. + * * That means that the end application builder should make decisions about + * the logging settings. This means that TI provided libraries are not + * opinionated about what log levels should be enabled or how modules + * should be routed to sinks. + * * TI's logging system will leverage SysConfig out of the box, but it should + * be possible to configure and use logging easily without the needing + * SysConfig. + * + * ## Stated Limitations ## + * + * * It is not possible to control which log sink is used for each call site. + * Routing of logs is controlled at a module level. + * * A maximum of 8 arguments is supported for variadic APIs. + * + * ## Anatomy of Log Statement ## + * + * At the core of the logging implementation is heavy use of the C + * preprocessor. When reading an application, the Log APIs may look like + * function calls, but the preprocessor expands them heavily. + * + * There are several ways in which the preprocessor is used. + * + * ### Global ### + * 1. To enable/disable logs globally. If `ti_log_Log_ENABLE` is not defined, + * all statements are removed by the preprocessor. This does not rely on LTO + * or any other optimization. It removes any traces of logs from the + * program. + * + * This define is pushed to `ti_utils_build_compiler.opt` whenever any Log + * module is enabled in SysConfig. + * + * ### Module ### + * 1. To enable/disable logs by module. If + * `ti_log_Log_ENABLE_=1` is not defined, all statements + * using that Log module are removed by the preprocessor. This does not rely + * on LTO or any other optimization. Removing the define removes all traces + * of the log from the compiled code. Just defining the symbol name + * `ti_log_Log_ENABLE_` without setting it to 1 will not + * include Log statements during compilation. + * + * These defines are automatically pushed to `ti_utils_build_compiler.opt` + * for all modules configured in SysConfig. + * + * Some TI libraries that have logging enabled also contain multiple log + * modules. Enabling only a subset of Log modules via the preprocessor will + * not cause the Log statements associated with the remaining Log modules to + * be removed since this is a compile-time event. The Log statements + * associated with individual modules can be removed from logging-enabled TI + * libraries by recompiling those libraries without the module-level flags + * in question. + * + * ### Per Log Statement ### + * 1. (Level filtering): Insert the if statement that checks if the log level + * of the statement has been enabled in its module configuration. If the log + * level is not enabled, the process ends here. + * + * 2. (String declaration): Automate placement of constant strings, format + * strings, and pointers to these strings in the the nonloadable metadata + * section of the out file. This saves FLASH on the target. Each string + * contains a large amount of data, including the following: + * + * * File and line number of the log statement + * * The log level and module of the log statement + * * The format string + * * The number of arguments + * + * 3. (Argument counting): Log APIs are variadic in nature, up to 8 arguments + * are supported. However, at preprocess time, the number of arguments must + * be known. + * + * 4. (Name spacing): Routing from module to sink. The module parameter of the + * Log API controls which sink its log statements will be routed to. The + * preprocessor does name expansion to look up the enabled log levels and + * selected sink function pointers from the module's configuration + * structure. NOTE: The used sink may require initialization. Please verify + * with the specific sink documentation on how to initialize the sink. + * + * 5. (Sink API Invocation): With the names resolved and levels checked, the + * logger is now ready to execute the sink function. This is done via + * function pointer. + * + * An simplified pseudo-C implementation of what `Log_printf(LogModule_App1, + * Log_DEBUG, "Hello World!");` would expand to is shown below. This will not + * compile and is not extensive, just for illustration. + * + * @code + * // Global log enable check, wrapped around each log site + * #if defined(ti_log_Log_ENABLE) + * #if ti_log_Log_ENABLE_LogModule_App1 == 1 + * // Check if the level of this specific log statement has been enabled by the module + * if (LogMod_LogModule_App1.levels & level) { + * // Note that ^^ is the record separator. Pack meta information into format string. This is stored off target. + * const string logMeta = "LOG_OPCODE_FORMATED_TEXT^^"../../log.c"^^80^^Log_DEBUG^^LogMod_LogModule_App1^^"Hello World!"^^0"; + * // Route log to the selected sink implementation. This is done via function pointer. + * // The 0 indicates no arguments. If runtime arguments were provided, they would follow. + * LogMod_LogModule_App1.printf(pointerToModuleConfig, 0); + * } + * #endif + * #endif + * @endcode + * + * From here, the logger has transferred control over to the sink + * implementation, which varies based on the transport (e.g. circular buffer in + * memory or UART). + * + * ## Modules ## + * + * When adding log statements to the target software, it is recommended to + * create a logging module for each software component in the image. Modules + * enable the reader to understand where the log record originated from. Some + * log visualizers may allow the reader to filter or sort log statements by + * module. It is also recommended to namespace modules. + * + * For example, a good module name for the `UART` driver that exists in + * `source/ti/drivers`, could be `ti_drivers_UART`. + * + * Modules also control the routing of log records to a sink. Routing is + * controlled via the LogModule panel in SysConfig, but can be changed in plain + * C code using the macro @ref Log_MODULE_DEFINE and passing the sink specific + * `Log_MODULE_INIT_` to the `init` parameter within the @ref Log_MODULE_DEFINE + * macro. An example for the LogBuf sink is below, it will do the following + * + * 1. Create a module called `LogModule_App1`. + * 1. Initialize the module for use with the buffer based LogSink. Use buffer + * instance called `CONFIG_ti_log_LogSinkBuf_0`. + * 1. Enable only the `Log_ERROR` level. Other logs will not be stored. + * + * @code + * #include + * #include + * Log_MODULE_DEFINE(LogModule_App1, Log_MODULE_INIT_SINK_BUF(CONFIG_ti_log_LogSinkBuf_0, Log_ERROR)); + * @endcode + * + * TI created libraries will never use @ref Log_MODULE_DEFINE. This leaves the + * choice of routing logs to their sinks to the end application writer. This is + * recommended when creating any static libraries to defer the final logging + * decisions to link time. + * + * Each new module will instantiate a Log_Module structure with a `levels` + * bitmap and pointers to the selected sink implementation and sink + * configuration. See the @ref Log_Module structure for more information. + * + * ## Levels ## + * Log levels are a way to indicate the severity or importance of the contents + * of a particular log call site. Each call site takes an argument that allows + * the user to specify the level. As with modules, log visualization tools + * allow the user to sort or filter on a given level. This can help the reader + * to find important or relevant log statements in visualization. + * + * Log levels are also used to control the emission of logs. Each call site + * will check that the level is enabled before calling the underlying log API. + * + * Depending on optimization, the check at each log statement for whether the + * given level is enabled or not may end up being optimized away, and the + * entire log statement may be optimized away if the log level is not enabled. + * + * @code + * if ((level) & module.levels) {// Call Log API + * } + * @endcode + * + * Optimization level `-flto` for both the TICLANG toolchain and GCC will + * typically be able to optimize the above statement. + * + * @remark + * + * ## Log Metadata ## + * + * Each time a Log API is invoked, a metadata string is placed in the .out + * file. This string contains information about the API type, file, line + * module, level, and other information associated with the log call site. Each + * call site emits a string to a specific memory section called `.log_data`. In + * addition to this, a pointer to the string in .log_data is stored in another + * section called `.log_ptr`. Because the .log_ptr section is always in the + * same location, and each entry is the same size, an indexing-scheme can be + * used to refer to each log-string. Entry 0 in .log_ptr would point to the + * first string, entry 1 would point to the second string, etc. This Is + * necessary on some devices where transmitting an entire 32-bit address as a + * reference to the string is not possible, and instead an 8-bit index can be + * transmitted across the Log sink implementation instead. In order to use + * logging, this section should be added to the linker command file. By + * default, this section points to a nonloadable region of memory. Meaning that + * the metadata will not be loaded on the target device. Instead, the various + * logging visualization tools such as wireshark and TI ROV2 will read the + * metadata from this section and properly decode the log statements. The + * benefit of this approach is that very little memory is consumed on target. + * Additionally, the log transport only needs to store or send pointers to this + * meta section when a log API is called. + * + * This approach minimizes the amount of memory consumed on device and bytes + * sent over the transport. This section can be loaded on target if desired or + * if you are creating a custom logger. The design does not preclude this. + * + * In order to use the logging framework, the log section must be added to the + * linker command file. Here is a sample for the TI linker. Other examples can + * be found in the TI provided linker files for each toolchain. + * + * @code + * MEMORY + * { + * // List other memory regions here + * LOG_DATA (R) : origin = 0x90000000, length = 0x40000 + * LOG_PTR (R) : origin = 0x94000008, length = 0x40000 + * } + * SECTIONS + * { + * .log_data : > LOG_DATA, type = COPY + * .log_ptr : { *(.log_ptr*) } > LOG_PTR align 4, type = COPY + * } + * @endcode + * + * ## Sinks ## + * + * Sinks are responsible for storing or transporting the log record. In general + * there are two categories of sinks: + * + * 1. Those that perform storage of logs. + * 2. Those that stream logs over a transport medium, and thus do not perform + * storage. + * + * Sinks may vary in their implementation based on the nature of the storage or + * transport that they support, but they all have the following in common: + * + * * Are named ti_log_LogSink. Where `` is the name of the + * sink. + * * Must implement the Log_printf and Log_buf APIs from this file. + * * Must provide _USE, _INIT, and _DEFINE macros. + * + * In addition, some sinks require initialization. This will be listed in the + * documentation for the sink implementation. Sinks are closely tied to their + * associated host side tooling. Since the log statements are not parsed at all + * by the target code, this must be delegated to a program running on a PC. + * While the binary format of log records may vary across sink implementations, + * it is suggested that each log record contain: + * + * 1. Timestamp + * 1. Pointer to metadata string. This will be looked up by the PC side tooling + * in the out file. + * 1. Runtime arguments + * + * This is the minimum amount of information needed to decode a log statement. + * + * # Usage # + * This section provides a basic @ref ti_log_LOG_Synopsis "usage summary" and a + * set of @ref ti_log_LOG_Examples "examples" in the form of commented code + * fragments. Detailed descriptions of the LOG APIs are provided in subsequent + * sections. + * + * @anchor ti_log_LOG_Synopsis + * ### Synopsis ### + * + * @code + * // Import the Log header + * #include + * + * // Define your log module and log sink + * // If using SysConfig, it will be done automatically, or it can be done manually: + * // Use helper macro from to make a sink instance (buffer + config) with 100 entries. + * Log_SINK_BUF_DEFINE(MyBufferSink, LogSinkBuf_Type_CIRCULAR, 100); + * + * // Use helper macro from to make a module pointing at the new sink instance. + * // This example will enable all log levels + * Log_MODULE_DEFINE(MyModule, Log_MODULE_INIT_SINK_BUF(MyBufferSink, Log_ALL)) + * + * // Some log sinks may require special initialization to configure hardware. Refer to the documentation of + * // the sink you wish to use. For example, LogSinkITM must be initialised like this before it can be used: + * // LogSinkITM_init(); + * + * // Invoke one of the log APIs you want to use for either pre-defined events or formatted strings + * Log_printf(MyModule, Log_DEBUG, "The answer is %d", 42); + * uint8_t buffer[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + * Log_buf(MyModule, Log_VERBOSE, buffer, sizeof(buffer)); + * @endcode + * + * + * + * @anchor ti_log_LOG_Examples + * ### Examples ### + * * @ref ti_utils_LOG_Example_event "Log Event" + * * @ref ti_utils_LOG_Example_printf "Log printf" + * * @ref ti_utils_LOG_Example_buf "Logging buffers" + * + * @anchor ti_utils_LOG_Example_event **Log Event**: + * + * The following example demonstrates how to create a log event object and use + * it in the code. There are two steps to using a log event: 1. instantiation + * and 2. call site(s). Instantiation creates the event and the necessary + * metadata, and call site is where the event is actually recorded by the + * logger framework. + * + * @code + * // Create a log event data type called LogEvent_count + * // The log module is MyModule + * // The format string is "count=%d" -- this should describe what the event does + * + * Log_EVENT_DEFINE(LogEvent_count, "count=%d"); + * @endcode + * + * Later on, in the application, the count event is consumed. Note the log + * module must match between event creation and call site. In the code below, a + * LogEvent record is created for serialization or stage by the Log sink. + * + * @code + * Log_EVENT_USE(LogEvent_count); // If not defined in same file + * // ... + * Log_event(MyModule, Log_DEBUG, LogEvent_count, count++); + * @endcode + * + * @anchor ti_utils_LOG_Example_printf **Log Printf**: + * + * The following example demonstrates use of the Log printf API. in code. Log + * will embed the format string in the call site and will take arguments using + * varadic arguments. + * + * @code + * Log_printf(MyModule, Log_DEBUG, "Hello World!"); + * @endcode + * + * The arguments are type-casted into a uintptr_t, which is an unsigned integer + * type. This limits the supported format specifiers to the following: + * - Unsigned decimal integer: \%u + * - Unsigned hexadecimal integer: \%x + * - Unsigned hexadecimal integer (capital letters): \%X + * - Character: \%c + * - Signed decimal integer for positive values: \%i, \%d + * - Signed octal for positive values: \%o + * + * @anchor ti_utils_LOG_Example_buf **Log Buf**: + * + * The following example demonstrates use of the Log buf API. in code. + * + * Buf will embed the format string in the call site and will take the buffer + * as a pointer and length. Buffers are treated as arrays of bytes. The buffer + * API should only be used when it is necessary to log data that is only + * available at runtime. It will actually send or store the entire contents of + * the buffer, so this API should be used sparingly as it is costly in terms of + * runtime and memory overhead. + * + * @code + * uint8_t bufferToLog[] = {0, 1, 2, 3, 4, 5}; + * Log_buf(ti_log_LogMain, Log_DEBUG, "The contents of bufferToLog are: ", bufferToLog, sizeof(bufferToLog)); + * @endcode + * + * @anchor ti_utils_LOG_Example_guide **Log API usage**: + * + * For a uniform experience with the logging tool, users are recommended to + * follow certain guidelines regarding the Log API. Typical use-cases for each + * API call is described below + * + * #### Log_printf #### + * + * Log_printf should be the default mechanism for emitting a log statement + * within an application. Along with the Log-levels, Log_printf should be used + * to communicate debug information as a formatted string, which accepts + * variadic arguments. In this case, a pointer to the string and the arguments + * themselves are transported by the Log sink. + * + * @code + * Log_printf(MyLibraryLogModule, Log_ERROR, "Library function received illegal argument: %d", arg); + * @endcode + * + * #### Log_event #### + * + * Log_event is meant to represent more generic debug-information, and + * typically something that can occur from anywhere in the application, as + * opposed to being localized in a single library. Events can also be defined + * once and referenced from anywhere in the application, so the same event can + * be used by multiple libraries. A generic example would be an event such as + * "Entering critical section" + * + * @code + * Log_EVENT_DEFINE(LogEvent_enterCritical, "Entering critical section"); + * + * Log_EVENT_USE(LogEvent_enterCritical); // If not defined in same file + * // ... + * Log_event(MyModule, Log_DEBUG, LogEvent_enterCritical); + * @endcode + * + * #### Log_buf #### + * + * When the debug-information to be emitted is a large amount of dynamic data, + * and is not suitable as an argument to printf, then Log_buf should be used. + * Log_buf can transport the contents of large dynamic buffers, and as a + * consequence has a larger overhead and should be used sparsely. + */ + +#ifndef ti_log_Log__include +#define ti_log_Log__include + +/*! @ingroup ti_log_LOG */ +/*@{*/ + +/* + * ======== Log.h ======== + * @brief Contains Log library APIs + */ +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/* + * ======== ti_log_Log_ENABLE ======== + * Enable instrumentation using link-time optimization implementation + * + * Define this symbol to add instrumentation at compile time. + * It must be defined before including this header file. + */ +#if ti_log_Log_ENABLE +/* + * ============================= + * ======== Log Enabled ======== + * ============================= + */ + +#define Log_TI_LOG_VERSION 0.1.0 +/** + * @brief Defines a log module + * + * Log modules are like namespaces for log statements, but also controls the + * enabled log levels and decides where the log statement is redirected. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + * @param[in] init Initialization macro from the wanted sink + * + * This is a helper to define `Log_Module LogMod_yourName` and initialize it + * with the configuration and functions of the wanted log sink. + * + * For example, you have already used the sink definition macros found in + * LogSinkITM.h, and now you want to define a new module that uses this: + * + * `Log_MODULE_DEFINE(MyDriver, Log_MODULE_INIT_SINK_ITM(Log_DEBUG | Log_ERROR))` + * + * Perhaps you used the LogSinkBuf.h helper macro which needs a unique name + * per instance and made a separate buffer for critical errors: + * + * `Log_MODULE_DEFINE(MyCritical, Log_MODULE_INIT_SINK_BUF(criticalBuf, Log_ERROR)` + * + * You would use this in your application via + * `Log(MyCritical, Log_ERROR, "Oops")` + */ +#define Log_MODULE_DEFINE(name, init) const Log_Module LogMod_ ## name = init + +/** + * @brief Defines Log module as weak + * + * If there are multiple modules containing Log statements per library, + * special care must be taken not to create link-time failures. + * Whether Log statements from a library are present in the final binary is + * determined by the library configuration the application links against + * (instrumented vs uninstrumented). + * Each Log statement has a link-time dependency on its Log module. Enabling + * only a subset of Log modules contained within the library will cause any + * Log statements from other Log modules of that library to fail at link-time. + * This is avoided by declaring a weak instance of each Log module in C code + * that is compiled into the library. That way, the SysConfig-generated Log + * module definitions will override the weak library ones but they are there + * if SysConfig does not define that particular module. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + * @param[in] init Initialization value of the Log_Module struct. + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define Log_MODULE_DEFINE_WEAK(name, init) const __weak Log_Module LogMod_ ## name = init +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define Log_MODULE_DEFINE_WEAK(name, init) const Log_Module LogMod_ ## name __attribute__((weak)) = init +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +a supported compiler." +#endif + +/** + * @brief Declares a reference to a log module + * + * Declares that a log module is defined in another file so that it can be + * used in the file with this macro in it. + * + * @note This is done automatically for `Log` and `Log_buf` statements. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + */ +#define Log_MODULE_USE(name) extern const Log_Module LogMod_ ## name + +/** + * @brief Resolves to the symbol name of the log module + * + * Provided for forward compatibility purposes should you have a need to + * reference the log module symbol directly. + */ +#define LOG_MODULE_SYM(name) LogMod_ ## name + +/** @cond NODOC */ + +/* This macro protects against side effects of the C preprocessor expansion + * of log statements. Each log API should be guarded by it. + * An article explaining this behavior can be found here: + * https://gcc.gnu.org/onlinedocs/cpp/Swallowing-the-Semicolon.html + */ +#define _Log_GUARD_MACRO(x) do{ x }while(0) + +/* + * + * ======== Log Private Macros ======== + * + * The following macros are intended to be private to the log module and + * are not intended for use by the user. Private macros will start with _Log. + * + * In the case of multi level macros (macros that invoke other macros), a + * letter is appended at the end of the definition. With each level of nesting, + * the appended letter is incremented. + * + * For example: _Log_test --> _Log_test_A --> _Log_test_B + */ +/* Extracts the first/remaining argument from __VA_ARGS__ */ +#define _Log_CAR_ARG(N, ...) N +#define _Log_CDR_ARG(N, ...) __VA_ARGS__ + + +/* + * ======== Meta string tokenization macros ======== + */ +/* Helper macro to concatenate two symbols */ +#define _Log_CONCAT2_A(x,y) x ## _ ## y +#define _Log_CONCAT2(x,y) _Log_CONCAT2_A(x,y) +#define _Log_CONCAT3(x,y,z) _Log_CONCAT2(x,_Log_CONCAT2(y,z)) + +/* Helper macro to concatenate two symbols */ +#define _Log__TOKEN2STRING_A(x) #x +#define _Log_TOKEN2STRING(x) _Log__TOKEN2STRING_A(x) + +/* Macro to place meta string in a memory section separated by record separator */ +#define _Log_APPEND_META_TO_FORMAT(opcode, \ + file, \ + line, \ + level, \ + module, \ + format, \ + nargs) \ + _Log_TOKEN2STRING(opcode) "\x1e" \ + _Log_TOKEN2STRING(file) "\x1e" \ + _Log_TOKEN2STRING(line) "\x1e" \ + _Log_TOKEN2STRING(level) "\x1e" \ + _Log_TOKEN2STRING(module) "\x1e" \ + _Log_TOKEN2STRING(format) "\x1e" \ + _Log_TOKEN2STRING(nargs) + +/* Place a string in trace format section named ".log_data" locally + * This section must exist in the linker file + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define _Log_PLACE_FORMAT_IN_SECTOR(name, opcode, level, module, format, nargs)\ + __root static const char name[] @ ".log_data" = \ + _Log_APPEND_META_TO_FORMAT(opcode, \ + __FILE__, \ + __LINE__, \ + level, \ + module, \ + format, \ + nargs); \ + __root static const char * const _Log_CONCAT2(Ptr, name) @ _Log_TOKEN2STRING(_Log_CONCAT2(.log_ptr, module)) = name; +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define _Log_PLACE_FORMAT_IN_SECTOR(name, opcode, level, module, format, nargs)\ + static const char name[] \ + __attribute__((used,section(".log_data"))) = \ + _Log_APPEND_META_TO_FORMAT(opcode, \ + __FILE__, \ + __LINE__, \ + level, \ + module, \ + format, \ + nargs); \ + static const char * const _Log_CONCAT2(Ptr, name) \ + __attribute__((used,section(_Log_TOKEN2STRING(_Log_CONCAT3(.log_ptr, __LINE__, module))))) = name; +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +a supported compiler." +#endif + +/* + * ======== Variadic macro workaround ======== + */ +/* Helper macro to count the number of arguments in __VA_ARGS_ */ +#define _Log_NUMARGS(...) _Log_NUMARGS_A(__VA_ARGS__, 8, 7, 6, 5, 4, 3, 2, 1, 0) +#define _Log_NUMARGS_A(...) _Log_NUMARGS_B(__VA_ARGS__) +#define _Log_NUMARGS_B(_first, _8, _7, _6, _5, _4, _3, _2, _1, N, ...) N + +/* + * Helper to select arg/noarg variant macro since empty va_arg fails + * when arguments are expected. Eg + * Log_VARIANT(test, A, 7, "Hello") -> test__noarg(A, 7, "Hello") + * Log_VARIANT(test, A, 7, "Hello %d", 42) -> test__arg1(A, 7, "Hello %d", 42) + */ +#define _Log_VARIANT(x, module, level, ...) \ + _Log_CONCAT2(x, _Log_NUMARGS_B(__VA_ARGS__, _arg8, _arg7, _arg6, _arg5, _arg4, _arg3, _arg2, _arg1, _noarg)) ( module, level, __VA_ARGS__ ) + +/* + * ======== Module-level preprocessor include macros ======== + */ + +/* Helper macro to extract the second argument of a variable number of input + * args + */ +#define _Log_SECOND_ARG(x, y, ...) y + +/* Temporary token name. + * Name must end in "1" for preprocessor substitution below to work. + */ +#define _Log_TOKEN_1 0, + +/* Helper macro to check whether a symbol is defined with a non-zero value. + * If x is a preprocessor define, the conversion below shows the macro output: + * x = 0 -> 0 + * x = 1 -> 1 + * x (no value) -> 0 + * (undefined) -> 0 + */ +#define _Log_DEFINED(x) _Log_DEFINED_A(x) + +/* If x is 1, _Log_TOKEN_##y turns into _Log_TOKEN_1 and is replaced with "0," + * If x is anything else, _Log_TOKEN_##y turns into _Log_TOKEN_y. + */ +#define _Log_DEFINED_A(y) _Log_DEFINED_B(_Log_TOKEN_##y) + +/* If z is "0,", _Log_SECOND_ARG is called with the triplet "0, 1, 0" and + * selects the second item in it, 1. + * If z is anything else, _Log_SECOND_ARG is called with the tuple "z 1, 0" and + * selects the second item in it, 0. + */ +#define _Log_DEFINED_B(z) _Log_SECOND_ARG(z 1, 0) + +/* Empty Log buf macro to use when a log module is not enabled in the + * preprocessor during compilation + */ +#define _Log_buf_C_0(module, level, format, data, size) + +/* Log_buf macro to use when a log module is enabled in the preprocessor during + * compilation. + */ +#define _Log_buf_C_1(module, level, format, data, size) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if ((Log_ENABLED & LogMod_ ## module.levels) && ((level) & LogMod_ ## module.levels)) { \ + _Log_PLACE_FORMAT_IN_SECTOR(_Log_CONCAT2(LogSymbol, __LINE__), \ + LOG_OPCODE_BUFFER, \ + level, \ + LogMod_ ## module, \ + format, \ + 0); \ + LogMod_ ## module.buf(&LogMod_ ## module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + data, \ + size); \ + } \ + ) + +/* First level indirection macro for Log_buf that delegates between an empty + * implementation and the actual log emission based on whether a module is + * enabled in the preprocessor during compilation. + * + * The _Log_DEFINED() macro generates a token output of [0, 1] that is then + * concatenated with "_Log_buf_C" to form the correct delegate macro name. + * + * The expected module define name is ti_log_Log_ENABLE_ | and must be + * set to 1. E.g. "-Dti_log_Log_ENABLE_MyLogModule=1". Just defining the symbol in + * the preprocessor will not emit any logs. + */ +#define _Log_buf_B(module, level, format, data, size) \ + _Log_CONCAT2(_Log_buf_C, _Log_DEFINED(ti_log_Log_ENABLE_ ## module))(module, level, format, data, size) + +/* + * Redirects to cast all printf arguments to uintptr_t to avoid surprises if + * passing wider values and the compiler silently allows it. + */ +#define _Log_printf__arg1(module, level, fmt, a0) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0) +#define _Log_printf__arg2(module, level, fmt, a0, a1) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1) +#define _Log_printf__arg3(module, level, fmt, a0, a1, a2) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2) +#define _Log_printf__arg4(module, level, fmt, a0, a1, a2, a3) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3) +#define _Log_printf__arg5(module, level, fmt, a0, a1, a2, a3, a4) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4) +#define _Log_printf__arg6(module, level, fmt, a0, a1, a2, a3, a4, a5) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5) +#define _Log_printf__arg7(module, level, fmt, a0, a1, a2, a3, a4, a5, a6) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5, \ + (uintptr_t)a6) +#define _Log_printf__arg8(module, level, fmt, a0, a1, a2, a3, a4, a5, a6, a7) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5, \ + (uintptr_t)a6, \ + (uintptr_t)a7) + +#define _Log_printf__arg(module, level, ...) \ + module.printf(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + _Log_NUMARGS(__VA_ARGS__), \ + _Log_CDR_ARG(__VA_ARGS__)) + +#define _Log_printf__noarg(module, level, ...) \ + module.printf(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + _Log_NUMARGS(__VA_ARGS__)) + +/* Empty Log_printf macro to use when a log module is not enabled in the + * preprocessor during compilation + */ +#define _Log_printf_C_0(opcode, module, level, ...) + +/* Log_printf macro to use when a log module is enabled in the preprocessor during + * compilation. + */ +#define _Log_printf_C_1(opcode, module, level, ...) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if ((Log_ENABLED & LogMod_ ## module.levels) && \ + ((level) & LogMod_ ## module.levels)) { \ + _Log_PLACE_FORMAT_IN_SECTOR(_Log_CONCAT2(LogSymbol, __LINE__), \ + opcode, \ + level, \ + LogMod_ ## module, \ + _Log_CAR_ARG(__VA_ARGS__), \ + _Log_NUMARGS(__VA_ARGS__)) \ + _Log_VARIANT(_Log_printf, LogMod_ ## module, level, __VA_ARGS__); \ + } \ + ) + +/* First level indirection macro for Log_printf that delegates between an empty + * implementation and the actual log emission based on whether a module is + * enabled in the preprocessor during compilation. + * + * The _Log_DEFINED() macro generates a token output of [0, 1] that is then + * concatenated with "_Log_buf_C" to form the correct delegate macro name. + * + * The expected module define name is ti_log_Log_ENABLE_ | and must be + * set to 1. E.g. "-Dti_log_Log_ENABLE_MyLogModule=1". Just defining the symbol in + * the preprocessor will not emit any logs. + */ +#define _Log_printf_B(opcode, module, level, ...) \ + _Log_CONCAT2(_Log_printf_C, _Log_DEFINED(ti_log_Log_ENABLE_ ## module))(opcode, module, level, __VA_ARGS__) + +/** @endcond */ + +/** + * @brief Construct a log event object + * + * Use this marco to define a log event object. The object is global, and may + * be used in other files by invoking Log_EVENT_USE(name) there. + * + * @param[in] name Event variable name, to be passed to Log_event API + * @param[in] fmt Restricted format string. Note `%s` is not supported. + * Supported format specifiers include: `%c`, `%f`, + * `%d`, `%x` + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define Log_EVENT_DEFINE(name, fmt) \ + __root const char LogSymbol_ ## name[] @ ".log_data" = \ + _Log_APPEND_META_TO_FORMAT(LOG_EVENT_CONSTRUCT, \ + __FILE__, \ + __LINE__, \ + name, \ + global, \ + fmt, \ + 0) + +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define Log_EVENT_DEFINE(name, fmt) \ + const char LogSymbol_ ## name[] \ + __attribute__((used,section(".log_data"))) = \ + _Log_APPEND_META_TO_FORMAT(LOG_EVENT_CONSTRUCT, \ + __FILE__, \ + __LINE__, \ + name, \ + global, \ + fmt, \ + 0) +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +a supported compiler." +#endif + +/** + * @brief Declare usage of a log event symbol defined elsewhere + * + * Use this marco to declare a log event symbol for use. It's just a fancy + * `extern` macro. + * + * @param[in] name Event variable name, to be passed to Log_event API + */ +#define Log_EVENT_USE(name) extern const char[] LogSymbol_ ## name; + + +/** + * @brief Log a continuous block of memory + * + * Use this macro to send out runtime data from the device. This API should be + * used when the data is non constant and can only be derived at runtime. It + * is the most intrusive in terms of record overhead and instructions used. + * + * @param[in] module Log module that the buffer originated from + * @param[in] level log level of type @ref Log_Level + * @param[in] format Restricted format string. + * @param[in] data Pointer to array of bytes (uint8_t *) + * @param[in] size Size in bytes of array to send + * + */ +#define Log_buf(module, level, format, data, size) _Log_buf_B(module, level, format, data, size) + +/** + * @brief Emit a log event + * + * Use this marco to enable printf style logging. This API offers the most + * flexibility as the construction of the format string is embedded in the call + * site of the API. It also supports true variadic arguments. + * + * @param[in] module Log module that the buffer originated from + * @param[in] level Log level of type @ref Log_Level + * @param[in] event Event to be logged. Can be either a constructed + * Log_EVENT symbol, or a printf-like format-string + * @param[in] ... Variable amount of arguments. Must match your + * event or format-string. + * + * Examples: + * `Log_printf(MyTimingEvent, t.start)`, `Log_printf("Hello World")`, `Log_printf("Age: %d", 42)` + * + * @note All arguments are treated as 32-bit wide and are promoted or + * truncated accordingly. + */ +#define Log_printf(module, level, ...) _Log_printf_B(LOG_OPCODE_FORMATED_TEXT, module, level, __VA_ARGS__) + +#define Log_event(module, level, ...) _Log_printf_B(LOG_OPCODE_EVENT, module, level, __VA_ARGS__) + +/* Macro for defining the version of the Log API */ + + + +#if defined(__IAR_SYSTEMS_ICC__) +#define _Log_DEFINE_LOG_VERSION(module, version) \ + __root static const char _Log_CONCAT2(Log_ti_log_version, __COUNTER__)[] @ ".log_data" = \ + _Log_APPEND_META_TO_FORMAT(LOG_OPCODE_VERSION, \ + module, \ + version, \ + 0, \ + 0, \ + 0, \ + 0) +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define _Log_DEFINE_LOG_VERSION(module, version) \ + static const char _Log_CONCAT2(Log_ti_log_version, __COUNTER__)[] \ + __attribute__((used,section(".log_data"))) = \ + _Log_APPEND_META_TO_FORMAT(LOG_OPCODE_VERSION, \ + module, \ + version, \ + 0, \ + 0, \ + 0, \ + 0) +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +a supported compiler." +#endif + +/* Generate a symbol in the elf file that defines the version of the Log API */ +_Log_DEFINE_LOG_VERSION(Log, Log_TI_LOG_VERSION); + +#else /* ti_log_Log_ENABLE */ + +/* + * ================================================= + * ======== Log Disabled (default behavior) ======== + * ================================================= + */ + +#define Log_MODULE_DEFINE(...) +#define Log_MODULE_DEFINE_WEAK(name, init) +#define Log_MODULE_USE(...) +#define Log_EVENT_DEFINE(name, fmt) +#define Log_EVENT_USE(name, fmt) +#define Log_printf(module, level, ...) +#define Log_event(module, level, ...) +#define Log_buf(module, level, ...) +#define _Log_DEFINE_LOG_VERSION(module, version) + +#endif /* ti_log_Log_ENABLE */ + +/* + * ======== Log_Level ======== + */ +typedef enum Log_Level { + Log_DEBUG = 1, /*!< This should be the default level, reserved to be used by users to insert into applications for debugging. Exported libraries should avoid using this level. */ + Log_VERBOSE = 4, /*!< This level is recommended to be used in libraries to emit verbose information */ + Log_INFO = 16, /*!< This level is recommended to be used in libraries to emit simple information */ + Log_WARNING = 64, /*!< This level is recommended to be used in libraries to emit warnings. It is up to the library developer to decide what constitutes a warning, but it should typically indicate something unexpected, but not something that leads to system failure */ + Log_ERROR = 256, /*!< This level is recommended to be used in libraries to emit errors. Typically, this should be used when something has failed and the system is unable to continue correct operation */ + Log_ALL = 1 + 4 + 16 + 64 + 256, /*!< This enables all levels */ + Log_ENABLED = 512 /*!< This is used to enable or disable the log module, independently of the log levels */ +} Log_Level; + +typedef const struct Log_Module Log_Module; + +typedef void (*Log_printf_fxn)(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...); + +typedef void (*Log_buf_fxn)(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint8_t *data, + size_t size); + +struct Log_Module { + void *sinkConfig; + const Log_printf_fxn printf; + const Log_buf_fxn buf; + uint32_t levels; +}; + +/*! @} */ +#if defined (__cplusplus) +} +#endif + +#endif // ti_log_Log__include From 3d4fea9e0899be73eb98c254550e157f82c630d8 Mon Sep 17 00:00:00 2001 From: Min Xu Date: Wed, 5 Jun 2024 12:47:11 +0200 Subject: [PATCH 5/7] hal: drivers: radio: Port radio driver for F3 devices to Zephyr Port RCL (radio control layer), the radio driver for TI F3 devices to Zephyr. This commit includes the source files of RCL, binary images of modem firmwares, and pre-generated radio settings for adc noise and BLE5. NOTE: currently, the radio settings for BLE5 are compiled as part of the driver library by default, which is a workaround for now. TI's BLE Stack controller requires the radio configuration C structs without the PHY abbreviation appended as a suffix. This commit removes the PHY abbreviation by disabling the "use_phy_abbreviation" when generating the radio settings in SmartRF Studio 8. Signed-off-by: Min Xu --- simplelink_lpf3/CMakeLists.txt | 53 + .../source/ti/boards/CMakeLists.txt | 31 + .../source/ti/boards/cc23x0r5/CMakeLists.txt | 47 + .../boards/cc23x0r5/rcl_settings_adc_noise.c | 110 + .../boards/cc23x0r5/rcl_settings_adc_noise.h | 191 + .../ti/boards/cc23x0r5/rcl_settings_ble.c | 312 + .../ti/boards/cc23x0r5/rcl_settings_ble.h | 324 + .../source/ti/boards/cc23x0r5/ti_log_config.c | 23 + .../ti/boards/cc23x0r5/tracer_control.c | 106 + .../source/ti/devices/cc23x0r5/CMakeLists.txt | 28 + .../ti/devices/cc23x0r5/inc/hw_lrfddbell.h | 13636 ++++++++-------- .../ti/devices/cc23x0r5/inc/hw_lrfdmdm.h | 7158 ++++++++ .../ti/devices/cc23x0r5/inc/hw_lrfdmdm32.h | 6027 +++++++ .../ti/devices/cc23x0r5/inc/hw_lrfdpbe.h | 4495 +++++ .../ti/devices/cc23x0r5/inc/hw_lrfdpbe32.h | 3599 ++++ .../ti/devices/cc23x0r5/inc/hw_lrfdrfe.h | 8223 ++++++++++ .../ti/devices/cc23x0r5/inc/hw_lrfdrfe32.h | 6236 +++++++ .../ti/devices/cc23x0r5/inc/hw_lrfdrxf.h | 124 +- .../ti/devices/cc23x0r5/inc/hw_lrfds2r.h | 231 + .../ti/devices/cc23x0r5/inc/hw_lrfdtrc.h | 429 + .../ti/devices/cc23x0r5/inc/hw_lrfdtxf.h | 124 +- .../devices/cc23x0r5/inc/pbe_ble5_ram_regs.h | 4504 +++++ .../cc23x0r5/inc/pbe_ble5_regdef_regs.h | 204 + .../cc23x0r5/inc/pbe_ble_cs_ram_regs.h | 696 + .../cc23x0r5/inc/pbe_ble_cs_regdef_regs.h | 48 + .../cc23x0r5/inc/pbe_common_ram_regs.h | 111 + .../cc23x0r5/inc/pbe_generic_ram_regs.h | 1550 ++ .../cc23x0r5/inc/pbe_generic_regdef_regs.h | 201 + .../devices/cc23x0r5/inc/pbe_ieee_ram_regs.h | 1404 ++ .../cc23x0r5/inc/pbe_ieee_regdef_regs.h | 199 + .../inc/rfe_coherent_pll_regdef_regs.h | 31 + .../cc23x0r5/inc/rfe_common_ram_regs.h | 766 + .../devices/cc23x0r5/inc/rfe_cpll_ram_regs.h | 1084 ++ .../cc23x0r5/rf_patches/lrf_mce_binary_ble5.h | 21 + .../rf_patches/lrf_mce_binary_ble5_cc23x0r5.c | 78 + .../rf_patches/lrf_mce_binary_ble_cs.h | 21 + .../lrf_mce_binary_ble_cs_cc23x0r5.c | 88 + .../rf_patches/lrf_mce_binary_common.h | 21 + .../lrf_mce_binary_common_cc23x0r5.c | 15 + .../rf_patches/lrf_mce_binary_genfsk.h | 21 + .../lrf_mce_binary_genfsk_cc23x0r5.c | 76 + .../cc23x0r5/rf_patches/lrf_mce_binary_ieee.h | 21 + .../rf_patches/lrf_mce_binary_ieee_cc23x0r5.c | 42 + .../cc23x0r5/rf_patches/lrf_pbe_binary_ble5.h | 21 + .../rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c | 131 + .../rf_patches/lrf_pbe_binary_ble_cs.h | 21 + .../lrf_pbe_binary_ble_cs_cc23x0r5.c | 62 + .../rf_patches/lrf_pbe_binary_common.h | 21 + .../lrf_pbe_binary_common_cc23x0r5.c | 15 + .../rf_patches/lrf_pbe_binary_generic.h | 21 + .../lrf_pbe_binary_generic_cc23x0r5.c | 107 + .../cc23x0r5/rf_patches/lrf_pbe_binary_ieee.h | 21 + .../rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c | 129 + .../cc23x0r5/rf_patches/lrf_rfe_binary_ble5.h | 21 + .../rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c | 122 + .../rf_patches/lrf_rfe_binary_ble5_nopll.h | 21 + .../lrf_rfe_binary_ble5_nopll_cc23x0r5.c | 122 + .../rf_patches/lrf_rfe_binary_ble_cs.h | 21 + .../lrf_rfe_binary_ble_cs_cc23x0r5.c | 123 + .../rf_patches/lrf_rfe_binary_ble_cs_nopll.h | 21 + .../lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c | 123 + .../rf_patches/lrf_rfe_binary_coherent_pll.h | 21 + .../lrf_rfe_binary_coherent_pll_cc23x0r5.c | 122 + .../lrf_rfe_binary_coherent_pll_nopll.h | 21 + ...f_rfe_binary_coherent_pll_nopll_cc23x0r5.c | 122 + .../rf_patches/lrf_rfe_binary_common.h | 21 + .../lrf_rfe_binary_common_cc23x0r5.c | 15 + .../rf_patches/lrf_rfe_binary_common_nopll.h | 21 + .../lrf_rfe_binary_common_nopll_cc23x0r5.c | 15 + .../rf_patches/lrf_rfe_binary_genfsk.h | 21 + .../lrf_rfe_binary_genfsk_cc23x0r5.c | 122 + .../rf_patches/lrf_rfe_binary_genfsk_nopll.h | 21 + .../lrf_rfe_binary_genfsk_nopll_cc23x0r5.c | 122 + .../cc23x0r5/rf_patches/lrf_rfe_binary_ieee.h | 21 + .../rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c | 122 + .../rf_patches/lrf_rfe_binary_ieee_nopll.h | 21 + .../lrf_rfe_binary_ieee_nopll_cc23x0r5.c | 122 + simplelink_lpf3/source/ti/drivers/rcl/LRF.c | 784 + simplelink_lpf3/source/ti/drivers/rcl/LRF.h | 314 + .../source/ti/drivers/rcl/LRFCC23X0.c | 1538 ++ .../source/ti/drivers/rcl/LRFCC23X0.h | 637 + simplelink_lpf3/source/ti/drivers/rcl/RCL.c | 912 ++ simplelink_lpf3/source/ti/drivers/rcl/RCL.h | 159 + .../source/ti/drivers/rcl/RCL_Buffer.c | 439 + .../source/ti/drivers/rcl/RCL_Buffer.h | 491 + .../source/ti/drivers/rcl/RCL_Client.h | 54 + .../source/ti/drivers/rcl/RCL_Command.h | 228 + .../source/ti/drivers/rcl/RCL_Debug.c | 50 + .../source/ti/drivers/rcl/RCL_Debug.h | 45 + .../source/ti/drivers/rcl/RCL_Event.h | 90 + .../source/ti/drivers/rcl/RCL_Profiling.c | 45 + .../source/ti/drivers/rcl/RCL_Profiling.h | 46 + .../source/ti/drivers/rcl/RCL_Scheduler.c | 757 + .../source/ti/drivers/rcl/RCL_Scheduler.h | 362 + .../source/ti/drivers/rcl/RCL_Tracer.c | 83 + .../source/ti/drivers/rcl/RCL_Tracer.h | 45 + .../source/ti/drivers/rcl/RCL_Types.h | 50 + .../source/ti/drivers/rcl/RCL_Version.h | 15 + .../ti/drivers/rcl/commands/adc_noise.h | 91 + .../source/ti/drivers/rcl/commands/ble5.h | 808 + .../source/ti/drivers/rcl/commands/ble_cs.h | 687 + .../source/ti/drivers/rcl/commands/generic.h | 476 + .../source/ti/drivers/rcl/commands/ieee.h | 313 + .../ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c | 475 + .../source/ti/drivers/rcl/hal/hal.h | 103 + .../ti/drivers/rcl/handlers/adc_noise.c | 316 + .../ti/drivers/rcl/handlers/adc_noise.h | 42 + .../source/ti/drivers/rcl/handlers/ble5.c | 6341 +++++++ .../source/ti/drivers/rcl/handlers/ble5.h | 164 + .../source/ti/drivers/rcl/handlers/ble_cs.c | 2049 +++ .../source/ti/drivers/rcl/handlers/ble_cs.h | 44 + .../source/ti/drivers/rcl/handlers/generic.c | 2219 +++ .../source/ti/drivers/rcl/handlers/generic.h | 50 + .../source/ti/drivers/rcl/handlers/ieee.c | 1768 ++ .../source/ti/drivers/rcl/handlers/ieee.h | 186 + .../ti/drivers/rcl/wrappers/RCL_AdcNoise.c | 183 + 116 files changed, 81279 insertions(+), 6942 deletions(-) create mode 100644 simplelink_lpf3/source/ti/boards/CMakeLists.txt create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/CMakeLists.txt create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.c create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.h create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.c create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.h create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/ti_log_config.c create mode 100644 simplelink_lpf3/source/ti/boards/cc23x0r5/tracer_control.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm32.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe32.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe32.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfds2r.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtrc.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_regdef_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_regdef_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_common_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_regdef_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_regdef_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_coherent_pll_regdef_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_common_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_cpll_ram_regs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll_cc23x0r5.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/LRF.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/LRF.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Client.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Command.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Event.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Types.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/RCL_Version.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/commands/adc_noise.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/commands/ble5.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/commands/ble_cs.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/commands/generic.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/commands/ieee.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/hal/hal.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.c create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.h create mode 100644 simplelink_lpf3/source/ti/drivers/rcl/wrappers/RCL_AdcNoise.c diff --git a/simplelink_lpf3/CMakeLists.txt b/simplelink_lpf3/CMakeLists.txt index 969bc57a..893240f2 100644 --- a/simplelink_lpf3/CMakeLists.txt +++ b/simplelink_lpf3/CMakeLists.txt @@ -1,4 +1,37 @@ +# Copyright (c) 2024, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# All targets in this file are for Cortex-M0P + add_subdirectory(source/ti/devices) +add_subdirectory(source/ti/boards) if(CONFIG_HAS_CC23X0_SDK) @@ -62,4 +95,24 @@ if(CONFIG_HAS_CC23X0_SDK) zephyr_linker_sources(RAM_SECTIONS ${CMAKE_CURRENT_SOURCE_DIR}/source/ti/drivers/dma/dma.ld ) + + # Radio Control Layer (RCL) driver + if(CONFIG_SIMPLELINK_F3_RADIO_DRIVER) + zephyr_library_sources( + source/ti/drivers/rcl/LRF.c + source/ti/drivers/rcl/LRFCC23X0.c + source/ti/drivers/rcl/RCL_Buffer.c + source/ti/drivers/rcl/RCL_Debug.c + source/ti/drivers/rcl/RCL_Profiling.c + source/ti/drivers/rcl/RCL_Scheduler.c + source/ti/drivers/rcl/RCL_Tracer.c + source/ti/drivers/rcl/RCL.c + source/ti/drivers/rcl/handlers/adc_noise.c + source/ti/drivers/rcl/handlers/ble_cs.c + source/ti/drivers/rcl/handlers/ble5.c + source/ti/drivers/rcl/handlers/generic.c + source/ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c + source/ti/drivers/rcl/wrappers/RCL_AdcNoise.c + ) + endif() endif() diff --git a/simplelink_lpf3/source/ti/boards/CMakeLists.txt b/simplelink_lpf3/source/ti/boards/CMakeLists.txt new file mode 100644 index 00000000..b5f41e9c --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2024, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +add_subdirectory_ifdef(CONFIG_HAS_CC23X0_SDK cc23x0r5) \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/CMakeLists.txt b/simplelink_lpf3/source/ti/boards/cc23x0r5/CMakeLists.txt new file mode 100644 index 00000000..7516b453 --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/CMakeLists.txt @@ -0,0 +1,47 @@ +# Copyright (c) 2022-2024, Texas Instruments Incorporated +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Texas Instruments Incorporated nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# All targets in this file are for Cortex-M0P + +if(CONFIG_SIMPLELINK_F3_RADIO_DRIVER) + zephyr_include_directories( + . + ) + + zephyr_library() + + zephyr_library_sources( + rcl_settings_adc_noise.c + ) + + # [Workaround]: Include the radio settings for ble by defualt + # TODO: radio settings should be selectable, see ZEPHYR-24 + zephyr_library_sources_ifdef(CONFIG_SIMPLELINK_F3_RF_SETTING_PREGEN rcl_settings_ble.c) +endif() \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.c b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.c new file mode 100644 index 00000000..ae43e718 --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.c @@ -0,0 +1,110 @@ +// SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (SOURCE FILE) +// +// +// CODE EXPORT INFORMATION +// This file is generated +// +// Tool name SmartRF Studio 8 +// Tool version 0.6.0.327 INTERNAL +// Created 2024-05-28 13:53:16.066 +// Computer swtools +// User - +// +// +// WORKSPACE INFORMATION +// +// Workspace file srf_cli.workspace +// Device CC2340R5 +// Package QFN40 5x5 RKP +// Revision(s) B (2.0) +// SDK SimpleLink LPF3 SDK 8.11.00.09 +// Board LP-EM-CC2340R5 +// PHY ADC Noise +// PHY abbreviation adc_noise +// +// +// VALIDATION WARNINGS +// +// No warnings + +#include "rcl_settings_adc_noise.h" +#include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_ble5.h) + + +// Configuration: Common +static const uint32_t LRF_commonRegConfig[] = +{ + 0x0000002C, // Segment length = 44 + 0x0000A002, // Data structure 32-bit region (start byte position = 0, count = 3) + (uint32_t) &LRF_swConfigAdcNoise, // LRF_swParam : swConfig + 0x00000000, // LRF_swParam : txPowerTable + (uint32_t) &(fcfg->appTrims), // LRF_swParam : trimDef + 0x00003003, // HW sparse region (address/value pairs, count = 4) + 0x30800000, // LRFDRFE.MAGNTHRCFG + 0x30880000, // LRFDRFE.RSSIOFFSET + 0x31201820, // LRFDRFE.MISC0 + 0x31300C07, // LRFDRFE.PHEDISC + 0x30A01002, // HW 16-bit region (start address = 0x30A0, count = 3) + 0x1F40A246, // LRFDRFE.SPARE3 LRFDRFE.SPARE2 + 0x00000000, // - LRFDRFE.SPARE4 + 0x30B01002, // HW 16-bit region (start address = 0x30B0, count = 3) + 0x0006000A, // LRFDRFE.IFAMPRFLDO LRFDRFE.LNA + 0x00000000, // - LRFDRFE.PA0 + 0x30C40005, // HW zero region (start address = 0x30C4, count = 6) + 0x30E4100C, // HW 16-bit region (start address = 0x30E4, count = 13) + 0x00000200, // LRFDRFE.DCO LRFDRFE.ATSTREFH + 0x00000008, // LRFDRFE.DIVLDO LRFDRFE.DIV + 0x00000000, // LRFDRFE.DCOLDO0 LRFDRFE.TDCLDO + 0x07060000, // LRFDRFE.PRE0 LRFDRFE.DCOLDO1 + 0x06050000, // LRFDRFE.PRE2 LRFDRFE.PRE1 + 0x40080603, // LRFDRFE.CAL0 LRFDRFE.PRE3 + 0x00007F00, // - LRFDRFE.CAL1 + 0x31381002, // HW 16-bit region (start address = 0x3138, count = 3) + 0x047FDF7F, // LRFDRFE.PLLMON1 LRFDRFE.PLLMON0 + 0x00001804, // - LRFDRFE.MOD0 + 0x68046005, // RAM 32-bit region (start address = 0x6804, count = 6) + 0x03000012, // RFE_COMMON_RAM.TDCCAL0 RFE_COMMON_RAM.SYNTHCTL + 0x00100000, // RFE_COMMON_RAM.TDCCAL2 RFE_COMMON_RAM.TDCCAL1 + 0x569B0400, // RFE_COMMON_RAM.K1LSB RFE_COMMON_RAM.TDCPLL + 0x012D010A, // RFE_COMMON_RAM.K2BL RFE_COMMON_RAM.K1MSB + 0x132C0034, // RFE_COMMON_RAM.K3BL RFE_COMMON_RAM.K2AL + 0x916F07AB, // RFE_COMMON_RAM.K5 RFE_COMMON_RAM.K3AL + 0x68206005, // RAM 32-bit region (start address = 0x6820, count = 6) + 0x00000000, // RFE_COMMON_RAM.RTRIMMIN RFE_COMMON_RAM.RTRIMOFF + 0x48080008, // RFE_COMMON_RAM.DIVF RFE_COMMON_RAM.DIVI + 0x00000000, // RFE_COMMON_RAM.DIVLDOF RFE_COMMON_RAM.DIVLDOI + 0x00470014, // RFE_COMMON_RAM.LDOSETTLE RFE_COMMON_RAM.DIVLDOIOFF + 0x0005002E, // RFE_COMMON_RAM.DCOSETTLE RFE_COMMON_RAM.CHRGSETTLE + 0x0000FE00, // RFE_COMMON_RAM.IFAMPRFLDODEFAULT RFE_COMMON_RAM.IFAMPRFLDOTX + 0x683E5003, // RAM 16-bit region (start address = 0x683E, count = 4) + 0x00220050, // RFE_COMMON_RAM.SPARE0SHADOW RFE_COMMON_RAM.PHYRSSIOFFSET + 0x00000045 // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW +}; + + +// LRF register configuration list +static const LRF_RegConfigList LRF_regConfigList = { + .numEntries = 1, + .entries = { + (LRF_ConfigWord*) LRF_commonRegConfig + } +}; + +// LRF_SwConfig data structure +const LRF_SwConfig LRF_swConfigAdcNoise = { + .rxIntFrequency = 0, + .rxFrequencyOffset = 0, + .txFrequencyOffset = 0, + .modFrequencyDeviation = 0x00000000, + .txShape = (LRF_TxShape*) 0, + .bwIndex = 0x01, + .bwIndexDither = 0x01 +}; + +// LRF_Config data structure +const LRF_Config LRF_configAdcNoise = { + .pbeImage = (LRF_TOPsmImage*) 0, + .mceImage = (LRF_TOPsmImage*) 0, + .rfeImage = (const LRF_TOPsmImage*) LRF_RFE_binary_ble5, + .regConfigList = &LRF_regConfigList +}; diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.h b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.h new file mode 100644 index 00000000..b85e8b4e --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_adc_noise.h @@ -0,0 +1,191 @@ +// SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (HEADER FILE) +// +// +// CODE EXPORT INFORMATION +// This file is generated +// +// Tool name SmartRF Studio 8 +// Tool version 0.6.0.327 INTERNAL +// Created 2024-05-28 13:53:16.066 +// Computer swtools +// User - +// +// +// WORKSPACE INFORMATION +// +// Workspace file srf_cli.workspace +// Device CC2340R5 +// Package QFN40 5x5 RKP +// Revision(s) B (2.0) +// SDK SimpleLink LPF3 SDK 8.11.00.09 +// Board LP-EM-CC2340R5 +// PHY ADC Noise +// PHY abbreviation adc_noise +// +// +// VALIDATION WARNINGS +// +// No warnings + +#ifndef RCLSETTINGSADCNOISE_H +#define RCLSETTINGSADCNOISE_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_fcfg.h) + + +// LRF data structures +extern const LRF_SwConfig LRF_swConfigAdcNoise; +extern const LRF_Config LRF_configAdcNoise; + + +// COMMON register field values + +// Address Module Register Bit(s) Field Value +// ----------------------------------------------------------------------------------- +// 0x3080 LRFDRFE MAGNTHRCFG [1] SEL 0x0 +// 0x3088 LRFDRFE RSSIOFFSET [7:0] VAL +// 0x30A0 LRFDRFE SPARE2 [15:0] VAL 0xA246 +// 0x30A4 LRFDRFE SPARE3 [15:0] VAL 0x1F40 +// 0x30A8 LRFDRFE SPARE4 [15:0] VAL 0x0000 +// 0x30B0 LRFDRFE LNA [7:4] TRIM +// 0x30B0 LRFDRFE LNA [3] BIAS 0x1 +// 0x30B0 LRFDRFE LNA [2:1] IB 0x1 +// 0x30B4 LRFDRFE IFAMPRFLDO [15:9] TRIM +// 0x30B4 LRFDRFE IFAMPRFLDO [7:4] AAFCAP +// 0x30B4 LRFDRFE IFAMPRFLDO [3:1] IFAMPIB 0x3 +// 0x30B8 LRFDRFE PA0 [4:0] TRIM +// 0x30C4 LRFDRFE IFADC0 [14:12] DITHERTRIM +// 0x30C4 LRFDRFE IFADC0 [11:10] DITHEREN +// 0x30C4 LRFDRFE IFADC0 [7:4] INT2ADJ +// 0x30C4 LRFDRFE IFADC0 [3:2] AAFCAP +// 0x30C8 LRFDRFE IFADC1 [15] NRZ +// 0x30C8 LRFDRFE IFADC1 [14:9] TRIM +// 0x30CC LRFDRFE IFADCLF [15:12] FF3 +// 0x30CC LRFDRFE IFADCLF [11:8] FF2 +// 0x30CC LRFDRFE IFADCLF [7:4] FF1 +// 0x30CC LRFDRFE IFADCLF [3:0] INT3 +// 0x30D0 LRFDRFE IFADCQUANT [2:0] QUANTTHR +// 0x30D4 LRFDRFE IFADCALDO [13:8] TRIMOUT +// 0x30D8 LRFDRFE IFADCDLDO [13:8] TRIMOUT +// 0x30E4 LRFDRFE ATSTREFH [14:10] IREFTRIM +// 0x30E4 LRFDRFE ATSTREFH [9] BIAS 0x1 +// 0x30E8 LRFDRFE DCO [6:3] TAILRESTRIM +// 0x30E8 LRFDRFE DCO [0] CRSCAPCM 0x0 +// 0x30EC LRFDRFE DIV [15] PDET 0x0 +// 0x30EC LRFDRFE DIV [14:12] NMIREFTRIM 0x0 +// 0x30EC LRFDRFE DIV [11:9] PMIREFTRIM 0x0 +// 0x30EC LRFDRFE DIV [8] TXBBOOST 0x0 +// 0x30EC LRFDRFE DIV [7] S1GFRC 0x0 +// 0x30EC LRFDRFE DIV [6:5] BUFGAIN 0x0 +// 0x30EC LRFDRFE DIV [4] BIAS 0x0 +// 0x30EC LRFDRFE DIV [3] OUT 0x1 +// 0x30EC LRFDRFE DIV [2:0] RATIO 0x0 +// 0x30F0 LRFDRFE DIVLDO [15] SPARE15 0x0 +// 0x30F0 LRFDRFE DIVLDO [14:8] VOUTTRIM +// 0x30F0 LRFDRFE DIVLDO [7] ITST 0x0 +// 0x30F0 LRFDRFE DIVLDO [6:4] TMUX 0x0 +// 0x30F0 LRFDRFE DIVLDO [3] SPARE3 0x0 +// 0x30F0 LRFDRFE DIVLDO [2] MODE 0x0 +// 0x30F0 LRFDRFE DIVLDO [1] BYPASS 0x0 +// 0x30F0 LRFDRFE DIVLDO [0] CTL 0x0 +// 0x30F4 LRFDRFE TDCLDO [14:8] VOUTTRIM +// 0x30F8 LRFDRFE DCOLDO0 [13:8] SECONDTRIM +// 0x30F8 LRFDRFE DCOLDO0 [7:4] FIRSTTRIM +// 0x30FC LRFDRFE DCOLDO1 [10] REFSRC 0x0 +// 0x30FC LRFDRFE DCOLDO1 [9:8] DIVATST 0x0 +// 0x3100 LRFDRFE PRE0 [13:8] PLLDIV1 0x07 +// 0x3100 LRFDRFE PRE0 [5:0] PLLDIV0 0x06 +// 0x3104 LRFDRFE PRE1 [5:0] HSDDC 0x00 +// 0x3108 LRFDRFE PRE2 [15:12] MIDCALDIVLSB 0x0 +// 0x3108 LRFDRFE PRE2 [11:6] CRSCALDIV 0x18 +// 0x3108 LRFDRFE PRE2 [5:0] FSMDIV 0x05 +// 0x310C LRFDRFE PRE3 [15:5] FINECALDIV 0x030 +// 0x310C LRFDRFE PRE3 [4:0] MIDCALDIVMSB 0x03 +// 0x3110 LRFDRFE CAL0 [14:8] FCSTART 0x40 +// 0x3110 LRFDRFE CAL0 [3:2] TDCAVG 0x2 +// 0x3114 LRFDRFE CAL1 [14:8] FCTOP 0x7F +// 0x3114 LRFDRFE CAL1 [6:0] FCBOT 0x00 +// 0x3120 LRFDRFE MISC0 [13] PHCPT 0x0 +// 0x3120 LRFDRFE MISC0 [12] TDCCALCORR 0x1 +// 0x3120 LRFDRFE MISC0 [11] TDCMSBCORR 0x1 +// 0x3120 LRFDRFE MISC0 [5:4] DLYCANCRS 0x2 +// 0x3130 LRFDRFE PHEDISC [13:10] CNT 0x3 +// 0x3130 LRFDRFE PHEDISC [9:0] THR 0x007 +// 0x3138 LRFDRFE PLLMON0 [15:14] PHELOLCNT 0x3 +// 0x3138 LRFDRFE PLLMON0 [13:8] PHELOLTHR 0x1F +// 0x3138 LRFDRFE PLLMON0 [6:0] FCTHR 0x7F +// 0x313C LRFDRFE PLLMON1 [12:8] PHELOCKCNT 0x04 +// 0x313C LRFDRFE PLLMON1 [7:0] PHELOCKTHR 0x7F +// 0x3140 LRFDRFE MOD0 [12:11] SCHEME 0x3 +// 0x3140 LRFDRFE MOD0 [10:8] SYMSHP 0x0 +// 0x3140 LRFDRFE MOD0 [3:2] INTPFACT 0x1 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [7] CHRGFILT 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [6] VREFBP 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [5] TXWAITMOD 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [4] PHEDISC 0x1 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [3] RTRIMTST 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [2] IIR 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [1] REFDTHR 0x1 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [0] FCDEM 0x0 +// 0x6806 RFE_COMMON_RAM TDCCAL0 [10:8] STOP 0x3 +// 0x6808 RFE_COMMON_RAM TDCCAL1 [7:0] SUB 0x00 +// 0x680A RFE_COMMON_RAM TDCCAL2 [5:0] AVG 0x10 +// 0x680C RFE_COMMON_RAM TDCPLL [10:8] STOP 0x4 +// 0x680E RFE_COMMON_RAM K1LSB [15:0] VAL 0x569B +// 0x6810 RFE_COMMON_RAM K1MSB [15:0] VAL 0x010A +// 0x6812 RFE_COMMON_RAM K2BL [15] HPM 0x0 +// 0x6812 RFE_COMMON_RAM K2BL [14:0] VAL 0x012D +// 0x6814 RFE_COMMON_RAM K2AL [15] HPM 0x0 +// 0x6814 RFE_COMMON_RAM K2AL [14:0] VAL 0x0034 +// 0x6816 RFE_COMMON_RAM K3BL [15:0] VAL 0x132C +// 0x6818 RFE_COMMON_RAM K3AL [15:0] VAL 0x07AB +// 0x681A RFE_COMMON_RAM K5 [15:0] VAL 0x916F +// 0x6820 RFE_COMMON_RAM RTRIMOFF [3:0] VAL 0x0 +// 0x6822 RFE_COMMON_RAM RTRIMMIN [3:0] VAL 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [15] PDET 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [14:12] NMIREFTRIM 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [11:9] PMIREFTRIM 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [8] TXBOOST 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [7] S1GFRC 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [6:5] BUFGAIN 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [4] BIAS 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [3] OUT 0x1 +// 0x6824 RFE_COMMON_RAM DIVI [2:0] RATIO 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [15] PDET 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [14:12] NMIREFTRIM 0x4 +// 0x6826 RFE_COMMON_RAM DIVF [11:9] PMIREFTRIM 0x4 +// 0x6826 RFE_COMMON_RAM DIVF [8] TXBOOST 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [7] S1GFRC 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [6:5] BUFGAIN 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [4] BIAS 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [3] OUT 0x1 +// 0x6826 RFE_COMMON_RAM DIVF [2:0] RATIO 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [15] ITEST 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [14:8] VOUTTRIM 0x00 +// 0x6828 RFE_COMMON_RAM DIVLDOI [7] ITST 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [6:4] TMUX 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [2] MODE 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [1] BYPASS 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [0] CTL 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [15] ITEST 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [14:8] VOUTTRIM 0x00 +// 0x682A RFE_COMMON_RAM DIVLDOF [7] ITST 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [6:4] TMUX 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [2] MODE 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [1] BYPASS 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [0] CTL 0x0 +// 0x682C RFE_COMMON_RAM DIVLDOIOFF [6:0] VAL 0x14 +// 0x682E RFE_COMMON_RAM LDOSETTLE [9:0] VAL 0x047 +// 0x6830 RFE_COMMON_RAM CHRGSETTLE [9:0] VAL 0x02E +// 0x6832 RFE_COMMON_RAM DCOSETTLE [9:0] VAL 0x005 +// 0x6834 RFE_COMMON_RAM IFAMPRFLDOTX [15:9] TRIM 0x7F +// 0x6836 RFE_COMMON_RAM IFAMPRFLDODEFAULT [15:9] TRIM 0x00 +// 0x683E RFE_COMMON_RAM PHYRSSIOFFSET [7:0] VAL 0x50 +// 0x6840 RFE_COMMON_RAM SPARE0SHADOW [15:0] VAL 0x0022 +// 0x6842 RFE_COMMON_RAM SPARE1SHADOW [15:0] VAL 0x0045 +// 0x6844 RFE_COMMON_RAM AGCINFO [0] MODE 0x0 + + +#endif diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.c b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.c new file mode 100644 index 00000000..f71be1ed --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.c @@ -0,0 +1,312 @@ +// SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (SOURCE FILE) +// +// Usage Protocol stack +// +// +// CODE EXPORT INFORMATION +// This file is generated +// +// Tool name SmartRF Studio 8 +// Tool version 0.6.0.327 INTERNAL +// +// +// WORKSPACE INFORMATION +// +// Workspace file srf_cli.workspace +// Device CC2340R5 +// Package QFN40 5x5 RKP +// Revision(s) B (2.0) +// SDK SimpleLink LPF3 SDK 8.11.00.09 +// Board LP-EM-CC2340R5 +// PHY 2.4 GHz - Bluetooth 5, LE - 1 Mbps / 2 Mbps / Coded +// +// +// PHY PROPERTIES +// +// Run-time properties: +// Sub-PHY 1 Mbps +// Channel 17 (2440 MHz) +// TX output power 5.0 dBm + +#include "rcl_settings_ble.h" +#include DeviceFamily_constructPath(rf_patches/lrf_pbe_binary_ble5.h) +#include DeviceFamily_constructPath(rf_patches/lrf_mce_binary_ble5.h) +#include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_ble5.h) + + +// Configuration: Common +static const uint32_t LRF_commonRegConfig[] = +{ + 0x0000003C, // Segment length = 60 + 0x0004A001, // Data structure 32-bit region (start byte position = 4, count = 2) + (uint32_t) &LRF_txPowerTable, // LRF_swParam : txPowerTable + (uint32_t) &(fcfg->appTrims), // LRF_swParam : trimDef + 0x14502001, // HW 32-bit region (start address = 0x1450, count = 2) + 0x22000000, // LRFDPBE.POLY0H LRFDPBE.POLY0L + 0x00065B00, // LRFDPBE.POLY1H LRFDPBE.POLY1L + 0x10B41004, // HW 16-bit region (start address = 0x10B4, count = 5) + 0x00C40021, // LRFDPBE.FCFG1 LRFDPBE.FCFG0 + 0x00800086, // LRFDPBE.FCFG3 LRFDPBE.FCFG2 + 0x00000044, // - LRFDPBE.FCFG4 + 0x14682000, // HW 32-bit region (start address = 0x1468, count = 1) + 0x00020004, // LRFDPBE.TXFWBTHRS LRFDPBE.RXFRBTHRS + 0x10DC1001, // HW 16-bit region (start address = 0x10DC, count = 2) + 0x0B0B0202, // LRFDPBE.TIMPRE LRFDPBE.TIMCTL + 0x00003009, // HW sparse region (address/value pairs, count = 10) + 0x20C00003, // LRFDMDM.ADCDIGCONF + 0x20C8001F, // LRFDMDM.MODSYMMAP0 + 0x20E40001, // LRFDMDM.DEMMISC1 + 0x20F00000, // LRFDMDM.DEMIQMC0 + 0x20FC0000, // LRFDMDM.DEMFIDC0 + 0x30800000, // LRFDRFE.MAGNTHRCFG + 0x30880000, // LRFDRFE.RSSIOFFSET + 0x30A80000, // LRFDRFE.SPARE4 + 0x31201820, // LRFDRFE.MISC0 + 0x31300C07, // LRFDRFE.PHEDISC + 0x246C2000, // HW 32-bit region (start address = 0x246C, count = 1) + 0x0000000C, // LRFDMDM.MODMAIN LRFDMDM.BAUDPRE + 0x30B41001, // HW 16-bit region (start address = 0x30B4, count = 2) + 0x00000006, // LRFDRFE.PA0 LRFDRFE.IFAMPRFLDO + 0x30C40005, // HW zero region (start address = 0x30C4, count = 6) + 0x30E4100C, // HW 16-bit region (start address = 0x30E4, count = 13) + 0x00000200, // LRFDRFE.DCO LRFDRFE.ATSTREFH + 0x00000008, // LRFDRFE.DIVLDO LRFDRFE.DIV + 0x00000000, // LRFDRFE.DCOLDO0 LRFDRFE.TDCLDO + 0x07060000, // LRFDRFE.PRE0 LRFDRFE.DCOLDO1 + 0x06050000, // LRFDRFE.PRE2 LRFDRFE.PRE1 + 0x40080603, // LRFDRFE.CAL0 LRFDRFE.PRE3 + 0x00007F00, // - LRFDRFE.CAL1 + 0x31381002, // HW 16-bit region (start address = 0x3138, count = 3) + 0x047FDF7F, // LRFDRFE.PLLMON1 LRFDRFE.PLLMON0 + 0x00001804, // - LRFDRFE.MOD0 + 0x202A5001, // RAM 16-bit region (start address = 0x202A, count = 2) + 0x00B400B4, // PBE_BLE5_RAM.RECALTIMEOUT PBE_BLE5_RAM.SYNTHCALTIMEOUT + 0x00007001, // RAM sparse region (address/value pairs, count = 2) + 0x20320197, // PBE_BLE5_RAM.FIFOCFG + 0x20360002, // PBE_BLE5_RAM.NAKHUB + 0x68046005, // RAM 32-bit region (start address = 0x6804, count = 6) + 0x03000012, // RFE_COMMON_RAM.TDCCAL0 RFE_COMMON_RAM.SYNTHCTL + 0x00100000, // RFE_COMMON_RAM.TDCCAL2 RFE_COMMON_RAM.TDCCAL1 + 0x569B0400, // RFE_COMMON_RAM.K1LSB RFE_COMMON_RAM.TDCPLL + 0x012D010A, // RFE_COMMON_RAM.K2BL RFE_COMMON_RAM.K1MSB + 0x132C0034, // RFE_COMMON_RAM.K3BL RFE_COMMON_RAM.K2AL + 0x916F07AB, // RFE_COMMON_RAM.K5 RFE_COMMON_RAM.K3AL + 0x68206005, // RAM 32-bit region (start address = 0x6820, count = 6) + 0x00000000, // RFE_COMMON_RAM.RTRIMMIN RFE_COMMON_RAM.RTRIMOFF + 0x48080008, // RFE_COMMON_RAM.DIVF RFE_COMMON_RAM.DIVI + 0x00000000, // RFE_COMMON_RAM.DIVLDOF RFE_COMMON_RAM.DIVLDOI + 0x00470014, // RFE_COMMON_RAM.LDOSETTLE RFE_COMMON_RAM.DIVLDOIOFF + 0x0005002E, // RFE_COMMON_RAM.DCOSETTLE RFE_COMMON_RAM.CHRGSETTLE + 0x0000FE00 // RFE_COMMON_RAM.IFAMPRFLDODEFAULT RFE_COMMON_RAM.IFAMPRFLDOTX +}; + +// Configuration: Sub-PHY = 1 Mbps, 2 Mbps +static const uint32_t LRF_subPhy1Mbps2MbpsRegConfig[] = +{ + 0x00024010, // Segment length = 16 + 0x00003004, // HW sparse region (address/value pairs, count = 5) + 0x1098AAAA, // LRFDPBE.MDMCMDPAR2 + 0x20B80015, // LRFDMDM.SYSTIMEVTMUX0 + 0x20F48087, // LRFDMDM.DEMDSBU + 0x2134005F, // LRFDMDM.DEMSWQU0 + 0x30A41F40, // LRFDRFE.SPARE3 + 0x21001008, // HW 16-bit region (start address = 0x2100, count = 9) + 0x00040224, // LRFDMDM.DEMDSXB0 LRFDMDM.DEMFEXB0 + 0x04000005, // LRFDMDM.DEMMAFI0 LRFDMDM.DEMFIFE0 + 0x00C17B20, // LRFDMDM.DEMMAFI2 LRFDMDM.DEMMAFI1 + 0x7F27000F, // LRFDMDM.DEMC1BE1 LRFDMDM.DEMC1BE0 + 0x0000017F, // - LRFDMDM.DEMC1BE2 + 0x30B0B000, // HW masked region (mask/value pairs, count = 1) + 0xFF0F000A, // LRFDRFE.LNA + 0x68425001, // RAM 16-bit region (start address = 0x6842, count = 2) + 0x00000045 // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW +}; + +// Configuration: Sub-PHY = 1 Mbps, Coded +static const uint32_t LRF_subPhy1MbpsCodedRegConfig[] = +{ + 0x00014005, // Segment length = 5 + 0x0000A000, // Data structure 32-bit region (start byte position = 0, count = 1) + (uint32_t) &LRF_swConfig1Mbps, // LRF_swParam : swConfig + 0x00003001, // HW sparse region (address/value pairs, count = 2) + 0x20D44000, // LRFDMDM.BAUD + 0x21240A18 // LRFDMDM.SPARE0 +}; + +// Configuration: Sub-PHY = 2 Mbps, Coded +static const uint32_t LRF_subPhy2MbpsCodedRegConfig[] = +{ + 0x00030002, // Segment length = 2 + 0x00007000, // RAM sparse region (address/value pairs, count = 1) + 0x683E004C // RFE_COMMON_RAM.PHYRSSIOFFSET +}; + +// Configuration: Sub-PHY = 1 Mbps +static const uint32_t LRF_subPhy1MbpsRegConfig[] = +{ + 0x0003400D, // Segment length = 13 + 0x00003002, // HW sparse region (address/value pairs, count = 3) + 0x10908007, // LRFDPBE.MDMCMDPAR0 + 0x20F80F50, // LRFDMDM.DEMCODC0 + 0x30A0A246, // LRFDRFE.SPARE2 + 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) + 0x118205F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 + 0x00007000, // RAM sparse region (address/value pairs, count = 1) + 0x20200000, // PBE_BLE5_RAM.PHY + 0x20245002, // RAM 16-bit region (start address = 0x2024, count = 3) + 0x01AE018E, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS + 0x00000226, // - PBE_BLE5_RAM.RXTIMEOUT + 0x683E5001, // RAM 16-bit region (start address = 0x683E, count = 2) + 0x75F80050 // RFE_COMMON_RAM.SPARE0SHADOW RFE_COMMON_RAM.PHYRSSIOFFSET +}; + +// Configuration: Sub-PHY = 2 Mbps +static const uint32_t LRF_subPhy2MbpsRegConfig[] = +{ + 0x00010010, // Segment length = 16 + 0x0000A000, // Data structure 32-bit region (start byte position = 0, count = 1) + (uint32_t) &LRF_swConfig2Mbps, // LRF_swParam : swConfig + 0x00003004, // HW sparse region (address/value pairs, count = 5) + 0x1090800F, // LRFDPBE.MDMCMDPAR0 + 0x20D48000, // LRFDMDM.BAUD + 0x20F80F70, // LRFDMDM.DEMCODC0 + 0x21240A2C, // LRFDMDM.SPARE0 + 0x30A0A357, // LRFDRFE.SPARE2 + 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) + 0x108100F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 + 0x00007001, // RAM sparse region (address/value pairs, count = 2) + 0x20200001, // PBE_BLE5_RAM.PHY + 0x684055FA, // RFE_COMMON_RAM.SPARE0SHADOW + 0x20245002, // RAM 16-bit region (start address = 0x2024, count = 3) + 0x018C01B2, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS + 0x000001C2 // - PBE_BLE5_RAM.RXTIMEOUT +}; + +// Configuration: Sub-PHY = Coded +static const uint32_t LRF_subPhyCodedRegConfig[] = +{ + 0x00020019, // Segment length = 25 + 0x00003001, // HW sparse region (address/value pairs, count = 2) + 0x10900097, // LRFDPBE.MDMCMDPAR0 + 0x10983C3C, // LRFDPBE.MDMCMDPAR2 + 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) + 0x158210F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 + 0x20F41001, // HW 16-bit region (start address = 0x20F4, count = 2) + 0x06F0808D, // LRFDMDM.DEMCODC0 LRFDMDM.DEMDSBU + 0x21001008, // HW 16-bit region (start address = 0x2100, count = 9) + 0x00060A24, // LRFDMDM.DEMDSXB0 LRFDMDM.DEMFEXB0 + 0x0000000C, // LRFDMDM.DEMMAFI0 LRFDMDM.DEMFIFE0 + 0x00783C14, // LRFDMDM.DEMMAFI2 LRFDMDM.DEMMAFI1 + 0x7F7F001F, // LRFDMDM.DEMC1BE1 LRFDMDM.DEMC1BE0 + 0x0000014C, // - LRFDMDM.DEMC1BE2 + 0x30941001, // HW 16-bit region (start address = 0x3094, count = 2) + 0x34F21307, // LRFDRFE.SPARE0 LRFDRFE.MAGNCTL1 + 0x34502000, // HW 32-bit region (start address = 0x3450, count = 1) + 0x00B00013, // LRFDRFE.SPARE3 LRFDRFE.SPARE2 + 0x30B0B000, // HW masked region (mask/value pairs, count = 1) + 0xFF0F000E, // LRFDRFE.LNA + 0x20205004, // RAM 16-bit region (start address = 0x2020, count = 5) + 0x01200003, // PBE_BLE5_RAM.PRETXIFS500K PBE_BLE5_RAM.PHY + 0x012C0102, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS + 0x000007EA, // - PBE_BLE5_RAM.RXTIMEOUT + 0x68425001, // RAM 16-bit region (start address = 0x6842, count = 2) + 0x0001001C // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW +}; + +// Configuration: Coded TX rate = S8 (8 symbols per bit = 125 kbps) +static const uint32_t LRF_codedTxRateS8RegConfig[] = +{ + 0x00044002, // Segment length = 2 + 0x00003000, // HW sparse region (address/value pairs, count = 1) + 0x21280000 // LRFDMDM.SPARE1 +}; + +// Configuration: Coded TX rate = S2 (2 symbols per bit = 500 kbps) +static const uint32_t LRF_codedTxRateS2RegConfig[] = +{ + 0x00040002, // Segment length = 2 + 0x00003000, // HW sparse region (address/value pairs, count = 1) + 0x21280001 // LRFDMDM.SPARE1 +}; + + +// LRF register configuration list +static const LRF_RegConfigList LRF_regConfigList = { + .numEntries = 9, + .entries = { + (LRF_ConfigWord*) LRF_commonRegConfig, + (LRF_ConfigWord*) LRF_subPhy1Mbps2MbpsRegConfig, + (LRF_ConfigWord*) LRF_subPhy1MbpsCodedRegConfig, + (LRF_ConfigWord*) LRF_subPhy2MbpsCodedRegConfig, + (LRF_ConfigWord*) LRF_subPhy1MbpsRegConfig, + (LRF_ConfigWord*) LRF_subPhy2MbpsRegConfig, + (LRF_ConfigWord*) LRF_subPhyCodedRegConfig, + (LRF_ConfigWord*) LRF_codedTxRateS8RegConfig, + (LRF_ConfigWord*) LRF_codedTxRateS2RegConfig + } +}; + +// LRF_TxShape data structure +const LRF_TxShape LRF_shapeBaseGfsk067 = { + .scale = 0x0FDE2, + .numCoeff = 0x0011, + .coeff = { 0x01, 0x02, 0x05, 0x0A, 0x14, 0x22, 0x37, 0x52, 0x71, 0x91, 0xB0, 0xCB, 0xE0, 0xEE, 0xF8, 0xFD, 0xFF } +}; + +// LRF_TxShape data structure +const LRF_TxShape LRF_shapeBaseGfsk05 = { + .scale = 0x0F183, + .numCoeff = 0x0014, + .coeff = { 0x01, 0x02, 0x03, 0x06, 0x0A, 0x11, 0x1A, 0x27, 0x37, 0x4B, 0x62, 0x7B, 0x94, 0xAD, 0xC4, 0xD8, 0xE7, 0xF3, 0xFB, 0xFF } +}; + +// LRF_SwConfig data structure +const LRF_SwConfig LRF_swConfig1Mbps = { + .rxIntFrequency = 1000000, + .rxFrequencyOffset = 0, + .txFrequencyOffset = 1000000, + .modFrequencyDeviation = 0x0003D090, + .txShape = &LRF_shapeBaseGfsk067, + .bwIndex = 0x00, + .bwIndexDither = 0x01 +}; + +// LRF_SwConfig data structure +const LRF_SwConfig LRF_swConfig2Mbps = { + .rxIntFrequency = 850000, + .rxFrequencyOffset = 0, + .txFrequencyOffset = 850000, + .modFrequencyDeviation = 0x0007A120, + .txShape = &LRF_shapeBaseGfsk05, + .bwIndex = 0x01, + .bwIndexDither = 0x01 +}; + +// LRF_TxPowerTable data structure +const LRF_TxPowerTable LRF_txPowerTable = { + .numEntries = 0x0000000E, + .powerTable = { + { .power = { .fraction = 0, .dBm = -20 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 18, .gain = 0, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = -16 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 20, .gain = 1, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = -12 }, .tempCoeff = 5, .value = { .reserved = 0, .ib = 17, .gain = 3, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = -8 }, .tempCoeff = 12, .value = { .reserved = 0, .ib = 17, .gain = 4, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = -4 }, .tempCoeff = 25, .value = { .reserved = 0, .ib = 17, .gain = 5, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 0 }, .tempCoeff = 40, .value = { .reserved = 0, .ib = 19, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 1 }, .tempCoeff = 65, .value = { .reserved = 0, .ib = 30, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 2 }, .tempCoeff = 41, .value = { .reserved = 0, .ib = 39, .gain = 4, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 3 }, .tempCoeff = 43, .value = { .reserved = 0, .ib = 31, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 4 }, .tempCoeff = 50, .value = { .reserved = 0, .ib = 37, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 5 }, .tempCoeff = 55, .value = { .reserved = 0, .ib = 27, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 6 }, .tempCoeff = 75, .value = { .reserved = 0, .ib = 38, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 7 }, .tempCoeff = 80, .value = { .reserved = 0, .ib = 25, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } }, + { .power = { .fraction = 0, .dBm = 8 }, .tempCoeff = 180, .value = { .reserved = 0, .ib = 63, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } } + } +}; + +// LRF_Config data structure +const LRF_Config LRF_config = { + .pbeImage = (const LRF_TOPsmImage*) LRF_PBE_binary_ble5, + .mceImage = (const LRF_TOPsmImage*) LRF_MCE_binary_ble5, + .rfeImage = (const LRF_TOPsmImage*) LRF_RFE_binary_ble5, + .regConfigList = &LRF_regConfigList +}; diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.h b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.h new file mode 100644 index 00000000..28d84bc6 --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/rcl_settings_ble.h @@ -0,0 +1,324 @@ +// SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (HEADER FILE) +// +// Usage Protocol stack +// +// +// CODE EXPORT INFORMATION +// This file is generated +// +// Tool name SmartRF Studio 8 +// Tool version 0.6.0.327 INTERNAL +// +// +// WORKSPACE INFORMATION +// +// Workspace file srf_cli.workspace +// Device CC2340R5 +// Package QFN40 5x5 RKP +// Revision(s) B (2.0) +// SDK SimpleLink LPF3 SDK 8.11.00.09 +// Board LP-EM-CC2340R5 +// PHY 2.4 GHz - Bluetooth 5, LE - 1 Mbps / 2 Mbps / Coded +// +// +// PHY PROPERTIES +// +// Run-time properties: +// Sub-PHY 1 Mbps +// Channel 17 (2440 MHz) +// TX output power 5.0 dBm + +#ifndef RCLSETTINGS_H +#define RCLSETTINGS_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_fcfg.h) + + +// PHY features +#define RCL_PHY_FEATURE_SUB_PHY_1_MBPS 0x0000 +#define RCL_PHY_FEATURE_SUB_PHY_2_MBPS 0x0001 +#define RCL_PHY_FEATURE_SUB_PHY_CODED 0x0002 +#define RCL_PHY_FEATURE_CODED_TX_RATE_S8 0x0000 +#define RCL_PHY_FEATURE_CODED_TX_RATE_S2 0x0004 + + +// LRF data structures +extern const LRF_TxShape LRF_shapeBaseGfsk067; +extern const LRF_TxShape LRF_shapeBaseGfsk05; +extern const LRF_SwConfig LRF_swConfig1Mbps; +extern const LRF_SwConfig LRF_swConfig2Mbps; +extern const LRF_TxPowerTable LRF_txPowerTable; +extern const LRF_Config LRF_config; + + +// SUB-PHY register field values + +// Address Module Register Bit(s) Field Value (1_MBPS) Value (2_MBPS) Value (CODED) +// --------------------------------------------------------------------------------------------------------------------------------- +// 0x1090 LRFDPBE MDMCMDPAR0 [15:0] VAL 0x8007 0x800F 0x0097 +// 0x1098 LRFDPBE MDMCMDPAR2 [15:0] VAL 0xAAAA 0xAAAA 0x3C3C +// 0x10A0 LRFDPBE POLY0L [15:0] VALLSB 0x0000 0x0000 0x0000 +// 0x10A4 LRFDPBE POLY0H [15:0] VALMSB 0x2200 0x2200 0x2200 +// 0x10A8 LRFDPBE POLY1L [15:0] VALLSB 0x5B00 0x5B00 0x5B00 +// 0x10AC LRFDPBE POLY1H [15:0] VALMSB 0x0006 0x0006 0x0006 +// 0x10B4 LRFDPBE FCFG0 [5] TXACOM 0x1 0x1 0x1 +// 0x10B4 LRFDPBE FCFG0 [4] TXADEAL 0x0 0x0 0x0 +// 0x10B4 LRFDPBE FCFG0 [1] RXACOM 0x0 0x0 0x0 +// 0x10B4 LRFDPBE FCFG0 [0] RXADEAL 0x1 0x1 0x1 +// 0x10B8 LRFDPBE FCFG1 [8:0] TXSTRT 0x0C4 0x0C4 0x0C4 +// 0x10BC LRFDPBE FCFG2 [7:0] TXSIZE 0x86 0x86 0x86 +// 0x10C0 LRFDPBE FCFG3 [8:0] RXSTRT 0x080 0x080 0x080 +// 0x10C4 LRFDPBE FCFG4 [7:0] RXSIZE 0x44 0x44 0x44 +// 0x10D0 LRFDPBE RXFRBTHRS [9:0] BYTES 0x004 0x004 0x004 +// 0x10D4 LRFDPBE TXFWBTHRS [9:0] BYTES 0x002 0x002 0x002 +// 0x10DC LRFDPBE TIMCTL [9] SRC1 0x1 0x1 0x1 +// 0x10DC LRFDPBE TIMCTL [1] SRC0 0x1 0x1 0x1 +// 0x10E0 LRFDPBE TIMPRE [13:8] PRE1 0x0B 0x0B 0x0B +// 0x10E0 LRFDPBE TIMPRE [5:0] PRE0 0x0B 0x0B 0x0B +// 0x20B8 LRFDMDM SYSTIMEVTMUX0 [11:6] SEL1 0x00 0x00 - +// 0x20B8 LRFDMDM SYSTIMEVTMUX0 [5:0] SEL0 0x15 0x15 - +// 0x20C0 LRFDMDM ADCDIGCONF [1] QBRANCHEN 0x1 0x1 0x1 +// 0x20C0 LRFDMDM ADCDIGCONF [0] IBRANCHEN 0x1 0x1 0x1 +// 0x20C8 LRFDMDM MODSYMMAP0 [7:4] SYM1 0x1 0x1 0x1 +// 0x20C8 LRFDMDM MODSYMMAP0 [3:0] SYM0 0xF 0xF 0xF +// 0x20D4 LRFDMDM BAUD [15:0] RATEWORD 0x4000 0x8000 0x4000 +// 0x20D8 LRFDMDM BAUDPRE [15:13] ALIGNVALUE 0x0 0x0 0x0 +// 0x20D8 LRFDMDM BAUDPRE [12:8] EXTRATEWORD - - 0x00 +// 0x20D8 LRFDMDM BAUDPRE [7:0] PRESCALER 0x0C 0x0C 0x0C +// 0x20DC LRFDMDM MODMAIN [3:2] FECSELECT 0x0 0x0 0x0 +// 0x20DC LRFDMDM MODMAIN [1:0] MODLEVELS 0x0 0x0 0x0 +// 0x20E4 LRFDMDM DEMMISC1 [1:0] CHFIBW 0x1 0x1 0x1 +// 0x20E8 LRFDMDM DEMMISC2 [13:12] MAFCGAIN 0x0 0x0 0x1 +// 0x20E8 LRFDMDM DEMMISC2 [11] STIMBYPASS 0x0 0x0 0x0 +// 0x20E8 LRFDMDM DEMMISC2 [10] STIMESTONLY 0x1 0x0 - +// 0x20E8 LRFDMDM DEMMISC2 [9:7] STIMTEAPERIOD 0x3 0x1 0x1 +// 0x20E8 LRFDMDM DEMMISC2 [6:4] STIMTEAGAIN 0x7 0x7 0x7 +// 0x20E8 LRFDMDM DEMMISC2 [3] PDIFLINPREDEN 0x1 0x1 0x1 +// 0x20E8 LRFDMDM DEMMISC2 [2] PDIFDESPECK 0x0 0x0 0x0 +// 0x20E8 LRFDMDM DEMMISC2 [1] PDIFIQCONJEN 0x0 0x0 0x0 +// 0x20E8 LRFDMDM DEMMISC2 [0] PDIFLIMITRANGE 0x1 0x1 0x1 +// 0x20EC LRFDMDM DEMMISC3 [14:13] BDE2DVGA 0x0 - 0x0 +// 0x20EC LRFDMDM DEMMISC3 [12] BDE1FILTMODE 0x1 0x1 0x1 +// 0x20EC LRFDMDM DEMMISC3 [11:10] LQIPERIOD - - 0x1 +// 0x20EC LRFDMDM DEMMISC3 [9:8] BDE1DVGA 0x1 - 0x1 +// 0x20EC LRFDMDM DEMMISC3 [7] BDE1NUMSTAGES 0x1 0x1 0x1 +// 0x20EC LRFDMDM DEMMISC3 [6:5] PDIFDECIM - - 0x0 +// 0x20EC LRFDMDM DEMMISC3 [4:0] BDE2DECRATIO 0x02 0x01 0x02 +// 0x20F0 LRFDMDM DEMIQMC0 [15:8] GAINFACTOR +// 0x20F0 LRFDMDM DEMIQMC0 [7:0] PHASEFACTOR +// 0x20F4 LRFDMDM DEMDSBU [15:8] DSBUAVGLENGTH 0x80 0x80 0x80 +// 0x20F4 LRFDMDM DEMDSBU [7:0] DSBUDELAY 0x87 0x87 0x8D +// 0x20F8 LRFDMDM DEMCODC0 [11] ESTSEL 0x1 0x1 0x0 +// 0x20F8 LRFDMDM DEMCODC0 [10:9] COMPSEL 0x3 0x3 0x3 +// 0x20F8 LRFDMDM DEMCODC0 [8] IIRUSEINITIAL 0x1 0x1 0x0 +// 0x20F8 LRFDMDM DEMCODC0 [7:5] IIRGAIN 0x2 0x3 0x7 +// 0x20F8 LRFDMDM DEMCODC0 [4] IIREN 0x1 0x1 0x1 +// 0x20FC LRFDMDM DEMFIDC0 [5:4] COMPSEL 0x0 0x0 0x0 +// 0x2100 LRFDMDM DEMFEXB0 [13] OUT2PASSTHROUGH - - 0x0 +// 0x2100 LRFDMDM DEMFEXB0 [12:11] OUT2SRCSEL - - 0x1 +// 0x2100 LRFDMDM DEMFEXB0 [10] OUT1PASSTHROUGH 0x0 0x0 0x0 +// 0x2100 LRFDMDM DEMFEXB0 [9:8] OUT1SRCSEL 0x2 0x2 0x2 +// 0x2100 LRFDMDM DEMFEXB0 [5:4] B3SRCSEL 0x2 0x2 0x2 +// 0x2100 LRFDMDM DEMFEXB0 [3:2] B2SRCSEL 0x1 0x1 0x1 +// 0x2100 LRFDMDM DEMFEXB0 [1:0] B1SRCSEL 0x0 0x0 0x0 +// 0x2104 LRFDMDM DEMDSXB0 [5] OUT2PASSTHROUGH 0x0 - - +// 0x2104 LRFDMDM DEMDSXB0 [3] OUTSRCSEL2 0x0 0x0 0x0 +// 0x2104 LRFDMDM DEMDSXB0 [2] OUTSRCSEL1 0x1 0x1 0x1 +// 0x2104 LRFDMDM DEMDSXB0 [1] B2SRCSEL 0x0 0x0 0x1 +// 0x2104 LRFDMDM DEMDSXB0 [0] B1SRCSEL 0x0 0x0 0x0 +// 0x2108 LRFDMDM DEMFIFE0 [11] FINEFOESEL 0x0 0x0 0x0 +// 0x2108 LRFDMDM DEMFIFE0 [10:9] FOCFFSEL 0x0 0x0 0x0 +// 0x2108 LRFDMDM DEMFIFE0 [4] IIRUSEINITIAL 0x0 0x0 0x0 +// 0x2108 LRFDMDM DEMFIFE0 [3:1] IIRGAIN 0x2 0x2 0x6 +// 0x2108 LRFDMDM DEMFIFE0 [0] IIREN 0x1 0x1 0x0 +// 0x210C LRFDMDM DEMMAFI0 [15:8] C1C7 0x04 0x04 0x00 +// 0x210C LRFDMDM DEMMAFI0 [7:0] C0C8 0x00 0x00 0x00 +// 0x2110 LRFDMDM DEMMAFI1 [15:8] C3C5 0x7B 0x7B 0x3C +// 0x2110 LRFDMDM DEMMAFI1 [7:0] C2C6 0x20 0x20 0x14 +// 0x2114 LRFDMDM DEMMAFI2 [8:0] C4 0x0C1 0x0C1 0x078 +// 0x2118 LRFDMDM DEMC1BE0 [15:11] MASKB 0x00 0x00 0x00 +// 0x2118 LRFDMDM DEMC1BE0 [10:6] MASKA 0x00 0x00 0x00 +// 0x2118 LRFDMDM DEMC1BE0 [5:4] CASCCONF 0x0 0x0 0x1 +// 0x2118 LRFDMDM DEMC1BE0 [3:0] COPYCONF 0xF 0xF 0xF +// 0x211C LRFDMDM DEMC1BE1 [15:8] THRESHOLDB 0x7F 0x7F 0x7F +// 0x211C LRFDMDM DEMC1BE1 [7:0] THRESHOLDA 0x27 0x27 0x7F +// 0x2120 LRFDMDM DEMC1BE2 [9:8] PEAKCONF 0x1 0x1 0x1 +// 0x2120 LRFDMDM DEMC1BE2 [7:0] THRESHOLDC 0x7F 0x7F 0x4C +// 0x2124 LRFDMDM SPARE0 [15:0] VAL 0x0A18 0x0A2C 0x0A18 +// 0x2134 LRFDMDM DEMSWQU0 [6] AUTOMAFC 0x1 0x1 - +// 0x2134 LRFDMDM DEMSWQU0 [4:0] REFLEN 0x1F 0x1F - +// 0x3080 LRFDRFE MAGNTHRCFG [1] SEL 0x0 0x0 0x0 +// 0x3088 LRFDRFE RSSIOFFSET [7:0] VAL +// 0x3094 LRFDRFE MAGNCTL1 [12] PERMODE - - 0x1 +// 0x3094 LRFDRFE MAGNCTL1 [11:8] SCL - - 0x3 +// 0x3094 LRFDRFE MAGNCTL1 [7:0] PER - - 0x07 +// 0x3098 LRFDRFE SPARE0 [15:0] VAL - - 0x34F2 +// 0x30A0 LRFDRFE SPARE2 [15:0] VAL 0xA246 0xA357 0x0013 +// 0x30A4 LRFDRFE SPARE3 [15:0] VAL 0x1F40 0x1F40 0x00B0 +// 0x30A8 LRFDRFE SPARE4 [15:0] VAL 0x0000 0x0000 0x0000 +// 0x30B0 LRFDRFE LNA [7:4] TRIM +// 0x30B0 LRFDRFE LNA [3] BIAS 0x1 0x1 0x1 +// 0x30B0 LRFDRFE LNA [2:1] IB 0x1 0x1 0x3 +// 0x30B4 LRFDRFE IFAMPRFLDO [15:9] TRIM +// 0x30B4 LRFDRFE IFAMPRFLDO [7:4] AAFCAP +// 0x30B4 LRFDRFE IFAMPRFLDO [3:1] IFAMPIB 0x3 0x3 0x3 +// 0x30B8 LRFDRFE PA0 [4:0] TRIM +// 0x30C4 LRFDRFE IFADC0 [14:12] DITHERTRIM +// 0x30C4 LRFDRFE IFADC0 [11:10] DITHEREN +// 0x30C4 LRFDRFE IFADC0 [7:4] INT2ADJ +// 0x30C4 LRFDRFE IFADC0 [3:2] AAFCAP +// 0x30C8 LRFDRFE IFADC1 [15] NRZ +// 0x30C8 LRFDRFE IFADC1 [14:9] TRIM +// 0x30CC LRFDRFE IFADCLF [15:12] FF3 +// 0x30CC LRFDRFE IFADCLF [11:8] FF2 +// 0x30CC LRFDRFE IFADCLF [7:4] FF1 +// 0x30CC LRFDRFE IFADCLF [3:0] INT3 +// 0x30D0 LRFDRFE IFADCQUANT [2:0] QUANTTHR +// 0x30D4 LRFDRFE IFADCALDO [13:8] TRIMOUT +// 0x30D8 LRFDRFE IFADCDLDO [13:8] TRIMOUT +// 0x30E4 LRFDRFE ATSTREFH [14:10] IREFTRIM +// 0x30E4 LRFDRFE ATSTREFH [9] BIAS 0x1 0x1 0x1 +// 0x30E8 LRFDRFE DCO [6:3] TAILRESTRIM +// 0x30E8 LRFDRFE DCO [0] CRSCAPCM 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [15] PDET 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [14:12] NMIREFTRIM 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [11:9] PMIREFTRIM 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [8] TXBBOOST 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [7] S1GFRC 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [6:5] BUFGAIN 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [4] BIAS 0x0 0x0 0x0 +// 0x30EC LRFDRFE DIV [3] OUT 0x1 0x1 0x1 +// 0x30EC LRFDRFE DIV [2:0] RATIO 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [15] SPARE15 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [14:8] VOUTTRIM +// 0x30F0 LRFDRFE DIVLDO [7] ITST 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [6:4] TMUX 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [3] SPARE3 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [2] MODE 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [1] BYPASS 0x0 0x0 0x0 +// 0x30F0 LRFDRFE DIVLDO [0] CTL 0x0 0x0 0x0 +// 0x30F4 LRFDRFE TDCLDO [14:8] VOUTTRIM +// 0x30F8 LRFDRFE DCOLDO0 [13:8] SECONDTRIM +// 0x30F8 LRFDRFE DCOLDO0 [7:4] FIRSTTRIM +// 0x30FC LRFDRFE DCOLDO1 [10] REFSRC 0x0 0x0 0x0 +// 0x30FC LRFDRFE DCOLDO1 [9:8] DIVATST 0x0 0x0 0x0 +// 0x3100 LRFDRFE PRE0 [13:8] PLLDIV1 0x07 0x07 0x07 +// 0x3100 LRFDRFE PRE0 [5:0] PLLDIV0 0x06 0x06 0x06 +// 0x3104 LRFDRFE PRE1 [5:0] HSDDC 0x00 0x00 0x00 +// 0x3108 LRFDRFE PRE2 [15:12] MIDCALDIVLSB 0x0 0x0 0x0 +// 0x3108 LRFDRFE PRE2 [11:6] CRSCALDIV 0x18 0x18 0x18 +// 0x3108 LRFDRFE PRE2 [5:0] FSMDIV 0x05 0x05 0x05 +// 0x310C LRFDRFE PRE3 [15:5] FINECALDIV 0x030 0x030 0x030 +// 0x310C LRFDRFE PRE3 [4:0] MIDCALDIVMSB 0x03 0x03 0x03 +// 0x3110 LRFDRFE CAL0 [14:8] FCSTART 0x40 0x40 0x40 +// 0x3110 LRFDRFE CAL0 [3:2] TDCAVG 0x2 0x2 0x2 +// 0x3114 LRFDRFE CAL1 [14:8] FCTOP 0x7F 0x7F 0x7F +// 0x3114 LRFDRFE CAL1 [6:0] FCBOT 0x00 0x00 0x00 +// 0x3120 LRFDRFE MISC0 [13] PHCPT 0x0 0x0 0x0 +// 0x3120 LRFDRFE MISC0 [12] TDCCALCORR 0x1 0x1 0x1 +// 0x3120 LRFDRFE MISC0 [11] TDCMSBCORR 0x1 0x1 0x1 +// 0x3120 LRFDRFE MISC0 [5:4] DLYCANCRS 0x2 0x2 0x2 +// 0x3130 LRFDRFE PHEDISC [13:10] CNT 0x3 0x3 0x3 +// 0x3130 LRFDRFE PHEDISC [9:0] THR 0x007 0x007 0x007 +// 0x3138 LRFDRFE PLLMON0 [15:14] PHELOLCNT 0x3 0x3 0x3 +// 0x3138 LRFDRFE PLLMON0 [13:8] PHELOLTHR 0x1F 0x1F 0x1F +// 0x3138 LRFDRFE PLLMON0 [6:0] FCTHR 0x7F 0x7F 0x7F +// 0x313C LRFDRFE PLLMON1 [12:8] PHELOCKCNT 0x04 0x04 0x04 +// 0x313C LRFDRFE PLLMON1 [7:0] PHELOCKTHR 0x7F 0x7F 0x7F +// 0x3140 LRFDRFE MOD0 [12:11] SCHEME 0x3 0x3 0x3 +// 0x3140 LRFDRFE MOD0 [10:8] SYMSHP 0x0 0x0 0x0 +// 0x3140 LRFDRFE MOD0 [3:2] INTPFACT 0x1 0x1 0x1 +// 0x2020 PBE_BLE5_RAM PHY [1:0] SEL 0x0 0x1 0x3 +// 0x2022 PBE_BLE5_RAM PRETXIFS500K [15:0] VAL - - 0x0120 +// 0x2024 PBE_BLE5_RAM PRETXIFS [15:0] VAL 0x018E 0x01B2 0x0102 +// 0x2026 PBE_BLE5_RAM PRERXIFS [15:0] VAL 0x01AE 0x018C 0x012C +// 0x2028 PBE_BLE5_RAM RXTIMEOUT [15:0] VAL 0x0226 0x01C2 0x07EA +// 0x202A PBE_BLE5_RAM SYNTHCALTIMEOUT [15:0] VAL 0x00B4 0x00B4 0x00B4 +// 0x202C PBE_BLE5_RAM RECALTIMEOUT [15:0] VAL 0x00B4 0x00B4 0x00B4 +// 0x2032 PBE_BLE5_RAM FIFOCFG [8] APPENDTIMESTAMP 0x1 0x1 0x1 +// 0x2032 PBE_BLE5_RAM FIFOCFG [7] APPENDRSSI 0x1 0x1 0x1 +// 0x2032 PBE_BLE5_RAM FIFOCFG [6] APPENDFREQEST 0x0 0x0 0x0 +// 0x2032 PBE_BLE5_RAM FIFOCFG [5] APPENDLQI 0x0 0x0 0x0 +// 0x2032 PBE_BLE5_RAM FIFOCFG [4] APPENDSTATUS 0x1 0x1 0x1 +// 0x2032 PBE_BLE5_RAM FIFOCFG [3] APPENDCRC 0x0 0x0 0x0 +// 0x2032 PBE_BLE5_RAM FIFOCFG [2] AUTOFLUSHEMPTY 0x1 0x1 0x1 +// 0x2032 PBE_BLE5_RAM FIFOCFG [1] AUTOFLUSHIGN 0x1 0x1 0x1 +// 0x2032 PBE_BLE5_RAM FIFOCFG [0] AUTOFLUSHCRC 0x1 0x1 0x1 +// 0x2036 PBE_BLE5_RAM NAKHUB [2:0] MAXNAK 0x2 0x2 0x2 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [7] CHRGFILT 0x0 0x0 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [6] VREFBP 0x0 0x0 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [5] TXWAITMOD 0x0 0x0 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [4] PHEDISC 0x1 0x1 0x1 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [3] RTRIMTST 0x0 0x0 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [2] IIR 0x0 0x0 0x0 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [1] REFDTHR 0x1 0x1 0x1 +// 0x6804 RFE_COMMON_RAM SYNTHCTL [0] FCDEM 0x0 0x0 0x0 +// 0x6806 RFE_COMMON_RAM TDCCAL0 [10:8] STOP 0x3 0x3 0x3 +// 0x6808 RFE_COMMON_RAM TDCCAL1 [7:0] SUB 0x00 0x00 0x00 +// 0x680A RFE_COMMON_RAM TDCCAL2 [5:0] AVG 0x10 0x10 0x10 +// 0x680C RFE_COMMON_RAM TDCPLL [10:8] STOP 0x4 0x4 0x4 +// 0x680E RFE_COMMON_RAM K1LSB [15:0] VAL 0x569B 0x569B 0x569B +// 0x6810 RFE_COMMON_RAM K1MSB [15:0] VAL 0x010A 0x010A 0x010A +// 0x6812 RFE_COMMON_RAM K2BL [15] HPM 0x0 0x0 0x0 +// 0x6812 RFE_COMMON_RAM K2BL [14:0] VAL 0x012D 0x012D 0x012D +// 0x6814 RFE_COMMON_RAM K2AL [15] HPM 0x0 0x0 0x0 +// 0x6814 RFE_COMMON_RAM K2AL [14:0] VAL 0x0034 0x0034 0x0034 +// 0x6816 RFE_COMMON_RAM K3BL [15:0] VAL 0x132C 0x132C 0x132C +// 0x6818 RFE_COMMON_RAM K3AL [15:0] VAL 0x07AB 0x07AB 0x07AB +// 0x681A RFE_COMMON_RAM K5 [15:0] VAL 0x916F 0x916F 0x916F +// 0x6820 RFE_COMMON_RAM RTRIMOFF [3:0] VAL 0x0 0x0 0x0 +// 0x6822 RFE_COMMON_RAM RTRIMMIN [3:0] VAL 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [15] PDET 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [14:12] NMIREFTRIM 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [11:9] PMIREFTRIM 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [8] TXBOOST 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [7] S1GFRC 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [6:5] BUFGAIN 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [4] BIAS 0x0 0x0 0x0 +// 0x6824 RFE_COMMON_RAM DIVI [3] OUT 0x1 0x1 0x1 +// 0x6824 RFE_COMMON_RAM DIVI [2:0] RATIO 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [15] PDET 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [14:12] NMIREFTRIM 0x4 0x4 0x4 +// 0x6826 RFE_COMMON_RAM DIVF [11:9] PMIREFTRIM 0x4 0x4 0x4 +// 0x6826 RFE_COMMON_RAM DIVF [8] TXBOOST 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [7] S1GFRC 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [6:5] BUFGAIN 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [4] BIAS 0x0 0x0 0x0 +// 0x6826 RFE_COMMON_RAM DIVF [3] OUT 0x1 0x1 0x1 +// 0x6826 RFE_COMMON_RAM DIVF [2:0] RATIO 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [15] ITEST 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [14:8] VOUTTRIM 0x00 0x00 0x00 +// 0x6828 RFE_COMMON_RAM DIVLDOI [7] ITST 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [6:4] TMUX 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [2] MODE 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [1] BYPASS 0x0 0x0 0x0 +// 0x6828 RFE_COMMON_RAM DIVLDOI [0] CTL 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [15] ITEST 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [14:8] VOUTTRIM 0x00 0x00 0x00 +// 0x682A RFE_COMMON_RAM DIVLDOF [7] ITST 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [6:4] TMUX 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [2] MODE 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [1] BYPASS 0x0 0x0 0x0 +// 0x682A RFE_COMMON_RAM DIVLDOF [0] CTL 0x0 0x0 0x0 +// 0x682C RFE_COMMON_RAM DIVLDOIOFF [6:0] VAL 0x14 0x14 0x14 +// 0x682E RFE_COMMON_RAM LDOSETTLE [9:0] VAL 0x047 0x047 0x047 +// 0x6830 RFE_COMMON_RAM CHRGSETTLE [9:0] VAL 0x02E 0x02E 0x02E +// 0x6832 RFE_COMMON_RAM DCOSETTLE [9:0] VAL 0x005 0x005 0x005 +// 0x6834 RFE_COMMON_RAM IFAMPRFLDOTX [15:9] TRIM 0x7F 0x7F 0x7F +// 0x6836 RFE_COMMON_RAM IFAMPRFLDODEFAULT [15:9] TRIM 0x00 0x00 0x00 +// 0x683E RFE_COMMON_RAM PHYRSSIOFFSET [7:0] VAL 0x50 0x4C 0x4C +// 0x6840 RFE_COMMON_RAM SPARE0SHADOW [15:0] VAL 0x75F8 0x55FA - +// 0x6842 RFE_COMMON_RAM SPARE1SHADOW [15:0] VAL 0x0045 0x0045 0x001C +// 0x6844 RFE_COMMON_RAM AGCINFO [0] MODE 0x0 0x0 0x1 + + +// CODED TX RATE register field values + +// Address Module Register Bit(s) Field Value (S8) Value (S2) +// --------------------------------------------------------------------------------------------------------------------------------- +// 0x2128 LRFDMDM SPARE1 [15:0] VAL 0x0000 0x0001 + + +#endif diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/ti_log_config.c b/simplelink_lpf3/source/ti/boards/cc23x0r5/ti_log_config.c new file mode 100644 index 00000000..6202d39d --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/ti_log_config.c @@ -0,0 +1,23 @@ +#include + + +#ifndef _DBGCH_SUPPORTED +#define _DBGCH_SUPPORTED 0x07 +#endif + +#if (_DBGCH_SUPPORTED & 1) +Log_MODULE_DEFINE(LogShortCh1, Log_MODULE_INIT_SINK_TRC_SHORT(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(LogLongCh1, Log_MODULE_INIT_SINK_TRC_LONG(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(TestCaseShortCh1, Log_MODULE_INIT_SINK_TRC_SHORT(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(TestCaseLongCh1, Log_MODULE_INIT_SINK_TRC_LONG(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(RclCoreShortCh1, Log_MODULE_INIT_SINK_TRC_SHORT(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(RclCoreLongCh1, Log_MODULE_INIT_SINK_TRC_LONG(Log_ALL | Log_ENABLED)); +#endif +#if (_DBGCH_SUPPORTED & 2) +Log_MODULE_DEFINE(LogShortCh2, Log_MODULE_INIT_SINK_TRC_SHORT(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(LogLongCh2, Log_MODULE_INIT_SINK_TRC_LONG(Log_ALL | Log_ENABLED)); +#endif +#if (_DBGCH_SUPPORTED & 4) +Log_MODULE_DEFINE(LogShortCh3, Log_MODULE_INIT_SINK_TRC_SHORT(Log_ALL | Log_ENABLED)); +Log_MODULE_DEFINE(LogLongCh3, Log_MODULE_INIT_SINK_TRC_LONG(Log_ALL | Log_ENABLED)); +#endif diff --git a/simplelink_lpf3/source/ti/boards/cc23x0r5/tracer_control.c b/simplelink_lpf3/source/ti/boards/cc23x0r5/tracer_control.c new file mode 100644 index 00000000..883c9524 --- /dev/null +++ b/simplelink_lpf3/source/ti/boards/cc23x0r5/tracer_control.c @@ -0,0 +1,106 @@ + +#include +#include +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdtrc.h) + +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_clkctl.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) + +#include +#include +#ifndef RCL_LITE_ONLY +#include +#endif + +static bool tracerEnabled = false; + +void RCL_Tracer_enable(void) +{ + /* TODO: As part of RCL-96, this should be changed so that enabling the clock is not part of + * the tracer wakeup routine, only the first enabling. That avoids the need for this global variable */ + if (!tracerEnabled) + { + tracerEnabled = true; + + /* Enable tracer clock */ + Power_setDependency(PowerLPF3_PERIPH_LRFD_TRC); + +#ifndef RCL_LITE_ONLY + /* Request power notification to keep tracer up after standby */ + RCL_openPowerNotifications(); +#endif + + /* Do the same enabling as after wakeup */ + RCL_Tracer_wakeup(); + } +} + +void RCL_Tracer_disable(void) +{ + if (tracerEnabled) + { + /* Disable tracer pins as when going to standby */ + RCL_Tracer_standby(); + +#ifndef RCL_LITE_ONLY + /* Remove power notifications */ + RCL_closePowerNotifications(); +#endif + + /* Disable the tracer */ + HWREG_WRITE_LRF(LRFDTRC_BASE + LRFDTRC_O_CFG) = (LRFDTRC_CFG_CH1EN_OFF) | + (LRFDTRC_CFG_CH2EN_OFF) | + (LRFDTRC_CFG_CH3EN_OFF) | + (LRFDTRC_CFG_TSEN_OFF); + + /* Disable tracer clock */ + Power_releaseDependency(PowerLPF3_PERIPH_LRFD_TRC); + + tracerEnabled = false; + } +} + +void RCL_Tracer_wakeup(void) +{ + if (tracerEnabled) + { + /* Enable the Tracer */ + HWREG_WRITE_LRF(LRFDTRC_BASE + LRFDTRC_O_CFG) = LRFDTRC_CFG_CH1EN_NORM | + LRFDTRC_CFG_CH2EN_TOPSM | + LRFDTRC_CFG_CH3EN_TOPSM | + LRFDTRC_CFG_TSEN_M | + LRFDTRC_CFG_PRESCAL_DIV1; + +#ifdef DeviceFamily_CC23X0R2 + /* Set tracer on GPO6 */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL0) | (LRFDDBELL_GPOSEL0_SRC2_RFCTRC); + HWREG(IOC_BASE + IOC_O_IOC6) = IOC_IOC6_PORTCFG_PFUNC4; // LRFD2 [trace] +#elif defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R22) || defined(DeviceFamily_CC2340R53) + /* Set tracer on GPO5 */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL1) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL1) | (LRFDDBELL_GPOSEL1_SRC6_RFCTRC); + HWREG(IOC_BASE + IOC_O_IOC5) = IOC_IOC5_PORTCFG_PFUNC3; // LRFD6 [trace] +#elif defined (DeviceFamily_CC27XX) + /* Set tracer on GPO20 */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_GPOSEL0) | (LRFDDBELL_GPOSEL0_SRC3_RFCTRC); + HWREG(IOC_BASE + IOC_O_IOC20) = IOC_IOC20_PORTCFG_PFUNC5; // LRFD3 [trace] +#endif + } +} + +void RCL_Tracer_standby(void) +{ + if (tracerEnabled) + { +#ifdef DeviceFamily_CC23X0R2 + HWREG(IOC_BASE + IOC_O_IOC6) = 0; +#elif defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R22) || defined(DeviceFamily_CC2340R53) + HWREG(IOC_BASE + IOC_O_IOC5) = 0; +#elif defined (DeviceFamily_CC27XX) + HWREG(IOC_BASE + IOC_O_IOC20) = 0; +#endif + } + /* Do not disable tracer module here, as it can give a lockup if tracing was ongoing and another trace is started */ +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt index 95af65df..2b2db566 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt @@ -45,3 +45,31 @@ zephyr_library_sources( driverlib/setup.c driverlib/uart.c ) + +# RF patches +if(CONFIG_SIMPLELINK_F3_RADIO_DRIVER) + zephyr_library_sources( + rf_patches/lrf_mce_binary_ble5_cc23x0r5.c + rf_patches/lrf_mce_binary_ble_cs_cc23x0r5.c + rf_patches/lrf_mce_binary_common_cc23x0r5.c + rf_patches/lrf_mce_binary_genfsk_cc23x0r5.c + rf_patches/lrf_mce_binary_ieee_cc23x0r5.c + rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c + rf_patches/lrf_pbe_binary_ble_cs_cc23x0r5.c + rf_patches/lrf_pbe_binary_common_cc23x0r5.c + rf_patches/lrf_pbe_binary_generic_cc23x0r5.c + rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c + rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c + rf_patches/lrf_rfe_binary_ble5_nopll_cc23x0r5.c + rf_patches/lrf_rfe_binary_ble_cs_cc23x0r5.c + rf_patches/lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c + rf_patches/lrf_rfe_binary_coherent_pll_cc23x0r5.c + rf_patches/lrf_rfe_binary_coherent_pll_nopll_cc23x0r5.c + rf_patches/lrf_rfe_binary_common_cc23x0r5.c + rf_patches/lrf_rfe_binary_common_nopll_cc23x0r5.c + rf_patches/lrf_rfe_binary_genfsk_cc23x0r5.c + rf_patches/lrf_rfe_binary_genfsk_nopll_cc23x0r5.c + rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c + rf_patches/lrf_rfe_binary_ieee_nopll_cc23x0r5.c + ) +endif() \ No newline at end of file diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h index f5eef3b3..bfcae0a5 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfddbell.h @@ -1,6818 +1,6818 @@ -/****************************************************************************** -* Filename: hw_lrfddbell_h -****************************************************************************** -* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -******************************************************************************/ - -#ifndef __HW_LRFDDBELL_H__ -#define __HW_LRFDDBELL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// LRFDDBELL component -// -//***************************************************************************** -// Description -#define LRFDDBELL_O_DESC 0x00000000U - -// Clock control -#define LRFDDBELL_O_CLKCTL 0x00000004U - -// DMA Configuration -#define LRFDDBELL_O_DMACFG 0x00000008U - -// Systimer Output Event Control Register -#define LRFDDBELL_O_SYSTIMOEV 0x0000000CU - -// System DMA Trigger -#define LRFDDBELL_O_SYSTDMATRIG 0x00000010U - -// GPO control -#define LRFDDBELL_O_GPOSEL0 0x00000014U - -// GPO control -#define LRFDDBELL_O_GPOSEL1 0x00000018U - -// Interrupt mask -#define LRFDDBELL_O_IMASK0 0x00000044U - -// Raw interrupt status -#define LRFDDBELL_O_RIS0 0x00000048U - -// Masked interrupt status -#define LRFDDBELL_O_MIS0 0x0000004CU - -// Interrupt set -#define LRFDDBELL_O_ISET0 0x00000050U - -// Interrupt clear -#define LRFDDBELL_O_ICLR0 0x00000054U - -// Interrupt mask -#define LRFDDBELL_O_IMASK1 0x00000084U - -// Raw interrupt status -#define LRFDDBELL_O_RIS1 0x00000088U - -// Masked interrupt status -#define LRFDDBELL_O_MIS1 0x0000008CU - -// Interrupt set -#define LRFDDBELL_O_ISET1 0x00000090U - -// Interrupt clear -#define LRFDDBELL_O_ICLR1 0x00000094U - -// Interrupt mask -#define LRFDDBELL_O_IMASK2 0x000000C4U - -// Raw interrupt status -#define LRFDDBELL_O_RIS2 0x000000C8U - -// Masked interrupt status -#define LRFDDBELL_O_MIS2 0x000000CCU - -// Interrupt set -#define LRFDDBELL_O_ISET2 0x000000D0U - -// Interrupt clear -#define LRFDDBELL_O_ICLR2 0x000000D4U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_DESC -// -//***************************************************************************** -// Field: [31:16] MODULEID -// -// Module identifier used to uniquely identify this IP. -#define LRFDDBELL_DESC_MODULEID_W 16U -#define LRFDDBELL_DESC_MODULEID_M 0xFFFF0000U -#define LRFDDBELL_DESC_MODULEID_S 16U - -// Field: [15:12] STDIPOFF -// -// Standard IP MMR block offset. Standard IP MMRs are the set of from -// aggregated IRQ registers till DTB. -// ENUMs: -// STDIPMMR These MMRs begin at offset 64*STDIPOFF from IP -// base address -// NO_STDIPMMR STDIP MMRs do not exist -#define LRFDDBELL_DESC_STDIPOFF_W 4U -#define LRFDDBELL_DESC_STDIPOFF_M 0x0000F000U -#define LRFDDBELL_DESC_STDIPOFF_S 12U -#define LRFDDBELL_DESC_STDIPOFF_STDIPMMR 0x00001000U -#define LRFDDBELL_DESC_STDIPOFF_NO_STDIPMMR 0x00000000U - -// Field: [11:8] INSTNUM -// -// IP Instance Number. If multiple instances of IP exist in the device, this -// field can identify the instance number -#define LRFDDBELL_DESC_INSTNUM_W 4U -#define LRFDDBELL_DESC_INSTNUM_M 0x00000F00U -#define LRFDDBELL_DESC_INSTNUM_S 8U - -// Field: [7:4] MAJREV -// -// Major rev of the IP -#define LRFDDBELL_DESC_MAJREV_W 4U -#define LRFDDBELL_DESC_MAJREV_M 0x000000F0U -#define LRFDDBELL_DESC_MAJREV_S 4U - -// Field: [3:0] MINREV -// -// Minor rev of the IP -#define LRFDDBELL_DESC_MINREV_W 4U -#define LRFDDBELL_DESC_MINREV_M 0x0000000FU -#define LRFDDBELL_DESC_MINREV_S 0U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_CLKCTL -// -//***************************************************************************** -// Field: [13] DEM -// -// Enable the clock to the demodulator. The modem will request this clock -// automatically. This bit is to force the clock to be free running -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_DEM 0x00002000U -#define LRFDDBELL_CLKCTL_DEM_M 0x00002000U -#define LRFDDBELL_CLKCTL_DEM_S 13U -#define LRFDDBELL_CLKCTL_DEM_EN 0x00002000U -#define LRFDDBELL_CLKCTL_DEM_DIS 0x00000000U - -// Field: [12] MOD -// -// Enable the clock to the modulator. Modem will request this clock -// automatically, this bit is to force the modulator clock to be free running. -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_MOD 0x00001000U -#define LRFDDBELL_CLKCTL_MOD_M 0x00001000U -#define LRFDDBELL_CLKCTL_MOD_S 12U -#define LRFDDBELL_CLKCTL_MOD_EN 0x00001000U -#define LRFDDBELL_CLKCTL_MOD_DIS 0x00000000U - -// Field: [11] S2RRAM -// -// Enable the clock to the S2R RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_S2RRAM 0x00000800U -#define LRFDDBELL_CLKCTL_S2RRAM_M 0x00000800U -#define LRFDDBELL_CLKCTL_S2RRAM_S 11U -#define LRFDDBELL_CLKCTL_S2RRAM_EN 0x00000800U -#define LRFDDBELL_CLKCTL_S2RRAM_DIS 0x00000000U - -// Field: [10] BUFRAM -// -// Enable the clock to the BUFRAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_BUFRAM 0x00000400U -#define LRFDDBELL_CLKCTL_BUFRAM_M 0x00000400U -#define LRFDDBELL_CLKCTL_BUFRAM_S 10U -#define LRFDDBELL_CLKCTL_BUFRAM_EN 0x00000400U -#define LRFDDBELL_CLKCTL_BUFRAM_DIS 0x00000000U - -// Field: [9] DSBRAM -// -// Enable the clock to the DSB RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_DSBRAM 0x00000200U -#define LRFDDBELL_CLKCTL_DSBRAM_M 0x00000200U -#define LRFDDBELL_CLKCTL_DSBRAM_S 9U -#define LRFDDBELL_CLKCTL_DSBRAM_EN 0x00000200U -#define LRFDDBELL_CLKCTL_DSBRAM_DIS 0x00000000U - -// Field: [8] RFERAM -// -// Enable the clock to the RFE RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_RFERAM 0x00000100U -#define LRFDDBELL_CLKCTL_RFERAM_M 0x00000100U -#define LRFDDBELL_CLKCTL_RFERAM_S 8U -#define LRFDDBELL_CLKCTL_RFERAM_EN 0x00000100U -#define LRFDDBELL_CLKCTL_RFERAM_DIS 0x00000000U - -// Field: [7] MCERAM -// -// Enable the clock to the MCE RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_MCERAM 0x00000080U -#define LRFDDBELL_CLKCTL_MCERAM_M 0x00000080U -#define LRFDDBELL_CLKCTL_MCERAM_S 7U -#define LRFDDBELL_CLKCTL_MCERAM_EN 0x00000080U -#define LRFDDBELL_CLKCTL_MCERAM_DIS 0x00000000U - -// Field: [6] PBERAM -// -// Enable the clock to the PBE RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_PBERAM 0x00000040U -#define LRFDDBELL_CLKCTL_PBERAM_M 0x00000040U -#define LRFDDBELL_CLKCTL_PBERAM_S 6U -#define LRFDDBELL_CLKCTL_PBERAM_EN 0x00000040U -#define LRFDDBELL_CLKCTL_PBERAM_DIS 0x00000000U - -// Field: [5] TRC -// -// Enable the clock to the Tracer -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_TRC 0x00000020U -#define LRFDDBELL_CLKCTL_TRC_M 0x00000020U -#define LRFDDBELL_CLKCTL_TRC_S 5U -#define LRFDDBELL_CLKCTL_TRC_EN 0x00000020U -#define LRFDDBELL_CLKCTL_TRC_DIS 0x00000000U - -// Field: [4] S2R -// -// Enable the clock to Samples2RAM -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_S2R 0x00000010U -#define LRFDDBELL_CLKCTL_S2R_M 0x00000010U -#define LRFDDBELL_CLKCTL_S2R_S 4U -#define LRFDDBELL_CLKCTL_S2R_EN 0x00000010U -#define LRFDDBELL_CLKCTL_S2R_DIS 0x00000000U - -// Field: [3] RFE -// -// Enable the clock to the RFE -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_RFE 0x00000008U -#define LRFDDBELL_CLKCTL_RFE_M 0x00000008U -#define LRFDDBELL_CLKCTL_RFE_S 3U -#define LRFDDBELL_CLKCTL_RFE_EN 0x00000008U -#define LRFDDBELL_CLKCTL_RFE_DIS 0x00000000U - -// Field: [2] MDM -// -// Enable the clock to the Modem -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_MDM 0x00000004U -#define LRFDDBELL_CLKCTL_MDM_M 0x00000004U -#define LRFDDBELL_CLKCTL_MDM_S 2U -#define LRFDDBELL_CLKCTL_MDM_EN 0x00000004U -#define LRFDDBELL_CLKCTL_MDM_DIS 0x00000000U - -// Field: [1] PBE -// -// Enable the clock to the PBE -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_PBE 0x00000002U -#define LRFDDBELL_CLKCTL_PBE_M 0x00000002U -#define LRFDDBELL_CLKCTL_PBE_S 1U -#define LRFDDBELL_CLKCTL_PBE_EN 0x00000002U -#define LRFDDBELL_CLKCTL_PBE_DIS 0x00000000U - -// Field: [0] BRIDGE -// -// Clock enable to AHB bridge. The bridge will request it's own clock, this bit -// it to override that feature to have a free running clock. -// ENUMs: -// EN Clock is requested -// DIS Clock not requested -#define LRFDDBELL_CLKCTL_BRIDGE 0x00000001U -#define LRFDDBELL_CLKCTL_BRIDGE_M 0x00000001U -#define LRFDDBELL_CLKCTL_BRIDGE_S 0U -#define LRFDDBELL_CLKCTL_BRIDGE_EN 0x00000001U -#define LRFDDBELL_CLKCTL_BRIDGE_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_DMACFG -// -//***************************************************************************** -// Field: [2:1] TRIGSRC -// -// Select DMA trigger source -// ENUMs: -// FIFO The DMA is triggered from the FIFO. See the FIFO -// configration register for what FIFO event will -// generate the trigger -// RFEFW The DMA is triggered by the MCE FW trigger -// MCEFW The DMA is triggered by the MCE FW trigger -// PBEFW The DMA is triggered by the PBE FW trigger -#define LRFDDBELL_DMACFG_TRIGSRC_W 2U -#define LRFDDBELL_DMACFG_TRIGSRC_M 0x00000006U -#define LRFDDBELL_DMACFG_TRIGSRC_S 1U -#define LRFDDBELL_DMACFG_TRIGSRC_FIFO 0x00000006U -#define LRFDDBELL_DMACFG_TRIGSRC_RFEFW 0x00000004U -#define LRFDDBELL_DMACFG_TRIGSRC_MCEFW 0x00000002U -#define LRFDDBELL_DMACFG_TRIGSRC_PBEFW 0x00000000U - -// Field: [0] EN -// -// Enables the DMA interface -// ENUMs: -// ON Enable DMA interface. The triggers are able to -// give activity on the interface -// OFF Disable DMA interface, no activity on interface -#define LRFDDBELL_DMACFG_EN 0x00000001U -#define LRFDDBELL_DMACFG_EN_M 0x00000001U -#define LRFDDBELL_DMACFG_EN_S 0U -#define LRFDDBELL_DMACFG_EN_ON 0x00000001U -#define LRFDDBELL_DMACFG_EN_OFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_SYSTIMOEV -// -//***************************************************************************** -// Field: [11:8] SRC2 -// -// Select source of systimer output event 2 (capture source) -// ENUMs: -// PBESYSTIM2 PBE FW systimer capture event 2 -// PBESYSTIM1 PBE FW systimer capture event 1 -// PBESYSTIM0 PBE FW systimer capture event 0 -// MDMHW2 MDM HW event 2 -// MDMHW1 MDM HW event 1 -// MDMHW0 MDM HW event 0 -// MCESYSTIM2 MCE FW systimer capture event 2 -// MCESYSTIM1 MCE FW systimer capture event 1 -// MCESYSTIM0 MCE FW systimer capture event 0 -// RFESYSTIM2 RFE FW systimer capture event 2 -// RFESYSTIM1 RFE FW systimer capture event 1 -// RFESYSTIM0 RFE FW systimer capture event 0 -// DIS Output not enabled, always 0. -#define LRFDDBELL_SYSTIMOEV_SRC2_W 4U -#define LRFDDBELL_SYSTIMOEV_SRC2_M 0x00000F00U -#define LRFDDBELL_SYSTIMOEV_SRC2_S 8U -#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM2 0x00000C00U -#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM1 0x00000B00U -#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM0 0x00000A00U -#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW2 0x00000900U -#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW1 0x00000800U -#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW0 0x00000700U -#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM2 0x00000600U -#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM1 0x00000500U -#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM0 0x00000400U -#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM2 0x00000300U -#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM1 0x00000200U -#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM0 0x00000100U -#define LRFDDBELL_SYSTIMOEV_SRC2_DIS 0x00000000U - -// Field: [7:4] SRC1 -// -// Select source of systimer output event 1 (capture source) -// ENUMs: -// PBESYSTIM2 PBE FW systimer capture event 2 -// PBESYSTIM1 PBE FW systimer capture event 1 -// PBESYSTIM0 PBE FW systimer capture event 0 -// MDMHW2 MDM HW event 2 -// MDMHW1 MDM HW event 1 -// MDMHW0 MDM HW event 0 -// MCESYSTIM2 MCE FW systimer capture event 2 -// MCESYSTIM1 MCE FW systimer capture event 1 -// MCESYSTIM0 MCE FW systimer capture event 0 -// RFESYSTIM2 RFE FW systimer capture event 2 -// RFESYSTIM1 RFE FW systimer capture event 1 -// RFESYSTIM0 RFE FW systimer capture event 0 -// DIS Output not enabled, always 0. -#define LRFDDBELL_SYSTIMOEV_SRC1_W 4U -#define LRFDDBELL_SYSTIMOEV_SRC1_M 0x000000F0U -#define LRFDDBELL_SYSTIMOEV_SRC1_S 4U -#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM2 0x000000C0U -#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM1 0x000000B0U -#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM0 0x000000A0U -#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW2 0x00000090U -#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW1 0x00000080U -#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW0 0x00000070U -#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM2 0x00000060U -#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM1 0x00000050U -#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM0 0x00000040U -#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM2 0x00000030U -#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM1 0x00000020U -#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM0 0x00000010U -#define LRFDDBELL_SYSTIMOEV_SRC1_DIS 0x00000000U - -// Field: [3:0] SRC0 -// -// Select source of systimer output event 0 (capture source) -// ENUMs: -// PBESYSTIM2 PBE FW systimer capture event 2 -// PBESYSTIM1 PBE FW systimer capture event 1 -// PBESYSTIM0 PBE FW systimer capture event 0 -// MDMHW2 MDM HW event 2 -// MDMHW1 MDM HW event 1 -// MDMHW0 MDM HW event 0 -// MCESYSTIM2 MCE FW systimer capture event 2 -// MCESYSTIM1 MCE FW systimer capture event 1 -// MCESYSTIM0 MCE FW systimer capture event 0 -// RFESYSTIM2 RFE FW systimer capture event 2 -// RFESYSTIM1 RFE FW systimer capture event 1 -// RFESYSTIM0 RFE FW systimer capture event 0 -// DIS Output not enabled, always 0. -#define LRFDDBELL_SYSTIMOEV_SRC0_W 4U -#define LRFDDBELL_SYSTIMOEV_SRC0_M 0x0000000FU -#define LRFDDBELL_SYSTIMOEV_SRC0_S 0U -#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM2 0x0000000CU -#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM1 0x0000000BU -#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM0 0x0000000AU -#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW2 0x00000009U -#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW1 0x00000008U -#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW0 0x00000007U -#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM2 0x00000006U -#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM1 0x00000005U -#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM0 0x00000004U -#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM2 0x00000003U -#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM1 0x00000002U -#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM0 0x00000001U -#define LRFDDBELL_SYSTIMOEV_SRC0_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_SYSTDMATRIG -// -//***************************************************************************** -// Field: [3] DMA -// -// Trigger a DMA request from the Radio -// ENUMs: -// TRIG DMA request manually triggered -// NOTRIG DMA not manually triggered -#define LRFDDBELL_SYSTDMATRIG_DMA 0x00000008U -#define LRFDDBELL_SYSTDMATRIG_DMA_M 0x00000008U -#define LRFDDBELL_SYSTDMATRIG_DMA_S 3U -#define LRFDDBELL_SYSTDMATRIG_DMA_TRIG 0x00000008U -#define LRFDDBELL_SYSTDMATRIG_DMA_NOTRIG 0x00000000U - -// Field: [2] SYST2 -// -// Trigger a capture event on systimer event 0 from the radio -// ENUMs: -// TRIG Capture event triggered -// NOTRIG Not capture event triggered -#define LRFDDBELL_SYSTDMATRIG_SYST2 0x00000004U -#define LRFDDBELL_SYSTDMATRIG_SYST2_M 0x00000004U -#define LRFDDBELL_SYSTDMATRIG_SYST2_S 2U -#define LRFDDBELL_SYSTDMATRIG_SYST2_TRIG 0x00000004U -#define LRFDDBELL_SYSTDMATRIG_SYST2_NOTRIG 0x00000000U - -// Field: [1] SYST1 -// -// Trigger a capture event on systimer event 0 from the radio -// ENUMs: -// TRIG Capture event triggered -// NOTRIG Not capture event triggered -#define LRFDDBELL_SYSTDMATRIG_SYST1 0x00000002U -#define LRFDDBELL_SYSTDMATRIG_SYST1_M 0x00000002U -#define LRFDDBELL_SYSTDMATRIG_SYST1_S 1U -#define LRFDDBELL_SYSTDMATRIG_SYST1_TRIG 0x00000002U -#define LRFDDBELL_SYSTDMATRIG_SYST1_NOTRIG 0x00000000U - -// Field: [0] SYST0 -// -// Trigger a capture event on systimer event 0 from the radio -// ENUMs: -// TRIG Capture event triggered -// NOTRIG Not capture event triggered -#define LRFDDBELL_SYSTDMATRIG_SYST0 0x00000001U -#define LRFDDBELL_SYSTDMATRIG_SYST0_M 0x00000001U -#define LRFDDBELL_SYSTDMATRIG_SYST0_S 0U -#define LRFDDBELL_SYSTDMATRIG_SYST0_TRIG 0x00000001U -#define LRFDDBELL_SYSTDMATRIG_SYST0_NOTRIG 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_GPOSEL0 -// -//***************************************************************************** -// Field: [28:24] SRC3 -// -// Select source of radio GPO line 3 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 3 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS Output not enabled -#define LRFDDBELL_GPOSEL0_SRC3_W 5U -#define LRFDDBELL_GPOSEL0_SRC3_M 0x1F000000U -#define LRFDDBELL_GPOSEL0_SRC3_S 24U -#define LRFDDBELL_GPOSEL0_SRC3_RFCTRC 0x19000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO7 0x18000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO6 0x17000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO5 0x16000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO4 0x15000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO3 0x14000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO2 0x13000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO1 0x12000000U -#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO0 0x11000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO7 0x10000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO6 0x0F000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO5 0x0E000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO4 0x0D000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO3 0x0C000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO2 0x0B000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO1 0x0A000000U -#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO0 0x09000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO7 0x08000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO6 0x07000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO5 0x06000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO4 0x05000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO3 0x04000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO2 0x03000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO1 0x02000000U -#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO0 0x01000000U -#define LRFDDBELL_GPOSEL0_SRC3_DIS 0x00000000U - -// Field: [20:16] SRC2 -// -// Select source of radio GPO line 2 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 2 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS Output not enabled -#define LRFDDBELL_GPOSEL0_SRC2_W 5U -#define LRFDDBELL_GPOSEL0_SRC2_M 0x001F0000U -#define LRFDDBELL_GPOSEL0_SRC2_S 16U -#define LRFDDBELL_GPOSEL0_SRC2_RFCTRC 0x00190000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO7 0x00180000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO6 0x00170000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO5 0x00160000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO4 0x00150000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO3 0x00140000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO2 0x00130000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO1 0x00120000U -#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO0 0x00110000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO7 0x00100000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO6 0x000F0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO5 0x000E0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO4 0x000D0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO3 0x000C0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO2 0x000B0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO1 0x000A0000U -#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO0 0x00090000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO7 0x00080000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO6 0x00070000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO5 0x00060000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO4 0x00050000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO3 0x00040000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO2 0x00030000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO1 0x00020000U -#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO0 0x00010000U -#define LRFDDBELL_GPOSEL0_SRC2_DIS 0x00000000U - -// Field: [12:8] SRC1 -// -// Select source of radio GPO line 1 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 1 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS Output not enabled -#define LRFDDBELL_GPOSEL0_SRC1_W 5U -#define LRFDDBELL_GPOSEL0_SRC1_M 0x00001F00U -#define LRFDDBELL_GPOSEL0_SRC1_S 8U -#define LRFDDBELL_GPOSEL0_SRC1_RFCTRC 0x00001900U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO7 0x00001800U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO6 0x00001700U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO5 0x00001600U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO4 0x00001500U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO3 0x00001400U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO2 0x00001300U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO1 0x00001200U -#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO0 0x00001100U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO7 0x00001000U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO6 0x00000F00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO5 0x00000E00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO4 0x00000D00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO3 0x00000C00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO2 0x00000B00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO1 0x00000A00U -#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO0 0x00000900U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO7 0x00000800U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO6 0x00000700U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO5 0x00000600U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO4 0x00000500U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO3 0x00000400U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO2 0x00000300U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO1 0x00000200U -#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO0 0x00000100U -#define LRFDDBELL_GPOSEL0_SRC1_DIS 0x00000000U - -// Field: [4:0] SRC0 -// -// Select source of radio GPO line 0 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 0 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS Output not enabled -#define LRFDDBELL_GPOSEL0_SRC0_W 5U -#define LRFDDBELL_GPOSEL0_SRC0_M 0x0000001FU -#define LRFDDBELL_GPOSEL0_SRC0_S 0U -#define LRFDDBELL_GPOSEL0_SRC0_RFCTRC 0x00000019U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO7 0x00000018U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO6 0x00000017U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO5 0x00000016U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO4 0x00000015U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO3 0x00000014U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO2 0x00000013U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO1 0x00000012U -#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO0 0x00000011U -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO7 0x00000010U -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO6 0x0000000FU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO5 0x0000000EU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO4 0x0000000DU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO3 0x0000000CU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO2 0x0000000BU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO1 0x0000000AU -#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO0 0x00000009U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO7 0x00000008U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO6 0x00000007U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO5 0x00000006U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO4 0x00000005U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO3 0x00000004U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO2 0x00000003U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO1 0x00000002U -#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO0 0x00000001U -#define LRFDDBELL_GPOSEL0_SRC0_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_GPOSEL1 -// -//***************************************************************************** -// Field: [28:24] SRC7 -// -// Select source of radio GPO line 7 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 7 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS No output not enabled -#define LRFDDBELL_GPOSEL1_SRC7_W 5U -#define LRFDDBELL_GPOSEL1_SRC7_M 0x1F000000U -#define LRFDDBELL_GPOSEL1_SRC7_S 24U -#define LRFDDBELL_GPOSEL1_SRC7_RFCTRC 0x19000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO7 0x18000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO6 0x17000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO5 0x16000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO4 0x15000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO3 0x14000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO2 0x13000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO1 0x12000000U -#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO0 0x11000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO7 0x10000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO6 0x0F000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO5 0x0E000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO4 0x0D000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO3 0x0C000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO2 0x0B000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO1 0x0A000000U -#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO0 0x09000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO7 0x08000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO6 0x07000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO5 0x06000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO4 0x05000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO3 0x04000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO2 0x03000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO1 0x02000000U -#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO0 0x01000000U -#define LRFDDBELL_GPOSEL1_SRC7_DIS 0x00000000U - -// Field: [20:16] SRC6 -// -// Select source of radio GPO line 6 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 6 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Selevt RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS No output not enabled -#define LRFDDBELL_GPOSEL1_SRC6_W 5U -#define LRFDDBELL_GPOSEL1_SRC6_M 0x001F0000U -#define LRFDDBELL_GPOSEL1_SRC6_S 16U -#define LRFDDBELL_GPOSEL1_SRC6_RFCTRC 0x00190000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO7 0x00180000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO6 0x00170000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO5 0x00160000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO4 0x00150000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO3 0x00140000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO2 0x00130000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO1 0x00120000U -#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO0 0x00110000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO7 0x00100000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO6 0x000F0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO5 0x000E0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO4 0x000D0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO3 0x000C0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO2 0x000B0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO1 0x000A0000U -#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO0 0x00090000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO7 0x00080000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO6 0x00070000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO5 0x00060000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO4 0x00050000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO3 0x00040000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO2 0x00030000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO1 0x00020000U -#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO0 0x00010000U -#define LRFDDBELL_GPOSEL1_SRC6_DIS 0x00000000U - -// Field: [12:8] SRC5 -// -// Select source of radio GPO line 5 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 5 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS No output not enabled -#define LRFDDBELL_GPOSEL1_SRC5_W 5U -#define LRFDDBELL_GPOSEL1_SRC5_M 0x00001F00U -#define LRFDDBELL_GPOSEL1_SRC5_S 8U -#define LRFDDBELL_GPOSEL1_SRC5_RFCTRC 0x00001900U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO7 0x00001800U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO6 0x00001700U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO5 0x00001600U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO4 0x00001500U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO3 0x00001400U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO2 0x00001300U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO1 0x00001200U -#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO0 0x00001100U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO7 0x00001000U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO6 0x00000F00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO5 0x00000E00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO4 0x00000D00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO3 0x00000C00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO2 0x00000B00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO1 0x00000A00U -#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO0 0x00000900U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO7 0x00000800U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO6 0x00000700U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO5 0x00000600U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO4 0x00000500U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO3 0x00000400U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO2 0x00000300U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO1 0x00000200U -#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO0 0x00000100U -#define LRFDDBELL_GPOSEL1_SRC5_DIS 0x00000000U - -// Field: [4:0] SRC4 -// -// Select source of radio GPO line 4 -// ENUMs: -// RFCTRC Select RFCTRC GPO line 4 -// RFEGPO7 Select RFE GPO line 7 -// RFEGPO6 Select RFE GPO line 6 -// RFEGPO5 Select RFE GPO line 5 -// RFEGPO4 Select RFE GPO line 4 -// RFEGPO3 Select RFE GPO line 3 -// RFEGPO2 Select RFE GPO line 2 -// RFEGPO1 Select RFE GPO line 1 -// RFEGPO0 Select RFE GPO line 0 -// MCEGPO7 Select MCE GPO line 7 -// MCEGPO6 Select MCE GPO line 6 -// MCEGPO5 Select MCE GPO line 5 -// MCEGPO4 Select MCE GPO line 4 -// MCEGPO3 Select MCE GPO line 3 -// MCEGPO2 Select MCE GPO line 2 -// MCEGPO1 Select MCE GPO line 1 -// MCEGPO0 Select MCE GPO line 0 -// PBEGPO7 Select PBE GPO line 7 -// PBEGPO6 Select PBE GPO line 6 -// PBEGPO5 Select PBE GPO line 5 -// PBEGPO4 Select PBE GPO line 4 -// PBEGPO3 Select PBE GPO line 3 -// PBEGPO2 Select PBE GPO line 2 -// PBEGPO1 Select PBE GPO line 1 -// PBEGPO0 Select PBE GPO line 0 -// DIS No output not enabled -#define LRFDDBELL_GPOSEL1_SRC4_W 5U -#define LRFDDBELL_GPOSEL1_SRC4_M 0x0000001FU -#define LRFDDBELL_GPOSEL1_SRC4_S 0U -#define LRFDDBELL_GPOSEL1_SRC4_RFCTRC 0x00000019U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO7 0x00000018U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO6 0x00000017U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO5 0x00000016U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO4 0x00000015U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO3 0x00000014U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO2 0x00000013U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO1 0x00000012U -#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO0 0x00000011U -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO7 0x00000010U -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO6 0x0000000FU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO5 0x0000000EU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO4 0x0000000DU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO3 0x0000000CU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO2 0x0000000BU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO1 0x0000000AU -#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO0 0x00000009U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO7 0x00000008U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO6 0x00000007U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO5 0x00000006U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO4 0x00000005U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO3 0x00000004U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO2 0x00000003U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO1 0x00000002U -#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO0 0x00000001U -#define LRFDDBELL_GPOSEL1_SRC4_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_IMASK0 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_SYSTIM2 0x80000000U -#define LRFDDBELL_IMASK0_SYSTIM2_M 0x80000000U -#define LRFDDBELL_IMASK0_SYSTIM2_S 31U -#define LRFDDBELL_IMASK0_SYSTIM2_EN 0x80000000U -#define LRFDDBELL_IMASK0_SYSTIM2_DIS 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_SYSTIM1 0x40000000U -#define LRFDDBELL_IMASK0_SYSTIM1_M 0x40000000U -#define LRFDDBELL_IMASK0_SYSTIM1_S 30U -#define LRFDDBELL_IMASK0_SYSTIM1_EN 0x40000000U -#define LRFDDBELL_IMASK0_SYSTIM1_DIS 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_SYSTIM0 0x20000000U -#define LRFDDBELL_IMASK0_SYSTIM0_M 0x20000000U -#define LRFDDBELL_IMASK0_SYSTIM0_S 29U -#define LRFDDBELL_IMASK0_SYSTIM0_EN 0x20000000U -#define LRFDDBELL_IMASK0_SYSTIM0_DIS 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMDONE 0x10000000U -#define LRFDDBELL_IMASK0_MDMDONE_M 0x10000000U -#define LRFDDBELL_IMASK0_MDMDONE_S 28U -#define LRFDDBELL_IMASK0_MDMDONE_EN 0x10000000U -#define LRFDDBELL_IMASK0_MDMDONE_DIS 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMIN 0x08000000U -#define LRFDDBELL_IMASK0_MDMIN_M 0x08000000U -#define LRFDDBELL_IMASK0_MDMIN_S 27U -#define LRFDDBELL_IMASK0_MDMIN_EN 0x08000000U -#define LRFDDBELL_IMASK0_MDMIN_DIS 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMOUT 0x04000000U -#define LRFDDBELL_IMASK0_MDMOUT_M 0x04000000U -#define LRFDDBELL_IMASK0_MDMOUT_S 26U -#define LRFDDBELL_IMASK0_MDMOUT_EN 0x04000000U -#define LRFDDBELL_IMASK0_MDMOUT_DIS 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMSOFT2 0x02000000U -#define LRFDDBELL_IMASK0_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_IMASK0_MDMSOFT2_S 25U -#define LRFDDBELL_IMASK0_MDMSOFT2_EN 0x02000000U -#define LRFDDBELL_IMASK0_MDMSOFT2_DIS 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMSOFT1 0x01000000U -#define LRFDDBELL_IMASK0_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_IMASK0_MDMSOFT1_S 24U -#define LRFDDBELL_IMASK0_MDMSOFT1_EN 0x01000000U -#define LRFDDBELL_IMASK0_MDMSOFT1_DIS 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_MDMSOFT0 0x00800000U -#define LRFDDBELL_IMASK0_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_IMASK0_MDMSOFT0_S 23U -#define LRFDDBELL_IMASK0_MDMSOFT0_EN 0x00800000U -#define LRFDDBELL_IMASK0_MDMSOFT0_DIS 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_RFEDONE 0x00400000U -#define LRFDDBELL_IMASK0_RFEDONE_M 0x00400000U -#define LRFDDBELL_IMASK0_RFEDONE_S 22U -#define LRFDDBELL_IMASK0_RFEDONE_EN 0x00400000U -#define LRFDDBELL_IMASK0_RFEDONE_DIS 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_RFESOFT1 0x00200000U -#define LRFDDBELL_IMASK0_RFESOFT1_M 0x00200000U -#define LRFDDBELL_IMASK0_RFESOFT1_S 21U -#define LRFDDBELL_IMASK0_RFESOFT1_EN 0x00200000U -#define LRFDDBELL_IMASK0_RFESOFT1_DIS 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_RFESOFT0 0x00100000U -#define LRFDDBELL_IMASK0_RFESOFT0_M 0x00100000U -#define LRFDDBELL_IMASK0_RFESOFT0_S 20U -#define LRFDDBELL_IMASK0_RFESOFT0_EN 0x00100000U -#define LRFDDBELL_IMASK0_RFESOFT0_DIS 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_LOCK 0x00080000U -#define LRFDDBELL_IMASK0_LOCK_M 0x00080000U -#define LRFDDBELL_IMASK0_LOCK_S 19U -#define LRFDDBELL_IMASK0_LOCK_EN 0x00080000U -#define LRFDDBELL_IMASK0_LOCK_DIS 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_LOL 0x00040000U -#define LRFDDBELL_IMASK0_LOL_M 0x00040000U -#define LRFDDBELL_IMASK0_LOL_S 18U -#define LRFDDBELL_IMASK0_LOL_EN 0x00040000U -#define LRFDDBELL_IMASK0_LOL_DIS 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_TXFIFO 0x00020000U -#define LRFDDBELL_IMASK0_TXFIFO_M 0x00020000U -#define LRFDDBELL_IMASK0_TXFIFO_S 17U -#define LRFDDBELL_IMASK0_TXFIFO_EN 0x00020000U -#define LRFDDBELL_IMASK0_TXFIFO_DIS 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_RXFIFO 0x00010000U -#define LRFDDBELL_IMASK0_RXFIFO_M 0x00010000U -#define LRFDDBELL_IMASK0_RXFIFO_S 16U -#define LRFDDBELL_IMASK0_RXFIFO_EN 0x00010000U -#define LRFDDBELL_IMASK0_RXFIFO_DIS 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE15 0x00008000U -#define LRFDDBELL_IMASK0_PBE15_M 0x00008000U -#define LRFDDBELL_IMASK0_PBE15_S 15U -#define LRFDDBELL_IMASK0_PBE15_EN 0x00008000U -#define LRFDDBELL_IMASK0_PBE15_DIS 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE14 0x00004000U -#define LRFDDBELL_IMASK0_PBE14_M 0x00004000U -#define LRFDDBELL_IMASK0_PBE14_S 14U -#define LRFDDBELL_IMASK0_PBE14_EN 0x00004000U -#define LRFDDBELL_IMASK0_PBE14_DIS 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE13 0x00002000U -#define LRFDDBELL_IMASK0_PBE13_M 0x00002000U -#define LRFDDBELL_IMASK0_PBE13_S 13U -#define LRFDDBELL_IMASK0_PBE13_EN 0x00002000U -#define LRFDDBELL_IMASK0_PBE13_DIS 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE12 0x00001000U -#define LRFDDBELL_IMASK0_PBE12_M 0x00001000U -#define LRFDDBELL_IMASK0_PBE12_S 12U -#define LRFDDBELL_IMASK0_PBE12_EN 0x00001000U -#define LRFDDBELL_IMASK0_PBE12_DIS 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE11 0x00000800U -#define LRFDDBELL_IMASK0_PBE11_M 0x00000800U -#define LRFDDBELL_IMASK0_PBE11_S 11U -#define LRFDDBELL_IMASK0_PBE11_EN 0x00000800U -#define LRFDDBELL_IMASK0_PBE11_DIS 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE10 0x00000400U -#define LRFDDBELL_IMASK0_PBE10_M 0x00000400U -#define LRFDDBELL_IMASK0_PBE10_S 10U -#define LRFDDBELL_IMASK0_PBE10_EN 0x00000400U -#define LRFDDBELL_IMASK0_PBE10_DIS 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE8 0x00000100U -#define LRFDDBELL_IMASK0_PBE8_M 0x00000100U -#define LRFDDBELL_IMASK0_PBE8_S 8U -#define LRFDDBELL_IMASK0_PBE8_EN 0x00000100U -#define LRFDDBELL_IMASK0_PBE8_DIS 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE7 0x00000080U -#define LRFDDBELL_IMASK0_PBE7_M 0x00000080U -#define LRFDDBELL_IMASK0_PBE7_S 7U -#define LRFDDBELL_IMASK0_PBE7_EN 0x00000080U -#define LRFDDBELL_IMASK0_PBE7_DIS 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE6 0x00000040U -#define LRFDDBELL_IMASK0_PBE6_M 0x00000040U -#define LRFDDBELL_IMASK0_PBE6_S 6U -#define LRFDDBELL_IMASK0_PBE6_EN 0x00000040U -#define LRFDDBELL_IMASK0_PBE6_DIS 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE5 0x00000020U -#define LRFDDBELL_IMASK0_PBE5_M 0x00000020U -#define LRFDDBELL_IMASK0_PBE5_S 5U -#define LRFDDBELL_IMASK0_PBE5_EN 0x00000020U -#define LRFDDBELL_IMASK0_PBE5_DIS 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE4 0x00000010U -#define LRFDDBELL_IMASK0_PBE4_M 0x00000010U -#define LRFDDBELL_IMASK0_PBE4_S 4U -#define LRFDDBELL_IMASK0_PBE4_EN 0x00000010U -#define LRFDDBELL_IMASK0_PBE4_DIS 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE3 0x00000008U -#define LRFDDBELL_IMASK0_PBE3_M 0x00000008U -#define LRFDDBELL_IMASK0_PBE3_S 3U -#define LRFDDBELL_IMASK0_PBE3_EN 0x00000008U -#define LRFDDBELL_IMASK0_PBE3_DIS 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE2 0x00000004U -#define LRFDDBELL_IMASK0_PBE2_M 0x00000004U -#define LRFDDBELL_IMASK0_PBE2_S 2U -#define LRFDDBELL_IMASK0_PBE2_EN 0x00000004U -#define LRFDDBELL_IMASK0_PBE2_DIS 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE1 0x00000002U -#define LRFDDBELL_IMASK0_PBE1_M 0x00000002U -#define LRFDDBELL_IMASK0_PBE1_S 1U -#define LRFDDBELL_IMASK0_PBE1_EN 0x00000002U -#define LRFDDBELL_IMASK0_PBE1_DIS 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK0_PBE0 0x00000001U -#define LRFDDBELL_IMASK0_PBE0_M 0x00000001U -#define LRFDDBELL_IMASK0_PBE0_S 0U -#define LRFDDBELL_IMASK0_PBE0_EN 0x00000001U -#define LRFDDBELL_IMASK0_PBE0_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_RIS0 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_SYSTIM2 0x80000000U -#define LRFDDBELL_RIS0_SYSTIM2_M 0x80000000U -#define LRFDDBELL_RIS0_SYSTIM2_S 31U -#define LRFDDBELL_RIS0_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_RIS0_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_SYSTIM1 0x40000000U -#define LRFDDBELL_RIS0_SYSTIM1_M 0x40000000U -#define LRFDDBELL_RIS0_SYSTIM1_S 30U -#define LRFDDBELL_RIS0_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_RIS0_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_SYSTIM0 0x20000000U -#define LRFDDBELL_RIS0_SYSTIM0_M 0x20000000U -#define LRFDDBELL_RIS0_SYSTIM0_S 29U -#define LRFDDBELL_RIS0_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_RIS0_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMDONE 0x10000000U -#define LRFDDBELL_RIS0_MDMDONE_M 0x10000000U -#define LRFDDBELL_RIS0_MDMDONE_S 28U -#define LRFDDBELL_RIS0_MDMDONE_SET 0x10000000U -#define LRFDDBELL_RIS0_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMIN 0x08000000U -#define LRFDDBELL_RIS0_MDMIN_M 0x08000000U -#define LRFDDBELL_RIS0_MDMIN_S 27U -#define LRFDDBELL_RIS0_MDMIN_SET 0x08000000U -#define LRFDDBELL_RIS0_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMOUT 0x04000000U -#define LRFDDBELL_RIS0_MDMOUT_M 0x04000000U -#define LRFDDBELL_RIS0_MDMOUT_S 26U -#define LRFDDBELL_RIS0_MDMOUT_SET 0x04000000U -#define LRFDDBELL_RIS0_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMSOFT2 0x02000000U -#define LRFDDBELL_RIS0_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_RIS0_MDMSOFT2_S 25U -#define LRFDDBELL_RIS0_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_RIS0_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMSOFT1 0x01000000U -#define LRFDDBELL_RIS0_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_RIS0_MDMSOFT1_S 24U -#define LRFDDBELL_RIS0_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_RIS0_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_MDMSOFT0 0x00800000U -#define LRFDDBELL_RIS0_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_RIS0_MDMSOFT0_S 23U -#define LRFDDBELL_RIS0_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_RIS0_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_RFEDONE 0x00400000U -#define LRFDDBELL_RIS0_RFEDONE_M 0x00400000U -#define LRFDDBELL_RIS0_RFEDONE_S 22U -#define LRFDDBELL_RIS0_RFEDONE_SET 0x00400000U -#define LRFDDBELL_RIS0_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_RFESOFT1 0x00200000U -#define LRFDDBELL_RIS0_RFESOFT1_M 0x00200000U -#define LRFDDBELL_RIS0_RFESOFT1_S 21U -#define LRFDDBELL_RIS0_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_RIS0_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_RFESOFT0 0x00100000U -#define LRFDDBELL_RIS0_RFESOFT0_M 0x00100000U -#define LRFDDBELL_RIS0_RFESOFT0_S 20U -#define LRFDDBELL_RIS0_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_RIS0_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_LOCK 0x00080000U -#define LRFDDBELL_RIS0_LOCK_M 0x00080000U -#define LRFDDBELL_RIS0_LOCK_S 19U -#define LRFDDBELL_RIS0_LOCK_SET 0x00080000U -#define LRFDDBELL_RIS0_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_LOL 0x00040000U -#define LRFDDBELL_RIS0_LOL_M 0x00040000U -#define LRFDDBELL_RIS0_LOL_S 18U -#define LRFDDBELL_RIS0_LOL_SET 0x00040000U -#define LRFDDBELL_RIS0_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_TXFIFO 0x00020000U -#define LRFDDBELL_RIS0_TXFIFO_M 0x00020000U -#define LRFDDBELL_RIS0_TXFIFO_S 17U -#define LRFDDBELL_RIS0_TXFIFO_SET 0x00020000U -#define LRFDDBELL_RIS0_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_RXFIFO 0x00010000U -#define LRFDDBELL_RIS0_RXFIFO_M 0x00010000U -#define LRFDDBELL_RIS0_RXFIFO_S 16U -#define LRFDDBELL_RIS0_RXFIFO_SET 0x00010000U -#define LRFDDBELL_RIS0_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE15 0x00008000U -#define LRFDDBELL_RIS0_PBE15_M 0x00008000U -#define LRFDDBELL_RIS0_PBE15_S 15U -#define LRFDDBELL_RIS0_PBE15_SET 0x00008000U -#define LRFDDBELL_RIS0_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE14 0x00004000U -#define LRFDDBELL_RIS0_PBE14_M 0x00004000U -#define LRFDDBELL_RIS0_PBE14_S 14U -#define LRFDDBELL_RIS0_PBE14_SET 0x00004000U -#define LRFDDBELL_RIS0_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE13 0x00002000U -#define LRFDDBELL_RIS0_PBE13_M 0x00002000U -#define LRFDDBELL_RIS0_PBE13_S 13U -#define LRFDDBELL_RIS0_PBE13_SET 0x00002000U -#define LRFDDBELL_RIS0_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE12 0x00001000U -#define LRFDDBELL_RIS0_PBE12_M 0x00001000U -#define LRFDDBELL_RIS0_PBE12_S 12U -#define LRFDDBELL_RIS0_PBE12_SET 0x00001000U -#define LRFDDBELL_RIS0_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE11 0x00000800U -#define LRFDDBELL_RIS0_PBE11_M 0x00000800U -#define LRFDDBELL_RIS0_PBE11_S 11U -#define LRFDDBELL_RIS0_PBE11_SET 0x00000800U -#define LRFDDBELL_RIS0_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE10 0x00000400U -#define LRFDDBELL_RIS0_PBE10_M 0x00000400U -#define LRFDDBELL_RIS0_PBE10_S 10U -#define LRFDDBELL_RIS0_PBE10_SET 0x00000400U -#define LRFDDBELL_RIS0_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE9 0x00000200U -#define LRFDDBELL_RIS0_PBE9_M 0x00000200U -#define LRFDDBELL_RIS0_PBE9_S 9U -#define LRFDDBELL_RIS0_PBE9_SET 0x00000200U -#define LRFDDBELL_RIS0_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE8 0x00000100U -#define LRFDDBELL_RIS0_PBE8_M 0x00000100U -#define LRFDDBELL_RIS0_PBE8_S 8U -#define LRFDDBELL_RIS0_PBE8_SET 0x00000100U -#define LRFDDBELL_RIS0_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE7 0x00000080U -#define LRFDDBELL_RIS0_PBE7_M 0x00000080U -#define LRFDDBELL_RIS0_PBE7_S 7U -#define LRFDDBELL_RIS0_PBE7_SET 0x00000080U -#define LRFDDBELL_RIS0_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE6 0x00000040U -#define LRFDDBELL_RIS0_PBE6_M 0x00000040U -#define LRFDDBELL_RIS0_PBE6_S 6U -#define LRFDDBELL_RIS0_PBE6_SET 0x00000040U -#define LRFDDBELL_RIS0_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE5 0x00000020U -#define LRFDDBELL_RIS0_PBE5_M 0x00000020U -#define LRFDDBELL_RIS0_PBE5_S 5U -#define LRFDDBELL_RIS0_PBE5_SET 0x00000020U -#define LRFDDBELL_RIS0_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE4 0x00000010U -#define LRFDDBELL_RIS0_PBE4_M 0x00000010U -#define LRFDDBELL_RIS0_PBE4_S 4U -#define LRFDDBELL_RIS0_PBE4_SET 0x00000010U -#define LRFDDBELL_RIS0_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE3 0x00000008U -#define LRFDDBELL_RIS0_PBE3_M 0x00000008U -#define LRFDDBELL_RIS0_PBE3_S 3U -#define LRFDDBELL_RIS0_PBE3_SET 0x00000008U -#define LRFDDBELL_RIS0_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE2 0x00000004U -#define LRFDDBELL_RIS0_PBE2_M 0x00000004U -#define LRFDDBELL_RIS0_PBE2_S 2U -#define LRFDDBELL_RIS0_PBE2_SET 0x00000004U -#define LRFDDBELL_RIS0_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE1 0x00000002U -#define LRFDDBELL_RIS0_PBE1_M 0x00000002U -#define LRFDDBELL_RIS0_PBE1_S 1U -#define LRFDDBELL_RIS0_PBE1_SET 0x00000002U -#define LRFDDBELL_RIS0_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS0_PBE0 0x00000001U -#define LRFDDBELL_RIS0_PBE0_M 0x00000001U -#define LRFDDBELL_RIS0_PBE0_S 0U -#define LRFDDBELL_RIS0_PBE0_SET 0x00000001U -#define LRFDDBELL_RIS0_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_MIS0 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_SYSTIM2 0x80000000U -#define LRFDDBELL_MIS0_SYSTIM2_M 0x80000000U -#define LRFDDBELL_MIS0_SYSTIM2_S 31U -#define LRFDDBELL_MIS0_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_MIS0_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_SYSTIM1 0x40000000U -#define LRFDDBELL_MIS0_SYSTIM1_M 0x40000000U -#define LRFDDBELL_MIS0_SYSTIM1_S 30U -#define LRFDDBELL_MIS0_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_MIS0_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_SYSTIM0 0x20000000U -#define LRFDDBELL_MIS0_SYSTIM0_M 0x20000000U -#define LRFDDBELL_MIS0_SYSTIM0_S 29U -#define LRFDDBELL_MIS0_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_MIS0_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMDONE 0x10000000U -#define LRFDDBELL_MIS0_MDMDONE_M 0x10000000U -#define LRFDDBELL_MIS0_MDMDONE_S 28U -#define LRFDDBELL_MIS0_MDMDONE_SET 0x10000000U -#define LRFDDBELL_MIS0_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMIN 0x08000000U -#define LRFDDBELL_MIS0_MDMIN_M 0x08000000U -#define LRFDDBELL_MIS0_MDMIN_S 27U -#define LRFDDBELL_MIS0_MDMIN_SET 0x08000000U -#define LRFDDBELL_MIS0_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMOUT 0x04000000U -#define LRFDDBELL_MIS0_MDMOUT_M 0x04000000U -#define LRFDDBELL_MIS0_MDMOUT_S 26U -#define LRFDDBELL_MIS0_MDMOUT_SET 0x04000000U -#define LRFDDBELL_MIS0_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMSOFT2 0x02000000U -#define LRFDDBELL_MIS0_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_MIS0_MDMSOFT2_S 25U -#define LRFDDBELL_MIS0_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_MIS0_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMSOFT1 0x01000000U -#define LRFDDBELL_MIS0_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_MIS0_MDMSOFT1_S 24U -#define LRFDDBELL_MIS0_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_MIS0_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_MDMSOFT0 0x00800000U -#define LRFDDBELL_MIS0_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_MIS0_MDMSOFT0_S 23U -#define LRFDDBELL_MIS0_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_MIS0_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_RFEDONE 0x00400000U -#define LRFDDBELL_MIS0_RFEDONE_M 0x00400000U -#define LRFDDBELL_MIS0_RFEDONE_S 22U -#define LRFDDBELL_MIS0_RFEDONE_SET 0x00400000U -#define LRFDDBELL_MIS0_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_RFESOFT1 0x00200000U -#define LRFDDBELL_MIS0_RFESOFT1_M 0x00200000U -#define LRFDDBELL_MIS0_RFESOFT1_S 21U -#define LRFDDBELL_MIS0_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_MIS0_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_RFESOFT0 0x00100000U -#define LRFDDBELL_MIS0_RFESOFT0_M 0x00100000U -#define LRFDDBELL_MIS0_RFESOFT0_S 20U -#define LRFDDBELL_MIS0_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_MIS0_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_LOCK 0x00080000U -#define LRFDDBELL_MIS0_LOCK_M 0x00080000U -#define LRFDDBELL_MIS0_LOCK_S 19U -#define LRFDDBELL_MIS0_LOCK_SET 0x00080000U -#define LRFDDBELL_MIS0_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_LOL 0x00040000U -#define LRFDDBELL_MIS0_LOL_M 0x00040000U -#define LRFDDBELL_MIS0_LOL_S 18U -#define LRFDDBELL_MIS0_LOL_SET 0x00040000U -#define LRFDDBELL_MIS0_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_TXFIFO 0x00020000U -#define LRFDDBELL_MIS0_TXFIFO_M 0x00020000U -#define LRFDDBELL_MIS0_TXFIFO_S 17U -#define LRFDDBELL_MIS0_TXFIFO_SET 0x00020000U -#define LRFDDBELL_MIS0_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_RXFIFO 0x00010000U -#define LRFDDBELL_MIS0_RXFIFO_M 0x00010000U -#define LRFDDBELL_MIS0_RXFIFO_S 16U -#define LRFDDBELL_MIS0_RXFIFO_SET 0x00010000U -#define LRFDDBELL_MIS0_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE15 0x00008000U -#define LRFDDBELL_MIS0_PBE15_M 0x00008000U -#define LRFDDBELL_MIS0_PBE15_S 15U -#define LRFDDBELL_MIS0_PBE15_SET 0x00008000U -#define LRFDDBELL_MIS0_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE14 0x00004000U -#define LRFDDBELL_MIS0_PBE14_M 0x00004000U -#define LRFDDBELL_MIS0_PBE14_S 14U -#define LRFDDBELL_MIS0_PBE14_SET 0x00004000U -#define LRFDDBELL_MIS0_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE13 0x00002000U -#define LRFDDBELL_MIS0_PBE13_M 0x00002000U -#define LRFDDBELL_MIS0_PBE13_S 13U -#define LRFDDBELL_MIS0_PBE13_SET 0x00002000U -#define LRFDDBELL_MIS0_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE12 0x00001000U -#define LRFDDBELL_MIS0_PBE12_M 0x00001000U -#define LRFDDBELL_MIS0_PBE12_S 12U -#define LRFDDBELL_MIS0_PBE12_SET 0x00001000U -#define LRFDDBELL_MIS0_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE11 0x00000800U -#define LRFDDBELL_MIS0_PBE11_M 0x00000800U -#define LRFDDBELL_MIS0_PBE11_S 11U -#define LRFDDBELL_MIS0_PBE11_SET 0x00000800U -#define LRFDDBELL_MIS0_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE10 0x00000400U -#define LRFDDBELL_MIS0_PBE10_M 0x00000400U -#define LRFDDBELL_MIS0_PBE10_S 10U -#define LRFDDBELL_MIS0_PBE10_SET 0x00000400U -#define LRFDDBELL_MIS0_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE9 0x00000200U -#define LRFDDBELL_MIS0_PBE9_M 0x00000200U -#define LRFDDBELL_MIS0_PBE9_S 9U -#define LRFDDBELL_MIS0_PBE9_SET 0x00000200U -#define LRFDDBELL_MIS0_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE8 0x00000100U -#define LRFDDBELL_MIS0_PBE8_M 0x00000100U -#define LRFDDBELL_MIS0_PBE8_S 8U -#define LRFDDBELL_MIS0_PBE8_SET 0x00000100U -#define LRFDDBELL_MIS0_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE7 0x00000080U -#define LRFDDBELL_MIS0_PBE7_M 0x00000080U -#define LRFDDBELL_MIS0_PBE7_S 7U -#define LRFDDBELL_MIS0_PBE7_SET 0x00000080U -#define LRFDDBELL_MIS0_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE6 0x00000040U -#define LRFDDBELL_MIS0_PBE6_M 0x00000040U -#define LRFDDBELL_MIS0_PBE6_S 6U -#define LRFDDBELL_MIS0_PBE6_SET 0x00000040U -#define LRFDDBELL_MIS0_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE5 0x00000020U -#define LRFDDBELL_MIS0_PBE5_M 0x00000020U -#define LRFDDBELL_MIS0_PBE5_S 5U -#define LRFDDBELL_MIS0_PBE5_SET 0x00000020U -#define LRFDDBELL_MIS0_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE4 0x00000010U -#define LRFDDBELL_MIS0_PBE4_M 0x00000010U -#define LRFDDBELL_MIS0_PBE4_S 4U -#define LRFDDBELL_MIS0_PBE4_SET 0x00000010U -#define LRFDDBELL_MIS0_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE3 0x00000008U -#define LRFDDBELL_MIS0_PBE3_M 0x00000008U -#define LRFDDBELL_MIS0_PBE3_S 3U -#define LRFDDBELL_MIS0_PBE3_SET 0x00000008U -#define LRFDDBELL_MIS0_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE2 0x00000004U -#define LRFDDBELL_MIS0_PBE2_M 0x00000004U -#define LRFDDBELL_MIS0_PBE2_S 2U -#define LRFDDBELL_MIS0_PBE2_SET 0x00000004U -#define LRFDDBELL_MIS0_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE1 0x00000002U -#define LRFDDBELL_MIS0_PBE1_M 0x00000002U -#define LRFDDBELL_MIS0_PBE1_S 1U -#define LRFDDBELL_MIS0_PBE1_SET 0x00000002U -#define LRFDDBELL_MIS0_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS0_PBE0 0x00000001U -#define LRFDDBELL_MIS0_PBE0_M 0x00000001U -#define LRFDDBELL_MIS0_PBE0_S 0U -#define LRFDDBELL_MIS0_PBE0_SET 0x00000001U -#define LRFDDBELL_MIS0_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ISET0 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_SYSTIM2 0x80000000U -#define LRFDDBELL_ISET0_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ISET0_SYSTIM2_S 31U -#define LRFDDBELL_ISET0_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_ISET0_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_SYSTIM1 0x40000000U -#define LRFDDBELL_ISET0_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ISET0_SYSTIM1_S 30U -#define LRFDDBELL_ISET0_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_ISET0_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_SYSTIM0 0x20000000U -#define LRFDDBELL_ISET0_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ISET0_SYSTIM0_S 29U -#define LRFDDBELL_ISET0_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_ISET0_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMDONE 0x10000000U -#define LRFDDBELL_ISET0_MDMDONE_M 0x10000000U -#define LRFDDBELL_ISET0_MDMDONE_S 28U -#define LRFDDBELL_ISET0_MDMDONE_SET 0x10000000U -#define LRFDDBELL_ISET0_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMIN 0x08000000U -#define LRFDDBELL_ISET0_MDMIN_M 0x08000000U -#define LRFDDBELL_ISET0_MDMIN_S 27U -#define LRFDDBELL_ISET0_MDMIN_SET 0x08000000U -#define LRFDDBELL_ISET0_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMOUT 0x04000000U -#define LRFDDBELL_ISET0_MDMOUT_M 0x04000000U -#define LRFDDBELL_ISET0_MDMOUT_S 26U -#define LRFDDBELL_ISET0_MDMOUT_SET 0x04000000U -#define LRFDDBELL_ISET0_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMSOFT2 0x02000000U -#define LRFDDBELL_ISET0_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ISET0_MDMSOFT2_S 25U -#define LRFDDBELL_ISET0_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_ISET0_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMSOFT1 0x01000000U -#define LRFDDBELL_ISET0_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ISET0_MDMSOFT1_S 24U -#define LRFDDBELL_ISET0_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_ISET0_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_MDMSOFT0 0x00800000U -#define LRFDDBELL_ISET0_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ISET0_MDMSOFT0_S 23U -#define LRFDDBELL_ISET0_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_ISET0_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_RFEDONE 0x00400000U -#define LRFDDBELL_ISET0_RFEDONE_M 0x00400000U -#define LRFDDBELL_ISET0_RFEDONE_S 22U -#define LRFDDBELL_ISET0_RFEDONE_SET 0x00400000U -#define LRFDDBELL_ISET0_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_RFESOFT1 0x00200000U -#define LRFDDBELL_ISET0_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ISET0_RFESOFT1_S 21U -#define LRFDDBELL_ISET0_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_ISET0_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_RFESOFT0 0x00100000U -#define LRFDDBELL_ISET0_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ISET0_RFESOFT0_S 20U -#define LRFDDBELL_ISET0_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_ISET0_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_LOCK 0x00080000U -#define LRFDDBELL_ISET0_LOCK_M 0x00080000U -#define LRFDDBELL_ISET0_LOCK_S 19U -#define LRFDDBELL_ISET0_LOCK_SET 0x00080000U -#define LRFDDBELL_ISET0_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_LOL 0x00040000U -#define LRFDDBELL_ISET0_LOL_M 0x00040000U -#define LRFDDBELL_ISET0_LOL_S 18U -#define LRFDDBELL_ISET0_LOL_SET 0x00040000U -#define LRFDDBELL_ISET0_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_TXFIFO 0x00020000U -#define LRFDDBELL_ISET0_TXFIFO_M 0x00020000U -#define LRFDDBELL_ISET0_TXFIFO_S 17U -#define LRFDDBELL_ISET0_TXFIFO_SET 0x00020000U -#define LRFDDBELL_ISET0_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_RXFIFO 0x00010000U -#define LRFDDBELL_ISET0_RXFIFO_M 0x00010000U -#define LRFDDBELL_ISET0_RXFIFO_S 16U -#define LRFDDBELL_ISET0_RXFIFO_SET 0x00010000U -#define LRFDDBELL_ISET0_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE15 0x00008000U -#define LRFDDBELL_ISET0_PBE15_M 0x00008000U -#define LRFDDBELL_ISET0_PBE15_S 15U -#define LRFDDBELL_ISET0_PBE15_SET 0x00008000U -#define LRFDDBELL_ISET0_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE14 0x00004000U -#define LRFDDBELL_ISET0_PBE14_M 0x00004000U -#define LRFDDBELL_ISET0_PBE14_S 14U -#define LRFDDBELL_ISET0_PBE14_SET 0x00004000U -#define LRFDDBELL_ISET0_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE13 0x00002000U -#define LRFDDBELL_ISET0_PBE13_M 0x00002000U -#define LRFDDBELL_ISET0_PBE13_S 13U -#define LRFDDBELL_ISET0_PBE13_SET 0x00002000U -#define LRFDDBELL_ISET0_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE12 0x00001000U -#define LRFDDBELL_ISET0_PBE12_M 0x00001000U -#define LRFDDBELL_ISET0_PBE12_S 12U -#define LRFDDBELL_ISET0_PBE12_SET 0x00001000U -#define LRFDDBELL_ISET0_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE11 0x00000800U -#define LRFDDBELL_ISET0_PBE11_M 0x00000800U -#define LRFDDBELL_ISET0_PBE11_S 11U -#define LRFDDBELL_ISET0_PBE11_SET 0x00000800U -#define LRFDDBELL_ISET0_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE10 0x00000400U -#define LRFDDBELL_ISET0_PBE10_M 0x00000400U -#define LRFDDBELL_ISET0_PBE10_S 10U -#define LRFDDBELL_ISET0_PBE10_SET 0x00000400U -#define LRFDDBELL_ISET0_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE9 0x00000200U -#define LRFDDBELL_ISET0_PBE9_M 0x00000200U -#define LRFDDBELL_ISET0_PBE9_S 9U -#define LRFDDBELL_ISET0_PBE9_SET 0x00000200U -#define LRFDDBELL_ISET0_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE8 0x00000100U -#define LRFDDBELL_ISET0_PBE8_M 0x00000100U -#define LRFDDBELL_ISET0_PBE8_S 8U -#define LRFDDBELL_ISET0_PBE8_SET 0x00000100U -#define LRFDDBELL_ISET0_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE7 0x00000080U -#define LRFDDBELL_ISET0_PBE7_M 0x00000080U -#define LRFDDBELL_ISET0_PBE7_S 7U -#define LRFDDBELL_ISET0_PBE7_SET 0x00000080U -#define LRFDDBELL_ISET0_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE6 0x00000040U -#define LRFDDBELL_ISET0_PBE6_M 0x00000040U -#define LRFDDBELL_ISET0_PBE6_S 6U -#define LRFDDBELL_ISET0_PBE6_SET 0x00000040U -#define LRFDDBELL_ISET0_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE5 0x00000020U -#define LRFDDBELL_ISET0_PBE5_M 0x00000020U -#define LRFDDBELL_ISET0_PBE5_S 5U -#define LRFDDBELL_ISET0_PBE5_SET 0x00000020U -#define LRFDDBELL_ISET0_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE4 0x00000010U -#define LRFDDBELL_ISET0_PBE4_M 0x00000010U -#define LRFDDBELL_ISET0_PBE4_S 4U -#define LRFDDBELL_ISET0_PBE4_SET 0x00000010U -#define LRFDDBELL_ISET0_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE3 0x00000008U -#define LRFDDBELL_ISET0_PBE3_M 0x00000008U -#define LRFDDBELL_ISET0_PBE3_S 3U -#define LRFDDBELL_ISET0_PBE3_SET 0x00000008U -#define LRFDDBELL_ISET0_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE2 0x00000004U -#define LRFDDBELL_ISET0_PBE2_M 0x00000004U -#define LRFDDBELL_ISET0_PBE2_S 2U -#define LRFDDBELL_ISET0_PBE2_SET 0x00000004U -#define LRFDDBELL_ISET0_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE1 0x00000002U -#define LRFDDBELL_ISET0_PBE1_M 0x00000002U -#define LRFDDBELL_ISET0_PBE1_S 1U -#define LRFDDBELL_ISET0_PBE1_SET 0x00000002U -#define LRFDDBELL_ISET0_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET0_PBE0 0x00000001U -#define LRFDDBELL_ISET0_PBE0_M 0x00000001U -#define LRFDDBELL_ISET0_PBE0_S 0U -#define LRFDDBELL_ISET0_PBE0_SET 0x00000001U -#define LRFDDBELL_ISET0_PBE0_NOEFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ICLR0 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_SYSTIM2 0x80000000U -#define LRFDDBELL_ICLR0_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ICLR0_SYSTIM2_S 31U -#define LRFDDBELL_ICLR0_SYSTIM2_CLR 0x80000000U -#define LRFDDBELL_ICLR0_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_SYSTIM1 0x40000000U -#define LRFDDBELL_ICLR0_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ICLR0_SYSTIM1_S 30U -#define LRFDDBELL_ICLR0_SYSTIM1_CLR 0x40000000U -#define LRFDDBELL_ICLR0_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_SYSTIM0 0x20000000U -#define LRFDDBELL_ICLR0_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ICLR0_SYSTIM0_S 29U -#define LRFDDBELL_ICLR0_SYSTIM0_CLR 0x20000000U -#define LRFDDBELL_ICLR0_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMDONE 0x10000000U -#define LRFDDBELL_ICLR0_MDMDONE_M 0x10000000U -#define LRFDDBELL_ICLR0_MDMDONE_S 28U -#define LRFDDBELL_ICLR0_MDMDONE_CLR 0x10000000U -#define LRFDDBELL_ICLR0_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMIN 0x08000000U -#define LRFDDBELL_ICLR0_MDMIN_M 0x08000000U -#define LRFDDBELL_ICLR0_MDMIN_S 27U -#define LRFDDBELL_ICLR0_MDMIN_CLR 0x08000000U -#define LRFDDBELL_ICLR0_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMOUT 0x04000000U -#define LRFDDBELL_ICLR0_MDMOUT_M 0x04000000U -#define LRFDDBELL_ICLR0_MDMOUT_S 26U -#define LRFDDBELL_ICLR0_MDMOUT_CLR 0x04000000U -#define LRFDDBELL_ICLR0_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMSOFT2 0x02000000U -#define LRFDDBELL_ICLR0_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ICLR0_MDMSOFT2_S 25U -#define LRFDDBELL_ICLR0_MDMSOFT2_CLR 0x02000000U -#define LRFDDBELL_ICLR0_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMSOFT1 0x01000000U -#define LRFDDBELL_ICLR0_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ICLR0_MDMSOFT1_S 24U -#define LRFDDBELL_ICLR0_MDMSOFT1_CLR 0x01000000U -#define LRFDDBELL_ICLR0_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_MDMSOFT0 0x00800000U -#define LRFDDBELL_ICLR0_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ICLR0_MDMSOFT0_S 23U -#define LRFDDBELL_ICLR0_MDMSOFT0_CLR 0x00800000U -#define LRFDDBELL_ICLR0_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_RFEDONE 0x00400000U -#define LRFDDBELL_ICLR0_RFEDONE_M 0x00400000U -#define LRFDDBELL_ICLR0_RFEDONE_S 22U -#define LRFDDBELL_ICLR0_RFEDONE_CLR 0x00400000U -#define LRFDDBELL_ICLR0_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_RFESOFT1 0x00200000U -#define LRFDDBELL_ICLR0_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ICLR0_RFESOFT1_S 21U -#define LRFDDBELL_ICLR0_RFESOFT1_CLR 0x00200000U -#define LRFDDBELL_ICLR0_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_RFESOFT0 0x00100000U -#define LRFDDBELL_ICLR0_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ICLR0_RFESOFT0_S 20U -#define LRFDDBELL_ICLR0_RFESOFT0_CLR 0x00100000U -#define LRFDDBELL_ICLR0_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_LOCK 0x00080000U -#define LRFDDBELL_ICLR0_LOCK_M 0x00080000U -#define LRFDDBELL_ICLR0_LOCK_S 19U -#define LRFDDBELL_ICLR0_LOCK_CLR 0x00080000U -#define LRFDDBELL_ICLR0_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_LOL 0x00040000U -#define LRFDDBELL_ICLR0_LOL_M 0x00040000U -#define LRFDDBELL_ICLR0_LOL_S 18U -#define LRFDDBELL_ICLR0_LOL_CLR 0x00040000U -#define LRFDDBELL_ICLR0_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_TXFIFO 0x00020000U -#define LRFDDBELL_ICLR0_TXFIFO_M 0x00020000U -#define LRFDDBELL_ICLR0_TXFIFO_S 17U -#define LRFDDBELL_ICLR0_TXFIFO_CLR 0x00020000U -#define LRFDDBELL_ICLR0_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_RXFIFO 0x00010000U -#define LRFDDBELL_ICLR0_RXFIFO_M 0x00010000U -#define LRFDDBELL_ICLR0_RXFIFO_S 16U -#define LRFDDBELL_ICLR0_RXFIFO_CLR 0x00010000U -#define LRFDDBELL_ICLR0_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE15 0x00008000U -#define LRFDDBELL_ICLR0_PBE15_M 0x00008000U -#define LRFDDBELL_ICLR0_PBE15_S 15U -#define LRFDDBELL_ICLR0_PBE15_CLR 0x00008000U -#define LRFDDBELL_ICLR0_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE14 0x00004000U -#define LRFDDBELL_ICLR0_PBE14_M 0x00004000U -#define LRFDDBELL_ICLR0_PBE14_S 14U -#define LRFDDBELL_ICLR0_PBE14_CLR 0x00004000U -#define LRFDDBELL_ICLR0_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE13 0x00002000U -#define LRFDDBELL_ICLR0_PBE13_M 0x00002000U -#define LRFDDBELL_ICLR0_PBE13_S 13U -#define LRFDDBELL_ICLR0_PBE13_CLR 0x00002000U -#define LRFDDBELL_ICLR0_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE12 0x00001000U -#define LRFDDBELL_ICLR0_PBE12_M 0x00001000U -#define LRFDDBELL_ICLR0_PBE12_S 12U -#define LRFDDBELL_ICLR0_PBE12_CLR 0x00001000U -#define LRFDDBELL_ICLR0_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE11 0x00000800U -#define LRFDDBELL_ICLR0_PBE11_M 0x00000800U -#define LRFDDBELL_ICLR0_PBE11_S 11U -#define LRFDDBELL_ICLR0_PBE11_CLR 0x00000800U -#define LRFDDBELL_ICLR0_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE10 0x00000400U -#define LRFDDBELL_ICLR0_PBE10_M 0x00000400U -#define LRFDDBELL_ICLR0_PBE10_S 10U -#define LRFDDBELL_ICLR0_PBE10_CLR 0x00000400U -#define LRFDDBELL_ICLR0_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE9 0x00000200U -#define LRFDDBELL_ICLR0_PBE9_M 0x00000200U -#define LRFDDBELL_ICLR0_PBE9_S 9U -#define LRFDDBELL_ICLR0_PBE9_CLR 0x00000200U -#define LRFDDBELL_ICLR0_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE8 0x00000100U -#define LRFDDBELL_ICLR0_PBE8_M 0x00000100U -#define LRFDDBELL_ICLR0_PBE8_S 8U -#define LRFDDBELL_ICLR0_PBE8_CLR 0x00000100U -#define LRFDDBELL_ICLR0_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE7 0x00000080U -#define LRFDDBELL_ICLR0_PBE7_M 0x00000080U -#define LRFDDBELL_ICLR0_PBE7_S 7U -#define LRFDDBELL_ICLR0_PBE7_CLR 0x00000080U -#define LRFDDBELL_ICLR0_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE6 0x00000040U -#define LRFDDBELL_ICLR0_PBE6_M 0x00000040U -#define LRFDDBELL_ICLR0_PBE6_S 6U -#define LRFDDBELL_ICLR0_PBE6_CLR 0x00000040U -#define LRFDDBELL_ICLR0_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE5 0x00000020U -#define LRFDDBELL_ICLR0_PBE5_M 0x00000020U -#define LRFDDBELL_ICLR0_PBE5_S 5U -#define LRFDDBELL_ICLR0_PBE5_CLR 0x00000020U -#define LRFDDBELL_ICLR0_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE4 0x00000010U -#define LRFDDBELL_ICLR0_PBE4_M 0x00000010U -#define LRFDDBELL_ICLR0_PBE4_S 4U -#define LRFDDBELL_ICLR0_PBE4_CLR 0x00000010U -#define LRFDDBELL_ICLR0_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE3 0x00000008U -#define LRFDDBELL_ICLR0_PBE3_M 0x00000008U -#define LRFDDBELL_ICLR0_PBE3_S 3U -#define LRFDDBELL_ICLR0_PBE3_CLR 0x00000008U -#define LRFDDBELL_ICLR0_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE2 0x00000004U -#define LRFDDBELL_ICLR0_PBE2_M 0x00000004U -#define LRFDDBELL_ICLR0_PBE2_S 2U -#define LRFDDBELL_ICLR0_PBE2_CLR 0x00000004U -#define LRFDDBELL_ICLR0_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE1 0x00000002U -#define LRFDDBELL_ICLR0_PBE1_M 0x00000002U -#define LRFDDBELL_ICLR0_PBE1_S 1U -#define LRFDDBELL_ICLR0_PBE1_CLR 0x00000002U -#define LRFDDBELL_ICLR0_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR0_PBE0 0x00000001U -#define LRFDDBELL_ICLR0_PBE0_M 0x00000001U -#define LRFDDBELL_ICLR0_PBE0_S 0U -#define LRFDDBELL_ICLR0_PBE0_CLR 0x00000001U -#define LRFDDBELL_ICLR0_PBE0_NOEFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_IMASK1 -// -//***************************************************************************** -// Field: [30] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_SYSTIM2 0x40000000U -#define LRFDDBELL_IMASK1_SYSTIM2_M 0x40000000U -#define LRFDDBELL_IMASK1_SYSTIM2_S 30U -#define LRFDDBELL_IMASK1_SYSTIM2_EN 0x40000000U -#define LRFDDBELL_IMASK1_SYSTIM2_DIS 0x00000000U - -// Field: [29] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_SYSTIM1 0x20000000U -#define LRFDDBELL_IMASK1_SYSTIM1_M 0x20000000U -#define LRFDDBELL_IMASK1_SYSTIM1_S 29U -#define LRFDDBELL_IMASK1_SYSTIM1_EN 0x20000000U -#define LRFDDBELL_IMASK1_SYSTIM1_DIS 0x00000000U - -// Field: [28] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_SYSTIM0 0x10000000U -#define LRFDDBELL_IMASK1_SYSTIM0_M 0x10000000U -#define LRFDDBELL_IMASK1_SYSTIM0_S 28U -#define LRFDDBELL_IMASK1_SYSTIM0_EN 0x10000000U -#define LRFDDBELL_IMASK1_SYSTIM0_DIS 0x00000000U - -// Field: [27] MDMDONE -// -// MDMDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMDONE 0x08000000U -#define LRFDDBELL_IMASK1_MDMDONE_M 0x08000000U -#define LRFDDBELL_IMASK1_MDMDONE_S 27U -#define LRFDDBELL_IMASK1_MDMDONE_EN 0x08000000U -#define LRFDDBELL_IMASK1_MDMDONE_DIS 0x00000000U - -// Field: [26] MDMIN -// -// MDMIN event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMIN 0x04000000U -#define LRFDDBELL_IMASK1_MDMIN_M 0x04000000U -#define LRFDDBELL_IMASK1_MDMIN_S 26U -#define LRFDDBELL_IMASK1_MDMIN_EN 0x04000000U -#define LRFDDBELL_IMASK1_MDMIN_DIS 0x00000000U - -// Field: [25] MDMOUT -// -// MDMOUT event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMOUT 0x02000000U -#define LRFDDBELL_IMASK1_MDMOUT_M 0x02000000U -#define LRFDDBELL_IMASK1_MDMOUT_S 25U -#define LRFDDBELL_IMASK1_MDMOUT_EN 0x02000000U -#define LRFDDBELL_IMASK1_MDMOUT_DIS 0x00000000U - -// Field: [24] MDMSOFT2 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMSOFT2 0x01000000U -#define LRFDDBELL_IMASK1_MDMSOFT2_M 0x01000000U -#define LRFDDBELL_IMASK1_MDMSOFT2_S 24U -#define LRFDDBELL_IMASK1_MDMSOFT2_EN 0x01000000U -#define LRFDDBELL_IMASK1_MDMSOFT2_DIS 0x00000000U - -// Field: [23] MDMSOFT1 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMSOFT1 0x00800000U -#define LRFDDBELL_IMASK1_MDMSOFT1_M 0x00800000U -#define LRFDDBELL_IMASK1_MDMSOFT1_S 23U -#define LRFDDBELL_IMASK1_MDMSOFT1_EN 0x00800000U -#define LRFDDBELL_IMASK1_MDMSOFT1_DIS 0x00000000U - -// Field: [22] MDMSOFT0 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_MDMSOFT0 0x00400000U -#define LRFDDBELL_IMASK1_MDMSOFT0_M 0x00400000U -#define LRFDDBELL_IMASK1_MDMSOFT0_S 22U -#define LRFDDBELL_IMASK1_MDMSOFT0_EN 0x00400000U -#define LRFDDBELL_IMASK1_MDMSOFT0_DIS 0x00000000U - -// Field: [21] RFEDONE -// -// RFEDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_RFEDONE 0x00200000U -#define LRFDDBELL_IMASK1_RFEDONE_M 0x00200000U -#define LRFDDBELL_IMASK1_RFEDONE_S 21U -#define LRFDDBELL_IMASK1_RFEDONE_EN 0x00200000U -#define LRFDDBELL_IMASK1_RFEDONE_DIS 0x00000000U - -// Field: [20] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_RFESOFT1 0x00100000U -#define LRFDDBELL_IMASK1_RFESOFT1_M 0x00100000U -#define LRFDDBELL_IMASK1_RFESOFT1_S 20U -#define LRFDDBELL_IMASK1_RFESOFT1_EN 0x00100000U -#define LRFDDBELL_IMASK1_RFESOFT1_DIS 0x00000000U - -// Field: [19] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_RFESOFT0 0x00080000U -#define LRFDDBELL_IMASK1_RFESOFT0_M 0x00080000U -#define LRFDDBELL_IMASK1_RFESOFT0_S 19U -#define LRFDDBELL_IMASK1_RFESOFT0_EN 0x00080000U -#define LRFDDBELL_IMASK1_RFESOFT0_DIS 0x00000000U - -// Field: [18] LOCK -// -// LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_LOCK 0x00040000U -#define LRFDDBELL_IMASK1_LOCK_M 0x00040000U -#define LRFDDBELL_IMASK1_LOCK_S 18U -#define LRFDDBELL_IMASK1_LOCK_EN 0x00040000U -#define LRFDDBELL_IMASK1_LOCK_DIS 0x00000000U - -// Field: [17] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_LOL 0x00020000U -#define LRFDDBELL_IMASK1_LOL_M 0x00020000U -#define LRFDDBELL_IMASK1_LOL_S 17U -#define LRFDDBELL_IMASK1_LOL_EN 0x00020000U -#define LRFDDBELL_IMASK1_LOL_DIS 0x00000000U - -// Field: [16] TXFIFO -// -// TXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_TXFIFO 0x00010000U -#define LRFDDBELL_IMASK1_TXFIFO_M 0x00010000U -#define LRFDDBELL_IMASK1_TXFIFO_S 16U -#define LRFDDBELL_IMASK1_TXFIFO_EN 0x00010000U -#define LRFDDBELL_IMASK1_TXFIFO_DIS 0x00000000U - -// Field: [15] RXFIFO -// -// RXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_RXFIFO 0x00008000U -#define LRFDDBELL_IMASK1_RXFIFO_M 0x00008000U -#define LRFDDBELL_IMASK1_RXFIFO_S 15U -#define LRFDDBELL_IMASK1_RXFIFO_EN 0x00008000U -#define LRFDDBELL_IMASK1_RXFIFO_DIS 0x00000000U - -// Field: [14] PBE15 -// -// PBE15 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE15 0x00004000U -#define LRFDDBELL_IMASK1_PBE15_M 0x00004000U -#define LRFDDBELL_IMASK1_PBE15_S 14U -#define LRFDDBELL_IMASK1_PBE15_EN 0x00004000U -#define LRFDDBELL_IMASK1_PBE15_DIS 0x00000000U - -// Field: [13] PBE14 -// -// PBE14 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE14 0x00002000U -#define LRFDDBELL_IMASK1_PBE14_M 0x00002000U -#define LRFDDBELL_IMASK1_PBE14_S 13U -#define LRFDDBELL_IMASK1_PBE14_EN 0x00002000U -#define LRFDDBELL_IMASK1_PBE14_DIS 0x00000000U - -// Field: [12] PBE13 -// -// PBE13 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE13 0x00001000U -#define LRFDDBELL_IMASK1_PBE13_M 0x00001000U -#define LRFDDBELL_IMASK1_PBE13_S 12U -#define LRFDDBELL_IMASK1_PBE13_EN 0x00001000U -#define LRFDDBELL_IMASK1_PBE13_DIS 0x00000000U - -// Field: [11] PBE12 -// -// PBE12 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE12 0x00000800U -#define LRFDDBELL_IMASK1_PBE12_M 0x00000800U -#define LRFDDBELL_IMASK1_PBE12_S 11U -#define LRFDDBELL_IMASK1_PBE12_EN 0x00000800U -#define LRFDDBELL_IMASK1_PBE12_DIS 0x00000000U - -// Field: [10] PBE11 -// -// PBE11 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE11 0x00000400U -#define LRFDDBELL_IMASK1_PBE11_M 0x00000400U -#define LRFDDBELL_IMASK1_PBE11_S 10U -#define LRFDDBELL_IMASK1_PBE11_EN 0x00000400U -#define LRFDDBELL_IMASK1_PBE11_DIS 0x00000000U - -// Field: [9] PBE10 -// -// PBE10 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE10 0x00000200U -#define LRFDDBELL_IMASK1_PBE10_M 0x00000200U -#define LRFDDBELL_IMASK1_PBE10_S 9U -#define LRFDDBELL_IMASK1_PBE10_EN 0x00000200U -#define LRFDDBELL_IMASK1_PBE10_DIS 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE8 0x00000100U -#define LRFDDBELL_IMASK1_PBE8_M 0x00000100U -#define LRFDDBELL_IMASK1_PBE8_S 8U -#define LRFDDBELL_IMASK1_PBE8_EN 0x00000100U -#define LRFDDBELL_IMASK1_PBE8_DIS 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE7 0x00000080U -#define LRFDDBELL_IMASK1_PBE7_M 0x00000080U -#define LRFDDBELL_IMASK1_PBE7_S 7U -#define LRFDDBELL_IMASK1_PBE7_EN 0x00000080U -#define LRFDDBELL_IMASK1_PBE7_DIS 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE6 0x00000040U -#define LRFDDBELL_IMASK1_PBE6_M 0x00000040U -#define LRFDDBELL_IMASK1_PBE6_S 6U -#define LRFDDBELL_IMASK1_PBE6_EN 0x00000040U -#define LRFDDBELL_IMASK1_PBE6_DIS 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE5 0x00000020U -#define LRFDDBELL_IMASK1_PBE5_M 0x00000020U -#define LRFDDBELL_IMASK1_PBE5_S 5U -#define LRFDDBELL_IMASK1_PBE5_EN 0x00000020U -#define LRFDDBELL_IMASK1_PBE5_DIS 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE4 0x00000010U -#define LRFDDBELL_IMASK1_PBE4_M 0x00000010U -#define LRFDDBELL_IMASK1_PBE4_S 4U -#define LRFDDBELL_IMASK1_PBE4_EN 0x00000010U -#define LRFDDBELL_IMASK1_PBE4_DIS 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE3 0x00000008U -#define LRFDDBELL_IMASK1_PBE3_M 0x00000008U -#define LRFDDBELL_IMASK1_PBE3_S 3U -#define LRFDDBELL_IMASK1_PBE3_EN 0x00000008U -#define LRFDDBELL_IMASK1_PBE3_DIS 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE2 0x00000004U -#define LRFDDBELL_IMASK1_PBE2_M 0x00000004U -#define LRFDDBELL_IMASK1_PBE2_S 2U -#define LRFDDBELL_IMASK1_PBE2_EN 0x00000004U -#define LRFDDBELL_IMASK1_PBE2_DIS 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE1 0x00000002U -#define LRFDDBELL_IMASK1_PBE1_M 0x00000002U -#define LRFDDBELL_IMASK1_PBE1_S 1U -#define LRFDDBELL_IMASK1_PBE1_EN 0x00000002U -#define LRFDDBELL_IMASK1_PBE1_DIS 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK1_PBE0 0x00000001U -#define LRFDDBELL_IMASK1_PBE0_M 0x00000001U -#define LRFDDBELL_IMASK1_PBE0_S 0U -#define LRFDDBELL_IMASK1_PBE0_EN 0x00000001U -#define LRFDDBELL_IMASK1_PBE0_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_RIS1 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_SYSTIM2 0x80000000U -#define LRFDDBELL_RIS1_SYSTIM2_M 0x80000000U -#define LRFDDBELL_RIS1_SYSTIM2_S 31U -#define LRFDDBELL_RIS1_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_RIS1_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_SYSTIM1 0x40000000U -#define LRFDDBELL_RIS1_SYSTIM1_M 0x40000000U -#define LRFDDBELL_RIS1_SYSTIM1_S 30U -#define LRFDDBELL_RIS1_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_RIS1_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_SYSTIM0 0x20000000U -#define LRFDDBELL_RIS1_SYSTIM0_M 0x20000000U -#define LRFDDBELL_RIS1_SYSTIM0_S 29U -#define LRFDDBELL_RIS1_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_RIS1_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMDONE 0x10000000U -#define LRFDDBELL_RIS1_MDMDONE_M 0x10000000U -#define LRFDDBELL_RIS1_MDMDONE_S 28U -#define LRFDDBELL_RIS1_MDMDONE_SET 0x10000000U -#define LRFDDBELL_RIS1_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMIN 0x08000000U -#define LRFDDBELL_RIS1_MDMIN_M 0x08000000U -#define LRFDDBELL_RIS1_MDMIN_S 27U -#define LRFDDBELL_RIS1_MDMIN_SET 0x08000000U -#define LRFDDBELL_RIS1_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMOUT 0x04000000U -#define LRFDDBELL_RIS1_MDMOUT_M 0x04000000U -#define LRFDDBELL_RIS1_MDMOUT_S 26U -#define LRFDDBELL_RIS1_MDMOUT_SET 0x04000000U -#define LRFDDBELL_RIS1_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMSOFT2 0x02000000U -#define LRFDDBELL_RIS1_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_RIS1_MDMSOFT2_S 25U -#define LRFDDBELL_RIS1_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_RIS1_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMSOFT1 0x01000000U -#define LRFDDBELL_RIS1_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_RIS1_MDMSOFT1_S 24U -#define LRFDDBELL_RIS1_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_RIS1_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_MDMSOFT0 0x00800000U -#define LRFDDBELL_RIS1_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_RIS1_MDMSOFT0_S 23U -#define LRFDDBELL_RIS1_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_RIS1_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_RFEDONE 0x00400000U -#define LRFDDBELL_RIS1_RFEDONE_M 0x00400000U -#define LRFDDBELL_RIS1_RFEDONE_S 22U -#define LRFDDBELL_RIS1_RFEDONE_SET 0x00400000U -#define LRFDDBELL_RIS1_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_RFESOFT1 0x00200000U -#define LRFDDBELL_RIS1_RFESOFT1_M 0x00200000U -#define LRFDDBELL_RIS1_RFESOFT1_S 21U -#define LRFDDBELL_RIS1_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_RIS1_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_RFESOFT0 0x00100000U -#define LRFDDBELL_RIS1_RFESOFT0_M 0x00100000U -#define LRFDDBELL_RIS1_RFESOFT0_S 20U -#define LRFDDBELL_RIS1_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_RIS1_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_LOCK 0x00080000U -#define LRFDDBELL_RIS1_LOCK_M 0x00080000U -#define LRFDDBELL_RIS1_LOCK_S 19U -#define LRFDDBELL_RIS1_LOCK_SET 0x00080000U -#define LRFDDBELL_RIS1_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_LOL 0x00040000U -#define LRFDDBELL_RIS1_LOL_M 0x00040000U -#define LRFDDBELL_RIS1_LOL_S 18U -#define LRFDDBELL_RIS1_LOL_SET 0x00040000U -#define LRFDDBELL_RIS1_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_TXFIFO 0x00020000U -#define LRFDDBELL_RIS1_TXFIFO_M 0x00020000U -#define LRFDDBELL_RIS1_TXFIFO_S 17U -#define LRFDDBELL_RIS1_TXFIFO_SET 0x00020000U -#define LRFDDBELL_RIS1_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_RXFIFO 0x00010000U -#define LRFDDBELL_RIS1_RXFIFO_M 0x00010000U -#define LRFDDBELL_RIS1_RXFIFO_S 16U -#define LRFDDBELL_RIS1_RXFIFO_SET 0x00010000U -#define LRFDDBELL_RIS1_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE15 0x00008000U -#define LRFDDBELL_RIS1_PBE15_M 0x00008000U -#define LRFDDBELL_RIS1_PBE15_S 15U -#define LRFDDBELL_RIS1_PBE15_SET 0x00008000U -#define LRFDDBELL_RIS1_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE14 0x00004000U -#define LRFDDBELL_RIS1_PBE14_M 0x00004000U -#define LRFDDBELL_RIS1_PBE14_S 14U -#define LRFDDBELL_RIS1_PBE14_SET 0x00004000U -#define LRFDDBELL_RIS1_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE13 0x00002000U -#define LRFDDBELL_RIS1_PBE13_M 0x00002000U -#define LRFDDBELL_RIS1_PBE13_S 13U -#define LRFDDBELL_RIS1_PBE13_SET 0x00002000U -#define LRFDDBELL_RIS1_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE12 0x00001000U -#define LRFDDBELL_RIS1_PBE12_M 0x00001000U -#define LRFDDBELL_RIS1_PBE12_S 12U -#define LRFDDBELL_RIS1_PBE12_SET 0x00001000U -#define LRFDDBELL_RIS1_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE11 0x00000800U -#define LRFDDBELL_RIS1_PBE11_M 0x00000800U -#define LRFDDBELL_RIS1_PBE11_S 11U -#define LRFDDBELL_RIS1_PBE11_SET 0x00000800U -#define LRFDDBELL_RIS1_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE10 0x00000400U -#define LRFDDBELL_RIS1_PBE10_M 0x00000400U -#define LRFDDBELL_RIS1_PBE10_S 10U -#define LRFDDBELL_RIS1_PBE10_SET 0x00000400U -#define LRFDDBELL_RIS1_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE9 0x00000200U -#define LRFDDBELL_RIS1_PBE9_M 0x00000200U -#define LRFDDBELL_RIS1_PBE9_S 9U -#define LRFDDBELL_RIS1_PBE9_SET 0x00000200U -#define LRFDDBELL_RIS1_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE8 0x00000100U -#define LRFDDBELL_RIS1_PBE8_M 0x00000100U -#define LRFDDBELL_RIS1_PBE8_S 8U -#define LRFDDBELL_RIS1_PBE8_SET 0x00000100U -#define LRFDDBELL_RIS1_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE7 0x00000080U -#define LRFDDBELL_RIS1_PBE7_M 0x00000080U -#define LRFDDBELL_RIS1_PBE7_S 7U -#define LRFDDBELL_RIS1_PBE7_SET 0x00000080U -#define LRFDDBELL_RIS1_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE6 0x00000040U -#define LRFDDBELL_RIS1_PBE6_M 0x00000040U -#define LRFDDBELL_RIS1_PBE6_S 6U -#define LRFDDBELL_RIS1_PBE6_SET 0x00000040U -#define LRFDDBELL_RIS1_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE5 0x00000020U -#define LRFDDBELL_RIS1_PBE5_M 0x00000020U -#define LRFDDBELL_RIS1_PBE5_S 5U -#define LRFDDBELL_RIS1_PBE5_SET 0x00000020U -#define LRFDDBELL_RIS1_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE4 0x00000010U -#define LRFDDBELL_RIS1_PBE4_M 0x00000010U -#define LRFDDBELL_RIS1_PBE4_S 4U -#define LRFDDBELL_RIS1_PBE4_SET 0x00000010U -#define LRFDDBELL_RIS1_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE3 0x00000008U -#define LRFDDBELL_RIS1_PBE3_M 0x00000008U -#define LRFDDBELL_RIS1_PBE3_S 3U -#define LRFDDBELL_RIS1_PBE3_SET 0x00000008U -#define LRFDDBELL_RIS1_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE2 0x00000004U -#define LRFDDBELL_RIS1_PBE2_M 0x00000004U -#define LRFDDBELL_RIS1_PBE2_S 2U -#define LRFDDBELL_RIS1_PBE2_SET 0x00000004U -#define LRFDDBELL_RIS1_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE1 0x00000002U -#define LRFDDBELL_RIS1_PBE1_M 0x00000002U -#define LRFDDBELL_RIS1_PBE1_S 1U -#define LRFDDBELL_RIS1_PBE1_SET 0x00000002U -#define LRFDDBELL_RIS1_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS1_PBE0 0x00000001U -#define LRFDDBELL_RIS1_PBE0_M 0x00000001U -#define LRFDDBELL_RIS1_PBE0_S 0U -#define LRFDDBELL_RIS1_PBE0_SET 0x00000001U -#define LRFDDBELL_RIS1_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_MIS1 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_SYSTIM2 0x80000000U -#define LRFDDBELL_MIS1_SYSTIM2_M 0x80000000U -#define LRFDDBELL_MIS1_SYSTIM2_S 31U -#define LRFDDBELL_MIS1_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_MIS1_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_SYSTIM1 0x40000000U -#define LRFDDBELL_MIS1_SYSTIM1_M 0x40000000U -#define LRFDDBELL_MIS1_SYSTIM1_S 30U -#define LRFDDBELL_MIS1_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_MIS1_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_SYSTIM0 0x20000000U -#define LRFDDBELL_MIS1_SYSTIM0_M 0x20000000U -#define LRFDDBELL_MIS1_SYSTIM0_S 29U -#define LRFDDBELL_MIS1_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_MIS1_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMDONE 0x10000000U -#define LRFDDBELL_MIS1_MDMDONE_M 0x10000000U -#define LRFDDBELL_MIS1_MDMDONE_S 28U -#define LRFDDBELL_MIS1_MDMDONE_SET 0x10000000U -#define LRFDDBELL_MIS1_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMIN 0x08000000U -#define LRFDDBELL_MIS1_MDMIN_M 0x08000000U -#define LRFDDBELL_MIS1_MDMIN_S 27U -#define LRFDDBELL_MIS1_MDMIN_SET 0x08000000U -#define LRFDDBELL_MIS1_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMOUT 0x04000000U -#define LRFDDBELL_MIS1_MDMOUT_M 0x04000000U -#define LRFDDBELL_MIS1_MDMOUT_S 26U -#define LRFDDBELL_MIS1_MDMOUT_SET 0x04000000U -#define LRFDDBELL_MIS1_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMSOFT2 0x02000000U -#define LRFDDBELL_MIS1_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_MIS1_MDMSOFT2_S 25U -#define LRFDDBELL_MIS1_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_MIS1_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMSOFT1 0x01000000U -#define LRFDDBELL_MIS1_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_MIS1_MDMSOFT1_S 24U -#define LRFDDBELL_MIS1_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_MIS1_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_MDMSOFT0 0x00800000U -#define LRFDDBELL_MIS1_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_MIS1_MDMSOFT0_S 23U -#define LRFDDBELL_MIS1_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_MIS1_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_RFEDONE 0x00400000U -#define LRFDDBELL_MIS1_RFEDONE_M 0x00400000U -#define LRFDDBELL_MIS1_RFEDONE_S 22U -#define LRFDDBELL_MIS1_RFEDONE_SET 0x00400000U -#define LRFDDBELL_MIS1_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_RFESOFT1 0x00200000U -#define LRFDDBELL_MIS1_RFESOFT1_M 0x00200000U -#define LRFDDBELL_MIS1_RFESOFT1_S 21U -#define LRFDDBELL_MIS1_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_MIS1_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_RFESOFT0 0x00100000U -#define LRFDDBELL_MIS1_RFESOFT0_M 0x00100000U -#define LRFDDBELL_MIS1_RFESOFT0_S 20U -#define LRFDDBELL_MIS1_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_MIS1_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_LOCK 0x00080000U -#define LRFDDBELL_MIS1_LOCK_M 0x00080000U -#define LRFDDBELL_MIS1_LOCK_S 19U -#define LRFDDBELL_MIS1_LOCK_SET 0x00080000U -#define LRFDDBELL_MIS1_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_LOL 0x00040000U -#define LRFDDBELL_MIS1_LOL_M 0x00040000U -#define LRFDDBELL_MIS1_LOL_S 18U -#define LRFDDBELL_MIS1_LOL_SET 0x00040000U -#define LRFDDBELL_MIS1_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_TXFIFO 0x00020000U -#define LRFDDBELL_MIS1_TXFIFO_M 0x00020000U -#define LRFDDBELL_MIS1_TXFIFO_S 17U -#define LRFDDBELL_MIS1_TXFIFO_SET 0x00020000U -#define LRFDDBELL_MIS1_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_RXFIFO 0x00010000U -#define LRFDDBELL_MIS1_RXFIFO_M 0x00010000U -#define LRFDDBELL_MIS1_RXFIFO_S 16U -#define LRFDDBELL_MIS1_RXFIFO_SET 0x00010000U -#define LRFDDBELL_MIS1_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE15 0x00008000U -#define LRFDDBELL_MIS1_PBE15_M 0x00008000U -#define LRFDDBELL_MIS1_PBE15_S 15U -#define LRFDDBELL_MIS1_PBE15_SET 0x00008000U -#define LRFDDBELL_MIS1_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE14 0x00004000U -#define LRFDDBELL_MIS1_PBE14_M 0x00004000U -#define LRFDDBELL_MIS1_PBE14_S 14U -#define LRFDDBELL_MIS1_PBE14_SET 0x00004000U -#define LRFDDBELL_MIS1_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE13 0x00002000U -#define LRFDDBELL_MIS1_PBE13_M 0x00002000U -#define LRFDDBELL_MIS1_PBE13_S 13U -#define LRFDDBELL_MIS1_PBE13_SET 0x00002000U -#define LRFDDBELL_MIS1_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE12 0x00001000U -#define LRFDDBELL_MIS1_PBE12_M 0x00001000U -#define LRFDDBELL_MIS1_PBE12_S 12U -#define LRFDDBELL_MIS1_PBE12_SET 0x00001000U -#define LRFDDBELL_MIS1_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE11 0x00000800U -#define LRFDDBELL_MIS1_PBE11_M 0x00000800U -#define LRFDDBELL_MIS1_PBE11_S 11U -#define LRFDDBELL_MIS1_PBE11_SET 0x00000800U -#define LRFDDBELL_MIS1_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE10 0x00000400U -#define LRFDDBELL_MIS1_PBE10_M 0x00000400U -#define LRFDDBELL_MIS1_PBE10_S 10U -#define LRFDDBELL_MIS1_PBE10_SET 0x00000400U -#define LRFDDBELL_MIS1_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE9 0x00000200U -#define LRFDDBELL_MIS1_PBE9_M 0x00000200U -#define LRFDDBELL_MIS1_PBE9_S 9U -#define LRFDDBELL_MIS1_PBE9_SET 0x00000200U -#define LRFDDBELL_MIS1_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE8 0x00000100U -#define LRFDDBELL_MIS1_PBE8_M 0x00000100U -#define LRFDDBELL_MIS1_PBE8_S 8U -#define LRFDDBELL_MIS1_PBE8_SET 0x00000100U -#define LRFDDBELL_MIS1_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE7 0x00000080U -#define LRFDDBELL_MIS1_PBE7_M 0x00000080U -#define LRFDDBELL_MIS1_PBE7_S 7U -#define LRFDDBELL_MIS1_PBE7_SET 0x00000080U -#define LRFDDBELL_MIS1_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE6 0x00000040U -#define LRFDDBELL_MIS1_PBE6_M 0x00000040U -#define LRFDDBELL_MIS1_PBE6_S 6U -#define LRFDDBELL_MIS1_PBE6_SET 0x00000040U -#define LRFDDBELL_MIS1_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE5 0x00000020U -#define LRFDDBELL_MIS1_PBE5_M 0x00000020U -#define LRFDDBELL_MIS1_PBE5_S 5U -#define LRFDDBELL_MIS1_PBE5_SET 0x00000020U -#define LRFDDBELL_MIS1_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE4 0x00000010U -#define LRFDDBELL_MIS1_PBE4_M 0x00000010U -#define LRFDDBELL_MIS1_PBE4_S 4U -#define LRFDDBELL_MIS1_PBE4_SET 0x00000010U -#define LRFDDBELL_MIS1_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE3 0x00000008U -#define LRFDDBELL_MIS1_PBE3_M 0x00000008U -#define LRFDDBELL_MIS1_PBE3_S 3U -#define LRFDDBELL_MIS1_PBE3_SET 0x00000008U -#define LRFDDBELL_MIS1_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE2 0x00000004U -#define LRFDDBELL_MIS1_PBE2_M 0x00000004U -#define LRFDDBELL_MIS1_PBE2_S 2U -#define LRFDDBELL_MIS1_PBE2_SET 0x00000004U -#define LRFDDBELL_MIS1_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE1 0x00000002U -#define LRFDDBELL_MIS1_PBE1_M 0x00000002U -#define LRFDDBELL_MIS1_PBE1_S 1U -#define LRFDDBELL_MIS1_PBE1_SET 0x00000002U -#define LRFDDBELL_MIS1_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS1_PBE0 0x00000001U -#define LRFDDBELL_MIS1_PBE0_M 0x00000001U -#define LRFDDBELL_MIS1_PBE0_S 0U -#define LRFDDBELL_MIS1_PBE0_SET 0x00000001U -#define LRFDDBELL_MIS1_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ISET1 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_SYSTIM2 0x80000000U -#define LRFDDBELL_ISET1_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ISET1_SYSTIM2_S 31U -#define LRFDDBELL_ISET1_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_ISET1_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_SYSTIM1 0x40000000U -#define LRFDDBELL_ISET1_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ISET1_SYSTIM1_S 30U -#define LRFDDBELL_ISET1_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_ISET1_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_SYSTIM0 0x20000000U -#define LRFDDBELL_ISET1_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ISET1_SYSTIM0_S 29U -#define LRFDDBELL_ISET1_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_ISET1_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMDONE 0x10000000U -#define LRFDDBELL_ISET1_MDMDONE_M 0x10000000U -#define LRFDDBELL_ISET1_MDMDONE_S 28U -#define LRFDDBELL_ISET1_MDMDONE_SET 0x10000000U -#define LRFDDBELL_ISET1_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMIN 0x08000000U -#define LRFDDBELL_ISET1_MDMIN_M 0x08000000U -#define LRFDDBELL_ISET1_MDMIN_S 27U -#define LRFDDBELL_ISET1_MDMIN_SET 0x08000000U -#define LRFDDBELL_ISET1_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMOUT 0x04000000U -#define LRFDDBELL_ISET1_MDMOUT_M 0x04000000U -#define LRFDDBELL_ISET1_MDMOUT_S 26U -#define LRFDDBELL_ISET1_MDMOUT_SET 0x04000000U -#define LRFDDBELL_ISET1_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMSOFT2 0x02000000U -#define LRFDDBELL_ISET1_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ISET1_MDMSOFT2_S 25U -#define LRFDDBELL_ISET1_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_ISET1_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMSOFT1 0x01000000U -#define LRFDDBELL_ISET1_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ISET1_MDMSOFT1_S 24U -#define LRFDDBELL_ISET1_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_ISET1_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_MDMSOFT0 0x00800000U -#define LRFDDBELL_ISET1_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ISET1_MDMSOFT0_S 23U -#define LRFDDBELL_ISET1_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_ISET1_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_RFEDONE 0x00400000U -#define LRFDDBELL_ISET1_RFEDONE_M 0x00400000U -#define LRFDDBELL_ISET1_RFEDONE_S 22U -#define LRFDDBELL_ISET1_RFEDONE_SET 0x00400000U -#define LRFDDBELL_ISET1_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_RFESOFT1 0x00200000U -#define LRFDDBELL_ISET1_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ISET1_RFESOFT1_S 21U -#define LRFDDBELL_ISET1_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_ISET1_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_RFESOFT0 0x00100000U -#define LRFDDBELL_ISET1_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ISET1_RFESOFT0_S 20U -#define LRFDDBELL_ISET1_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_ISET1_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_LOCK 0x00080000U -#define LRFDDBELL_ISET1_LOCK_M 0x00080000U -#define LRFDDBELL_ISET1_LOCK_S 19U -#define LRFDDBELL_ISET1_LOCK_SET 0x00080000U -#define LRFDDBELL_ISET1_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_LOL 0x00040000U -#define LRFDDBELL_ISET1_LOL_M 0x00040000U -#define LRFDDBELL_ISET1_LOL_S 18U -#define LRFDDBELL_ISET1_LOL_SET 0x00040000U -#define LRFDDBELL_ISET1_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_TXFIFO 0x00020000U -#define LRFDDBELL_ISET1_TXFIFO_M 0x00020000U -#define LRFDDBELL_ISET1_TXFIFO_S 17U -#define LRFDDBELL_ISET1_TXFIFO_SET 0x00020000U -#define LRFDDBELL_ISET1_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_RXFIFO 0x00010000U -#define LRFDDBELL_ISET1_RXFIFO_M 0x00010000U -#define LRFDDBELL_ISET1_RXFIFO_S 16U -#define LRFDDBELL_ISET1_RXFIFO_SET 0x00010000U -#define LRFDDBELL_ISET1_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE15 0x00008000U -#define LRFDDBELL_ISET1_PBE15_M 0x00008000U -#define LRFDDBELL_ISET1_PBE15_S 15U -#define LRFDDBELL_ISET1_PBE15_SET 0x00008000U -#define LRFDDBELL_ISET1_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE14 0x00004000U -#define LRFDDBELL_ISET1_PBE14_M 0x00004000U -#define LRFDDBELL_ISET1_PBE14_S 14U -#define LRFDDBELL_ISET1_PBE14_SET 0x00004000U -#define LRFDDBELL_ISET1_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE13 0x00002000U -#define LRFDDBELL_ISET1_PBE13_M 0x00002000U -#define LRFDDBELL_ISET1_PBE13_S 13U -#define LRFDDBELL_ISET1_PBE13_SET 0x00002000U -#define LRFDDBELL_ISET1_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE12 0x00001000U -#define LRFDDBELL_ISET1_PBE12_M 0x00001000U -#define LRFDDBELL_ISET1_PBE12_S 12U -#define LRFDDBELL_ISET1_PBE12_SET 0x00001000U -#define LRFDDBELL_ISET1_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE11 0x00000800U -#define LRFDDBELL_ISET1_PBE11_M 0x00000800U -#define LRFDDBELL_ISET1_PBE11_S 11U -#define LRFDDBELL_ISET1_PBE11_SET 0x00000800U -#define LRFDDBELL_ISET1_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE10 0x00000400U -#define LRFDDBELL_ISET1_PBE10_M 0x00000400U -#define LRFDDBELL_ISET1_PBE10_S 10U -#define LRFDDBELL_ISET1_PBE10_SET 0x00000400U -#define LRFDDBELL_ISET1_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE9 0x00000200U -#define LRFDDBELL_ISET1_PBE9_M 0x00000200U -#define LRFDDBELL_ISET1_PBE9_S 9U -#define LRFDDBELL_ISET1_PBE9_SET 0x00000200U -#define LRFDDBELL_ISET1_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE8 0x00000100U -#define LRFDDBELL_ISET1_PBE8_M 0x00000100U -#define LRFDDBELL_ISET1_PBE8_S 8U -#define LRFDDBELL_ISET1_PBE8_SET 0x00000100U -#define LRFDDBELL_ISET1_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE7 0x00000080U -#define LRFDDBELL_ISET1_PBE7_M 0x00000080U -#define LRFDDBELL_ISET1_PBE7_S 7U -#define LRFDDBELL_ISET1_PBE7_SET 0x00000080U -#define LRFDDBELL_ISET1_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE6 0x00000040U -#define LRFDDBELL_ISET1_PBE6_M 0x00000040U -#define LRFDDBELL_ISET1_PBE6_S 6U -#define LRFDDBELL_ISET1_PBE6_SET 0x00000040U -#define LRFDDBELL_ISET1_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE5 0x00000020U -#define LRFDDBELL_ISET1_PBE5_M 0x00000020U -#define LRFDDBELL_ISET1_PBE5_S 5U -#define LRFDDBELL_ISET1_PBE5_SET 0x00000020U -#define LRFDDBELL_ISET1_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE4 0x00000010U -#define LRFDDBELL_ISET1_PBE4_M 0x00000010U -#define LRFDDBELL_ISET1_PBE4_S 4U -#define LRFDDBELL_ISET1_PBE4_SET 0x00000010U -#define LRFDDBELL_ISET1_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE3 0x00000008U -#define LRFDDBELL_ISET1_PBE3_M 0x00000008U -#define LRFDDBELL_ISET1_PBE3_S 3U -#define LRFDDBELL_ISET1_PBE3_SET 0x00000008U -#define LRFDDBELL_ISET1_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE2 0x00000004U -#define LRFDDBELL_ISET1_PBE2_M 0x00000004U -#define LRFDDBELL_ISET1_PBE2_S 2U -#define LRFDDBELL_ISET1_PBE2_SET 0x00000004U -#define LRFDDBELL_ISET1_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE1 0x00000002U -#define LRFDDBELL_ISET1_PBE1_M 0x00000002U -#define LRFDDBELL_ISET1_PBE1_S 1U -#define LRFDDBELL_ISET1_PBE1_SET 0x00000002U -#define LRFDDBELL_ISET1_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET1_PBE0 0x00000001U -#define LRFDDBELL_ISET1_PBE0_M 0x00000001U -#define LRFDDBELL_ISET1_PBE0_S 0U -#define LRFDDBELL_ISET1_PBE0_SET 0x00000001U -#define LRFDDBELL_ISET1_PBE0_NOEFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ICLR1 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_SYSTIM2 0x80000000U -#define LRFDDBELL_ICLR1_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ICLR1_SYSTIM2_S 31U -#define LRFDDBELL_ICLR1_SYSTIM2_CLR 0x80000000U -#define LRFDDBELL_ICLR1_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_SYSTIM1 0x40000000U -#define LRFDDBELL_ICLR1_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ICLR1_SYSTIM1_S 30U -#define LRFDDBELL_ICLR1_SYSTIM1_CLR 0x40000000U -#define LRFDDBELL_ICLR1_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_SYSTIM0 0x20000000U -#define LRFDDBELL_ICLR1_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ICLR1_SYSTIM0_S 29U -#define LRFDDBELL_ICLR1_SYSTIM0_CLR 0x20000000U -#define LRFDDBELL_ICLR1_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMDONE 0x10000000U -#define LRFDDBELL_ICLR1_MDMDONE_M 0x10000000U -#define LRFDDBELL_ICLR1_MDMDONE_S 28U -#define LRFDDBELL_ICLR1_MDMDONE_CLR 0x10000000U -#define LRFDDBELL_ICLR1_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMIN 0x08000000U -#define LRFDDBELL_ICLR1_MDMIN_M 0x08000000U -#define LRFDDBELL_ICLR1_MDMIN_S 27U -#define LRFDDBELL_ICLR1_MDMIN_CLR 0x08000000U -#define LRFDDBELL_ICLR1_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMOUT 0x04000000U -#define LRFDDBELL_ICLR1_MDMOUT_M 0x04000000U -#define LRFDDBELL_ICLR1_MDMOUT_S 26U -#define LRFDDBELL_ICLR1_MDMOUT_CLR 0x04000000U -#define LRFDDBELL_ICLR1_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMSOFT2 0x02000000U -#define LRFDDBELL_ICLR1_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ICLR1_MDMSOFT2_S 25U -#define LRFDDBELL_ICLR1_MDMSOFT2_CLR 0x02000000U -#define LRFDDBELL_ICLR1_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMSOFT1 0x01000000U -#define LRFDDBELL_ICLR1_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ICLR1_MDMSOFT1_S 24U -#define LRFDDBELL_ICLR1_MDMSOFT1_CLR 0x01000000U -#define LRFDDBELL_ICLR1_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_MDMSOFT0 0x00800000U -#define LRFDDBELL_ICLR1_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ICLR1_MDMSOFT0_S 23U -#define LRFDDBELL_ICLR1_MDMSOFT0_CLR 0x00800000U -#define LRFDDBELL_ICLR1_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_RFEDONE 0x00400000U -#define LRFDDBELL_ICLR1_RFEDONE_M 0x00400000U -#define LRFDDBELL_ICLR1_RFEDONE_S 22U -#define LRFDDBELL_ICLR1_RFEDONE_CLR 0x00400000U -#define LRFDDBELL_ICLR1_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_RFESOFT1 0x00200000U -#define LRFDDBELL_ICLR1_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ICLR1_RFESOFT1_S 21U -#define LRFDDBELL_ICLR1_RFESOFT1_CLR 0x00200000U -#define LRFDDBELL_ICLR1_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_RFESOFT0 0x00100000U -#define LRFDDBELL_ICLR1_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ICLR1_RFESOFT0_S 20U -#define LRFDDBELL_ICLR1_RFESOFT0_CLR 0x00100000U -#define LRFDDBELL_ICLR1_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_LOCK 0x00080000U -#define LRFDDBELL_ICLR1_LOCK_M 0x00080000U -#define LRFDDBELL_ICLR1_LOCK_S 19U -#define LRFDDBELL_ICLR1_LOCK_CLR 0x00080000U -#define LRFDDBELL_ICLR1_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_LOL 0x00040000U -#define LRFDDBELL_ICLR1_LOL_M 0x00040000U -#define LRFDDBELL_ICLR1_LOL_S 18U -#define LRFDDBELL_ICLR1_LOL_CLR 0x00040000U -#define LRFDDBELL_ICLR1_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_TXFIFO 0x00020000U -#define LRFDDBELL_ICLR1_TXFIFO_M 0x00020000U -#define LRFDDBELL_ICLR1_TXFIFO_S 17U -#define LRFDDBELL_ICLR1_TXFIFO_CLR 0x00020000U -#define LRFDDBELL_ICLR1_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_RXFIFO 0x00010000U -#define LRFDDBELL_ICLR1_RXFIFO_M 0x00010000U -#define LRFDDBELL_ICLR1_RXFIFO_S 16U -#define LRFDDBELL_ICLR1_RXFIFO_CLR 0x00010000U -#define LRFDDBELL_ICLR1_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE15 0x00008000U -#define LRFDDBELL_ICLR1_PBE15_M 0x00008000U -#define LRFDDBELL_ICLR1_PBE15_S 15U -#define LRFDDBELL_ICLR1_PBE15_CLR 0x00008000U -#define LRFDDBELL_ICLR1_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE14 0x00004000U -#define LRFDDBELL_ICLR1_PBE14_M 0x00004000U -#define LRFDDBELL_ICLR1_PBE14_S 14U -#define LRFDDBELL_ICLR1_PBE14_CLR 0x00004000U -#define LRFDDBELL_ICLR1_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE13 0x00002000U -#define LRFDDBELL_ICLR1_PBE13_M 0x00002000U -#define LRFDDBELL_ICLR1_PBE13_S 13U -#define LRFDDBELL_ICLR1_PBE13_CLR 0x00002000U -#define LRFDDBELL_ICLR1_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE12 0x00001000U -#define LRFDDBELL_ICLR1_PBE12_M 0x00001000U -#define LRFDDBELL_ICLR1_PBE12_S 12U -#define LRFDDBELL_ICLR1_PBE12_CLR 0x00001000U -#define LRFDDBELL_ICLR1_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE11 0x00000800U -#define LRFDDBELL_ICLR1_PBE11_M 0x00000800U -#define LRFDDBELL_ICLR1_PBE11_S 11U -#define LRFDDBELL_ICLR1_PBE11_CLR 0x00000800U -#define LRFDDBELL_ICLR1_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE10 0x00000400U -#define LRFDDBELL_ICLR1_PBE10_M 0x00000400U -#define LRFDDBELL_ICLR1_PBE10_S 10U -#define LRFDDBELL_ICLR1_PBE10_CLR 0x00000400U -#define LRFDDBELL_ICLR1_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE9 0x00000200U -#define LRFDDBELL_ICLR1_PBE9_M 0x00000200U -#define LRFDDBELL_ICLR1_PBE9_S 9U -#define LRFDDBELL_ICLR1_PBE9_CLR 0x00000200U -#define LRFDDBELL_ICLR1_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE8 0x00000100U -#define LRFDDBELL_ICLR1_PBE8_M 0x00000100U -#define LRFDDBELL_ICLR1_PBE8_S 8U -#define LRFDDBELL_ICLR1_PBE8_CLR 0x00000100U -#define LRFDDBELL_ICLR1_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE7 0x00000080U -#define LRFDDBELL_ICLR1_PBE7_M 0x00000080U -#define LRFDDBELL_ICLR1_PBE7_S 7U -#define LRFDDBELL_ICLR1_PBE7_CLR 0x00000080U -#define LRFDDBELL_ICLR1_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE6 0x00000040U -#define LRFDDBELL_ICLR1_PBE6_M 0x00000040U -#define LRFDDBELL_ICLR1_PBE6_S 6U -#define LRFDDBELL_ICLR1_PBE6_CLR 0x00000040U -#define LRFDDBELL_ICLR1_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE5 0x00000020U -#define LRFDDBELL_ICLR1_PBE5_M 0x00000020U -#define LRFDDBELL_ICLR1_PBE5_S 5U -#define LRFDDBELL_ICLR1_PBE5_CLR 0x00000020U -#define LRFDDBELL_ICLR1_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE4 0x00000010U -#define LRFDDBELL_ICLR1_PBE4_M 0x00000010U -#define LRFDDBELL_ICLR1_PBE4_S 4U -#define LRFDDBELL_ICLR1_PBE4_CLR 0x00000010U -#define LRFDDBELL_ICLR1_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE3 0x00000008U -#define LRFDDBELL_ICLR1_PBE3_M 0x00000008U -#define LRFDDBELL_ICLR1_PBE3_S 3U -#define LRFDDBELL_ICLR1_PBE3_CLR 0x00000008U -#define LRFDDBELL_ICLR1_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE2 0x00000004U -#define LRFDDBELL_ICLR1_PBE2_M 0x00000004U -#define LRFDDBELL_ICLR1_PBE2_S 2U -#define LRFDDBELL_ICLR1_PBE2_CLR 0x00000004U -#define LRFDDBELL_ICLR1_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE1 0x00000002U -#define LRFDDBELL_ICLR1_PBE1_M 0x00000002U -#define LRFDDBELL_ICLR1_PBE1_S 1U -#define LRFDDBELL_ICLR1_PBE1_CLR 0x00000002U -#define LRFDDBELL_ICLR1_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR1_PBE0 0x00000001U -#define LRFDDBELL_ICLR1_PBE0_M 0x00000001U -#define LRFDDBELL_ICLR1_PBE0_S 0U -#define LRFDDBELL_ICLR1_PBE0_CLR 0x00000001U -#define LRFDDBELL_ICLR1_PBE0_NOEFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_IMASK2 -// -//***************************************************************************** -// Field: [30] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_SYSTIM2 0x40000000U -#define LRFDDBELL_IMASK2_SYSTIM2_M 0x40000000U -#define LRFDDBELL_IMASK2_SYSTIM2_S 30U -#define LRFDDBELL_IMASK2_SYSTIM2_EN 0x40000000U -#define LRFDDBELL_IMASK2_SYSTIM2_DIS 0x00000000U - -// Field: [29] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_SYSTIM1 0x20000000U -#define LRFDDBELL_IMASK2_SYSTIM1_M 0x20000000U -#define LRFDDBELL_IMASK2_SYSTIM1_S 29U -#define LRFDDBELL_IMASK2_SYSTIM1_EN 0x20000000U -#define LRFDDBELL_IMASK2_SYSTIM1_DIS 0x00000000U - -// Field: [28] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_SYSTIM0 0x10000000U -#define LRFDDBELL_IMASK2_SYSTIM0_M 0x10000000U -#define LRFDDBELL_IMASK2_SYSTIM0_S 28U -#define LRFDDBELL_IMASK2_SYSTIM0_EN 0x10000000U -#define LRFDDBELL_IMASK2_SYSTIM0_DIS 0x00000000U - -// Field: [27] MDMDONE -// -// MDMDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMDONE 0x08000000U -#define LRFDDBELL_IMASK2_MDMDONE_M 0x08000000U -#define LRFDDBELL_IMASK2_MDMDONE_S 27U -#define LRFDDBELL_IMASK2_MDMDONE_EN 0x08000000U -#define LRFDDBELL_IMASK2_MDMDONE_DIS 0x00000000U - -// Field: [26] MDMIN -// -// MDMIN event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMIN 0x04000000U -#define LRFDDBELL_IMASK2_MDMIN_M 0x04000000U -#define LRFDDBELL_IMASK2_MDMIN_S 26U -#define LRFDDBELL_IMASK2_MDMIN_EN 0x04000000U -#define LRFDDBELL_IMASK2_MDMIN_DIS 0x00000000U - -// Field: [25] MDMOUT -// -// MDMOUT event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMOUT 0x02000000U -#define LRFDDBELL_IMASK2_MDMOUT_M 0x02000000U -#define LRFDDBELL_IMASK2_MDMOUT_S 25U -#define LRFDDBELL_IMASK2_MDMOUT_EN 0x02000000U -#define LRFDDBELL_IMASK2_MDMOUT_DIS 0x00000000U - -// Field: [24] MDMSOFT2 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMSOFT2 0x01000000U -#define LRFDDBELL_IMASK2_MDMSOFT2_M 0x01000000U -#define LRFDDBELL_IMASK2_MDMSOFT2_S 24U -#define LRFDDBELL_IMASK2_MDMSOFT2_EN 0x01000000U -#define LRFDDBELL_IMASK2_MDMSOFT2_DIS 0x00000000U - -// Field: [23] MDMSOFT1 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMSOFT1 0x00800000U -#define LRFDDBELL_IMASK2_MDMSOFT1_M 0x00800000U -#define LRFDDBELL_IMASK2_MDMSOFT1_S 23U -#define LRFDDBELL_IMASK2_MDMSOFT1_EN 0x00800000U -#define LRFDDBELL_IMASK2_MDMSOFT1_DIS 0x00000000U - -// Field: [22] MDMSOFT0 -// -// MDMSOFT2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_MDMSOFT0 0x00400000U -#define LRFDDBELL_IMASK2_MDMSOFT0_M 0x00400000U -#define LRFDDBELL_IMASK2_MDMSOFT0_S 22U -#define LRFDDBELL_IMASK2_MDMSOFT0_EN 0x00400000U -#define LRFDDBELL_IMASK2_MDMSOFT0_DIS 0x00000000U - -// Field: [21] RFEDONE -// -// RFEDONE event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_RFEDONE 0x00200000U -#define LRFDDBELL_IMASK2_RFEDONE_M 0x00200000U -#define LRFDDBELL_IMASK2_RFEDONE_S 21U -#define LRFDDBELL_IMASK2_RFEDONE_EN 0x00200000U -#define LRFDDBELL_IMASK2_RFEDONE_DIS 0x00000000U - -// Field: [20] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_RFESOFT1 0x00100000U -#define LRFDDBELL_IMASK2_RFESOFT1_M 0x00100000U -#define LRFDDBELL_IMASK2_RFESOFT1_S 20U -#define LRFDDBELL_IMASK2_RFESOFT1_EN 0x00100000U -#define LRFDDBELL_IMASK2_RFESOFT1_DIS 0x00000000U - -// Field: [19] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_RFESOFT0 0x00080000U -#define LRFDDBELL_IMASK2_RFESOFT0_M 0x00080000U -#define LRFDDBELL_IMASK2_RFESOFT0_S 19U -#define LRFDDBELL_IMASK2_RFESOFT0_EN 0x00080000U -#define LRFDDBELL_IMASK2_RFESOFT0_DIS 0x00000000U - -// Field: [18] LOCK -// -// LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_LOCK 0x00040000U -#define LRFDDBELL_IMASK2_LOCK_M 0x00040000U -#define LRFDDBELL_IMASK2_LOCK_S 18U -#define LRFDDBELL_IMASK2_LOCK_EN 0x00040000U -#define LRFDDBELL_IMASK2_LOCK_DIS 0x00000000U - -// Field: [17] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_LOL 0x00020000U -#define LRFDDBELL_IMASK2_LOL_M 0x00020000U -#define LRFDDBELL_IMASK2_LOL_S 17U -#define LRFDDBELL_IMASK2_LOL_EN 0x00020000U -#define LRFDDBELL_IMASK2_LOL_DIS 0x00000000U - -// Field: [16] TXFIFO -// -// TXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_TXFIFO 0x00010000U -#define LRFDDBELL_IMASK2_TXFIFO_M 0x00010000U -#define LRFDDBELL_IMASK2_TXFIFO_S 16U -#define LRFDDBELL_IMASK2_TXFIFO_EN 0x00010000U -#define LRFDDBELL_IMASK2_TXFIFO_DIS 0x00000000U - -// Field: [15] RXFIFO -// -// RXFIFO event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_RXFIFO 0x00008000U -#define LRFDDBELL_IMASK2_RXFIFO_M 0x00008000U -#define LRFDDBELL_IMASK2_RXFIFO_S 15U -#define LRFDDBELL_IMASK2_RXFIFO_EN 0x00008000U -#define LRFDDBELL_IMASK2_RXFIFO_DIS 0x00000000U - -// Field: [14] PBE15 -// -// PBE15 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE15 0x00004000U -#define LRFDDBELL_IMASK2_PBE15_M 0x00004000U -#define LRFDDBELL_IMASK2_PBE15_S 14U -#define LRFDDBELL_IMASK2_PBE15_EN 0x00004000U -#define LRFDDBELL_IMASK2_PBE15_DIS 0x00000000U - -// Field: [13] PBE14 -// -// PBE14 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE14 0x00002000U -#define LRFDDBELL_IMASK2_PBE14_M 0x00002000U -#define LRFDDBELL_IMASK2_PBE14_S 13U -#define LRFDDBELL_IMASK2_PBE14_EN 0x00002000U -#define LRFDDBELL_IMASK2_PBE14_DIS 0x00000000U - -// Field: [12] PBE13 -// -// PBE13 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE13 0x00001000U -#define LRFDDBELL_IMASK2_PBE13_M 0x00001000U -#define LRFDDBELL_IMASK2_PBE13_S 12U -#define LRFDDBELL_IMASK2_PBE13_EN 0x00001000U -#define LRFDDBELL_IMASK2_PBE13_DIS 0x00000000U - -// Field: [11] PBE12 -// -// PBE12 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE12 0x00000800U -#define LRFDDBELL_IMASK2_PBE12_M 0x00000800U -#define LRFDDBELL_IMASK2_PBE12_S 11U -#define LRFDDBELL_IMASK2_PBE12_EN 0x00000800U -#define LRFDDBELL_IMASK2_PBE12_DIS 0x00000000U - -// Field: [10] PBE11 -// -// PBE11 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE11 0x00000400U -#define LRFDDBELL_IMASK2_PBE11_M 0x00000400U -#define LRFDDBELL_IMASK2_PBE11_S 10U -#define LRFDDBELL_IMASK2_PBE11_EN 0x00000400U -#define LRFDDBELL_IMASK2_PBE11_DIS 0x00000000U - -// Field: [9] PBE10 -// -// PBE10 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE10 0x00000200U -#define LRFDDBELL_IMASK2_PBE10_M 0x00000200U -#define LRFDDBELL_IMASK2_PBE10_S 9U -#define LRFDDBELL_IMASK2_PBE10_EN 0x00000200U -#define LRFDDBELL_IMASK2_PBE10_DIS 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE8 0x00000100U -#define LRFDDBELL_IMASK2_PBE8_M 0x00000100U -#define LRFDDBELL_IMASK2_PBE8_S 8U -#define LRFDDBELL_IMASK2_PBE8_EN 0x00000100U -#define LRFDDBELL_IMASK2_PBE8_DIS 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE7 0x00000080U -#define LRFDDBELL_IMASK2_PBE7_M 0x00000080U -#define LRFDDBELL_IMASK2_PBE7_S 7U -#define LRFDDBELL_IMASK2_PBE7_EN 0x00000080U -#define LRFDDBELL_IMASK2_PBE7_DIS 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE6 0x00000040U -#define LRFDDBELL_IMASK2_PBE6_M 0x00000040U -#define LRFDDBELL_IMASK2_PBE6_S 6U -#define LRFDDBELL_IMASK2_PBE6_EN 0x00000040U -#define LRFDDBELL_IMASK2_PBE6_DIS 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE5 0x00000020U -#define LRFDDBELL_IMASK2_PBE5_M 0x00000020U -#define LRFDDBELL_IMASK2_PBE5_S 5U -#define LRFDDBELL_IMASK2_PBE5_EN 0x00000020U -#define LRFDDBELL_IMASK2_PBE5_DIS 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE4 0x00000010U -#define LRFDDBELL_IMASK2_PBE4_M 0x00000010U -#define LRFDDBELL_IMASK2_PBE4_S 4U -#define LRFDDBELL_IMASK2_PBE4_EN 0x00000010U -#define LRFDDBELL_IMASK2_PBE4_DIS 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE3 0x00000008U -#define LRFDDBELL_IMASK2_PBE3_M 0x00000008U -#define LRFDDBELL_IMASK2_PBE3_S 3U -#define LRFDDBELL_IMASK2_PBE3_EN 0x00000008U -#define LRFDDBELL_IMASK2_PBE3_DIS 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE2 0x00000004U -#define LRFDDBELL_IMASK2_PBE2_M 0x00000004U -#define LRFDDBELL_IMASK2_PBE2_S 2U -#define LRFDDBELL_IMASK2_PBE2_EN 0x00000004U -#define LRFDDBELL_IMASK2_PBE2_DIS 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE1 0x00000002U -#define LRFDDBELL_IMASK2_PBE1_M 0x00000002U -#define LRFDDBELL_IMASK2_PBE1_S 1U -#define LRFDDBELL_IMASK2_PBE1_EN 0x00000002U -#define LRFDDBELL_IMASK2_PBE1_DIS 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// EN Enable interrupt mask -// DIS Disable interrupt mask -#define LRFDDBELL_IMASK2_PBE0 0x00000001U -#define LRFDDBELL_IMASK2_PBE0_M 0x00000001U -#define LRFDDBELL_IMASK2_PBE0_S 0U -#define LRFDDBELL_IMASK2_PBE0_EN 0x00000001U -#define LRFDDBELL_IMASK2_PBE0_DIS 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_RIS2 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_SYSTIM2 0x80000000U -#define LRFDDBELL_RIS2_SYSTIM2_M 0x80000000U -#define LRFDDBELL_RIS2_SYSTIM2_S 31U -#define LRFDDBELL_RIS2_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_RIS2_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_SYSTIM1 0x40000000U -#define LRFDDBELL_RIS2_SYSTIM1_M 0x40000000U -#define LRFDDBELL_RIS2_SYSTIM1_S 30U -#define LRFDDBELL_RIS2_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_RIS2_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_SYSTIM0 0x20000000U -#define LRFDDBELL_RIS2_SYSTIM0_M 0x20000000U -#define LRFDDBELL_RIS2_SYSTIM0_S 29U -#define LRFDDBELL_RIS2_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_RIS2_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMDONE 0x10000000U -#define LRFDDBELL_RIS2_MDMDONE_M 0x10000000U -#define LRFDDBELL_RIS2_MDMDONE_S 28U -#define LRFDDBELL_RIS2_MDMDONE_SET 0x10000000U -#define LRFDDBELL_RIS2_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMIN 0x08000000U -#define LRFDDBELL_RIS2_MDMIN_M 0x08000000U -#define LRFDDBELL_RIS2_MDMIN_S 27U -#define LRFDDBELL_RIS2_MDMIN_SET 0x08000000U -#define LRFDDBELL_RIS2_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMOUT 0x04000000U -#define LRFDDBELL_RIS2_MDMOUT_M 0x04000000U -#define LRFDDBELL_RIS2_MDMOUT_S 26U -#define LRFDDBELL_RIS2_MDMOUT_SET 0x04000000U -#define LRFDDBELL_RIS2_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMSOFT2 0x02000000U -#define LRFDDBELL_RIS2_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_RIS2_MDMSOFT2_S 25U -#define LRFDDBELL_RIS2_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_RIS2_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMSOFT1 0x01000000U -#define LRFDDBELL_RIS2_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_RIS2_MDMSOFT1_S 24U -#define LRFDDBELL_RIS2_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_RIS2_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_MDMSOFT0 0x00800000U -#define LRFDDBELL_RIS2_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_RIS2_MDMSOFT0_S 23U -#define LRFDDBELL_RIS2_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_RIS2_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_RFEDONE 0x00400000U -#define LRFDDBELL_RIS2_RFEDONE_M 0x00400000U -#define LRFDDBELL_RIS2_RFEDONE_S 22U -#define LRFDDBELL_RIS2_RFEDONE_SET 0x00400000U -#define LRFDDBELL_RIS2_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_RFESOFT1 0x00200000U -#define LRFDDBELL_RIS2_RFESOFT1_M 0x00200000U -#define LRFDDBELL_RIS2_RFESOFT1_S 21U -#define LRFDDBELL_RIS2_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_RIS2_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_RFESOFT0 0x00100000U -#define LRFDDBELL_RIS2_RFESOFT0_M 0x00100000U -#define LRFDDBELL_RIS2_RFESOFT0_S 20U -#define LRFDDBELL_RIS2_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_RIS2_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_LOCK 0x00080000U -#define LRFDDBELL_RIS2_LOCK_M 0x00080000U -#define LRFDDBELL_RIS2_LOCK_S 19U -#define LRFDDBELL_RIS2_LOCK_SET 0x00080000U -#define LRFDDBELL_RIS2_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_LOL 0x00040000U -#define LRFDDBELL_RIS2_LOL_M 0x00040000U -#define LRFDDBELL_RIS2_LOL_S 18U -#define LRFDDBELL_RIS2_LOL_SET 0x00040000U -#define LRFDDBELL_RIS2_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_TXFIFO 0x00020000U -#define LRFDDBELL_RIS2_TXFIFO_M 0x00020000U -#define LRFDDBELL_RIS2_TXFIFO_S 17U -#define LRFDDBELL_RIS2_TXFIFO_SET 0x00020000U -#define LRFDDBELL_RIS2_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_RXFIFO 0x00010000U -#define LRFDDBELL_RIS2_RXFIFO_M 0x00010000U -#define LRFDDBELL_RIS2_RXFIFO_S 16U -#define LRFDDBELL_RIS2_RXFIFO_SET 0x00010000U -#define LRFDDBELL_RIS2_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE15 0x00008000U -#define LRFDDBELL_RIS2_PBE15_M 0x00008000U -#define LRFDDBELL_RIS2_PBE15_S 15U -#define LRFDDBELL_RIS2_PBE15_SET 0x00008000U -#define LRFDDBELL_RIS2_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE14 0x00004000U -#define LRFDDBELL_RIS2_PBE14_M 0x00004000U -#define LRFDDBELL_RIS2_PBE14_S 14U -#define LRFDDBELL_RIS2_PBE14_SET 0x00004000U -#define LRFDDBELL_RIS2_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE13 0x00002000U -#define LRFDDBELL_RIS2_PBE13_M 0x00002000U -#define LRFDDBELL_RIS2_PBE13_S 13U -#define LRFDDBELL_RIS2_PBE13_SET 0x00002000U -#define LRFDDBELL_RIS2_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE12 0x00001000U -#define LRFDDBELL_RIS2_PBE12_M 0x00001000U -#define LRFDDBELL_RIS2_PBE12_S 12U -#define LRFDDBELL_RIS2_PBE12_SET 0x00001000U -#define LRFDDBELL_RIS2_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE11 0x00000800U -#define LRFDDBELL_RIS2_PBE11_M 0x00000800U -#define LRFDDBELL_RIS2_PBE11_S 11U -#define LRFDDBELL_RIS2_PBE11_SET 0x00000800U -#define LRFDDBELL_RIS2_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE10 0x00000400U -#define LRFDDBELL_RIS2_PBE10_M 0x00000400U -#define LRFDDBELL_RIS2_PBE10_S 10U -#define LRFDDBELL_RIS2_PBE10_SET 0x00000400U -#define LRFDDBELL_RIS2_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE9 0x00000200U -#define LRFDDBELL_RIS2_PBE9_M 0x00000200U -#define LRFDDBELL_RIS2_PBE9_S 9U -#define LRFDDBELL_RIS2_PBE9_SET 0x00000200U -#define LRFDDBELL_RIS2_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE8 0x00000100U -#define LRFDDBELL_RIS2_PBE8_M 0x00000100U -#define LRFDDBELL_RIS2_PBE8_S 8U -#define LRFDDBELL_RIS2_PBE8_SET 0x00000100U -#define LRFDDBELL_RIS2_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE7 0x00000080U -#define LRFDDBELL_RIS2_PBE7_M 0x00000080U -#define LRFDDBELL_RIS2_PBE7_S 7U -#define LRFDDBELL_RIS2_PBE7_SET 0x00000080U -#define LRFDDBELL_RIS2_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE6 0x00000040U -#define LRFDDBELL_RIS2_PBE6_M 0x00000040U -#define LRFDDBELL_RIS2_PBE6_S 6U -#define LRFDDBELL_RIS2_PBE6_SET 0x00000040U -#define LRFDDBELL_RIS2_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE5 0x00000020U -#define LRFDDBELL_RIS2_PBE5_M 0x00000020U -#define LRFDDBELL_RIS2_PBE5_S 5U -#define LRFDDBELL_RIS2_PBE5_SET 0x00000020U -#define LRFDDBELL_RIS2_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE4 0x00000010U -#define LRFDDBELL_RIS2_PBE4_M 0x00000010U -#define LRFDDBELL_RIS2_PBE4_S 4U -#define LRFDDBELL_RIS2_PBE4_SET 0x00000010U -#define LRFDDBELL_RIS2_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE3 0x00000008U -#define LRFDDBELL_RIS2_PBE3_M 0x00000008U -#define LRFDDBELL_RIS2_PBE3_S 3U -#define LRFDDBELL_RIS2_PBE3_SET 0x00000008U -#define LRFDDBELL_RIS2_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE2 0x00000004U -#define LRFDDBELL_RIS2_PBE2_M 0x00000004U -#define LRFDDBELL_RIS2_PBE2_S 2U -#define LRFDDBELL_RIS2_PBE2_SET 0x00000004U -#define LRFDDBELL_RIS2_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE1 0x00000002U -#define LRFDDBELL_RIS2_PBE1_M 0x00000002U -#define LRFDDBELL_RIS2_PBE1_S 1U -#define LRFDDBELL_RIS2_PBE1_SET 0x00000002U -#define LRFDDBELL_RIS2_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_RIS2_PBE0 0x00000001U -#define LRFDDBELL_RIS2_PBE0_M 0x00000001U -#define LRFDDBELL_RIS2_PBE0_S 0U -#define LRFDDBELL_RIS2_PBE0_SET 0x00000001U -#define LRFDDBELL_RIS2_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_MIS2 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_SYSTIM2 0x80000000U -#define LRFDDBELL_MIS2_SYSTIM2_M 0x80000000U -#define LRFDDBELL_MIS2_SYSTIM2_S 31U -#define LRFDDBELL_MIS2_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_MIS2_SYSTIM2_CLR 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_SYSTIM1 0x40000000U -#define LRFDDBELL_MIS2_SYSTIM1_M 0x40000000U -#define LRFDDBELL_MIS2_SYSTIM1_S 30U -#define LRFDDBELL_MIS2_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_MIS2_SYSTIM1_CLR 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_SYSTIM0 0x20000000U -#define LRFDDBELL_MIS2_SYSTIM0_M 0x20000000U -#define LRFDDBELL_MIS2_SYSTIM0_S 29U -#define LRFDDBELL_MIS2_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_MIS2_SYSTIM0_CLR 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMDONE 0x10000000U -#define LRFDDBELL_MIS2_MDMDONE_M 0x10000000U -#define LRFDDBELL_MIS2_MDMDONE_S 28U -#define LRFDDBELL_MIS2_MDMDONE_SET 0x10000000U -#define LRFDDBELL_MIS2_MDMDONE_CLR 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMIN 0x08000000U -#define LRFDDBELL_MIS2_MDMIN_M 0x08000000U -#define LRFDDBELL_MIS2_MDMIN_S 27U -#define LRFDDBELL_MIS2_MDMIN_SET 0x08000000U -#define LRFDDBELL_MIS2_MDMIN_CLR 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMOUT 0x04000000U -#define LRFDDBELL_MIS2_MDMOUT_M 0x04000000U -#define LRFDDBELL_MIS2_MDMOUT_S 26U -#define LRFDDBELL_MIS2_MDMOUT_SET 0x04000000U -#define LRFDDBELL_MIS2_MDMOUT_CLR 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMSOFT2 0x02000000U -#define LRFDDBELL_MIS2_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_MIS2_MDMSOFT2_S 25U -#define LRFDDBELL_MIS2_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_MIS2_MDMSOFT2_CLR 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMSOFT1 0x01000000U -#define LRFDDBELL_MIS2_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_MIS2_MDMSOFT1_S 24U -#define LRFDDBELL_MIS2_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_MIS2_MDMSOFT1_CLR 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_MDMSOFT0 0x00800000U -#define LRFDDBELL_MIS2_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_MIS2_MDMSOFT0_S 23U -#define LRFDDBELL_MIS2_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_MIS2_MDMSOFT0_CLR 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_RFEDONE 0x00400000U -#define LRFDDBELL_MIS2_RFEDONE_M 0x00400000U -#define LRFDDBELL_MIS2_RFEDONE_S 22U -#define LRFDDBELL_MIS2_RFEDONE_SET 0x00400000U -#define LRFDDBELL_MIS2_RFEDONE_CLR 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_RFESOFT1 0x00200000U -#define LRFDDBELL_MIS2_RFESOFT1_M 0x00200000U -#define LRFDDBELL_MIS2_RFESOFT1_S 21U -#define LRFDDBELL_MIS2_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_MIS2_RFESOFT1_CLR 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_RFESOFT0 0x00100000U -#define LRFDDBELL_MIS2_RFESOFT0_M 0x00100000U -#define LRFDDBELL_MIS2_RFESOFT0_S 20U -#define LRFDDBELL_MIS2_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_MIS2_RFESOFT0_CLR 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_LOCK 0x00080000U -#define LRFDDBELL_MIS2_LOCK_M 0x00080000U -#define LRFDDBELL_MIS2_LOCK_S 19U -#define LRFDDBELL_MIS2_LOCK_SET 0x00080000U -#define LRFDDBELL_MIS2_LOCK_CLR 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_LOL 0x00040000U -#define LRFDDBELL_MIS2_LOL_M 0x00040000U -#define LRFDDBELL_MIS2_LOL_S 18U -#define LRFDDBELL_MIS2_LOL_SET 0x00040000U -#define LRFDDBELL_MIS2_LOL_CLR 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_TXFIFO 0x00020000U -#define LRFDDBELL_MIS2_TXFIFO_M 0x00020000U -#define LRFDDBELL_MIS2_TXFIFO_S 17U -#define LRFDDBELL_MIS2_TXFIFO_SET 0x00020000U -#define LRFDDBELL_MIS2_TXFIFO_CLR 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_RXFIFO 0x00010000U -#define LRFDDBELL_MIS2_RXFIFO_M 0x00010000U -#define LRFDDBELL_MIS2_RXFIFO_S 16U -#define LRFDDBELL_MIS2_RXFIFO_SET 0x00010000U -#define LRFDDBELL_MIS2_RXFIFO_CLR 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE15 0x00008000U -#define LRFDDBELL_MIS2_PBE15_M 0x00008000U -#define LRFDDBELL_MIS2_PBE15_S 15U -#define LRFDDBELL_MIS2_PBE15_SET 0x00008000U -#define LRFDDBELL_MIS2_PBE15_CLR 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE14 0x00004000U -#define LRFDDBELL_MIS2_PBE14_M 0x00004000U -#define LRFDDBELL_MIS2_PBE14_S 14U -#define LRFDDBELL_MIS2_PBE14_SET 0x00004000U -#define LRFDDBELL_MIS2_PBE14_CLR 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE13 0x00002000U -#define LRFDDBELL_MIS2_PBE13_M 0x00002000U -#define LRFDDBELL_MIS2_PBE13_S 13U -#define LRFDDBELL_MIS2_PBE13_SET 0x00002000U -#define LRFDDBELL_MIS2_PBE13_CLR 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE12 0x00001000U -#define LRFDDBELL_MIS2_PBE12_M 0x00001000U -#define LRFDDBELL_MIS2_PBE12_S 12U -#define LRFDDBELL_MIS2_PBE12_SET 0x00001000U -#define LRFDDBELL_MIS2_PBE12_CLR 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE11 0x00000800U -#define LRFDDBELL_MIS2_PBE11_M 0x00000800U -#define LRFDDBELL_MIS2_PBE11_S 11U -#define LRFDDBELL_MIS2_PBE11_SET 0x00000800U -#define LRFDDBELL_MIS2_PBE11_CLR 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE10 0x00000400U -#define LRFDDBELL_MIS2_PBE10_M 0x00000400U -#define LRFDDBELL_MIS2_PBE10_S 10U -#define LRFDDBELL_MIS2_PBE10_SET 0x00000400U -#define LRFDDBELL_MIS2_PBE10_CLR 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE9 0x00000200U -#define LRFDDBELL_MIS2_PBE9_M 0x00000200U -#define LRFDDBELL_MIS2_PBE9_S 9U -#define LRFDDBELL_MIS2_PBE9_SET 0x00000200U -#define LRFDDBELL_MIS2_PBE9_CLR 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE8 0x00000100U -#define LRFDDBELL_MIS2_PBE8_M 0x00000100U -#define LRFDDBELL_MIS2_PBE8_S 8U -#define LRFDDBELL_MIS2_PBE8_SET 0x00000100U -#define LRFDDBELL_MIS2_PBE8_CLR 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE7 0x00000080U -#define LRFDDBELL_MIS2_PBE7_M 0x00000080U -#define LRFDDBELL_MIS2_PBE7_S 7U -#define LRFDDBELL_MIS2_PBE7_SET 0x00000080U -#define LRFDDBELL_MIS2_PBE7_CLR 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE6 0x00000040U -#define LRFDDBELL_MIS2_PBE6_M 0x00000040U -#define LRFDDBELL_MIS2_PBE6_S 6U -#define LRFDDBELL_MIS2_PBE6_SET 0x00000040U -#define LRFDDBELL_MIS2_PBE6_CLR 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE5 0x00000020U -#define LRFDDBELL_MIS2_PBE5_M 0x00000020U -#define LRFDDBELL_MIS2_PBE5_S 5U -#define LRFDDBELL_MIS2_PBE5_SET 0x00000020U -#define LRFDDBELL_MIS2_PBE5_CLR 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE4 0x00000010U -#define LRFDDBELL_MIS2_PBE4_M 0x00000010U -#define LRFDDBELL_MIS2_PBE4_S 4U -#define LRFDDBELL_MIS2_PBE4_SET 0x00000010U -#define LRFDDBELL_MIS2_PBE4_CLR 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE3 0x00000008U -#define LRFDDBELL_MIS2_PBE3_M 0x00000008U -#define LRFDDBELL_MIS2_PBE3_S 3U -#define LRFDDBELL_MIS2_PBE3_SET 0x00000008U -#define LRFDDBELL_MIS2_PBE3_CLR 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE2 0x00000004U -#define LRFDDBELL_MIS2_PBE2_M 0x00000004U -#define LRFDDBELL_MIS2_PBE2_S 2U -#define LRFDDBELL_MIS2_PBE2_SET 0x00000004U -#define LRFDDBELL_MIS2_PBE2_CLR 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE1 0x00000002U -#define LRFDDBELL_MIS2_PBE1_M 0x00000002U -#define LRFDDBELL_MIS2_PBE1_S 1U -#define LRFDDBELL_MIS2_PBE1_SET 0x00000002U -#define LRFDDBELL_MIS2_PBE1_CLR 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Interrupt occurred -// CLR Interrupt did not occur -#define LRFDDBELL_MIS2_PBE0 0x00000001U -#define LRFDDBELL_MIS2_PBE0_M 0x00000001U -#define LRFDDBELL_MIS2_PBE0_S 0U -#define LRFDDBELL_MIS2_PBE0_SET 0x00000001U -#define LRFDDBELL_MIS2_PBE0_CLR 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ISET2 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_SYSTIM2 0x80000000U -#define LRFDDBELL_ISET2_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ISET2_SYSTIM2_S 31U -#define LRFDDBELL_ISET2_SYSTIM2_SET 0x80000000U -#define LRFDDBELL_ISET2_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_SYSTIM1 0x40000000U -#define LRFDDBELL_ISET2_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ISET2_SYSTIM1_S 30U -#define LRFDDBELL_ISET2_SYSTIM1_SET 0x40000000U -#define LRFDDBELL_ISET2_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_SYSTIM0 0x20000000U -#define LRFDDBELL_ISET2_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ISET2_SYSTIM0_S 29U -#define LRFDDBELL_ISET2_SYSTIM0_SET 0x20000000U -#define LRFDDBELL_ISET2_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMDONE 0x10000000U -#define LRFDDBELL_ISET2_MDMDONE_M 0x10000000U -#define LRFDDBELL_ISET2_MDMDONE_S 28U -#define LRFDDBELL_ISET2_MDMDONE_SET 0x10000000U -#define LRFDDBELL_ISET2_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMIN 0x08000000U -#define LRFDDBELL_ISET2_MDMIN_M 0x08000000U -#define LRFDDBELL_ISET2_MDMIN_S 27U -#define LRFDDBELL_ISET2_MDMIN_SET 0x08000000U -#define LRFDDBELL_ISET2_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMOUT 0x04000000U -#define LRFDDBELL_ISET2_MDMOUT_M 0x04000000U -#define LRFDDBELL_ISET2_MDMOUT_S 26U -#define LRFDDBELL_ISET2_MDMOUT_SET 0x04000000U -#define LRFDDBELL_ISET2_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMSOFT2 0x02000000U -#define LRFDDBELL_ISET2_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ISET2_MDMSOFT2_S 25U -#define LRFDDBELL_ISET2_MDMSOFT2_SET 0x02000000U -#define LRFDDBELL_ISET2_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMSOFT1 0x01000000U -#define LRFDDBELL_ISET2_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ISET2_MDMSOFT1_S 24U -#define LRFDDBELL_ISET2_MDMSOFT1_SET 0x01000000U -#define LRFDDBELL_ISET2_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_MDMSOFT0 0x00800000U -#define LRFDDBELL_ISET2_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ISET2_MDMSOFT0_S 23U -#define LRFDDBELL_ISET2_MDMSOFT0_SET 0x00800000U -#define LRFDDBELL_ISET2_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_RFEDONE 0x00400000U -#define LRFDDBELL_ISET2_RFEDONE_M 0x00400000U -#define LRFDDBELL_ISET2_RFEDONE_S 22U -#define LRFDDBELL_ISET2_RFEDONE_SET 0x00400000U -#define LRFDDBELL_ISET2_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_RFESOFT1 0x00200000U -#define LRFDDBELL_ISET2_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ISET2_RFESOFT1_S 21U -#define LRFDDBELL_ISET2_RFESOFT1_SET 0x00200000U -#define LRFDDBELL_ISET2_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_RFESOFT0 0x00100000U -#define LRFDDBELL_ISET2_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ISET2_RFESOFT0_S 20U -#define LRFDDBELL_ISET2_RFESOFT0_SET 0x00100000U -#define LRFDDBELL_ISET2_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_LOCK 0x00080000U -#define LRFDDBELL_ISET2_LOCK_M 0x00080000U -#define LRFDDBELL_ISET2_LOCK_S 19U -#define LRFDDBELL_ISET2_LOCK_SET 0x00080000U -#define LRFDDBELL_ISET2_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_LOL 0x00040000U -#define LRFDDBELL_ISET2_LOL_M 0x00040000U -#define LRFDDBELL_ISET2_LOL_S 18U -#define LRFDDBELL_ISET2_LOL_SET 0x00040000U -#define LRFDDBELL_ISET2_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_TXFIFO 0x00020000U -#define LRFDDBELL_ISET2_TXFIFO_M 0x00020000U -#define LRFDDBELL_ISET2_TXFIFO_S 17U -#define LRFDDBELL_ISET2_TXFIFO_SET 0x00020000U -#define LRFDDBELL_ISET2_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_RXFIFO 0x00010000U -#define LRFDDBELL_ISET2_RXFIFO_M 0x00010000U -#define LRFDDBELL_ISET2_RXFIFO_S 16U -#define LRFDDBELL_ISET2_RXFIFO_SET 0x00010000U -#define LRFDDBELL_ISET2_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE15 0x00008000U -#define LRFDDBELL_ISET2_PBE15_M 0x00008000U -#define LRFDDBELL_ISET2_PBE15_S 15U -#define LRFDDBELL_ISET2_PBE15_SET 0x00008000U -#define LRFDDBELL_ISET2_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE14 0x00004000U -#define LRFDDBELL_ISET2_PBE14_M 0x00004000U -#define LRFDDBELL_ISET2_PBE14_S 14U -#define LRFDDBELL_ISET2_PBE14_SET 0x00004000U -#define LRFDDBELL_ISET2_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE13 0x00002000U -#define LRFDDBELL_ISET2_PBE13_M 0x00002000U -#define LRFDDBELL_ISET2_PBE13_S 13U -#define LRFDDBELL_ISET2_PBE13_SET 0x00002000U -#define LRFDDBELL_ISET2_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE12 0x00001000U -#define LRFDDBELL_ISET2_PBE12_M 0x00001000U -#define LRFDDBELL_ISET2_PBE12_S 12U -#define LRFDDBELL_ISET2_PBE12_SET 0x00001000U -#define LRFDDBELL_ISET2_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE11 0x00000800U -#define LRFDDBELL_ISET2_PBE11_M 0x00000800U -#define LRFDDBELL_ISET2_PBE11_S 11U -#define LRFDDBELL_ISET2_PBE11_SET 0x00000800U -#define LRFDDBELL_ISET2_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE10 0x00000400U -#define LRFDDBELL_ISET2_PBE10_M 0x00000400U -#define LRFDDBELL_ISET2_PBE10_S 10U -#define LRFDDBELL_ISET2_PBE10_SET 0x00000400U -#define LRFDDBELL_ISET2_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE9 0x00000200U -#define LRFDDBELL_ISET2_PBE9_M 0x00000200U -#define LRFDDBELL_ISET2_PBE9_S 9U -#define LRFDDBELL_ISET2_PBE9_SET 0x00000200U -#define LRFDDBELL_ISET2_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE8 0x00000100U -#define LRFDDBELL_ISET2_PBE8_M 0x00000100U -#define LRFDDBELL_ISET2_PBE8_S 8U -#define LRFDDBELL_ISET2_PBE8_SET 0x00000100U -#define LRFDDBELL_ISET2_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE7 0x00000080U -#define LRFDDBELL_ISET2_PBE7_M 0x00000080U -#define LRFDDBELL_ISET2_PBE7_S 7U -#define LRFDDBELL_ISET2_PBE7_SET 0x00000080U -#define LRFDDBELL_ISET2_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE6 0x00000040U -#define LRFDDBELL_ISET2_PBE6_M 0x00000040U -#define LRFDDBELL_ISET2_PBE6_S 6U -#define LRFDDBELL_ISET2_PBE6_SET 0x00000040U -#define LRFDDBELL_ISET2_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE5 0x00000020U -#define LRFDDBELL_ISET2_PBE5_M 0x00000020U -#define LRFDDBELL_ISET2_PBE5_S 5U -#define LRFDDBELL_ISET2_PBE5_SET 0x00000020U -#define LRFDDBELL_ISET2_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE4 0x00000010U -#define LRFDDBELL_ISET2_PBE4_M 0x00000010U -#define LRFDDBELL_ISET2_PBE4_S 4U -#define LRFDDBELL_ISET2_PBE4_SET 0x00000010U -#define LRFDDBELL_ISET2_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE3 0x00000008U -#define LRFDDBELL_ISET2_PBE3_M 0x00000008U -#define LRFDDBELL_ISET2_PBE3_S 3U -#define LRFDDBELL_ISET2_PBE3_SET 0x00000008U -#define LRFDDBELL_ISET2_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE2 0x00000004U -#define LRFDDBELL_ISET2_PBE2_M 0x00000004U -#define LRFDDBELL_ISET2_PBE2_S 2U -#define LRFDDBELL_ISET2_PBE2_SET 0x00000004U -#define LRFDDBELL_ISET2_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE1 0x00000002U -#define LRFDDBELL_ISET2_PBE1_M 0x00000002U -#define LRFDDBELL_ISET2_PBE1_S 1U -#define LRFDDBELL_ISET2_PBE1_SET 0x00000002U -#define LRFDDBELL_ISET2_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// SET Set Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ISET2_PBE0 0x00000001U -#define LRFDDBELL_ISET2_PBE0_M 0x00000001U -#define LRFDDBELL_ISET2_PBE0_S 0U -#define LRFDDBELL_ISET2_PBE0_SET 0x00000001U -#define LRFDDBELL_ISET2_PBE0_NOEFF 0x00000000U - -//***************************************************************************** -// -// Register: LRFDDBELL_O_ICLR2 -// -//***************************************************************************** -// Field: [31] SYSTIM2 -// -// SYSTIM2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_SYSTIM2 0x80000000U -#define LRFDDBELL_ICLR2_SYSTIM2_M 0x80000000U -#define LRFDDBELL_ICLR2_SYSTIM2_S 31U -#define LRFDDBELL_ICLR2_SYSTIM2_CLR 0x80000000U -#define LRFDDBELL_ICLR2_SYSTIM2_NOEFF 0x00000000U - -// Field: [30] SYSTIM1 -// -// SYSTIM1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_SYSTIM1 0x40000000U -#define LRFDDBELL_ICLR2_SYSTIM1_M 0x40000000U -#define LRFDDBELL_ICLR2_SYSTIM1_S 30U -#define LRFDDBELL_ICLR2_SYSTIM1_CLR 0x40000000U -#define LRFDDBELL_ICLR2_SYSTIM1_NOEFF 0x00000000U - -// Field: [29] SYSTIM0 -// -// SYSTIM0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_SYSTIM0 0x20000000U -#define LRFDDBELL_ICLR2_SYSTIM0_M 0x20000000U -#define LRFDDBELL_ICLR2_SYSTIM0_S 29U -#define LRFDDBELL_ICLR2_SYSTIM0_CLR 0x20000000U -#define LRFDDBELL_ICLR2_SYSTIM0_NOEFF 0x00000000U - -// Field: [28] MDMDONE -// -// MDMDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMDONE 0x10000000U -#define LRFDDBELL_ICLR2_MDMDONE_M 0x10000000U -#define LRFDDBELL_ICLR2_MDMDONE_S 28U -#define LRFDDBELL_ICLR2_MDMDONE_CLR 0x10000000U -#define LRFDDBELL_ICLR2_MDMDONE_NOEFF 0x00000000U - -// Field: [27] MDMIN -// -// MDMIN event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMIN 0x08000000U -#define LRFDDBELL_ICLR2_MDMIN_M 0x08000000U -#define LRFDDBELL_ICLR2_MDMIN_S 27U -#define LRFDDBELL_ICLR2_MDMIN_CLR 0x08000000U -#define LRFDDBELL_ICLR2_MDMIN_NOEFF 0x00000000U - -// Field: [26] MDMOUT -// -// MDMOUT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMOUT 0x04000000U -#define LRFDDBELL_ICLR2_MDMOUT_M 0x04000000U -#define LRFDDBELL_ICLR2_MDMOUT_S 26U -#define LRFDDBELL_ICLR2_MDMOUT_CLR 0x04000000U -#define LRFDDBELL_ICLR2_MDMOUT_NOEFF 0x00000000U - -// Field: [25] MDMSOFT2 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMSOFT2 0x02000000U -#define LRFDDBELL_ICLR2_MDMSOFT2_M 0x02000000U -#define LRFDDBELL_ICLR2_MDMSOFT2_S 25U -#define LRFDDBELL_ICLR2_MDMSOFT2_CLR 0x02000000U -#define LRFDDBELL_ICLR2_MDMSOFT2_NOEFF 0x00000000U - -// Field: [24] MDMSOFT1 -// -// MDMSOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMSOFT1 0x01000000U -#define LRFDDBELL_ICLR2_MDMSOFT1_M 0x01000000U -#define LRFDDBELL_ICLR2_MDMSOFT1_S 24U -#define LRFDDBELL_ICLR2_MDMSOFT1_CLR 0x01000000U -#define LRFDDBELL_ICLR2_MDMSOFT1_NOEFF 0x00000000U - -// Field: [23] MDMSOFT0 -// -// MDMSOFT event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_MDMSOFT0 0x00800000U -#define LRFDDBELL_ICLR2_MDMSOFT0_M 0x00800000U -#define LRFDDBELL_ICLR2_MDMSOFT0_S 23U -#define LRFDDBELL_ICLR2_MDMSOFT0_CLR 0x00800000U -#define LRFDDBELL_ICLR2_MDMSOFT0_NOEFF 0x00000000U - -// Field: [22] RFEDONE -// -// RFEDONE event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_RFEDONE 0x00400000U -#define LRFDDBELL_ICLR2_RFEDONE_M 0x00400000U -#define LRFDDBELL_ICLR2_RFEDONE_S 22U -#define LRFDDBELL_ICLR2_RFEDONE_CLR 0x00400000U -#define LRFDDBELL_ICLR2_RFEDONE_NOEFF 0x00000000U - -// Field: [21] RFESOFT1 -// -// RFESOFT1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_RFESOFT1 0x00200000U -#define LRFDDBELL_ICLR2_RFESOFT1_M 0x00200000U -#define LRFDDBELL_ICLR2_RFESOFT1_S 21U -#define LRFDDBELL_ICLR2_RFESOFT1_CLR 0x00200000U -#define LRFDDBELL_ICLR2_RFESOFT1_NOEFF 0x00000000U - -// Field: [20] RFESOFT0 -// -// RFESOFT0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_RFESOFT0 0x00100000U -#define LRFDDBELL_ICLR2_RFESOFT0_M 0x00100000U -#define LRFDDBELL_ICLR2_RFESOFT0_S 20U -#define LRFDDBELL_ICLR2_RFESOFT0_CLR 0x00100000U -#define LRFDDBELL_ICLR2_RFESOFT0_NOEFF 0x00000000U - -// Field: [19] LOCK -// -// LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_LOCK 0x00080000U -#define LRFDDBELL_ICLR2_LOCK_M 0x00080000U -#define LRFDDBELL_ICLR2_LOCK_S 19U -#define LRFDDBELL_ICLR2_LOCK_CLR 0x00080000U -#define LRFDDBELL_ICLR2_LOCK_NOEFF 0x00000000U - -// Field: [18] LOL -// -// LOSS_OF_LOCK event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_LOL 0x00040000U -#define LRFDDBELL_ICLR2_LOL_M 0x00040000U -#define LRFDDBELL_ICLR2_LOL_S 18U -#define LRFDDBELL_ICLR2_LOL_CLR 0x00040000U -#define LRFDDBELL_ICLR2_LOL_NOEFF 0x00000000U - -// Field: [17] TXFIFO -// -// TXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_TXFIFO 0x00020000U -#define LRFDDBELL_ICLR2_TXFIFO_M 0x00020000U -#define LRFDDBELL_ICLR2_TXFIFO_S 17U -#define LRFDDBELL_ICLR2_TXFIFO_CLR 0x00020000U -#define LRFDDBELL_ICLR2_TXFIFO_NOEFF 0x00000000U - -// Field: [16] RXFIFO -// -// RXFIFO event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_RXFIFO 0x00010000U -#define LRFDDBELL_ICLR2_RXFIFO_M 0x00010000U -#define LRFDDBELL_ICLR2_RXFIFO_S 16U -#define LRFDDBELL_ICLR2_RXFIFO_CLR 0x00010000U -#define LRFDDBELL_ICLR2_RXFIFO_NOEFF 0x00000000U - -// Field: [15] PBE15 -// -// PBE15 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE15 0x00008000U -#define LRFDDBELL_ICLR2_PBE15_M 0x00008000U -#define LRFDDBELL_ICLR2_PBE15_S 15U -#define LRFDDBELL_ICLR2_PBE15_CLR 0x00008000U -#define LRFDDBELL_ICLR2_PBE15_NOEFF 0x00000000U - -// Field: [14] PBE14 -// -// PBE14 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE14 0x00004000U -#define LRFDDBELL_ICLR2_PBE14_M 0x00004000U -#define LRFDDBELL_ICLR2_PBE14_S 14U -#define LRFDDBELL_ICLR2_PBE14_CLR 0x00004000U -#define LRFDDBELL_ICLR2_PBE14_NOEFF 0x00000000U - -// Field: [13] PBE13 -// -// PBE13 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE13 0x00002000U -#define LRFDDBELL_ICLR2_PBE13_M 0x00002000U -#define LRFDDBELL_ICLR2_PBE13_S 13U -#define LRFDDBELL_ICLR2_PBE13_CLR 0x00002000U -#define LRFDDBELL_ICLR2_PBE13_NOEFF 0x00000000U - -// Field: [12] PBE12 -// -// PBE12 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE12 0x00001000U -#define LRFDDBELL_ICLR2_PBE12_M 0x00001000U -#define LRFDDBELL_ICLR2_PBE12_S 12U -#define LRFDDBELL_ICLR2_PBE12_CLR 0x00001000U -#define LRFDDBELL_ICLR2_PBE12_NOEFF 0x00000000U - -// Field: [11] PBE11 -// -// PBE11 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE11 0x00000800U -#define LRFDDBELL_ICLR2_PBE11_M 0x00000800U -#define LRFDDBELL_ICLR2_PBE11_S 11U -#define LRFDDBELL_ICLR2_PBE11_CLR 0x00000800U -#define LRFDDBELL_ICLR2_PBE11_NOEFF 0x00000000U - -// Field: [10] PBE10 -// -// PBE10 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE10 0x00000400U -#define LRFDDBELL_ICLR2_PBE10_M 0x00000400U -#define LRFDDBELL_ICLR2_PBE10_S 10U -#define LRFDDBELL_ICLR2_PBE10_CLR 0x00000400U -#define LRFDDBELL_ICLR2_PBE10_NOEFF 0x00000000U - -// Field: [9] PBE9 -// -// PBE9 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE9 0x00000200U -#define LRFDDBELL_ICLR2_PBE9_M 0x00000200U -#define LRFDDBELL_ICLR2_PBE9_S 9U -#define LRFDDBELL_ICLR2_PBE9_CLR 0x00000200U -#define LRFDDBELL_ICLR2_PBE9_NOEFF 0x00000000U - -// Field: [8] PBE8 -// -// PBE8 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE8 0x00000100U -#define LRFDDBELL_ICLR2_PBE8_M 0x00000100U -#define LRFDDBELL_ICLR2_PBE8_S 8U -#define LRFDDBELL_ICLR2_PBE8_CLR 0x00000100U -#define LRFDDBELL_ICLR2_PBE8_NOEFF 0x00000000U - -// Field: [7] PBE7 -// -// PBE7 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE7 0x00000080U -#define LRFDDBELL_ICLR2_PBE7_M 0x00000080U -#define LRFDDBELL_ICLR2_PBE7_S 7U -#define LRFDDBELL_ICLR2_PBE7_CLR 0x00000080U -#define LRFDDBELL_ICLR2_PBE7_NOEFF 0x00000000U - -// Field: [6] PBE6 -// -// PBE6 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE6 0x00000040U -#define LRFDDBELL_ICLR2_PBE6_M 0x00000040U -#define LRFDDBELL_ICLR2_PBE6_S 6U -#define LRFDDBELL_ICLR2_PBE6_CLR 0x00000040U -#define LRFDDBELL_ICLR2_PBE6_NOEFF 0x00000000U - -// Field: [5] PBE5 -// -// PBE5 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE5 0x00000020U -#define LRFDDBELL_ICLR2_PBE5_M 0x00000020U -#define LRFDDBELL_ICLR2_PBE5_S 5U -#define LRFDDBELL_ICLR2_PBE5_CLR 0x00000020U -#define LRFDDBELL_ICLR2_PBE5_NOEFF 0x00000000U - -// Field: [4] PBE4 -// -// PBE4 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE4 0x00000010U -#define LRFDDBELL_ICLR2_PBE4_M 0x00000010U -#define LRFDDBELL_ICLR2_PBE4_S 4U -#define LRFDDBELL_ICLR2_PBE4_CLR 0x00000010U -#define LRFDDBELL_ICLR2_PBE4_NOEFF 0x00000000U - -// Field: [3] PBE3 -// -// PBE3 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE3 0x00000008U -#define LRFDDBELL_ICLR2_PBE3_M 0x00000008U -#define LRFDDBELL_ICLR2_PBE3_S 3U -#define LRFDDBELL_ICLR2_PBE3_CLR 0x00000008U -#define LRFDDBELL_ICLR2_PBE3_NOEFF 0x00000000U - -// Field: [2] PBE2 -// -// PBE2 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE2 0x00000004U -#define LRFDDBELL_ICLR2_PBE2_M 0x00000004U -#define LRFDDBELL_ICLR2_PBE2_S 2U -#define LRFDDBELL_ICLR2_PBE2_CLR 0x00000004U -#define LRFDDBELL_ICLR2_PBE2_NOEFF 0x00000000U - -// Field: [1] PBE1 -// -// PBE1 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE1 0x00000002U -#define LRFDDBELL_ICLR2_PBE1_M 0x00000002U -#define LRFDDBELL_ICLR2_PBE1_S 1U -#define LRFDDBELL_ICLR2_PBE1_CLR 0x00000002U -#define LRFDDBELL_ICLR2_PBE1_NOEFF 0x00000000U - -// Field: [0] PBE0 -// -// PBE0 event -// ENUMs: -// CLR Clear Interrupt -// NOEFF Writing 0 has no effect -#define LRFDDBELL_ICLR2_PBE0 0x00000001U -#define LRFDDBELL_ICLR2_PBE0_M 0x00000001U -#define LRFDDBELL_ICLR2_PBE0_S 0U -#define LRFDDBELL_ICLR2_PBE0_CLR 0x00000001U -#define LRFDDBELL_ICLR2_PBE0_NOEFF 0x00000000U - - -#endif // __LRFDDBELL__ +/****************************************************************************** +* Filename: hw_lrfddbell_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDDBELL_H__ +#define __HW_LRFDDBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDDBELL component +// +//***************************************************************************** +// Description +#define LRFDDBELL_O_DESC 0x00000000U + +// Clock control +#define LRFDDBELL_O_CLKCTL 0x00000004U + +// DMA Configuration +#define LRFDDBELL_O_DMACFG 0x00000008U + +// Systimer Output Event Control Register +#define LRFDDBELL_O_SYSTIMOEV 0x0000000CU + +// System DMA Trigger +#define LRFDDBELL_O_SYSTDMATRIG 0x00000010U + +// GPO control +#define LRFDDBELL_O_GPOSEL0 0x00000014U + +// GPO control +#define LRFDDBELL_O_GPOSEL1 0x00000018U + +// Interrupt mask +#define LRFDDBELL_O_IMASK0 0x00000044U + +// Raw interrupt status +#define LRFDDBELL_O_RIS0 0x00000048U + +// Masked interrupt status +#define LRFDDBELL_O_MIS0 0x0000004CU + +// Interrupt set +#define LRFDDBELL_O_ISET0 0x00000050U + +// Interrupt clear +#define LRFDDBELL_O_ICLR0 0x00000054U + +// Interrupt mask +#define LRFDDBELL_O_IMASK1 0x00000084U + +// Raw interrupt status +#define LRFDDBELL_O_RIS1 0x00000088U + +// Masked interrupt status +#define LRFDDBELL_O_MIS1 0x0000008CU + +// Interrupt set +#define LRFDDBELL_O_ISET1 0x00000090U + +// Interrupt clear +#define LRFDDBELL_O_ICLR1 0x00000094U + +// Interrupt mask +#define LRFDDBELL_O_IMASK2 0x000000C4U + +// Raw interrupt status +#define LRFDDBELL_O_RIS2 0x000000C8U + +// Masked interrupt status +#define LRFDDBELL_O_MIS2 0x000000CCU + +// Interrupt set +#define LRFDDBELL_O_ISET2 0x000000D0U + +// Interrupt clear +#define LRFDDBELL_O_ICLR2 0x000000D4U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_DESC +// +//***************************************************************************** +// Field: [31:16] MODULEID +// +// Module identifier used to uniquely identify this IP. +#define LRFDDBELL_DESC_MODULEID_W 16U +#define LRFDDBELL_DESC_MODULEID_M 0xFFFF0000U +#define LRFDDBELL_DESC_MODULEID_S 16U + +// Field: [15:12] STDIPOFF +// +// Standard IP MMR block offset. Standard IP MMRs are the set of from +// aggregated IRQ registers till DTB. +// ENUMs: +// STDIPMMR These MMRs begin at offset 64*STDIPOFF from IP +// base address +// NO_STDIPMMR STDIP MMRs do not exist +#define LRFDDBELL_DESC_STDIPOFF_W 4U +#define LRFDDBELL_DESC_STDIPOFF_M 0x0000F000U +#define LRFDDBELL_DESC_STDIPOFF_S 12U +#define LRFDDBELL_DESC_STDIPOFF_STDIPMMR 0x00001000U +#define LRFDDBELL_DESC_STDIPOFF_NO_STDIPMMR 0x00000000U + +// Field: [11:8] INSTNUM +// +// IP Instance Number. If multiple instances of IP exist in the device, this +// field can identify the instance number +#define LRFDDBELL_DESC_INSTNUM_W 4U +#define LRFDDBELL_DESC_INSTNUM_M 0x00000F00U +#define LRFDDBELL_DESC_INSTNUM_S 8U + +// Field: [7:4] MAJREV +// +// Major rev of the IP +#define LRFDDBELL_DESC_MAJREV_W 4U +#define LRFDDBELL_DESC_MAJREV_M 0x000000F0U +#define LRFDDBELL_DESC_MAJREV_S 4U + +// Field: [3:0] MINREV +// +// Minor rev of the IP +#define LRFDDBELL_DESC_MINREV_W 4U +#define LRFDDBELL_DESC_MINREV_M 0x0000000FU +#define LRFDDBELL_DESC_MINREV_S 0U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_CLKCTL +// +//***************************************************************************** +// Field: [13] DEM +// +// Enable the clock to the demodulator. The modem will request this clock +// automatically. This bit is to force the clock to be free running +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_DEM 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_M 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_S 13U +#define LRFDDBELL_CLKCTL_DEM_EN 0x00002000U +#define LRFDDBELL_CLKCTL_DEM_DIS 0x00000000U + +// Field: [12] MOD +// +// Enable the clock to the modulator. Modem will request this clock +// automatically, this bit is to force the modulator clock to be free running. +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MOD 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_M 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_S 12U +#define LRFDDBELL_CLKCTL_MOD_EN 0x00001000U +#define LRFDDBELL_CLKCTL_MOD_DIS 0x00000000U + +// Field: [11] S2RRAM +// +// Enable the clock to the S2R RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_S2RRAM 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_M 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_S 11U +#define LRFDDBELL_CLKCTL_S2RRAM_EN 0x00000800U +#define LRFDDBELL_CLKCTL_S2RRAM_DIS 0x00000000U + +// Field: [10] BUFRAM +// +// Enable the clock to the BUFRAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_BUFRAM 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_M 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_S 10U +#define LRFDDBELL_CLKCTL_BUFRAM_EN 0x00000400U +#define LRFDDBELL_CLKCTL_BUFRAM_DIS 0x00000000U + +// Field: [9] DSBRAM +// +// Enable the clock to the DSB RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_DSBRAM 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_M 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_S 9U +#define LRFDDBELL_CLKCTL_DSBRAM_EN 0x00000200U +#define LRFDDBELL_CLKCTL_DSBRAM_DIS 0x00000000U + +// Field: [8] RFERAM +// +// Enable the clock to the RFE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_RFERAM 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_M 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_S 8U +#define LRFDDBELL_CLKCTL_RFERAM_EN 0x00000100U +#define LRFDDBELL_CLKCTL_RFERAM_DIS 0x00000000U + +// Field: [7] MCERAM +// +// Enable the clock to the MCE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MCERAM 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_M 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_S 7U +#define LRFDDBELL_CLKCTL_MCERAM_EN 0x00000080U +#define LRFDDBELL_CLKCTL_MCERAM_DIS 0x00000000U + +// Field: [6] PBERAM +// +// Enable the clock to the PBE RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_PBERAM 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_M 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_S 6U +#define LRFDDBELL_CLKCTL_PBERAM_EN 0x00000040U +#define LRFDDBELL_CLKCTL_PBERAM_DIS 0x00000000U + +// Field: [5] TRC +// +// Enable the clock to the Tracer +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_TRC 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_M 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_S 5U +#define LRFDDBELL_CLKCTL_TRC_EN 0x00000020U +#define LRFDDBELL_CLKCTL_TRC_DIS 0x00000000U + +// Field: [4] S2R +// +// Enable the clock to Samples2RAM +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_S2R 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_M 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_S 4U +#define LRFDDBELL_CLKCTL_S2R_EN 0x00000010U +#define LRFDDBELL_CLKCTL_S2R_DIS 0x00000000U + +// Field: [3] RFE +// +// Enable the clock to the RFE +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_RFE 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_M 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_S 3U +#define LRFDDBELL_CLKCTL_RFE_EN 0x00000008U +#define LRFDDBELL_CLKCTL_RFE_DIS 0x00000000U + +// Field: [2] MDM +// +// Enable the clock to the Modem +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_MDM 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_M 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_S 2U +#define LRFDDBELL_CLKCTL_MDM_EN 0x00000004U +#define LRFDDBELL_CLKCTL_MDM_DIS 0x00000000U + +// Field: [1] PBE +// +// Enable the clock to the PBE +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_PBE 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_M 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_S 1U +#define LRFDDBELL_CLKCTL_PBE_EN 0x00000002U +#define LRFDDBELL_CLKCTL_PBE_DIS 0x00000000U + +// Field: [0] BRIDGE +// +// Clock enable to AHB bridge. The bridge will request it's own clock, this bit +// it to override that feature to have a free running clock. +// ENUMs: +// EN Clock is requested +// DIS Clock not requested +#define LRFDDBELL_CLKCTL_BRIDGE 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_M 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_S 0U +#define LRFDDBELL_CLKCTL_BRIDGE_EN 0x00000001U +#define LRFDDBELL_CLKCTL_BRIDGE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_DMACFG +// +//***************************************************************************** +// Field: [2:1] TRIGSRC +// +// Select DMA trigger source +// ENUMs: +// FIFO The DMA is triggered from the FIFO. See the FIFO +// configration register for what FIFO event will +// generate the trigger +// RFEFW The DMA is triggered by the MCE FW trigger +// MCEFW The DMA is triggered by the MCE FW trigger +// PBEFW The DMA is triggered by the PBE FW trigger +#define LRFDDBELL_DMACFG_TRIGSRC_W 2U +#define LRFDDBELL_DMACFG_TRIGSRC_M 0x00000006U +#define LRFDDBELL_DMACFG_TRIGSRC_S 1U +#define LRFDDBELL_DMACFG_TRIGSRC_FIFO 0x00000006U +#define LRFDDBELL_DMACFG_TRIGSRC_RFEFW 0x00000004U +#define LRFDDBELL_DMACFG_TRIGSRC_MCEFW 0x00000002U +#define LRFDDBELL_DMACFG_TRIGSRC_PBEFW 0x00000000U + +// Field: [0] EN +// +// Enables the DMA interface +// ENUMs: +// ON Enable DMA interface. The triggers are able to +// give activity on the interface +// OFF Disable DMA interface, no activity on interface +#define LRFDDBELL_DMACFG_EN 0x00000001U +#define LRFDDBELL_DMACFG_EN_M 0x00000001U +#define LRFDDBELL_DMACFG_EN_S 0U +#define LRFDDBELL_DMACFG_EN_ON 0x00000001U +#define LRFDDBELL_DMACFG_EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_SYSTIMOEV +// +//***************************************************************************** +// Field: [11:8] SRC2 +// +// Select source of systimer output event 2 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC2_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC2_M 0x00000F00U +#define LRFDDBELL_SYSTIMOEV_SRC2_S 8U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM2 0x00000C00U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM1 0x00000B00U +#define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM0 0x00000A00U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW2 0x00000900U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW1 0x00000800U +#define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW0 0x00000700U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM2 0x00000600U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM1 0x00000500U +#define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM0 0x00000400U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM2 0x00000300U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM1 0x00000200U +#define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM0 0x00000100U +#define LRFDDBELL_SYSTIMOEV_SRC2_DIS 0x00000000U + +// Field: [7:4] SRC1 +// +// Select source of systimer output event 1 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC1_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC1_M 0x000000F0U +#define LRFDDBELL_SYSTIMOEV_SRC1_S 4U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM2 0x000000C0U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM1 0x000000B0U +#define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM0 0x000000A0U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW2 0x00000090U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW1 0x00000080U +#define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW0 0x00000070U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM2 0x00000060U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM1 0x00000050U +#define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM0 0x00000040U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM2 0x00000030U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM1 0x00000020U +#define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM0 0x00000010U +#define LRFDDBELL_SYSTIMOEV_SRC1_DIS 0x00000000U + +// Field: [3:0] SRC0 +// +// Select source of systimer output event 0 (capture source) +// ENUMs: +// PBESYSTIM2 PBE FW systimer capture event 2 +// PBESYSTIM1 PBE FW systimer capture event 1 +// PBESYSTIM0 PBE FW systimer capture event 0 +// MDMHW2 MDM HW event 2 +// MDMHW1 MDM HW event 1 +// MDMHW0 MDM HW event 0 +// MCESYSTIM2 MCE FW systimer capture event 2 +// MCESYSTIM1 MCE FW systimer capture event 1 +// MCESYSTIM0 MCE FW systimer capture event 0 +// RFESYSTIM2 RFE FW systimer capture event 2 +// RFESYSTIM1 RFE FW systimer capture event 1 +// RFESYSTIM0 RFE FW systimer capture event 0 +// DIS Output not enabled, always 0. +#define LRFDDBELL_SYSTIMOEV_SRC0_W 4U +#define LRFDDBELL_SYSTIMOEV_SRC0_M 0x0000000FU +#define LRFDDBELL_SYSTIMOEV_SRC0_S 0U +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM2 0x0000000CU +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM1 0x0000000BU +#define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM0 0x0000000AU +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW2 0x00000009U +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW1 0x00000008U +#define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW0 0x00000007U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM2 0x00000006U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM1 0x00000005U +#define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM0 0x00000004U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM2 0x00000003U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM1 0x00000002U +#define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM0 0x00000001U +#define LRFDDBELL_SYSTIMOEV_SRC0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_SYSTDMATRIG +// +//***************************************************************************** +// Field: [3] DMA +// +// Trigger a DMA request from the Radio +// ENUMs: +// TRIG DMA request manually triggered +// NOTRIG DMA not manually triggered +#define LRFDDBELL_SYSTDMATRIG_DMA 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_M 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_S 3U +#define LRFDDBELL_SYSTDMATRIG_DMA_TRIG 0x00000008U +#define LRFDDBELL_SYSTDMATRIG_DMA_NOTRIG 0x00000000U + +// Field: [2] SYST2 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST2 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_M 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_S 2U +#define LRFDDBELL_SYSTDMATRIG_SYST2_TRIG 0x00000004U +#define LRFDDBELL_SYSTDMATRIG_SYST2_NOTRIG 0x00000000U + +// Field: [1] SYST1 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST1 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_M 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_S 1U +#define LRFDDBELL_SYSTDMATRIG_SYST1_TRIG 0x00000002U +#define LRFDDBELL_SYSTDMATRIG_SYST1_NOTRIG 0x00000000U + +// Field: [0] SYST0 +// +// Trigger a capture event on systimer event 0 from the radio +// ENUMs: +// TRIG Capture event triggered +// NOTRIG Not capture event triggered +#define LRFDDBELL_SYSTDMATRIG_SYST0 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_M 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_S 0U +#define LRFDDBELL_SYSTDMATRIG_SYST0_TRIG 0x00000001U +#define LRFDDBELL_SYSTDMATRIG_SYST0_NOTRIG 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_GPOSEL0 +// +//***************************************************************************** +// Field: [28:24] SRC3 +// +// Select source of radio GPO line 3 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 3 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC3_W 5U +#define LRFDDBELL_GPOSEL0_SRC3_M 0x1F000000U +#define LRFDDBELL_GPOSEL0_SRC3_S 24U +#define LRFDDBELL_GPOSEL0_SRC3_RFCTRC 0x19000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO7 0x18000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO6 0x17000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO5 0x16000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO4 0x15000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO3 0x14000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO2 0x13000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO1 0x12000000U +#define LRFDDBELL_GPOSEL0_SRC3_RFEGPO0 0x11000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO7 0x10000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO6 0x0F000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO5 0x0E000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO4 0x0D000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO3 0x0C000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO2 0x0B000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO1 0x0A000000U +#define LRFDDBELL_GPOSEL0_SRC3_MCEGPO0 0x09000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO7 0x08000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO6 0x07000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO5 0x06000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO4 0x05000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO3 0x04000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO2 0x03000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO1 0x02000000U +#define LRFDDBELL_GPOSEL0_SRC3_PBEGPO0 0x01000000U +#define LRFDDBELL_GPOSEL0_SRC3_DIS 0x00000000U + +// Field: [20:16] SRC2 +// +// Select source of radio GPO line 2 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 2 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC2_W 5U +#define LRFDDBELL_GPOSEL0_SRC2_M 0x001F0000U +#define LRFDDBELL_GPOSEL0_SRC2_S 16U +#define LRFDDBELL_GPOSEL0_SRC2_RFCTRC 0x00190000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO7 0x00180000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO6 0x00170000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO5 0x00160000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO4 0x00150000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO3 0x00140000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO2 0x00130000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO1 0x00120000U +#define LRFDDBELL_GPOSEL0_SRC2_RFEGPO0 0x00110000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO7 0x00100000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO6 0x000F0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO5 0x000E0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO4 0x000D0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO3 0x000C0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO2 0x000B0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO1 0x000A0000U +#define LRFDDBELL_GPOSEL0_SRC2_MCEGPO0 0x00090000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO7 0x00080000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO6 0x00070000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO5 0x00060000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO4 0x00050000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO3 0x00040000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO2 0x00030000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO1 0x00020000U +#define LRFDDBELL_GPOSEL0_SRC2_PBEGPO0 0x00010000U +#define LRFDDBELL_GPOSEL0_SRC2_DIS 0x00000000U + +// Field: [12:8] SRC1 +// +// Select source of radio GPO line 1 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 1 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC1_W 5U +#define LRFDDBELL_GPOSEL0_SRC1_M 0x00001F00U +#define LRFDDBELL_GPOSEL0_SRC1_S 8U +#define LRFDDBELL_GPOSEL0_SRC1_RFCTRC 0x00001900U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO7 0x00001800U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO6 0x00001700U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO5 0x00001600U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO4 0x00001500U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO3 0x00001400U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO2 0x00001300U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO1 0x00001200U +#define LRFDDBELL_GPOSEL0_SRC1_RFEGPO0 0x00001100U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO7 0x00001000U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO6 0x00000F00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO5 0x00000E00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO4 0x00000D00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO3 0x00000C00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO2 0x00000B00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO1 0x00000A00U +#define LRFDDBELL_GPOSEL0_SRC1_MCEGPO0 0x00000900U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO7 0x00000800U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO6 0x00000700U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO5 0x00000600U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO4 0x00000500U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO3 0x00000400U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO2 0x00000300U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO1 0x00000200U +#define LRFDDBELL_GPOSEL0_SRC1_PBEGPO0 0x00000100U +#define LRFDDBELL_GPOSEL0_SRC1_DIS 0x00000000U + +// Field: [4:0] SRC0 +// +// Select source of radio GPO line 0 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 0 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS Output not enabled +#define LRFDDBELL_GPOSEL0_SRC0_W 5U +#define LRFDDBELL_GPOSEL0_SRC0_M 0x0000001FU +#define LRFDDBELL_GPOSEL0_SRC0_S 0U +#define LRFDDBELL_GPOSEL0_SRC0_RFCTRC 0x00000019U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO7 0x00000018U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO6 0x00000017U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO5 0x00000016U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO4 0x00000015U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO3 0x00000014U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO2 0x00000013U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO1 0x00000012U +#define LRFDDBELL_GPOSEL0_SRC0_RFEGPO0 0x00000011U +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO7 0x00000010U +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO6 0x0000000FU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO5 0x0000000EU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO4 0x0000000DU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO3 0x0000000CU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO2 0x0000000BU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO1 0x0000000AU +#define LRFDDBELL_GPOSEL0_SRC0_MCEGPO0 0x00000009U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO7 0x00000008U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO6 0x00000007U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO5 0x00000006U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO4 0x00000005U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO3 0x00000004U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO2 0x00000003U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO1 0x00000002U +#define LRFDDBELL_GPOSEL0_SRC0_PBEGPO0 0x00000001U +#define LRFDDBELL_GPOSEL0_SRC0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_GPOSEL1 +// +//***************************************************************************** +// Field: [28:24] SRC7 +// +// Select source of radio GPO line 7 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 7 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC7_W 5U +#define LRFDDBELL_GPOSEL1_SRC7_M 0x1F000000U +#define LRFDDBELL_GPOSEL1_SRC7_S 24U +#define LRFDDBELL_GPOSEL1_SRC7_RFCTRC 0x19000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO7 0x18000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO6 0x17000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO5 0x16000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO4 0x15000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO3 0x14000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO2 0x13000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO1 0x12000000U +#define LRFDDBELL_GPOSEL1_SRC7_RFEGPO0 0x11000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO7 0x10000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO6 0x0F000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO5 0x0E000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO4 0x0D000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO3 0x0C000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO2 0x0B000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO1 0x0A000000U +#define LRFDDBELL_GPOSEL1_SRC7_MCEGPO0 0x09000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO7 0x08000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO6 0x07000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO5 0x06000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO4 0x05000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO3 0x04000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO2 0x03000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO1 0x02000000U +#define LRFDDBELL_GPOSEL1_SRC7_PBEGPO0 0x01000000U +#define LRFDDBELL_GPOSEL1_SRC7_DIS 0x00000000U + +// Field: [20:16] SRC6 +// +// Select source of radio GPO line 6 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 6 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Selevt RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC6_W 5U +#define LRFDDBELL_GPOSEL1_SRC6_M 0x001F0000U +#define LRFDDBELL_GPOSEL1_SRC6_S 16U +#define LRFDDBELL_GPOSEL1_SRC6_RFCTRC 0x00190000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO7 0x00180000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO6 0x00170000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO5 0x00160000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO4 0x00150000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO3 0x00140000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO2 0x00130000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO1 0x00120000U +#define LRFDDBELL_GPOSEL1_SRC6_RFEGPO0 0x00110000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO7 0x00100000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO6 0x000F0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO5 0x000E0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO4 0x000D0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO3 0x000C0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO2 0x000B0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO1 0x000A0000U +#define LRFDDBELL_GPOSEL1_SRC6_MCEGPO0 0x00090000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO7 0x00080000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO6 0x00070000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO5 0x00060000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO4 0x00050000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO3 0x00040000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO2 0x00030000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO1 0x00020000U +#define LRFDDBELL_GPOSEL1_SRC6_PBEGPO0 0x00010000U +#define LRFDDBELL_GPOSEL1_SRC6_DIS 0x00000000U + +// Field: [12:8] SRC5 +// +// Select source of radio GPO line 5 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 5 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC5_W 5U +#define LRFDDBELL_GPOSEL1_SRC5_M 0x00001F00U +#define LRFDDBELL_GPOSEL1_SRC5_S 8U +#define LRFDDBELL_GPOSEL1_SRC5_RFCTRC 0x00001900U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO7 0x00001800U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO6 0x00001700U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO5 0x00001600U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO4 0x00001500U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO3 0x00001400U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO2 0x00001300U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO1 0x00001200U +#define LRFDDBELL_GPOSEL1_SRC5_RFEGPO0 0x00001100U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO7 0x00001000U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO6 0x00000F00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO5 0x00000E00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO4 0x00000D00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO3 0x00000C00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO2 0x00000B00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO1 0x00000A00U +#define LRFDDBELL_GPOSEL1_SRC5_MCEGPO0 0x00000900U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO7 0x00000800U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO6 0x00000700U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO5 0x00000600U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO4 0x00000500U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO3 0x00000400U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO2 0x00000300U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO1 0x00000200U +#define LRFDDBELL_GPOSEL1_SRC5_PBEGPO0 0x00000100U +#define LRFDDBELL_GPOSEL1_SRC5_DIS 0x00000000U + +// Field: [4:0] SRC4 +// +// Select source of radio GPO line 4 +// ENUMs: +// RFCTRC Select RFCTRC GPO line 4 +// RFEGPO7 Select RFE GPO line 7 +// RFEGPO6 Select RFE GPO line 6 +// RFEGPO5 Select RFE GPO line 5 +// RFEGPO4 Select RFE GPO line 4 +// RFEGPO3 Select RFE GPO line 3 +// RFEGPO2 Select RFE GPO line 2 +// RFEGPO1 Select RFE GPO line 1 +// RFEGPO0 Select RFE GPO line 0 +// MCEGPO7 Select MCE GPO line 7 +// MCEGPO6 Select MCE GPO line 6 +// MCEGPO5 Select MCE GPO line 5 +// MCEGPO4 Select MCE GPO line 4 +// MCEGPO3 Select MCE GPO line 3 +// MCEGPO2 Select MCE GPO line 2 +// MCEGPO1 Select MCE GPO line 1 +// MCEGPO0 Select MCE GPO line 0 +// PBEGPO7 Select PBE GPO line 7 +// PBEGPO6 Select PBE GPO line 6 +// PBEGPO5 Select PBE GPO line 5 +// PBEGPO4 Select PBE GPO line 4 +// PBEGPO3 Select PBE GPO line 3 +// PBEGPO2 Select PBE GPO line 2 +// PBEGPO1 Select PBE GPO line 1 +// PBEGPO0 Select PBE GPO line 0 +// DIS No output not enabled +#define LRFDDBELL_GPOSEL1_SRC4_W 5U +#define LRFDDBELL_GPOSEL1_SRC4_M 0x0000001FU +#define LRFDDBELL_GPOSEL1_SRC4_S 0U +#define LRFDDBELL_GPOSEL1_SRC4_RFCTRC 0x00000019U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO7 0x00000018U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO6 0x00000017U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO5 0x00000016U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO4 0x00000015U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO3 0x00000014U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO2 0x00000013U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO1 0x00000012U +#define LRFDDBELL_GPOSEL1_SRC4_RFEGPO0 0x00000011U +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO7 0x00000010U +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO6 0x0000000FU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO5 0x0000000EU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO4 0x0000000DU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO3 0x0000000CU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO2 0x0000000BU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO1 0x0000000AU +#define LRFDDBELL_GPOSEL1_SRC4_MCEGPO0 0x00000009U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO7 0x00000008U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO6 0x00000007U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO5 0x00000006U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO4 0x00000005U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO3 0x00000004U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO2 0x00000003U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO1 0x00000002U +#define LRFDDBELL_GPOSEL1_SRC4_PBEGPO0 0x00000001U +#define LRFDDBELL_GPOSEL1_SRC4_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM2 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_S 31U +#define LRFDDBELL_IMASK0_SYSTIM2_EN 0x80000000U +#define LRFDDBELL_IMASK0_SYSTIM2_DIS 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM1 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_S 30U +#define LRFDDBELL_IMASK0_SYSTIM1_EN 0x40000000U +#define LRFDDBELL_IMASK0_SYSTIM1_DIS 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_SYSTIM0 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_S 29U +#define LRFDDBELL_IMASK0_SYSTIM0_EN 0x20000000U +#define LRFDDBELL_IMASK0_SYSTIM0_DIS 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMDONE 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_M 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_S 28U +#define LRFDDBELL_IMASK0_MDMDONE_EN 0x10000000U +#define LRFDDBELL_IMASK0_MDMDONE_DIS 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMIN 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_M 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_S 27U +#define LRFDDBELL_IMASK0_MDMIN_EN 0x08000000U +#define LRFDDBELL_IMASK0_MDMIN_DIS 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMOUT 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_M 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_S 26U +#define LRFDDBELL_IMASK0_MDMOUT_EN 0x04000000U +#define LRFDDBELL_IMASK0_MDMOUT_DIS 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT2 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_S 25U +#define LRFDDBELL_IMASK0_MDMSOFT2_EN 0x02000000U +#define LRFDDBELL_IMASK0_MDMSOFT2_DIS 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT1 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_S 24U +#define LRFDDBELL_IMASK0_MDMSOFT1_EN 0x01000000U +#define LRFDDBELL_IMASK0_MDMSOFT1_DIS 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_MDMSOFT0 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_S 23U +#define LRFDDBELL_IMASK0_MDMSOFT0_EN 0x00800000U +#define LRFDDBELL_IMASK0_MDMSOFT0_DIS 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFEDONE 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_M 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_S 22U +#define LRFDDBELL_IMASK0_RFEDONE_EN 0x00400000U +#define LRFDDBELL_IMASK0_RFEDONE_DIS 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFESOFT1 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_S 21U +#define LRFDDBELL_IMASK0_RFESOFT1_EN 0x00200000U +#define LRFDDBELL_IMASK0_RFESOFT1_DIS 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RFESOFT0 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_S 20U +#define LRFDDBELL_IMASK0_RFESOFT0_EN 0x00100000U +#define LRFDDBELL_IMASK0_RFESOFT0_DIS 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_LOCK 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_M 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_S 19U +#define LRFDDBELL_IMASK0_LOCK_EN 0x00080000U +#define LRFDDBELL_IMASK0_LOCK_DIS 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_LOL 0x00040000U +#define LRFDDBELL_IMASK0_LOL_M 0x00040000U +#define LRFDDBELL_IMASK0_LOL_S 18U +#define LRFDDBELL_IMASK0_LOL_EN 0x00040000U +#define LRFDDBELL_IMASK0_LOL_DIS 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_TXFIFO 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_M 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_S 17U +#define LRFDDBELL_IMASK0_TXFIFO_EN 0x00020000U +#define LRFDDBELL_IMASK0_TXFIFO_DIS 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_RXFIFO 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_S 16U +#define LRFDDBELL_IMASK0_RXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK0_RXFIFO_DIS 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE15 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_M 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_S 15U +#define LRFDDBELL_IMASK0_PBE15_EN 0x00008000U +#define LRFDDBELL_IMASK0_PBE15_DIS 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE14 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_M 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_S 14U +#define LRFDDBELL_IMASK0_PBE14_EN 0x00004000U +#define LRFDDBELL_IMASK0_PBE14_DIS 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE13 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_M 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_S 13U +#define LRFDDBELL_IMASK0_PBE13_EN 0x00002000U +#define LRFDDBELL_IMASK0_PBE13_DIS 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE12 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_M 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_S 12U +#define LRFDDBELL_IMASK0_PBE12_EN 0x00001000U +#define LRFDDBELL_IMASK0_PBE12_DIS 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE11 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_M 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_S 11U +#define LRFDDBELL_IMASK0_PBE11_EN 0x00000800U +#define LRFDDBELL_IMASK0_PBE11_DIS 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE10 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_M 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_S 10U +#define LRFDDBELL_IMASK0_PBE10_EN 0x00000400U +#define LRFDDBELL_IMASK0_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE8 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_S 8U +#define LRFDDBELL_IMASK0_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK0_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE7 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_S 7U +#define LRFDDBELL_IMASK0_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK0_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE6 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_S 6U +#define LRFDDBELL_IMASK0_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK0_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE5 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_S 5U +#define LRFDDBELL_IMASK0_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK0_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE4 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_S 4U +#define LRFDDBELL_IMASK0_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK0_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE3 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_S 3U +#define LRFDDBELL_IMASK0_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK0_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE2 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_S 2U +#define LRFDDBELL_IMASK0_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK0_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE1 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_S 1U +#define LRFDDBELL_IMASK0_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK0_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK0_PBE0 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_S 0U +#define LRFDDBELL_IMASK0_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK0_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_S 31U +#define LRFDDBELL_RIS0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS0_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_S 30U +#define LRFDDBELL_RIS0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS0_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_S 29U +#define LRFDDBELL_RIS0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS0_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMDONE 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_S 28U +#define LRFDDBELL_RIS0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS0_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMIN 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_S 27U +#define LRFDDBELL_RIS0_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS0_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMOUT 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_S 26U +#define LRFDDBELL_RIS0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS0_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_S 25U +#define LRFDDBELL_RIS0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS0_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_S 24U +#define LRFDDBELL_RIS0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS0_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_S 23U +#define LRFDDBELL_RIS0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS0_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFEDONE 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_S 22U +#define LRFDDBELL_RIS0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS0_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_S 21U +#define LRFDDBELL_RIS0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS0_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_S 20U +#define LRFDDBELL_RIS0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS0_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_LOCK 0x00080000U +#define LRFDDBELL_RIS0_LOCK_M 0x00080000U +#define LRFDDBELL_RIS0_LOCK_S 19U +#define LRFDDBELL_RIS0_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS0_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_LOL 0x00040000U +#define LRFDDBELL_RIS0_LOL_M 0x00040000U +#define LRFDDBELL_RIS0_LOL_S 18U +#define LRFDDBELL_RIS0_LOL_SET 0x00040000U +#define LRFDDBELL_RIS0_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_TXFIFO 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_S 17U +#define LRFDDBELL_RIS0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS0_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_RXFIFO 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_S 16U +#define LRFDDBELL_RIS0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS0_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE15 0x00008000U +#define LRFDDBELL_RIS0_PBE15_M 0x00008000U +#define LRFDDBELL_RIS0_PBE15_S 15U +#define LRFDDBELL_RIS0_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS0_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE14 0x00004000U +#define LRFDDBELL_RIS0_PBE14_M 0x00004000U +#define LRFDDBELL_RIS0_PBE14_S 14U +#define LRFDDBELL_RIS0_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS0_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE13 0x00002000U +#define LRFDDBELL_RIS0_PBE13_M 0x00002000U +#define LRFDDBELL_RIS0_PBE13_S 13U +#define LRFDDBELL_RIS0_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS0_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE12 0x00001000U +#define LRFDDBELL_RIS0_PBE12_M 0x00001000U +#define LRFDDBELL_RIS0_PBE12_S 12U +#define LRFDDBELL_RIS0_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS0_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE11 0x00000800U +#define LRFDDBELL_RIS0_PBE11_M 0x00000800U +#define LRFDDBELL_RIS0_PBE11_S 11U +#define LRFDDBELL_RIS0_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS0_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE10 0x00000400U +#define LRFDDBELL_RIS0_PBE10_M 0x00000400U +#define LRFDDBELL_RIS0_PBE10_S 10U +#define LRFDDBELL_RIS0_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS0_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE9 0x00000200U +#define LRFDDBELL_RIS0_PBE9_M 0x00000200U +#define LRFDDBELL_RIS0_PBE9_S 9U +#define LRFDDBELL_RIS0_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS0_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE8 0x00000100U +#define LRFDDBELL_RIS0_PBE8_M 0x00000100U +#define LRFDDBELL_RIS0_PBE8_S 8U +#define LRFDDBELL_RIS0_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS0_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE7 0x00000080U +#define LRFDDBELL_RIS0_PBE7_M 0x00000080U +#define LRFDDBELL_RIS0_PBE7_S 7U +#define LRFDDBELL_RIS0_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS0_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE6 0x00000040U +#define LRFDDBELL_RIS0_PBE6_M 0x00000040U +#define LRFDDBELL_RIS0_PBE6_S 6U +#define LRFDDBELL_RIS0_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS0_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE5 0x00000020U +#define LRFDDBELL_RIS0_PBE5_M 0x00000020U +#define LRFDDBELL_RIS0_PBE5_S 5U +#define LRFDDBELL_RIS0_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS0_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE4 0x00000010U +#define LRFDDBELL_RIS0_PBE4_M 0x00000010U +#define LRFDDBELL_RIS0_PBE4_S 4U +#define LRFDDBELL_RIS0_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS0_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE3 0x00000008U +#define LRFDDBELL_RIS0_PBE3_M 0x00000008U +#define LRFDDBELL_RIS0_PBE3_S 3U +#define LRFDDBELL_RIS0_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS0_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE2 0x00000004U +#define LRFDDBELL_RIS0_PBE2_M 0x00000004U +#define LRFDDBELL_RIS0_PBE2_S 2U +#define LRFDDBELL_RIS0_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS0_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE1 0x00000002U +#define LRFDDBELL_RIS0_PBE1_M 0x00000002U +#define LRFDDBELL_RIS0_PBE1_S 1U +#define LRFDDBELL_RIS0_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS0_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS0_PBE0 0x00000001U +#define LRFDDBELL_RIS0_PBE0_M 0x00000001U +#define LRFDDBELL_RIS0_PBE0_S 0U +#define LRFDDBELL_RIS0_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS0_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_S 31U +#define LRFDDBELL_MIS0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS0_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_S 30U +#define LRFDDBELL_MIS0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS0_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_S 29U +#define LRFDDBELL_MIS0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS0_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMDONE 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_S 28U +#define LRFDDBELL_MIS0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS0_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMIN 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_S 27U +#define LRFDDBELL_MIS0_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS0_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMOUT 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_S 26U +#define LRFDDBELL_MIS0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS0_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_S 25U +#define LRFDDBELL_MIS0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS0_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_S 24U +#define LRFDDBELL_MIS0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS0_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_S 23U +#define LRFDDBELL_MIS0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS0_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFEDONE 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_S 22U +#define LRFDDBELL_MIS0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS0_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_S 21U +#define LRFDDBELL_MIS0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS0_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_S 20U +#define LRFDDBELL_MIS0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS0_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_LOCK 0x00080000U +#define LRFDDBELL_MIS0_LOCK_M 0x00080000U +#define LRFDDBELL_MIS0_LOCK_S 19U +#define LRFDDBELL_MIS0_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS0_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_LOL 0x00040000U +#define LRFDDBELL_MIS0_LOL_M 0x00040000U +#define LRFDDBELL_MIS0_LOL_S 18U +#define LRFDDBELL_MIS0_LOL_SET 0x00040000U +#define LRFDDBELL_MIS0_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_TXFIFO 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_S 17U +#define LRFDDBELL_MIS0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS0_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_RXFIFO 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_S 16U +#define LRFDDBELL_MIS0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS0_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE15 0x00008000U +#define LRFDDBELL_MIS0_PBE15_M 0x00008000U +#define LRFDDBELL_MIS0_PBE15_S 15U +#define LRFDDBELL_MIS0_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS0_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE14 0x00004000U +#define LRFDDBELL_MIS0_PBE14_M 0x00004000U +#define LRFDDBELL_MIS0_PBE14_S 14U +#define LRFDDBELL_MIS0_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS0_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE13 0x00002000U +#define LRFDDBELL_MIS0_PBE13_M 0x00002000U +#define LRFDDBELL_MIS0_PBE13_S 13U +#define LRFDDBELL_MIS0_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS0_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE12 0x00001000U +#define LRFDDBELL_MIS0_PBE12_M 0x00001000U +#define LRFDDBELL_MIS0_PBE12_S 12U +#define LRFDDBELL_MIS0_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS0_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE11 0x00000800U +#define LRFDDBELL_MIS0_PBE11_M 0x00000800U +#define LRFDDBELL_MIS0_PBE11_S 11U +#define LRFDDBELL_MIS0_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS0_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE10 0x00000400U +#define LRFDDBELL_MIS0_PBE10_M 0x00000400U +#define LRFDDBELL_MIS0_PBE10_S 10U +#define LRFDDBELL_MIS0_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS0_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE9 0x00000200U +#define LRFDDBELL_MIS0_PBE9_M 0x00000200U +#define LRFDDBELL_MIS0_PBE9_S 9U +#define LRFDDBELL_MIS0_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS0_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE8 0x00000100U +#define LRFDDBELL_MIS0_PBE8_M 0x00000100U +#define LRFDDBELL_MIS0_PBE8_S 8U +#define LRFDDBELL_MIS0_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS0_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE7 0x00000080U +#define LRFDDBELL_MIS0_PBE7_M 0x00000080U +#define LRFDDBELL_MIS0_PBE7_S 7U +#define LRFDDBELL_MIS0_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS0_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE6 0x00000040U +#define LRFDDBELL_MIS0_PBE6_M 0x00000040U +#define LRFDDBELL_MIS0_PBE6_S 6U +#define LRFDDBELL_MIS0_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS0_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE5 0x00000020U +#define LRFDDBELL_MIS0_PBE5_M 0x00000020U +#define LRFDDBELL_MIS0_PBE5_S 5U +#define LRFDDBELL_MIS0_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS0_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE4 0x00000010U +#define LRFDDBELL_MIS0_PBE4_M 0x00000010U +#define LRFDDBELL_MIS0_PBE4_S 4U +#define LRFDDBELL_MIS0_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS0_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE3 0x00000008U +#define LRFDDBELL_MIS0_PBE3_M 0x00000008U +#define LRFDDBELL_MIS0_PBE3_S 3U +#define LRFDDBELL_MIS0_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS0_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE2 0x00000004U +#define LRFDDBELL_MIS0_PBE2_M 0x00000004U +#define LRFDDBELL_MIS0_PBE2_S 2U +#define LRFDDBELL_MIS0_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS0_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE1 0x00000002U +#define LRFDDBELL_MIS0_PBE1_M 0x00000002U +#define LRFDDBELL_MIS0_PBE1_S 1U +#define LRFDDBELL_MIS0_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS0_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS0_PBE0 0x00000001U +#define LRFDDBELL_MIS0_PBE0_M 0x00000001U +#define LRFDDBELL_MIS0_PBE0_S 0U +#define LRFDDBELL_MIS0_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS0_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_S 31U +#define LRFDDBELL_ISET0_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET0_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_S 30U +#define LRFDDBELL_ISET0_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET0_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_S 29U +#define LRFDDBELL_ISET0_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET0_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMDONE 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_S 28U +#define LRFDDBELL_ISET0_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET0_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMIN 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_S 27U +#define LRFDDBELL_ISET0_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET0_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMOUT 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_S 26U +#define LRFDDBELL_ISET0_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET0_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_S 25U +#define LRFDDBELL_ISET0_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET0_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_S 24U +#define LRFDDBELL_ISET0_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET0_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_S 23U +#define LRFDDBELL_ISET0_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET0_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFEDONE 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_S 22U +#define LRFDDBELL_ISET0_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET0_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_S 21U +#define LRFDDBELL_ISET0_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET0_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_S 20U +#define LRFDDBELL_ISET0_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET0_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_LOCK 0x00080000U +#define LRFDDBELL_ISET0_LOCK_M 0x00080000U +#define LRFDDBELL_ISET0_LOCK_S 19U +#define LRFDDBELL_ISET0_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET0_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_LOL 0x00040000U +#define LRFDDBELL_ISET0_LOL_M 0x00040000U +#define LRFDDBELL_ISET0_LOL_S 18U +#define LRFDDBELL_ISET0_LOL_SET 0x00040000U +#define LRFDDBELL_ISET0_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_TXFIFO 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_S 17U +#define LRFDDBELL_ISET0_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET0_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_RXFIFO 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_S 16U +#define LRFDDBELL_ISET0_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET0_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE15 0x00008000U +#define LRFDDBELL_ISET0_PBE15_M 0x00008000U +#define LRFDDBELL_ISET0_PBE15_S 15U +#define LRFDDBELL_ISET0_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET0_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE14 0x00004000U +#define LRFDDBELL_ISET0_PBE14_M 0x00004000U +#define LRFDDBELL_ISET0_PBE14_S 14U +#define LRFDDBELL_ISET0_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET0_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE13 0x00002000U +#define LRFDDBELL_ISET0_PBE13_M 0x00002000U +#define LRFDDBELL_ISET0_PBE13_S 13U +#define LRFDDBELL_ISET0_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET0_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE12 0x00001000U +#define LRFDDBELL_ISET0_PBE12_M 0x00001000U +#define LRFDDBELL_ISET0_PBE12_S 12U +#define LRFDDBELL_ISET0_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET0_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE11 0x00000800U +#define LRFDDBELL_ISET0_PBE11_M 0x00000800U +#define LRFDDBELL_ISET0_PBE11_S 11U +#define LRFDDBELL_ISET0_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET0_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE10 0x00000400U +#define LRFDDBELL_ISET0_PBE10_M 0x00000400U +#define LRFDDBELL_ISET0_PBE10_S 10U +#define LRFDDBELL_ISET0_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET0_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE9 0x00000200U +#define LRFDDBELL_ISET0_PBE9_M 0x00000200U +#define LRFDDBELL_ISET0_PBE9_S 9U +#define LRFDDBELL_ISET0_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET0_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE8 0x00000100U +#define LRFDDBELL_ISET0_PBE8_M 0x00000100U +#define LRFDDBELL_ISET0_PBE8_S 8U +#define LRFDDBELL_ISET0_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET0_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE7 0x00000080U +#define LRFDDBELL_ISET0_PBE7_M 0x00000080U +#define LRFDDBELL_ISET0_PBE7_S 7U +#define LRFDDBELL_ISET0_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET0_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE6 0x00000040U +#define LRFDDBELL_ISET0_PBE6_M 0x00000040U +#define LRFDDBELL_ISET0_PBE6_S 6U +#define LRFDDBELL_ISET0_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET0_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE5 0x00000020U +#define LRFDDBELL_ISET0_PBE5_M 0x00000020U +#define LRFDDBELL_ISET0_PBE5_S 5U +#define LRFDDBELL_ISET0_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET0_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE4 0x00000010U +#define LRFDDBELL_ISET0_PBE4_M 0x00000010U +#define LRFDDBELL_ISET0_PBE4_S 4U +#define LRFDDBELL_ISET0_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET0_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE3 0x00000008U +#define LRFDDBELL_ISET0_PBE3_M 0x00000008U +#define LRFDDBELL_ISET0_PBE3_S 3U +#define LRFDDBELL_ISET0_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET0_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE2 0x00000004U +#define LRFDDBELL_ISET0_PBE2_M 0x00000004U +#define LRFDDBELL_ISET0_PBE2_S 2U +#define LRFDDBELL_ISET0_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET0_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE1 0x00000002U +#define LRFDDBELL_ISET0_PBE1_M 0x00000002U +#define LRFDDBELL_ISET0_PBE1_S 1U +#define LRFDDBELL_ISET0_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET0_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET0_PBE0 0x00000001U +#define LRFDDBELL_ISET0_PBE0_M 0x00000001U +#define LRFDDBELL_ISET0_PBE0_S 0U +#define LRFDDBELL_ISET0_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET0_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR0 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_S 31U +#define LRFDDBELL_ICLR0_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR0_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_S 30U +#define LRFDDBELL_ICLR0_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR0_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_S 29U +#define LRFDDBELL_ICLR0_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR0_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_S 28U +#define LRFDDBELL_ICLR0_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR0_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMIN 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_S 27U +#define LRFDDBELL_ICLR0_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR0_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_S 26U +#define LRFDDBELL_ICLR0_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR0_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR0_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR0_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR0_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR0_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR0_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR0_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_S 22U +#define LRFDDBELL_ICLR0_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR0_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_S 21U +#define LRFDDBELL_ICLR0_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR0_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_S 20U +#define LRFDDBELL_ICLR0_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR0_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_LOCK 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_S 19U +#define LRFDDBELL_ICLR0_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR0_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_LOL 0x00040000U +#define LRFDDBELL_ICLR0_LOL_M 0x00040000U +#define LRFDDBELL_ICLR0_LOL_S 18U +#define LRFDDBELL_ICLR0_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR0_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_S 17U +#define LRFDDBELL_ICLR0_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR0_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_S 16U +#define LRFDDBELL_ICLR0_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR0_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE15 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_S 15U +#define LRFDDBELL_ICLR0_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR0_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE14 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_S 14U +#define LRFDDBELL_ICLR0_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR0_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE13 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_S 13U +#define LRFDDBELL_ICLR0_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR0_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE12 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_S 12U +#define LRFDDBELL_ICLR0_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR0_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE11 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_S 11U +#define LRFDDBELL_ICLR0_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR0_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE10 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_S 10U +#define LRFDDBELL_ICLR0_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR0_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE9 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_S 9U +#define LRFDDBELL_ICLR0_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR0_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE8 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_S 8U +#define LRFDDBELL_ICLR0_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR0_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE7 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_S 7U +#define LRFDDBELL_ICLR0_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR0_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE6 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_S 6U +#define LRFDDBELL_ICLR0_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR0_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE5 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_S 5U +#define LRFDDBELL_ICLR0_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR0_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE4 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_S 4U +#define LRFDDBELL_ICLR0_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR0_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE3 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_S 3U +#define LRFDDBELL_ICLR0_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR0_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE2 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_S 2U +#define LRFDDBELL_ICLR0_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR0_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE1 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_S 1U +#define LRFDDBELL_ICLR0_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR0_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR0_PBE0 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_S 0U +#define LRFDDBELL_ICLR0_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR0_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK1 +// +//***************************************************************************** +// Field: [30] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM2 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_M 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_S 30U +#define LRFDDBELL_IMASK1_SYSTIM2_EN 0x40000000U +#define LRFDDBELL_IMASK1_SYSTIM2_DIS 0x00000000U + +// Field: [29] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM1 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_M 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_S 29U +#define LRFDDBELL_IMASK1_SYSTIM1_EN 0x20000000U +#define LRFDDBELL_IMASK1_SYSTIM1_DIS 0x00000000U + +// Field: [28] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_SYSTIM0 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_M 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_S 28U +#define LRFDDBELL_IMASK1_SYSTIM0_EN 0x10000000U +#define LRFDDBELL_IMASK1_SYSTIM0_DIS 0x00000000U + +// Field: [27] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMDONE 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_M 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_S 27U +#define LRFDDBELL_IMASK1_MDMDONE_EN 0x08000000U +#define LRFDDBELL_IMASK1_MDMDONE_DIS 0x00000000U + +// Field: [26] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMIN 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_M 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_S 26U +#define LRFDDBELL_IMASK1_MDMIN_EN 0x04000000U +#define LRFDDBELL_IMASK1_MDMIN_DIS 0x00000000U + +// Field: [25] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMOUT 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_M 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_S 25U +#define LRFDDBELL_IMASK1_MDMOUT_EN 0x02000000U +#define LRFDDBELL_IMASK1_MDMOUT_DIS 0x00000000U + +// Field: [24] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT2 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_M 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_S 24U +#define LRFDDBELL_IMASK1_MDMSOFT2_EN 0x01000000U +#define LRFDDBELL_IMASK1_MDMSOFT2_DIS 0x00000000U + +// Field: [23] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT1 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_M 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_S 23U +#define LRFDDBELL_IMASK1_MDMSOFT1_EN 0x00800000U +#define LRFDDBELL_IMASK1_MDMSOFT1_DIS 0x00000000U + +// Field: [22] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_MDMSOFT0 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_M 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_S 22U +#define LRFDDBELL_IMASK1_MDMSOFT0_EN 0x00400000U +#define LRFDDBELL_IMASK1_MDMSOFT0_DIS 0x00000000U + +// Field: [21] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFEDONE 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_M 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_S 21U +#define LRFDDBELL_IMASK1_RFEDONE_EN 0x00200000U +#define LRFDDBELL_IMASK1_RFEDONE_DIS 0x00000000U + +// Field: [20] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFESOFT1 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_M 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_S 20U +#define LRFDDBELL_IMASK1_RFESOFT1_EN 0x00100000U +#define LRFDDBELL_IMASK1_RFESOFT1_DIS 0x00000000U + +// Field: [19] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RFESOFT0 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_M 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_S 19U +#define LRFDDBELL_IMASK1_RFESOFT0_EN 0x00080000U +#define LRFDDBELL_IMASK1_RFESOFT0_DIS 0x00000000U + +// Field: [18] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_LOCK 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_M 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_S 18U +#define LRFDDBELL_IMASK1_LOCK_EN 0x00040000U +#define LRFDDBELL_IMASK1_LOCK_DIS 0x00000000U + +// Field: [17] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_LOL 0x00020000U +#define LRFDDBELL_IMASK1_LOL_M 0x00020000U +#define LRFDDBELL_IMASK1_LOL_S 17U +#define LRFDDBELL_IMASK1_LOL_EN 0x00020000U +#define LRFDDBELL_IMASK1_LOL_DIS 0x00000000U + +// Field: [16] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_TXFIFO 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_S 16U +#define LRFDDBELL_IMASK1_TXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK1_TXFIFO_DIS 0x00000000U + +// Field: [15] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_RXFIFO 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_M 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_S 15U +#define LRFDDBELL_IMASK1_RXFIFO_EN 0x00008000U +#define LRFDDBELL_IMASK1_RXFIFO_DIS 0x00000000U + +// Field: [14] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE15 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_M 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_S 14U +#define LRFDDBELL_IMASK1_PBE15_EN 0x00004000U +#define LRFDDBELL_IMASK1_PBE15_DIS 0x00000000U + +// Field: [13] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE14 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_M 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_S 13U +#define LRFDDBELL_IMASK1_PBE14_EN 0x00002000U +#define LRFDDBELL_IMASK1_PBE14_DIS 0x00000000U + +// Field: [12] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE13 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_M 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_S 12U +#define LRFDDBELL_IMASK1_PBE13_EN 0x00001000U +#define LRFDDBELL_IMASK1_PBE13_DIS 0x00000000U + +// Field: [11] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE12 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_M 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_S 11U +#define LRFDDBELL_IMASK1_PBE12_EN 0x00000800U +#define LRFDDBELL_IMASK1_PBE12_DIS 0x00000000U + +// Field: [10] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE11 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_M 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_S 10U +#define LRFDDBELL_IMASK1_PBE11_EN 0x00000400U +#define LRFDDBELL_IMASK1_PBE11_DIS 0x00000000U + +// Field: [9] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE10 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_M 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_S 9U +#define LRFDDBELL_IMASK1_PBE10_EN 0x00000200U +#define LRFDDBELL_IMASK1_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE8 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_S 8U +#define LRFDDBELL_IMASK1_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK1_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE7 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_S 7U +#define LRFDDBELL_IMASK1_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK1_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE6 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_S 6U +#define LRFDDBELL_IMASK1_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK1_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE5 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_S 5U +#define LRFDDBELL_IMASK1_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK1_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE4 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_S 4U +#define LRFDDBELL_IMASK1_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK1_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE3 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_S 3U +#define LRFDDBELL_IMASK1_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK1_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE2 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_S 2U +#define LRFDDBELL_IMASK1_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK1_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE1 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_S 1U +#define LRFDDBELL_IMASK1_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK1_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK1_PBE0 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_S 0U +#define LRFDDBELL_IMASK1_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK1_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_S 31U +#define LRFDDBELL_RIS1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS1_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_S 30U +#define LRFDDBELL_RIS1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS1_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_S 29U +#define LRFDDBELL_RIS1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS1_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMDONE 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_S 28U +#define LRFDDBELL_RIS1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS1_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMIN 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_S 27U +#define LRFDDBELL_RIS1_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS1_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMOUT 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_S 26U +#define LRFDDBELL_RIS1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS1_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_S 25U +#define LRFDDBELL_RIS1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS1_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_S 24U +#define LRFDDBELL_RIS1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS1_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_S 23U +#define LRFDDBELL_RIS1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS1_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFEDONE 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_S 22U +#define LRFDDBELL_RIS1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS1_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_S 21U +#define LRFDDBELL_RIS1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS1_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_S 20U +#define LRFDDBELL_RIS1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS1_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_LOCK 0x00080000U +#define LRFDDBELL_RIS1_LOCK_M 0x00080000U +#define LRFDDBELL_RIS1_LOCK_S 19U +#define LRFDDBELL_RIS1_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS1_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_LOL 0x00040000U +#define LRFDDBELL_RIS1_LOL_M 0x00040000U +#define LRFDDBELL_RIS1_LOL_S 18U +#define LRFDDBELL_RIS1_LOL_SET 0x00040000U +#define LRFDDBELL_RIS1_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_TXFIFO 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_S 17U +#define LRFDDBELL_RIS1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS1_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_RXFIFO 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_S 16U +#define LRFDDBELL_RIS1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS1_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE15 0x00008000U +#define LRFDDBELL_RIS1_PBE15_M 0x00008000U +#define LRFDDBELL_RIS1_PBE15_S 15U +#define LRFDDBELL_RIS1_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS1_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE14 0x00004000U +#define LRFDDBELL_RIS1_PBE14_M 0x00004000U +#define LRFDDBELL_RIS1_PBE14_S 14U +#define LRFDDBELL_RIS1_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS1_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE13 0x00002000U +#define LRFDDBELL_RIS1_PBE13_M 0x00002000U +#define LRFDDBELL_RIS1_PBE13_S 13U +#define LRFDDBELL_RIS1_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS1_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE12 0x00001000U +#define LRFDDBELL_RIS1_PBE12_M 0x00001000U +#define LRFDDBELL_RIS1_PBE12_S 12U +#define LRFDDBELL_RIS1_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS1_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE11 0x00000800U +#define LRFDDBELL_RIS1_PBE11_M 0x00000800U +#define LRFDDBELL_RIS1_PBE11_S 11U +#define LRFDDBELL_RIS1_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS1_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE10 0x00000400U +#define LRFDDBELL_RIS1_PBE10_M 0x00000400U +#define LRFDDBELL_RIS1_PBE10_S 10U +#define LRFDDBELL_RIS1_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS1_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE9 0x00000200U +#define LRFDDBELL_RIS1_PBE9_M 0x00000200U +#define LRFDDBELL_RIS1_PBE9_S 9U +#define LRFDDBELL_RIS1_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS1_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE8 0x00000100U +#define LRFDDBELL_RIS1_PBE8_M 0x00000100U +#define LRFDDBELL_RIS1_PBE8_S 8U +#define LRFDDBELL_RIS1_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS1_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE7 0x00000080U +#define LRFDDBELL_RIS1_PBE7_M 0x00000080U +#define LRFDDBELL_RIS1_PBE7_S 7U +#define LRFDDBELL_RIS1_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS1_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE6 0x00000040U +#define LRFDDBELL_RIS1_PBE6_M 0x00000040U +#define LRFDDBELL_RIS1_PBE6_S 6U +#define LRFDDBELL_RIS1_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS1_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE5 0x00000020U +#define LRFDDBELL_RIS1_PBE5_M 0x00000020U +#define LRFDDBELL_RIS1_PBE5_S 5U +#define LRFDDBELL_RIS1_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS1_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE4 0x00000010U +#define LRFDDBELL_RIS1_PBE4_M 0x00000010U +#define LRFDDBELL_RIS1_PBE4_S 4U +#define LRFDDBELL_RIS1_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS1_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE3 0x00000008U +#define LRFDDBELL_RIS1_PBE3_M 0x00000008U +#define LRFDDBELL_RIS1_PBE3_S 3U +#define LRFDDBELL_RIS1_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS1_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE2 0x00000004U +#define LRFDDBELL_RIS1_PBE2_M 0x00000004U +#define LRFDDBELL_RIS1_PBE2_S 2U +#define LRFDDBELL_RIS1_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS1_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE1 0x00000002U +#define LRFDDBELL_RIS1_PBE1_M 0x00000002U +#define LRFDDBELL_RIS1_PBE1_S 1U +#define LRFDDBELL_RIS1_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS1_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS1_PBE0 0x00000001U +#define LRFDDBELL_RIS1_PBE0_M 0x00000001U +#define LRFDDBELL_RIS1_PBE0_S 0U +#define LRFDDBELL_RIS1_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS1_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_S 31U +#define LRFDDBELL_MIS1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS1_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_S 30U +#define LRFDDBELL_MIS1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS1_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_S 29U +#define LRFDDBELL_MIS1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS1_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMDONE 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_S 28U +#define LRFDDBELL_MIS1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS1_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMIN 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_S 27U +#define LRFDDBELL_MIS1_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS1_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMOUT 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_S 26U +#define LRFDDBELL_MIS1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS1_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_S 25U +#define LRFDDBELL_MIS1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS1_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_S 24U +#define LRFDDBELL_MIS1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS1_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_S 23U +#define LRFDDBELL_MIS1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS1_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFEDONE 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_S 22U +#define LRFDDBELL_MIS1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS1_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_S 21U +#define LRFDDBELL_MIS1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS1_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_S 20U +#define LRFDDBELL_MIS1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS1_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_LOCK 0x00080000U +#define LRFDDBELL_MIS1_LOCK_M 0x00080000U +#define LRFDDBELL_MIS1_LOCK_S 19U +#define LRFDDBELL_MIS1_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS1_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_LOL 0x00040000U +#define LRFDDBELL_MIS1_LOL_M 0x00040000U +#define LRFDDBELL_MIS1_LOL_S 18U +#define LRFDDBELL_MIS1_LOL_SET 0x00040000U +#define LRFDDBELL_MIS1_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_TXFIFO 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_S 17U +#define LRFDDBELL_MIS1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS1_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_RXFIFO 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_S 16U +#define LRFDDBELL_MIS1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS1_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE15 0x00008000U +#define LRFDDBELL_MIS1_PBE15_M 0x00008000U +#define LRFDDBELL_MIS1_PBE15_S 15U +#define LRFDDBELL_MIS1_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS1_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE14 0x00004000U +#define LRFDDBELL_MIS1_PBE14_M 0x00004000U +#define LRFDDBELL_MIS1_PBE14_S 14U +#define LRFDDBELL_MIS1_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS1_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE13 0x00002000U +#define LRFDDBELL_MIS1_PBE13_M 0x00002000U +#define LRFDDBELL_MIS1_PBE13_S 13U +#define LRFDDBELL_MIS1_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS1_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE12 0x00001000U +#define LRFDDBELL_MIS1_PBE12_M 0x00001000U +#define LRFDDBELL_MIS1_PBE12_S 12U +#define LRFDDBELL_MIS1_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS1_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE11 0x00000800U +#define LRFDDBELL_MIS1_PBE11_M 0x00000800U +#define LRFDDBELL_MIS1_PBE11_S 11U +#define LRFDDBELL_MIS1_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS1_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE10 0x00000400U +#define LRFDDBELL_MIS1_PBE10_M 0x00000400U +#define LRFDDBELL_MIS1_PBE10_S 10U +#define LRFDDBELL_MIS1_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS1_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE9 0x00000200U +#define LRFDDBELL_MIS1_PBE9_M 0x00000200U +#define LRFDDBELL_MIS1_PBE9_S 9U +#define LRFDDBELL_MIS1_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS1_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE8 0x00000100U +#define LRFDDBELL_MIS1_PBE8_M 0x00000100U +#define LRFDDBELL_MIS1_PBE8_S 8U +#define LRFDDBELL_MIS1_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS1_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE7 0x00000080U +#define LRFDDBELL_MIS1_PBE7_M 0x00000080U +#define LRFDDBELL_MIS1_PBE7_S 7U +#define LRFDDBELL_MIS1_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS1_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE6 0x00000040U +#define LRFDDBELL_MIS1_PBE6_M 0x00000040U +#define LRFDDBELL_MIS1_PBE6_S 6U +#define LRFDDBELL_MIS1_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS1_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE5 0x00000020U +#define LRFDDBELL_MIS1_PBE5_M 0x00000020U +#define LRFDDBELL_MIS1_PBE5_S 5U +#define LRFDDBELL_MIS1_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS1_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE4 0x00000010U +#define LRFDDBELL_MIS1_PBE4_M 0x00000010U +#define LRFDDBELL_MIS1_PBE4_S 4U +#define LRFDDBELL_MIS1_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS1_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE3 0x00000008U +#define LRFDDBELL_MIS1_PBE3_M 0x00000008U +#define LRFDDBELL_MIS1_PBE3_S 3U +#define LRFDDBELL_MIS1_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS1_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE2 0x00000004U +#define LRFDDBELL_MIS1_PBE2_M 0x00000004U +#define LRFDDBELL_MIS1_PBE2_S 2U +#define LRFDDBELL_MIS1_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS1_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE1 0x00000002U +#define LRFDDBELL_MIS1_PBE1_M 0x00000002U +#define LRFDDBELL_MIS1_PBE1_S 1U +#define LRFDDBELL_MIS1_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS1_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS1_PBE0 0x00000001U +#define LRFDDBELL_MIS1_PBE0_M 0x00000001U +#define LRFDDBELL_MIS1_PBE0_S 0U +#define LRFDDBELL_MIS1_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS1_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_S 31U +#define LRFDDBELL_ISET1_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET1_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_S 30U +#define LRFDDBELL_ISET1_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET1_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_S 29U +#define LRFDDBELL_ISET1_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET1_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMDONE 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_S 28U +#define LRFDDBELL_ISET1_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET1_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMIN 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_S 27U +#define LRFDDBELL_ISET1_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET1_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMOUT 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_S 26U +#define LRFDDBELL_ISET1_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET1_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_S 25U +#define LRFDDBELL_ISET1_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET1_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_S 24U +#define LRFDDBELL_ISET1_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET1_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_S 23U +#define LRFDDBELL_ISET1_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET1_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFEDONE 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_S 22U +#define LRFDDBELL_ISET1_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET1_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_S 21U +#define LRFDDBELL_ISET1_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET1_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_S 20U +#define LRFDDBELL_ISET1_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET1_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_LOCK 0x00080000U +#define LRFDDBELL_ISET1_LOCK_M 0x00080000U +#define LRFDDBELL_ISET1_LOCK_S 19U +#define LRFDDBELL_ISET1_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET1_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_LOL 0x00040000U +#define LRFDDBELL_ISET1_LOL_M 0x00040000U +#define LRFDDBELL_ISET1_LOL_S 18U +#define LRFDDBELL_ISET1_LOL_SET 0x00040000U +#define LRFDDBELL_ISET1_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_TXFIFO 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_S 17U +#define LRFDDBELL_ISET1_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET1_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_RXFIFO 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_S 16U +#define LRFDDBELL_ISET1_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET1_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE15 0x00008000U +#define LRFDDBELL_ISET1_PBE15_M 0x00008000U +#define LRFDDBELL_ISET1_PBE15_S 15U +#define LRFDDBELL_ISET1_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET1_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE14 0x00004000U +#define LRFDDBELL_ISET1_PBE14_M 0x00004000U +#define LRFDDBELL_ISET1_PBE14_S 14U +#define LRFDDBELL_ISET1_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET1_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE13 0x00002000U +#define LRFDDBELL_ISET1_PBE13_M 0x00002000U +#define LRFDDBELL_ISET1_PBE13_S 13U +#define LRFDDBELL_ISET1_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET1_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE12 0x00001000U +#define LRFDDBELL_ISET1_PBE12_M 0x00001000U +#define LRFDDBELL_ISET1_PBE12_S 12U +#define LRFDDBELL_ISET1_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET1_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE11 0x00000800U +#define LRFDDBELL_ISET1_PBE11_M 0x00000800U +#define LRFDDBELL_ISET1_PBE11_S 11U +#define LRFDDBELL_ISET1_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET1_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE10 0x00000400U +#define LRFDDBELL_ISET1_PBE10_M 0x00000400U +#define LRFDDBELL_ISET1_PBE10_S 10U +#define LRFDDBELL_ISET1_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET1_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE9 0x00000200U +#define LRFDDBELL_ISET1_PBE9_M 0x00000200U +#define LRFDDBELL_ISET1_PBE9_S 9U +#define LRFDDBELL_ISET1_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET1_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE8 0x00000100U +#define LRFDDBELL_ISET1_PBE8_M 0x00000100U +#define LRFDDBELL_ISET1_PBE8_S 8U +#define LRFDDBELL_ISET1_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET1_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE7 0x00000080U +#define LRFDDBELL_ISET1_PBE7_M 0x00000080U +#define LRFDDBELL_ISET1_PBE7_S 7U +#define LRFDDBELL_ISET1_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET1_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE6 0x00000040U +#define LRFDDBELL_ISET1_PBE6_M 0x00000040U +#define LRFDDBELL_ISET1_PBE6_S 6U +#define LRFDDBELL_ISET1_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET1_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE5 0x00000020U +#define LRFDDBELL_ISET1_PBE5_M 0x00000020U +#define LRFDDBELL_ISET1_PBE5_S 5U +#define LRFDDBELL_ISET1_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET1_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE4 0x00000010U +#define LRFDDBELL_ISET1_PBE4_M 0x00000010U +#define LRFDDBELL_ISET1_PBE4_S 4U +#define LRFDDBELL_ISET1_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET1_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE3 0x00000008U +#define LRFDDBELL_ISET1_PBE3_M 0x00000008U +#define LRFDDBELL_ISET1_PBE3_S 3U +#define LRFDDBELL_ISET1_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET1_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE2 0x00000004U +#define LRFDDBELL_ISET1_PBE2_M 0x00000004U +#define LRFDDBELL_ISET1_PBE2_S 2U +#define LRFDDBELL_ISET1_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET1_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE1 0x00000002U +#define LRFDDBELL_ISET1_PBE1_M 0x00000002U +#define LRFDDBELL_ISET1_PBE1_S 1U +#define LRFDDBELL_ISET1_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET1_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET1_PBE0 0x00000001U +#define LRFDDBELL_ISET1_PBE0_M 0x00000001U +#define LRFDDBELL_ISET1_PBE0_S 0U +#define LRFDDBELL_ISET1_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET1_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR1 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_S 31U +#define LRFDDBELL_ICLR1_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR1_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_S 30U +#define LRFDDBELL_ICLR1_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR1_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_S 29U +#define LRFDDBELL_ICLR1_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR1_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_S 28U +#define LRFDDBELL_ICLR1_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR1_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMIN 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_S 27U +#define LRFDDBELL_ICLR1_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR1_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_S 26U +#define LRFDDBELL_ICLR1_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR1_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR1_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR1_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR1_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR1_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR1_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR1_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_S 22U +#define LRFDDBELL_ICLR1_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR1_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_S 21U +#define LRFDDBELL_ICLR1_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR1_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_S 20U +#define LRFDDBELL_ICLR1_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR1_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_LOCK 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_S 19U +#define LRFDDBELL_ICLR1_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR1_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_LOL 0x00040000U +#define LRFDDBELL_ICLR1_LOL_M 0x00040000U +#define LRFDDBELL_ICLR1_LOL_S 18U +#define LRFDDBELL_ICLR1_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR1_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_S 17U +#define LRFDDBELL_ICLR1_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR1_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_S 16U +#define LRFDDBELL_ICLR1_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR1_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE15 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_S 15U +#define LRFDDBELL_ICLR1_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR1_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE14 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_S 14U +#define LRFDDBELL_ICLR1_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR1_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE13 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_S 13U +#define LRFDDBELL_ICLR1_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR1_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE12 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_S 12U +#define LRFDDBELL_ICLR1_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR1_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE11 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_S 11U +#define LRFDDBELL_ICLR1_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR1_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE10 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_S 10U +#define LRFDDBELL_ICLR1_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR1_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE9 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_S 9U +#define LRFDDBELL_ICLR1_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR1_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE8 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_S 8U +#define LRFDDBELL_ICLR1_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR1_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE7 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_S 7U +#define LRFDDBELL_ICLR1_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR1_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE6 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_S 6U +#define LRFDDBELL_ICLR1_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR1_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE5 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_S 5U +#define LRFDDBELL_ICLR1_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR1_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE4 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_S 4U +#define LRFDDBELL_ICLR1_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR1_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE3 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_S 3U +#define LRFDDBELL_ICLR1_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR1_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE2 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_S 2U +#define LRFDDBELL_ICLR1_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR1_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE1 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_S 1U +#define LRFDDBELL_ICLR1_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR1_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR1_PBE0 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_S 0U +#define LRFDDBELL_ICLR1_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR1_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_IMASK2 +// +//***************************************************************************** +// Field: [30] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM2 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_M 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_S 30U +#define LRFDDBELL_IMASK2_SYSTIM2_EN 0x40000000U +#define LRFDDBELL_IMASK2_SYSTIM2_DIS 0x00000000U + +// Field: [29] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM1 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_M 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_S 29U +#define LRFDDBELL_IMASK2_SYSTIM1_EN 0x20000000U +#define LRFDDBELL_IMASK2_SYSTIM1_DIS 0x00000000U + +// Field: [28] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_SYSTIM0 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_M 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_S 28U +#define LRFDDBELL_IMASK2_SYSTIM0_EN 0x10000000U +#define LRFDDBELL_IMASK2_SYSTIM0_DIS 0x00000000U + +// Field: [27] MDMDONE +// +// MDMDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMDONE 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_M 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_S 27U +#define LRFDDBELL_IMASK2_MDMDONE_EN 0x08000000U +#define LRFDDBELL_IMASK2_MDMDONE_DIS 0x00000000U + +// Field: [26] MDMIN +// +// MDMIN event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMIN 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_M 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_S 26U +#define LRFDDBELL_IMASK2_MDMIN_EN 0x04000000U +#define LRFDDBELL_IMASK2_MDMIN_DIS 0x00000000U + +// Field: [25] MDMOUT +// +// MDMOUT event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMOUT 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_M 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_S 25U +#define LRFDDBELL_IMASK2_MDMOUT_EN 0x02000000U +#define LRFDDBELL_IMASK2_MDMOUT_DIS 0x00000000U + +// Field: [24] MDMSOFT2 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT2 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_M 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_S 24U +#define LRFDDBELL_IMASK2_MDMSOFT2_EN 0x01000000U +#define LRFDDBELL_IMASK2_MDMSOFT2_DIS 0x00000000U + +// Field: [23] MDMSOFT1 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT1 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_M 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_S 23U +#define LRFDDBELL_IMASK2_MDMSOFT1_EN 0x00800000U +#define LRFDDBELL_IMASK2_MDMSOFT1_DIS 0x00000000U + +// Field: [22] MDMSOFT0 +// +// MDMSOFT2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_MDMSOFT0 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_M 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_S 22U +#define LRFDDBELL_IMASK2_MDMSOFT0_EN 0x00400000U +#define LRFDDBELL_IMASK2_MDMSOFT0_DIS 0x00000000U + +// Field: [21] RFEDONE +// +// RFEDONE event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFEDONE 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_M 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_S 21U +#define LRFDDBELL_IMASK2_RFEDONE_EN 0x00200000U +#define LRFDDBELL_IMASK2_RFEDONE_DIS 0x00000000U + +// Field: [20] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFESOFT1 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_M 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_S 20U +#define LRFDDBELL_IMASK2_RFESOFT1_EN 0x00100000U +#define LRFDDBELL_IMASK2_RFESOFT1_DIS 0x00000000U + +// Field: [19] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RFESOFT0 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_M 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_S 19U +#define LRFDDBELL_IMASK2_RFESOFT0_EN 0x00080000U +#define LRFDDBELL_IMASK2_RFESOFT0_DIS 0x00000000U + +// Field: [18] LOCK +// +// LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_LOCK 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_M 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_S 18U +#define LRFDDBELL_IMASK2_LOCK_EN 0x00040000U +#define LRFDDBELL_IMASK2_LOCK_DIS 0x00000000U + +// Field: [17] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_LOL 0x00020000U +#define LRFDDBELL_IMASK2_LOL_M 0x00020000U +#define LRFDDBELL_IMASK2_LOL_S 17U +#define LRFDDBELL_IMASK2_LOL_EN 0x00020000U +#define LRFDDBELL_IMASK2_LOL_DIS 0x00000000U + +// Field: [16] TXFIFO +// +// TXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_TXFIFO 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_M 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_S 16U +#define LRFDDBELL_IMASK2_TXFIFO_EN 0x00010000U +#define LRFDDBELL_IMASK2_TXFIFO_DIS 0x00000000U + +// Field: [15] RXFIFO +// +// RXFIFO event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_RXFIFO 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_M 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_S 15U +#define LRFDDBELL_IMASK2_RXFIFO_EN 0x00008000U +#define LRFDDBELL_IMASK2_RXFIFO_DIS 0x00000000U + +// Field: [14] PBE15 +// +// PBE15 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE15 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_M 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_S 14U +#define LRFDDBELL_IMASK2_PBE15_EN 0x00004000U +#define LRFDDBELL_IMASK2_PBE15_DIS 0x00000000U + +// Field: [13] PBE14 +// +// PBE14 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE14 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_M 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_S 13U +#define LRFDDBELL_IMASK2_PBE14_EN 0x00002000U +#define LRFDDBELL_IMASK2_PBE14_DIS 0x00000000U + +// Field: [12] PBE13 +// +// PBE13 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE13 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_M 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_S 12U +#define LRFDDBELL_IMASK2_PBE13_EN 0x00001000U +#define LRFDDBELL_IMASK2_PBE13_DIS 0x00000000U + +// Field: [11] PBE12 +// +// PBE12 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE12 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_M 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_S 11U +#define LRFDDBELL_IMASK2_PBE12_EN 0x00000800U +#define LRFDDBELL_IMASK2_PBE12_DIS 0x00000000U + +// Field: [10] PBE11 +// +// PBE11 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE11 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_M 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_S 10U +#define LRFDDBELL_IMASK2_PBE11_EN 0x00000400U +#define LRFDDBELL_IMASK2_PBE11_DIS 0x00000000U + +// Field: [9] PBE10 +// +// PBE10 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE10 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_M 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_S 9U +#define LRFDDBELL_IMASK2_PBE10_EN 0x00000200U +#define LRFDDBELL_IMASK2_PBE10_DIS 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE8 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_M 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_S 8U +#define LRFDDBELL_IMASK2_PBE8_EN 0x00000100U +#define LRFDDBELL_IMASK2_PBE8_DIS 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE7 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_M 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_S 7U +#define LRFDDBELL_IMASK2_PBE7_EN 0x00000080U +#define LRFDDBELL_IMASK2_PBE7_DIS 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE6 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_M 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_S 6U +#define LRFDDBELL_IMASK2_PBE6_EN 0x00000040U +#define LRFDDBELL_IMASK2_PBE6_DIS 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE5 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_M 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_S 5U +#define LRFDDBELL_IMASK2_PBE5_EN 0x00000020U +#define LRFDDBELL_IMASK2_PBE5_DIS 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE4 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_M 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_S 4U +#define LRFDDBELL_IMASK2_PBE4_EN 0x00000010U +#define LRFDDBELL_IMASK2_PBE4_DIS 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE3 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_M 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_S 3U +#define LRFDDBELL_IMASK2_PBE3_EN 0x00000008U +#define LRFDDBELL_IMASK2_PBE3_DIS 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE2 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_M 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_S 2U +#define LRFDDBELL_IMASK2_PBE2_EN 0x00000004U +#define LRFDDBELL_IMASK2_PBE2_DIS 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE1 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_M 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_S 1U +#define LRFDDBELL_IMASK2_PBE1_EN 0x00000002U +#define LRFDDBELL_IMASK2_PBE1_DIS 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// EN Enable interrupt mask +// DIS Disable interrupt mask +#define LRFDDBELL_IMASK2_PBE0 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_M 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_S 0U +#define LRFDDBELL_IMASK2_PBE0_EN 0x00000001U +#define LRFDDBELL_IMASK2_PBE0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_RIS2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM2 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_S 31U +#define LRFDDBELL_RIS2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_RIS2_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM1 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_S 30U +#define LRFDDBELL_RIS2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_RIS2_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_SYSTIM0 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_S 29U +#define LRFDDBELL_RIS2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_RIS2_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMDONE 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_M 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_S 28U +#define LRFDDBELL_RIS2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_RIS2_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMIN 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_M 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_S 27U +#define LRFDDBELL_RIS2_MDMIN_SET 0x08000000U +#define LRFDDBELL_RIS2_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMOUT 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_M 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_S 26U +#define LRFDDBELL_RIS2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_RIS2_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT2 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_S 25U +#define LRFDDBELL_RIS2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_RIS2_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT1 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_S 24U +#define LRFDDBELL_RIS2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_RIS2_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_MDMSOFT0 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_S 23U +#define LRFDDBELL_RIS2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_RIS2_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFEDONE 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_M 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_S 22U +#define LRFDDBELL_RIS2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_RIS2_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFESOFT1 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_S 21U +#define LRFDDBELL_RIS2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_RIS2_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RFESOFT0 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_S 20U +#define LRFDDBELL_RIS2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_RIS2_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_LOCK 0x00080000U +#define LRFDDBELL_RIS2_LOCK_M 0x00080000U +#define LRFDDBELL_RIS2_LOCK_S 19U +#define LRFDDBELL_RIS2_LOCK_SET 0x00080000U +#define LRFDDBELL_RIS2_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_LOL 0x00040000U +#define LRFDDBELL_RIS2_LOL_M 0x00040000U +#define LRFDDBELL_RIS2_LOL_S 18U +#define LRFDDBELL_RIS2_LOL_SET 0x00040000U +#define LRFDDBELL_RIS2_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_TXFIFO 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_M 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_S 17U +#define LRFDDBELL_RIS2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_RIS2_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_RXFIFO 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_M 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_S 16U +#define LRFDDBELL_RIS2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_RIS2_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE15 0x00008000U +#define LRFDDBELL_RIS2_PBE15_M 0x00008000U +#define LRFDDBELL_RIS2_PBE15_S 15U +#define LRFDDBELL_RIS2_PBE15_SET 0x00008000U +#define LRFDDBELL_RIS2_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE14 0x00004000U +#define LRFDDBELL_RIS2_PBE14_M 0x00004000U +#define LRFDDBELL_RIS2_PBE14_S 14U +#define LRFDDBELL_RIS2_PBE14_SET 0x00004000U +#define LRFDDBELL_RIS2_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE13 0x00002000U +#define LRFDDBELL_RIS2_PBE13_M 0x00002000U +#define LRFDDBELL_RIS2_PBE13_S 13U +#define LRFDDBELL_RIS2_PBE13_SET 0x00002000U +#define LRFDDBELL_RIS2_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE12 0x00001000U +#define LRFDDBELL_RIS2_PBE12_M 0x00001000U +#define LRFDDBELL_RIS2_PBE12_S 12U +#define LRFDDBELL_RIS2_PBE12_SET 0x00001000U +#define LRFDDBELL_RIS2_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE11 0x00000800U +#define LRFDDBELL_RIS2_PBE11_M 0x00000800U +#define LRFDDBELL_RIS2_PBE11_S 11U +#define LRFDDBELL_RIS2_PBE11_SET 0x00000800U +#define LRFDDBELL_RIS2_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE10 0x00000400U +#define LRFDDBELL_RIS2_PBE10_M 0x00000400U +#define LRFDDBELL_RIS2_PBE10_S 10U +#define LRFDDBELL_RIS2_PBE10_SET 0x00000400U +#define LRFDDBELL_RIS2_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE9 0x00000200U +#define LRFDDBELL_RIS2_PBE9_M 0x00000200U +#define LRFDDBELL_RIS2_PBE9_S 9U +#define LRFDDBELL_RIS2_PBE9_SET 0x00000200U +#define LRFDDBELL_RIS2_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE8 0x00000100U +#define LRFDDBELL_RIS2_PBE8_M 0x00000100U +#define LRFDDBELL_RIS2_PBE8_S 8U +#define LRFDDBELL_RIS2_PBE8_SET 0x00000100U +#define LRFDDBELL_RIS2_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE7 0x00000080U +#define LRFDDBELL_RIS2_PBE7_M 0x00000080U +#define LRFDDBELL_RIS2_PBE7_S 7U +#define LRFDDBELL_RIS2_PBE7_SET 0x00000080U +#define LRFDDBELL_RIS2_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE6 0x00000040U +#define LRFDDBELL_RIS2_PBE6_M 0x00000040U +#define LRFDDBELL_RIS2_PBE6_S 6U +#define LRFDDBELL_RIS2_PBE6_SET 0x00000040U +#define LRFDDBELL_RIS2_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE5 0x00000020U +#define LRFDDBELL_RIS2_PBE5_M 0x00000020U +#define LRFDDBELL_RIS2_PBE5_S 5U +#define LRFDDBELL_RIS2_PBE5_SET 0x00000020U +#define LRFDDBELL_RIS2_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE4 0x00000010U +#define LRFDDBELL_RIS2_PBE4_M 0x00000010U +#define LRFDDBELL_RIS2_PBE4_S 4U +#define LRFDDBELL_RIS2_PBE4_SET 0x00000010U +#define LRFDDBELL_RIS2_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE3 0x00000008U +#define LRFDDBELL_RIS2_PBE3_M 0x00000008U +#define LRFDDBELL_RIS2_PBE3_S 3U +#define LRFDDBELL_RIS2_PBE3_SET 0x00000008U +#define LRFDDBELL_RIS2_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE2 0x00000004U +#define LRFDDBELL_RIS2_PBE2_M 0x00000004U +#define LRFDDBELL_RIS2_PBE2_S 2U +#define LRFDDBELL_RIS2_PBE2_SET 0x00000004U +#define LRFDDBELL_RIS2_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE1 0x00000002U +#define LRFDDBELL_RIS2_PBE1_M 0x00000002U +#define LRFDDBELL_RIS2_PBE1_S 1U +#define LRFDDBELL_RIS2_PBE1_SET 0x00000002U +#define LRFDDBELL_RIS2_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_RIS2_PBE0 0x00000001U +#define LRFDDBELL_RIS2_PBE0_M 0x00000001U +#define LRFDDBELL_RIS2_PBE0_S 0U +#define LRFDDBELL_RIS2_PBE0_SET 0x00000001U +#define LRFDDBELL_RIS2_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_MIS2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM2 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_S 31U +#define LRFDDBELL_MIS2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_MIS2_SYSTIM2_CLR 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM1 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_S 30U +#define LRFDDBELL_MIS2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_MIS2_SYSTIM1_CLR 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_SYSTIM0 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_S 29U +#define LRFDDBELL_MIS2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_MIS2_SYSTIM0_CLR 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMDONE 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_M 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_S 28U +#define LRFDDBELL_MIS2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_MIS2_MDMDONE_CLR 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMIN 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_M 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_S 27U +#define LRFDDBELL_MIS2_MDMIN_SET 0x08000000U +#define LRFDDBELL_MIS2_MDMIN_CLR 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMOUT 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_M 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_S 26U +#define LRFDDBELL_MIS2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_MIS2_MDMOUT_CLR 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT2 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_S 25U +#define LRFDDBELL_MIS2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_MIS2_MDMSOFT2_CLR 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT1 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_S 24U +#define LRFDDBELL_MIS2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_MIS2_MDMSOFT1_CLR 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_MDMSOFT0 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_S 23U +#define LRFDDBELL_MIS2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_MIS2_MDMSOFT0_CLR 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFEDONE 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_M 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_S 22U +#define LRFDDBELL_MIS2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_MIS2_RFEDONE_CLR 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFESOFT1 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_S 21U +#define LRFDDBELL_MIS2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_MIS2_RFESOFT1_CLR 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RFESOFT0 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_S 20U +#define LRFDDBELL_MIS2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_MIS2_RFESOFT0_CLR 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_LOCK 0x00080000U +#define LRFDDBELL_MIS2_LOCK_M 0x00080000U +#define LRFDDBELL_MIS2_LOCK_S 19U +#define LRFDDBELL_MIS2_LOCK_SET 0x00080000U +#define LRFDDBELL_MIS2_LOCK_CLR 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_LOL 0x00040000U +#define LRFDDBELL_MIS2_LOL_M 0x00040000U +#define LRFDDBELL_MIS2_LOL_S 18U +#define LRFDDBELL_MIS2_LOL_SET 0x00040000U +#define LRFDDBELL_MIS2_LOL_CLR 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_TXFIFO 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_M 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_S 17U +#define LRFDDBELL_MIS2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_MIS2_TXFIFO_CLR 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_RXFIFO 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_M 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_S 16U +#define LRFDDBELL_MIS2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_MIS2_RXFIFO_CLR 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE15 0x00008000U +#define LRFDDBELL_MIS2_PBE15_M 0x00008000U +#define LRFDDBELL_MIS2_PBE15_S 15U +#define LRFDDBELL_MIS2_PBE15_SET 0x00008000U +#define LRFDDBELL_MIS2_PBE15_CLR 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE14 0x00004000U +#define LRFDDBELL_MIS2_PBE14_M 0x00004000U +#define LRFDDBELL_MIS2_PBE14_S 14U +#define LRFDDBELL_MIS2_PBE14_SET 0x00004000U +#define LRFDDBELL_MIS2_PBE14_CLR 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE13 0x00002000U +#define LRFDDBELL_MIS2_PBE13_M 0x00002000U +#define LRFDDBELL_MIS2_PBE13_S 13U +#define LRFDDBELL_MIS2_PBE13_SET 0x00002000U +#define LRFDDBELL_MIS2_PBE13_CLR 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE12 0x00001000U +#define LRFDDBELL_MIS2_PBE12_M 0x00001000U +#define LRFDDBELL_MIS2_PBE12_S 12U +#define LRFDDBELL_MIS2_PBE12_SET 0x00001000U +#define LRFDDBELL_MIS2_PBE12_CLR 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE11 0x00000800U +#define LRFDDBELL_MIS2_PBE11_M 0x00000800U +#define LRFDDBELL_MIS2_PBE11_S 11U +#define LRFDDBELL_MIS2_PBE11_SET 0x00000800U +#define LRFDDBELL_MIS2_PBE11_CLR 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE10 0x00000400U +#define LRFDDBELL_MIS2_PBE10_M 0x00000400U +#define LRFDDBELL_MIS2_PBE10_S 10U +#define LRFDDBELL_MIS2_PBE10_SET 0x00000400U +#define LRFDDBELL_MIS2_PBE10_CLR 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE9 0x00000200U +#define LRFDDBELL_MIS2_PBE9_M 0x00000200U +#define LRFDDBELL_MIS2_PBE9_S 9U +#define LRFDDBELL_MIS2_PBE9_SET 0x00000200U +#define LRFDDBELL_MIS2_PBE9_CLR 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE8 0x00000100U +#define LRFDDBELL_MIS2_PBE8_M 0x00000100U +#define LRFDDBELL_MIS2_PBE8_S 8U +#define LRFDDBELL_MIS2_PBE8_SET 0x00000100U +#define LRFDDBELL_MIS2_PBE8_CLR 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE7 0x00000080U +#define LRFDDBELL_MIS2_PBE7_M 0x00000080U +#define LRFDDBELL_MIS2_PBE7_S 7U +#define LRFDDBELL_MIS2_PBE7_SET 0x00000080U +#define LRFDDBELL_MIS2_PBE7_CLR 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE6 0x00000040U +#define LRFDDBELL_MIS2_PBE6_M 0x00000040U +#define LRFDDBELL_MIS2_PBE6_S 6U +#define LRFDDBELL_MIS2_PBE6_SET 0x00000040U +#define LRFDDBELL_MIS2_PBE6_CLR 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE5 0x00000020U +#define LRFDDBELL_MIS2_PBE5_M 0x00000020U +#define LRFDDBELL_MIS2_PBE5_S 5U +#define LRFDDBELL_MIS2_PBE5_SET 0x00000020U +#define LRFDDBELL_MIS2_PBE5_CLR 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE4 0x00000010U +#define LRFDDBELL_MIS2_PBE4_M 0x00000010U +#define LRFDDBELL_MIS2_PBE4_S 4U +#define LRFDDBELL_MIS2_PBE4_SET 0x00000010U +#define LRFDDBELL_MIS2_PBE4_CLR 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE3 0x00000008U +#define LRFDDBELL_MIS2_PBE3_M 0x00000008U +#define LRFDDBELL_MIS2_PBE3_S 3U +#define LRFDDBELL_MIS2_PBE3_SET 0x00000008U +#define LRFDDBELL_MIS2_PBE3_CLR 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE2 0x00000004U +#define LRFDDBELL_MIS2_PBE2_M 0x00000004U +#define LRFDDBELL_MIS2_PBE2_S 2U +#define LRFDDBELL_MIS2_PBE2_SET 0x00000004U +#define LRFDDBELL_MIS2_PBE2_CLR 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE1 0x00000002U +#define LRFDDBELL_MIS2_PBE1_M 0x00000002U +#define LRFDDBELL_MIS2_PBE1_S 1U +#define LRFDDBELL_MIS2_PBE1_SET 0x00000002U +#define LRFDDBELL_MIS2_PBE1_CLR 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Interrupt occurred +// CLR Interrupt did not occur +#define LRFDDBELL_MIS2_PBE0 0x00000001U +#define LRFDDBELL_MIS2_PBE0_M 0x00000001U +#define LRFDDBELL_MIS2_PBE0_S 0U +#define LRFDDBELL_MIS2_PBE0_SET 0x00000001U +#define LRFDDBELL_MIS2_PBE0_CLR 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ISET2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM2 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_S 31U +#define LRFDDBELL_ISET2_SYSTIM2_SET 0x80000000U +#define LRFDDBELL_ISET2_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM1 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_S 30U +#define LRFDDBELL_ISET2_SYSTIM1_SET 0x40000000U +#define LRFDDBELL_ISET2_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_SYSTIM0 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_S 29U +#define LRFDDBELL_ISET2_SYSTIM0_SET 0x20000000U +#define LRFDDBELL_ISET2_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMDONE 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_M 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_S 28U +#define LRFDDBELL_ISET2_MDMDONE_SET 0x10000000U +#define LRFDDBELL_ISET2_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMIN 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_M 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_S 27U +#define LRFDDBELL_ISET2_MDMIN_SET 0x08000000U +#define LRFDDBELL_ISET2_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMOUT 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_M 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_S 26U +#define LRFDDBELL_ISET2_MDMOUT_SET 0x04000000U +#define LRFDDBELL_ISET2_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT2 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_S 25U +#define LRFDDBELL_ISET2_MDMSOFT2_SET 0x02000000U +#define LRFDDBELL_ISET2_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT1 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_S 24U +#define LRFDDBELL_ISET2_MDMSOFT1_SET 0x01000000U +#define LRFDDBELL_ISET2_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_MDMSOFT0 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_S 23U +#define LRFDDBELL_ISET2_MDMSOFT0_SET 0x00800000U +#define LRFDDBELL_ISET2_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFEDONE 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_M 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_S 22U +#define LRFDDBELL_ISET2_RFEDONE_SET 0x00400000U +#define LRFDDBELL_ISET2_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFESOFT1 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_S 21U +#define LRFDDBELL_ISET2_RFESOFT1_SET 0x00200000U +#define LRFDDBELL_ISET2_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RFESOFT0 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_S 20U +#define LRFDDBELL_ISET2_RFESOFT0_SET 0x00100000U +#define LRFDDBELL_ISET2_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_LOCK 0x00080000U +#define LRFDDBELL_ISET2_LOCK_M 0x00080000U +#define LRFDDBELL_ISET2_LOCK_S 19U +#define LRFDDBELL_ISET2_LOCK_SET 0x00080000U +#define LRFDDBELL_ISET2_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_LOL 0x00040000U +#define LRFDDBELL_ISET2_LOL_M 0x00040000U +#define LRFDDBELL_ISET2_LOL_S 18U +#define LRFDDBELL_ISET2_LOL_SET 0x00040000U +#define LRFDDBELL_ISET2_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_TXFIFO 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_M 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_S 17U +#define LRFDDBELL_ISET2_TXFIFO_SET 0x00020000U +#define LRFDDBELL_ISET2_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_RXFIFO 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_M 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_S 16U +#define LRFDDBELL_ISET2_RXFIFO_SET 0x00010000U +#define LRFDDBELL_ISET2_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE15 0x00008000U +#define LRFDDBELL_ISET2_PBE15_M 0x00008000U +#define LRFDDBELL_ISET2_PBE15_S 15U +#define LRFDDBELL_ISET2_PBE15_SET 0x00008000U +#define LRFDDBELL_ISET2_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE14 0x00004000U +#define LRFDDBELL_ISET2_PBE14_M 0x00004000U +#define LRFDDBELL_ISET2_PBE14_S 14U +#define LRFDDBELL_ISET2_PBE14_SET 0x00004000U +#define LRFDDBELL_ISET2_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE13 0x00002000U +#define LRFDDBELL_ISET2_PBE13_M 0x00002000U +#define LRFDDBELL_ISET2_PBE13_S 13U +#define LRFDDBELL_ISET2_PBE13_SET 0x00002000U +#define LRFDDBELL_ISET2_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE12 0x00001000U +#define LRFDDBELL_ISET2_PBE12_M 0x00001000U +#define LRFDDBELL_ISET2_PBE12_S 12U +#define LRFDDBELL_ISET2_PBE12_SET 0x00001000U +#define LRFDDBELL_ISET2_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE11 0x00000800U +#define LRFDDBELL_ISET2_PBE11_M 0x00000800U +#define LRFDDBELL_ISET2_PBE11_S 11U +#define LRFDDBELL_ISET2_PBE11_SET 0x00000800U +#define LRFDDBELL_ISET2_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE10 0x00000400U +#define LRFDDBELL_ISET2_PBE10_M 0x00000400U +#define LRFDDBELL_ISET2_PBE10_S 10U +#define LRFDDBELL_ISET2_PBE10_SET 0x00000400U +#define LRFDDBELL_ISET2_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE9 0x00000200U +#define LRFDDBELL_ISET2_PBE9_M 0x00000200U +#define LRFDDBELL_ISET2_PBE9_S 9U +#define LRFDDBELL_ISET2_PBE9_SET 0x00000200U +#define LRFDDBELL_ISET2_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE8 0x00000100U +#define LRFDDBELL_ISET2_PBE8_M 0x00000100U +#define LRFDDBELL_ISET2_PBE8_S 8U +#define LRFDDBELL_ISET2_PBE8_SET 0x00000100U +#define LRFDDBELL_ISET2_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE7 0x00000080U +#define LRFDDBELL_ISET2_PBE7_M 0x00000080U +#define LRFDDBELL_ISET2_PBE7_S 7U +#define LRFDDBELL_ISET2_PBE7_SET 0x00000080U +#define LRFDDBELL_ISET2_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE6 0x00000040U +#define LRFDDBELL_ISET2_PBE6_M 0x00000040U +#define LRFDDBELL_ISET2_PBE6_S 6U +#define LRFDDBELL_ISET2_PBE6_SET 0x00000040U +#define LRFDDBELL_ISET2_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE5 0x00000020U +#define LRFDDBELL_ISET2_PBE5_M 0x00000020U +#define LRFDDBELL_ISET2_PBE5_S 5U +#define LRFDDBELL_ISET2_PBE5_SET 0x00000020U +#define LRFDDBELL_ISET2_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE4 0x00000010U +#define LRFDDBELL_ISET2_PBE4_M 0x00000010U +#define LRFDDBELL_ISET2_PBE4_S 4U +#define LRFDDBELL_ISET2_PBE4_SET 0x00000010U +#define LRFDDBELL_ISET2_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE3 0x00000008U +#define LRFDDBELL_ISET2_PBE3_M 0x00000008U +#define LRFDDBELL_ISET2_PBE3_S 3U +#define LRFDDBELL_ISET2_PBE3_SET 0x00000008U +#define LRFDDBELL_ISET2_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE2 0x00000004U +#define LRFDDBELL_ISET2_PBE2_M 0x00000004U +#define LRFDDBELL_ISET2_PBE2_S 2U +#define LRFDDBELL_ISET2_PBE2_SET 0x00000004U +#define LRFDDBELL_ISET2_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE1 0x00000002U +#define LRFDDBELL_ISET2_PBE1_M 0x00000002U +#define LRFDDBELL_ISET2_PBE1_S 1U +#define LRFDDBELL_ISET2_PBE1_SET 0x00000002U +#define LRFDDBELL_ISET2_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// SET Set Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ISET2_PBE0 0x00000001U +#define LRFDDBELL_ISET2_PBE0_M 0x00000001U +#define LRFDDBELL_ISET2_PBE0_S 0U +#define LRFDDBELL_ISET2_PBE0_SET 0x00000001U +#define LRFDDBELL_ISET2_PBE0_NOEFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDDBELL_O_ICLR2 +// +//***************************************************************************** +// Field: [31] SYSTIM2 +// +// SYSTIM2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM2 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_M 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_S 31U +#define LRFDDBELL_ICLR2_SYSTIM2_CLR 0x80000000U +#define LRFDDBELL_ICLR2_SYSTIM2_NOEFF 0x00000000U + +// Field: [30] SYSTIM1 +// +// SYSTIM1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM1 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_M 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_S 30U +#define LRFDDBELL_ICLR2_SYSTIM1_CLR 0x40000000U +#define LRFDDBELL_ICLR2_SYSTIM1_NOEFF 0x00000000U + +// Field: [29] SYSTIM0 +// +// SYSTIM0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_SYSTIM0 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_M 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_S 29U +#define LRFDDBELL_ICLR2_SYSTIM0_CLR 0x20000000U +#define LRFDDBELL_ICLR2_SYSTIM0_NOEFF 0x00000000U + +// Field: [28] MDMDONE +// +// MDMDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMDONE 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_M 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_S 28U +#define LRFDDBELL_ICLR2_MDMDONE_CLR 0x10000000U +#define LRFDDBELL_ICLR2_MDMDONE_NOEFF 0x00000000U + +// Field: [27] MDMIN +// +// MDMIN event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMIN 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_M 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_S 27U +#define LRFDDBELL_ICLR2_MDMIN_CLR 0x08000000U +#define LRFDDBELL_ICLR2_MDMIN_NOEFF 0x00000000U + +// Field: [26] MDMOUT +// +// MDMOUT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMOUT 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_M 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_S 26U +#define LRFDDBELL_ICLR2_MDMOUT_CLR 0x04000000U +#define LRFDDBELL_ICLR2_MDMOUT_NOEFF 0x00000000U + +// Field: [25] MDMSOFT2 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT2 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_M 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_S 25U +#define LRFDDBELL_ICLR2_MDMSOFT2_CLR 0x02000000U +#define LRFDDBELL_ICLR2_MDMSOFT2_NOEFF 0x00000000U + +// Field: [24] MDMSOFT1 +// +// MDMSOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT1 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_M 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_S 24U +#define LRFDDBELL_ICLR2_MDMSOFT1_CLR 0x01000000U +#define LRFDDBELL_ICLR2_MDMSOFT1_NOEFF 0x00000000U + +// Field: [23] MDMSOFT0 +// +// MDMSOFT event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_MDMSOFT0 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_M 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_S 23U +#define LRFDDBELL_ICLR2_MDMSOFT0_CLR 0x00800000U +#define LRFDDBELL_ICLR2_MDMSOFT0_NOEFF 0x00000000U + +// Field: [22] RFEDONE +// +// RFEDONE event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFEDONE 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_M 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_S 22U +#define LRFDDBELL_ICLR2_RFEDONE_CLR 0x00400000U +#define LRFDDBELL_ICLR2_RFEDONE_NOEFF 0x00000000U + +// Field: [21] RFESOFT1 +// +// RFESOFT1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFESOFT1 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_M 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_S 21U +#define LRFDDBELL_ICLR2_RFESOFT1_CLR 0x00200000U +#define LRFDDBELL_ICLR2_RFESOFT1_NOEFF 0x00000000U + +// Field: [20] RFESOFT0 +// +// RFESOFT0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RFESOFT0 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_M 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_S 20U +#define LRFDDBELL_ICLR2_RFESOFT0_CLR 0x00100000U +#define LRFDDBELL_ICLR2_RFESOFT0_NOEFF 0x00000000U + +// Field: [19] LOCK +// +// LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_LOCK 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_M 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_S 19U +#define LRFDDBELL_ICLR2_LOCK_CLR 0x00080000U +#define LRFDDBELL_ICLR2_LOCK_NOEFF 0x00000000U + +// Field: [18] LOL +// +// LOSS_OF_LOCK event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_LOL 0x00040000U +#define LRFDDBELL_ICLR2_LOL_M 0x00040000U +#define LRFDDBELL_ICLR2_LOL_S 18U +#define LRFDDBELL_ICLR2_LOL_CLR 0x00040000U +#define LRFDDBELL_ICLR2_LOL_NOEFF 0x00000000U + +// Field: [17] TXFIFO +// +// TXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_TXFIFO 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_M 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_S 17U +#define LRFDDBELL_ICLR2_TXFIFO_CLR 0x00020000U +#define LRFDDBELL_ICLR2_TXFIFO_NOEFF 0x00000000U + +// Field: [16] RXFIFO +// +// RXFIFO event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_RXFIFO 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_M 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_S 16U +#define LRFDDBELL_ICLR2_RXFIFO_CLR 0x00010000U +#define LRFDDBELL_ICLR2_RXFIFO_NOEFF 0x00000000U + +// Field: [15] PBE15 +// +// PBE15 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE15 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_M 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_S 15U +#define LRFDDBELL_ICLR2_PBE15_CLR 0x00008000U +#define LRFDDBELL_ICLR2_PBE15_NOEFF 0x00000000U + +// Field: [14] PBE14 +// +// PBE14 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE14 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_M 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_S 14U +#define LRFDDBELL_ICLR2_PBE14_CLR 0x00004000U +#define LRFDDBELL_ICLR2_PBE14_NOEFF 0x00000000U + +// Field: [13] PBE13 +// +// PBE13 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE13 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_M 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_S 13U +#define LRFDDBELL_ICLR2_PBE13_CLR 0x00002000U +#define LRFDDBELL_ICLR2_PBE13_NOEFF 0x00000000U + +// Field: [12] PBE12 +// +// PBE12 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE12 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_M 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_S 12U +#define LRFDDBELL_ICLR2_PBE12_CLR 0x00001000U +#define LRFDDBELL_ICLR2_PBE12_NOEFF 0x00000000U + +// Field: [11] PBE11 +// +// PBE11 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE11 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_M 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_S 11U +#define LRFDDBELL_ICLR2_PBE11_CLR 0x00000800U +#define LRFDDBELL_ICLR2_PBE11_NOEFF 0x00000000U + +// Field: [10] PBE10 +// +// PBE10 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE10 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_M 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_S 10U +#define LRFDDBELL_ICLR2_PBE10_CLR 0x00000400U +#define LRFDDBELL_ICLR2_PBE10_NOEFF 0x00000000U + +// Field: [9] PBE9 +// +// PBE9 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE9 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_M 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_S 9U +#define LRFDDBELL_ICLR2_PBE9_CLR 0x00000200U +#define LRFDDBELL_ICLR2_PBE9_NOEFF 0x00000000U + +// Field: [8] PBE8 +// +// PBE8 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE8 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_M 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_S 8U +#define LRFDDBELL_ICLR2_PBE8_CLR 0x00000100U +#define LRFDDBELL_ICLR2_PBE8_NOEFF 0x00000000U + +// Field: [7] PBE7 +// +// PBE7 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE7 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_M 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_S 7U +#define LRFDDBELL_ICLR2_PBE7_CLR 0x00000080U +#define LRFDDBELL_ICLR2_PBE7_NOEFF 0x00000000U + +// Field: [6] PBE6 +// +// PBE6 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE6 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_M 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_S 6U +#define LRFDDBELL_ICLR2_PBE6_CLR 0x00000040U +#define LRFDDBELL_ICLR2_PBE6_NOEFF 0x00000000U + +// Field: [5] PBE5 +// +// PBE5 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE5 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_M 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_S 5U +#define LRFDDBELL_ICLR2_PBE5_CLR 0x00000020U +#define LRFDDBELL_ICLR2_PBE5_NOEFF 0x00000000U + +// Field: [4] PBE4 +// +// PBE4 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE4 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_M 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_S 4U +#define LRFDDBELL_ICLR2_PBE4_CLR 0x00000010U +#define LRFDDBELL_ICLR2_PBE4_NOEFF 0x00000000U + +// Field: [3] PBE3 +// +// PBE3 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE3 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_M 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_S 3U +#define LRFDDBELL_ICLR2_PBE3_CLR 0x00000008U +#define LRFDDBELL_ICLR2_PBE3_NOEFF 0x00000000U + +// Field: [2] PBE2 +// +// PBE2 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE2 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_M 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_S 2U +#define LRFDDBELL_ICLR2_PBE2_CLR 0x00000004U +#define LRFDDBELL_ICLR2_PBE2_NOEFF 0x00000000U + +// Field: [1] PBE1 +// +// PBE1 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE1 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_M 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_S 1U +#define LRFDDBELL_ICLR2_PBE1_CLR 0x00000002U +#define LRFDDBELL_ICLR2_PBE1_NOEFF 0x00000000U + +// Field: [0] PBE0 +// +// PBE0 event +// ENUMs: +// CLR Clear Interrupt +// NOEFF Writing 0 has no effect +#define LRFDDBELL_ICLR2_PBE0 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_M 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_S 0U +#define LRFDDBELL_ICLR2_PBE0_CLR 0x00000001U +#define LRFDDBELL_ICLR2_PBE0_NOEFF 0x00000000U + + +#endif // __LRFDDBELL__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm.h new file mode 100644 index 00000000..1119204e --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm.h @@ -0,0 +1,7158 @@ +/****************************************************************************** +* Filename: hw_lrfdmdm_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDMDM_H__ +#define __HW_LRFDMDM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDMDM component +// +//***************************************************************************** +// Modem Enable Register +#define LRFDMDM_O_ENABLE 0x00000000U + +// MCE program source select register +#define LRFDMDM_O_FWSRC 0x00000004U + +// Modem Initialize Register +#define LRFDMDM_O_INIT 0x00000008U + +// Demodulator Enable Register 0 +#define LRFDMDM_O_DEMENABLE0 0x00000010U + +// Demodulator Enable Register 1 +#define LRFDMDM_O_DEMENABLE1 0x00000014U + +// Demodulator Initialize Register 0 +#define LRFDMDM_O_DEMINIT0 0x00000018U + +// Demodulator Initialize Register 1 +#define LRFDMDM_O_DEMINIT1 0x0000001CU + +// Modem Command Engine (MCE) Strobe Register 0 +#define LRFDMDM_O_STRB0 0x00000020U + +// Modem Command Engine (MCE) Strobe Register 1 +#define LRFDMDM_O_STRB1 0x00000024U + +// MCE Event Flag Register 0 +#define LRFDMDM_O_EVT0 0x00000028U + +// MCE Event Flag Register 1 +#define LRFDMDM_O_EVT1 0x0000002CU + +// MCE Event Flag Register 2 +#define LRFDMDM_O_EVT2 0x00000030U + +// MCE Event Mask Register 0 +#define LRFDMDM_O_EVTMSK0 0x00000038U + +// MCE Event Mask Register 1 +#define LRFDMDM_O_EVTMSK1 0x0000003CU + +// MCE Event Mask Register 2 +#define LRFDMDM_O_EVTMSK2 0x00000040U + +// MCE Event Clear Register 0 +#define LRFDMDM_O_EVTCLR0 0x00000048U + +// MCE Event Clear Register 1 +#define LRFDMDM_O_EVTCLR1 0x0000004CU + +// MCE Event Clear Register 2 +#define LRFDMDM_O_EVTCLR2 0x00000050U + +// Modem Power Down Request Register +#define LRFDMDM_O_PDREQ 0x00000058U + +// Modem API Command Register +#define LRFDMDM_O_API 0x0000005CU + +// Modem API Command Parameter 0 +#define LRFDMDM_O_CMDPAR0 0x00000060U + +// Modem API Command Parameter 1 +#define LRFDMDM_O_CMDPAR1 0x00000064U + +// Modem API Command Parameter 2 +#define LRFDMDM_O_CMDPAR2 0x00000068U + +// Modem Command Status Register +#define LRFDMDM_O_MSGBOX 0x0000006CU + +// Frequency Offset +#define LRFDMDM_O_FREQ 0x00000070U + +// Modem FIFO Write Register +#define LRFDMDM_O_FIFOWR 0x00000074U + +// Modem FIFO Read Register +#define LRFDMDM_O_FIFORD 0x00000078U + +// Modem FIFO Write Configuration +#define LRFDMDM_O_FIFOWRCTRL 0x00000080U + +// Modem FIFO Read Configuration +#define LRFDMDM_O_FIFORDCTRL 0x00000084U + +// Modem FIFO Status Flags +#define LRFDMDM_O_FIFOSTA 0x0000008CU + +// MCE-to-RFE Send Data Register +#define LRFDMDM_O_RFEDATOUT0 0x00000090U + +// RFE-to-MCE Receive Data Register +#define LRFDMDM_O_RFEDATIN0 0x00000094U + +// MCE-to-RFE Send Command Register +#define LRFDMDM_O_RFECMDOUT 0x00000098U + +// RFE-to-MCE Receive Command Register +#define LRFDMDM_O_RFECMDIN 0x0000009CU + +// MCE-to-PBE Send Data Register +#define LRFDMDM_O_PBEDATOUT0 0x000000A0U + +// RFE-to-MCE Receive Data Register +#define LRFDMDM_O_PBEDATIN0 0x000000A4U + +// MCE-to-PBE Send Command Register +#define LRFDMDM_O_PBECMDOUT 0x000000A8U + +// PBE-to-MCE Receive Command Register +#define LRFDMDM_O_PBECMDIN 0x000000ACU + +// Link quality indicator +#define LRFDMDM_O_LQIEST 0x000000B0U + +// PBE event mux +#define LRFDMDM_O_PBEEVTMUX 0x000000B4U + +// SYSTIME event mux 0 +#define LRFDMDM_O_SYSTIMEVTMUX0 0x000000B8U + +// SYSTIME event mux 1 +#define LRFDMDM_O_SYSTIMEVTMUX1 0x000000BCU + +// ADC Digital Interface Configuration +#define LRFDMDM_O_ADCDIGCONF 0x000000C0U + +// Modulator Preamble Control +#define LRFDMDM_O_MODPRECTRL 0x000000C4U + +// Modulator Symbol Mapping Register 0 +#define LRFDMDM_O_MODSYMMAP0 0x000000C8U + +// Modulator Symbol Mapping Register 1 +#define LRFDMDM_O_MODSYMMAP1 0x000000CCU + +// Modulator Soft Symbol Transmit +#define LRFDMDM_O_MODSOFTTX 0x000000D0U + +// Modem Baud Rate Control +#define LRFDMDM_O_BAUD 0x000000D4U + +// Modem Baud Rate Prescaler Control +#define LRFDMDM_O_BAUDPRE 0x000000D8U + +// Modulator Main Config Register +#define LRFDMDM_O_MODMAIN 0x000000DCU + +// Demodulator Config Register 0 +#define LRFDMDM_O_DEMMISC0 0x000000E0U + +// Demodulator Config Register 1 +#define LRFDMDM_O_DEMMISC1 0x000000E4U + +// Demodulator Config Register 2 +#define LRFDMDM_O_DEMMISC2 0x000000E8U + +// Demodulator Config Register 3 +#define LRFDMDM_O_DEMMISC3 0x000000ECU + +// Demodulator I/Q Mismatch Compensation Register +#define LRFDMDM_O_DEMIQMC0 0x000000F0U + +// Dynamic Sample Buffer Config Register +#define LRFDMDM_O_DEMDSBU 0x000000F4U + +// Demodulator Coarse DC Offset Estimator Register 0 +#define LRFDMDM_O_DEMCODC0 0x000000F8U + +// Demodulator Fine DC Offset Estimator Register 0 +#define LRFDMDM_O_DEMFIDC0 0x000000FCU + +// Demodulator Front-End Crossbar Register 0 +#define LRFDMDM_O_DEMFEXB0 0x00000100U + +// Demodulator Decode Stage Crossbar Register 0 +#define LRFDMDM_O_DEMDSXB0 0x00000104U + +// Demodulator Fine Frequency Offset Estimator Register 0 +#define LRFDMDM_O_DEMFIFE0 0x00000108U + +// Demodulator Matched Filter Register 0 +#define LRFDMDM_O_DEMMAFI0 0x0000010CU + +// Demodulator Matched Filter Register 1 +#define LRFDMDM_O_DEMMAFI1 0x00000110U + +// Demodulator Matched Filter Register 2 +#define LRFDMDM_O_DEMMAFI2 0x00000114U + +// Demodulator Correlator 1-bit Engine Register 0 +#define LRFDMDM_O_DEMC1BE0 0x00000118U + +// Demodulator Correlator 1-bit Engine Register 1 +#define LRFDMDM_O_DEMC1BE1 0x0000011CU + +// Demodulator Correlator 1-bit Engine Register 2 +#define LRFDMDM_O_DEMC1BE2 0x00000120U + +// Modem Spare 0 +#define LRFDMDM_O_SPARE0 0x00000124U + +// Modem Spare 1 +#define LRFDMDM_O_SPARE1 0x00000128U + +// Modem Spare 2 +#define LRFDMDM_O_SPARE2 0x0000012CU + +// Modem Spare 3 +#define LRFDMDM_O_SPARE3 0x00000130U + +// Demodulator Sync Word Qualifier Register 0 +#define LRFDMDM_O_DEMSWQU0 0x00000134U + +// Correlator reference register 0 +#define LRFDMDM_O_DEMC1BEREF0 0x00000138U + +// Correlator reference register 1 +#define LRFDMDM_O_DEMC1BEREF1 0x0000013CU + +// Correlator reference register 2 +#define LRFDMDM_O_DEMC1BEREF2 0x00000140U + +// Correlator reference register 3 +#define LRFDMDM_O_DEMC1BEREF3 0x00000144U + +// Dynamic Modem Control Signals from MCE +#define LRFDMDM_O_MODCTRL 0x00000148U + +// Dynamic Modulator Preamble Register +#define LRFDMDM_O_MODPREAMBLE 0x0000014CU + +// Demodulator Fractional Resampler Register 0 +#define LRFDMDM_O_DEMFRAC0 0x00000150U + +// Demodulator Fractional Resampler Register 1 +#define LRFDMDM_O_DEMFRAC1 0x00000154U + +// Demodulator Fractional Resampler Register 2 +#define LRFDMDM_O_DEMFRAC2 0x00000158U + +// Demodulator Fractional Resampler Register 3 +#define LRFDMDM_O_DEMFRAC3 0x0000015CU + +// Demodulator Coarse DC Offset Estimator Register 1 +#define LRFDMDM_O_DEMCODC1 0x00000160U + +// Demodulator Coarse DC Offset Estimator Register 2 +#define LRFDMDM_O_DEMCODC2 0x00000164U + +// Demodulator Fine DC Offset Estimator Register 1 +#define LRFDMDM_O_DEMFIDC1 0x00000168U + +// Demodulator Fine DC Offset Estimator Register 2 +#define LRFDMDM_O_DEMFIDC2 0x0000016CU + +// Demodulator Fine Frequency Offset Estimator Register 1 +#define LRFDMDM_O_DEMFIFE1 0x00000170U + +// Demodulator Manual Frequency Compensation Register 0 +#define LRFDMDM_O_DEMMAFC0 0x00000174U + +// Demodulator Matched Filter Register 4 +#define LRFDMDM_O_DEMMAFI4 0x00000178U + +// Demodulator Sync Word DC Imbalance Register +#define LRFDMDM_O_DEMSWIMBAL 0x0000017CU + +// Demodulator Soft PDIFF Value Register +#define LRFDMDM_O_DEMSOFTPDIFF 0x00000180U + +// Demodulator Debug Register +#define LRFDMDM_O_DEMDEBUG 0x00000184U + +// Viterbi Control Register +#define LRFDMDM_O_VITCTRL 0x00000188U + +// Viterbi Compute Register +#define LRFDMDM_O_VITCOMPUTE 0x0000018CU + +// Viterbi APM Readback Register +#define LRFDMDM_O_VITAPMRDBACK 0x00000190U + +// Viterbi State Register +#define LRFDMDM_O_VITSTATE 0x00000194U + +// Viterbi Branch Metric 1 and 0 Register +#define LRFDMDM_O_VITBRMETRIC10 0x00000198U + +// Viterbi Branch Metric 3 and 2 Register +#define LRFDMDM_O_VITBRMETRIC32 0x0000019CU + +// Viterbi Branch Metric 5 and 4 Register +#define LRFDMDM_O_VITBRMETRIC54 0x000001A0U + +// Viterbi Branch Metric 7 and 6 Register +#define LRFDMDM_O_VITBRMETRIC76 0x000001A4U + +// Modem Timer and Counter Control Register +#define LRFDMDM_O_TIMCTL 0x000001E4U + +// Modem Counter Increment Configuration +#define LRFDMDM_O_TIMINC 0x000001E8U + +// Modem Timer/Counter Period Configuration +#define LRFDMDM_O_TIMPER 0x000001ECU + +// Modem Counter Value +#define LRFDMDM_O_TIMCNT 0x000001F0U + +// Modem Counter Capture Value +#define LRFDMDM_O_TIMCAPT 0x000001F4U + +// Modem Timebase Control Register +#define LRFDMDM_O_TIMEBASE 0x000001F8U + +// Local Count Ones Input Register +#define LRFDMDM_O_COUNT1IN 0x000001FCU + +// Local Count Ones Result Register +#define LRFDMDM_O_COUNT1RES 0x00000200U + +// Local Branch Metric Accelerator Module Register 1 +#define LRFDMDM_O_BRMACC1 0x00000208U + +// Local Branch Metric Accelerator Module Register 2 +#define LRFDMDM_O_BRMACC2 0x0000020CU + +// MCE Tracer Send Trigger Register +#define LRFDMDM_O_MCETRCCTRL 0x00000210U + +// MCE Tracer Status Register +#define LRFDMDM_O_MCETRCSTAT 0x00000214U + +// MCE Tracer Command Register +#define LRFDMDM_O_MCETRCCMD 0x00000218U + +// MCE Tracer Command Parameter Register 0 +#define LRFDMDM_O_MCETRCPAR0 0x0000021CU + +// MCE Tracer Command Parameter Register 1 +#define LRFDMDM_O_MCETRCPAR1 0x00000220U + +// Modem Readback Capture Register 0 +#define LRFDMDM_O_RDCAPT0 0x00000224U + +// Modem Readback Capture Register 1 +#define LRFDMDM_O_RDCAPT1 0x00000228U + +// Frontend capture readback register 0 +#define LRFDMDM_O_FECAPT0 0x0000022CU + +// Frontend capture readback register 1 +#define LRFDMDM_O_FECAPT1 0x00000230U + +// Decoding stage capture register 0 +#define LRFDMDM_O_DSCAPT0 0x00000234U + +// Decoding stage capture register 1 +#define LRFDMDM_O_DSCAPT1 0x00000238U + +// Decoding stage capture register 2 +#define LRFDMDM_O_DSCAPT2 0x0000023CU + +// Decoding stage capture register 3 +#define LRFDMDM_O_DSCAPT3 0x00000240U + +// Demodulator sync word qualifier register 1 +#define LRFDMDM_O_DEMSWQU1 0x00000244U + +// Control of the MCE GPO signals +#define LRFDMDM_O_GPOCTRL0 0x00000248U + +// Control of the MCE GPO signals +#define LRFDMDM_O_GPOCTRL1 0x0000024CU + +// RFE received signal strength indicator +#define LRFDMDM_O_RFERSSI 0x00000250U + +// RFE received signal strength indicator +#define LRFDMDM_O_RFEMAXRSSI 0x00000254U + +// RFE front end gain setting +#define LRFDMDM_O_RFEDBGAIN 0x00000258U + +// Modem Sync Word Register 0 +#define LRFDMDM_O_SYNC0 0x0000025CU + +// Modem Sync Word Register 1 +#define LRFDMDM_O_SYNC1 0x00000260U + +// Modem Sync Word Register 2 +#define LRFDMDM_O_SYNC2 0x00000264U + +// Modem Sync Word Register 3 +#define LRFDMDM_O_SYNC3 0x00000268U + +//***************************************************************************** +// +// Register: LRFDMDM_O_ENABLE +// +//***************************************************************************** +// Field: [5] ADCDIG +// +// Enables the ADC Digital interface +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_ADCDIG 0x00000020U +#define LRFDMDM_ENABLE_ADCDIG_M 0x00000020U +#define LRFDMDM_ENABLE_ADCDIG_S 5U +#define LRFDMDM_ENABLE_ADCDIG_EN 0x00000020U +#define LRFDMDM_ENABLE_ADCDIG_DIS 0x00000000U + +// Field: [4] DEMODULATOR +// +// Enables the Demodulator +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_DEMODULATOR 0x00000010U +#define LRFDMDM_ENABLE_DEMODULATOR_M 0x00000010U +#define LRFDMDM_ENABLE_DEMODULATOR_S 4U +#define LRFDMDM_ENABLE_DEMODULATOR_EN 0x00000010U +#define LRFDMDM_ENABLE_DEMODULATOR_DIS 0x00000000U + +// Field: [3] MODULATOR +// +// Enables the Modulator +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_MODULATOR 0x00000008U +#define LRFDMDM_ENABLE_MODULATOR_M 0x00000008U +#define LRFDMDM_ENABLE_MODULATOR_S 3U +#define LRFDMDM_ENABLE_MODULATOR_EN 0x00000008U +#define LRFDMDM_ENABLE_MODULATOR_DIS 0x00000000U + +// Field: [2] TIMEBASE +// +// Enables the Modem Timebase +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_TIMEBASE 0x00000004U +#define LRFDMDM_ENABLE_TIMEBASE_M 0x00000004U +#define LRFDMDM_ENABLE_TIMEBASE_S 2U +#define LRFDMDM_ENABLE_TIMEBASE_EN 0x00000004U +#define LRFDMDM_ENABLE_TIMEBASE_DIS 0x00000000U + +// Field: [1] TXRXFIFO +// +// Enables the TX/RX FIFO +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_TXRXFIFO 0x00000002U +#define LRFDMDM_ENABLE_TXRXFIFO_M 0x00000002U +#define LRFDMDM_ENABLE_TXRXFIFO_S 1U +#define LRFDMDM_ENABLE_TXRXFIFO_EN 0x00000002U +#define LRFDMDM_ENABLE_TXRXFIFO_DIS 0x00000000U + +// Field: [0] TOPSM +// +// Enables the TOPsm (MCE) +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM_ENABLE_TOPSM 0x00000001U +#define LRFDMDM_ENABLE_TOPSM_M 0x00000001U +#define LRFDMDM_ENABLE_TOPSM_S 0U +#define LRFDMDM_ENABLE_TOPSM_EN 0x00000001U +#define LRFDMDM_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FWSRC +// +//***************************************************************************** +// Field: [2] DATARAM +// +// Selects which RAM will be used for data storage +// ENUMs: +// S2RRAM Use S2RRAM for data +// MDMRAM Use MDMRAM for data +#define LRFDMDM_FWSRC_DATARAM 0x00000004U +#define LRFDMDM_FWSRC_DATARAM_M 0x00000004U +#define LRFDMDM_FWSRC_DATARAM_S 2U +#define LRFDMDM_FWSRC_DATARAM_S2RRAM 0x00000004U +#define LRFDMDM_FWSRC_DATARAM_MDMRAM 0x00000000U + +// Field: [1] FWRAM +// +// Select which RAM we run FW from +// ENUMs: +// S2RRAM Run code from S2RRAM +// MDMRAM Run code from MDMRAM +#define LRFDMDM_FWSRC_FWRAM 0x00000002U +#define LRFDMDM_FWSRC_FWRAM_M 0x00000002U +#define LRFDMDM_FWSRC_FWRAM_S 1U +#define LRFDMDM_FWSRC_FWRAM_S2RRAM 0x00000002U +#define LRFDMDM_FWSRC_FWRAM_MDMRAM 0x00000000U + +// Field: [0] BANK +// +// Sets the MSB of the address to the memory holding the program +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDMDM_FWSRC_BANK 0x00000001U +#define LRFDMDM_FWSRC_BANK_M 0x00000001U +#define LRFDMDM_FWSRC_BANK_S 0U +#define LRFDMDM_FWSRC_BANK_ONE 0x00000001U +#define LRFDMDM_FWSRC_BANK_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_INIT +// +//***************************************************************************** +// Field: [5] ADCDIG +// +// Synch reset ADC Digital interface +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_ADCDIG 0x00000020U +#define LRFDMDM_INIT_ADCDIG_M 0x00000020U +#define LRFDMDM_INIT_ADCDIG_S 5U +#define LRFDMDM_INIT_ADCDIG_RESET 0x00000020U +#define LRFDMDM_INIT_ADCDIG_NO_EFFECT 0x00000000U + +// Field: [4] DEMODULATOR +// +// Synch reset Demodulator +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_DEMODULATOR 0x00000010U +#define LRFDMDM_INIT_DEMODULATOR_M 0x00000010U +#define LRFDMDM_INIT_DEMODULATOR_S 4U +#define LRFDMDM_INIT_DEMODULATOR_RESET 0x00000010U +#define LRFDMDM_INIT_DEMODULATOR_NO_EFFECT 0x00000000U + +// Field: [3] MODULATOR +// +// Synch reset Modulator +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_MODULATOR 0x00000008U +#define LRFDMDM_INIT_MODULATOR_M 0x00000008U +#define LRFDMDM_INIT_MODULATOR_S 3U +#define LRFDMDM_INIT_MODULATOR_RESET 0x00000008U +#define LRFDMDM_INIT_MODULATOR_NO_EFFECT 0x00000000U + +// Field: [2] TIMEBASE +// +// Synch reset Modem Timebase +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_TIMEBASE 0x00000004U +#define LRFDMDM_INIT_TIMEBASE_M 0x00000004U +#define LRFDMDM_INIT_TIMEBASE_S 2U +#define LRFDMDM_INIT_TIMEBASE_RESET 0x00000004U +#define LRFDMDM_INIT_TIMEBASE_NO_EFFECT 0x00000000U + +// Field: [1] TXRXFIFO +// +// Synch reset TX/RX FIFO +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_TXRXFIFO 0x00000002U +#define LRFDMDM_INIT_TXRXFIFO_M 0x00000002U +#define LRFDMDM_INIT_TXRXFIFO_S 1U +#define LRFDMDM_INIT_TXRXFIFO_RESET 0x00000002U +#define LRFDMDM_INIT_TXRXFIFO_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// Synch reset TOPsm (MCE) +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_INIT_TOPSM 0x00000001U +#define LRFDMDM_INIT_TOPSM_M 0x00000001U +#define LRFDMDM_INIT_TOPSM_S 0U +#define LRFDMDM_INIT_TOPSM_RESET 0x00000001U +#define LRFDMDM_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMENABLE0 +// +//***************************************************************************** +// Field: [8] FRAC +// +// Enables the fractional resampler +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_FRAC 0x00000100U +#define LRFDMDM_DEMENABLE0_FRAC_M 0x00000100U +#define LRFDMDM_DEMENABLE0_FRAC_S 8U +#define LRFDMDM_DEMENABLE0_FRAC_EN 0x00000100U +#define LRFDMDM_DEMENABLE0_FRAC_DIS 0x00000000U + +// Field: [7] FIDC +// +// Enables the fine DC estimator +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_FIDC 0x00000080U +#define LRFDMDM_DEMENABLE0_FIDC_M 0x00000080U +#define LRFDMDM_DEMENABLE0_FIDC_S 7U +#define LRFDMDM_DEMENABLE0_FIDC_EN 0x00000080U +#define LRFDMDM_DEMENABLE0_FIDC_DIS 0x00000000U + +// Field: [6] CHFI +// +// Enables the channel filter +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_CHFI 0x00000040U +#define LRFDMDM_DEMENABLE0_CHFI_M 0x00000040U +#define LRFDMDM_DEMENABLE0_CHFI_S 6U +#define LRFDMDM_DEMENABLE0_CHFI_EN 0x00000040U +#define LRFDMDM_DEMENABLE0_CHFI_DIS 0x00000000U + +// Field: [5] BDEC +// +// Enables the cascaded dec-by-2 stages (bde1 and bde2) +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_BDEC 0x00000020U +#define LRFDMDM_DEMENABLE0_BDEC_M 0x00000020U +#define LRFDMDM_DEMENABLE0_BDEC_S 5U +#define LRFDMDM_DEMENABLE0_BDEC_EN 0x00000020U +#define LRFDMDM_DEMENABLE0_BDEC_DIS 0x00000000U + +// Field: [4] IQMC +// +// Enables the IQ mismatch compensation +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_IQMC 0x00000010U +#define LRFDMDM_DEMENABLE0_IQMC_M 0x00000010U +#define LRFDMDM_DEMENABLE0_IQMC_S 4U +#define LRFDMDM_DEMENABLE0_IQMC_EN 0x00000010U +#define LRFDMDM_DEMENABLE0_IQMC_DIS 0x00000000U + +// Field: [3] MGE1 +// +// Enables the magnitude estimator engine #1 +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_MGE1 0x00000008U +#define LRFDMDM_DEMENABLE0_MGE1_M 0x00000008U +#define LRFDMDM_DEMENABLE0_MGE1_S 3U +#define LRFDMDM_DEMENABLE0_MGE1_EN 0x00000008U +#define LRFDMDM_DEMENABLE0_MGE1_DIS 0x00000000U + +// Field: [2] MGE0 +// +// Enables the magnitude estimator engine #0 +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_MGE0 0x00000004U +#define LRFDMDM_DEMENABLE0_MGE0_M 0x00000004U +#define LRFDMDM_DEMENABLE0_MGE0_S 2U +#define LRFDMDM_DEMENABLE0_MGE0_EN 0x00000004U +#define LRFDMDM_DEMENABLE0_MGE0_DIS 0x00000000U + +// Field: [1] CODC +// +// Enables the coarse DC estimator +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_CODC 0x00000002U +#define LRFDMDM_DEMENABLE0_CODC_M 0x00000002U +#define LRFDMDM_DEMENABLE0_CODC_S 1U +#define LRFDMDM_DEMENABLE0_CODC_EN 0x00000002U +#define LRFDMDM_DEMENABLE0_CODC_DIS 0x00000000U + +// Field: [0] CMIX +// +// Enables the N/1024 complex mixer +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE0_CMIX 0x00000001U +#define LRFDMDM_DEMENABLE0_CMIX_M 0x00000001U +#define LRFDMDM_DEMENABLE0_CMIX_S 0U +#define LRFDMDM_DEMENABLE0_CMIX_EN 0x00000001U +#define LRFDMDM_DEMENABLE0_CMIX_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMENABLE1 +// +//***************************************************************************** +// Field: [13] VITE +// +// Enables the Viterbi module +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_VITE 0x00002000U +#define LRFDMDM_DEMENABLE1_VITE_M 0x00002000U +#define LRFDMDM_DEMENABLE1_VITE_S 13U +#define LRFDMDM_DEMENABLE1_VITE_EN 0x00002000U +#define LRFDMDM_DEMENABLE1_VITE_DIS 0x00000000U + +// Field: [12] MLSE +// +// Enables the MLSE module +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_MLSE 0x00001000U +#define LRFDMDM_DEMENABLE1_MLSE_M 0x00001000U +#define LRFDMDM_DEMENABLE1_MLSE_S 12U +#define LRFDMDM_DEMENABLE1_MLSE_EN 0x00001000U +#define LRFDMDM_DEMENABLE1_MLSE_DIS 0x00000000U + +// Field: [11] SOFD +// +// Enables the soft decision module +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_SOFD 0x00000800U +#define LRFDMDM_DEMENABLE1_SOFD_M 0x00000800U +#define LRFDMDM_DEMENABLE1_SOFD_S 11U +#define LRFDMDM_DEMENABLE1_SOFD_EN 0x00000800U +#define LRFDMDM_DEMENABLE1_SOFD_DIS 0x00000000U + +// Field: [10] SWQU +// +// Enables the sync word qualifier +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_SWQU 0x00000400U +#define LRFDMDM_DEMENABLE1_SWQU_M 0x00000400U +#define LRFDMDM_DEMENABLE1_SWQU_S 10U +#define LRFDMDM_DEMENABLE1_SWQU_EN 0x00000400U +#define LRFDMDM_DEMENABLE1_SWQU_DIS 0x00000000U + +// Field: [9] MAFC +// +// Enables the manual frequency compensation module +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_MAFC 0x00000200U +#define LRFDMDM_DEMENABLE1_MAFC_M 0x00000200U +#define LRFDMDM_DEMENABLE1_MAFC_S 9U +#define LRFDMDM_DEMENABLE1_MAFC_EN 0x00000200U +#define LRFDMDM_DEMENABLE1_MAFC_DIS 0x00000000U + +// Field: [8] MAFI +// +// Enables the matched filter +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_MAFI 0x00000100U +#define LRFDMDM_DEMENABLE1_MAFI_M 0x00000100U +#define LRFDMDM_DEMENABLE1_MAFI_S 8U +#define LRFDMDM_DEMENABLE1_MAFI_EN 0x00000100U +#define LRFDMDM_DEMENABLE1_MAFI_DIS 0x00000000U + +// Field: [7] FIFE +// +// Enables the fine frequency offset estimator +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_FIFE 0x00000080U +#define LRFDMDM_DEMENABLE1_FIFE_M 0x00000080U +#define LRFDMDM_DEMENABLE1_FIFE_S 7U +#define LRFDMDM_DEMENABLE1_FIFE_EN 0x00000080U +#define LRFDMDM_DEMENABLE1_FIFE_DIS 0x00000000U + +// Field: [6] PDIF +// +// Enables the phase differentiation +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_PDIF 0x00000040U +#define LRFDMDM_DEMENABLE1_PDIF_M 0x00000040U +#define LRFDMDM_DEMENABLE1_PDIF_S 6U +#define LRFDMDM_DEMENABLE1_PDIF_EN 0x00000040U +#define LRFDMDM_DEMENABLE1_PDIF_DIS 0x00000000U + +// Field: [5] CA2P +// +// Enables the cart 2 polar conversion +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_CA2P 0x00000020U +#define LRFDMDM_DEMENABLE1_CA2P_M 0x00000020U +#define LRFDMDM_DEMENABLE1_CA2P_S 5U +#define LRFDMDM_DEMENABLE1_CA2P_EN 0x00000020U +#define LRFDMDM_DEMENABLE1_CA2P_DIS 0x00000000U + +// Field: [4] C1BE +// +// Enables the correlation 1-bit engine +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_C1BE 0x00000010U +#define LRFDMDM_DEMENABLE1_C1BE_M 0x00000010U +#define LRFDMDM_DEMENABLE1_C1BE_S 4U +#define LRFDMDM_DEMENABLE1_C1BE_EN 0x00000010U +#define LRFDMDM_DEMENABLE1_C1BE_DIS 0x00000000U + +// Field: [3] LQIE +// +// Enables the LQI engine +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_LQIE 0x00000008U +#define LRFDMDM_DEMENABLE1_LQIE_M 0x00000008U +#define LRFDMDM_DEMENABLE1_LQIE_S 3U +#define LRFDMDM_DEMENABLE1_LQIE_EN 0x00000008U +#define LRFDMDM_DEMENABLE1_LQIE_DIS 0x00000000U + +// Field: [2] F4BA +// +// Enables the clock-domain crossing fifo +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_F4BA 0x00000004U +#define LRFDMDM_DEMENABLE1_F4BA_M 0x00000004U +#define LRFDMDM_DEMENABLE1_F4BA_S 2U +#define LRFDMDM_DEMENABLE1_F4BA_EN 0x00000004U +#define LRFDMDM_DEMENABLE1_F4BA_DIS 0x00000000U + +// Field: [1] STIM +// +// Enables the symbol timing tracker +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_STIM 0x00000002U +#define LRFDMDM_DEMENABLE1_STIM_M 0x00000002U +#define LRFDMDM_DEMENABLE1_STIM_S 1U +#define LRFDMDM_DEMENABLE1_STIM_EN 0x00000002U +#define LRFDMDM_DEMENABLE1_STIM_DIS 0x00000000U + +// Field: [0] DSBU +// +// Enables the dynamic sample buffer +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM_DEMENABLE1_DSBU 0x00000001U +#define LRFDMDM_DEMENABLE1_DSBU_M 0x00000001U +#define LRFDMDM_DEMENABLE1_DSBU_S 0U +#define LRFDMDM_DEMENABLE1_DSBU_EN 0x00000001U +#define LRFDMDM_DEMENABLE1_DSBU_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMINIT0 +// +//***************************************************************************** +// Field: [8] FRAC +// +// Synch reset fractional resampler +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_FRAC 0x00000100U +#define LRFDMDM_DEMINIT0_FRAC_M 0x00000100U +#define LRFDMDM_DEMINIT0_FRAC_S 8U +#define LRFDMDM_DEMINIT0_FRAC_RESET 0x00000100U +#define LRFDMDM_DEMINIT0_FRAC_NO_EFFECT 0x00000000U + +// Field: [7] FIDC +// +// Synch reset fine DC estimator +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_FIDC 0x00000080U +#define LRFDMDM_DEMINIT0_FIDC_M 0x00000080U +#define LRFDMDM_DEMINIT0_FIDC_S 7U +#define LRFDMDM_DEMINIT0_FIDC_RESET 0x00000080U +#define LRFDMDM_DEMINIT0_FIDC_NO_EFFECT 0x00000000U + +// Field: [6] CHFI +// +// Synch reset channel filter +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_CHFI 0x00000040U +#define LRFDMDM_DEMINIT0_CHFI_M 0x00000040U +#define LRFDMDM_DEMINIT0_CHFI_S 6U +#define LRFDMDM_DEMINIT0_CHFI_RESET 0x00000040U +#define LRFDMDM_DEMINIT0_CHFI_NO_EFFECT 0x00000000U + +// Field: [5] BDEC +// +// Synch reset cascaded dec-by-2 stages (bde1 and bde2) +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_BDEC 0x00000020U +#define LRFDMDM_DEMINIT0_BDEC_M 0x00000020U +#define LRFDMDM_DEMINIT0_BDEC_S 5U +#define LRFDMDM_DEMINIT0_BDEC_RESET 0x00000020U +#define LRFDMDM_DEMINIT0_BDEC_NO_EFFECT 0x00000000U + +// Field: [4] IQMC +// +// Synch reset IQ mismatch compensation +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_IQMC 0x00000010U +#define LRFDMDM_DEMINIT0_IQMC_M 0x00000010U +#define LRFDMDM_DEMINIT0_IQMC_S 4U +#define LRFDMDM_DEMINIT0_IQMC_RESET 0x00000010U +#define LRFDMDM_DEMINIT0_IQMC_NO_EFFECT 0x00000000U + +// Field: [3] MGE1 +// +// Synch reset magnitude estimator engine #1 +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_MGE1 0x00000008U +#define LRFDMDM_DEMINIT0_MGE1_M 0x00000008U +#define LRFDMDM_DEMINIT0_MGE1_S 3U +#define LRFDMDM_DEMINIT0_MGE1_RESET 0x00000008U +#define LRFDMDM_DEMINIT0_MGE1_NO_EFFECT 0x00000000U + +// Field: [2] MGE0 +// +// Synch reset magnitude estimator engine #0 +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_MGE0 0x00000004U +#define LRFDMDM_DEMINIT0_MGE0_M 0x00000004U +#define LRFDMDM_DEMINIT0_MGE0_S 2U +#define LRFDMDM_DEMINIT0_MGE0_RESET 0x00000004U +#define LRFDMDM_DEMINIT0_MGE0_NO_EFFECT 0x00000000U + +// Field: [1] CODC +// +// Synch reset coarse DC estimator +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_CODC 0x00000002U +#define LRFDMDM_DEMINIT0_CODC_M 0x00000002U +#define LRFDMDM_DEMINIT0_CODC_S 1U +#define LRFDMDM_DEMINIT0_CODC_RESET 0x00000002U +#define LRFDMDM_DEMINIT0_CODC_NO_EFFECT 0x00000000U + +// Field: [0] CMIX +// +// Synch reset N/1024 complex mixer +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT0_CMIX 0x00000001U +#define LRFDMDM_DEMINIT0_CMIX_M 0x00000001U +#define LRFDMDM_DEMINIT0_CMIX_S 0U +#define LRFDMDM_DEMINIT0_CMIX_RESET 0x00000001U +#define LRFDMDM_DEMINIT0_CMIX_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMINIT1 +// +//***************************************************************************** +// Field: [13] VITE +// +// Synch reset Viterbi Module +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_VITE 0x00002000U +#define LRFDMDM_DEMINIT1_VITE_M 0x00002000U +#define LRFDMDM_DEMINIT1_VITE_S 13U +#define LRFDMDM_DEMINIT1_VITE_RESET 0x00002000U +#define LRFDMDM_DEMINIT1_VITE_NO_EFFECT 0x00000000U + +// Field: [12] MLSE +// +// Synch reset MLSE module +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_MLSE 0x00001000U +#define LRFDMDM_DEMINIT1_MLSE_M 0x00001000U +#define LRFDMDM_DEMINIT1_MLSE_S 12U +#define LRFDMDM_DEMINIT1_MLSE_RESET 0x00001000U +#define LRFDMDM_DEMINIT1_MLSE_NO_EFFECT 0x00000000U + +// Field: [11] SOFD +// +// Synch reset soft decision module +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_SOFD 0x00000800U +#define LRFDMDM_DEMINIT1_SOFD_M 0x00000800U +#define LRFDMDM_DEMINIT1_SOFD_S 11U +#define LRFDMDM_DEMINIT1_SOFD_RESET 0x00000800U +#define LRFDMDM_DEMINIT1_SOFD_NO_EFFECT 0x00000000U + +// Field: [10] SWQU +// +// Synch reset sync word qualifyer +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_SWQU 0x00000400U +#define LRFDMDM_DEMINIT1_SWQU_M 0x00000400U +#define LRFDMDM_DEMINIT1_SWQU_S 10U +#define LRFDMDM_DEMINIT1_SWQU_RESET 0x00000400U +#define LRFDMDM_DEMINIT1_SWQU_NO_EFFECT 0x00000000U + +// Field: [9] MAFC +// +// Synch reset manual frequency compensation module +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_MAFC 0x00000200U +#define LRFDMDM_DEMINIT1_MAFC_M 0x00000200U +#define LRFDMDM_DEMINIT1_MAFC_S 9U +#define LRFDMDM_DEMINIT1_MAFC_RESET 0x00000200U +#define LRFDMDM_DEMINIT1_MAFC_NO_EFFECT 0x00000000U + +// Field: [8] MAFI +// +// Synch reset matched filter +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_MAFI 0x00000100U +#define LRFDMDM_DEMINIT1_MAFI_M 0x00000100U +#define LRFDMDM_DEMINIT1_MAFI_S 8U +#define LRFDMDM_DEMINIT1_MAFI_RESET 0x00000100U +#define LRFDMDM_DEMINIT1_MAFI_NO_EFFECT 0x00000000U + +// Field: [7] FIFE +// +// Synch reset fine frequency offset estimator +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_FIFE 0x00000080U +#define LRFDMDM_DEMINIT1_FIFE_M 0x00000080U +#define LRFDMDM_DEMINIT1_FIFE_S 7U +#define LRFDMDM_DEMINIT1_FIFE_RESET 0x00000080U +#define LRFDMDM_DEMINIT1_FIFE_NO_EFFECT 0x00000000U + +// Field: [6] PDIF +// +// Synch reset phase differentiation +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_PDIF 0x00000040U +#define LRFDMDM_DEMINIT1_PDIF_M 0x00000040U +#define LRFDMDM_DEMINIT1_PDIF_S 6U +#define LRFDMDM_DEMINIT1_PDIF_RESET 0x00000040U +#define LRFDMDM_DEMINIT1_PDIF_NO_EFFECT 0x00000000U + +// Field: [5] CA2P +// +// Synch reset cart 2 polar conversion +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_CA2P 0x00000020U +#define LRFDMDM_DEMINIT1_CA2P_M 0x00000020U +#define LRFDMDM_DEMINIT1_CA2P_S 5U +#define LRFDMDM_DEMINIT1_CA2P_RESET 0x00000020U +#define LRFDMDM_DEMINIT1_CA2P_NO_EFFECT 0x00000000U + +// Field: [4] C1BE +// +// Synch reset correlation 1-bit engine +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_C1BE 0x00000010U +#define LRFDMDM_DEMINIT1_C1BE_M 0x00000010U +#define LRFDMDM_DEMINIT1_C1BE_S 4U +#define LRFDMDM_DEMINIT1_C1BE_RESET 0x00000010U +#define LRFDMDM_DEMINIT1_C1BE_NO_EFFECT 0x00000000U + +// Field: [3] LQIE +// +// Synch reset LQI engine +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_LQIE 0x00000008U +#define LRFDMDM_DEMINIT1_LQIE_M 0x00000008U +#define LRFDMDM_DEMINIT1_LQIE_S 3U +#define LRFDMDM_DEMINIT1_LQIE_RESET 0x00000008U +#define LRFDMDM_DEMINIT1_LQIE_NO_EFFECT 0x00000000U + +// Field: [2] F4BA +// +// Synch reset clock-domain crossing fifo +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_F4BA 0x00000004U +#define LRFDMDM_DEMINIT1_F4BA_M 0x00000004U +#define LRFDMDM_DEMINIT1_F4BA_S 2U +#define LRFDMDM_DEMINIT1_F4BA_RESET 0x00000004U +#define LRFDMDM_DEMINIT1_F4BA_NO_EFFECT 0x00000000U + +// Field: [1] STIM +// +// Synch reset symbol timing tracker +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_STIM 0x00000002U +#define LRFDMDM_DEMINIT1_STIM_M 0x00000002U +#define LRFDMDM_DEMINIT1_STIM_S 1U +#define LRFDMDM_DEMINIT1_STIM_RESET 0x00000002U +#define LRFDMDM_DEMINIT1_STIM_NO_EFFECT 0x00000000U + +// Field: [0] DSBU +// +// Synch reset dynamic sample buffer +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM_DEMINIT1_DSBU 0x00000001U +#define LRFDMDM_DEMINIT1_DSBU_M 0x00000001U +#define LRFDMDM_DEMINIT1_DSBU_S 0U +#define LRFDMDM_DEMINIT1_DSBU_RESET 0x00000001U +#define LRFDMDM_DEMINIT1_DSBU_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_STRB0 +// +//***************************************************************************** +// Field: [11] TIMBADVANCE +// +// Advance the timebase one 4baud sample, so the current symbol will have three +// 4baud samples. +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM_STRB0_TIMBADVANCE 0x00000800U +#define LRFDMDM_STRB0_TIMBADVANCE_M 0x00000800U +#define LRFDMDM_STRB0_TIMBADVANCE_S 11U +#define LRFDMDM_STRB0_TIMBADVANCE_ON 0x00000800U +#define LRFDMDM_STRB0_TIMBADVANCE_NO_EFFECT 0x00000000U + +// Field: [10] TIMBSTALL +// +// Stall the timebase one 4baud sample, so the current symbol will have five +// 4baud samples. +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM_STRB0_TIMBSTALL 0x00000400U +#define LRFDMDM_STRB0_TIMBSTALL_M 0x00000400U +#define LRFDMDM_STRB0_TIMBSTALL_S 10U +#define LRFDMDM_STRB0_TIMBSTALL_ON 0x00000400U +#define LRFDMDM_STRB0_TIMBSTALL_NO_EFFECT 0x00000000U + +// Field: [9] EVT5 +// +// Firmware defined +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT5 0x00000200U +#define LRFDMDM_STRB0_EVT5_M 0x00000200U +#define LRFDMDM_STRB0_EVT5_S 9U +#define LRFDMDM_STRB0_EVT5_ONE 0x00000200U +#define LRFDMDM_STRB0_EVT5_ZERO 0x00000000U + +// Field: [8] EVT4 +// +// Firmware defined +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT4 0x00000100U +#define LRFDMDM_STRB0_EVT4_M 0x00000100U +#define LRFDMDM_STRB0_EVT4_S 8U +#define LRFDMDM_STRB0_EVT4_ONE 0x00000100U +#define LRFDMDM_STRB0_EVT4_ZERO 0x00000000U + +// Field: [7] MLSETERM +// +// Terminate MLSE unit +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_STRB0_MLSETERM 0x00000080U +#define LRFDMDM_STRB0_MLSETERM_M 0x00000080U +#define LRFDMDM_STRB0_MLSETERM_S 7U +#define LRFDMDM_STRB0_MLSETERM_ON 0x00000080U +#define LRFDMDM_STRB0_MLSETERM_OFF 0x00000000U + +// Field: [6] EVT3 +// +// Firmware defined +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT3 0x00000040U +#define LRFDMDM_STRB0_EVT3_M 0x00000040U +#define LRFDMDM_STRB0_EVT3_S 6U +#define LRFDMDM_STRB0_EVT3_ONE 0x00000040U +#define LRFDMDM_STRB0_EVT3_ZERO 0x00000000U + +// Field: [5] EVT2 +// +// Firmware defined SYSTIMER event 2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT2 0x00000020U +#define LRFDMDM_STRB0_EVT2_M 0x00000020U +#define LRFDMDM_STRB0_EVT2_S 5U +#define LRFDMDM_STRB0_EVT2_ONE 0x00000020U +#define LRFDMDM_STRB0_EVT2_ZERO 0x00000000U + +// Field: [4] EVT1 +// +// Firmware defined SYSTIMER event 1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT1 0x00000010U +#define LRFDMDM_STRB0_EVT1_M 0x00000010U +#define LRFDMDM_STRB0_EVT1_S 4U +#define LRFDMDM_STRB0_EVT1_ONE 0x00000010U +#define LRFDMDM_STRB0_EVT1_ZERO 0x00000000U + +// Field: [3] EVT0 +// +// Firmware defined SYSTIMER event 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB0_EVT0 0x00000008U +#define LRFDMDM_STRB0_EVT0_M 0x00000008U +#define LRFDMDM_STRB0_EVT0_S 3U +#define LRFDMDM_STRB0_EVT0_ONE 0x00000008U +#define LRFDMDM_STRB0_EVT0_ZERO 0x00000000U + +// Field: [2] TIMBALIGN +// +// Align the 1baud to the next 4baud event +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM_STRB0_TIMBALIGN 0x00000004U +#define LRFDMDM_STRB0_TIMBALIGN_M 0x00000004U +#define LRFDMDM_STRB0_TIMBALIGN_S 2U +#define LRFDMDM_STRB0_TIMBALIGN_ON 0x00000004U +#define LRFDMDM_STRB0_TIMBALIGN_NO_EFFECT 0x00000000U + +// Field: [1] DSBURST +// +// Restart DSBU +// ENUMs: +// RESTART Restart module +// NO_EFFECT No effect +#define LRFDMDM_STRB0_DSBURST 0x00000002U +#define LRFDMDM_STRB0_DSBURST_M 0x00000002U +#define LRFDMDM_STRB0_DSBURST_S 1U +#define LRFDMDM_STRB0_DSBURST_RESTART 0x00000002U +#define LRFDMDM_STRB0_DSBURST_NO_EFFECT 0x00000000U + +// Field: [0] CMDDONE +// +// Signal command done to CPE +// ENUMs: +// YES The bit is 1 +// NO The bit is 0 +#define LRFDMDM_STRB0_CMDDONE 0x00000001U +#define LRFDMDM_STRB0_CMDDONE_M 0x00000001U +#define LRFDMDM_STRB0_CMDDONE_S 0U +#define LRFDMDM_STRB0_CMDDONE_YES 0x00000001U +#define LRFDMDM_STRB0_CMDDONE_NO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_STRB1 +// +//***************************************************************************** +// Field: [13] S2RTRG +// +// Arm/Trigger the S2R module +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_S2RTRG 0x00002000U +#define LRFDMDM_STRB1_S2RTRG_M 0x00002000U +#define LRFDMDM_STRB1_S2RTRG_S 13U +#define LRFDMDM_STRB1_S2RTRG_ONE 0x00002000U +#define LRFDMDM_STRB1_S2RTRG_ZERO 0x00000000U + +// Field: [12] DMATRG +// +// FW triggered DMA transfer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_DMATRG 0x00001000U +#define LRFDMDM_STRB1_DMATRG_M 0x00001000U +#define LRFDMDM_STRB1_DMATRG_S 12U +#define LRFDMDM_STRB1_DMATRG_ONE 0x00001000U +#define LRFDMDM_STRB1_DMATRG_ZERO 0x00000000U + +// Field: [11] SYSTCAPT2 +// +// Systimer capture event 2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_SYSTCAPT2 0x00000800U +#define LRFDMDM_STRB1_SYSTCAPT2_M 0x00000800U +#define LRFDMDM_STRB1_SYSTCAPT2_S 11U +#define LRFDMDM_STRB1_SYSTCAPT2_ONE 0x00000800U +#define LRFDMDM_STRB1_SYSTCAPT2_ZERO 0x00000000U + +// Field: [10] SYSTCAPT1 +// +// Systimer capture event 1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_SYSTCAPT1 0x00000400U +#define LRFDMDM_STRB1_SYSTCAPT1_M 0x00000400U +#define LRFDMDM_STRB1_SYSTCAPT1_S 10U +#define LRFDMDM_STRB1_SYSTCAPT1_ONE 0x00000400U +#define LRFDMDM_STRB1_SYSTCAPT1_ZERO 0x00000000U + +// Field: [9] SYSTCAPT0 +// +// Systimer capture event 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_SYSTCAPT0 0x00000200U +#define LRFDMDM_STRB1_SYSTCAPT0_M 0x00000200U +#define LRFDMDM_STRB1_SYSTCAPT0_S 9U +#define LRFDMDM_STRB1_SYSTCAPT0_ONE 0x00000200U +#define LRFDMDM_STRB1_SYSTCAPT0_ZERO 0x00000000U + +// Field: [8] C1BEPEAKAB +// +// Restart C1BE peak A and B search +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BEPEAKAB 0x00000100U +#define LRFDMDM_STRB1_C1BEPEAKAB_M 0x00000100U +#define LRFDMDM_STRB1_C1BEPEAKAB_S 8U +#define LRFDMDM_STRB1_C1BEPEAKAB_ONE 0x00000100U +#define LRFDMDM_STRB1_C1BEPEAKAB_ZERO 0x00000000U + +// Field: [7] C1BEPEAKC +// +// Restart C1BE peak C search (corr C is corr A+B combined = 64 symbols = 256 +// samples) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BEPEAKC 0x00000080U +#define LRFDMDM_STRB1_C1BEPEAKC_M 0x00000080U +#define LRFDMDM_STRB1_C1BEPEAKC_S 7U +#define LRFDMDM_STRB1_C1BEPEAKC_ONE 0x00000080U +#define LRFDMDM_STRB1_C1BEPEAKC_ZERO 0x00000000U + +// Field: [6] C1BEPEAKB +// +// Restart C1BE peak B search (32 symbols = 128 samples) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BEPEAKB 0x00000040U +#define LRFDMDM_STRB1_C1BEPEAKB_M 0x00000040U +#define LRFDMDM_STRB1_C1BEPEAKB_S 6U +#define LRFDMDM_STRB1_C1BEPEAKB_ONE 0x00000040U +#define LRFDMDM_STRB1_C1BEPEAKB_ZERO 0x00000000U + +// Field: [5] C1BEPEAKA +// +// Restart C1BE peak A search (32 symbols = 128 samples) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BEPEAKA 0x00000020U +#define LRFDMDM_STRB1_C1BEPEAKA_M 0x00000020U +#define LRFDMDM_STRB1_C1BEPEAKA_S 5U +#define LRFDMDM_STRB1_C1BEPEAKA_ONE 0x00000020U +#define LRFDMDM_STRB1_C1BEPEAKA_ZERO 0x00000000U + +// Field: [4] C1BEADVANCE +// +// Speed up correlator autocopy with one sample +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BEADVANCE 0x00000010U +#define LRFDMDM_STRB1_C1BEADVANCE_M 0x00000010U +#define LRFDMDM_STRB1_C1BEADVANCE_S 4U +#define LRFDMDM_STRB1_C1BEADVANCE_ONE 0x00000010U +#define LRFDMDM_STRB1_C1BEADVANCE_ZERO 0x00000000U + +// Field: [3] C1BESTALL +// +// Slow down correlator autocopy with one sample +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BESTALL 0x00000008U +#define LRFDMDM_STRB1_C1BESTALL_M 0x00000008U +#define LRFDMDM_STRB1_C1BESTALL_S 3U +#define LRFDMDM_STRB1_C1BESTALL_ONE 0x00000008U +#define LRFDMDM_STRB1_C1BESTALL_ZERO 0x00000000U + +// Field: [2:1] C1BEROT +// +// Correlator rotate command to shift reg B +// ENUMs: +// ROT16R Rotate 16 samples to the right +// ROT1L Rotate 1 sample to the left +// ROT1R Rotate 1 sample to the right +// ROT0 No additional rotation (normal shift-right mode) +#define LRFDMDM_STRB1_C1BEROT_W 2U +#define LRFDMDM_STRB1_C1BEROT_M 0x00000006U +#define LRFDMDM_STRB1_C1BEROT_S 1U +#define LRFDMDM_STRB1_C1BEROT_ROT16R 0x00000006U +#define LRFDMDM_STRB1_C1BEROT_ROT1L 0x00000004U +#define LRFDMDM_STRB1_C1BEROT_ROT1R 0x00000002U +#define LRFDMDM_STRB1_C1BEROT_ROT0 0x00000000U + +// Field: [0] C1BECOPY +// +// Copy contents of shift reg A into shift reg B +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_STRB1_C1BECOPY 0x00000001U +#define LRFDMDM_STRB1_C1BECOPY_M 0x00000001U +#define LRFDMDM_STRB1_C1BECOPY_S 0U +#define LRFDMDM_STRB1_C1BECOPY_ONE 0x00000001U +#define LRFDMDM_STRB1_C1BECOPY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVT0 +// +//***************************************************************************** +// Field: [15] PBEDAT +// +// New data from PBE received in PBEDATIN0 register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_PBEDAT 0x00008000U +#define LRFDMDM_EVT0_PBEDAT_M 0x00008000U +#define LRFDMDM_EVT0_PBEDAT_S 15U +#define LRFDMDM_EVT0_PBEDAT_ONE 0x00008000U +#define LRFDMDM_EVT0_PBEDAT_ZERO 0x00000000U + +// Field: [14] PBECMD +// +// New command from PBE received in PBECMDIN register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_PBECMD 0x00004000U +#define LRFDMDM_EVT0_PBECMD_M 0x00004000U +#define LRFDMDM_EVT0_PBECMD_S 14U +#define LRFDMDM_EVT0_PBECMD_ONE 0x00004000U +#define LRFDMDM_EVT0_PBECMD_ZERO 0x00000000U + +// Field: [13] RFEDAT +// +// New data from RFE received in RFEDATIN0 register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_RFEDAT 0x00002000U +#define LRFDMDM_EVT0_RFEDAT_M 0x00002000U +#define LRFDMDM_EVT0_RFEDAT_S 13U +#define LRFDMDM_EVT0_RFEDAT_ONE 0x00002000U +#define LRFDMDM_EVT0_RFEDAT_ZERO 0x00000000U + +// Field: [12] BDEC +// +// BDEC output enable event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_BDEC 0x00001000U +#define LRFDMDM_EVT0_BDEC_M 0x00001000U +#define LRFDMDM_EVT0_BDEC_S 12U +#define LRFDMDM_EVT0_BDEC_ONE 0x00001000U +#define LRFDMDM_EVT0_BDEC_ZERO 0x00000000U + +// Field: [11] FRAC +// +// FRAC output enable event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_FRAC 0x00000800U +#define LRFDMDM_EVT0_FRAC_M 0x00000800U +#define LRFDMDM_EVT0_FRAC_S 11U +#define LRFDMDM_EVT0_FRAC_ONE 0x00000800U +#define LRFDMDM_EVT0_FRAC_ZERO 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// Event 2 from SYSTIMER +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_SYSTIMEVT2 0x00000400U +#define LRFDMDM_EVT0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM_EVT0_SYSTIMEVT2_S 10U +#define LRFDMDM_EVT0_SYSTIMEVT2_ONE 0x00000400U +#define LRFDMDM_EVT0_SYSTIMEVT2_ZERO 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// Event 1 from SYSTIMER +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_SYSTIMEVT1 0x00000200U +#define LRFDMDM_EVT0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM_EVT0_SYSTIMEVT1_S 9U +#define LRFDMDM_EVT0_SYSTIMEVT1_ONE 0x00000200U +#define LRFDMDM_EVT0_SYSTIMEVT1_ZERO 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// Event 0 from SYSTIMER +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_SYSTIMEVT0 0x00000100U +#define LRFDMDM_EVT0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM_EVT0_SYSTIMEVT0_S 8U +#define LRFDMDM_EVT0_SYSTIMEVT0_ONE 0x00000100U +#define LRFDMDM_EVT0_SYSTIMEVT0_ZERO 0x00000000U + +// Field: [7] FIFOWR +// +// A write to the modem FIFO (via FIFOWR register), probably by CPE. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_FIFOWR 0x00000080U +#define LRFDMDM_EVT0_FIFOWR_M 0x00000080U +#define LRFDMDM_EVT0_FIFOWR_S 7U +#define LRFDMDM_EVT0_FIFOWR_ONE 0x00000080U +#define LRFDMDM_EVT0_FIFOWR_ZERO 0x00000000U + +// Field: [6] COUNTER +// +// Counter value reached in local timer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_COUNTER 0x00000040U +#define LRFDMDM_EVT0_COUNTER_M 0x00000040U +#define LRFDMDM_EVT0_COUNTER_S 6U +#define LRFDMDM_EVT0_COUNTER_ONE 0x00000040U +#define LRFDMDM_EVT0_COUNTER_ZERO 0x00000000U + +// Field: [5] RFECMD +// +// New command from RFE received in RFECMDIN register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_RFECMD 0x00000020U +#define LRFDMDM_EVT0_RFECMD_M 0x00000020U +#define LRFDMDM_EVT0_RFECMD_S 5U +#define LRFDMDM_EVT0_RFECMD_ONE 0x00000020U +#define LRFDMDM_EVT0_RFECMD_ZERO 0x00000000U + +// Field: [4] FIFOOVFL +// +// Modem FIFO overflow error event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_FIFOOVFL 0x00000010U +#define LRFDMDM_EVT0_FIFOOVFL_M 0x00000010U +#define LRFDMDM_EVT0_FIFOOVFL_S 4U +#define LRFDMDM_EVT0_FIFOOVFL_ONE 0x00000010U +#define LRFDMDM_EVT0_FIFOOVFL_ZERO 0x00000000U + +// Field: [3] FIFOUNFL +// +// Modem FIFO underflow error event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_FIFOUNFL 0x00000008U +#define LRFDMDM_EVT0_FIFOUNFL_M 0x00000008U +#define LRFDMDM_EVT0_FIFOUNFL_S 3U +#define LRFDMDM_EVT0_FIFOUNFL_ONE 0x00000008U +#define LRFDMDM_EVT0_FIFOUNFL_ZERO 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// Clock enable event at 4 times baud rate +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_CLKEN4BAUD 0x00000004U +#define LRFDMDM_EVT0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM_EVT0_CLKEN4BAUD_S 2U +#define LRFDMDM_EVT0_CLKEN4BAUD_ONE 0x00000004U +#define LRFDMDM_EVT0_CLKEN4BAUD_ZERO 0x00000000U + +// Field: [1] TIMER +// +// Timer period expired in local timer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_TIMER 0x00000002U +#define LRFDMDM_EVT0_TIMER_M 0x00000002U +#define LRFDMDM_EVT0_TIMER_S 1U +#define LRFDMDM_EVT0_TIMER_ONE 0x00000002U +#define LRFDMDM_EVT0_TIMER_ZERO 0x00000000U + +// Field: [0] MDMAPI +// +// New command from PBE has been written in API register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT0_MDMAPI 0x00000001U +#define LRFDMDM_EVT0_MDMAPI_M 0x00000001U +#define LRFDMDM_EVT0_MDMAPI_S 0U +#define LRFDMDM_EVT0_MDMAPI_ONE 0x00000001U +#define LRFDMDM_EVT0_MDMAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVT1 +// +//***************************************************************************** +// Field: [8] REFCLK +// +// PLL REFCLK tick +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_REFCLK 0x00000100U +#define LRFDMDM_EVT1_REFCLK_M 0x00000100U +#define LRFDMDM_EVT1_REFCLK_S 8U +#define LRFDMDM_EVT1_REFCLK_ONE 0x00000100U +#define LRFDMDM_EVT1_REFCLK_ZERO 0x00000000U + +// Field: [7] S2RSTOP +// +// S2R module has written to the STOP_ADDRESS register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_S2RSTOP 0x00000080U +#define LRFDMDM_EVT1_S2RSTOP_M 0x00000080U +#define LRFDMDM_EVT1_S2RSTOP_S 7U +#define LRFDMDM_EVT1_S2RSTOP_ONE 0x00000080U +#define LRFDMDM_EVT1_S2RSTOP_ZERO 0x00000000U + +// Field: [6] SWQUFALSESYNC +// +// Sync word qualifier rejected sync due to bit errors (happens if a correlator +// event was incorrect due to noise). +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_SWQUFALSESYNC 0x00000040U +#define LRFDMDM_EVT1_SWQUFALSESYNC_M 0x00000040U +#define LRFDMDM_EVT1_SWQUFALSESYNC_S 6U +#define LRFDMDM_EVT1_SWQUFALSESYNC_ONE 0x00000040U +#define LRFDMDM_EVT1_SWQUFALSESYNC_ZERO 0x00000000U + +// Field: [5] SWQUSYNCED +// +// Sync word qualifier detected sync word +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_SWQUSYNCED 0x00000020U +#define LRFDMDM_EVT1_SWQUSYNCED_M 0x00000020U +#define LRFDMDM_EVT1_SWQUSYNCED_S 5U +#define LRFDMDM_EVT1_SWQUSYNCED_ONE 0x00000020U +#define LRFDMDM_EVT1_SWQUSYNCED_ZERO 0x00000000U + +// Field: [4] CLKENBAUDF +// +// Clock enable event at flushed baud rate +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_CLKENBAUDF 0x00000010U +#define LRFDMDM_EVT1_CLKENBAUDF_M 0x00000010U +#define LRFDMDM_EVT1_CLKENBAUDF_S 4U +#define LRFDMDM_EVT1_CLKENBAUDF_ONE 0x00000010U +#define LRFDMDM_EVT1_CLKENBAUDF_ZERO 0x00000000U + +// Field: [3] FIFORVALID +// +// Modem FIFO has valid data so a new word can be read from it, via FIFORD. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_FIFORVALID 0x00000008U +#define LRFDMDM_EVT1_FIFORVALID_M 0x00000008U +#define LRFDMDM_EVT1_FIFORVALID_S 3U +#define LRFDMDM_EVT1_FIFORVALID_ONE 0x00000008U +#define LRFDMDM_EVT1_FIFORVALID_ZERO 0x00000000U + +// Field: [2] FIFOWREADY +// +// Modem FIFO is ready for more data so a new word can be written to it, via +// FIFOWR register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_FIFOWREADY 0x00000004U +#define LRFDMDM_EVT1_FIFOWREADY_M 0x00000004U +#define LRFDMDM_EVT1_FIFOWREADY_S 2U +#define LRFDMDM_EVT1_FIFOWREADY_ONE 0x00000004U +#define LRFDMDM_EVT1_FIFOWREADY_ZERO 0x00000000U + +// Field: [1] CLKENBAUD +// +// Clock enable event at baud rate +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_CLKENBAUD 0x00000002U +#define LRFDMDM_EVT1_CLKENBAUD_M 0x00000002U +#define LRFDMDM_EVT1_CLKENBAUD_S 1U +#define LRFDMDM_EVT1_CLKENBAUD_ONE 0x00000002U +#define LRFDMDM_EVT1_CLKENBAUD_ZERO 0x00000000U + +// Field: [0] PREAMBLEDONE +// +// Preamble done interrupt from modulator +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT1_PREAMBLEDONE 0x00000001U +#define LRFDMDM_EVT1_PREAMBLEDONE_M 0x00000001U +#define LRFDMDM_EVT1_PREAMBLEDONE_S 0U +#define LRFDMDM_EVT1_PREAMBLEDONE_ONE 0x00000001U +#define LRFDMDM_EVT1_PREAMBLEDONE_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVT2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// External input event line GPI1 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_GPI1 0x00008000U +#define LRFDMDM_EVT2_GPI1_M 0x00008000U +#define LRFDMDM_EVT2_GPI1_S 15U +#define LRFDMDM_EVT2_GPI1_ONE 0x00008000U +#define LRFDMDM_EVT2_GPI1_ZERO 0x00000000U + +// Field: [14] GPI0 +// +// External input event line GPI0 from IOC. (Also, when loopback mode is +// enabled in DEMDEBUG.LOOPBACKMODE, this input line represents the symbols fed +// to the demodulator's decode stage). +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_GPI0 0x00004000U +#define LRFDMDM_EVT2_GPI0_M 0x00004000U +#define LRFDMDM_EVT2_GPI0_S 14U +#define LRFDMDM_EVT2_GPI0_ONE 0x00004000U +#define LRFDMDM_EVT2_GPI0_ZERO 0x00000000U + +// Field: [12] C1BEBLOADED +// +// C1BE correlator B loaded (by auto-copy function) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEBLOADED 0x00001000U +#define LRFDMDM_EVT2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM_EVT2_C1BEBLOADED_S 12U +#define LRFDMDM_EVT2_C1BEBLOADED_ONE 0x00001000U +#define LRFDMDM_EVT2_C1BEBLOADED_ZERO 0x00000000U + +// Field: [11] C1BECMBANY +// +// C1BE correlator AB combined, any peak detect: (abs(corr A) > thr A) and +// (abs(corr B) > thr B). Event occurs one sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECMBANY 0x00000800U +#define LRFDMDM_EVT2_C1BECMBANY_M 0x00000800U +#define LRFDMDM_EVT2_C1BECMBANY_S 11U +#define LRFDMDM_EVT2_C1BECMBANY_ONE 0x00000800U +#define LRFDMDM_EVT2_C1BECMBANY_ZERO 0x00000000U + +// Field: [10] C1BECMBNEG +// +// C1BE correlator AB combined, negative peak detect: (corr A < -thr A) and +// (corr B < -thr B). Event occurs one sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECMBNEG 0x00000400U +#define LRFDMDM_EVT2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM_EVT2_C1BECMBNEG_S 10U +#define LRFDMDM_EVT2_C1BECMBNEG_ONE 0x00000400U +#define LRFDMDM_EVT2_C1BECMBNEG_ZERO 0x00000000U + +// Field: [9] C1BECMBPOS +// +// C1BE correlator AB combined, positive peak detect: (corr A > thr A) and +// (corr B > thr B). Event occurs one sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECMBPOS 0x00000200U +#define LRFDMDM_EVT2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM_EVT2_C1BECMBPOS_S 9U +#define LRFDMDM_EVT2_C1BECMBPOS_ONE 0x00000200U +#define LRFDMDM_EVT2_C1BECMBPOS_ZERO 0x00000000U + +// Field: [8] C1BECANY +// +// C1BE correlator C, any peak detect: abs(corr C) > thr C. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECANY 0x00000100U +#define LRFDMDM_EVT2_C1BECANY_M 0x00000100U +#define LRFDMDM_EVT2_C1BECANY_S 8U +#define LRFDMDM_EVT2_C1BECANY_ONE 0x00000100U +#define LRFDMDM_EVT2_C1BECANY_ZERO 0x00000000U + +// Field: [7] C1BECNEG +// +// C1BE correlator C, negative peak detect: corr C < -thr C. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECNEG 0x00000080U +#define LRFDMDM_EVT2_C1BECNEG_M 0x00000080U +#define LRFDMDM_EVT2_C1BECNEG_S 7U +#define LRFDMDM_EVT2_C1BECNEG_ONE 0x00000080U +#define LRFDMDM_EVT2_C1BECNEG_ZERO 0x00000000U + +// Field: [6] C1BECPOS +// +// C1BE correlator C, positive peak detect: corr C > thr C. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BECPOS 0x00000040U +#define LRFDMDM_EVT2_C1BECPOS_M 0x00000040U +#define LRFDMDM_EVT2_C1BECPOS_S 6U +#define LRFDMDM_EVT2_C1BECPOS_ONE 0x00000040U +#define LRFDMDM_EVT2_C1BECPOS_ZERO 0x00000000U + +// Field: [5] C1BEBANY +// +// C1BE correlator B, any peak detect: abs(corr B) > thr B. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEBANY 0x00000020U +#define LRFDMDM_EVT2_C1BEBANY_M 0x00000020U +#define LRFDMDM_EVT2_C1BEBANY_S 5U +#define LRFDMDM_EVT2_C1BEBANY_ONE 0x00000020U +#define LRFDMDM_EVT2_C1BEBANY_ZERO 0x00000000U + +// Field: [4] C1BEBNEG +// +// C1BE correlator B, negative peak detect: corr B < -threshold B. Event occurs +// one sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEBNEG 0x00000010U +#define LRFDMDM_EVT2_C1BEBNEG_M 0x00000010U +#define LRFDMDM_EVT2_C1BEBNEG_S 4U +#define LRFDMDM_EVT2_C1BEBNEG_ONE 0x00000010U +#define LRFDMDM_EVT2_C1BEBNEG_ZERO 0x00000000U + +// Field: [3] C1BEBPOS +// +// C1BE correlator B, positive peak detect: corr B > threshold B. Event occurs +// one sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEBPOS 0x00000008U +#define LRFDMDM_EVT2_C1BEBPOS_M 0x00000008U +#define LRFDMDM_EVT2_C1BEBPOS_S 3U +#define LRFDMDM_EVT2_C1BEBPOS_ONE 0x00000008U +#define LRFDMDM_EVT2_C1BEBPOS_ZERO 0x00000000U + +// Field: [2] C1BEAANY +// +// C1BE correlator A, any peak detect: abs(corr A) > thr A. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEAANY 0x00000004U +#define LRFDMDM_EVT2_C1BEAANY_M 0x00000004U +#define LRFDMDM_EVT2_C1BEAANY_S 2U +#define LRFDMDM_EVT2_C1BEAANY_ONE 0x00000004U +#define LRFDMDM_EVT2_C1BEAANY_ZERO 0x00000000U + +// Field: [1] C1BEANEG +// +// C1BE correlator A, negative peak detect: corr A < -thr A. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEANEG 0x00000002U +#define LRFDMDM_EVT2_C1BEANEG_M 0x00000002U +#define LRFDMDM_EVT2_C1BEANEG_S 1U +#define LRFDMDM_EVT2_C1BEANEG_ONE 0x00000002U +#define LRFDMDM_EVT2_C1BEANEG_ZERO 0x00000000U + +// Field: [0] C1BEAPOS +// +// C1BE correlator A, positive peak detect: corr A > thr A. Event occurs one +// sample after actual peak. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_EVT2_C1BEAPOS 0x00000001U +#define LRFDMDM_EVT2_C1BEAPOS_M 0x00000001U +#define LRFDMDM_EVT2_C1BEAPOS_S 0U +#define LRFDMDM_EVT2_C1BEAPOS_ONE 0x00000001U +#define LRFDMDM_EVT2_C1BEAPOS_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTMSK0 +// +//***************************************************************************** +// Field: [15] PBEDAT +// +// Enable mask for event EVT0.PBEDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_PBEDAT 0x00008000U +#define LRFDMDM_EVTMSK0_PBEDAT_M 0x00008000U +#define LRFDMDM_EVTMSK0_PBEDAT_S 15U +#define LRFDMDM_EVTMSK0_PBEDAT_EN 0x00008000U +#define LRFDMDM_EVTMSK0_PBEDAT_DIS 0x00000000U + +// Field: [14] PBECMD +// +// Enable mask for event EVT0.PBECMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_PBECMD 0x00004000U +#define LRFDMDM_EVTMSK0_PBECMD_M 0x00004000U +#define LRFDMDM_EVTMSK0_PBECMD_S 14U +#define LRFDMDM_EVTMSK0_PBECMD_EN 0x00004000U +#define LRFDMDM_EVTMSK0_PBECMD_DIS 0x00000000U + +// Field: [13] RFEDAT +// +// Enable mask for event EVT0.RFEDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_RFEDAT 0x00002000U +#define LRFDMDM_EVTMSK0_RFEDAT_M 0x00002000U +#define LRFDMDM_EVTMSK0_RFEDAT_S 13U +#define LRFDMDM_EVTMSK0_RFEDAT_EN 0x00002000U +#define LRFDMDM_EVTMSK0_RFEDAT_DIS 0x00000000U + +// Field: [12] BDEC +// +// Enable mask for event EVT0.BDEC +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_BDEC 0x00001000U +#define LRFDMDM_EVTMSK0_BDEC_M 0x00001000U +#define LRFDMDM_EVTMSK0_BDEC_S 12U +#define LRFDMDM_EVTMSK0_BDEC_EN 0x00001000U +#define LRFDMDM_EVTMSK0_BDEC_DIS 0x00000000U + +// Field: [11] FRAC +// +// Enable mask for event EVT0.FRAC +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_FRAC 0x00000800U +#define LRFDMDM_EVTMSK0_FRAC_M 0x00000800U +#define LRFDMDM_EVTMSK0_FRAC_S 11U +#define LRFDMDM_EVTMSK0_FRAC_EN 0x00000800U +#define LRFDMDM_EVTMSK0_FRAC_DIS 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// Enable mask for event EVT0.SYSTIMEVT2 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_SYSTIMEVT2 0x00000400U +#define LRFDMDM_EVTMSK0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM_EVTMSK0_SYSTIMEVT2_S 10U +#define LRFDMDM_EVTMSK0_SYSTIMEVT2_EN 0x00000400U +#define LRFDMDM_EVTMSK0_SYSTIMEVT2_DIS 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// Enable mask for event EVT0.SYSTIMEVT1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_SYSTIMEVT1 0x00000200U +#define LRFDMDM_EVTMSK0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM_EVTMSK0_SYSTIMEVT1_S 9U +#define LRFDMDM_EVTMSK0_SYSTIMEVT1_EN 0x00000200U +#define LRFDMDM_EVTMSK0_SYSTIMEVT1_DIS 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// Enable mask for event EVT0.SYSTIMEVT0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_SYSTIMEVT0 0x00000100U +#define LRFDMDM_EVTMSK0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM_EVTMSK0_SYSTIMEVT0_S 8U +#define LRFDMDM_EVTMSK0_SYSTIMEVT0_EN 0x00000100U +#define LRFDMDM_EVTMSK0_SYSTIMEVT0_DIS 0x00000000U + +// Field: [7] FIFOWR +// +// Enable mask for event EVT0.FIFOWR +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_FIFOWR 0x00000080U +#define LRFDMDM_EVTMSK0_FIFOWR_M 0x00000080U +#define LRFDMDM_EVTMSK0_FIFOWR_S 7U +#define LRFDMDM_EVTMSK0_FIFOWR_EN 0x00000080U +#define LRFDMDM_EVTMSK0_FIFOWR_DIS 0x00000000U + +// Field: [6] COUNTER +// +// Enable mask for event EVT0.COUNTER +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_COUNTER 0x00000040U +#define LRFDMDM_EVTMSK0_COUNTER_M 0x00000040U +#define LRFDMDM_EVTMSK0_COUNTER_S 6U +#define LRFDMDM_EVTMSK0_COUNTER_EN 0x00000040U +#define LRFDMDM_EVTMSK0_COUNTER_DIS 0x00000000U + +// Field: [5] RFECMD +// +// Enable mask for event EVT0.RFECMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_RFECMD 0x00000020U +#define LRFDMDM_EVTMSK0_RFECMD_M 0x00000020U +#define LRFDMDM_EVTMSK0_RFECMD_S 5U +#define LRFDMDM_EVTMSK0_RFECMD_EN 0x00000020U +#define LRFDMDM_EVTMSK0_RFECMD_DIS 0x00000000U + +// Field: [4] FIFOOVFL +// +// Enable mask for event EVT0.FIFOOVFL +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_FIFOOVFL 0x00000010U +#define LRFDMDM_EVTMSK0_FIFOOVFL_M 0x00000010U +#define LRFDMDM_EVTMSK0_FIFOOVFL_S 4U +#define LRFDMDM_EVTMSK0_FIFOOVFL_EN 0x00000010U +#define LRFDMDM_EVTMSK0_FIFOOVFL_DIS 0x00000000U + +// Field: [3] FIFOUNFL +// +// Enable mask for event EVT0.FIFOUNFL +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_FIFOUNFL 0x00000008U +#define LRFDMDM_EVTMSK0_FIFOUNFL_M 0x00000008U +#define LRFDMDM_EVTMSK0_FIFOUNFL_S 3U +#define LRFDMDM_EVTMSK0_FIFOUNFL_EN 0x00000008U +#define LRFDMDM_EVTMSK0_FIFOUNFL_DIS 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// Enable mask for event EVT0.CLKEN4BAUD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_CLKEN4BAUD 0x00000004U +#define LRFDMDM_EVTMSK0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM_EVTMSK0_CLKEN4BAUD_S 2U +#define LRFDMDM_EVTMSK0_CLKEN4BAUD_EN 0x00000004U +#define LRFDMDM_EVTMSK0_CLKEN4BAUD_DIS 0x00000000U + +// Field: [1] TIMER +// +// Enable mask for event EVT0.TIMER +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_TIMER 0x00000002U +#define LRFDMDM_EVTMSK0_TIMER_M 0x00000002U +#define LRFDMDM_EVTMSK0_TIMER_S 1U +#define LRFDMDM_EVTMSK0_TIMER_EN 0x00000002U +#define LRFDMDM_EVTMSK0_TIMER_DIS 0x00000000U + +// Field: [0] MDMAPI +// +// Enable mask for event EVT0.MDMAPI +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK0_MDMAPI 0x00000001U +#define LRFDMDM_EVTMSK0_MDMAPI_M 0x00000001U +#define LRFDMDM_EVTMSK0_MDMAPI_S 0U +#define LRFDMDM_EVTMSK0_MDMAPI_EN 0x00000001U +#define LRFDMDM_EVTMSK0_MDMAPI_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTMSK1 +// +//***************************************************************************** +// Field: [8] REFCLK +// +// Enable mask for EVT1.REFCLK +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_REFCLK 0x00000100U +#define LRFDMDM_EVTMSK1_REFCLK_M 0x00000100U +#define LRFDMDM_EVTMSK1_REFCLK_S 8U +#define LRFDMDM_EVTMSK1_REFCLK_EN 0x00000100U +#define LRFDMDM_EVTMSK1_REFCLK_DIS 0x00000000U + +// Field: [7] S2RSTOP +// +// Enable mask for EVT1.S2RSTOP +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_S2RSTOP 0x00000080U +#define LRFDMDM_EVTMSK1_S2RSTOP_M 0x00000080U +#define LRFDMDM_EVTMSK1_S2RSTOP_S 7U +#define LRFDMDM_EVTMSK1_S2RSTOP_EN 0x00000080U +#define LRFDMDM_EVTMSK1_S2RSTOP_DIS 0x00000000U + +// Field: [6] SWQUFALSESYNC +// +// Enable mask for event EVT1.SWQUFALSESYNC +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_SWQUFALSESYNC 0x00000040U +#define LRFDMDM_EVTMSK1_SWQUFALSESYNC_M 0x00000040U +#define LRFDMDM_EVTMSK1_SWQUFALSESYNC_S 6U +#define LRFDMDM_EVTMSK1_SWQUFALSESYNC_EN 0x00000040U +#define LRFDMDM_EVTMSK1_SWQUFALSESYNC_DIS 0x00000000U + +// Field: [5] SWQUSYNCED +// +// Enable mask for event EVT1.SWQUSYNCED +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_SWQUSYNCED 0x00000020U +#define LRFDMDM_EVTMSK1_SWQUSYNCED_M 0x00000020U +#define LRFDMDM_EVTMSK1_SWQUSYNCED_S 5U +#define LRFDMDM_EVTMSK1_SWQUSYNCED_EN 0x00000020U +#define LRFDMDM_EVTMSK1_SWQUSYNCED_DIS 0x00000000U + +// Field: [4] CLKENBAUDF +// +// Enable mask for event EVT1.CLKENBAUDF +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_CLKENBAUDF 0x00000010U +#define LRFDMDM_EVTMSK1_CLKENBAUDF_M 0x00000010U +#define LRFDMDM_EVTMSK1_CLKENBAUDF_S 4U +#define LRFDMDM_EVTMSK1_CLKENBAUDF_EN 0x00000010U +#define LRFDMDM_EVTMSK1_CLKENBAUDF_DIS 0x00000000U + +// Field: [3] FIFORVALID +// +// Enable mask for event EVT1.FIFORVALID +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_FIFORVALID 0x00000008U +#define LRFDMDM_EVTMSK1_FIFORVALID_M 0x00000008U +#define LRFDMDM_EVTMSK1_FIFORVALID_S 3U +#define LRFDMDM_EVTMSK1_FIFORVALID_EN 0x00000008U +#define LRFDMDM_EVTMSK1_FIFORVALID_DIS 0x00000000U + +// Field: [2] FIFOWREADY +// +// Enable mask for event EVT1.FIFOWREADY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_FIFOWREADY 0x00000004U +#define LRFDMDM_EVTMSK1_FIFOWREADY_M 0x00000004U +#define LRFDMDM_EVTMSK1_FIFOWREADY_S 2U +#define LRFDMDM_EVTMSK1_FIFOWREADY_EN 0x00000004U +#define LRFDMDM_EVTMSK1_FIFOWREADY_DIS 0x00000000U + +// Field: [1] CLKENBAUD +// +// Enable mask for event EVT1.CLKENBAUD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_CLKENBAUD 0x00000002U +#define LRFDMDM_EVTMSK1_CLKENBAUD_M 0x00000002U +#define LRFDMDM_EVTMSK1_CLKENBAUD_S 1U +#define LRFDMDM_EVTMSK1_CLKENBAUD_EN 0x00000002U +#define LRFDMDM_EVTMSK1_CLKENBAUD_DIS 0x00000000U + +// Field: [0] PREAMBLEDONE +// +// Enable mask for event EVT1.PREAMBLEDONE +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK1_PREAMBLEDONE 0x00000001U +#define LRFDMDM_EVTMSK1_PREAMBLEDONE_M 0x00000001U +#define LRFDMDM_EVTMSK1_PREAMBLEDONE_S 0U +#define LRFDMDM_EVTMSK1_PREAMBLEDONE_EN 0x00000001U +#define LRFDMDM_EVTMSK1_PREAMBLEDONE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTMSK2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// Enable mask for event EVT2.GPI1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_GPI1 0x00008000U +#define LRFDMDM_EVTMSK2_GPI1_M 0x00008000U +#define LRFDMDM_EVTMSK2_GPI1_S 15U +#define LRFDMDM_EVTMSK2_GPI1_EN 0x00008000U +#define LRFDMDM_EVTMSK2_GPI1_DIS 0x00000000U + +// Field: [14] GPI0 +// +// Enable mask for event EVT2.GPI0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_GPI0 0x00004000U +#define LRFDMDM_EVTMSK2_GPI0_M 0x00004000U +#define LRFDMDM_EVTMSK2_GPI0_S 14U +#define LRFDMDM_EVTMSK2_GPI0_EN 0x00004000U +#define LRFDMDM_EVTMSK2_GPI0_DIS 0x00000000U + +// Field: [12] C1BEBLOADED +// +// Enable mask for event EVT2.C1BEBLOADED +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEBLOADED 0x00001000U +#define LRFDMDM_EVTMSK2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM_EVTMSK2_C1BEBLOADED_S 12U +#define LRFDMDM_EVTMSK2_C1BEBLOADED_EN 0x00001000U +#define LRFDMDM_EVTMSK2_C1BEBLOADED_DIS 0x00000000U + +// Field: [11] C1BECMBANY +// +// Enable mask for event EVT2.C1BECMBANY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECMBANY 0x00000800U +#define LRFDMDM_EVTMSK2_C1BECMBANY_M 0x00000800U +#define LRFDMDM_EVTMSK2_C1BECMBANY_S 11U +#define LRFDMDM_EVTMSK2_C1BECMBANY_EN 0x00000800U +#define LRFDMDM_EVTMSK2_C1BECMBANY_DIS 0x00000000U + +// Field: [10] C1BECMBNEG +// +// Enable mask for event EVT2.C1BECMBNEG +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECMBNEG 0x00000400U +#define LRFDMDM_EVTMSK2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM_EVTMSK2_C1BECMBNEG_S 10U +#define LRFDMDM_EVTMSK2_C1BECMBNEG_EN 0x00000400U +#define LRFDMDM_EVTMSK2_C1BECMBNEG_DIS 0x00000000U + +// Field: [9] C1BECMBPOS +// +// Enable mask for event EVT2.C1BECMBPOS +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECMBPOS 0x00000200U +#define LRFDMDM_EVTMSK2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM_EVTMSK2_C1BECMBPOS_S 9U +#define LRFDMDM_EVTMSK2_C1BECMBPOS_EN 0x00000200U +#define LRFDMDM_EVTMSK2_C1BECMBPOS_DIS 0x00000000U + +// Field: [8] C1BECANY +// +// Enable mask for event EVT2.C1BECANY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECANY 0x00000100U +#define LRFDMDM_EVTMSK2_C1BECANY_M 0x00000100U +#define LRFDMDM_EVTMSK2_C1BECANY_S 8U +#define LRFDMDM_EVTMSK2_C1BECANY_EN 0x00000100U +#define LRFDMDM_EVTMSK2_C1BECANY_DIS 0x00000000U + +// Field: [7] C1BECNEG +// +// Enable mask for event EVT2.C1BECNEG +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECNEG 0x00000080U +#define LRFDMDM_EVTMSK2_C1BECNEG_M 0x00000080U +#define LRFDMDM_EVTMSK2_C1BECNEG_S 7U +#define LRFDMDM_EVTMSK2_C1BECNEG_EN 0x00000080U +#define LRFDMDM_EVTMSK2_C1BECNEG_DIS 0x00000000U + +// Field: [6] C1BECPOS +// +// Enable mask for event EVT2.C1BECPOS +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BECPOS 0x00000040U +#define LRFDMDM_EVTMSK2_C1BECPOS_M 0x00000040U +#define LRFDMDM_EVTMSK2_C1BECPOS_S 6U +#define LRFDMDM_EVTMSK2_C1BECPOS_EN 0x00000040U +#define LRFDMDM_EVTMSK2_C1BECPOS_DIS 0x00000000U + +// Field: [5] C1BEBANY +// +// Enable mask for event EVT2.C1BEBANY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEBANY 0x00000020U +#define LRFDMDM_EVTMSK2_C1BEBANY_M 0x00000020U +#define LRFDMDM_EVTMSK2_C1BEBANY_S 5U +#define LRFDMDM_EVTMSK2_C1BEBANY_EN 0x00000020U +#define LRFDMDM_EVTMSK2_C1BEBANY_DIS 0x00000000U + +// Field: [4] C1BEBNEG +// +// Enable mask for event EVT2.C1BEBNEG +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEBNEG 0x00000010U +#define LRFDMDM_EVTMSK2_C1BEBNEG_M 0x00000010U +#define LRFDMDM_EVTMSK2_C1BEBNEG_S 4U +#define LRFDMDM_EVTMSK2_C1BEBNEG_EN 0x00000010U +#define LRFDMDM_EVTMSK2_C1BEBNEG_DIS 0x00000000U + +// Field: [3] C1BEBPOS +// +// Enable mask for event EVT2.C1BEBPOS +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEBPOS 0x00000008U +#define LRFDMDM_EVTMSK2_C1BEBPOS_M 0x00000008U +#define LRFDMDM_EVTMSK2_C1BEBPOS_S 3U +#define LRFDMDM_EVTMSK2_C1BEBPOS_EN 0x00000008U +#define LRFDMDM_EVTMSK2_C1BEBPOS_DIS 0x00000000U + +// Field: [2] C1BEAANY +// +// Enable mask for event EVT2.C1BEAANY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEAANY 0x00000004U +#define LRFDMDM_EVTMSK2_C1BEAANY_M 0x00000004U +#define LRFDMDM_EVTMSK2_C1BEAANY_S 2U +#define LRFDMDM_EVTMSK2_C1BEAANY_EN 0x00000004U +#define LRFDMDM_EVTMSK2_C1BEAANY_DIS 0x00000000U + +// Field: [1] C1BEANEG +// +// Enable mask for event EVT2.C1BEANEG +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEANEG 0x00000002U +#define LRFDMDM_EVTMSK2_C1BEANEG_M 0x00000002U +#define LRFDMDM_EVTMSK2_C1BEANEG_S 1U +#define LRFDMDM_EVTMSK2_C1BEANEG_EN 0x00000002U +#define LRFDMDM_EVTMSK2_C1BEANEG_DIS 0x00000000U + +// Field: [0] C1BEAPOS +// +// Enable mask for event EVT2.C1BEAPOS +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_EVTMSK2_C1BEAPOS 0x00000001U +#define LRFDMDM_EVTMSK2_C1BEAPOS_M 0x00000001U +#define LRFDMDM_EVTMSK2_C1BEAPOS_S 0U +#define LRFDMDM_EVTMSK2_C1BEAPOS_EN 0x00000001U +#define LRFDMDM_EVTMSK2_C1BEAPOS_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTCLR0 +// +//***************************************************************************** +// Field: [15] PBEDAT +// +// Clear event EVT0.PBEDAT +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_PBEDAT 0x00008000U +#define LRFDMDM_EVTCLR0_PBEDAT_M 0x00008000U +#define LRFDMDM_EVTCLR0_PBEDAT_S 15U +#define LRFDMDM_EVTCLR0_PBEDAT_CLEAR 0x00008000U +#define LRFDMDM_EVTCLR0_PBEDAT_RETAIN 0x00000000U + +// Field: [14] PBECMD +// +// Clear event EVT0.PBECMD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_PBECMD 0x00004000U +#define LRFDMDM_EVTCLR0_PBECMD_M 0x00004000U +#define LRFDMDM_EVTCLR0_PBECMD_S 14U +#define LRFDMDM_EVTCLR0_PBECMD_CLEAR 0x00004000U +#define LRFDMDM_EVTCLR0_PBECMD_RETAIN 0x00000000U + +// Field: [13] RFEDAT +// +// Clear event EVT0.RFEDAT +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_RFEDAT 0x00002000U +#define LRFDMDM_EVTCLR0_RFEDAT_M 0x00002000U +#define LRFDMDM_EVTCLR0_RFEDAT_S 13U +#define LRFDMDM_EVTCLR0_RFEDAT_CLEAR 0x00002000U +#define LRFDMDM_EVTCLR0_RFEDAT_RETAIN 0x00000000U + +// Field: [12] BDEC +// +// Clear event EVT0.BDEC +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_BDEC 0x00001000U +#define LRFDMDM_EVTCLR0_BDEC_M 0x00001000U +#define LRFDMDM_EVTCLR0_BDEC_S 12U +#define LRFDMDM_EVTCLR0_BDEC_CLEAR 0x00001000U +#define LRFDMDM_EVTCLR0_BDEC_RETAIN 0x00000000U + +// Field: [11] FRAC +// +// Clear event EVT0.FRAC +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_FRAC 0x00000800U +#define LRFDMDM_EVTCLR0_FRAC_M 0x00000800U +#define LRFDMDM_EVTCLR0_FRAC_S 11U +#define LRFDMDM_EVTCLR0_FRAC_CLEAR 0x00000800U +#define LRFDMDM_EVTCLR0_FRAC_RETAIN 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// Clear event EVT0.SYSTIMEVT2 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_SYSTIMEVT2 0x00000400U +#define LRFDMDM_EVTCLR0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM_EVTCLR0_SYSTIMEVT2_S 10U +#define LRFDMDM_EVTCLR0_SYSTIMEVT2_CLEAR 0x00000400U +#define LRFDMDM_EVTCLR0_SYSTIMEVT2_RETAIN 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// Clear event EVT0.SYSTIMEVT1 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_SYSTIMEVT1 0x00000200U +#define LRFDMDM_EVTCLR0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM_EVTCLR0_SYSTIMEVT1_S 9U +#define LRFDMDM_EVTCLR0_SYSTIMEVT1_CLEAR 0x00000200U +#define LRFDMDM_EVTCLR0_SYSTIMEVT1_RETAIN 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// Clear event EVT0.SYSTIMEVT0 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_SYSTIMEVT0 0x00000100U +#define LRFDMDM_EVTCLR0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM_EVTCLR0_SYSTIMEVT0_S 8U +#define LRFDMDM_EVTCLR0_SYSTIMEVT0_CLEAR 0x00000100U +#define LRFDMDM_EVTCLR0_SYSTIMEVT0_RETAIN 0x00000000U + +// Field: [7] FIFOWR +// +// Clear event EVT0.FIFOWR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_FIFOWR 0x00000080U +#define LRFDMDM_EVTCLR0_FIFOWR_M 0x00000080U +#define LRFDMDM_EVTCLR0_FIFOWR_S 7U +#define LRFDMDM_EVTCLR0_FIFOWR_CLEAR 0x00000080U +#define LRFDMDM_EVTCLR0_FIFOWR_RETAIN 0x00000000U + +// Field: [6] COUNTER +// +// Clear event EVT0.COUNTER +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_COUNTER 0x00000040U +#define LRFDMDM_EVTCLR0_COUNTER_M 0x00000040U +#define LRFDMDM_EVTCLR0_COUNTER_S 6U +#define LRFDMDM_EVTCLR0_COUNTER_CLEAR 0x00000040U +#define LRFDMDM_EVTCLR0_COUNTER_RETAIN 0x00000000U + +// Field: [5] RFECMD +// +// Clear event EVT0.RFECMD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_RFECMD 0x00000020U +#define LRFDMDM_EVTCLR0_RFECMD_M 0x00000020U +#define LRFDMDM_EVTCLR0_RFECMD_S 5U +#define LRFDMDM_EVTCLR0_RFECMD_CLEAR 0x00000020U +#define LRFDMDM_EVTCLR0_RFECMD_RETAIN 0x00000000U + +// Field: [4] FIFOOVFL +// +// Clear event EVT0.FIFOOVFL +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_FIFOOVFL 0x00000010U +#define LRFDMDM_EVTCLR0_FIFOOVFL_M 0x00000010U +#define LRFDMDM_EVTCLR0_FIFOOVFL_S 4U +#define LRFDMDM_EVTCLR0_FIFOOVFL_CLEAR 0x00000010U +#define LRFDMDM_EVTCLR0_FIFOOVFL_RETAIN 0x00000000U + +// Field: [3] FIFOUNFL +// +// Clear event EVT0.FIFOUNFL +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_FIFOUNFL 0x00000008U +#define LRFDMDM_EVTCLR0_FIFOUNFL_M 0x00000008U +#define LRFDMDM_EVTCLR0_FIFOUNFL_S 3U +#define LRFDMDM_EVTCLR0_FIFOUNFL_CLEAR 0x00000008U +#define LRFDMDM_EVTCLR0_FIFOUNFL_RETAIN 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// Clear event EVT0.CLKEN4BAUD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_CLKEN4BAUD 0x00000004U +#define LRFDMDM_EVTCLR0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM_EVTCLR0_CLKEN4BAUD_S 2U +#define LRFDMDM_EVTCLR0_CLKEN4BAUD_CLEAR 0x00000004U +#define LRFDMDM_EVTCLR0_CLKEN4BAUD_RETAIN 0x00000000U + +// Field: [1] TIMER +// +// Clear event EVT0.TIMER +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_TIMER 0x00000002U +#define LRFDMDM_EVTCLR0_TIMER_M 0x00000002U +#define LRFDMDM_EVTCLR0_TIMER_S 1U +#define LRFDMDM_EVTCLR0_TIMER_CLEAR 0x00000002U +#define LRFDMDM_EVTCLR0_TIMER_RETAIN 0x00000000U + +// Field: [0] MDMAPI +// +// Clear event EVT0.MDMAPI +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR0_MDMAPI 0x00000001U +#define LRFDMDM_EVTCLR0_MDMAPI_M 0x00000001U +#define LRFDMDM_EVTCLR0_MDMAPI_S 0U +#define LRFDMDM_EVTCLR0_MDMAPI_CLEAR 0x00000001U +#define LRFDMDM_EVTCLR0_MDMAPI_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTCLR1 +// +//***************************************************************************** +// Field: [8] REFCLK +// +// Clear event EVT1.REFCLK +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_REFCLK 0x00000100U +#define LRFDMDM_EVTCLR1_REFCLK_M 0x00000100U +#define LRFDMDM_EVTCLR1_REFCLK_S 8U +#define LRFDMDM_EVTCLR1_REFCLK_CLEAR 0x00000100U +#define LRFDMDM_EVTCLR1_REFCLK_RETAIN 0x00000000U + +// Field: [7] S2RSTOP +// +// Clear event EVT1.S2RSTOP +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_S2RSTOP 0x00000080U +#define LRFDMDM_EVTCLR1_S2RSTOP_M 0x00000080U +#define LRFDMDM_EVTCLR1_S2RSTOP_S 7U +#define LRFDMDM_EVTCLR1_S2RSTOP_CLEAR 0x00000080U +#define LRFDMDM_EVTCLR1_S2RSTOP_RETAIN 0x00000000U + +// Field: [6] SWQUFALSESYNC +// +// Clear event EVT1.SWQUFALSESYNC +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_SWQUFALSESYNC 0x00000040U +#define LRFDMDM_EVTCLR1_SWQUFALSESYNC_M 0x00000040U +#define LRFDMDM_EVTCLR1_SWQUFALSESYNC_S 6U +#define LRFDMDM_EVTCLR1_SWQUFALSESYNC_CLEAR 0x00000040U +#define LRFDMDM_EVTCLR1_SWQUFALSESYNC_RETAIN 0x00000000U + +// Field: [5] SWQUSYNCED +// +// Clear event EVT1.SWQUSYNCED +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_SWQUSYNCED 0x00000020U +#define LRFDMDM_EVTCLR1_SWQUSYNCED_M 0x00000020U +#define LRFDMDM_EVTCLR1_SWQUSYNCED_S 5U +#define LRFDMDM_EVTCLR1_SWQUSYNCED_CLEAR 0x00000020U +#define LRFDMDM_EVTCLR1_SWQUSYNCED_RETAIN 0x00000000U + +// Field: [4] CLKENBAUDF +// +// Clear event EVT1.CLKENBAUDF +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_CLKENBAUDF 0x00000010U +#define LRFDMDM_EVTCLR1_CLKENBAUDF_M 0x00000010U +#define LRFDMDM_EVTCLR1_CLKENBAUDF_S 4U +#define LRFDMDM_EVTCLR1_CLKENBAUDF_CLEAR 0x00000010U +#define LRFDMDM_EVTCLR1_CLKENBAUDF_RETAIN 0x00000000U + +// Field: [3] FIFORVALID +// +// Clear event EVT1.FIFORVALID +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_FIFORVALID 0x00000008U +#define LRFDMDM_EVTCLR1_FIFORVALID_M 0x00000008U +#define LRFDMDM_EVTCLR1_FIFORVALID_S 3U +#define LRFDMDM_EVTCLR1_FIFORVALID_CLEAR 0x00000008U +#define LRFDMDM_EVTCLR1_FIFORVALID_RETAIN 0x00000000U + +// Field: [2] FIFOWREADY +// +// Clear event EVT1.FIFOWREADY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_FIFOWREADY 0x00000004U +#define LRFDMDM_EVTCLR1_FIFOWREADY_M 0x00000004U +#define LRFDMDM_EVTCLR1_FIFOWREADY_S 2U +#define LRFDMDM_EVTCLR1_FIFOWREADY_CLEAR 0x00000004U +#define LRFDMDM_EVTCLR1_FIFOWREADY_RETAIN 0x00000000U + +// Field: [1] CLKENBAUD +// +// Clear event EVT1.CLKENBAUD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_CLKENBAUD 0x00000002U +#define LRFDMDM_EVTCLR1_CLKENBAUD_M 0x00000002U +#define LRFDMDM_EVTCLR1_CLKENBAUD_S 1U +#define LRFDMDM_EVTCLR1_CLKENBAUD_CLEAR 0x00000002U +#define LRFDMDM_EVTCLR1_CLKENBAUD_RETAIN 0x00000000U + +// Field: [0] PREAMBLEDONE +// +// Clear event EVT1.PREAMBLEDONE +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR1_PREAMBLEDONE 0x00000001U +#define LRFDMDM_EVTCLR1_PREAMBLEDONE_M 0x00000001U +#define LRFDMDM_EVTCLR1_PREAMBLEDONE_S 0U +#define LRFDMDM_EVTCLR1_PREAMBLEDONE_CLEAR 0x00000001U +#define LRFDMDM_EVTCLR1_PREAMBLEDONE_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_EVTCLR2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// Clear event EVT2.GPI1 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_GPI1 0x00008000U +#define LRFDMDM_EVTCLR2_GPI1_M 0x00008000U +#define LRFDMDM_EVTCLR2_GPI1_S 15U +#define LRFDMDM_EVTCLR2_GPI1_CLEAR 0x00008000U +#define LRFDMDM_EVTCLR2_GPI1_RETAIN 0x00000000U + +// Field: [14] GPI0 +// +// Clear event EVT2.GPI0 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_GPI0 0x00004000U +#define LRFDMDM_EVTCLR2_GPI0_M 0x00004000U +#define LRFDMDM_EVTCLR2_GPI0_S 14U +#define LRFDMDM_EVTCLR2_GPI0_CLEAR 0x00004000U +#define LRFDMDM_EVTCLR2_GPI0_RETAIN 0x00000000U + +// Field: [12] C1BEBLOADED +// +// Clear event EVT2.C1BEBLOADED +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEBLOADED 0x00001000U +#define LRFDMDM_EVTCLR2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM_EVTCLR2_C1BEBLOADED_S 12U +#define LRFDMDM_EVTCLR2_C1BEBLOADED_CLEAR 0x00001000U +#define LRFDMDM_EVTCLR2_C1BEBLOADED_RETAIN 0x00000000U + +// Field: [11] C1BECMBANY +// +// Clear event EVT2.C1BECMBANY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECMBANY 0x00000800U +#define LRFDMDM_EVTCLR2_C1BECMBANY_M 0x00000800U +#define LRFDMDM_EVTCLR2_C1BECMBANY_S 11U +#define LRFDMDM_EVTCLR2_C1BECMBANY_CLEAR 0x00000800U +#define LRFDMDM_EVTCLR2_C1BECMBANY_RETAIN 0x00000000U + +// Field: [10] C1BECMBNEG +// +// Clear event EVT2.C1BECMBNEG +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECMBNEG 0x00000400U +#define LRFDMDM_EVTCLR2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM_EVTCLR2_C1BECMBNEG_S 10U +#define LRFDMDM_EVTCLR2_C1BECMBNEG_CLEAR 0x00000400U +#define LRFDMDM_EVTCLR2_C1BECMBNEG_RETAIN 0x00000000U + +// Field: [9] C1BECMBPOS +// +// Clear event EVT2.C1BECMBPOS +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECMBPOS 0x00000200U +#define LRFDMDM_EVTCLR2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM_EVTCLR2_C1BECMBPOS_S 9U +#define LRFDMDM_EVTCLR2_C1BECMBPOS_CLEAR 0x00000200U +#define LRFDMDM_EVTCLR2_C1BECMBPOS_RETAIN 0x00000000U + +// Field: [8] C1BECANY +// +// Clear event EVT2.C1BECANY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECANY 0x00000100U +#define LRFDMDM_EVTCLR2_C1BECANY_M 0x00000100U +#define LRFDMDM_EVTCLR2_C1BECANY_S 8U +#define LRFDMDM_EVTCLR2_C1BECANY_CLEAR 0x00000100U +#define LRFDMDM_EVTCLR2_C1BECANY_RETAIN 0x00000000U + +// Field: [7] C1BECNEG +// +// Clear event EVT2.C1BECNEG +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECNEG 0x00000080U +#define LRFDMDM_EVTCLR2_C1BECNEG_M 0x00000080U +#define LRFDMDM_EVTCLR2_C1BECNEG_S 7U +#define LRFDMDM_EVTCLR2_C1BECNEG_CLEAR 0x00000080U +#define LRFDMDM_EVTCLR2_C1BECNEG_RETAIN 0x00000000U + +// Field: [6] C1BECPOS +// +// Clear event EVT2.C1BECPOS +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BECPOS 0x00000040U +#define LRFDMDM_EVTCLR2_C1BECPOS_M 0x00000040U +#define LRFDMDM_EVTCLR2_C1BECPOS_S 6U +#define LRFDMDM_EVTCLR2_C1BECPOS_CLEAR 0x00000040U +#define LRFDMDM_EVTCLR2_C1BECPOS_RETAIN 0x00000000U + +// Field: [5] C1BEBANY +// +// Clear event EVT2.C1BEBANY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEBANY 0x00000020U +#define LRFDMDM_EVTCLR2_C1BEBANY_M 0x00000020U +#define LRFDMDM_EVTCLR2_C1BEBANY_S 5U +#define LRFDMDM_EVTCLR2_C1BEBANY_CLEAR 0x00000020U +#define LRFDMDM_EVTCLR2_C1BEBANY_RETAIN 0x00000000U + +// Field: [4] C1BEBNEG +// +// Clear event EVT2.C1BEBNEG +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEBNEG 0x00000010U +#define LRFDMDM_EVTCLR2_C1BEBNEG_M 0x00000010U +#define LRFDMDM_EVTCLR2_C1BEBNEG_S 4U +#define LRFDMDM_EVTCLR2_C1BEBNEG_CLEAR 0x00000010U +#define LRFDMDM_EVTCLR2_C1BEBNEG_RETAIN 0x00000000U + +// Field: [3] C1BEBPOS +// +// Clear event EVT2.C1BEBPOS +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEBPOS 0x00000008U +#define LRFDMDM_EVTCLR2_C1BEBPOS_M 0x00000008U +#define LRFDMDM_EVTCLR2_C1BEBPOS_S 3U +#define LRFDMDM_EVTCLR2_C1BEBPOS_CLEAR 0x00000008U +#define LRFDMDM_EVTCLR2_C1BEBPOS_RETAIN 0x00000000U + +// Field: [2] C1BEAANY +// +// Clear event EVT2.C1BEAANY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEAANY 0x00000004U +#define LRFDMDM_EVTCLR2_C1BEAANY_M 0x00000004U +#define LRFDMDM_EVTCLR2_C1BEAANY_S 2U +#define LRFDMDM_EVTCLR2_C1BEAANY_CLEAR 0x00000004U +#define LRFDMDM_EVTCLR2_C1BEAANY_RETAIN 0x00000000U + +// Field: [1] C1BEANEG +// +// Clear event EVT2.C1BEANEG +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEANEG 0x00000002U +#define LRFDMDM_EVTCLR2_C1BEANEG_M 0x00000002U +#define LRFDMDM_EVTCLR2_C1BEANEG_S 1U +#define LRFDMDM_EVTCLR2_C1BEANEG_CLEAR 0x00000002U +#define LRFDMDM_EVTCLR2_C1BEANEG_RETAIN 0x00000000U + +// Field: [0] C1BEAPOS +// +// Clear event EVT2.C1BEAPOS +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM_EVTCLR2_C1BEAPOS 0x00000001U +#define LRFDMDM_EVTCLR2_C1BEAPOS_M 0x00000001U +#define LRFDMDM_EVTCLR2_C1BEAPOS_S 0U +#define LRFDMDM_EVTCLR2_C1BEAPOS_CLEAR 0x00000001U +#define LRFDMDM_EVTCLR2_C1BEAPOS_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PDREQ +// +//***************************************************************************** +// Field: [0] TOPSMPDREQ +// +// Requests power-down for TOPsm core. If the TOPsm has an ongoing memory +// access, the hardware will safely gate the clock after the transaction has +// completed. +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_PDREQ_TOPSMPDREQ 0x00000001U +#define LRFDMDM_PDREQ_TOPSMPDREQ_M 0x00000001U +#define LRFDMDM_PDREQ_TOPSMPDREQ_S 0U +#define LRFDMDM_PDREQ_TOPSMPDREQ_ON 0x00000001U +#define LRFDMDM_PDREQ_TOPSMPDREQ_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_API +// +//***************************************************************************** +// Field: [7:4] PROTOCOLID +// +// Protocol ID +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_API_PROTOCOLID_W 4U +#define LRFDMDM_API_PROTOCOLID_M 0x000000F0U +#define LRFDMDM_API_PROTOCOLID_S 4U +#define LRFDMDM_API_PROTOCOLID_ALLONES 0x000000F0U +#define LRFDMDM_API_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [3:0] MDMCMD +// +// Modem command +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All bits are 0 +#define LRFDMDM_API_MDMCMD_W 4U +#define LRFDMDM_API_MDMCMD_M 0x0000000FU +#define LRFDMDM_API_MDMCMD_S 0U +#define LRFDMDM_API_MDMCMD_ALLONES 0x0000000FU +#define LRFDMDM_API_MDMCMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_CMDPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0, software defined function +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_CMDPAR0_VAL_W 16U +#define LRFDMDM_CMDPAR0_VAL_M 0x0000FFFFU +#define LRFDMDM_CMDPAR0_VAL_S 0U +#define LRFDMDM_CMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_CMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_CMDPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1, software defined function +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_CMDPAR1_VAL_W 16U +#define LRFDMDM_CMDPAR1_VAL_M 0x0000FFFFU +#define LRFDMDM_CMDPAR1_VAL_S 0U +#define LRFDMDM_CMDPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_CMDPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_CMDPAR2 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 2, software defined function +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_CMDPAR2_VAL_W 16U +#define LRFDMDM_CMDPAR2_VAL_M 0x0000FFFFU +#define LRFDMDM_CMDPAR2_VAL_S 0U +#define LRFDMDM_CMDPAR2_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_CMDPAR2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MSGBOX +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Diverse status, error, report bits from MCE. Readable as well in PBE. +// Controlled by software. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MSGBOX_VAL_W 8U +#define LRFDMDM_MSGBOX_VAL_M 0x000000FFU +#define LRFDMDM_MSGBOX_VAL_S 0U +#define LRFDMDM_MSGBOX_VAL_ALLONES 0x000000FFU +#define LRFDMDM_MSGBOX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FREQ +// +//***************************************************************************** +// Field: [15:0] OFFSET +// +// Frequency Offset from MCE, controlled by software +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_FREQ_OFFSET_W 16U +#define LRFDMDM_FREQ_OFFSET_M 0x0000FFFFU +#define LRFDMDM_FREQ_OFFSET_S 0U +#define LRFDMDM_FREQ_OFFSET_ALLONES 0x0000FFFFU +#define LRFDMDM_FREQ_OFFSET_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FIFOWR +// +//***************************************************************************** +// Field: [15:0] PAYLOADIN +// +// FIFO write port. The actual port size is configurable in FIFOWRCTRL +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_FIFOWR_PAYLOADIN_W 16U +#define LRFDMDM_FIFOWR_PAYLOADIN_M 0x0000FFFFU +#define LRFDMDM_FIFOWR_PAYLOADIN_S 0U +#define LRFDMDM_FIFOWR_PAYLOADIN_ALLONES 0x0000FFFFU +#define LRFDMDM_FIFOWR_PAYLOADIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FIFORD +// +//***************************************************************************** +// Field: [15:0] PAYLOADOUT +// +// FIFO read port. The actual port size is configurable in FIFORDCTRL +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_FIFORD_PAYLOADOUT_W 16U +#define LRFDMDM_FIFORD_PAYLOADOUT_M 0x0000FFFFU +#define LRFDMDM_FIFORD_PAYLOADOUT_S 0U +#define LRFDMDM_FIFORD_PAYLOADOUT_ALLONES 0x0000FFFFU +#define LRFDMDM_FIFORD_PAYLOADOUT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FIFOWRCTRL +// +//***************************************************************************** +// Field: [5:4] FIFOWRPORT +// +// FIFO write port mapping +// ENUMs: +// PBE PBE has write access +// MODEM Modem has write access +// MDMFIFOWR The FIFOWR register is used for write access +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_W 2U +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_M 0x00000030U +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_S 4U +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_PBE 0x00000020U +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_MODEM 0x00000010U +#define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_MDMFIFOWR 0x00000000U + +// Field: [3:0] WORDSZWR +// +// Actual bits in every word write access +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_W 4U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_M 0x0000000FU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_S 0U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS16 0x0000000FU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS15 0x0000000EU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS14 0x0000000DU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS13 0x0000000CU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS12 0x0000000BU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS11 0x0000000AU +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS10 0x00000009U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS9 0x00000008U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS8 0x00000007U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS7 0x00000006U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS6 0x00000005U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS5 0x00000004U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS4 0x00000003U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS3 0x00000002U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS2 0x00000001U +#define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FIFORDCTRL +// +//***************************************************************************** +// Field: [5:4] FIFORDPORT +// +// FIFO read port mapping +// ENUMs: +// PBE PBE has read access +// MODEM Modem has read access +// MDMFIFORD The FIFORD register is used for read access +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_W 2U +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_M 0x00000030U +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_S 4U +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_PBE 0x00000020U +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_MODEM 0x00000010U +#define LRFDMDM_FIFORDCTRL_FIFORDPORT_MDMFIFORD 0x00000000U + +// Field: [3:0] WORDSZRD +// +// Actual bits in every word read access +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDMDM_FIFORDCTRL_WORDSZRD_W 4U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_M 0x0000000FU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_S 0U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS16 0x0000000FU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS15 0x0000000EU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS14 0x0000000DU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS13 0x0000000CU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS12 0x0000000BU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS11 0x0000000AU +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS10 0x00000009U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS9 0x00000008U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS8 0x00000007U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS7 0x00000006U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS6 0x00000005U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS5 0x00000004U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS4 0x00000003U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS3 0x00000002U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS2 0x00000001U +#define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FIFOSTA +// +//***************************************************************************** +// Field: [5] OVERFLOW +// +// FIFO overflow error. If this flag is asserted the modem FIFO must be +// re-initialized with INIT.TXRXFIFO to clear it. Note that re-initializing +// will flush the FIFO. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_OVERFLOW 0x00000020U +#define LRFDMDM_FIFOSTA_OVERFLOW_M 0x00000020U +#define LRFDMDM_FIFOSTA_OVERFLOW_S 5U +#define LRFDMDM_FIFOSTA_OVERFLOW_ONE 0x00000020U +#define LRFDMDM_FIFOSTA_OVERFLOW_ZERO 0x00000000U + +// Field: [4] ALMOSTFULL +// +// FIFO is almost full. Asserts when the FIFO fill level is above the almost +// full threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_ALMOSTFULL 0x00000010U +#define LRFDMDM_FIFOSTA_ALMOSTFULL_M 0x00000010U +#define LRFDMDM_FIFOSTA_ALMOSTFULL_S 4U +#define LRFDMDM_FIFOSTA_ALMOSTFULL_ONE 0x00000010U +#define LRFDMDM_FIFOSTA_ALMOSTFULL_ZERO 0x00000000U + +// Field: [3] ALMOSTEMPTY +// +// FIFO is almost empty. Asserts when the FIFO fill level is below the almost +// empty threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_ALMOSTEMPTY 0x00000008U +#define LRFDMDM_FIFOSTA_ALMOSTEMPTY_M 0x00000008U +#define LRFDMDM_FIFOSTA_ALMOSTEMPTY_S 3U +#define LRFDMDM_FIFOSTA_ALMOSTEMPTY_ONE 0x00000008U +#define LRFDMDM_FIFOSTA_ALMOSTEMPTY_ZERO 0x00000000U + +// Field: [2] UNDERFLOW +// +// FIFO underflow error. If this flag is asserted the modem FIFO must be +// re-initialized with INIT.TXRXFIFO to clear it. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_UNDERFLOW 0x00000004U +#define LRFDMDM_FIFOSTA_UNDERFLOW_M 0x00000004U +#define LRFDMDM_FIFOSTA_UNDERFLOW_S 2U +#define LRFDMDM_FIFOSTA_UNDERFLOW_ONE 0x00000004U +#define LRFDMDM_FIFOSTA_UNDERFLOW_ZERO 0x00000000U + +// Field: [1] RXVALID +// +// A full data word is valid and can be read in FIFORD register read port. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_RXVALID 0x00000002U +#define LRFDMDM_FIFOSTA_RXVALID_M 0x00000002U +#define LRFDMDM_FIFOSTA_RXVALID_S 1U +#define LRFDMDM_FIFOSTA_RXVALID_ONE 0x00000002U +#define LRFDMDM_FIFOSTA_RXVALID_ZERO 0x00000000U + +// Field: [0] TXREADY +// +// The FIFOWR register write port is ready to receive a data word. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_FIFOSTA_TXREADY 0x00000001U +#define LRFDMDM_FIFOSTA_TXREADY_M 0x00000001U +#define LRFDMDM_FIFOSTA_TXREADY_S 0U +#define LRFDMDM_FIFOSTA_TXREADY_ONE 0x00000001U +#define LRFDMDM_FIFOSTA_TXREADY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to RFE. Writing to this register will trigger an event in the +// RFE, and the command value written here will be readable in +// LRFDRFE:MCEDATIN0 register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFEDATOUT0_VAL_W 16U +#define LRFDMDM_RFEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDMDM_RFEDATOUT0_VAL_S 0U +#define LRFDMDM_RFEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_RFEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from RFE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFEDATIN0_VAL_W 16U +#define LRFDMDM_RFEDATIN0_VAL_M 0x0000FFFFU +#define LRFDMDM_RFEDATIN0_VAL_S 0U +#define LRFDMDM_RFEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_RFEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to RFE. Writing to this register will trigger an event in +// the RFE, and the command value written here will be readable in +// LRFDRFE:MCECMDIN register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFECMDOUT_VAL_W 4U +#define LRFDMDM_RFECMDOUT_VAL_M 0x0000000FU +#define LRFDMDM_RFECMDOUT_VAL_S 0U +#define LRFDMDM_RFECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDMDM_RFECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from RFE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFECMDIN_VAL_W 4U +#define LRFDMDM_RFECMDIN_VAL_M 0x0000000FU +#define LRFDMDM_RFECMDIN_VAL_S 0U +#define LRFDMDM_RFECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDMDM_RFECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PBEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to PBE. Writing to this register will trigger an event in the +// PBE, and the command value written here will be readable in +// LRFDPBE:MCEDATIN0 register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_PBEDATOUT0_VAL_W 16U +#define LRFDMDM_PBEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDMDM_PBEDATOUT0_VAL_S 0U +#define LRFDMDM_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_PBEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PBEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from PBE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_PBEDATIN0_VAL_W 16U +#define LRFDMDM_PBEDATIN0_VAL_M 0x0000FFFFU +#define LRFDMDM_PBEDATIN0_VAL_S 0U +#define LRFDMDM_PBEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_PBEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PBECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to PBE. Writing to this register will trigger an event in +// the PBE, and the command value written here will be readable in +// LRFDPBE:MCECMDIN register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_PBECMDOUT_VAL_W 4U +#define LRFDMDM_PBECMDOUT_VAL_M 0x0000000FU +#define LRFDMDM_PBECMDOUT_VAL_S 0U +#define LRFDMDM_PBECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDMDM_PBECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PBECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from PBE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_PBECMDIN_VAL_W 4U +#define LRFDMDM_PBECMDIN_VAL_M 0x0000000FU +#define LRFDMDM_PBECMDIN_VAL_S 0U +#define LRFDMDM_PBECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDMDM_PBECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_LQIEST +// +//***************************************************************************** +// Field: [7:0] VAL +// +// LQI Estimate value to PBE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_LQIEST_VAL_W 8U +#define LRFDMDM_LQIEST_VAL_M 0x000000FFU +#define LRFDMDM_LQIEST_VAL_S 0U +#define LRFDMDM_LQIEST_VAL_ALLONES 0x000000FFU +#define LRFDMDM_LQIEST_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_PBEEVTMUX +// +//***************************************************************************** +// Field: [5:0] SEL +// +// Select one internal event and route to the PBE for usage in the event-unit +// there +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_PBEEVTMUX_SEL_W 6U +#define LRFDMDM_PBEEVTMUX_SEL_M 0x0000003FU +#define LRFDMDM_PBEEVTMUX_SEL_S 0U +#define LRFDMDM_PBEEVTMUX_SEL_ALLONES 0x0000003FU +#define LRFDMDM_PBEEVTMUX_SEL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYSTIMEVTMUX0 +// +//***************************************************************************** +// Field: [11:6] SEL1 +// +// Selects one source to send to the systimer output event 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYSTIMEVTMUX0_SEL1_W 6U +#define LRFDMDM_SYSTIMEVTMUX0_SEL1_M 0x00000FC0U +#define LRFDMDM_SYSTIMEVTMUX0_SEL1_S 6U +#define LRFDMDM_SYSTIMEVTMUX0_SEL1_ALLONES 0x00000FC0U +#define LRFDMDM_SYSTIMEVTMUX0_SEL1_ALLZEROS 0x00000000U + +// Field: [5:0] SEL0 +// +// Selects one source to send to the systimer output event 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYSTIMEVTMUX0_SEL0_W 6U +#define LRFDMDM_SYSTIMEVTMUX0_SEL0_M 0x0000003FU +#define LRFDMDM_SYSTIMEVTMUX0_SEL0_S 0U +#define LRFDMDM_SYSTIMEVTMUX0_SEL0_ALLONES 0x0000003FU +#define LRFDMDM_SYSTIMEVTMUX0_SEL0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYSTIMEVTMUX1 +// +//***************************************************************************** +// Field: [5:0] SEL2 +// +// Selects one source to send to the systimer output event 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYSTIMEVTMUX1_SEL2_W 6U +#define LRFDMDM_SYSTIMEVTMUX1_SEL2_M 0x0000003FU +#define LRFDMDM_SYSTIMEVTMUX1_SEL2_S 0U +#define LRFDMDM_SYSTIMEVTMUX1_SEL2_ALLONES 0x0000003FU +#define LRFDMDM_SYSTIMEVTMUX1_SEL2_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_ADCDIGCONF +// +//***************************************************************************** +// Field: [1] QBRANCHEN +// +// Enables Q component data branch in ADCDIG +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_ADCDIGCONF_QBRANCHEN 0x00000002U +#define LRFDMDM_ADCDIGCONF_QBRANCHEN_M 0x00000002U +#define LRFDMDM_ADCDIGCONF_QBRANCHEN_S 1U +#define LRFDMDM_ADCDIGCONF_QBRANCHEN_ON 0x00000002U +#define LRFDMDM_ADCDIGCONF_QBRANCHEN_OFF 0x00000000U + +// Field: [0] IBRANCHEN +// +// Enables I component data branch in ADCDIG +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_ADCDIGCONF_IBRANCHEN 0x00000001U +#define LRFDMDM_ADCDIGCONF_IBRANCHEN_M 0x00000001U +#define LRFDMDM_ADCDIGCONF_IBRANCHEN_S 0U +#define LRFDMDM_ADCDIGCONF_IBRANCHEN_ON 0x00000001U +#define LRFDMDM_ADCDIGCONF_IBRANCHEN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODPRECTRL +// +//***************************************************************************** +// Field: [7:4] REPS +// +// Number of preamble repetitions of preamble pattern +// ENUMs: +// REPS16 16 repetitions +// REPS15 15 repetitions +// REPS14 14 repetitions +// REPS13 13 repetitions +// REPS12 12 repetitions +// REPS11 11 repetitions +// REPS10 10 repetitions +// REPS9 9 repetitions +// REPS8 8 repetitions +// REPS7 7 repetitions +// REPS6 6 repetitions +// REPS5 5 repetitions +// REPS4 4 repetitions +// REPS3 3 repetitions +// REPS2 2 repetitions +// REPS1 1 repetition (i.e. only once) +#define LRFDMDM_MODPRECTRL_REPS_W 4U +#define LRFDMDM_MODPRECTRL_REPS_M 0x000000F0U +#define LRFDMDM_MODPRECTRL_REPS_S 4U +#define LRFDMDM_MODPRECTRL_REPS_REPS16 0x000000F0U +#define LRFDMDM_MODPRECTRL_REPS_REPS15 0x000000E0U +#define LRFDMDM_MODPRECTRL_REPS_REPS14 0x000000D0U +#define LRFDMDM_MODPRECTRL_REPS_REPS13 0x000000C0U +#define LRFDMDM_MODPRECTRL_REPS_REPS12 0x000000B0U +#define LRFDMDM_MODPRECTRL_REPS_REPS11 0x000000A0U +#define LRFDMDM_MODPRECTRL_REPS_REPS10 0x00000090U +#define LRFDMDM_MODPRECTRL_REPS_REPS9 0x00000080U +#define LRFDMDM_MODPRECTRL_REPS_REPS8 0x00000070U +#define LRFDMDM_MODPRECTRL_REPS_REPS7 0x00000060U +#define LRFDMDM_MODPRECTRL_REPS_REPS6 0x00000050U +#define LRFDMDM_MODPRECTRL_REPS_REPS5 0x00000040U +#define LRFDMDM_MODPRECTRL_REPS_REPS4 0x00000030U +#define LRFDMDM_MODPRECTRL_REPS_REPS3 0x00000020U +#define LRFDMDM_MODPRECTRL_REPS_REPS2 0x00000010U +#define LRFDMDM_MODPRECTRL_REPS_REPS1 0x00000000U + +// Field: [3:0] SIZE +// +// Preamble pattern size in bits +// ENUMs: +// BITS16 16 bits +// BITS8 8 bits +// BITS4 4 bits +#define LRFDMDM_MODPRECTRL_SIZE_W 4U +#define LRFDMDM_MODPRECTRL_SIZE_M 0x0000000FU +#define LRFDMDM_MODPRECTRL_SIZE_S 0U +#define LRFDMDM_MODPRECTRL_SIZE_BITS16 0x0000000FU +#define LRFDMDM_MODPRECTRL_SIZE_BITS8 0x00000007U +#define LRFDMDM_MODPRECTRL_SIZE_BITS4 0x00000003U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODSYMMAP0 +// +//***************************************************************************** +// Field: [15:12] SYM3 +// +// Decimal value for bits '11' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP0_SYM3_W 4U +#define LRFDMDM_MODSYMMAP0_SYM3_M 0x0000F000U +#define LRFDMDM_MODSYMMAP0_SYM3_S 12U +#define LRFDMDM_MODSYMMAP0_SYM3_ALLONES 0x0000F000U +#define LRFDMDM_MODSYMMAP0_SYM3_ALLZEROS 0x00000000U + +// Field: [11:8] SYM2 +// +// Decimal value for bits '10' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP0_SYM2_W 4U +#define LRFDMDM_MODSYMMAP0_SYM2_M 0x00000F00U +#define LRFDMDM_MODSYMMAP0_SYM2_S 8U +#define LRFDMDM_MODSYMMAP0_SYM2_ALLONES 0x00000F00U +#define LRFDMDM_MODSYMMAP0_SYM2_ALLZEROS 0x00000000U + +// Field: [7:4] SYM1 +// +// Decimal value for bit '1' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP0_SYM1_W 4U +#define LRFDMDM_MODSYMMAP0_SYM1_M 0x000000F0U +#define LRFDMDM_MODSYMMAP0_SYM1_S 4U +#define LRFDMDM_MODSYMMAP0_SYM1_ALLONES 0x000000F0U +#define LRFDMDM_MODSYMMAP0_SYM1_ALLZEROS 0x00000000U + +// Field: [3:0] SYM0 +// +// Decimal value for bit '0' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP0_SYM0_W 4U +#define LRFDMDM_MODSYMMAP0_SYM0_M 0x0000000FU +#define LRFDMDM_MODSYMMAP0_SYM0_S 0U +#define LRFDMDM_MODSYMMAP0_SYM0_ALLONES 0x0000000FU +#define LRFDMDM_MODSYMMAP0_SYM0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODSYMMAP1 +// +//***************************************************************************** +// Field: [15:12] SYM7 +// +// Decimal value for bits '111' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP1_SYM7_W 4U +#define LRFDMDM_MODSYMMAP1_SYM7_M 0x0000F000U +#define LRFDMDM_MODSYMMAP1_SYM7_S 12U +#define LRFDMDM_MODSYMMAP1_SYM7_ALLONES 0x0000F000U +#define LRFDMDM_MODSYMMAP1_SYM7_ALLZEROS 0x00000000U + +// Field: [11:8] SYM6 +// +// Decimal value for bits '110' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP1_SYM6_W 4U +#define LRFDMDM_MODSYMMAP1_SYM6_M 0x00000F00U +#define LRFDMDM_MODSYMMAP1_SYM6_S 8U +#define LRFDMDM_MODSYMMAP1_SYM6_ALLONES 0x00000F00U +#define LRFDMDM_MODSYMMAP1_SYM6_ALLZEROS 0x00000000U + +// Field: [7:4] SYM5 +// +// Decimal value for bits '101' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP1_SYM5_W 4U +#define LRFDMDM_MODSYMMAP1_SYM5_M 0x000000F0U +#define LRFDMDM_MODSYMMAP1_SYM5_S 4U +#define LRFDMDM_MODSYMMAP1_SYM5_ALLONES 0x000000F0U +#define LRFDMDM_MODSYMMAP1_SYM5_ALLZEROS 0x00000000U + +// Field: [3:0] SYM4 +// +// Decimal value for bits '100' +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSYMMAP1_SYM4_W 4U +#define LRFDMDM_MODSYMMAP1_SYM4_M 0x0000000FU +#define LRFDMDM_MODSYMMAP1_SYM4_S 0U +#define LRFDMDM_MODSYMMAP1_SYM4_ALLONES 0x0000000FU +#define LRFDMDM_MODSYMMAP1_SYM4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODSOFTTX +// +//***************************************************************************** +// Field: [3:0] SOFTSYMBOL +// +// Soft symbol {-7..+7} used when MODCTRL.SOFTTXENABLE is enabled. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODSOFTTX_SOFTSYMBOL_W 4U +#define LRFDMDM_MODSOFTTX_SOFTSYMBOL_M 0x0000000FU +#define LRFDMDM_MODSOFTTX_SOFTSYMBOL_S 0U +#define LRFDMDM_MODSOFTTX_SOFTSYMBOL_ALLONES 0x0000000FU +#define LRFDMDM_MODSOFTTX_SOFTSYMBOL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_BAUD +// +//***************************************************************************** +// Field: [15:0] RATEWORD +// +// Rate word (bits [20:5]). The 5 LSBs of the 21-bit rate word are defined in +// BAUDPRE.EXTRATEWORD register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BAUD_RATEWORD_W 16U +#define LRFDMDM_BAUD_RATEWORD_M 0x0000FFFFU +#define LRFDMDM_BAUD_RATEWORD_S 0U +#define LRFDMDM_BAUD_RATEWORD_ALLONES 0x0000FFFFU +#define LRFDMDM_BAUD_RATEWORD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_BAUDPRE +// +//***************************************************************************** +// Field: [15:13] ALIGNVALUE +// +// Align value for timebase after sync +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BAUDPRE_ALIGNVALUE_W 3U +#define LRFDMDM_BAUDPRE_ALIGNVALUE_M 0x0000E000U +#define LRFDMDM_BAUDPRE_ALIGNVALUE_S 13U +#define LRFDMDM_BAUDPRE_ALIGNVALUE_ALLONES 0x0000E000U +#define LRFDMDM_BAUDPRE_ALIGNVALUE_ALLZEROS 0x00000000U + +// Field: [12:8] EXTRATEWORD +// +// Extended Rate Word (bits [4:0]). These are the 5 LSBs extending the 16 MSBs +// configured in BAUD.RATEWORD to form a 21 bit rate word. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BAUDPRE_EXTRATEWORD_W 5U +#define LRFDMDM_BAUDPRE_EXTRATEWORD_M 0x00001F00U +#define LRFDMDM_BAUDPRE_EXTRATEWORD_S 8U +#define LRFDMDM_BAUDPRE_EXTRATEWORD_ALLONES 0x00001F00U +#define LRFDMDM_BAUDPRE_EXTRATEWORD_ALLZEROS 0x00000000U + +// Field: [7:0] PRESCALER +// +// Prescaler value, range 1 to 255 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BAUDPRE_PRESCALER_W 8U +#define LRFDMDM_BAUDPRE_PRESCALER_M 0x000000FFU +#define LRFDMDM_BAUDPRE_PRESCALER_S 0U +#define LRFDMDM_BAUDPRE_PRESCALER_ALLONES 0x000000FFU +#define LRFDMDM_BAUDPRE_PRESCALER_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODMAIN +// +//***************************************************************************** +// Field: [3:2] FECSELECT +// +// Forward Error Correction Selection. Used for some signal-wiring in modulator +// and demodulator. +// ENUMs: +// BLR Bluetooth LE coded long range compatible FEC +// RESERVED Reserved +// IEEE15_4 IEEE 802.15.4 +// NOSEL No FEC encoding selected +#define LRFDMDM_MODMAIN_FECSELECT_W 2U +#define LRFDMDM_MODMAIN_FECSELECT_M 0x0000000CU +#define LRFDMDM_MODMAIN_FECSELECT_S 2U +#define LRFDMDM_MODMAIN_FECSELECT_BLR 0x0000000CU +#define LRFDMDM_MODMAIN_FECSELECT_RESERVED 0x00000008U +#define LRFDMDM_MODMAIN_FECSELECT_IEEE15_4 0x00000004U +#define LRFDMDM_MODMAIN_FECSELECT_NOSEL 0x00000000U + +// Field: [1:0] MODLEVELS +// +// Number of modulation levels +// ENUMs: +// LVL8 8 levels +// LVL4 4 levels +// LVL2 2 levels +#define LRFDMDM_MODMAIN_MODLEVELS_W 2U +#define LRFDMDM_MODMAIN_MODLEVELS_M 0x00000003U +#define LRFDMDM_MODMAIN_MODLEVELS_S 0U +#define LRFDMDM_MODMAIN_MODLEVELS_LVL8 0x00000002U +#define LRFDMDM_MODMAIN_MODLEVELS_LVL4 0x00000001U +#define LRFDMDM_MODMAIN_MODLEVELS_LVL2 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMISC0 +// +//***************************************************************************** +// Field: [9:0] CMIXN +// +// Signed factor of mixer phasor, Fmix=n*Fs/1024 , where n in range [-512, 511] +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMISC0_CMIXN_W 10U +#define LRFDMDM_DEMMISC0_CMIXN_M 0x000003FFU +#define LRFDMDM_DEMMISC0_CMIXN_S 0U +#define LRFDMDM_DEMMISC0_CMIXN_ALLONES 0x000003FFU +#define LRFDMDM_DEMMISC0_CMIXN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMISC1 +// +//***************************************************************************** +// Field: [12:8] CDCTGAINMA +// +// Gives the gain mantissa of the CDC P/Q tracker +// ENUMs: +// ALLONES Maximum gain mantissa. +// ALLZEROS When CDCTGAINMA is set to zero, the tracker loop +// is disabled. +#define LRFDMDM_DEMMISC1_CDCTGAINMA_W 5U +#define LRFDMDM_DEMMISC1_CDCTGAINMA_M 0x00001F00U +#define LRFDMDM_DEMMISC1_CDCTGAINMA_S 8U +#define LRFDMDM_DEMMISC1_CDCTGAINMA_ALLONES 0x00001F00U +#define LRFDMDM_DEMMISC1_CDCTGAINMA_ALLZEROS 0x00000000U + +// Field: [7:5] CDCTGAINEX +// +// Gives the gain exponent of the CDC P/Q tracker +// ENUMs: +// ALLONES When CDCTGAINEX is set to all zeroes, the +// CDCGAINMA multiplier is 512 +// ALLZEROS When CDCTGAINEX is set to all zeroes, the +// CDCGAINMA multiplier is 4 +#define LRFDMDM_DEMMISC1_CDCTGAINEX_W 3U +#define LRFDMDM_DEMMISC1_CDCTGAINEX_M 0x000000E0U +#define LRFDMDM_DEMMISC1_CDCTGAINEX_S 5U +#define LRFDMDM_DEMMISC1_CDCTGAINEX_ALLONES 0x000000E0U +#define LRFDMDM_DEMMISC1_CDCTGAINEX_ALLZEROS 0x00000000U + +// Field: [4] CDCCOLRST +// +// Collision restart for CDC FIFO +// ENUMs: +// EN Enable collision detect and restart feature +// DIS Do not enable collision detect and restart feature +#define LRFDMDM_DEMMISC1_CDCCOLRST 0x00000010U +#define LRFDMDM_DEMMISC1_CDCCOLRST_M 0x00000010U +#define LRFDMDM_DEMMISC1_CDCCOLRST_S 4U +#define LRFDMDM_DEMMISC1_CDCCOLRST_EN 0x00000010U +#define LRFDMDM_DEMMISC1_CDCCOLRST_DIS 0x00000000U + +// Field: [3:2] MGE1SRCSEL +// +// Source select magnitude estimator 1 +// ENUMs: +// CHFI Output of CHFI +// FEXB1 Output of the FEXB, as selected by +// DEMFEXB0.OUT2SRCSEL register +// FIDC Output of the FIDC (x4 samples) +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_W 2U +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_M 0x0000000CU +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_S 2U +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_CHFI 0x00000008U +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_FEXB1 0x00000004U +#define LRFDMDM_DEMMISC1_MGE1SRCSEL_FIDC 0x00000000U + +// Field: [1:0] CHFIBW +// +// Select bandwidth (cut-off frequency) of demodulator channel filter +// ENUMs: +// BW0_29 0.29 * Fs. Using FIR filter with taps [2 3 1 -8 +// -18 -14 17 72 126 149 126 72 17 -14 -18 -8 1 3 +// 2]. +// BW0_41667 0.41667 * Fs. Using FIR filter with taps [-1 -4 2 +// 12 4 -25 -31 38 154 213 154 38 -31 -25 4 12 2 +// -4 -1]. +// BW0_3333 0.33333 * Fs. Using FIR filter with taps [0 4 6 0 +// -16 -25 0 65 138 170 138 65 0 -25 -16 0 6 4 0]. +// BW0_5 0.5 * Fs. Using FIR filter with taps [3 0 -9 0 20 +// 0 -46 0 160 256 160 0 -46 0 20 0 -9 0 3]. +#define LRFDMDM_DEMMISC1_CHFIBW_W 2U +#define LRFDMDM_DEMMISC1_CHFIBW_M 0x00000003U +#define LRFDMDM_DEMMISC1_CHFIBW_S 0U +#define LRFDMDM_DEMMISC1_CHFIBW_BW0_29 0x00000003U +#define LRFDMDM_DEMMISC1_CHFIBW_BW0_41667 0x00000002U +#define LRFDMDM_DEMMISC1_CHFIBW_BW0_3333 0x00000001U +#define LRFDMDM_DEMMISC1_CHFIBW_BW0_5 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMISC2 +// +//***************************************************************************** +// Field: [14] MLSERUN +// +// Enable maximum likelihood sequence estimation (MLSE) desicions +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_DEMMISC2_MLSERUN 0x00004000U +#define LRFDMDM_DEMMISC2_MLSERUN_M 0x00004000U +#define LRFDMDM_DEMMISC2_MLSERUN_S 14U +#define LRFDMDM_DEMMISC2_MLSERUN_EN 0x00004000U +#define LRFDMDM_DEMMISC2_MLSERUN_DIS 0x00000000U + +// Field: [13:12] MAFCGAIN +// +// Set gain in MAFC. Multiplies symbols with 2^N before symbol recovery stage +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMISC2_MAFCGAIN_W 2U +#define LRFDMDM_DEMMISC2_MAFCGAIN_M 0x00003000U +#define LRFDMDM_DEMMISC2_MAFCGAIN_S 12U +#define LRFDMDM_DEMMISC2_MAFCGAIN_ALLONES 0x00003000U +#define LRFDMDM_DEMMISC2_MAFCGAIN_ALLZEROS 0x00000000U + +// Field: [11] STIMBYPASS +// +// Use to bypass STIM estimator +// ENUMs: +// EN Perform estimation only (no timing correction) +// DIS Perform both estimation and correct timing +#define LRFDMDM_DEMMISC2_STIMBYPASS 0x00000800U +#define LRFDMDM_DEMMISC2_STIMBYPASS_M 0x00000800U +#define LRFDMDM_DEMMISC2_STIMBYPASS_S 11U +#define LRFDMDM_DEMMISC2_STIMBYPASS_EN 0x00000800U +#define LRFDMDM_DEMMISC2_STIMBYPASS_DIS 0x00000000U + +// Field: [10] STIMESTONLY +// +// Only perform symbol timing error estimation in STIM, without doing timing +// correction +// ENUMs: +// EN Perform estimation only (no timing correction) +// DIS Perform both estimation and correct timing +#define LRFDMDM_DEMMISC2_STIMESTONLY 0x00000400U +#define LRFDMDM_DEMMISC2_STIMESTONLY_M 0x00000400U +#define LRFDMDM_DEMMISC2_STIMESTONLY_S 10U +#define LRFDMDM_DEMMISC2_STIMESTONLY_EN 0x00000400U +#define LRFDMDM_DEMMISC2_STIMESTONLY_DIS 0x00000000U + +// Field: [9:7] STIMTEAPERIOD +// +// Symbol timing error accumulator period (4 to 128 symbols) in STIM +// ENUMs: +// SYM128 128 symbols +// SYM64 64 symbols +// SYM32 32 symbols +// SYM16 16 symbols +// SYM8 8 symbols +// SYM4 4 symbols +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_W 3U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_M 0x00000380U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_S 7U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM128 0x00000280U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM64 0x00000200U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM32 0x00000180U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM16 0x00000100U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM8 0x00000080U +#define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM4 0x00000000U + +// Field: [6:4] STIMTEAGAIN +// +// Symbol timing error accumulator gain in STIM +// ENUMs: +// DIV4 Gain is 1/4 +// DIV8 Gain is 1/8 +// DIV16 Gain is 1/16 +// DIV32 Gain is 1/32 +// DIV64 Gain is 1/64 +// DIV128 Gain is 1/128 +// DIV256 Gain is 1/256 +// DIV512 Gain is 1/512 +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_W 3U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_M 0x00000070U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_S 4U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV4 0x00000070U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV8 0x00000060U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV16 0x00000050U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV32 0x00000040U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV64 0x00000030U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV128 0x00000020U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV256 0x00000010U +#define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV512 0x00000000U + +// Field: [3] PDIFLINPREDEN +// +// Enable linear predictor in PDIF at CORDIC output +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_DEMMISC2_PDIFLINPREDEN 0x00000008U +#define LRFDMDM_DEMMISC2_PDIFLINPREDEN_M 0x00000008U +#define LRFDMDM_DEMMISC2_PDIFLINPREDEN_S 3U +#define LRFDMDM_DEMMISC2_PDIFLINPREDEN_ON 0x00000008U +#define LRFDMDM_DEMMISC2_PDIFLINPREDEN_OFF 0x00000000U + +// Field: [2] PDIFDESPECK +// +// Enable despeckler in PDIF at CORDIC output +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_DEMMISC2_PDIFDESPECK 0x00000004U +#define LRFDMDM_DEMMISC2_PDIFDESPECK_M 0x00000004U +#define LRFDMDM_DEMMISC2_PDIFDESPECK_S 2U +#define LRFDMDM_DEMMISC2_PDIFDESPECK_EN 0x00000004U +#define LRFDMDM_DEMMISC2_PDIFDESPECK_DIS 0x00000000U + +// Field: [1] PDIFIQCONJEN +// +// Conjugate the complex I/Q signal in PDIF +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_DEMMISC2_PDIFIQCONJEN 0x00000002U +#define LRFDMDM_DEMMISC2_PDIFIQCONJEN_M 0x00000002U +#define LRFDMDM_DEMMISC2_PDIFIQCONJEN_S 1U +#define LRFDMDM_DEMMISC2_PDIFIQCONJEN_ON 0x00000002U +#define LRFDMDM_DEMMISC2_PDIFIQCONJEN_OFF 0x00000000U + +// Field: [0] PDIFLIMITRANGE +// +// Limit range on maximal PDIF output, i.e. instantaneous frequency sample +// ENUMs: +// EN Limit the range to 7-bit, i.e. +/- 64 +// DIS Allow full 8-bit range, i.e. +/- 128 +#define LRFDMDM_DEMMISC2_PDIFLIMITRANGE 0x00000001U +#define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_M 0x00000001U +#define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_S 0U +#define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_EN 0x00000001U +#define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMISC3 +// +//***************************************************************************** +// Field: [14:13] BDE2DVGA +// +// DVGA settings for BDE2. The DVGA control for BDE2 is shared with the RFE in +// its LRFDRFE:GAINCTRL.BDE2DVGA register. +// Software should determine who uses them. Please note that if both processors +// attempt to control it, the resulting setting will be the two settings ORed +// together. +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDMDM_DEMMISC3_BDE2DVGA_W 2U +#define LRFDMDM_DEMMISC3_BDE2DVGA_M 0x00006000U +#define LRFDMDM_DEMMISC3_BDE2DVGA_S 13U +#define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN8 0x00006000U +#define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN4 0x00004000U +#define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN2 0x00002000U +#define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN1 0x00000000U + +// Field: [12] BDE1FILTMODE +// +// BDE1 Filter only mode. When enabled, BDE1 lp filters in signal path, but no +// decimation occurs. +// ENUMs: +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM_DEMMISC3_BDE1FILTMODE 0x00001000U +#define LRFDMDM_DEMMISC3_BDE1FILTMODE_M 0x00001000U +#define LRFDMDM_DEMMISC3_BDE1FILTMODE_S 12U +#define LRFDMDM_DEMMISC3_BDE1FILTMODE_DIV2 0x00001000U +#define LRFDMDM_DEMMISC3_BDE1FILTMODE_DIV1 0x00000000U + +// Field: [11:10] LQIPERIOD +// +// LQI measurement period +// ENUMs: +// SYM1024 1024 symbols +// SYM256 256 symbols +// SYM64 64 symbols +// SYM16 16 symbols +#define LRFDMDM_DEMMISC3_LQIPERIOD_W 2U +#define LRFDMDM_DEMMISC3_LQIPERIOD_M 0x00000C00U +#define LRFDMDM_DEMMISC3_LQIPERIOD_S 10U +#define LRFDMDM_DEMMISC3_LQIPERIOD_SYM1024 0x00000C00U +#define LRFDMDM_DEMMISC3_LQIPERIOD_SYM256 0x00000800U +#define LRFDMDM_DEMMISC3_LQIPERIOD_SYM64 0x00000400U +#define LRFDMDM_DEMMISC3_LQIPERIOD_SYM16 0x00000000U + +// Field: [9:8] BDE1DVGA +// +// DVGA settings for BDE1. The DVGA control for BDE1 is shared with the RFE in +// its LRFDRFE:GAINCTRL.BDE1DVGA register. +// Software should determine who uses them. Please note that if both processors +// attempt to control it, the resulting setting will be the two settings ORed +// together. +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDMDM_DEMMISC3_BDE1DVGA_W 2U +#define LRFDMDM_DEMMISC3_BDE1DVGA_M 0x00000300U +#define LRFDMDM_DEMMISC3_BDE1DVGA_S 8U +#define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN8 0x00000300U +#define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN4 0x00000200U +#define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN2 0x00000100U +#define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN1 0x00000000U + +// Field: [7] BDE1NUMSTAGES +// +// BDE1 decimation filter setting +// ENUMs: +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM_DEMMISC3_BDE1NUMSTAGES 0x00000080U +#define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_M 0x00000080U +#define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_S 7U +#define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_DIV2 0x00000080U +#define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_DIV1 0x00000000U + +// Field: [6:5] PDIFDECIM +// +// Additional decimation in PDIF +// ENUMs: +// DIV4 Decimate by 4 +// DIV2 Decimate by 2 +// DIV1 No decimation +#define LRFDMDM_DEMMISC3_PDIFDECIM_W 2U +#define LRFDMDM_DEMMISC3_PDIFDECIM_M 0x00000060U +#define LRFDMDM_DEMMISC3_PDIFDECIM_S 5U +#define LRFDMDM_DEMMISC3_PDIFDECIM_DIV4 0x00000040U +#define LRFDMDM_DEMMISC3_PDIFDECIM_DIV2 0x00000020U +#define LRFDMDM_DEMMISC3_PDIFDECIM_DIV1 0x00000000U + +// Field: [4:0] BDE2DECRATIO +// +// BDE2 decimation filter setting +// ENUMs: +// DIV8 Decimate by 8 +// DIV4 Decimate by 4 +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_W 5U +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_M 0x0000001FU +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_S 0U +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV8 0x00000003U +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV4 0x00000002U +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV2 0x00000001U +#define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMIQMC0 +// +//***************************************************************************** +// Field: [15:8] GAINFACTOR +// +// Gain factor to compensate for unequal gains between the I and Q signal paths +// in the analog RF front-end. +// The compensation is done by scaling the I path amplitude (no compensation of +// Q path). +// The gain factor is given as an unsigned number in the range [0,255] +// corresponding to gain factor range [0,2], +// where value 128 gives gain factor 1.0 (no gain). Any gain compensation is +// applied in a stage after the phase compensation. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMIQMC0_GAINFACTOR_W 8U +#define LRFDMDM_DEMIQMC0_GAINFACTOR_M 0x0000FF00U +#define LRFDMDM_DEMIQMC0_GAINFACTOR_S 8U +#define LRFDMDM_DEMIQMC0_GAINFACTOR_ALLONES 0x0000FF00U +#define LRFDMDM_DEMIQMC0_GAINFACTOR_ALLZEROS 0x00000000U + +// Field: [7:0] PHASEFACTOR +// +// Phase factor to compensate for unorthogonal I and Q signals. +// The phase factor is given as a signed number in the range [-128,127] +// corresponding to phase factor range [-0.5, 0.496], +// where the phase factor can be calculated as phase_factor = tan(phase_error). +// This gives an available phase error compensation range of [-26.6, 26.4] +// degrees. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMIQMC0_PHASEFACTOR_W 8U +#define LRFDMDM_DEMIQMC0_PHASEFACTOR_M 0x000000FFU +#define LRFDMDM_DEMIQMC0_PHASEFACTOR_S 0U +#define LRFDMDM_DEMIQMC0_PHASEFACTOR_ALLONES 0x000000FFU +#define LRFDMDM_DEMIQMC0_PHASEFACTOR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMDSBU +// +//***************************************************************************** +// Field: [15:8] DSBUAVGLENGTH +// +// Length for moving average of the newest DSBU samples. +// The buffer can hold up to 256 samples. Length of 255 is maximum. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_W 8U +#define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_M 0x0000FF00U +#define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_S 8U +#define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_ALLONES 0x0000FF00U +#define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_ALLZEROS 0x00000000U + +// Field: [7:0] DSBUDELAY +// +// Output delay from sample buffer, as offset between write and read pointers. +// The buffer can hold up to 256 samples. Delay of 0 means maximum. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMDSBU_DSBUDELAY_W 8U +#define LRFDMDM_DEMDSBU_DSBUDELAY_M 0x000000FFU +#define LRFDMDM_DEMDSBU_DSBUDELAY_S 0U +#define LRFDMDM_DEMDSBU_DSBUDELAY_ALLONES 0x000000FFU +#define LRFDMDM_DEMDSBU_DSBUDELAY_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMCODC0 +// +//***************************************************************************** +// Field: [11] ESTSEL +// +// Select which estimator to show as readable output +// ENUMs: +// IIR Read back latest IIR estimate +// ACC Read back latest accumulator estimate +#define LRFDMDM_DEMCODC0_ESTSEL 0x00000800U +#define LRFDMDM_DEMCODC0_ESTSEL_M 0x00000800U +#define LRFDMDM_DEMCODC0_ESTSEL_S 11U +#define LRFDMDM_DEMCODC0_ESTSEL_IIR 0x00000800U +#define LRFDMDM_DEMCODC0_ESTSEL_ACC 0x00000000U + +// Field: [10:9] COMPSEL +// +// Select estimator to use for coarse DC offset compensation +// ENUMs: +// IIR Compensate with latest IIR estimate +// ACC Compensate with latest accumulator estimate +// MANUAL Use manually programmable values from DEMCODC1 +// registers +#define LRFDMDM_DEMCODC0_COMPSEL_W 2U +#define LRFDMDM_DEMCODC0_COMPSEL_M 0x00000600U +#define LRFDMDM_DEMCODC0_COMPSEL_S 9U +#define LRFDMDM_DEMCODC0_COMPSEL_IIR 0x00000600U +#define LRFDMDM_DEMCODC0_COMPSEL_ACC 0x00000400U +#define LRFDMDM_DEMCODC0_COMPSEL_MANUAL 0x00000000U + +// Field: [8] IIRUSEINITIAL +// +// When enabled, a configurable value is loaded to initialize IIR filter when +// CODC estimator is re-initialized. +// ENUMs: +// EN Use the manual compensation values in DEMCODC1 for +// initialization +// DIS Initialize IIR filter with value zero +#define LRFDMDM_DEMCODC0_IIRUSEINITIAL 0x00000100U +#define LRFDMDM_DEMCODC0_IIRUSEINITIAL_M 0x00000100U +#define LRFDMDM_DEMCODC0_IIRUSEINITIAL_S 8U +#define LRFDMDM_DEMCODC0_IIRUSEINITIAL_EN 0x00000100U +#define LRFDMDM_DEMCODC0_IIRUSEINITIAL_DIS 0x00000000U + +// Field: [7:5] IIRGAIN +// +// Adjust first-order IIR filter adaptation which controls filter bandwidth. +// ENUMs: +// DIV1024 Use 1/1024 IIR adaptation +// DIV512 Use 1/512 IIR adaptation +// DIV256 Use 1/256 IIR adaptation +// DIV128 Use 1/128 IIR adaptation +// DIV64 Use 1/64 IIR adaptation +// DIV32 Use 1/32 IIR adaptation +// DIV16 Use 1/16 IIR adaptation +// OFF Filter disabled +#define LRFDMDM_DEMCODC0_IIRGAIN_W 3U +#define LRFDMDM_DEMCODC0_IIRGAIN_M 0x000000E0U +#define LRFDMDM_DEMCODC0_IIRGAIN_S 5U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV1024 0x000000E0U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV512 0x000000C0U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV256 0x000000A0U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV128 0x00000080U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV64 0x00000060U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV32 0x00000040U +#define LRFDMDM_DEMCODC0_IIRGAIN_DIV16 0x00000020U +#define LRFDMDM_DEMCODC0_IIRGAIN_OFF 0x00000000U + +// Field: [4] IIREN +// +// Enable first-order IIR filter inside CODC +// ENUMs: +// ON Enable IIR estimator +// OFF Disable IIR estimator +#define LRFDMDM_DEMCODC0_IIREN 0x00000010U +#define LRFDMDM_DEMCODC0_IIREN_M 0x00000010U +#define LRFDMDM_DEMCODC0_IIREN_S 4U +#define LRFDMDM_DEMCODC0_IIREN_ON 0x00000010U +#define LRFDMDM_DEMCODC0_IIREN_OFF 0x00000000U + +// Field: [3] ACCMODE +// +// Accumulator estimator mode +// ENUMs: +// CONT Generate new DC estimates continuously +// SINGLE Generate a single DC estimate only, then stop +#define LRFDMDM_DEMCODC0_ACCMODE 0x00000008U +#define LRFDMDM_DEMCODC0_ACCMODE_M 0x00000008U +#define LRFDMDM_DEMCODC0_ACCMODE_S 3U +#define LRFDMDM_DEMCODC0_ACCMODE_CONT 0x00000008U +#define LRFDMDM_DEMCODC0_ACCMODE_SINGLE 0x00000000U + +// Field: [2:1] ACCPERIOD +// +// Integration period for accumulator estimator +// ENUMs: +// SMPL512 512 samples +// SMPL128 128 samples +// SMPL32 32 samples +// SMPL8 8 samples +#define LRFDMDM_DEMCODC0_ACCPERIOD_W 2U +#define LRFDMDM_DEMCODC0_ACCPERIOD_M 0x00000006U +#define LRFDMDM_DEMCODC0_ACCPERIOD_S 1U +#define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL512 0x00000006U +#define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL128 0x00000004U +#define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL32 0x00000002U +#define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL8 0x00000000U + +// Field: [0] ACCEN +// +// Enable accumulator based estimator inside CODC +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM_DEMCODC0_ACCEN 0x00000001U +#define LRFDMDM_DEMCODC0_ACCEN_M 0x00000001U +#define LRFDMDM_DEMCODC0_ACCEN_S 0U +#define LRFDMDM_DEMCODC0_ACCEN_ON 0x00000001U +#define LRFDMDM_DEMCODC0_ACCEN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFIDC0 +// +//***************************************************************************** +// Field: [5:4] COMPSEL +// +// Select estimator to use for fine DC offset compensation +// ENUMs: +// ACC Compensate with latest accumulator estimate +// MANUAL Use manually programmable values from DEMFIDC1 +// registers +#define LRFDMDM_DEMFIDC0_COMPSEL_W 2U +#define LRFDMDM_DEMFIDC0_COMPSEL_M 0x00000030U +#define LRFDMDM_DEMFIDC0_COMPSEL_S 4U +#define LRFDMDM_DEMFIDC0_COMPSEL_ACC 0x00000020U +#define LRFDMDM_DEMFIDC0_COMPSEL_MANUAL 0x00000000U + +// Field: [3:2] ACCPERIOD +// +// Integration period for accumulator estimator +// ENUMs: +// SMPL512 512 samples +// SMPL128 128 samples +// SMPL32 32 samples +// SMPL8 8 samples +#define LRFDMDM_DEMFIDC0_ACCPERIOD_W 2U +#define LRFDMDM_DEMFIDC0_ACCPERIOD_M 0x0000000CU +#define LRFDMDM_DEMFIDC0_ACCPERIOD_S 2U +#define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL512 0x0000000CU +#define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 0x00000008U +#define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 0x00000004U +#define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL8 0x00000000U + +// Field: [1] ACCMODE +// +// Accumulator estimator mode +// ENUMs: +// CONT Generate new DC estimates continuously +// SINGLE Generate a single DC estimate only, then stop +#define LRFDMDM_DEMFIDC0_ACCMODE 0x00000002U +#define LRFDMDM_DEMFIDC0_ACCMODE_M 0x00000002U +#define LRFDMDM_DEMFIDC0_ACCMODE_S 1U +#define LRFDMDM_DEMFIDC0_ACCMODE_CONT 0x00000002U +#define LRFDMDM_DEMFIDC0_ACCMODE_SINGLE 0x00000000U + +// Field: [0] ACCEN +// +// Enable accumulator based estimator inside FIDC +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM_DEMFIDC0_ACCEN 0x00000001U +#define LRFDMDM_DEMFIDC0_ACCEN_M 0x00000001U +#define LRFDMDM_DEMFIDC0_ACCEN_S 0U +#define LRFDMDM_DEMFIDC0_ACCEN_ON 0x00000001U +#define LRFDMDM_DEMFIDC0_ACCEN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFEXB0 +// +//***************************************************************************** +// Field: [13] OUT2PASSTHROUGH +// +// Front-end crossbar output #2 is direct passthrough of the crossbar input +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH 0x00002000U +#define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_M 0x00002000U +#define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_S 13U +#define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_ONE 0x00002000U +#define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_ZERO 0x00000000U + +// Field: [12:11] OUT2SRCSEL +// +// Source select for XBAR output #2 (towards magnitude estimation engine MGE0) +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is coarse DC remover (CODC) +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_M 0x00001800U +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_S 11U +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_BDE1 0x00001000U +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_CMIX 0x00000800U +#define LRFDMDM_DEMFEXB0_OUT2SRCSEL_CODC 0x00000000U + +// Field: [10] OUT1PASSTHROUGH +// +// Front-end crossbar output #1 is direct passthrough of the crossbar input +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH 0x00000400U +#define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_M 0x00000400U +#define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_S 10U +#define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_ONE 0x00000400U +#define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_ZERO 0x00000000U + +// Field: [9:8] OUT1SRCSEL +// +// Source select for XBAR output #1 (main output, towards BDE2 and rest of +// demodulator) +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is coarse DC remover (CODC) +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_M 0x00000300U +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_S 8U +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_BDE1 0x00000200U +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_CMIX 0x00000100U +#define LRFDMDM_DEMFEXB0_OUT1SRCSEL_CODC 0x00000000U + +// Field: [7:6] B4SRCSEL +// +// Not used +// ENUMs: +// ONES Source is complex N*Fs/1024 mixer (ONES) +// ZEROS Source is complex N*Fs/1024 mixer (ZEROS) +#define LRFDMDM_DEMFEXB0_B4SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_B4SRCSEL_M 0x000000C0U +#define LRFDMDM_DEMFEXB0_B4SRCSEL_S 6U +#define LRFDMDM_DEMFEXB0_B4SRCSEL_ONES 0x000000C0U +#define LRFDMDM_DEMFEXB0_B4SRCSEL_ZEROS 0x00000000U + +// Field: [5:4] B3SRCSEL +// +// Source select for BDE1 (XBAR block #3) +// ENUMs: +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is complex N*Fs/1024 mixer (CMIX) +// INPUT Source is crossbar main input +#define LRFDMDM_DEMFEXB0_B3SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_B3SRCSEL_M 0x00000030U +#define LRFDMDM_DEMFEXB0_B3SRCSEL_S 4U +#define LRFDMDM_DEMFEXB0_B3SRCSEL_CMIX 0x00000020U +#define LRFDMDM_DEMFEXB0_B3SRCSEL_CODC 0x00000010U +#define LRFDMDM_DEMFEXB0_B3SRCSEL_INPUT 0x00000000U + +// Field: [3:2] B2SRCSEL +// +// Source select for CMIX (XBAR block #2) +// ENUMs: +// BDE1 Source is coarse DC remover (CODC) +// CODC Source is coarse DC remover (CODC) +// INPUT Source is crossbar main input +#define LRFDMDM_DEMFEXB0_B2SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_B2SRCSEL_M 0x0000000CU +#define LRFDMDM_DEMFEXB0_B2SRCSEL_S 2U +#define LRFDMDM_DEMFEXB0_B2SRCSEL_BDE1 0x00000008U +#define LRFDMDM_DEMFEXB0_B2SRCSEL_CODC 0x00000004U +#define LRFDMDM_DEMFEXB0_B2SRCSEL_INPUT 0x00000000U + +// Field: [1:0] B1SRCSEL +// +// Source select for CODC (XBAR block #1) +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// INPUT Source is crossbar main input +#define LRFDMDM_DEMFEXB0_B1SRCSEL_W 2U +#define LRFDMDM_DEMFEXB0_B1SRCSEL_M 0x00000003U +#define LRFDMDM_DEMFEXB0_B1SRCSEL_S 0U +#define LRFDMDM_DEMFEXB0_B1SRCSEL_BDE1 0x00000002U +#define LRFDMDM_DEMFEXB0_B1SRCSEL_CMIX 0x00000001U +#define LRFDMDM_DEMFEXB0_B1SRCSEL_INPUT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMDSXB0 +// +//***************************************************************************** +// Field: [5] OUT2PASSTHROUGH +// +// Crossbar output #2 is direct passthrough of the crossbar input +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH 0x00000020U +#define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_M 0x00000020U +#define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_S 5U +#define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_ONE 0x00000020U +#define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_ZERO 0x00000000U + +// Field: [4] OUT1PASSTHROUGH +// +// Crossbar output #1 is direct passthrough of the crossbar input +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH 0x00000010U +#define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_M 0x00000010U +#define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_S 4U +#define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_ONE 0x00000010U +#define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_ZERO 0x00000000U + +// Field: [3] OUTSRCSEL2 +// +// Source select XBAR output, branch 1 (baud branch) +// ENUMs: +// MAFI Source is matched filter (MAFI) +// FIFE Source is fine frequency offset estimator (FIFE) +#define LRFDMDM_DEMDSXB0_OUTSRCSEL2 0x00000008U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL2_M 0x00000008U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL2_S 3U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL2_MAFI 0x00000008U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL2_FIFE 0x00000000U + +// Field: [2] OUTSRCSEL1 +// +// Source select for XBAR output, branch 2 (flushed branch) +// ENUMs: +// MAFI Source is matched filter (MAFI) +// FIFE Source is fine frequency offset estimator (FIFE) +#define LRFDMDM_DEMDSXB0_OUTSRCSEL1 0x00000004U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL1_M 0x00000004U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL1_S 2U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL1_MAFI 0x00000004U +#define LRFDMDM_DEMDSXB0_OUTSRCSEL1_FIFE 0x00000000U + +// Field: [1] B2SRCSEL +// +// Source select for MAFI (XBAR block #2) +// ENUMs: +// FIFE Source is fine frequency offset estimator (FIFE) +// INPUT Source is crossbar main input +#define LRFDMDM_DEMDSXB0_B2SRCSEL 0x00000002U +#define LRFDMDM_DEMDSXB0_B2SRCSEL_M 0x00000002U +#define LRFDMDM_DEMDSXB0_B2SRCSEL_S 1U +#define LRFDMDM_DEMDSXB0_B2SRCSEL_FIFE 0x00000002U +#define LRFDMDM_DEMDSXB0_B2SRCSEL_INPUT 0x00000000U + +// Field: [0] B1SRCSEL +// +// Source select for FIFE (XBAR block #1) +// ENUMs: +// MAFI Source is matched filter (MAFI) +// INPUT Source is crossbar main input +#define LRFDMDM_DEMDSXB0_B1SRCSEL 0x00000001U +#define LRFDMDM_DEMDSXB0_B1SRCSEL_M 0x00000001U +#define LRFDMDM_DEMDSXB0_B1SRCSEL_S 0U +#define LRFDMDM_DEMDSXB0_B1SRCSEL_MAFI 0x00000001U +#define LRFDMDM_DEMDSXB0_B1SRCSEL_INPUT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFIFE0 +// +//***************************************************************************** +// Field: [11] FINEFOESEL +// +// Select which estimator to show as readable output +// ENUMs: +// ACC Latest accumulator estimate +// IIR Latest IIR estimate +#define LRFDMDM_DEMFIFE0_FINEFOESEL 0x00000800U +#define LRFDMDM_DEMFIFE0_FINEFOESEL_M 0x00000800U +#define LRFDMDM_DEMFIFE0_FINEFOESEL_S 11U +#define LRFDMDM_DEMFIFE0_FINEFOESEL_ACC 0x00000800U +#define LRFDMDM_DEMFIFE0_FINEFOESEL_IIR 0x00000000U + +// Field: [10:9] FOCFFSEL +// +// Select which estimate source to be used in feed-forward compensation point +// ENUMs: +// MANUAL Use programmable manual value from register bank. +// (Note: an input register is not implemented, so +// the manual compensation value is tied to '0') +// ACC Compensate with latest accumulator estimate +// IIR Compensate with latest IIR estimate +#define LRFDMDM_DEMFIFE0_FOCFFSEL_W 2U +#define LRFDMDM_DEMFIFE0_FOCFFSEL_M 0x00000600U +#define LRFDMDM_DEMFIFE0_FOCFFSEL_S 9U +#define LRFDMDM_DEMFIFE0_FOCFFSEL_MANUAL 0x00000400U +#define LRFDMDM_DEMFIFE0_FOCFFSEL_ACC 0x00000200U +#define LRFDMDM_DEMFIFE0_FOCFFSEL_IIR 0x00000000U + +// Field: [8] ACCCNTMODE +// +// Accumulator estimator mode +// ENUMs: +// CONT Generate new frequency offset estimates +// continuously +// SINGLE Generate a single frequency offset estimate only, +// then stop +#define LRFDMDM_DEMFIFE0_ACCCNTMODE 0x00000100U +#define LRFDMDM_DEMFIFE0_ACCCNTMODE_M 0x00000100U +#define LRFDMDM_DEMFIFE0_ACCCNTMODE_S 8U +#define LRFDMDM_DEMFIFE0_ACCCNTMODE_CONT 0x00000100U +#define LRFDMDM_DEMFIFE0_ACCCNTMODE_SINGLE 0x00000000U + +// Field: [7:6] ACCPERIOD +// +// Integration period for accumulator +// ENUMs: +// PER512 512 samples +// PER256 256 samples +// PER128 128 samples +// PER64 64 samples +#define LRFDMDM_DEMFIFE0_ACCPERIOD_W 2U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_M 0x000000C0U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_S 6U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_PER512 0x000000C0U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_PER256 0x00000080U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_PER128 0x00000040U +#define LRFDMDM_DEMFIFE0_ACCPERIOD_PER64 0x00000000U + +// Field: [5] ACCEN +// +// Enable accumulator based frequency offset estimator inside FIFE +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM_DEMFIFE0_ACCEN 0x00000020U +#define LRFDMDM_DEMFIFE0_ACCEN_M 0x00000020U +#define LRFDMDM_DEMFIFE0_ACCEN_S 5U +#define LRFDMDM_DEMFIFE0_ACCEN_ON 0x00000020U +#define LRFDMDM_DEMFIFE0_ACCEN_OFF 0x00000000U + +// Field: [4] IIRUSEINITIAL +// +// When enabled, a configurable value is loaded to initialize IIR filter when +// FIFE estimator is re-initialized. +// ENUMs: +// EN Use the manual compensation value in DEMFIFE1 for +// initialization +// DIS Initialize IIR filter with value zero +#define LRFDMDM_DEMFIFE0_IIRUSEINITIAL 0x00000010U +#define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_M 0x00000010U +#define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_S 4U +#define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_EN 0x00000010U +#define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_DIS 0x00000000U + +// Field: [3:1] IIRGAIN +// +// Adjust first-order IIR filter adaptation which controls filter bandwidth +// ENUMs: +// DIV1024 Use 1/1024 IIR adaptation +// DIV512 Use 1/512 IIR adaptation +// DIV256 Use 1/256 IIR adaptation +// DIV128 Use 1/128 IIR adaptation +// DIV64 Use 1/64 IIR adaptation +// DIV32 Use 1/32 IIR adaptation +// DIV16 Use 1/16 IIR adaptation +// OFF Filter disabled +#define LRFDMDM_DEMFIFE0_IIRGAIN_W 3U +#define LRFDMDM_DEMFIFE0_IIRGAIN_M 0x0000000EU +#define LRFDMDM_DEMFIFE0_IIRGAIN_S 1U +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV1024 0x0000000EU +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV512 0x0000000CU +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV256 0x0000000AU +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV128 0x00000008U +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV64 0x00000006U +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV32 0x00000004U +#define LRFDMDM_DEMFIFE0_IIRGAIN_DIV16 0x00000002U +#define LRFDMDM_DEMFIFE0_IIRGAIN_OFF 0x00000000U + +// Field: [0] IIREN +// +// Enable first-order IIR filter based freq offset estimator inside FIFE +// ENUMs: +// ON Enable IIR estimator +// OFF Disable IIR estimator +#define LRFDMDM_DEMFIFE0_IIREN 0x00000001U +#define LRFDMDM_DEMFIFE0_IIREN_M 0x00000001U +#define LRFDMDM_DEMFIFE0_IIREN_S 0U +#define LRFDMDM_DEMFIFE0_IIREN_ON 0x00000001U +#define LRFDMDM_DEMFIFE0_IIREN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMAFI0 +// +//***************************************************************************** +// Field: [15:8] C1C7 +// +// Filter coefficient c1 (and c7) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI0_C1C7_W 8U +#define LRFDMDM_DEMMAFI0_C1C7_M 0x0000FF00U +#define LRFDMDM_DEMMAFI0_C1C7_S 8U +#define LRFDMDM_DEMMAFI0_C1C7_ALLONES 0x0000FF00U +#define LRFDMDM_DEMMAFI0_C1C7_ALLZEROS 0x00000000U + +// Field: [7:0] C0C8 +// +// Filter coefficient c0 (and c8) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI0_C0C8_W 8U +#define LRFDMDM_DEMMAFI0_C0C8_M 0x000000FFU +#define LRFDMDM_DEMMAFI0_C0C8_S 0U +#define LRFDMDM_DEMMAFI0_C0C8_ALLONES 0x000000FFU +#define LRFDMDM_DEMMAFI0_C0C8_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMAFI1 +// +//***************************************************************************** +// Field: [15:8] C3C5 +// +// Filter coefficient c3 (and c5) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI1_C3C5_W 8U +#define LRFDMDM_DEMMAFI1_C3C5_M 0x0000FF00U +#define LRFDMDM_DEMMAFI1_C3C5_S 8U +#define LRFDMDM_DEMMAFI1_C3C5_ALLONES 0x0000FF00U +#define LRFDMDM_DEMMAFI1_C3C5_ALLZEROS 0x00000000U + +// Field: [7:0] C2C6 +// +// Filter coefficient c2 (and c6) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI1_C2C6_W 8U +#define LRFDMDM_DEMMAFI1_C2C6_M 0x000000FFU +#define LRFDMDM_DEMMAFI1_C2C6_S 0U +#define LRFDMDM_DEMMAFI1_C2C6_ALLONES 0x000000FFU +#define LRFDMDM_DEMMAFI1_C2C6_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMAFI2 +// +//***************************************************************************** +// Field: [8:0] C4 +// +// Filter coefficient c4. The matched filter will have unity gain when the sum +// of all coefficients c0 to c8 equals 512. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI2_C4_W 9U +#define LRFDMDM_DEMMAFI2_C4_M 0x000001FFU +#define LRFDMDM_DEMMAFI2_C4_S 0U +#define LRFDMDM_DEMMAFI2_C4_ALLONES 0x000001FFU +#define LRFDMDM_DEMMAFI2_C4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BE0 +// +//***************************************************************************** +// Field: [15:11] MASKB +// +// Mask for correlator B to select the correlator length to use. +// The number specifies number of nibbles (i.e. 4-bit block, which typically +// corresponds to one symbol) +// of the correlator holding the oldest samples that will be ignored in +// computations. +// When set to zero, the full 128 sample (=32 symbol) correlator length will be +// used. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE0_MASKB_W 5U +#define LRFDMDM_DEMC1BE0_MASKB_M 0x0000F800U +#define LRFDMDM_DEMC1BE0_MASKB_S 11U +#define LRFDMDM_DEMC1BE0_MASKB_ALLONES 0x0000F800U +#define LRFDMDM_DEMC1BE0_MASKB_ALLZEROS 0x00000000U + +// Field: [10:6] MASKA +// +// Mask for correlator A to select the correlator length to use. +// The number specifies number of nibbles (i.e. 4-bit block, which typically +// corresponds to one symbol) +// of the correlator holding the oldest samples that will be ignored in +// computations. +// When set to zero, the full 128 sample (=32 symbol) correlator length will be +// used. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE0_MASKA_W 5U +#define LRFDMDM_DEMC1BE0_MASKA_M 0x000007C0U +#define LRFDMDM_DEMC1BE0_MASKA_S 6U +#define LRFDMDM_DEMC1BE0_MASKA_ALLONES 0x000007C0U +#define LRFDMDM_DEMC1BE0_MASKA_ALLZEROS 0x00000000U + +// Field: [5:4] CASCCONF +// +// Correlator cascade configuration +// ENUMs: +// PARALLEL Connect correlators in parallel +// SERIAL Connect correlators in series (A -> B) +// SINGLE Correlator B not used +#define LRFDMDM_DEMC1BE0_CASCCONF_W 2U +#define LRFDMDM_DEMC1BE0_CASCCONF_M 0x00000030U +#define LRFDMDM_DEMC1BE0_CASCCONF_S 4U +#define LRFDMDM_DEMC1BE0_CASCCONF_PARALLEL 0x00000020U +#define LRFDMDM_DEMC1BE0_CASCCONF_SERIAL 0x00000010U +#define LRFDMDM_DEMC1BE0_CASCCONF_SINGLE 0x00000000U + +// Field: [3:0] COPYCONF +// +// Control auto copy of contents from corr A to corr B +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE0_COPYCONF_W 4U +#define LRFDMDM_DEMC1BE0_COPYCONF_M 0x0000000FU +#define LRFDMDM_DEMC1BE0_COPYCONF_S 0U +#define LRFDMDM_DEMC1BE0_COPYCONF_ALLONES 0x0000000FU +#define LRFDMDM_DEMC1BE0_COPYCONF_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BE1 +// +//***************************************************************************** +// Field: [15:8] THRESHOLDB +// +// Correlation threshold value for correlator B +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE1_THRESHOLDB_W 8U +#define LRFDMDM_DEMC1BE1_THRESHOLDB_M 0x0000FF00U +#define LRFDMDM_DEMC1BE1_THRESHOLDB_S 8U +#define LRFDMDM_DEMC1BE1_THRESHOLDB_ALLONES 0x0000FF00U +#define LRFDMDM_DEMC1BE1_THRESHOLDB_ALLZEROS 0x00000000U + +// Field: [7:0] THRESHOLDA +// +// Correlation threshold value for correlator A +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE1_THRESHOLDA_W 8U +#define LRFDMDM_DEMC1BE1_THRESHOLDA_M 0x000000FFU +#define LRFDMDM_DEMC1BE1_THRESHOLDA_S 0U +#define LRFDMDM_DEMC1BE1_THRESHOLDA_ALLONES 0x000000FFU +#define LRFDMDM_DEMC1BE1_THRESHOLDA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BE2 +// +//***************************************************************************** +// Field: [10] PARLOADCONF +// +// Configuration to control peak event generation (applies to correlators A, B, +// D, E) +// ENUMs: +// ATOD Trigger peak event only if peak is highest in +// correlator since search start +// ATOB Trigger peak event on all peaks above threshold +#define LRFDMDM_DEMC1BE2_PARLOADCONF 0x00000400U +#define LRFDMDM_DEMC1BE2_PARLOADCONF_M 0x00000400U +#define LRFDMDM_DEMC1BE2_PARLOADCONF_S 10U +#define LRFDMDM_DEMC1BE2_PARLOADCONF_ATOD 0x00000400U +#define LRFDMDM_DEMC1BE2_PARLOADCONF_ATOB 0x00000000U + +// Field: [9:8] PEAKCONF +// +// Configuration to control peak event generation (applies to correlators A, B, +// D, E) +// ENUMs: +// BESTAB Trigger peak event for combined highest peak +// search for corr "A and B" and "D and E" in +// pairs +// BEST Trigger peak event only if peak is highest in +// correlator since search start +// THRESH Trigger peak event on all peaks above threshold +#define LRFDMDM_DEMC1BE2_PEAKCONF_W 2U +#define LRFDMDM_DEMC1BE2_PEAKCONF_M 0x00000300U +#define LRFDMDM_DEMC1BE2_PEAKCONF_S 8U +#define LRFDMDM_DEMC1BE2_PEAKCONF_BESTAB 0x00000200U +#define LRFDMDM_DEMC1BE2_PEAKCONF_BEST 0x00000100U +#define LRFDMDM_DEMC1BE2_PEAKCONF_THRESH 0x00000000U + +// Field: [7:0] THRESHOLDC +// +// Correlation threshold value for correlator C (corr C is A+B concatenated) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BE2_THRESHOLDC_W 8U +#define LRFDMDM_DEMC1BE2_THRESHOLDC_M 0x000000FFU +#define LRFDMDM_DEMC1BE2_THRESHOLDC_S 0U +#define LRFDMDM_DEMC1BE2_THRESHOLDC_ALLONES 0x000000FFU +#define LRFDMDM_DEMC1BE2_THRESHOLDC_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SPARE0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SPARE0_VAL_W 16U +#define LRFDMDM_SPARE0_VAL_M 0x0000FFFFU +#define LRFDMDM_SPARE0_VAL_S 0U +#define LRFDMDM_SPARE0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_SPARE0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SPARE1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SPARE1_VAL_W 16U +#define LRFDMDM_SPARE1_VAL_M 0x0000FFFFU +#define LRFDMDM_SPARE1_VAL_S 0U +#define LRFDMDM_SPARE1_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_SPARE1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SPARE2 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SPARE2_VAL_W 16U +#define LRFDMDM_SPARE2_VAL_M 0x0000FFFFU +#define LRFDMDM_SPARE2_VAL_S 0U +#define LRFDMDM_SPARE2_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_SPARE2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SPARE3 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SPARE3_VAL_W 16U +#define LRFDMDM_SPARE3_VAL_M 0x0000FFFFU +#define LRFDMDM_SPARE3_VAL_S 0U +#define LRFDMDM_SPARE3_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_SPARE3_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMSWQU0 +// +//***************************************************************************** +// Field: [7] SYNCMODE +// +// 0: Search for A and B in parallell +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMSWQU0_SYNCMODE 0x00000080U +#define LRFDMDM_DEMSWQU0_SYNCMODE_M 0x00000080U +#define LRFDMDM_DEMSWQU0_SYNCMODE_S 7U +#define LRFDMDM_DEMSWQU0_SYNCMODE_ONE 0x00000080U +#define LRFDMDM_DEMSWQU0_SYNCMODE_ZERO 0x00000000U + +// Field: [6] AUTOMAFC +// +// Let sync word qualifier automatically control the manual frequency offset +// compensation (MAFC) block when it is running. +// ENUMs: +// ON Give control to sync word qualifier +// OFF Keep manual control over MAFC +#define LRFDMDM_DEMSWQU0_AUTOMAFC 0x00000040U +#define LRFDMDM_DEMSWQU0_AUTOMAFC_M 0x00000040U +#define LRFDMDM_DEMSWQU0_AUTOMAFC_S 6U +#define LRFDMDM_DEMSWQU0_AUTOMAFC_ON 0x00000040U +#define LRFDMDM_DEMSWQU0_AUTOMAFC_OFF 0x00000000U + +// Field: [5] RUN +// +// Start/stop sync word qualifier. +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_DEMSWQU0_RUN 0x00000020U +#define LRFDMDM_DEMSWQU0_RUN_M 0x00000020U +#define LRFDMDM_DEMSWQU0_RUN_S 5U +#define LRFDMDM_DEMSWQU0_RUN_ON 0x00000020U +#define LRFDMDM_DEMSWQU0_RUN_OFF 0x00000000U + +// Field: [4:0] REFLEN +// +// Bit length of sync word qualifier reference vector, constituted by (reflen + +// 1) most significant bits of sync word A and/or B. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMSWQU0_REFLEN_W 5U +#define LRFDMDM_DEMSWQU0_REFLEN_M 0x0000001FU +#define LRFDMDM_DEMSWQU0_REFLEN_S 0U +#define LRFDMDM_DEMSWQU0_REFLEN_ALLONES 0x0000001FU +#define LRFDMDM_DEMSWQU0_REFLEN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BEREF0 +// +//***************************************************************************** +// Field: [15:0] CAR15C0 +// +// Corr A reference bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BEREF0_CAR15C0_W 16U +#define LRFDMDM_DEMC1BEREF0_CAR15C0_M 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF0_CAR15C0_S 0U +#define LRFDMDM_DEMC1BEREF0_CAR15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF0_CAR15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BEREF1 +// +//***************************************************************************** +// Field: [15:0] CAR31C16 +// +// Corr A reference bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BEREF1_CAR31C16_W 16U +#define LRFDMDM_DEMC1BEREF1_CAR31C16_M 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF1_CAR31C16_S 0U +#define LRFDMDM_DEMC1BEREF1_CAR31C16_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF1_CAR31C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BEREF2 +// +//***************************************************************************** +// Field: [15:0] CBR15C0 +// +// Corr B reference bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BEREF2_CBR15C0_W 16U +#define LRFDMDM_DEMC1BEREF2_CBR15C0_M 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF2_CBR15C0_S 0U +#define LRFDMDM_DEMC1BEREF2_CBR15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF2_CBR15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMC1BEREF3 +// +//***************************************************************************** +// Field: [15:0] CBR31C16 +// +// Corr B reference bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMC1BEREF3_CBR31C16_W 16U +#define LRFDMDM_DEMC1BEREF3_CBR31C16_M 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF3_CBR31C16_S 0U +#define LRFDMDM_DEMC1BEREF3_CBR31C16_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMC1BEREF3_CBR31C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODCTRL +// +//***************************************************************************** +// Field: [11] DSBUSEL +// +// Select DSBU input source. It is not valid anymore. This bitfield is reserved +// for future use. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_MODCTRL_DSBUSEL 0x00000800U +#define LRFDMDM_MODCTRL_DSBUSEL_M 0x00000800U +#define LRFDMDM_MODCTRL_DSBUSEL_S 11U +#define LRFDMDM_MODCTRL_DSBUSEL_ONE 0x00000800U +#define LRFDMDM_MODCTRL_DSBUSEL_ZERO 0x00000000U + +// Field: [10] HDISMODE +// +// Enable Hilbert discriminator mode for data descicion +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_MODCTRL_HDISMODE 0x00000400U +#define LRFDMDM_MODCTRL_HDISMODE_M 0x00000400U +#define LRFDMDM_MODCTRL_HDISMODE_S 10U +#define LRFDMDM_MODCTRL_HDISMODE_EN 0x00000400U +#define LRFDMDM_MODCTRL_HDISMODE_DIS 0x00000000U + +// Field: [9] PARBITQUALEN +// +// Enable Parallel Bit Qualifier (read DEMC1BEA) +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_MODCTRL_PARBITQUALEN 0x00000200U +#define LRFDMDM_MODCTRL_PARBITQUALEN_M 0x00000200U +#define LRFDMDM_MODCTRL_PARBITQUALEN_S 9U +#define LRFDMDM_MODCTRL_PARBITQUALEN_ON 0x00000200U +#define LRFDMDM_MODCTRL_PARBITQUALEN_OFF 0x00000000U + +// Field: [8:7] STIMMODE +// +// Controls STIM module for different modes +// ENUMs: +// EARLY STIM starts early +// LATE STIM starts late +// NORMAL Normal Mode +#define LRFDMDM_MODCTRL_STIMMODE_W 2U +#define LRFDMDM_MODCTRL_STIMMODE_M 0x00000180U +#define LRFDMDM_MODCTRL_STIMMODE_S 7U +#define LRFDMDM_MODCTRL_STIMMODE_EARLY 0x00000100U +#define LRFDMDM_MODCTRL_STIMMODE_LATE 0x00000080U +#define LRFDMDM_MODCTRL_STIMMODE_NORMAL 0x00000000U + +// Field: [6] C1BEMODE +// +// Controls the C1BE mode +// ENUMs: +// EARLYLATE Set the C1BE in special early/late mode +// NORMAL Normal mode +#define LRFDMDM_MODCTRL_C1BEMODE 0x00000040U +#define LRFDMDM_MODCTRL_C1BEMODE_M 0x00000040U +#define LRFDMDM_MODCTRL_C1BEMODE_S 6U +#define LRFDMDM_MODCTRL_C1BEMODE_EARLYLATE 0x00000040U +#define LRFDMDM_MODCTRL_C1BEMODE_NORMAL 0x00000000U + +// Field: [5] SOFTPDIFFMODE +// +// Enable Soft PDIFF mode for RX +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_MODCTRL_SOFTPDIFFMODE 0x00000020U +#define LRFDMDM_MODCTRL_SOFTPDIFFMODE_M 0x00000020U +#define LRFDMDM_MODCTRL_SOFTPDIFFMODE_S 5U +#define LRFDMDM_MODCTRL_SOFTPDIFFMODE_EN 0x00000020U +#define LRFDMDM_MODCTRL_SOFTPDIFFMODE_DIS 0x00000000U + +// Field: [4] SOFTTXENABLE +// +// Enable SOFT TX mode, controlled via MODSOFTTX +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_MODCTRL_SOFTTXENABLE 0x00000010U +#define LRFDMDM_MODCTRL_SOFTTXENABLE_M 0x00000010U +#define LRFDMDM_MODCTRL_SOFTTXENABLE_S 4U +#define LRFDMDM_MODCTRL_SOFTTXENABLE_ON 0x00000010U +#define LRFDMDM_MODCTRL_SOFTTXENABLE_OFF 0x00000000U + +// Field: [3] FECENABLE +// +// Global FEC modes enable +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_MODCTRL_FECENABLE 0x00000008U +#define LRFDMDM_MODCTRL_FECENABLE_M 0x00000008U +#define LRFDMDM_MODCTRL_FECENABLE_S 3U +#define LRFDMDM_MODCTRL_FECENABLE_ON 0x00000008U +#define LRFDMDM_MODCTRL_FECENABLE_OFF 0x00000000U + +// Field: [2] FEC5TERMINATE +// +// Goes into termination mode in 5Mbps TX FEC. This bitfield is not valid +// anymore. +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM_MODCTRL_FEC5TERMINATE 0x00000004U +#define LRFDMDM_MODCTRL_FEC5TERMINATE_M 0x00000004U +#define LRFDMDM_MODCTRL_FEC5TERMINATE_S 2U +#define LRFDMDM_MODCTRL_FEC5TERMINATE_ON 0x00000004U +#define LRFDMDM_MODCTRL_FEC5TERMINATE_OFF 0x00000000U + +// Field: [1] TONEINSERT +// +// Inserts a tone +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_MODCTRL_TONEINSERT 0x00000002U +#define LRFDMDM_MODCTRL_TONEINSERT_M 0x00000002U +#define LRFDMDM_MODCTRL_TONEINSERT_S 1U +#define LRFDMDM_MODCTRL_TONEINSERT_EN 0x00000002U +#define LRFDMDM_MODCTRL_TONEINSERT_DIS 0x00000000U + +// Field: [0] PREAMBLEINSERT +// +// Inserts preamble +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM_MODCTRL_PREAMBLEINSERT 0x00000001U +#define LRFDMDM_MODCTRL_PREAMBLEINSERT_M 0x00000001U +#define LRFDMDM_MODCTRL_PREAMBLEINSERT_S 0U +#define LRFDMDM_MODCTRL_PREAMBLEINSERT_EN 0x00000001U +#define LRFDMDM_MODCTRL_PREAMBLEINSERT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MODPREAMBLE +// +//***************************************************************************** +// Field: [15:0] WORD +// +// 16 bit preamble word pattern. The LSB is transmitted first +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MODPREAMBLE_WORD_W 16U +#define LRFDMDM_MODPREAMBLE_WORD_M 0x0000FFFFU +#define LRFDMDM_MODPREAMBLE_WORD_S 0U +#define LRFDMDM_MODPREAMBLE_WORD_ALLONES 0x0000FFFFU +#define LRFDMDM_MODPREAMBLE_WORD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFRAC0 +// +//***************************************************************************** +// Field: [15:0] P15C0 +// +// Downsampler P[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. +// The hardware requires the resampling factor P/Q to be in the range [1/4, 1], +// i.e. only down-sampling with a factor in the range [1,4] is supported. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFRAC0_P15C0_W 16U +#define LRFDMDM_DEMFRAC0_P15C0_M 0x0000FFFFU +#define LRFDMDM_DEMFRAC0_P15C0_S 0U +#define LRFDMDM_DEMFRAC0_P15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMFRAC0_P15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFRAC1 +// +//***************************************************************************** +// Field: [11:0] P27C16 +// +// Downsampler P[27:16] +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFRAC1_P27C16_W 12U +#define LRFDMDM_DEMFRAC1_P27C16_M 0x00000FFFU +#define LRFDMDM_DEMFRAC1_P27C16_S 0U +#define LRFDMDM_DEMFRAC1_P27C16_ALLONES 0x00000FFFU +#define LRFDMDM_DEMFRAC1_P27C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFRAC2 +// +//***************************************************************************** +// Field: [15:0] Q15C0 +// +// Downsampler Q[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. +// The hardware requires the resampling factor P/Q to be in the range [1/4, 1], +// i.e. only down-sampling with a factor in the range [1,4] is supported. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFRAC2_Q15C0_W 16U +#define LRFDMDM_DEMFRAC2_Q15C0_M 0x0000FFFFU +#define LRFDMDM_DEMFRAC2_Q15C0_S 0U +#define LRFDMDM_DEMFRAC2_Q15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_DEMFRAC2_Q15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFRAC3 +// +//***************************************************************************** +// Field: [11:0] Q27C16 +// +// Downsampler Q[27:16] +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFRAC3_Q27C16_W 12U +#define LRFDMDM_DEMFRAC3_Q27C16_M 0x00000FFFU +#define LRFDMDM_DEMFRAC3_Q27C16_S 0U +#define LRFDMDM_DEMFRAC3_Q27C16_ALLONES 0x00000FFFU +#define LRFDMDM_DEMFRAC3_Q27C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMCODC1 +// +//***************************************************************************** +// Field: [12:0] COMPIVAL +// +// Compensation value, I branch +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMCODC1_COMPIVAL_W 13U +#define LRFDMDM_DEMCODC1_COMPIVAL_M 0x00001FFFU +#define LRFDMDM_DEMCODC1_COMPIVAL_S 0U +#define LRFDMDM_DEMCODC1_COMPIVAL_ALLONES 0x00001FFFU +#define LRFDMDM_DEMCODC1_COMPIVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMCODC2 +// +//***************************************************************************** +// Field: [12:0] COMPQVAL +// +// Compensation value, Q branch +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMCODC2_COMPQVAL_W 13U +#define LRFDMDM_DEMCODC2_COMPQVAL_M 0x00001FFFU +#define LRFDMDM_DEMCODC2_COMPQVAL_S 0U +#define LRFDMDM_DEMCODC2_COMPQVAL_ALLONES 0x00001FFFU +#define LRFDMDM_DEMCODC2_COMPQVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFIDC1 +// +//***************************************************************************** +// Field: [12:0] COMPIVAL +// +// Compensation value for I path +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFIDC1_COMPIVAL_W 13U +#define LRFDMDM_DEMFIDC1_COMPIVAL_M 0x00001FFFU +#define LRFDMDM_DEMFIDC1_COMPIVAL_S 0U +#define LRFDMDM_DEMFIDC1_COMPIVAL_ALLONES 0x00001FFFU +#define LRFDMDM_DEMFIDC1_COMPIVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFIDC2 +// +//***************************************************************************** +// Field: [12:0] COMPQVAL +// +// Compensation value for Q path +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFIDC2_COMPQVAL_W 13U +#define LRFDMDM_DEMFIDC2_COMPQVAL_M 0x00001FFFU +#define LRFDMDM_DEMFIDC2_COMPQVAL_S 0U +#define LRFDMDM_DEMFIDC2_COMPQVAL_ALLONES 0x00001FFFU +#define LRFDMDM_DEMFIDC2_COMPQVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMFIFE1 +// +//***************************************************************************** +// Field: [7:0] FOCFBREGVAL +// +// Value for feed-back compensation point (signed) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMFIFE1_FOCFBREGVAL_W 8U +#define LRFDMDM_DEMFIFE1_FOCFBREGVAL_M 0x000000FFU +#define LRFDMDM_DEMFIFE1_FOCFBREGVAL_S 0U +#define LRFDMDM_DEMFIFE1_FOCFBREGVAL_ALLONES 0x000000FFU +#define LRFDMDM_DEMFIFE1_FOCFBREGVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMAFC0 +// +//***************************************************************************** +// Field: [7:0] COMPVAL +// +// Value for manual compensation (signed) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFC0_COMPVAL_W 8U +#define LRFDMDM_DEMMAFC0_COMPVAL_M 0x000000FFU +#define LRFDMDM_DEMMAFC0_COMPVAL_S 0U +#define LRFDMDM_DEMMAFC0_COMPVAL_ALLONES 0x000000FFU +#define LRFDMDM_DEMMAFC0_COMPVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMMAFI4 +// +//***************************************************************************** +// Field: [7:0] TERMVAL +// +// Input value to terminate matched filter with. Writing to this register +// triggers the termination. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMMAFI4_TERMVAL_W 8U +#define LRFDMDM_DEMMAFI4_TERMVAL_M 0x000000FFU +#define LRFDMDM_DEMMAFI4_TERMVAL_S 0U +#define LRFDMDM_DEMMAFI4_TERMVAL_ALLONES 0x000000FFU +#define LRFDMDM_DEMMAFI4_TERMVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMSWIMBAL +// +//***************************************************************************** +// Field: [15:8] IMBALB +// +// DC imbalance in sync word B, applied via SWQU upon C1BE correlator A peak +// event +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMSWIMBAL_IMBALB_W 8U +#define LRFDMDM_DEMSWIMBAL_IMBALB_M 0x0000FF00U +#define LRFDMDM_DEMSWIMBAL_IMBALB_S 8U +#define LRFDMDM_DEMSWIMBAL_IMBALB_ALLONES 0x0000FF00U +#define LRFDMDM_DEMSWIMBAL_IMBALB_ALLZEROS 0x00000000U + +// Field: [7:0] IMBALA +// +// DC imbalance in sync word A, applied via SWQU upon C1BE correlator B peak +// event +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMSWIMBAL_IMBALA_W 8U +#define LRFDMDM_DEMSWIMBAL_IMBALA_M 0x000000FFU +#define LRFDMDM_DEMSWIMBAL_IMBALA_S 0U +#define LRFDMDM_DEMSWIMBAL_IMBALA_ALLONES 0x000000FFU +#define LRFDMDM_DEMSWIMBAL_IMBALA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMSOFTPDIFF +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Replaces PDIFF output when in Soft PDIFF Mode. Can be used for manually +// feeding samples (e.g. on-off-keying (OOK) samples from RFE) into the +// demodulator decode stage. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMSOFTPDIFF_VAL_W 8U +#define LRFDMDM_DEMSOFTPDIFF_VAL_M 0x000000FFU +#define LRFDMDM_DEMSOFTPDIFF_VAL_S 0U +#define LRFDMDM_DEMSOFTPDIFF_VAL_ALLONES 0x000000FFU +#define LRFDMDM_DEMSOFTPDIFF_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMDEBUG +// +//***************************************************************************** +// Field: [11:9] LOOPBACKPIN +// +// Choose which GPI pin is connected to loopback +// ENUMs: +// GPI7 GPI7 connected to loopback +// GPI6 GPI6 connected to loopback +// GPI5 GPI5 connected to loopback +// GPI4 GPI4 connected to loopback +// GPI3 GPI3 connected to loopback +// GPI2 GPI2 connected to loopback +// GPI1 GPI1 connected to loopback +// GPI0 GPI0 connected to loopback +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_W 3U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_M 0x00000E00U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_S 9U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI7 0x00000E00U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI6 0x00000C00U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI5 0x00000A00U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI4 0x00000800U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI3 0x00000600U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI2 0x00000400U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI1 0x00000200U +#define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI0 0x00000000U + +// Field: [8] DECSTAGETRIGGER +// +// Set high to trigger event to S2R module. Need to be written low again (no HW +// clear) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER 0x00000100U +#define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_M 0x00000100U +#define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_S 8U +#define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_ONE 0x00000100U +#define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_ZERO 0x00000000U + +// Field: [7:5] DECSTAGEDEBUG +// +// Selects which decode stage signal source to dump for debugging via S2R +// module. +// The decode stage samples are signed 8-bit samples, +// packed into 32-bit words with the oldest sample as the most significant +// byte. +// ENUMs: +// SOFD Dump SOFD output samples +// STIM Dump STIM output samples +// MAFC Dump MAFC output samples +// C1BE Dump C1BE correlator A value (truncated to 8 LSBs +// only, may overflow if correlator value is +// +128). +// MAFI Dump MAFI output samples +// FIFE Dump PDIF output samples +// PDIF Dump PDIF output samples +// NOSEL No source selected +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_W 3U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_M 0x000000E0U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_S 5U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_SOFD 0x000000E0U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_STIM 0x000000C0U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_MAFC 0x000000A0U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_C1BE 0x00000080U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_MAFI 0x00000060U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_FIFE 0x00000040U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_PDIF 0x00000020U +#define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_NOSEL 0x00000000U + +// Field: [4] FRONTENDTRIGGER +// +// Set high to trigger event to S2R module. Need to be written low again (no HW +// clear) +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER 0x00000010U +#define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_M 0x00000010U +#define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_S 4U +#define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_ONE 0x00000010U +#define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_ZERO 0x00000000U + +// Field: [3:1] FRONTENDDEBUG +// +// Selects which front-end stage signal source to dump for debugging via S2R +// module. +// The front-end stage samples are signed 16-bit samples from both I and Q +// signal path, +// packed together into 32-bit words with the I sample as the 16 MSB and Q +// sample as the 16 LSB. +// ENUMs: +// FIDC Dump FRAC output samples +// FRAC Dump FRAC output samples +// CHFI Dump CHFI output samples +// BDE2 Dump BDE2 output samples +// FEXB2 Dump FEXB output #2 samples, as selected by +// DEMFEXB0.OUT2SRCSEL register +// BDE1 Dump BDE1 output samples +// IQMC Dump IQMC output samples +// NOSEL No source selected +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_W 3U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_M 0x0000000EU +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_S 1U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FIDC 0x0000000EU +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FRAC 0x0000000CU +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_CHFI 0x0000000AU +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_BDE2 0x00000008U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FEXB2 0x00000006U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_BDE1 0x00000004U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_IQMC 0x00000002U +#define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_NOSEL 0x00000000U + +// Field: [0] LOOPBACKMODE +// +// Enables loopback mode +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMDEBUG_LOOPBACKMODE 0x00000001U +#define LRFDMDM_DEMDEBUG_LOOPBACKMODE_M 0x00000001U +#define LRFDMDM_DEMDEBUG_LOOPBACKMODE_S 0U +#define LRFDMDM_DEMDEBUG_LOOPBACKMODE_ONE 0x00000001U +#define LRFDMDM_DEMDEBUG_LOOPBACKMODE_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITCTRL +// +//***************************************************************************** +// Field: [7:6] METRSEL +// +// Selects which HW module is connected to viterbi decoder +// ENUMs: +// MLSE Use MLSE Metrics +// SOFD Use SOFD Metrics +// PHAC Use PHAC Metrics +// MET5M Use 5Mbps Metrics +#define LRFDMDM_VITCTRL_METRSEL_W 2U +#define LRFDMDM_VITCTRL_METRSEL_M 0x000000C0U +#define LRFDMDM_VITCTRL_METRSEL_S 6U +#define LRFDMDM_VITCTRL_METRSEL_MLSE 0x000000C0U +#define LRFDMDM_VITCTRL_METRSEL_SOFD 0x00000080U +#define LRFDMDM_VITCTRL_METRSEL_PHAC 0x00000040U +#define LRFDMDM_VITCTRL_METRSEL_MET5M 0x00000000U + +// Field: [5:2] APMRDBACKSEL +// +// Selects the APM to read back via VITAPMRDBACK register. +// ENUMs: +// APM7 View APM 7 +// APM6 View APM 6 +// APM5 View APM 5 +// APM4 View APM 4 +// APM3 View APM 3 +// APM2 View APM 2 +// APM1 View APM 1 +// APM0 View APM 0 +// NOSEL No selection +#define LRFDMDM_VITCTRL_APMRDBACKSEL_W 4U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_M 0x0000003CU +#define LRFDMDM_VITCTRL_APMRDBACKSEL_S 2U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM7 0x0000003CU +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM6 0x00000038U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM5 0x00000034U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM4 0x00000030U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM3 0x0000002CU +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM2 0x00000028U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM1 0x00000024U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_APM0 0x00000020U +#define LRFDMDM_VITCTRL_APMRDBACKSEL_NOSEL 0x00000000U + +// Field: [1] ACSITERATIONS +// +// Number of iterations per ACS element +// ENUMs: +// CODE23 4 iterations per ACS (4 branches, 2/3 codes) +// CODE12 2 iterations per ACS (2 branches, 1/2 codes) +#define LRFDMDM_VITCTRL_ACSITERATIONS 0x00000002U +#define LRFDMDM_VITCTRL_ACSITERATIONS_M 0x00000002U +#define LRFDMDM_VITCTRL_ACSITERATIONS_S 1U +#define LRFDMDM_VITCTRL_ACSITERATIONS_CODE23 0x00000002U +#define LRFDMDM_VITCTRL_ACSITERATIONS_CODE12 0x00000000U + +// Field: [0] METRICS +// +// Select Metrics +// ENUMs: +// SOFT Use soft Metrics (register based) +// HW Use HW metrics as defined by VITCTRL.METRSEL bits +#define LRFDMDM_VITCTRL_METRICS 0x00000001U +#define LRFDMDM_VITCTRL_METRICS_M 0x00000001U +#define LRFDMDM_VITCTRL_METRICS_S 0U +#define LRFDMDM_VITCTRL_METRICS_SOFT 0x00000001U +#define LRFDMDM_VITCTRL_METRICS_HW 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITCOMPUTE +// +//***************************************************************************** +// Field: [0] START +// +// Initiates a compute cycle +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_VITCOMPUTE_START 0x00000001U +#define LRFDMDM_VITCOMPUTE_START_M 0x00000001U +#define LRFDMDM_VITCOMPUTE_START_S 0U +#define LRFDMDM_VITCOMPUTE_START_ONE 0x00000001U +#define LRFDMDM_VITCOMPUTE_START_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITAPMRDBACK +// +//***************************************************************************** +// Field: [9:0] VALUE +// +// APM for element i (selected in VITCTRL register). +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITAPMRDBACK_VALUE_W 10U +#define LRFDMDM_VITAPMRDBACK_VALUE_M 0x000003FFU +#define LRFDMDM_VITAPMRDBACK_VALUE_S 0U +#define LRFDMDM_VITAPMRDBACK_VALUE_ALLONES 0x000003FFU +#define LRFDMDM_VITAPMRDBACK_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITSTATE +// +//***************************************************************************** +// Field: [2:0] VALUE +// +// Current Winning State +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITSTATE_VALUE_W 3U +#define LRFDMDM_VITSTATE_VALUE_M 0x00000007U +#define LRFDMDM_VITSTATE_VALUE_S 0U +#define LRFDMDM_VITSTATE_VALUE_ALLONES 0x00000007U +#define LRFDMDM_VITSTATE_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITBRMETRIC10 +// +//***************************************************************************** +// Field: [15:8] MET1 +// +// Branch Metric 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC10_MET1_W 8U +#define LRFDMDM_VITBRMETRIC10_MET1_M 0x0000FF00U +#define LRFDMDM_VITBRMETRIC10_MET1_S 8U +#define LRFDMDM_VITBRMETRIC10_MET1_ALLONES 0x0000FF00U +#define LRFDMDM_VITBRMETRIC10_MET1_ALLZEROS 0x00000000U + +// Field: [7:0] MET0 +// +// Branch Metric 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC10_MET0_W 8U +#define LRFDMDM_VITBRMETRIC10_MET0_M 0x000000FFU +#define LRFDMDM_VITBRMETRIC10_MET0_S 0U +#define LRFDMDM_VITBRMETRIC10_MET0_ALLONES 0x000000FFU +#define LRFDMDM_VITBRMETRIC10_MET0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITBRMETRIC32 +// +//***************************************************************************** +// Field: [15:8] MET3 +// +// Branch Metric 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC32_MET3_W 8U +#define LRFDMDM_VITBRMETRIC32_MET3_M 0x0000FF00U +#define LRFDMDM_VITBRMETRIC32_MET3_S 8U +#define LRFDMDM_VITBRMETRIC32_MET3_ALLONES 0x0000FF00U +#define LRFDMDM_VITBRMETRIC32_MET3_ALLZEROS 0x00000000U + +// Field: [7:0] MET2 +// +// Branch Metric 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC32_MET2_W 8U +#define LRFDMDM_VITBRMETRIC32_MET2_M 0x000000FFU +#define LRFDMDM_VITBRMETRIC32_MET2_S 0U +#define LRFDMDM_VITBRMETRIC32_MET2_ALLONES 0x000000FFU +#define LRFDMDM_VITBRMETRIC32_MET2_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITBRMETRIC54 +// +//***************************************************************************** +// Field: [15:8] MET5 +// +// Branch Metric 5 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC54_MET5_W 8U +#define LRFDMDM_VITBRMETRIC54_MET5_M 0x0000FF00U +#define LRFDMDM_VITBRMETRIC54_MET5_S 8U +#define LRFDMDM_VITBRMETRIC54_MET5_ALLONES 0x0000FF00U +#define LRFDMDM_VITBRMETRIC54_MET5_ALLZEROS 0x00000000U + +// Field: [7:0] MET4 +// +// Branch Metric 4 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC54_MET4_W 8U +#define LRFDMDM_VITBRMETRIC54_MET4_M 0x000000FFU +#define LRFDMDM_VITBRMETRIC54_MET4_S 0U +#define LRFDMDM_VITBRMETRIC54_MET4_ALLONES 0x000000FFU +#define LRFDMDM_VITBRMETRIC54_MET4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_VITBRMETRIC76 +// +//***************************************************************************** +// Field: [15:8] MET7 +// +// Branch Metric 7 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC76_MET7_W 8U +#define LRFDMDM_VITBRMETRIC76_MET7_M 0x0000FF00U +#define LRFDMDM_VITBRMETRIC76_MET7_S 8U +#define LRFDMDM_VITBRMETRIC76_MET7_ALLONES 0x0000FF00U +#define LRFDMDM_VITBRMETRIC76_MET7_ALLZEROS 0x00000000U + +// Field: [7:0] MET6 +// +// Branch Metric 6 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_VITBRMETRIC76_MET6_W 8U +#define LRFDMDM_VITBRMETRIC76_MET6_M 0x000000FFU +#define LRFDMDM_VITBRMETRIC76_MET6_S 0U +#define LRFDMDM_VITBRMETRIC76_MET6_ALLONES 0x000000FFU +#define LRFDMDM_VITBRMETRIC76_MET6_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMCTL +// +//***************************************************************************** +// Field: [13:8] CPTSRC +// +// Selects bit number from event bus for a counter capture. Event number in +// range 0 to 63 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_TIMCTL_CPTSRC_W 6U +#define LRFDMDM_TIMCTL_CPTSRC_M 0x00003F00U +#define LRFDMDM_TIMCTL_CPTSRC_S 8U +#define LRFDMDM_TIMCTL_CPTSRC_ALLONES 0x00003F00U +#define LRFDMDM_TIMCTL_CPTSRC_ALLZEROS 0x00000000U + +// Field: [7] CPTCTL +// +// Enable counter capture on event. Upon a capture event, the counter value +// will be captured in TIMCAPT register. +// ENUMs: +// EN Enable capture mode for counter +// DIS Disable capture mode for counter +#define LRFDMDM_TIMCTL_CPTCTL 0x00000080U +#define LRFDMDM_TIMCTL_CPTCTL_M 0x00000080U +#define LRFDMDM_TIMCTL_CPTCTL_S 7U +#define LRFDMDM_TIMCTL_CPTCTL_EN 0x00000080U +#define LRFDMDM_TIMCTL_CPTCTL_DIS 0x00000000U + +// Field: [6:5] CNTRSRC +// +// Select event source for counter +// ENUMs: +// CLK4BAUDF Use 4xBaud flushed event +// CLK4BAUD Use 4xBaud event +// CLKBAUD Use baud event +// CLK Use clock +#define LRFDMDM_TIMCTL_CNTRSRC_W 2U +#define LRFDMDM_TIMCTL_CNTRSRC_M 0x00000060U +#define LRFDMDM_TIMCTL_CNTRSRC_S 5U +#define LRFDMDM_TIMCTL_CNTRSRC_CLK4BAUDF 0x00000060U +#define LRFDMDM_TIMCTL_CNTRSRC_CLK4BAUD 0x00000040U +#define LRFDMDM_TIMCTL_CNTRSRC_CLKBAUD 0x00000020U +#define LRFDMDM_TIMCTL_CNTRSRC_CLK 0x00000000U + +// Field: [4] CNTRCLR +// +// Clear counter value in TIMCNT to zero when this bit is set to 1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_TIMCTL_CNTRCLR 0x00000010U +#define LRFDMDM_TIMCTL_CNTRCLR_M 0x00000010U +#define LRFDMDM_TIMCTL_CNTRCLR_S 4U +#define LRFDMDM_TIMCTL_CNTRCLR_ONE 0x00000010U +#define LRFDMDM_TIMCTL_CNTRCLR_ZERO 0x00000000U + +// Field: [3] CNTRCTL +// +// Enable 16-bit counter when set to 1. The counter will continue from its +// current value. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_TIMCTL_CNTRCTL 0x00000008U +#define LRFDMDM_TIMCTL_CNTRCTL_M 0x00000008U +#define LRFDMDM_TIMCTL_CNTRCTL_S 3U +#define LRFDMDM_TIMCTL_CNTRCTL_ONE 0x00000008U +#define LRFDMDM_TIMCTL_CNTRCTL_ZERO 0x00000000U + +// Field: [2:1] TIMSRC +// +// Select timer tick source for timer +// ENUMs: +// CLK4BAUDF 4xBaud flushed +// CLK4BAUD 4xBaud +// CLKBAUD Baud +// CLK Clock +#define LRFDMDM_TIMCTL_TIMSRC_W 2U +#define LRFDMDM_TIMCTL_TIMSRC_M 0x00000006U +#define LRFDMDM_TIMCTL_TIMSRC_S 1U +#define LRFDMDM_TIMCTL_TIMSRC_CLK4BAUDF 0x00000006U +#define LRFDMDM_TIMCTL_TIMSRC_CLK4BAUD 0x00000004U +#define LRFDMDM_TIMCTL_TIMSRC_CLKBAUD 0x00000002U +#define LRFDMDM_TIMCTL_TIMSRC_CLK 0x00000000U + +// Field: [0] TIMCTL +// +// Enable 16-bit timer. It will generate a timer interrupt after TIMPER timer +// ticks. +// Note that the internal timer value is not readable from the MCE. If this is +// needed the counter should be used instead of the timer. +// ENUMs: +// EN Will enable timer +// DIS Will disable timer and clear internal timer value +#define LRFDMDM_TIMCTL_TIMCTL 0x00000001U +#define LRFDMDM_TIMCTL_TIMCTL_M 0x00000001U +#define LRFDMDM_TIMCTL_TIMCTL_S 0U +#define LRFDMDM_TIMCTL_TIMCTL_EN 0x00000001U +#define LRFDMDM_TIMCTL_TIMCTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMINC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Programmable counter increment. For each counter event: TIMCNT + 1). +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_TIMINC_VAL_W 16U +#define LRFDMDM_TIMINC_VAL_M 0x0000FFFFU +#define LRFDMDM_TIMINC_VAL_S 0U +#define LRFDMDM_TIMINC_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_TIMINC_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMPER +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Configurable 16 bit period that can be used for either the timer or the +// counter. +// In timer context, when timer value reach the timer period (i.e. it expires) +// a TIMER_IRQ event will occur, +// and the timer will restart from zero (until the timer is manually disabled). +// In counter context, a COUNTER_IRQ event will occur when the counter is equal +// to or higher than the period value. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_TIMPER_VAL_W 16U +#define LRFDMDM_TIMPER_VAL_M 0x0000FFFFU +#define LRFDMDM_TIMPER_VAL_S 0U +#define LRFDMDM_TIMPER_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_TIMPER_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMCNT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// 16 bit counter value that can be read by the MCE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_TIMCNT_VAL_W 16U +#define LRFDMDM_TIMCNT_VAL_M 0x0000FFFFU +#define LRFDMDM_TIMCNT_VAL_S 0U +#define LRFDMDM_TIMCNT_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_TIMCNT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMCAPT +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Captured value of counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_TIMCAPT_VALUE_W 16U +#define LRFDMDM_TIMCAPT_VALUE_M 0x0000FFFFU +#define LRFDMDM_TIMCAPT_VALUE_S 0U +#define LRFDMDM_TIMCAPT_VALUE_ALLONES 0x0000FFFFU +#define LRFDMDM_TIMCAPT_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_TIMEBASE +// +//***************************************************************************** +// Field: [0] FLUSH +// +// Starts a flushing process +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_TIMEBASE_FLUSH 0x00000001U +#define LRFDMDM_TIMEBASE_FLUSH_M 0x00000001U +#define LRFDMDM_TIMEBASE_FLUSH_S 0U +#define LRFDMDM_TIMEBASE_FLUSH_ONE 0x00000001U +#define LRFDMDM_TIMEBASE_FLUSH_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_COUNT1IN +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Input data, which we shall find the number of 1's in +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_COUNT1IN_VAL_W 16U +#define LRFDMDM_COUNT1IN_VAL_M 0x0000FFFFU +#define LRFDMDM_COUNT1IN_VAL_S 0U +#define LRFDMDM_COUNT1IN_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_COUNT1IN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_COUNT1RES +// +//***************************************************************************** +// Field: [4:0] VAL +// +// Number of 1's in the COUNT1IN register +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_COUNT1RES_VAL_W 5U +#define LRFDMDM_COUNT1RES_VAL_M 0x0000001FU +#define LRFDMDM_COUNT1RES_VAL_S 0U +#define LRFDMDM_COUNT1RES_VAL_ALLONES 0x0000001FU +#define LRFDMDM_COUNT1RES_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_BRMACC1 +// +//***************************************************************************** +// Field: [15:8] METRIC01 +// +// Metric to 01 (-1 +1) symbol. Immediately calculated when BRMACC0 register is +// written. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BRMACC1_METRIC01_W 8U +#define LRFDMDM_BRMACC1_METRIC01_M 0x0000FF00U +#define LRFDMDM_BRMACC1_METRIC01_S 8U +#define LRFDMDM_BRMACC1_METRIC01_ALLONES 0x0000FF00U +#define LRFDMDM_BRMACC1_METRIC01_ALLZEROS 0x00000000U + +// Field: [7:0] METRIC00 +// +// Metric to 00 (-1 -1) symbol. Immediately calculated when BRMACC0 register is +// written. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BRMACC1_METRIC00_W 8U +#define LRFDMDM_BRMACC1_METRIC00_M 0x000000FFU +#define LRFDMDM_BRMACC1_METRIC00_S 0U +#define LRFDMDM_BRMACC1_METRIC00_ALLONES 0x000000FFU +#define LRFDMDM_BRMACC1_METRIC00_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_BRMACC2 +// +//***************************************************************************** +// Field: [15:8] METRIC11 +// +// Metric to 11 (+1 +1) symbol. Immediately calculated when BRMACC0 register is +// written. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BRMACC2_METRIC11_W 8U +#define LRFDMDM_BRMACC2_METRIC11_M 0x0000FF00U +#define LRFDMDM_BRMACC2_METRIC11_S 8U +#define LRFDMDM_BRMACC2_METRIC11_ALLONES 0x0000FF00U +#define LRFDMDM_BRMACC2_METRIC11_ALLZEROS 0x00000000U + +// Field: [7:0] METRIC10 +// +// Metric to 10 (+1 -1) symbol. Immediately calculated when BRMACC0 register is +// written. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_BRMACC2_METRIC10_W 8U +#define LRFDMDM_BRMACC2_METRIC10_M 0x000000FFU +#define LRFDMDM_BRMACC2_METRIC10_S 0U +#define LRFDMDM_BRMACC2_METRIC10_ALLONES 0x000000FFU +#define LRFDMDM_BRMACC2_METRIC10_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MCETRCCTRL +// +//***************************************************************************** +// Field: [0] SEND +// +// Sends a command to the tracer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_MCETRCCTRL_SEND 0x00000001U +#define LRFDMDM_MCETRCCTRL_SEND_M 0x00000001U +#define LRFDMDM_MCETRCCTRL_SEND_S 0U +#define LRFDMDM_MCETRCCTRL_SEND_ONE 0x00000001U +#define LRFDMDM_MCETRCCTRL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MCETRCSTAT +// +//***************************************************************************** +// Field: [0] BUSY +// +// Checks if the tracer is busy +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_MCETRCSTAT_BUSY 0x00000001U +#define LRFDMDM_MCETRCSTAT_BUSY_M 0x00000001U +#define LRFDMDM_MCETRCSTAT_BUSY_S 0U +#define LRFDMDM_MCETRCSTAT_BUSY_ONE 0x00000001U +#define LRFDMDM_MCETRCSTAT_BUSY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MCETRCCMD +// +//***************************************************************************** +// Field: [9:8] PARCNT +// +// Number of parameters +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MCETRCCMD_PARCNT_W 2U +#define LRFDMDM_MCETRCCMD_PARCNT_M 0x00000300U +#define LRFDMDM_MCETRCCMD_PARCNT_S 8U +#define LRFDMDM_MCETRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDMDM_MCETRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// Packet header +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MCETRCCMD_PKTHDR_W 8U +#define LRFDMDM_MCETRCCMD_PKTHDR_M 0x000000FFU +#define LRFDMDM_MCETRCCMD_PKTHDR_S 0U +#define LRFDMDM_MCETRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDMDM_MCETRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MCETRCPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MCETRCPAR0_VAL_W 16U +#define LRFDMDM_MCETRCPAR0_VAL_M 0x0000FFFFU +#define LRFDMDM_MCETRCPAR0_VAL_S 0U +#define LRFDMDM_MCETRCPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_MCETRCPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_MCETRCPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_MCETRCPAR1_VAL_W 16U +#define LRFDMDM_MCETRCPAR1_VAL_M 0x0000FFFFU +#define LRFDMDM_MCETRCPAR1_VAL_S 0U +#define LRFDMDM_MCETRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM_MCETRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RDCAPT0 +// +//***************************************************************************** +// Field: [5] CHFI +// +// Capture CHFI output samples into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_CHFI 0x00000020U +#define LRFDMDM_RDCAPT0_CHFI_M 0x00000020U +#define LRFDMDM_RDCAPT0_CHFI_S 5U +#define LRFDMDM_RDCAPT0_CHFI_ONE 0x00000020U +#define LRFDMDM_RDCAPT0_CHFI_ZERO 0x00000000U + +// Field: [4] BDE2 +// +// Capture BDE2 output samples into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_BDE2 0x00000010U +#define LRFDMDM_RDCAPT0_BDE2_M 0x00000010U +#define LRFDMDM_RDCAPT0_BDE2_S 4U +#define LRFDMDM_RDCAPT0_BDE2_ONE 0x00000010U +#define LRFDMDM_RDCAPT0_BDE2_ZERO 0x00000000U + +// Field: [3] FIDC +// +// Capture FIDC output samples into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_FIDC 0x00000008U +#define LRFDMDM_RDCAPT0_FIDC_M 0x00000008U +#define LRFDMDM_RDCAPT0_FIDC_S 3U +#define LRFDMDM_RDCAPT0_FIDC_ONE 0x00000008U +#define LRFDMDM_RDCAPT0_FIDC_ZERO 0x00000000U + +// Field: [2] FRAC +// +// Capture FRAC output samples into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_FRAC 0x00000004U +#define LRFDMDM_RDCAPT0_FRAC_M 0x00000004U +#define LRFDMDM_RDCAPT0_FRAC_S 2U +#define LRFDMDM_RDCAPT0_FRAC_ONE 0x00000004U +#define LRFDMDM_RDCAPT0_FRAC_ZERO 0x00000000U + +// Field: [1] MGEX +// +// Capture MGE1 and MGE2 output values into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_MGEX 0x00000002U +#define LRFDMDM_RDCAPT0_MGEX_M 0x00000002U +#define LRFDMDM_RDCAPT0_MGEX_S 1U +#define LRFDMDM_RDCAPT0_MGEX_ONE 0x00000002U +#define LRFDMDM_RDCAPT0_MGEX_ZERO 0x00000000U + +// Field: [0] CODC +// +// Capture CODC output samples into FECAPT0 and FECAPT1. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT0_CODC 0x00000001U +#define LRFDMDM_RDCAPT0_CODC_M 0x00000001U +#define LRFDMDM_RDCAPT0_CODC_S 0U +#define LRFDMDM_RDCAPT0_CODC_ONE 0x00000001U +#define LRFDMDM_RDCAPT0_CODC_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RDCAPT1 +// +//***************************************************************************** +// Field: [11] C1BEX2 +// +// Capture C1BE B correlation peak x[n-1] value into DSCAPT0 RC register. +// Capture C1BE B correlation peak value into DSCAPT1 RC register. +// Capture C1BE B correlation peak x[n+1] value into DSCAPT2 RC register. +// Capture C1BE B qual value into DSCAPT3 RC register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_C1BEX2 0x00000800U +#define LRFDMDM_RDCAPT1_C1BEX2_M 0x00000800U +#define LRFDMDM_RDCAPT1_C1BEX2_S 11U +#define LRFDMDM_RDCAPT1_C1BEX2_ONE 0x00000800U +#define LRFDMDM_RDCAPT1_C1BEX2_ZERO 0x00000000U + +// Field: [10] C1BEX1 +// +// Capture C1BE A correlation peak x[n-1] value into DSCAPT0 RC register. +// Capture C1BE A correlation peak value into DSCAPT1 RC register. +// Capture C1BE A correlation peak x[n+1] value into DSCAPT2 RC register. +// Capture C1BE A qual value into DSCAPT3 RC register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_C1BEX1 0x00000400U +#define LRFDMDM_RDCAPT1_C1BEX1_M 0x00000400U +#define LRFDMDM_RDCAPT1_C1BEX1_S 10U +#define LRFDMDM_RDCAPT1_C1BEX1_ONE 0x00000400U +#define LRFDMDM_RDCAPT1_C1BEX1_ZERO 0x00000000U + +// Field: [9] C1BEX0 +// +// Capture C1BE A values into DSCAPT0 RC register +// Capture C1BE B values into DSCAPT1 RC register +// Capture C1BE C values into DSCAPT2 RC register +// Capture C1BE Corr Peak C into DSCAPT3 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_C1BEX0 0x00000200U +#define LRFDMDM_RDCAPT1_C1BEX0_M 0x00000200U +#define LRFDMDM_RDCAPT1_C1BEX0_S 9U +#define LRFDMDM_RDCAPT1_C1BEX0_ONE 0x00000200U +#define LRFDMDM_RDCAPT1_C1BEX0_ZERO 0x00000000U + +// Field: [8] SOFD +// +// Capture SOFD soft symbol into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_SOFD 0x00000100U +#define LRFDMDM_RDCAPT1_SOFD_M 0x00000100U +#define LRFDMDM_RDCAPT1_SOFD_S 8U +#define LRFDMDM_RDCAPT1_SOFD_ONE 0x00000100U +#define LRFDMDM_RDCAPT1_SOFD_ZERO 0x00000000U + +// Field: [7] LQIE +// +// Capture LQIE value into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_LQIE 0x00000080U +#define LRFDMDM_RDCAPT1_LQIE_M 0x00000080U +#define LRFDMDM_RDCAPT1_LQIE_S 7U +#define LRFDMDM_RDCAPT1_LQIE_ONE 0x00000080U +#define LRFDMDM_RDCAPT1_LQIE_ZERO 0x00000000U + +// Field: [6] STIM +// +// Capture STIM Events value into DSCAPT0 RC register bit 50. +// Capture STIM Delta value into DSCAPT1 RC register bit 3:0. +// Capture STIM Gardner Error(9:8) into DSCAPT1 RC register bit 7:6. +// Capture STIM Gardner Error(7:0) into DSCAPT2 RC register. +// Capture STIM output sample into DSCAPT3 RC register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_STIM 0x00000040U +#define LRFDMDM_RDCAPT1_STIM_M 0x00000040U +#define LRFDMDM_RDCAPT1_STIM_S 6U +#define LRFDMDM_RDCAPT1_STIM_ONE 0x00000040U +#define LRFDMDM_RDCAPT1_STIM_ZERO 0x00000000U + +// Field: [5] FIFE +// +// Capture FIFE sample into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_FIFE 0x00000020U +#define LRFDMDM_RDCAPT1_FIFE_M 0x00000020U +#define LRFDMDM_RDCAPT1_FIFE_S 5U +#define LRFDMDM_RDCAPT1_FIFE_ONE 0x00000020U +#define LRFDMDM_RDCAPT1_FIFE_ZERO 0x00000000U + +// Field: [4] PDIF +// +// Capture PDIF sample into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_PDIF 0x00000010U +#define LRFDMDM_RDCAPT1_PDIF_M 0x00000010U +#define LRFDMDM_RDCAPT1_PDIF_S 4U +#define LRFDMDM_RDCAPT1_PDIF_ONE 0x00000010U +#define LRFDMDM_RDCAPT1_PDIF_ZERO 0x00000000U + +// Field: [3] CA2P +// +// Capture CA2P sample into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_CA2P 0x00000008U +#define LRFDMDM_RDCAPT1_CA2P_M 0x00000008U +#define LRFDMDM_RDCAPT1_CA2P_S 3U +#define LRFDMDM_RDCAPT1_CA2P_ONE 0x00000008U +#define LRFDMDM_RDCAPT1_CA2P_ZERO 0x00000000U + +// Field: [2] MAFI +// +// Capture MAFI sample into DSCAPT0 RC register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_MAFI 0x00000004U +#define LRFDMDM_RDCAPT1_MAFI_M 0x00000004U +#define LRFDMDM_RDCAPT1_MAFI_S 2U +#define LRFDMDM_RDCAPT1_MAFI_ONE 0x00000004U +#define LRFDMDM_RDCAPT1_MAFI_ZERO 0x00000000U + +// Field: [1] DSBU +// +// Capture DSBU read pointer into DSCAPT0 register +// Capture DSBU write pointer into DSCAPT1 register +// Capture DSBU average value into DSCAPT2 register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_DSBU 0x00000002U +#define LRFDMDM_RDCAPT1_DSBU_M 0x00000002U +#define LRFDMDM_RDCAPT1_DSBU_S 1U +#define LRFDMDM_RDCAPT1_DSBU_ONE 0x00000002U +#define LRFDMDM_RDCAPT1_DSBU_ZERO 0x00000000U + +// Field: [0] MLSEBIT +// +// Capture MLSE bit into DSCAPT0 register +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_RDCAPT1_MLSEBIT 0x00000001U +#define LRFDMDM_RDCAPT1_MLSEBIT_M 0x00000001U +#define LRFDMDM_RDCAPT1_MLSEBIT_S 0U +#define LRFDMDM_RDCAPT1_MLSEBIT_ONE 0x00000001U +#define LRFDMDM_RDCAPT1_MLSEBIT_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FECAPT0 +// +//***************************************************************************** +// Field: [12:0] VAL +// +// Readback value, I channel +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_FECAPT0_VAL_W 13U +#define LRFDMDM_FECAPT0_VAL_M 0x00001FFFU +#define LRFDMDM_FECAPT0_VAL_S 0U +#define LRFDMDM_FECAPT0_VAL_ALLONES 0x00001FFFU +#define LRFDMDM_FECAPT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_FECAPT1 +// +//***************************************************************************** +// Field: [12:0] VAL +// +// Readback value, Q channel +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_FECAPT1_VAL_W 13U +#define LRFDMDM_FECAPT1_VAL_M 0x00001FFFU +#define LRFDMDM_FECAPT1_VAL_S 0U +#define LRFDMDM_FECAPT1_VAL_ALLONES 0x00001FFFU +#define LRFDMDM_FECAPT1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DSCAPT0 +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Readback channel 0 after writing to RDCAPT1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DSCAPT0_VAL_W 8U +#define LRFDMDM_DSCAPT0_VAL_M 0x000000FFU +#define LRFDMDM_DSCAPT0_VAL_S 0U +#define LRFDMDM_DSCAPT0_VAL_ALLONES 0x000000FFU +#define LRFDMDM_DSCAPT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DSCAPT1 +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Readback channel 1 after writing to RDCAPT1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DSCAPT1_VAL_W 8U +#define LRFDMDM_DSCAPT1_VAL_M 0x000000FFU +#define LRFDMDM_DSCAPT1_VAL_S 0U +#define LRFDMDM_DSCAPT1_VAL_ALLONES 0x000000FFU +#define LRFDMDM_DSCAPT1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DSCAPT2 +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Readback channel 2 after writing to RDCAPT1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DSCAPT2_VAL_W 8U +#define LRFDMDM_DSCAPT2_VAL_M 0x000000FFU +#define LRFDMDM_DSCAPT2_VAL_S 0U +#define LRFDMDM_DSCAPT2_VAL_ALLONES 0x000000FFU +#define LRFDMDM_DSCAPT2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DSCAPT3 +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Readback channel 3 after writing to RDCAPT1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DSCAPT3_VAL_W 8U +#define LRFDMDM_DSCAPT3_VAL_M 0x000000FFU +#define LRFDMDM_DSCAPT3_VAL_S 0U +#define LRFDMDM_DSCAPT3_VAL_ALLONES 0x000000FFU +#define LRFDMDM_DSCAPT3_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_DEMSWQU1 +// +//***************************************************************************** +// Field: [9:2] MAFCCOMPVAL +// +// Frequency Offset value computed by SWQU +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_W 8U +#define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_M 0x000003FCU +#define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_S 2U +#define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_ALLONES 0x000003FCU +#define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_ALLZEROS 0x00000000U + +// Field: [1] SWSEL +// +// Shows which sync word had a peak event and was selected for sync word +// qualification test. +// This is to tell which sync word was detected when radio operates in receive +// mode with dual sync word search. +// ENUMs: +// B The C1BE emitted a correlator B peak event and +// SWQU selected sync word B for qualification +// test +// A The C1BE emitted a correlator A peak event and +// SWQU selected sync word A for qualification +// test (or no SWQU sync word test has been +// performed yet) +#define LRFDMDM_DEMSWQU1_SWSEL 0x00000002U +#define LRFDMDM_DEMSWQU1_SWSEL_M 0x00000002U +#define LRFDMDM_DEMSWQU1_SWSEL_S 1U +#define LRFDMDM_DEMSWQU1_SWSEL_B 0x00000002U +#define LRFDMDM_DEMSWQU1_SWSEL_A 0x00000000U + +// Field: [0] SYNCED +// +// Reads as '1' when the sync word specified by DEMSWQU1.SWSEL has passed +// qualification, otherwise '0'. +// Note that the sync word qualification is only performed on MSB portion of +// the reference vector, +// as specified in DEMSWQU0.REFLEN register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_DEMSWQU1_SYNCED 0x00000001U +#define LRFDMDM_DEMSWQU1_SYNCED_M 0x00000001U +#define LRFDMDM_DEMSWQU1_SYNCED_S 0U +#define LRFDMDM_DEMSWQU1_SYNCED_ONE 0x00000001U +#define LRFDMDM_DEMSWQU1_SYNCED_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_GPOCTRL0 +// +//***************************************************************************** +// Field: [15:14] GPO7 +// +// Direct control of MCE_GPO(7) : +// 00 : FW source 7 +// 01: HW source 7 +// 10: HW source 15 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// TOPSM_WAIT Output hardware clk +// SW7 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO7_W 2U +#define LRFDMDM_GPOCTRL0_GPO7_M 0x0000C000U +#define LRFDMDM_GPOCTRL0_GPO7_S 14U +#define LRFDMDM_GPOCTRL0_GPO7_THREE 0x0000C000U +#define LRFDMDM_GPOCTRL0_GPO7_TWO 0x00008000U +#define LRFDMDM_GPOCTRL0_GPO7_TOPSM_WAIT 0x00004000U +#define LRFDMDM_GPOCTRL0_GPO7_SW7 0x00000000U + +// Field: [13:12] GPO6 +// +// Direct control of MCE_GPO(6) : +// 00 : FW source 6 +// 01: HW source 6 +// 10: HW source 14 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// TRANSPARENT_OUT The bit is 1 +// SW6 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO6_W 2U +#define LRFDMDM_GPOCTRL0_GPO6_M 0x00003000U +#define LRFDMDM_GPOCTRL0_GPO6_S 12U +#define LRFDMDM_GPOCTRL0_GPO6_THREE 0x00003000U +#define LRFDMDM_GPOCTRL0_GPO6_TWO 0x00002000U +#define LRFDMDM_GPOCTRL0_GPO6_TRANSPARENT_OUT 0x00001000U +#define LRFDMDM_GPOCTRL0_GPO6_SW6 0x00000000U + +// Field: [11:10] GPO5 +// +// Direct control of MCE_GPO(5) : +// 00 : FW source 5 +// 01: HW source 5 +// 10: HW source 13 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// DEM_OUT_WORD The bit is 1 +// SW5 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO5_W 2U +#define LRFDMDM_GPOCTRL0_GPO5_M 0x00000C00U +#define LRFDMDM_GPOCTRL0_GPO5_S 10U +#define LRFDMDM_GPOCTRL0_GPO5_THREE 0x00000C00U +#define LRFDMDM_GPOCTRL0_GPO5_TWO 0x00000800U +#define LRFDMDM_GPOCTRL0_GPO5_DEM_OUT_WORD 0x00000400U +#define LRFDMDM_GPOCTRL0_GPO5_SW5 0x00000000U + +// Field: [9:8] GPO4 +// +// Direct control of MCE_GPO(4) : +// 00 : FW source 4 +// 01: HW source 4 +// 10: HW source 12 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_C The bit is 1 +// SW4 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO4_W 2U +#define LRFDMDM_GPOCTRL0_GPO4_M 0x00000300U +#define LRFDMDM_GPOCTRL0_GPO4_S 8U +#define LRFDMDM_GPOCTRL0_GPO4_THREE 0x00000300U +#define LRFDMDM_GPOCTRL0_GPO4_TWO 0x00000200U +#define LRFDMDM_GPOCTRL0_GPO4_CORR_PEAK_C 0x00000100U +#define LRFDMDM_GPOCTRL0_GPO4_SW4 0x00000000U + +// Field: [7:6] GPO3 +// +// Direct control of MCE_GPO(3) : +// 00 : FW source 3 +// 01: HW source 3 +// 10: HW source 11 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_B The bit is 1 +// SW3 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO3_W 2U +#define LRFDMDM_GPOCTRL0_GPO3_M 0x000000C0U +#define LRFDMDM_GPOCTRL0_GPO3_S 6U +#define LRFDMDM_GPOCTRL0_GPO3_THREE 0x000000C0U +#define LRFDMDM_GPOCTRL0_GPO3_TWO 0x00000080U +#define LRFDMDM_GPOCTRL0_GPO3_CORR_PEAK_B 0x00000040U +#define LRFDMDM_GPOCTRL0_GPO3_SW3 0x00000000U + +// Field: [5:4] GPO2 +// +// Direct control of MCE_GPO(2) : +// 00 : FW source 2 +// 01: HW source 2 +// 10: HW source 10 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_A The bit is 1 +// SW2 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO2_W 2U +#define LRFDMDM_GPOCTRL0_GPO2_M 0x00000030U +#define LRFDMDM_GPOCTRL0_GPO2_S 4U +#define LRFDMDM_GPOCTRL0_GPO2_THREE 0x00000030U +#define LRFDMDM_GPOCTRL0_GPO2_TWO 0x00000020U +#define LRFDMDM_GPOCTRL0_GPO2_CORR_PEAK_A 0x00000010U +#define LRFDMDM_GPOCTRL0_GPO2_SW2 0x00000000U + +// Field: [3:2] GPO1 +// +// Direct control of MCE_GPO(1) : +// 00 : FW source 1 +// 01: HW source 1 +// 10: HW source 9 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// HWCLK1 Output Loopback symbol on pin MDMGPO1 +// SW1 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO1_W 2U +#define LRFDMDM_GPOCTRL0_GPO1_M 0x0000000CU +#define LRFDMDM_GPOCTRL0_GPO1_S 2U +#define LRFDMDM_GPOCTRL0_GPO1_THREE 0x0000000CU +#define LRFDMDM_GPOCTRL0_GPO1_TWO 0x00000008U +#define LRFDMDM_GPOCTRL0_GPO1_HWCLK1 0x00000004U +#define LRFDMDM_GPOCTRL0_GPO1_SW1 0x00000000U + +// Field: [1:0] GPO0 +// +// Direct control of MCE_GPO(0) : +// 00 : FW source 0 +// 01: HW source 0 +// 10: HW source 8 +// 11: Reserved +// ENUMs: +// THREE HW Source 3 +// LOOPBACK HW source 2 +// HWCLK0 Output hardware clock on pin MDMGPO0 +// SW0 Output GPOCTRL1.SW +#define LRFDMDM_GPOCTRL0_GPO0_W 2U +#define LRFDMDM_GPOCTRL0_GPO0_M 0x00000003U +#define LRFDMDM_GPOCTRL0_GPO0_S 0U +#define LRFDMDM_GPOCTRL0_GPO0_THREE 0x00000003U +#define LRFDMDM_GPOCTRL0_GPO0_LOOPBACK 0x00000002U +#define LRFDMDM_GPOCTRL0_GPO0_HWCLK0 0x00000001U +#define LRFDMDM_GPOCTRL0_GPO0_SW0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_GPOCTRL1 +// +//***************************************************************************** +// Field: [15:14] HWCLKSTRETCH +// +// Control strech for hwclk0 and hwclk1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_W 2U +#define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_M 0x0000C000U +#define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_S 14U +#define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_ONE 0x00004000U +#define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_ZERO 0x00000000U + +// Field: [13:11] HWCLKMUX1 +// +// Select clock source for hwclk1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_GPOCTRL1_HWCLKMUX1_W 3U +#define LRFDMDM_GPOCTRL1_HWCLKMUX1_M 0x00003800U +#define LRFDMDM_GPOCTRL1_HWCLKMUX1_S 11U +#define LRFDMDM_GPOCTRL1_HWCLKMUX1_ONE 0x00000800U +#define LRFDMDM_GPOCTRL1_HWCLKMUX1_ZERO 0x00000000U + +// Field: [10:8] HWCLKMUX0 +// +// Select clock source for hwclk0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_GPOCTRL1_HWCLKMUX0_W 3U +#define LRFDMDM_GPOCTRL1_HWCLKMUX0_M 0x00000700U +#define LRFDMDM_GPOCTRL1_HWCLKMUX0_S 8U +#define LRFDMDM_GPOCTRL1_HWCLKMUX0_ONE 0x00000100U +#define LRFDMDM_GPOCTRL1_HWCLKMUX0_ZERO 0x00000000U + +// Field: [7:0] SW +// +// Software controlled GPO +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM_GPOCTRL1_SW_W 8U +#define LRFDMDM_GPOCTRL1_SW_M 0x000000FFU +#define LRFDMDM_GPOCTRL1_SW_S 0U +#define LRFDMDM_GPOCTRL1_SW_ONE 0x00000001U +#define LRFDMDM_GPOCTRL1_SW_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFERSSI +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Current RSSI estimate +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFERSSI_VAL_W 8U +#define LRFDMDM_RFERSSI_VAL_M 0x000000FFU +#define LRFDMDM_RFERSSI_VAL_S 0U +#define LRFDMDM_RFERSSI_VAL_ALLONES 0x000000FFU +#define LRFDMDM_RFERSSI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFEMAXRSSI +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Highest RSSI since start of reception +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFEMAXRSSI_VAL_W 8U +#define LRFDMDM_RFEMAXRSSI_VAL_M 0x000000FFU +#define LRFDMDM_RFEMAXRSSI_VAL_S 0U +#define LRFDMDM_RFEMAXRSSI_VAL_ALLONES 0x000000FFU +#define LRFDMDM_RFEMAXRSSI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_RFEDBGAIN +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Current gain setting +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_RFEDBGAIN_VAL_W 8U +#define LRFDMDM_RFEDBGAIN_VAL_M 0x000000FFU +#define LRFDMDM_RFEDBGAIN_VAL_S 0U +#define LRFDMDM_RFEDBGAIN_VAL_ALLONES 0x000000FFU +#define LRFDMDM_RFEDBGAIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYNC0 +// +//***************************************************************************** +// Field: [15:0] SWA15C0 +// +// Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as +// most signicant bits of sync word A. +// The sync word is expected to be transmitted/received in LSB to MSB order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYNC0_SWA15C0_W 16U +#define LRFDMDM_SYNC0_SWA15C0_M 0x0000FFFFU +#define LRFDMDM_SYNC0_SWA15C0_S 0U +#define LRFDMDM_SYNC0_SWA15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_SYNC0_SWA15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYNC1 +// +//***************************************************************************** +// Field: [15:0] SWA31C16 +// +// Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word A. +// The sync word is expected to be transmitted/received in LSB to MSB order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYNC1_SWA31C16_W 16U +#define LRFDMDM_SYNC1_SWA31C16_M 0x0000FFFFU +#define LRFDMDM_SYNC1_SWA31C16_S 0U +#define LRFDMDM_SYNC1_SWA31C16_ALLONES 0x0000FFFFU +#define LRFDMDM_SYNC1_SWA31C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYNC2 +// +//***************************************************************************** +// Field: [15:0] SWB15C0 +// +// Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word B. +// The sync word is expected to be transmitted/received in LSB to MSB order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYNC2_SWB15C0_W 16U +#define LRFDMDM_SYNC2_SWB15C0_M 0x0000FFFFU +#define LRFDMDM_SYNC2_SWB15C0_S 0U +#define LRFDMDM_SYNC2_SWB15C0_ALLONES 0x0000FFFFU +#define LRFDMDM_SYNC2_SWB15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM_O_SYNC3 +// +//***************************************************************************** +// Field: [15:0] SWB31C16 +// +// Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word B. +// The sync word is expected to be transmitted/received in LSB to MSB order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM_SYNC3_SWB31C16_W 16U +#define LRFDMDM_SYNC3_SWB31C16_M 0x0000FFFFU +#define LRFDMDM_SYNC3_SWB31C16_S 0U +#define LRFDMDM_SYNC3_SWB31C16_ALLONES 0x0000FFFFU +#define LRFDMDM_SYNC3_SWB31C16_ALLZEROS 0x00000000U + + +#endif // __LRFDMDM__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm32.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm32.h new file mode 100644 index 00000000..cb54d8fe --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdmdm32.h @@ -0,0 +1,6027 @@ +/****************************************************************************** +* Filename: hw_lrfdmdm32_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDMDM32_H__ +#define __HW_LRFDMDM32_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDMDM32 component +// +//***************************************************************************** +// Modem Enable Register +#define LRFDMDM32_O_FWSRC_ENABLE 0x00000000U + +// Modem Initialize Register +#define LRFDMDM32_O_INIT 0x00000004U + +// Demodulator Enable Register 0 +#define LRFDMDM32_O_DEMENABLE1_DEMENABLE0 0x00000008U + +// Demodulator Initialize Register 0 +#define LRFDMDM32_O_DEMINIT1_DEMINIT0 0x0000000CU + +// Modem Command Engine (MCE) Strobe Register 0 +#define LRFDMDM32_O_STRB1_STRB0 0x00000010U + +// MCE Event Flag Register 0 +#define LRFDMDM32_O_EVT1_EVT0 0x00000014U + +// MCE Event Flag Register 2 +#define LRFDMDM32_O_EVT2 0x00000018U + +// MCE Event Mask Register 0 +#define LRFDMDM32_O_EVTMSK1_EVTMSK0 0x0000001CU + +// MCE Event Mask Register 2 +#define LRFDMDM32_O_EVTMSK2 0x00000020U + +// MCE Event Clear Register 0 +#define LRFDMDM32_O_EVTCLR1_EVTCLR0 0x00000024U + +// MCE Event Clear Register 2 +#define LRFDMDM32_O_EVTCLR2 0x00000028U + +// Modem Power Down Request Register +#define LRFDMDM32_O_API_PDREQ 0x0000002CU + +// Modem API Command Parameter 0 +#define LRFDMDM32_O_CMDPAR1_CMDPAR0 0x00000030U + +// Modem API Command Parameter 2 +#define LRFDMDM32_O_MSGBOX_CMDPAR2 0x00000034U + +// Frequency Offset +#define LRFDMDM32_O_FIFOWR_FREQ 0x00000038U + +// Modem FIFO Read Register +#define LRFDMDM32_O_FIFORD 0x0000003CU + +// Modem FIFO Write Configuration +#define LRFDMDM32_O_FIFORDCTRL_FIFOWRCTRL 0x00000040U + +// Modem FIFO Status Flags +#define LRFDMDM32_O_FIFOSTA 0x00000044U + +// MCE-to-RFE Send Data Register +#define LRFDMDM32_O_RFEDATIN0_RFEDATOUT0 0x00000048U + +// MCE-to-RFE Send Command Register +#define LRFDMDM32_O_RFECMDIN_RFECMDOUT 0x0000004CU + +// MCE-to-PBE Send Data Register +#define LRFDMDM32_O_PBEDATIN0_PBEDATOUT0 0x00000050U + +// MCE-to-PBE Send Command Register +#define LRFDMDM32_O_PBECMDIN_PBECMDOUT 0x00000054U + +// Link quality indicator +#define LRFDMDM32_O_PBEEVTMUX_LQIEST 0x00000058U + +// SYSTIME event mux 0 +#define LRFDMDM32_O_SYSTIMEVTMUX1_SYSTIMEVTMUX0 0x0000005CU + +// ADC Digital Interface Configuration +#define LRFDMDM32_O_MODPRECTRL_ADCDIGCONF 0x00000060U + +// Modulator Symbol Mapping Register 0 +#define LRFDMDM32_O_MODSYMMAP1_MODSYMMAP0 0x00000064U + +// Modulator Soft Symbol Transmit +#define LRFDMDM32_O_BAUD_MODSOFTTX 0x00000068U + +// Modem Baud Rate Prescaler Control +#define LRFDMDM32_O_MODMAIN_BAUDPRE 0x0000006CU + +// Demodulator Config Register 0 +#define LRFDMDM32_O_DEMMISC1_DEMMISC0 0x00000070U + +// Demodulator Config Register 2 +#define LRFDMDM32_O_DEMMISC3_DEMMISC2 0x00000074U + +// Demodulator I/Q Mismatch Compensation Register +#define LRFDMDM32_O_DEMDSBU_DEMIQMC0 0x00000078U + +// Demodulator Coarse DC Offset Estimator Register 0 +#define LRFDMDM32_O_DEMFIDC0_DEMCODC0 0x0000007CU + +// Demodulator Front-End Crossbar Register 0 +#define LRFDMDM32_O_DEMDSXB0_DEMFEXB0 0x00000080U + +// Demodulator Fine Frequency Offset Estimator Register 0 +#define LRFDMDM32_O_DEMMAFI0_DEMFIFE0 0x00000084U + +// Demodulator Matched Filter Register 1 +#define LRFDMDM32_O_DEMMAFI2_DEMMAFI1 0x00000088U + +// Demodulator Correlator 1-bit Engine Register 0 +#define LRFDMDM32_O_DEMC1BE1_DEMC1BE0 0x0000008CU + +// Demodulator Correlator 1-bit Engine Register 2 +#define LRFDMDM32_O_SPARE0_DEMC1BE2 0x00000090U + +// Modem Spare 1 +#define LRFDMDM32_O_SPARE2_SPARE1 0x00000094U + +// Modem Spare 3 +#define LRFDMDM32_O_DEMSWQU0_SPARE3 0x00000098U + +// Correlator reference register 0 +#define LRFDMDM32_O_DEMC1BEREF1_DEMC1BEREF0 0x0000009CU + +// Correlator reference register 2 +#define LRFDMDM32_O_DEMC1BEREF3_DEMC1BEREF2 0x000000A0U + +// Dynamic Modem Control Signals from MCE +#define LRFDMDM32_O_MODPREAMBLE_MODCTRL 0x000000A4U + +// Demodulator Fractional Resampler Register 0 +#define LRFDMDM32_O_DEMFRAC1_DEMFRAC0 0x000000A8U + +// Demodulator Fractional Resampler Register 2 +#define LRFDMDM32_O_DEMFRAC3_DEMFRAC2 0x000000ACU + +// Demodulator Coarse DC Offset Estimator Register 1 +#define LRFDMDM32_O_DEMCODC2_DEMCODC1 0x000000B0U + +// Demodulator Fine DC Offset Estimator Register 1 +#define LRFDMDM32_O_DEMFIDC2_DEMFIDC1 0x000000B4U + +// Demodulator Fine Frequency Offset Estimator Register 1 +#define LRFDMDM32_O_DEMMAFC0_DEMFIFE1 0x000000B8U + +// Demodulator Matched Filter Register 4 +#define LRFDMDM32_O_DEMSWIMBAL_DEMMAFI4 0x000000BCU + +// Demodulator Soft PDIFF Value Register +#define LRFDMDM32_O_DEMDEBUG_DEMSOFTPDIFF 0x000000C0U + +// Viterbi Control Register +#define LRFDMDM32_O_VITCOMPUTE_VITCTRL 0x000000C4U + +// Viterbi APM Readback Register +#define LRFDMDM32_O_VITSTATE_VITAPMRDBACK 0x000000C8U + +// Viterbi Branch Metric 1 and 0 Register +#define LRFDMDM32_O_VITBRMETRIC32_VITBRMETRIC10 0x000000CCU + +// Viterbi Branch Metric 5 and 4 Register +#define LRFDMDM32_O_VITBRMETRIC76_VITBRMETRIC54 0x000000D0U + +// Modem Timer and Counter Control Register +#define LRFDMDM32_O_TIMCTL 0x000000F0U + +// Modem Counter Increment Configuration +#define LRFDMDM32_O_TIMPER_TIMINC 0x000000F4U + +// Modem Counter Value +#define LRFDMDM32_O_TIMCAPT_TIMCNT 0x000000F8U + +// Modem Timebase Control Register +#define LRFDMDM32_O_COUNT1IN_TIMEBASE 0x000000FCU + +// Local Count Ones Result Register +#define LRFDMDM32_O_COUNT1RES 0x00000100U + +// Local Branch Metric Accelerator Module Register 1 +#define LRFDMDM32_O_BRMACC2_BRMACC1 0x00000104U + +// MCE Tracer Send Trigger Register +#define LRFDMDM32_O_MCETRCSTAT_MCETRCCTRL 0x00000108U + +// MCE Tracer Command Register +#define LRFDMDM32_O_MCETRCPAR0_MCETRCCMD 0x0000010CU + +// MCE Tracer Command Parameter Register 1 +#define LRFDMDM32_O_RDCAPT0_MCETRCPAR1 0x00000110U + +// Modem Readback Capture Register 1 +#define LRFDMDM32_O_FECAPT0_RDCAPT1 0x00000114U + +// Frontend capture readback register 1 +#define LRFDMDM32_O_DSCAPT0_FECAPT1 0x00000118U + +// Decoding stage capture register 1 +#define LRFDMDM32_O_DSCAPT2_DSCAPT1 0x0000011CU + +// Decoding stage capture register 3 +#define LRFDMDM32_O_DEMSWQU1_DSCAPT3 0x00000120U + +// Control of the MCE GPO signals +#define LRFDMDM32_O_GPOCTRL1_GPOCTRL0 0x00000124U + +// RFE received signal strength indicator +#define LRFDMDM32_O_RFEMAXRSSI_RFERSSI 0x00000128U + +// RFE front end gain setting +#define LRFDMDM32_O_SYNC0_RFEDBGAIN 0x0000012CU + +// Modem Sync Word Register 1 +#define LRFDMDM32_O_SYNC2_SYNC1 0x00000130U + +// Modem Sync Word Register 3 +#define LRFDMDM32_O_SYNC3 0x00000134U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FWSRC_ENABLE +// +//***************************************************************************** +// Field: [18] DATARAM +// +// ENUMs: +// S2RRAM Use S2RRAM for data +// MDMRAM Use MDMRAM for data +#define LRFDMDM32_FWSRC_ENABLE_DATARAM 0x00040000U +#define LRFDMDM32_FWSRC_ENABLE_DATARAM_M 0x00040000U +#define LRFDMDM32_FWSRC_ENABLE_DATARAM_S 18U +#define LRFDMDM32_FWSRC_ENABLE_DATARAM_S2RRAM 0x00040000U +#define LRFDMDM32_FWSRC_ENABLE_DATARAM_MDMRAM 0x00000000U + +// Field: [17] FWRAM +// +// ENUMs: +// S2RRAM Run code from S2RRAM +// MDMRAM Run code from MDMRAM +#define LRFDMDM32_FWSRC_ENABLE_FWRAM 0x00020000U +#define LRFDMDM32_FWSRC_ENABLE_FWRAM_M 0x00020000U +#define LRFDMDM32_FWSRC_ENABLE_FWRAM_S 17U +#define LRFDMDM32_FWSRC_ENABLE_FWRAM_S2RRAM 0x00020000U +#define LRFDMDM32_FWSRC_ENABLE_FWRAM_MDMRAM 0x00000000U + +// Field: [16] BANK +// +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDMDM32_FWSRC_ENABLE_BANK 0x00010000U +#define LRFDMDM32_FWSRC_ENABLE_BANK_M 0x00010000U +#define LRFDMDM32_FWSRC_ENABLE_BANK_S 16U +#define LRFDMDM32_FWSRC_ENABLE_BANK_ONE 0x00010000U +#define LRFDMDM32_FWSRC_ENABLE_BANK_ZERO 0x00000000U + +// Field: [5] ADCDIG +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_ADCDIG 0x00000020U +#define LRFDMDM32_FWSRC_ENABLE_ADCDIG_M 0x00000020U +#define LRFDMDM32_FWSRC_ENABLE_ADCDIG_S 5U +#define LRFDMDM32_FWSRC_ENABLE_ADCDIG_EN 0x00000020U +#define LRFDMDM32_FWSRC_ENABLE_ADCDIG_DIS 0x00000000U + +// Field: [4] DEMODULATOR +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_DEMODULATOR 0x00000010U +#define LRFDMDM32_FWSRC_ENABLE_DEMODULATOR_M 0x00000010U +#define LRFDMDM32_FWSRC_ENABLE_DEMODULATOR_S 4U +#define LRFDMDM32_FWSRC_ENABLE_DEMODULATOR_EN 0x00000010U +#define LRFDMDM32_FWSRC_ENABLE_DEMODULATOR_DIS 0x00000000U + +// Field: [3] MODULATOR +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_MODULATOR 0x00000008U +#define LRFDMDM32_FWSRC_ENABLE_MODULATOR_M 0x00000008U +#define LRFDMDM32_FWSRC_ENABLE_MODULATOR_S 3U +#define LRFDMDM32_FWSRC_ENABLE_MODULATOR_EN 0x00000008U +#define LRFDMDM32_FWSRC_ENABLE_MODULATOR_DIS 0x00000000U + +// Field: [2] TIMEBASE +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_TIMEBASE 0x00000004U +#define LRFDMDM32_FWSRC_ENABLE_TIMEBASE_M 0x00000004U +#define LRFDMDM32_FWSRC_ENABLE_TIMEBASE_S 2U +#define LRFDMDM32_FWSRC_ENABLE_TIMEBASE_EN 0x00000004U +#define LRFDMDM32_FWSRC_ENABLE_TIMEBASE_DIS 0x00000000U + +// Field: [1] TXRXFIFO +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_TXRXFIFO 0x00000002U +#define LRFDMDM32_FWSRC_ENABLE_TXRXFIFO_M 0x00000002U +#define LRFDMDM32_FWSRC_ENABLE_TXRXFIFO_S 1U +#define LRFDMDM32_FWSRC_ENABLE_TXRXFIFO_EN 0x00000002U +#define LRFDMDM32_FWSRC_ENABLE_TXRXFIFO_DIS 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDMDM32_FWSRC_ENABLE_TOPSM 0x00000001U +#define LRFDMDM32_FWSRC_ENABLE_TOPSM_M 0x00000001U +#define LRFDMDM32_FWSRC_ENABLE_TOPSM_S 0U +#define LRFDMDM32_FWSRC_ENABLE_TOPSM_EN 0x00000001U +#define LRFDMDM32_FWSRC_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_INIT +// +//***************************************************************************** +// Field: [5] ADCDIG +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_ADCDIG 0x00000020U +#define LRFDMDM32_INIT_ADCDIG_M 0x00000020U +#define LRFDMDM32_INIT_ADCDIG_S 5U +#define LRFDMDM32_INIT_ADCDIG_RESET 0x00000020U +#define LRFDMDM32_INIT_ADCDIG_NO_EFFECT 0x00000000U + +// Field: [4] DEMODULATOR +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_DEMODULATOR 0x00000010U +#define LRFDMDM32_INIT_DEMODULATOR_M 0x00000010U +#define LRFDMDM32_INIT_DEMODULATOR_S 4U +#define LRFDMDM32_INIT_DEMODULATOR_RESET 0x00000010U +#define LRFDMDM32_INIT_DEMODULATOR_NO_EFFECT 0x00000000U + +// Field: [3] MODULATOR +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_MODULATOR 0x00000008U +#define LRFDMDM32_INIT_MODULATOR_M 0x00000008U +#define LRFDMDM32_INIT_MODULATOR_S 3U +#define LRFDMDM32_INIT_MODULATOR_RESET 0x00000008U +#define LRFDMDM32_INIT_MODULATOR_NO_EFFECT 0x00000000U + +// Field: [2] TIMEBASE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_TIMEBASE 0x00000004U +#define LRFDMDM32_INIT_TIMEBASE_M 0x00000004U +#define LRFDMDM32_INIT_TIMEBASE_S 2U +#define LRFDMDM32_INIT_TIMEBASE_RESET 0x00000004U +#define LRFDMDM32_INIT_TIMEBASE_NO_EFFECT 0x00000000U + +// Field: [1] TXRXFIFO +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_TXRXFIFO 0x00000002U +#define LRFDMDM32_INIT_TXRXFIFO_M 0x00000002U +#define LRFDMDM32_INIT_TXRXFIFO_S 1U +#define LRFDMDM32_INIT_TXRXFIFO_RESET 0x00000002U +#define LRFDMDM32_INIT_TXRXFIFO_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_INIT_TOPSM 0x00000001U +#define LRFDMDM32_INIT_TOPSM_M 0x00000001U +#define LRFDMDM32_INIT_TOPSM_S 0U +#define LRFDMDM32_INIT_TOPSM_RESET 0x00000001U +#define LRFDMDM32_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMENABLE1_DEMENABLE0 +// +//***************************************************************************** +// Field: [29] VITE +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_VITE 0x20000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_VITE_M 0x20000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_VITE_S 29U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_VITE_EN 0x20000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_VITE_DIS 0x00000000U + +// Field: [28] MLSE +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MLSE 0x10000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MLSE_M 0x10000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MLSE_S 28U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MLSE_EN 0x10000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MLSE_DIS 0x00000000U + +// Field: [27] SOFD +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SOFD 0x08000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SOFD_M 0x08000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SOFD_S 27U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SOFD_EN 0x08000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SOFD_DIS 0x00000000U + +// Field: [26] SWQU +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SWQU 0x04000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SWQU_M 0x04000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SWQU_S 26U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SWQU_EN 0x04000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_SWQU_DIS 0x00000000U + +// Field: [25] MAFC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFC 0x02000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFC_M 0x02000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFC_S 25U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFC_EN 0x02000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFC_DIS 0x00000000U + +// Field: [24] MAFI +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFI 0x01000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFI_M 0x01000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFI_S 24U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFI_EN 0x01000000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MAFI_DIS 0x00000000U + +// Field: [23] FIFE +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIFE 0x00800000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIFE_M 0x00800000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIFE_S 23U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIFE_EN 0x00800000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIFE_DIS 0x00000000U + +// Field: [22] PDIF +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_PDIF 0x00400000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_PDIF_M 0x00400000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_PDIF_S 22U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_PDIF_EN 0x00400000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_PDIF_DIS 0x00000000U + +// Field: [21] CA2P +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CA2P 0x00200000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CA2P_M 0x00200000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CA2P_S 21U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CA2P_EN 0x00200000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CA2P_DIS 0x00000000U + +// Field: [20] C1BE +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_C1BE 0x00100000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_C1BE_M 0x00100000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_C1BE_S 20U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_C1BE_EN 0x00100000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_C1BE_DIS 0x00000000U + +// Field: [19] LQIE +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_LQIE 0x00080000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_LQIE_M 0x00080000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_LQIE_S 19U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_LQIE_EN 0x00080000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_LQIE_DIS 0x00000000U + +// Field: [18] F4BA +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_F4BA 0x00040000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_F4BA_M 0x00040000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_F4BA_S 18U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_F4BA_EN 0x00040000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_F4BA_DIS 0x00000000U + +// Field: [17] STIM +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_STIM 0x00020000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_STIM_M 0x00020000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_STIM_S 17U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_STIM_EN 0x00020000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_STIM_DIS 0x00000000U + +// Field: [16] DSBU +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_DSBU 0x00010000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_DSBU_M 0x00010000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_DSBU_S 16U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_DSBU_EN 0x00010000U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_DSBU_DIS 0x00000000U + +// Field: [8] FRAC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FRAC 0x00000100U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FRAC_M 0x00000100U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FRAC_S 8U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FRAC_EN 0x00000100U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FRAC_DIS 0x00000000U + +// Field: [7] FIDC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIDC 0x00000080U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIDC_M 0x00000080U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIDC_S 7U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIDC_EN 0x00000080U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_FIDC_DIS 0x00000000U + +// Field: [6] CHFI +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CHFI 0x00000040U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CHFI_M 0x00000040U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CHFI_S 6U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CHFI_EN 0x00000040U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CHFI_DIS 0x00000000U + +// Field: [5] BDEC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_BDEC 0x00000020U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_BDEC_M 0x00000020U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_BDEC_S 5U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_BDEC_EN 0x00000020U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_BDEC_DIS 0x00000000U + +// Field: [4] IQMC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_IQMC 0x00000010U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_IQMC_M 0x00000010U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_IQMC_S 4U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_IQMC_EN 0x00000010U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_IQMC_DIS 0x00000000U + +// Field: [3] MGE1 +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE1 0x00000008U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE1_M 0x00000008U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE1_S 3U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE1_EN 0x00000008U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE1_DIS 0x00000000U + +// Field: [2] MGE0 +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE0 0x00000004U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE0_M 0x00000004U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE0_S 2U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE0_EN 0x00000004U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_MGE0_DIS 0x00000000U + +// Field: [1] CODC +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CODC 0x00000002U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CODC_M 0x00000002U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CODC_S 1U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CODC_EN 0x00000002U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CODC_DIS 0x00000000U + +// Field: [0] CMIX +// +// ENUMs: +// EN Enable module +// DIS Disable +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CMIX 0x00000001U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CMIX_M 0x00000001U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CMIX_S 0U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CMIX_EN 0x00000001U +#define LRFDMDM32_DEMENABLE1_DEMENABLE0_CMIX_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMINIT1_DEMINIT0 +// +//***************************************************************************** +// Field: [29] VITE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_VITE 0x20000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_VITE_M 0x20000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_VITE_S 29U +#define LRFDMDM32_DEMINIT1_DEMINIT0_VITE_RESET 0x20000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_VITE_NO_EFFECT 0x00000000U + +// Field: [28] MLSE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_MLSE 0x10000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MLSE_M 0x10000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MLSE_S 28U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MLSE_RESET 0x10000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MLSE_NO_EFFECT 0x00000000U + +// Field: [27] SOFD +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_SOFD 0x08000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SOFD_M 0x08000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SOFD_S 27U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SOFD_RESET 0x08000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SOFD_NO_EFFECT 0x00000000U + +// Field: [26] SWQU +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_SWQU 0x04000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SWQU_M 0x04000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SWQU_S 26U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SWQU_RESET 0x04000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_SWQU_NO_EFFECT 0x00000000U + +// Field: [25] MAFC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFC 0x02000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFC_M 0x02000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFC_S 25U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFC_RESET 0x02000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFC_NO_EFFECT 0x00000000U + +// Field: [24] MAFI +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFI 0x01000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFI_M 0x01000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFI_S 24U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFI_RESET 0x01000000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MAFI_NO_EFFECT 0x00000000U + +// Field: [23] FIFE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIFE 0x00800000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIFE_M 0x00800000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIFE_S 23U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIFE_RESET 0x00800000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIFE_NO_EFFECT 0x00000000U + +// Field: [22] PDIF +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_PDIF 0x00400000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_PDIF_M 0x00400000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_PDIF_S 22U +#define LRFDMDM32_DEMINIT1_DEMINIT0_PDIF_RESET 0x00400000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_PDIF_NO_EFFECT 0x00000000U + +// Field: [21] CA2P +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_CA2P 0x00200000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CA2P_M 0x00200000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CA2P_S 21U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CA2P_RESET 0x00200000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CA2P_NO_EFFECT 0x00000000U + +// Field: [20] C1BE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_C1BE 0x00100000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_C1BE_M 0x00100000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_C1BE_S 20U +#define LRFDMDM32_DEMINIT1_DEMINIT0_C1BE_RESET 0x00100000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_C1BE_NO_EFFECT 0x00000000U + +// Field: [19] LQIE +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_LQIE 0x00080000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_LQIE_M 0x00080000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_LQIE_S 19U +#define LRFDMDM32_DEMINIT1_DEMINIT0_LQIE_RESET 0x00080000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_LQIE_NO_EFFECT 0x00000000U + +// Field: [18] F4BA +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_F4BA 0x00040000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_F4BA_M 0x00040000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_F4BA_S 18U +#define LRFDMDM32_DEMINIT1_DEMINIT0_F4BA_RESET 0x00040000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_F4BA_NO_EFFECT 0x00000000U + +// Field: [17] STIM +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_STIM 0x00020000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_STIM_M 0x00020000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_STIM_S 17U +#define LRFDMDM32_DEMINIT1_DEMINIT0_STIM_RESET 0x00020000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_STIM_NO_EFFECT 0x00000000U + +// Field: [16] DSBU +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_DSBU 0x00010000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_DSBU_M 0x00010000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_DSBU_S 16U +#define LRFDMDM32_DEMINIT1_DEMINIT0_DSBU_RESET 0x00010000U +#define LRFDMDM32_DEMINIT1_DEMINIT0_DSBU_NO_EFFECT 0x00000000U + +// Field: [8] FRAC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_FRAC 0x00000100U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FRAC_M 0x00000100U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FRAC_S 8U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FRAC_RESET 0x00000100U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FRAC_NO_EFFECT 0x00000000U + +// Field: [7] FIDC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIDC 0x00000080U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIDC_M 0x00000080U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIDC_S 7U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIDC_RESET 0x00000080U +#define LRFDMDM32_DEMINIT1_DEMINIT0_FIDC_NO_EFFECT 0x00000000U + +// Field: [6] CHFI +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_CHFI 0x00000040U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CHFI_M 0x00000040U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CHFI_S 6U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CHFI_RESET 0x00000040U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CHFI_NO_EFFECT 0x00000000U + +// Field: [5] BDEC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_BDEC 0x00000020U +#define LRFDMDM32_DEMINIT1_DEMINIT0_BDEC_M 0x00000020U +#define LRFDMDM32_DEMINIT1_DEMINIT0_BDEC_S 5U +#define LRFDMDM32_DEMINIT1_DEMINIT0_BDEC_RESET 0x00000020U +#define LRFDMDM32_DEMINIT1_DEMINIT0_BDEC_NO_EFFECT 0x00000000U + +// Field: [4] IQMC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_IQMC 0x00000010U +#define LRFDMDM32_DEMINIT1_DEMINIT0_IQMC_M 0x00000010U +#define LRFDMDM32_DEMINIT1_DEMINIT0_IQMC_S 4U +#define LRFDMDM32_DEMINIT1_DEMINIT0_IQMC_RESET 0x00000010U +#define LRFDMDM32_DEMINIT1_DEMINIT0_IQMC_NO_EFFECT 0x00000000U + +// Field: [3] MGE1 +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE1 0x00000008U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE1_M 0x00000008U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE1_S 3U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE1_RESET 0x00000008U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE1_NO_EFFECT 0x00000000U + +// Field: [2] MGE0 +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE0 0x00000004U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE0_M 0x00000004U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE0_S 2U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE0_RESET 0x00000004U +#define LRFDMDM32_DEMINIT1_DEMINIT0_MGE0_NO_EFFECT 0x00000000U + +// Field: [1] CODC +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_CODC 0x00000002U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CODC_M 0x00000002U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CODC_S 1U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CODC_RESET 0x00000002U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CODC_NO_EFFECT 0x00000000U + +// Field: [0] CMIX +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDMDM32_DEMINIT1_DEMINIT0_CMIX 0x00000001U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CMIX_M 0x00000001U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CMIX_S 0U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CMIX_RESET 0x00000001U +#define LRFDMDM32_DEMINIT1_DEMINIT0_CMIX_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_STRB1_STRB0 +// +//***************************************************************************** +// Field: [29] S2RTRG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_S2RTRG 0x20000000U +#define LRFDMDM32_STRB1_STRB0_S2RTRG_M 0x20000000U +#define LRFDMDM32_STRB1_STRB0_S2RTRG_S 29U +#define LRFDMDM32_STRB1_STRB0_S2RTRG_ONE 0x20000000U +#define LRFDMDM32_STRB1_STRB0_S2RTRG_ZERO 0x00000000U + +// Field: [28] DMATRG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_DMATRG 0x10000000U +#define LRFDMDM32_STRB1_STRB0_DMATRG_M 0x10000000U +#define LRFDMDM32_STRB1_STRB0_DMATRG_S 28U +#define LRFDMDM32_STRB1_STRB0_DMATRG_ONE 0x10000000U +#define LRFDMDM32_STRB1_STRB0_DMATRG_ZERO 0x00000000U + +// Field: [27] SYSTCAPT2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT2 0x08000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT2_M 0x08000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT2_S 27U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT2_ONE 0x08000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT2_ZERO 0x00000000U + +// Field: [26] SYSTCAPT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT1 0x04000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT1_M 0x04000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT1_S 26U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT1_ONE 0x04000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT1_ZERO 0x00000000U + +// Field: [25] SYSTCAPT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT0 0x02000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT0_M 0x02000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT0_S 25U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT0_ONE 0x02000000U +#define LRFDMDM32_STRB1_STRB0_SYSTCAPT0_ZERO 0x00000000U + +// Field: [24] C1BEPEAKAB +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKAB 0x01000000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKAB_M 0x01000000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKAB_S 24U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKAB_ONE 0x01000000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKAB_ZERO 0x00000000U + +// Field: [23] C1BEPEAKC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKC 0x00800000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKC_M 0x00800000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKC_S 23U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKC_ONE 0x00800000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKC_ZERO 0x00000000U + +// Field: [22] C1BEPEAKB +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKB 0x00400000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKB_M 0x00400000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKB_S 22U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKB_ONE 0x00400000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKB_ZERO 0x00000000U + +// Field: [21] C1BEPEAKA +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKA 0x00200000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKA_M 0x00200000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKA_S 21U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKA_ONE 0x00200000U +#define LRFDMDM32_STRB1_STRB0_C1BEPEAKA_ZERO 0x00000000U + +// Field: [20] C1BEADVANCE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BEADVANCE 0x00100000U +#define LRFDMDM32_STRB1_STRB0_C1BEADVANCE_M 0x00100000U +#define LRFDMDM32_STRB1_STRB0_C1BEADVANCE_S 20U +#define LRFDMDM32_STRB1_STRB0_C1BEADVANCE_ONE 0x00100000U +#define LRFDMDM32_STRB1_STRB0_C1BEADVANCE_ZERO 0x00000000U + +// Field: [19] C1BESTALL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BESTALL 0x00080000U +#define LRFDMDM32_STRB1_STRB0_C1BESTALL_M 0x00080000U +#define LRFDMDM32_STRB1_STRB0_C1BESTALL_S 19U +#define LRFDMDM32_STRB1_STRB0_C1BESTALL_ONE 0x00080000U +#define LRFDMDM32_STRB1_STRB0_C1BESTALL_ZERO 0x00000000U + +// Field: [18:17] C1BEROT +// +// ENUMs: +// ROT16R Rotate 16 samples to the right +// ROT1L Rotate 1 sample to the left +// ROT1R Rotate 1 sample to the right +// ROT0 No additional rotation (normal shift-right mode) +#define LRFDMDM32_STRB1_STRB0_C1BEROT_W 2U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_M 0x00060000U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_S 17U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_ROT16R 0x00060000U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_ROT1L 0x00040000U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_ROT1R 0x00020000U +#define LRFDMDM32_STRB1_STRB0_C1BEROT_ROT0 0x00000000U + +// Field: [16] C1BECOPY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_C1BECOPY 0x00010000U +#define LRFDMDM32_STRB1_STRB0_C1BECOPY_M 0x00010000U +#define LRFDMDM32_STRB1_STRB0_C1BECOPY_S 16U +#define LRFDMDM32_STRB1_STRB0_C1BECOPY_ONE 0x00010000U +#define LRFDMDM32_STRB1_STRB0_C1BECOPY_ZERO 0x00000000U + +// Field: [11] TIMBADVANCE +// +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM32_STRB1_STRB0_TIMBADVANCE 0x00000800U +#define LRFDMDM32_STRB1_STRB0_TIMBADVANCE_M 0x00000800U +#define LRFDMDM32_STRB1_STRB0_TIMBADVANCE_S 11U +#define LRFDMDM32_STRB1_STRB0_TIMBADVANCE_ON 0x00000800U +#define LRFDMDM32_STRB1_STRB0_TIMBADVANCE_NO_EFFECT 0x00000000U + +// Field: [10] TIMBSTALL +// +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM32_STRB1_STRB0_TIMBSTALL 0x00000400U +#define LRFDMDM32_STRB1_STRB0_TIMBSTALL_M 0x00000400U +#define LRFDMDM32_STRB1_STRB0_TIMBSTALL_S 10U +#define LRFDMDM32_STRB1_STRB0_TIMBSTALL_ON 0x00000400U +#define LRFDMDM32_STRB1_STRB0_TIMBSTALL_NO_EFFECT 0x00000000U + +// Field: [9] EVT5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT5 0x00000200U +#define LRFDMDM32_STRB1_STRB0_EVT5_M 0x00000200U +#define LRFDMDM32_STRB1_STRB0_EVT5_S 9U +#define LRFDMDM32_STRB1_STRB0_EVT5_ONE 0x00000200U +#define LRFDMDM32_STRB1_STRB0_EVT5_ZERO 0x00000000U + +// Field: [8] EVT4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT4 0x00000100U +#define LRFDMDM32_STRB1_STRB0_EVT4_M 0x00000100U +#define LRFDMDM32_STRB1_STRB0_EVT4_S 8U +#define LRFDMDM32_STRB1_STRB0_EVT4_ONE 0x00000100U +#define LRFDMDM32_STRB1_STRB0_EVT4_ZERO 0x00000000U + +// Field: [7] MLSETERM +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_STRB1_STRB0_MLSETERM 0x00000080U +#define LRFDMDM32_STRB1_STRB0_MLSETERM_M 0x00000080U +#define LRFDMDM32_STRB1_STRB0_MLSETERM_S 7U +#define LRFDMDM32_STRB1_STRB0_MLSETERM_ON 0x00000080U +#define LRFDMDM32_STRB1_STRB0_MLSETERM_OFF 0x00000000U + +// Field: [6] EVT3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT3 0x00000040U +#define LRFDMDM32_STRB1_STRB0_EVT3_M 0x00000040U +#define LRFDMDM32_STRB1_STRB0_EVT3_S 6U +#define LRFDMDM32_STRB1_STRB0_EVT3_ONE 0x00000040U +#define LRFDMDM32_STRB1_STRB0_EVT3_ZERO 0x00000000U + +// Field: [5] EVT2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT2 0x00000020U +#define LRFDMDM32_STRB1_STRB0_EVT2_M 0x00000020U +#define LRFDMDM32_STRB1_STRB0_EVT2_S 5U +#define LRFDMDM32_STRB1_STRB0_EVT2_ONE 0x00000020U +#define LRFDMDM32_STRB1_STRB0_EVT2_ZERO 0x00000000U + +// Field: [4] EVT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT1 0x00000010U +#define LRFDMDM32_STRB1_STRB0_EVT1_M 0x00000010U +#define LRFDMDM32_STRB1_STRB0_EVT1_S 4U +#define LRFDMDM32_STRB1_STRB0_EVT1_ONE 0x00000010U +#define LRFDMDM32_STRB1_STRB0_EVT1_ZERO 0x00000000U + +// Field: [3] EVT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_EVT0 0x00000008U +#define LRFDMDM32_STRB1_STRB0_EVT0_M 0x00000008U +#define LRFDMDM32_STRB1_STRB0_EVT0_S 3U +#define LRFDMDM32_STRB1_STRB0_EVT0_ONE 0x00000008U +#define LRFDMDM32_STRB1_STRB0_EVT0_ZERO 0x00000000U + +// Field: [2] TIMBALIGN +// +// ENUMs: +// ON The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDMDM32_STRB1_STRB0_TIMBALIGN 0x00000004U +#define LRFDMDM32_STRB1_STRB0_TIMBALIGN_M 0x00000004U +#define LRFDMDM32_STRB1_STRB0_TIMBALIGN_S 2U +#define LRFDMDM32_STRB1_STRB0_TIMBALIGN_ON 0x00000004U +#define LRFDMDM32_STRB1_STRB0_TIMBALIGN_NO_EFFECT 0x00000000U + +// Field: [1] DSBURST +// +// ENUMs: +// RESTART Restart module +// NO_EFFECT No effect +#define LRFDMDM32_STRB1_STRB0_DSBURST 0x00000002U +#define LRFDMDM32_STRB1_STRB0_DSBURST_M 0x00000002U +#define LRFDMDM32_STRB1_STRB0_DSBURST_S 1U +#define LRFDMDM32_STRB1_STRB0_DSBURST_RESTART 0x00000002U +#define LRFDMDM32_STRB1_STRB0_DSBURST_NO_EFFECT 0x00000000U + +// Field: [0] CMDDONE +// +// ENUMs: +// YES The bit is 1 +// NO The bit is 0 +#define LRFDMDM32_STRB1_STRB0_CMDDONE 0x00000001U +#define LRFDMDM32_STRB1_STRB0_CMDDONE_M 0x00000001U +#define LRFDMDM32_STRB1_STRB0_CMDDONE_S 0U +#define LRFDMDM32_STRB1_STRB0_CMDDONE_YES 0x00000001U +#define LRFDMDM32_STRB1_STRB0_CMDDONE_NO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVT1_EVT0 +// +//***************************************************************************** +// Field: [24] REFCLK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_REFCLK 0x01000000U +#define LRFDMDM32_EVT1_EVT0_REFCLK_M 0x01000000U +#define LRFDMDM32_EVT1_EVT0_REFCLK_S 24U +#define LRFDMDM32_EVT1_EVT0_REFCLK_ONE 0x01000000U +#define LRFDMDM32_EVT1_EVT0_REFCLK_ZERO 0x00000000U + +// Field: [23] S2RSTOP +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_S2RSTOP 0x00800000U +#define LRFDMDM32_EVT1_EVT0_S2RSTOP_M 0x00800000U +#define LRFDMDM32_EVT1_EVT0_S2RSTOP_S 23U +#define LRFDMDM32_EVT1_EVT0_S2RSTOP_ONE 0x00800000U +#define LRFDMDM32_EVT1_EVT0_S2RSTOP_ZERO 0x00000000U + +// Field: [22] SWQUFALSESYNC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_SWQUFALSESYNC 0x00400000U +#define LRFDMDM32_EVT1_EVT0_SWQUFALSESYNC_M 0x00400000U +#define LRFDMDM32_EVT1_EVT0_SWQUFALSESYNC_S 22U +#define LRFDMDM32_EVT1_EVT0_SWQUFALSESYNC_ONE 0x00400000U +#define LRFDMDM32_EVT1_EVT0_SWQUFALSESYNC_ZERO 0x00000000U + +// Field: [21] SWQUSYNCED +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_SWQUSYNCED 0x00200000U +#define LRFDMDM32_EVT1_EVT0_SWQUSYNCED_M 0x00200000U +#define LRFDMDM32_EVT1_EVT0_SWQUSYNCED_S 21U +#define LRFDMDM32_EVT1_EVT0_SWQUSYNCED_ONE 0x00200000U +#define LRFDMDM32_EVT1_EVT0_SWQUSYNCED_ZERO 0x00000000U + +// Field: [20] CLKENBAUDF +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_CLKENBAUDF 0x00100000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUDF_M 0x00100000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUDF_S 20U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUDF_ONE 0x00100000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUDF_ZERO 0x00000000U + +// Field: [19] FIFORVALID +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FIFORVALID 0x00080000U +#define LRFDMDM32_EVT1_EVT0_FIFORVALID_M 0x00080000U +#define LRFDMDM32_EVT1_EVT0_FIFORVALID_S 19U +#define LRFDMDM32_EVT1_EVT0_FIFORVALID_ONE 0x00080000U +#define LRFDMDM32_EVT1_EVT0_FIFORVALID_ZERO 0x00000000U + +// Field: [18] FIFOWREADY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FIFOWREADY 0x00040000U +#define LRFDMDM32_EVT1_EVT0_FIFOWREADY_M 0x00040000U +#define LRFDMDM32_EVT1_EVT0_FIFOWREADY_S 18U +#define LRFDMDM32_EVT1_EVT0_FIFOWREADY_ONE 0x00040000U +#define LRFDMDM32_EVT1_EVT0_FIFOWREADY_ZERO 0x00000000U + +// Field: [17] CLKENBAUD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_CLKENBAUD 0x00020000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUD_M 0x00020000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUD_S 17U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUD_ONE 0x00020000U +#define LRFDMDM32_EVT1_EVT0_CLKENBAUD_ZERO 0x00000000U + +// Field: [16] PREAMBLEDONE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_PREAMBLEDONE 0x00010000U +#define LRFDMDM32_EVT1_EVT0_PREAMBLEDONE_M 0x00010000U +#define LRFDMDM32_EVT1_EVT0_PREAMBLEDONE_S 16U +#define LRFDMDM32_EVT1_EVT0_PREAMBLEDONE_ONE 0x00010000U +#define LRFDMDM32_EVT1_EVT0_PREAMBLEDONE_ZERO 0x00000000U + +// Field: [15] PBEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_PBEDAT 0x00008000U +#define LRFDMDM32_EVT1_EVT0_PBEDAT_M 0x00008000U +#define LRFDMDM32_EVT1_EVT0_PBEDAT_S 15U +#define LRFDMDM32_EVT1_EVT0_PBEDAT_ONE 0x00008000U +#define LRFDMDM32_EVT1_EVT0_PBEDAT_ZERO 0x00000000U + +// Field: [14] PBECMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_PBECMD 0x00004000U +#define LRFDMDM32_EVT1_EVT0_PBECMD_M 0x00004000U +#define LRFDMDM32_EVT1_EVT0_PBECMD_S 14U +#define LRFDMDM32_EVT1_EVT0_PBECMD_ONE 0x00004000U +#define LRFDMDM32_EVT1_EVT0_PBECMD_ZERO 0x00000000U + +// Field: [13] RFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_RFEDAT 0x00002000U +#define LRFDMDM32_EVT1_EVT0_RFEDAT_M 0x00002000U +#define LRFDMDM32_EVT1_EVT0_RFEDAT_S 13U +#define LRFDMDM32_EVT1_EVT0_RFEDAT_ONE 0x00002000U +#define LRFDMDM32_EVT1_EVT0_RFEDAT_ZERO 0x00000000U + +// Field: [12] BDEC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_BDEC 0x00001000U +#define LRFDMDM32_EVT1_EVT0_BDEC_M 0x00001000U +#define LRFDMDM32_EVT1_EVT0_BDEC_S 12U +#define LRFDMDM32_EVT1_EVT0_BDEC_ONE 0x00001000U +#define LRFDMDM32_EVT1_EVT0_BDEC_ZERO 0x00000000U + +// Field: [11] FRAC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FRAC 0x00000800U +#define LRFDMDM32_EVT1_EVT0_FRAC_M 0x00000800U +#define LRFDMDM32_EVT1_EVT0_FRAC_S 11U +#define LRFDMDM32_EVT1_EVT0_FRAC_ONE 0x00000800U +#define LRFDMDM32_EVT1_EVT0_FRAC_ZERO 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT2 0x00000400U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT2_S 10U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT2_ONE 0x00000400U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT2_ZERO 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT1 0x00000200U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT1_S 9U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT1_ONE 0x00000200U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT1_ZERO 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT0 0x00000100U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT0_S 8U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT0_ONE 0x00000100U +#define LRFDMDM32_EVT1_EVT0_SYSTIMEVT0_ZERO 0x00000000U + +// Field: [7] FIFOWR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FIFOWR 0x00000080U +#define LRFDMDM32_EVT1_EVT0_FIFOWR_M 0x00000080U +#define LRFDMDM32_EVT1_EVT0_FIFOWR_S 7U +#define LRFDMDM32_EVT1_EVT0_FIFOWR_ONE 0x00000080U +#define LRFDMDM32_EVT1_EVT0_FIFOWR_ZERO 0x00000000U + +// Field: [6] COUNTER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_COUNTER 0x00000040U +#define LRFDMDM32_EVT1_EVT0_COUNTER_M 0x00000040U +#define LRFDMDM32_EVT1_EVT0_COUNTER_S 6U +#define LRFDMDM32_EVT1_EVT0_COUNTER_ONE 0x00000040U +#define LRFDMDM32_EVT1_EVT0_COUNTER_ZERO 0x00000000U + +// Field: [5] RFECMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_RFECMD 0x00000020U +#define LRFDMDM32_EVT1_EVT0_RFECMD_M 0x00000020U +#define LRFDMDM32_EVT1_EVT0_RFECMD_S 5U +#define LRFDMDM32_EVT1_EVT0_RFECMD_ONE 0x00000020U +#define LRFDMDM32_EVT1_EVT0_RFECMD_ZERO 0x00000000U + +// Field: [4] FIFOOVFL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FIFOOVFL 0x00000010U +#define LRFDMDM32_EVT1_EVT0_FIFOOVFL_M 0x00000010U +#define LRFDMDM32_EVT1_EVT0_FIFOOVFL_S 4U +#define LRFDMDM32_EVT1_EVT0_FIFOOVFL_ONE 0x00000010U +#define LRFDMDM32_EVT1_EVT0_FIFOOVFL_ZERO 0x00000000U + +// Field: [3] FIFOUNFL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_FIFOUNFL 0x00000008U +#define LRFDMDM32_EVT1_EVT0_FIFOUNFL_M 0x00000008U +#define LRFDMDM32_EVT1_EVT0_FIFOUNFL_S 3U +#define LRFDMDM32_EVT1_EVT0_FIFOUNFL_ONE 0x00000008U +#define LRFDMDM32_EVT1_EVT0_FIFOUNFL_ZERO 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_CLKEN4BAUD 0x00000004U +#define LRFDMDM32_EVT1_EVT0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM32_EVT1_EVT0_CLKEN4BAUD_S 2U +#define LRFDMDM32_EVT1_EVT0_CLKEN4BAUD_ONE 0x00000004U +#define LRFDMDM32_EVT1_EVT0_CLKEN4BAUD_ZERO 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_TIMER 0x00000002U +#define LRFDMDM32_EVT1_EVT0_TIMER_M 0x00000002U +#define LRFDMDM32_EVT1_EVT0_TIMER_S 1U +#define LRFDMDM32_EVT1_EVT0_TIMER_ONE 0x00000002U +#define LRFDMDM32_EVT1_EVT0_TIMER_ZERO 0x00000000U + +// Field: [0] MDMAPI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT1_EVT0_MDMAPI 0x00000001U +#define LRFDMDM32_EVT1_EVT0_MDMAPI_M 0x00000001U +#define LRFDMDM32_EVT1_EVT0_MDMAPI_S 0U +#define LRFDMDM32_EVT1_EVT0_MDMAPI_ONE 0x00000001U +#define LRFDMDM32_EVT1_EVT0_MDMAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVT2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_GPI1 0x00008000U +#define LRFDMDM32_EVT2_GPI1_M 0x00008000U +#define LRFDMDM32_EVT2_GPI1_S 15U +#define LRFDMDM32_EVT2_GPI1_ONE 0x00008000U +#define LRFDMDM32_EVT2_GPI1_ZERO 0x00000000U + +// Field: [14] GPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_GPI0 0x00004000U +#define LRFDMDM32_EVT2_GPI0_M 0x00004000U +#define LRFDMDM32_EVT2_GPI0_S 14U +#define LRFDMDM32_EVT2_GPI0_ONE 0x00004000U +#define LRFDMDM32_EVT2_GPI0_ZERO 0x00000000U + +// Field: [12] C1BEBLOADED +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEBLOADED 0x00001000U +#define LRFDMDM32_EVT2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM32_EVT2_C1BEBLOADED_S 12U +#define LRFDMDM32_EVT2_C1BEBLOADED_ONE 0x00001000U +#define LRFDMDM32_EVT2_C1BEBLOADED_ZERO 0x00000000U + +// Field: [11] C1BECMBANY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECMBANY 0x00000800U +#define LRFDMDM32_EVT2_C1BECMBANY_M 0x00000800U +#define LRFDMDM32_EVT2_C1BECMBANY_S 11U +#define LRFDMDM32_EVT2_C1BECMBANY_ONE 0x00000800U +#define LRFDMDM32_EVT2_C1BECMBANY_ZERO 0x00000000U + +// Field: [10] C1BECMBNEG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECMBNEG 0x00000400U +#define LRFDMDM32_EVT2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM32_EVT2_C1BECMBNEG_S 10U +#define LRFDMDM32_EVT2_C1BECMBNEG_ONE 0x00000400U +#define LRFDMDM32_EVT2_C1BECMBNEG_ZERO 0x00000000U + +// Field: [9] C1BECMBPOS +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECMBPOS 0x00000200U +#define LRFDMDM32_EVT2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM32_EVT2_C1BECMBPOS_S 9U +#define LRFDMDM32_EVT2_C1BECMBPOS_ONE 0x00000200U +#define LRFDMDM32_EVT2_C1BECMBPOS_ZERO 0x00000000U + +// Field: [8] C1BECANY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECANY 0x00000100U +#define LRFDMDM32_EVT2_C1BECANY_M 0x00000100U +#define LRFDMDM32_EVT2_C1BECANY_S 8U +#define LRFDMDM32_EVT2_C1BECANY_ONE 0x00000100U +#define LRFDMDM32_EVT2_C1BECANY_ZERO 0x00000000U + +// Field: [7] C1BECNEG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECNEG 0x00000080U +#define LRFDMDM32_EVT2_C1BECNEG_M 0x00000080U +#define LRFDMDM32_EVT2_C1BECNEG_S 7U +#define LRFDMDM32_EVT2_C1BECNEG_ONE 0x00000080U +#define LRFDMDM32_EVT2_C1BECNEG_ZERO 0x00000000U + +// Field: [6] C1BECPOS +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BECPOS 0x00000040U +#define LRFDMDM32_EVT2_C1BECPOS_M 0x00000040U +#define LRFDMDM32_EVT2_C1BECPOS_S 6U +#define LRFDMDM32_EVT2_C1BECPOS_ONE 0x00000040U +#define LRFDMDM32_EVT2_C1BECPOS_ZERO 0x00000000U + +// Field: [5] C1BEBANY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEBANY 0x00000020U +#define LRFDMDM32_EVT2_C1BEBANY_M 0x00000020U +#define LRFDMDM32_EVT2_C1BEBANY_S 5U +#define LRFDMDM32_EVT2_C1BEBANY_ONE 0x00000020U +#define LRFDMDM32_EVT2_C1BEBANY_ZERO 0x00000000U + +// Field: [4] C1BEBNEG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEBNEG 0x00000010U +#define LRFDMDM32_EVT2_C1BEBNEG_M 0x00000010U +#define LRFDMDM32_EVT2_C1BEBNEG_S 4U +#define LRFDMDM32_EVT2_C1BEBNEG_ONE 0x00000010U +#define LRFDMDM32_EVT2_C1BEBNEG_ZERO 0x00000000U + +// Field: [3] C1BEBPOS +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEBPOS 0x00000008U +#define LRFDMDM32_EVT2_C1BEBPOS_M 0x00000008U +#define LRFDMDM32_EVT2_C1BEBPOS_S 3U +#define LRFDMDM32_EVT2_C1BEBPOS_ONE 0x00000008U +#define LRFDMDM32_EVT2_C1BEBPOS_ZERO 0x00000000U + +// Field: [2] C1BEAANY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEAANY 0x00000004U +#define LRFDMDM32_EVT2_C1BEAANY_M 0x00000004U +#define LRFDMDM32_EVT2_C1BEAANY_S 2U +#define LRFDMDM32_EVT2_C1BEAANY_ONE 0x00000004U +#define LRFDMDM32_EVT2_C1BEAANY_ZERO 0x00000000U + +// Field: [1] C1BEANEG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEANEG 0x00000002U +#define LRFDMDM32_EVT2_C1BEANEG_M 0x00000002U +#define LRFDMDM32_EVT2_C1BEANEG_S 1U +#define LRFDMDM32_EVT2_C1BEANEG_ONE 0x00000002U +#define LRFDMDM32_EVT2_C1BEANEG_ZERO 0x00000000U + +// Field: [0] C1BEAPOS +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_EVT2_C1BEAPOS 0x00000001U +#define LRFDMDM32_EVT2_C1BEAPOS_M 0x00000001U +#define LRFDMDM32_EVT2_C1BEAPOS_S 0U +#define LRFDMDM32_EVT2_C1BEAPOS_ONE 0x00000001U +#define LRFDMDM32_EVT2_C1BEAPOS_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVTMSK1_EVTMSK0 +// +//***************************************************************************** +// Field: [24] REFCLK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_REFCLK 0x01000000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_REFCLK_M 0x01000000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_REFCLK_S 24U +#define LRFDMDM32_EVTMSK1_EVTMSK0_REFCLK_EN 0x01000000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_REFCLK_DIS 0x00000000U + +// Field: [23] S2RSTOP +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_S2RSTOP 0x00800000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_S2RSTOP_M 0x00800000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_S2RSTOP_S 23U +#define LRFDMDM32_EVTMSK1_EVTMSK0_S2RSTOP_EN 0x00800000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_S2RSTOP_DIS 0x00000000U + +// Field: [22] SWQUFALSESYNC +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUFALSESYNC 0x00400000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUFALSESYNC_M 0x00400000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUFALSESYNC_S 22U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUFALSESYNC_EN 0x00400000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUFALSESYNC_DIS 0x00000000U + +// Field: [21] SWQUSYNCED +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUSYNCED 0x00200000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUSYNCED_M 0x00200000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUSYNCED_S 21U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUSYNCED_EN 0x00200000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SWQUSYNCED_DIS 0x00000000U + +// Field: [20] CLKENBAUDF +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUDF 0x00100000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUDF_M 0x00100000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUDF_S 20U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUDF_EN 0x00100000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUDF_DIS 0x00000000U + +// Field: [19] FIFORVALID +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFORVALID 0x00080000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFORVALID_M 0x00080000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFORVALID_S 19U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFORVALID_EN 0x00080000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFORVALID_DIS 0x00000000U + +// Field: [18] FIFOWREADY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWREADY 0x00040000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWREADY_M 0x00040000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWREADY_S 18U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWREADY_EN 0x00040000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWREADY_DIS 0x00000000U + +// Field: [17] CLKENBAUD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUD 0x00020000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUD_M 0x00020000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUD_S 17U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUD_EN 0x00020000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKENBAUD_DIS 0x00000000U + +// Field: [16] PREAMBLEDONE +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_PREAMBLEDONE 0x00010000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PREAMBLEDONE_M 0x00010000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PREAMBLEDONE_S 16U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PREAMBLEDONE_EN 0x00010000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PREAMBLEDONE_DIS 0x00000000U + +// Field: [15] PBEDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBEDAT 0x00008000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBEDAT_M 0x00008000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBEDAT_S 15U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBEDAT_EN 0x00008000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBEDAT_DIS 0x00000000U + +// Field: [14] PBECMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBECMD 0x00004000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBECMD_M 0x00004000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBECMD_S 14U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBECMD_EN 0x00004000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_PBECMD_DIS 0x00000000U + +// Field: [13] RFEDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFEDAT 0x00002000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFEDAT_M 0x00002000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFEDAT_S 13U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFEDAT_EN 0x00002000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFEDAT_DIS 0x00000000U + +// Field: [12] BDEC +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_BDEC 0x00001000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_BDEC_M 0x00001000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_BDEC_S 12U +#define LRFDMDM32_EVTMSK1_EVTMSK0_BDEC_EN 0x00001000U +#define LRFDMDM32_EVTMSK1_EVTMSK0_BDEC_DIS 0x00000000U + +// Field: [11] FRAC +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FRAC 0x00000800U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FRAC_M 0x00000800U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FRAC_S 11U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FRAC_EN 0x00000800U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FRAC_DIS 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT2 0x00000400U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT2_S 10U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT2_EN 0x00000400U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT2_DIS 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT1 0x00000200U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT1_S 9U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT1_EN 0x00000200U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT1_DIS 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT0 0x00000100U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT0_S 8U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT0_EN 0x00000100U +#define LRFDMDM32_EVTMSK1_EVTMSK0_SYSTIMEVT0_DIS 0x00000000U + +// Field: [7] FIFOWR +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWR 0x00000080U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWR_M 0x00000080U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWR_S 7U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWR_EN 0x00000080U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOWR_DIS 0x00000000U + +// Field: [6] COUNTER +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_COUNTER 0x00000040U +#define LRFDMDM32_EVTMSK1_EVTMSK0_COUNTER_M 0x00000040U +#define LRFDMDM32_EVTMSK1_EVTMSK0_COUNTER_S 6U +#define LRFDMDM32_EVTMSK1_EVTMSK0_COUNTER_EN 0x00000040U +#define LRFDMDM32_EVTMSK1_EVTMSK0_COUNTER_DIS 0x00000000U + +// Field: [5] RFECMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFECMD 0x00000020U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFECMD_M 0x00000020U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFECMD_S 5U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFECMD_EN 0x00000020U +#define LRFDMDM32_EVTMSK1_EVTMSK0_RFECMD_DIS 0x00000000U + +// Field: [4] FIFOOVFL +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOOVFL 0x00000010U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOOVFL_M 0x00000010U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOOVFL_S 4U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOOVFL_EN 0x00000010U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOOVFL_DIS 0x00000000U + +// Field: [3] FIFOUNFL +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOUNFL 0x00000008U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOUNFL_M 0x00000008U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOUNFL_S 3U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOUNFL_EN 0x00000008U +#define LRFDMDM32_EVTMSK1_EVTMSK0_FIFOUNFL_DIS 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKEN4BAUD 0x00000004U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKEN4BAUD_S 2U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKEN4BAUD_EN 0x00000004U +#define LRFDMDM32_EVTMSK1_EVTMSK0_CLKEN4BAUD_DIS 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_TIMER 0x00000002U +#define LRFDMDM32_EVTMSK1_EVTMSK0_TIMER_M 0x00000002U +#define LRFDMDM32_EVTMSK1_EVTMSK0_TIMER_S 1U +#define LRFDMDM32_EVTMSK1_EVTMSK0_TIMER_EN 0x00000002U +#define LRFDMDM32_EVTMSK1_EVTMSK0_TIMER_DIS 0x00000000U + +// Field: [0] MDMAPI +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK1_EVTMSK0_MDMAPI 0x00000001U +#define LRFDMDM32_EVTMSK1_EVTMSK0_MDMAPI_M 0x00000001U +#define LRFDMDM32_EVTMSK1_EVTMSK0_MDMAPI_S 0U +#define LRFDMDM32_EVTMSK1_EVTMSK0_MDMAPI_EN 0x00000001U +#define LRFDMDM32_EVTMSK1_EVTMSK0_MDMAPI_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVTMSK2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_GPI1 0x00008000U +#define LRFDMDM32_EVTMSK2_GPI1_M 0x00008000U +#define LRFDMDM32_EVTMSK2_GPI1_S 15U +#define LRFDMDM32_EVTMSK2_GPI1_EN 0x00008000U +#define LRFDMDM32_EVTMSK2_GPI1_DIS 0x00000000U + +// Field: [14] GPI0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_GPI0 0x00004000U +#define LRFDMDM32_EVTMSK2_GPI0_M 0x00004000U +#define LRFDMDM32_EVTMSK2_GPI0_S 14U +#define LRFDMDM32_EVTMSK2_GPI0_EN 0x00004000U +#define LRFDMDM32_EVTMSK2_GPI0_DIS 0x00000000U + +// Field: [12] C1BEBLOADED +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEBLOADED 0x00001000U +#define LRFDMDM32_EVTMSK2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM32_EVTMSK2_C1BEBLOADED_S 12U +#define LRFDMDM32_EVTMSK2_C1BEBLOADED_EN 0x00001000U +#define LRFDMDM32_EVTMSK2_C1BEBLOADED_DIS 0x00000000U + +// Field: [11] C1BECMBANY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECMBANY 0x00000800U +#define LRFDMDM32_EVTMSK2_C1BECMBANY_M 0x00000800U +#define LRFDMDM32_EVTMSK2_C1BECMBANY_S 11U +#define LRFDMDM32_EVTMSK2_C1BECMBANY_EN 0x00000800U +#define LRFDMDM32_EVTMSK2_C1BECMBANY_DIS 0x00000000U + +// Field: [10] C1BECMBNEG +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECMBNEG 0x00000400U +#define LRFDMDM32_EVTMSK2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM32_EVTMSK2_C1BECMBNEG_S 10U +#define LRFDMDM32_EVTMSK2_C1BECMBNEG_EN 0x00000400U +#define LRFDMDM32_EVTMSK2_C1BECMBNEG_DIS 0x00000000U + +// Field: [9] C1BECMBPOS +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECMBPOS 0x00000200U +#define LRFDMDM32_EVTMSK2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM32_EVTMSK2_C1BECMBPOS_S 9U +#define LRFDMDM32_EVTMSK2_C1BECMBPOS_EN 0x00000200U +#define LRFDMDM32_EVTMSK2_C1BECMBPOS_DIS 0x00000000U + +// Field: [8] C1BECANY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECANY 0x00000100U +#define LRFDMDM32_EVTMSK2_C1BECANY_M 0x00000100U +#define LRFDMDM32_EVTMSK2_C1BECANY_S 8U +#define LRFDMDM32_EVTMSK2_C1BECANY_EN 0x00000100U +#define LRFDMDM32_EVTMSK2_C1BECANY_DIS 0x00000000U + +// Field: [7] C1BECNEG +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECNEG 0x00000080U +#define LRFDMDM32_EVTMSK2_C1BECNEG_M 0x00000080U +#define LRFDMDM32_EVTMSK2_C1BECNEG_S 7U +#define LRFDMDM32_EVTMSK2_C1BECNEG_EN 0x00000080U +#define LRFDMDM32_EVTMSK2_C1BECNEG_DIS 0x00000000U + +// Field: [6] C1BECPOS +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BECPOS 0x00000040U +#define LRFDMDM32_EVTMSK2_C1BECPOS_M 0x00000040U +#define LRFDMDM32_EVTMSK2_C1BECPOS_S 6U +#define LRFDMDM32_EVTMSK2_C1BECPOS_EN 0x00000040U +#define LRFDMDM32_EVTMSK2_C1BECPOS_DIS 0x00000000U + +// Field: [5] C1BEBANY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEBANY 0x00000020U +#define LRFDMDM32_EVTMSK2_C1BEBANY_M 0x00000020U +#define LRFDMDM32_EVTMSK2_C1BEBANY_S 5U +#define LRFDMDM32_EVTMSK2_C1BEBANY_EN 0x00000020U +#define LRFDMDM32_EVTMSK2_C1BEBANY_DIS 0x00000000U + +// Field: [4] C1BEBNEG +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEBNEG 0x00000010U +#define LRFDMDM32_EVTMSK2_C1BEBNEG_M 0x00000010U +#define LRFDMDM32_EVTMSK2_C1BEBNEG_S 4U +#define LRFDMDM32_EVTMSK2_C1BEBNEG_EN 0x00000010U +#define LRFDMDM32_EVTMSK2_C1BEBNEG_DIS 0x00000000U + +// Field: [3] C1BEBPOS +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEBPOS 0x00000008U +#define LRFDMDM32_EVTMSK2_C1BEBPOS_M 0x00000008U +#define LRFDMDM32_EVTMSK2_C1BEBPOS_S 3U +#define LRFDMDM32_EVTMSK2_C1BEBPOS_EN 0x00000008U +#define LRFDMDM32_EVTMSK2_C1BEBPOS_DIS 0x00000000U + +// Field: [2] C1BEAANY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEAANY 0x00000004U +#define LRFDMDM32_EVTMSK2_C1BEAANY_M 0x00000004U +#define LRFDMDM32_EVTMSK2_C1BEAANY_S 2U +#define LRFDMDM32_EVTMSK2_C1BEAANY_EN 0x00000004U +#define LRFDMDM32_EVTMSK2_C1BEAANY_DIS 0x00000000U + +// Field: [1] C1BEANEG +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEANEG 0x00000002U +#define LRFDMDM32_EVTMSK2_C1BEANEG_M 0x00000002U +#define LRFDMDM32_EVTMSK2_C1BEANEG_S 1U +#define LRFDMDM32_EVTMSK2_C1BEANEG_EN 0x00000002U +#define LRFDMDM32_EVTMSK2_C1BEANEG_DIS 0x00000000U + +// Field: [0] C1BEAPOS +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_EVTMSK2_C1BEAPOS 0x00000001U +#define LRFDMDM32_EVTMSK2_C1BEAPOS_M 0x00000001U +#define LRFDMDM32_EVTMSK2_C1BEAPOS_S 0U +#define LRFDMDM32_EVTMSK2_C1BEAPOS_EN 0x00000001U +#define LRFDMDM32_EVTMSK2_C1BEAPOS_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVTCLR1_EVTCLR0 +// +//***************************************************************************** +// Field: [24] REFCLK +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_REFCLK 0x01000000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_REFCLK_M 0x01000000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_REFCLK_S 24U +#define LRFDMDM32_EVTCLR1_EVTCLR0_REFCLK_CLEAR 0x01000000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_REFCLK_RETAIN 0x00000000U + +// Field: [23] S2RSTOP +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_S2RSTOP 0x00800000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_S2RSTOP_M 0x00800000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_S2RSTOP_S 23U +#define LRFDMDM32_EVTCLR1_EVTCLR0_S2RSTOP_CLEAR 0x00800000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_S2RSTOP_RETAIN 0x00000000U + +// Field: [22] SWQUFALSESYNC +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUFALSESYNC 0x00400000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUFALSESYNC_M 0x00400000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUFALSESYNC_S 22U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUFALSESYNC_CLEAR 0x00400000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUFALSESYNC_RETAIN 0x00000000U + +// Field: [21] SWQUSYNCED +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUSYNCED 0x00200000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUSYNCED_M 0x00200000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUSYNCED_S 21U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUSYNCED_CLEAR 0x00200000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SWQUSYNCED_RETAIN 0x00000000U + +// Field: [20] CLKENBAUDF +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUDF 0x00100000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUDF_M 0x00100000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUDF_S 20U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUDF_CLEAR 0x00100000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUDF_RETAIN 0x00000000U + +// Field: [19] FIFORVALID +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFORVALID 0x00080000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFORVALID_M 0x00080000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFORVALID_S 19U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFORVALID_CLEAR 0x00080000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFORVALID_RETAIN 0x00000000U + +// Field: [18] FIFOWREADY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWREADY 0x00040000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWREADY_M 0x00040000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWREADY_S 18U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWREADY_CLEAR 0x00040000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWREADY_RETAIN 0x00000000U + +// Field: [17] CLKENBAUD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUD 0x00020000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUD_M 0x00020000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUD_S 17U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUD_CLEAR 0x00020000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKENBAUD_RETAIN 0x00000000U + +// Field: [16] PREAMBLEDONE +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_PREAMBLEDONE 0x00010000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PREAMBLEDONE_M 0x00010000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PREAMBLEDONE_S 16U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PREAMBLEDONE_CLEAR 0x00010000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PREAMBLEDONE_RETAIN 0x00000000U + +// Field: [15] PBEDAT +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBEDAT 0x00008000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBEDAT_M 0x00008000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBEDAT_S 15U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBEDAT_CLEAR 0x00008000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBEDAT_RETAIN 0x00000000U + +// Field: [14] PBECMD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBECMD 0x00004000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBECMD_M 0x00004000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBECMD_S 14U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBECMD_CLEAR 0x00004000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_PBECMD_RETAIN 0x00000000U + +// Field: [13] RFEDAT +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFEDAT 0x00002000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFEDAT_M 0x00002000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFEDAT_S 13U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFEDAT_CLEAR 0x00002000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFEDAT_RETAIN 0x00000000U + +// Field: [12] BDEC +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_BDEC 0x00001000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_BDEC_M 0x00001000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_BDEC_S 12U +#define LRFDMDM32_EVTCLR1_EVTCLR0_BDEC_CLEAR 0x00001000U +#define LRFDMDM32_EVTCLR1_EVTCLR0_BDEC_RETAIN 0x00000000U + +// Field: [11] FRAC +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FRAC 0x00000800U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FRAC_M 0x00000800U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FRAC_S 11U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FRAC_CLEAR 0x00000800U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FRAC_RETAIN 0x00000000U + +// Field: [10] SYSTIMEVT2 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT2 0x00000400U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT2_M 0x00000400U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT2_S 10U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT2_CLEAR 0x00000400U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT2_RETAIN 0x00000000U + +// Field: [9] SYSTIMEVT1 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT1 0x00000200U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT1_M 0x00000200U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT1_S 9U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT1_CLEAR 0x00000200U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT1_RETAIN 0x00000000U + +// Field: [8] SYSTIMEVT0 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT0 0x00000100U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT0_M 0x00000100U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT0_S 8U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT0_CLEAR 0x00000100U +#define LRFDMDM32_EVTCLR1_EVTCLR0_SYSTIMEVT0_RETAIN 0x00000000U + +// Field: [7] FIFOWR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWR 0x00000080U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWR_M 0x00000080U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWR_S 7U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWR_CLEAR 0x00000080U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOWR_RETAIN 0x00000000U + +// Field: [6] COUNTER +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_COUNTER 0x00000040U +#define LRFDMDM32_EVTCLR1_EVTCLR0_COUNTER_M 0x00000040U +#define LRFDMDM32_EVTCLR1_EVTCLR0_COUNTER_S 6U +#define LRFDMDM32_EVTCLR1_EVTCLR0_COUNTER_CLEAR 0x00000040U +#define LRFDMDM32_EVTCLR1_EVTCLR0_COUNTER_RETAIN 0x00000000U + +// Field: [5] RFECMD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFECMD 0x00000020U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFECMD_M 0x00000020U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFECMD_S 5U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFECMD_CLEAR 0x00000020U +#define LRFDMDM32_EVTCLR1_EVTCLR0_RFECMD_RETAIN 0x00000000U + +// Field: [4] FIFOOVFL +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOOVFL 0x00000010U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOOVFL_M 0x00000010U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOOVFL_S 4U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOOVFL_CLEAR 0x00000010U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOOVFL_RETAIN 0x00000000U + +// Field: [3] FIFOUNFL +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOUNFL 0x00000008U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOUNFL_M 0x00000008U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOUNFL_S 3U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOUNFL_CLEAR 0x00000008U +#define LRFDMDM32_EVTCLR1_EVTCLR0_FIFOUNFL_RETAIN 0x00000000U + +// Field: [2] CLKEN4BAUD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKEN4BAUD 0x00000004U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKEN4BAUD_M 0x00000004U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKEN4BAUD_S 2U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKEN4BAUD_CLEAR 0x00000004U +#define LRFDMDM32_EVTCLR1_EVTCLR0_CLKEN4BAUD_RETAIN 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_TIMER 0x00000002U +#define LRFDMDM32_EVTCLR1_EVTCLR0_TIMER_M 0x00000002U +#define LRFDMDM32_EVTCLR1_EVTCLR0_TIMER_S 1U +#define LRFDMDM32_EVTCLR1_EVTCLR0_TIMER_CLEAR 0x00000002U +#define LRFDMDM32_EVTCLR1_EVTCLR0_TIMER_RETAIN 0x00000000U + +// Field: [0] MDMAPI +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR1_EVTCLR0_MDMAPI 0x00000001U +#define LRFDMDM32_EVTCLR1_EVTCLR0_MDMAPI_M 0x00000001U +#define LRFDMDM32_EVTCLR1_EVTCLR0_MDMAPI_S 0U +#define LRFDMDM32_EVTCLR1_EVTCLR0_MDMAPI_CLEAR 0x00000001U +#define LRFDMDM32_EVTCLR1_EVTCLR0_MDMAPI_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_EVTCLR2 +// +//***************************************************************************** +// Field: [15] GPI1 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_GPI1 0x00008000U +#define LRFDMDM32_EVTCLR2_GPI1_M 0x00008000U +#define LRFDMDM32_EVTCLR2_GPI1_S 15U +#define LRFDMDM32_EVTCLR2_GPI1_CLEAR 0x00008000U +#define LRFDMDM32_EVTCLR2_GPI1_RETAIN 0x00000000U + +// Field: [14] GPI0 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_GPI0 0x00004000U +#define LRFDMDM32_EVTCLR2_GPI0_M 0x00004000U +#define LRFDMDM32_EVTCLR2_GPI0_S 14U +#define LRFDMDM32_EVTCLR2_GPI0_CLEAR 0x00004000U +#define LRFDMDM32_EVTCLR2_GPI0_RETAIN 0x00000000U + +// Field: [12] C1BEBLOADED +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEBLOADED 0x00001000U +#define LRFDMDM32_EVTCLR2_C1BEBLOADED_M 0x00001000U +#define LRFDMDM32_EVTCLR2_C1BEBLOADED_S 12U +#define LRFDMDM32_EVTCLR2_C1BEBLOADED_CLEAR 0x00001000U +#define LRFDMDM32_EVTCLR2_C1BEBLOADED_RETAIN 0x00000000U + +// Field: [11] C1BECMBANY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECMBANY 0x00000800U +#define LRFDMDM32_EVTCLR2_C1BECMBANY_M 0x00000800U +#define LRFDMDM32_EVTCLR2_C1BECMBANY_S 11U +#define LRFDMDM32_EVTCLR2_C1BECMBANY_CLEAR 0x00000800U +#define LRFDMDM32_EVTCLR2_C1BECMBANY_RETAIN 0x00000000U + +// Field: [10] C1BECMBNEG +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECMBNEG 0x00000400U +#define LRFDMDM32_EVTCLR2_C1BECMBNEG_M 0x00000400U +#define LRFDMDM32_EVTCLR2_C1BECMBNEG_S 10U +#define LRFDMDM32_EVTCLR2_C1BECMBNEG_CLEAR 0x00000400U +#define LRFDMDM32_EVTCLR2_C1BECMBNEG_RETAIN 0x00000000U + +// Field: [9] C1BECMBPOS +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECMBPOS 0x00000200U +#define LRFDMDM32_EVTCLR2_C1BECMBPOS_M 0x00000200U +#define LRFDMDM32_EVTCLR2_C1BECMBPOS_S 9U +#define LRFDMDM32_EVTCLR2_C1BECMBPOS_CLEAR 0x00000200U +#define LRFDMDM32_EVTCLR2_C1BECMBPOS_RETAIN 0x00000000U + +// Field: [8] C1BECANY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECANY 0x00000100U +#define LRFDMDM32_EVTCLR2_C1BECANY_M 0x00000100U +#define LRFDMDM32_EVTCLR2_C1BECANY_S 8U +#define LRFDMDM32_EVTCLR2_C1BECANY_CLEAR 0x00000100U +#define LRFDMDM32_EVTCLR2_C1BECANY_RETAIN 0x00000000U + +// Field: [7] C1BECNEG +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECNEG 0x00000080U +#define LRFDMDM32_EVTCLR2_C1BECNEG_M 0x00000080U +#define LRFDMDM32_EVTCLR2_C1BECNEG_S 7U +#define LRFDMDM32_EVTCLR2_C1BECNEG_CLEAR 0x00000080U +#define LRFDMDM32_EVTCLR2_C1BECNEG_RETAIN 0x00000000U + +// Field: [6] C1BECPOS +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BECPOS 0x00000040U +#define LRFDMDM32_EVTCLR2_C1BECPOS_M 0x00000040U +#define LRFDMDM32_EVTCLR2_C1BECPOS_S 6U +#define LRFDMDM32_EVTCLR2_C1BECPOS_CLEAR 0x00000040U +#define LRFDMDM32_EVTCLR2_C1BECPOS_RETAIN 0x00000000U + +// Field: [5] C1BEBANY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEBANY 0x00000020U +#define LRFDMDM32_EVTCLR2_C1BEBANY_M 0x00000020U +#define LRFDMDM32_EVTCLR2_C1BEBANY_S 5U +#define LRFDMDM32_EVTCLR2_C1BEBANY_CLEAR 0x00000020U +#define LRFDMDM32_EVTCLR2_C1BEBANY_RETAIN 0x00000000U + +// Field: [4] C1BEBNEG +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEBNEG 0x00000010U +#define LRFDMDM32_EVTCLR2_C1BEBNEG_M 0x00000010U +#define LRFDMDM32_EVTCLR2_C1BEBNEG_S 4U +#define LRFDMDM32_EVTCLR2_C1BEBNEG_CLEAR 0x00000010U +#define LRFDMDM32_EVTCLR2_C1BEBNEG_RETAIN 0x00000000U + +// Field: [3] C1BEBPOS +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEBPOS 0x00000008U +#define LRFDMDM32_EVTCLR2_C1BEBPOS_M 0x00000008U +#define LRFDMDM32_EVTCLR2_C1BEBPOS_S 3U +#define LRFDMDM32_EVTCLR2_C1BEBPOS_CLEAR 0x00000008U +#define LRFDMDM32_EVTCLR2_C1BEBPOS_RETAIN 0x00000000U + +// Field: [2] C1BEAANY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEAANY 0x00000004U +#define LRFDMDM32_EVTCLR2_C1BEAANY_M 0x00000004U +#define LRFDMDM32_EVTCLR2_C1BEAANY_S 2U +#define LRFDMDM32_EVTCLR2_C1BEAANY_CLEAR 0x00000004U +#define LRFDMDM32_EVTCLR2_C1BEAANY_RETAIN 0x00000000U + +// Field: [1] C1BEANEG +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEANEG 0x00000002U +#define LRFDMDM32_EVTCLR2_C1BEANEG_M 0x00000002U +#define LRFDMDM32_EVTCLR2_C1BEANEG_S 1U +#define LRFDMDM32_EVTCLR2_C1BEANEG_CLEAR 0x00000002U +#define LRFDMDM32_EVTCLR2_C1BEANEG_RETAIN 0x00000000U + +// Field: [0] C1BEAPOS +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDMDM32_EVTCLR2_C1BEAPOS 0x00000001U +#define LRFDMDM32_EVTCLR2_C1BEAPOS_M 0x00000001U +#define LRFDMDM32_EVTCLR2_C1BEAPOS_S 0U +#define LRFDMDM32_EVTCLR2_C1BEAPOS_CLEAR 0x00000001U +#define LRFDMDM32_EVTCLR2_C1BEAPOS_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_API_PDREQ +// +//***************************************************************************** +// Field: [23:20] PROTOCOLID +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_API_PDREQ_PROTOCOLID_W 4U +#define LRFDMDM32_API_PDREQ_PROTOCOLID_M 0x00F00000U +#define LRFDMDM32_API_PDREQ_PROTOCOLID_S 20U +#define LRFDMDM32_API_PDREQ_PROTOCOLID_ALLONES 0x00F00000U +#define LRFDMDM32_API_PDREQ_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [19:16] MDMCMD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All bits are 0 +#define LRFDMDM32_API_PDREQ_MDMCMD_W 4U +#define LRFDMDM32_API_PDREQ_MDMCMD_M 0x000F0000U +#define LRFDMDM32_API_PDREQ_MDMCMD_S 16U +#define LRFDMDM32_API_PDREQ_MDMCMD_ALLONES 0x000F0000U +#define LRFDMDM32_API_PDREQ_MDMCMD_ALLZEROS 0x00000000U + +// Field: [0] TOPSMPDREQ +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_API_PDREQ_TOPSMPDREQ 0x00000001U +#define LRFDMDM32_API_PDREQ_TOPSMPDREQ_M 0x00000001U +#define LRFDMDM32_API_PDREQ_TOPSMPDREQ_S 0U +#define LRFDMDM32_API_PDREQ_TOPSMPDREQ_ON 0x00000001U +#define LRFDMDM32_API_PDREQ_TOPSMPDREQ_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_CMDPAR1_CMDPAR0 +// +//***************************************************************************** +// Field: [31:16] CMDPAR1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR1_VAL_W 16U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR1_VAL_M 0xFFFF0000U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR1_VAL_S 16U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR1_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR1_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] CMDPAR0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR0_VAL_W 16U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR0_VAL_M 0x0000FFFFU +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR0_VAL_S 0U +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_CMDPAR1_CMDPAR0_CMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MSGBOX_CMDPAR2 +// +//***************************************************************************** +// Field: [23:16] MSGBOX_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MSGBOX_CMDPAR2_MSGBOX_VAL_W 8U +#define LRFDMDM32_MSGBOX_CMDPAR2_MSGBOX_VAL_M 0x00FF0000U +#define LRFDMDM32_MSGBOX_CMDPAR2_MSGBOX_VAL_S 16U +#define LRFDMDM32_MSGBOX_CMDPAR2_MSGBOX_VAL_ALLONES 0x00FF0000U +#define LRFDMDM32_MSGBOX_CMDPAR2_MSGBOX_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] CMDPAR2_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MSGBOX_CMDPAR2_CMDPAR2_VAL_W 16U +#define LRFDMDM32_MSGBOX_CMDPAR2_CMDPAR2_VAL_M 0x0000FFFFU +#define LRFDMDM32_MSGBOX_CMDPAR2_CMDPAR2_VAL_S 0U +#define LRFDMDM32_MSGBOX_CMDPAR2_CMDPAR2_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_MSGBOX_CMDPAR2_CMDPAR2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FIFOWR_FREQ +// +//***************************************************************************** +// Field: [31:16] PAYLOADIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_FIFOWR_FREQ_PAYLOADIN_W 16U +#define LRFDMDM32_FIFOWR_FREQ_PAYLOADIN_M 0xFFFF0000U +#define LRFDMDM32_FIFOWR_FREQ_PAYLOADIN_S 16U +#define LRFDMDM32_FIFOWR_FREQ_PAYLOADIN_ALLONES 0xFFFF0000U +#define LRFDMDM32_FIFOWR_FREQ_PAYLOADIN_ALLZEROS 0x00000000U + +// Field: [15:0] OFFSET +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_FIFOWR_FREQ_OFFSET_W 16U +#define LRFDMDM32_FIFOWR_FREQ_OFFSET_M 0x0000FFFFU +#define LRFDMDM32_FIFOWR_FREQ_OFFSET_S 0U +#define LRFDMDM32_FIFOWR_FREQ_OFFSET_ALLONES 0x0000FFFFU +#define LRFDMDM32_FIFOWR_FREQ_OFFSET_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FIFORD +// +//***************************************************************************** +// Field: [15:0] PAYLOADOUT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_FIFORD_PAYLOADOUT_W 16U +#define LRFDMDM32_FIFORD_PAYLOADOUT_M 0x0000FFFFU +#define LRFDMDM32_FIFORD_PAYLOADOUT_S 0U +#define LRFDMDM32_FIFORD_PAYLOADOUT_ALLONES 0x0000FFFFU +#define LRFDMDM32_FIFORD_PAYLOADOUT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FIFORDCTRL_FIFOWRCTRL +// +//***************************************************************************** +// Field: [21:20] FIFORDPORT +// +// ENUMs: +// PBE PBE has read access +// MODEM Modem has read access +// MDMFIFORD The FIFORD register is used for read access +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_W 2U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_M 0x00300000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_S 20U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_PBE 0x00200000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_MODEM 0x00100000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFORDPORT_MDMFIFORD 0x00000000U + +// Field: [19:16] WORDSZRD +// +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_W 4U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_M 0x000F0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_S 16U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS16 0x000F0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS15 0x000E0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS14 0x000D0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS13 0x000C0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS12 0x000B0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS11 0x000A0000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS10 0x00090000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS9 0x00080000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS8 0x00070000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS7 0x00060000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS6 0x00050000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS5 0x00040000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS4 0x00030000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS3 0x00020000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS2 0x00010000U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZRD_BITS1 0x00000000U + +// Field: [5:4] FIFOWRPORT +// +// ENUMs: +// PBE PBE has write access +// MODEM Modem has write access +// MDMFIFOWR The FIFOWR register is used for write access +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_W 2U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_M 0x00000030U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_S 4U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_PBE 0x00000020U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_MODEM 0x00000010U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_FIFOWRPORT_MDMFIFOWR 0x00000000U + +// Field: [3:0] WORDSZWR +// +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_W 4U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_M 0x0000000FU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_S 0U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS16 0x0000000FU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS15 0x0000000EU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS14 0x0000000DU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS13 0x0000000CU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS12 0x0000000BU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS11 0x0000000AU +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS10 0x00000009U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS9 0x00000008U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS8 0x00000007U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS7 0x00000006U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS6 0x00000005U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS5 0x00000004U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS4 0x00000003U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS3 0x00000002U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS2 0x00000001U +#define LRFDMDM32_FIFORDCTRL_FIFOWRCTRL_WORDSZWR_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FIFOSTA +// +//***************************************************************************** +// Field: [21] OVERFLOW +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_OVERFLOW 0x00200000U +#define LRFDMDM32_FIFOSTA_OVERFLOW_M 0x00200000U +#define LRFDMDM32_FIFOSTA_OVERFLOW_S 21U +#define LRFDMDM32_FIFOSTA_OVERFLOW_ONE 0x00200000U +#define LRFDMDM32_FIFOSTA_OVERFLOW_ZERO 0x00000000U + +// Field: [20] ALMOSTFULL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_ALMOSTFULL 0x00100000U +#define LRFDMDM32_FIFOSTA_ALMOSTFULL_M 0x00100000U +#define LRFDMDM32_FIFOSTA_ALMOSTFULL_S 20U +#define LRFDMDM32_FIFOSTA_ALMOSTFULL_ONE 0x00100000U +#define LRFDMDM32_FIFOSTA_ALMOSTFULL_ZERO 0x00000000U + +// Field: [19] ALMOSTEMPTY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_ALMOSTEMPTY 0x00080000U +#define LRFDMDM32_FIFOSTA_ALMOSTEMPTY_M 0x00080000U +#define LRFDMDM32_FIFOSTA_ALMOSTEMPTY_S 19U +#define LRFDMDM32_FIFOSTA_ALMOSTEMPTY_ONE 0x00080000U +#define LRFDMDM32_FIFOSTA_ALMOSTEMPTY_ZERO 0x00000000U + +// Field: [18] UNDERFLOW +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_UNDERFLOW 0x00040000U +#define LRFDMDM32_FIFOSTA_UNDERFLOW_M 0x00040000U +#define LRFDMDM32_FIFOSTA_UNDERFLOW_S 18U +#define LRFDMDM32_FIFOSTA_UNDERFLOW_ONE 0x00040000U +#define LRFDMDM32_FIFOSTA_UNDERFLOW_ZERO 0x00000000U + +// Field: [17] RXVALID +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_RXVALID 0x00020000U +#define LRFDMDM32_FIFOSTA_RXVALID_M 0x00020000U +#define LRFDMDM32_FIFOSTA_RXVALID_S 17U +#define LRFDMDM32_FIFOSTA_RXVALID_ONE 0x00020000U +#define LRFDMDM32_FIFOSTA_RXVALID_ZERO 0x00000000U + +// Field: [16] TXREADY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FIFOSTA_TXREADY 0x00010000U +#define LRFDMDM32_FIFOSTA_TXREADY_M 0x00010000U +#define LRFDMDM32_FIFOSTA_TXREADY_S 16U +#define LRFDMDM32_FIFOSTA_TXREADY_ONE 0x00010000U +#define LRFDMDM32_FIFOSTA_TXREADY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_RFEDATIN0_RFEDATOUT0 +// +//***************************************************************************** +// Field: [31:16] RFEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATIN0_VAL_W 16U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATIN0_VAL_M 0xFFFF0000U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATIN0_VAL_S 16U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATIN0_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATIN0_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] RFEDATOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATOUT0_VAL_W 16U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATOUT0_VAL_S 0U +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_RFEDATIN0_RFEDATOUT0_RFEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_RFECMDIN_RFECMDOUT +// +//***************************************************************************** +// Field: [19:16] RFECMDIN_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDIN_VAL_W 4U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDIN_VAL_M 0x000F0000U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDIN_VAL_S 16U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDIN_VAL_ALLONES 0x000F0000U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDIN_VAL_ALLZEROS 0x00000000U + +// Field: [3:0] RFECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDOUT_VAL_W 4U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDOUT_VAL_M 0x0000000FU +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDOUT_VAL_S 0U +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDMDM32_RFECMDIN_RFECMDOUT_RFECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_PBEDATIN0_PBEDATOUT0 +// +//***************************************************************************** +// Field: [31:16] PBEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_W 16U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_M 0xFFFF0000U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_S 16U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] PBEDATOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_W 16U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_S 0U +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_PBECMDIN_PBECMDOUT +// +//***************************************************************************** +// Field: [19:16] PBECMDIN_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_W 4U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_M 0x000F0000U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_S 16U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLONES 0x000F0000U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLZEROS 0x00000000U + +// Field: [3:0] PBECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_W 4U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_M 0x0000000FU +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_S 0U +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDMDM32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_PBEEVTMUX_LQIEST +// +//***************************************************************************** +// Field: [21:16] SEL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBEEVTMUX_LQIEST_SEL_W 6U +#define LRFDMDM32_PBEEVTMUX_LQIEST_SEL_M 0x003F0000U +#define LRFDMDM32_PBEEVTMUX_LQIEST_SEL_S 16U +#define LRFDMDM32_PBEEVTMUX_LQIEST_SEL_ALLONES 0x003F0000U +#define LRFDMDM32_PBEEVTMUX_LQIEST_SEL_ALLZEROS 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_PBEEVTMUX_LQIEST_VAL_W 8U +#define LRFDMDM32_PBEEVTMUX_LQIEST_VAL_M 0x000000FFU +#define LRFDMDM32_PBEEVTMUX_LQIEST_VAL_S 0U +#define LRFDMDM32_PBEEVTMUX_LQIEST_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_PBEEVTMUX_LQIEST_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SYSTIMEVTMUX1_SYSTIMEVTMUX0 +// +//***************************************************************************** +// Field: [21:16] SEL2 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL2_W 6U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL2_M 0x003F0000U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL2_S 16U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL2_ALLONES 0x003F0000U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL2_ALLZEROS 0x00000000U + +// Field: [11:6] SEL1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL1_W 6U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL1_M 0x00000FC0U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL1_S 6U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL1_ALLONES 0x00000FC0U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL1_ALLZEROS 0x00000000U + +// Field: [5:0] SEL0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL0_W 6U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL0_M 0x0000003FU +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL0_S 0U +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL0_ALLONES 0x0000003FU +#define LRFDMDM32_SYSTIMEVTMUX1_SYSTIMEVTMUX0_SEL0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MODPRECTRL_ADCDIGCONF +// +//***************************************************************************** +// Field: [23:20] REPS +// +// ENUMs: +// REPS16 16 repetitions +// REPS15 15 repetitions +// REPS14 14 repetitions +// REPS13 13 repetitions +// REPS12 12 repetitions +// REPS11 11 repetitions +// REPS10 10 repetitions +// REPS9 9 repetitions +// REPS8 8 repetitions +// REPS7 7 repetitions +// REPS6 6 repetitions +// REPS5 5 repetitions +// REPS4 4 repetitions +// REPS3 3 repetitions +// REPS2 2 repetitions +// REPS1 1 repetition (i.e. only once) +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_W 4U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_M 0x00F00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_S 20U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS16 0x00F00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS15 0x00E00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS14 0x00D00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS13 0x00C00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS12 0x00B00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS11 0x00A00000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS10 0x00900000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS9 0x00800000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS8 0x00700000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS7 0x00600000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS6 0x00500000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS5 0x00400000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS4 0x00300000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS3 0x00200000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS2 0x00100000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_REPS_REPS1 0x00000000U + +// Field: [19:16] SIZE +// +// ENUMs: +// BITS16 16 bits +// BITS8 8 bits +// BITS4 4 bits +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_W 4U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_M 0x000F0000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_S 16U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_BITS16 0x000F0000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_BITS8 0x00070000U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_SIZE_BITS4 0x00030000U + +// Field: [1] QBRANCHEN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_QBRANCHEN 0x00000002U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_QBRANCHEN_M 0x00000002U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_QBRANCHEN_S 1U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_QBRANCHEN_ON 0x00000002U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_QBRANCHEN_OFF 0x00000000U + +// Field: [0] IBRANCHEN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_IBRANCHEN 0x00000001U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_IBRANCHEN_M 0x00000001U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_IBRANCHEN_S 0U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_IBRANCHEN_ON 0x00000001U +#define LRFDMDM32_MODPRECTRL_ADCDIGCONF_IBRANCHEN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MODSYMMAP1_MODSYMMAP0 +// +//***************************************************************************** +// Field: [31:28] SYM7 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM7_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM7_M 0xF0000000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM7_S 28U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM7_ALLONES 0xF0000000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM7_ALLZEROS 0x00000000U + +// Field: [27:24] SYM6 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM6_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM6_M 0x0F000000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM6_S 24U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM6_ALLONES 0x0F000000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM6_ALLZEROS 0x00000000U + +// Field: [23:20] SYM5 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM5_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM5_M 0x00F00000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM5_S 20U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM5_ALLONES 0x00F00000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM5_ALLZEROS 0x00000000U + +// Field: [19:16] SYM4 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM4_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM4_M 0x000F0000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM4_S 16U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM4_ALLONES 0x000F0000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM4_ALLZEROS 0x00000000U + +// Field: [15:12] SYM3 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM3_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM3_M 0x0000F000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM3_S 12U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM3_ALLONES 0x0000F000U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM3_ALLZEROS 0x00000000U + +// Field: [11:8] SYM2 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM2_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM2_M 0x00000F00U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM2_S 8U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM2_ALLONES 0x00000F00U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM2_ALLZEROS 0x00000000U + +// Field: [7:4] SYM1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM1_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM1_M 0x000000F0U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM1_S 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM1_ALLONES 0x000000F0U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM1_ALLZEROS 0x00000000U + +// Field: [3:0] SYM0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM0_W 4U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM0_M 0x0000000FU +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM0_S 0U +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM0_ALLONES 0x0000000FU +#define LRFDMDM32_MODSYMMAP1_MODSYMMAP0_SYM0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_BAUD_MODSOFTTX +// +//***************************************************************************** +// Field: [31:16] RATEWORD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BAUD_MODSOFTTX_RATEWORD_W 16U +#define LRFDMDM32_BAUD_MODSOFTTX_RATEWORD_M 0xFFFF0000U +#define LRFDMDM32_BAUD_MODSOFTTX_RATEWORD_S 16U +#define LRFDMDM32_BAUD_MODSOFTTX_RATEWORD_ALLONES 0xFFFF0000U +#define LRFDMDM32_BAUD_MODSOFTTX_RATEWORD_ALLZEROS 0x00000000U + +// Field: [3:0] SOFTSYMBOL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BAUD_MODSOFTTX_SOFTSYMBOL_W 4U +#define LRFDMDM32_BAUD_MODSOFTTX_SOFTSYMBOL_M 0x0000000FU +#define LRFDMDM32_BAUD_MODSOFTTX_SOFTSYMBOL_S 0U +#define LRFDMDM32_BAUD_MODSOFTTX_SOFTSYMBOL_ALLONES 0x0000000FU +#define LRFDMDM32_BAUD_MODSOFTTX_SOFTSYMBOL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MODMAIN_BAUDPRE +// +//***************************************************************************** +// Field: [19:18] FECSELECT +// +// ENUMs: +// BLR Bluetooth LE coded long range compatible FEC +// RESERVED Reserved +// IEEE15_4 IEEE 802.15.4 +// NOSEL No FEC encoding selected +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_W 2U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_M 0x000C0000U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_S 18U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_BLR 0x000C0000U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_RESERVED 0x00080000U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_IEEE15_4 0x00040000U +#define LRFDMDM32_MODMAIN_BAUDPRE_FECSELECT_NOSEL 0x00000000U + +// Field: [17:16] MODLEVELS +// +// ENUMs: +// LVL8 8 levels +// LVL4 4 levels +// LVL2 2 levels +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_W 2U +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_M 0x00030000U +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_S 16U +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_LVL8 0x00020000U +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_LVL4 0x00010000U +#define LRFDMDM32_MODMAIN_BAUDPRE_MODLEVELS_LVL2 0x00000000U + +// Field: [15:13] ALIGNVALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODMAIN_BAUDPRE_ALIGNVALUE_W 3U +#define LRFDMDM32_MODMAIN_BAUDPRE_ALIGNVALUE_M 0x0000E000U +#define LRFDMDM32_MODMAIN_BAUDPRE_ALIGNVALUE_S 13U +#define LRFDMDM32_MODMAIN_BAUDPRE_ALIGNVALUE_ALLONES 0x0000E000U +#define LRFDMDM32_MODMAIN_BAUDPRE_ALIGNVALUE_ALLZEROS 0x00000000U + +// Field: [12:8] EXTRATEWORD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODMAIN_BAUDPRE_EXTRATEWORD_W 5U +#define LRFDMDM32_MODMAIN_BAUDPRE_EXTRATEWORD_M 0x00001F00U +#define LRFDMDM32_MODMAIN_BAUDPRE_EXTRATEWORD_S 8U +#define LRFDMDM32_MODMAIN_BAUDPRE_EXTRATEWORD_ALLONES 0x00001F00U +#define LRFDMDM32_MODMAIN_BAUDPRE_EXTRATEWORD_ALLZEROS 0x00000000U + +// Field: [7:0] PRESCALER +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODMAIN_BAUDPRE_PRESCALER_W 8U +#define LRFDMDM32_MODMAIN_BAUDPRE_PRESCALER_M 0x000000FFU +#define LRFDMDM32_MODMAIN_BAUDPRE_PRESCALER_S 0U +#define LRFDMDM32_MODMAIN_BAUDPRE_PRESCALER_ALLONES 0x000000FFU +#define LRFDMDM32_MODMAIN_BAUDPRE_PRESCALER_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMMISC1_DEMMISC0 +// +//***************************************************************************** +// Field: [28:24] CDCTGAINMA +// +// ENUMs: +// ALLONES Maximum gain mantissa. +// ALLZEROS When CDCTGAINMA is set to zero, the tracker loop +// is disabled. +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINMA_W 5U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINMA_M 0x1F000000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINMA_S 24U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINMA_ALLONES 0x1F000000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINMA_ALLZEROS 0x00000000U + +// Field: [23:21] CDCTGAINEX +// +// ENUMs: +// ALLONES When CDCTGAINEX is set to all zeroes, the +// CDCGAINMA multiplier is 512 +// ALLZEROS When CDCTGAINEX is set to all zeroes, the +// CDCGAINMA multiplier is 4 +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINEX_W 3U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINEX_M 0x00E00000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINEX_S 21U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINEX_ALLONES 0x00E00000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCTGAINEX_ALLZEROS 0x00000000U + +// Field: [20] CDCCOLRST +// +// ENUMs: +// EN Enable collision detect and restart feature +// DIS Do not enable collision detect and restart feature +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCCOLRST 0x00100000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCCOLRST_M 0x00100000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCCOLRST_S 20U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCCOLRST_EN 0x00100000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CDCCOLRST_DIS 0x00000000U + +// Field: [19:18] MGE1SRCSEL +// +// ENUMs: +// CHFI Output of CHFI +// FEXB1 Output of the FEXB, as selected by +// DEMFEXB0.OUT2SRCSEL register +// FIDC Output of the FIDC (x4 samples) +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_W 2U +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_M 0x000C0000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_S 18U +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_CHFI 0x00080000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_FEXB1 0x00040000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_MGE1SRCSEL_FIDC 0x00000000U + +// Field: [17:16] CHFIBW +// +// ENUMs: +// BW0_29 0.29 * Fs. Using FIR filter with taps [2 3 1 -8 +// -18 -14 17 72 126 149 126 72 17 -14 -18 -8 1 3 +// 2]. +// BW0_41667 0.41667 * Fs. Using FIR filter with taps [-1 -4 2 +// 12 4 -25 -31 38 154 213 154 38 -31 -25 4 12 2 +// -4 -1]. +// BW0_3333 0.33333 * Fs. Using FIR filter with taps [0 4 6 0 +// -16 -25 0 65 138 170 138 65 0 -25 -16 0 6 4 0]. +// BW0_5 0.5 * Fs. Using FIR filter with taps [3 0 -9 0 20 +// 0 -46 0 160 256 160 0 -46 0 20 0 -9 0 3]. +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_W 2U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_M 0x00030000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_S 16U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_BW0_29 0x00030000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_BW0_41667 0x00020000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_BW0_3333 0x00010000U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CHFIBW_BW0_5 0x00000000U + +// Field: [9:0] CMIXN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMISC1_DEMMISC0_CMIXN_W 10U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CMIXN_M 0x000003FFU +#define LRFDMDM32_DEMMISC1_DEMMISC0_CMIXN_S 0U +#define LRFDMDM32_DEMMISC1_DEMMISC0_CMIXN_ALLONES 0x000003FFU +#define LRFDMDM32_DEMMISC1_DEMMISC0_CMIXN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMMISC3_DEMMISC2 +// +//***************************************************************************** +// Field: [30:29] BDE2DVGA +// +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_W 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_M 0x60000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_S 29U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_GAIN8 0x60000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_GAIN4 0x40000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_GAIN2 0x20000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DVGA_GAIN1 0x00000000U + +// Field: [28] BDE1FILTMODE +// +// ENUMs: +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1FILTMODE 0x10000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1FILTMODE_M 0x10000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1FILTMODE_S 28U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1FILTMODE_DIV2 0x10000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1FILTMODE_DIV1 0x00000000U + +// Field: [27:26] LQIPERIOD +// +// ENUMs: +// SYM1024 1024 symbols +// SYM256 256 symbols +// SYM64 64 symbols +// SYM16 16 symbols +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_W 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_M 0x0C000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_S 26U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_SYM1024 0x0C000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_SYM256 0x08000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_SYM64 0x04000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_LQIPERIOD_SYM16 0x00000000U + +// Field: [25:24] BDE1DVGA +// +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_W 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_M 0x03000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_S 24U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_GAIN8 0x03000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_GAIN4 0x02000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_GAIN2 0x01000000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1DVGA_GAIN1 0x00000000U + +// Field: [23] BDE1NUMSTAGES +// +// ENUMs: +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1NUMSTAGES 0x00800000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1NUMSTAGES_M 0x00800000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1NUMSTAGES_S 23U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1NUMSTAGES_DIV2 0x00800000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE1NUMSTAGES_DIV1 0x00000000U + +// Field: [22:21] PDIFDECIM +// +// ENUMs: +// DIV4 Decimate by 4 +// DIV2 Decimate by 2 +// DIV1 No decimation +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_W 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_M 0x00600000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_S 21U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_DIV4 0x00400000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_DIV2 0x00200000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDECIM_DIV1 0x00000000U + +// Field: [20:16] BDE2DECRATIO +// +// ENUMs: +// DIV8 Decimate by 8 +// DIV4 Decimate by 4 +// DIV2 Decimate by 2 +// DIV1 Decimate by 1 (no decimation) +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_W 5U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_M 0x001F0000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_S 16U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_DIV8 0x00030000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_DIV4 0x00020000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_DIV2 0x00010000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_BDE2DECRATIO_DIV1 0x00000000U + +// Field: [14] MLSERUN +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_DEMMISC3_DEMMISC2_MLSERUN 0x00004000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MLSERUN_M 0x00004000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MLSERUN_S 14U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MLSERUN_EN 0x00004000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MLSERUN_DIS 0x00000000U + +// Field: [13:12] MAFCGAIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMISC3_DEMMISC2_MAFCGAIN_W 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MAFCGAIN_M 0x00003000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MAFCGAIN_S 12U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MAFCGAIN_ALLONES 0x00003000U +#define LRFDMDM32_DEMMISC3_DEMMISC2_MAFCGAIN_ALLZEROS 0x00000000U + +// Field: [11] STIMBYPASS +// +// ENUMs: +// EN Perform estimation only (no timing correction) +// DIS Perform both estimation and correct timing +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMBYPASS 0x00000800U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMBYPASS_M 0x00000800U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMBYPASS_S 11U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMBYPASS_EN 0x00000800U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMBYPASS_DIS 0x00000000U + +// Field: [10] STIMESTONLY +// +// ENUMs: +// EN Perform estimation only (no timing correction) +// DIS Perform both estimation and correct timing +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMESTONLY 0x00000400U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMESTONLY_M 0x00000400U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMESTONLY_S 10U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMESTONLY_EN 0x00000400U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMESTONLY_DIS 0x00000000U + +// Field: [9:7] STIMTEAPERIOD +// +// ENUMs: +// SYM128 128 symbols +// SYM64 64 symbols +// SYM32 32 symbols +// SYM16 16 symbols +// SYM8 8 symbols +// SYM4 4 symbols +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_W 3U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_M 0x00000380U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_S 7U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM128 0x00000280U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM64 0x00000200U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM32 0x00000180U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM16 0x00000100U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM8 0x00000080U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAPERIOD_SYM4 0x00000000U + +// Field: [6:4] STIMTEAGAIN +// +// ENUMs: +// DIV4 Gain is 1/4 +// DIV8 Gain is 1/8 +// DIV16 Gain is 1/16 +// DIV32 Gain is 1/32 +// DIV64 Gain is 1/64 +// DIV128 Gain is 1/128 +// DIV256 Gain is 1/256 +// DIV512 Gain is 1/512 +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_W 3U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_M 0x00000070U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_S 4U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV4 0x00000070U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV8 0x00000060U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV16 0x00000050U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV32 0x00000040U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV64 0x00000030U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV128 0x00000020U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV256 0x00000010U +#define LRFDMDM32_DEMMISC3_DEMMISC2_STIMTEAGAIN_DIV512 0x00000000U + +// Field: [3] PDIFLINPREDEN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLINPREDEN 0x00000008U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLINPREDEN_M 0x00000008U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLINPREDEN_S 3U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLINPREDEN_ON 0x00000008U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLINPREDEN_OFF 0x00000000U + +// Field: [2] PDIFDESPECK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDESPECK 0x00000004U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDESPECK_M 0x00000004U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDESPECK_S 2U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDESPECK_EN 0x00000004U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFDESPECK_DIS 0x00000000U + +// Field: [1] PDIFIQCONJEN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFIQCONJEN 0x00000002U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFIQCONJEN_M 0x00000002U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFIQCONJEN_S 1U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFIQCONJEN_ON 0x00000002U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFIQCONJEN_OFF 0x00000000U + +// Field: [0] PDIFLIMITRANGE +// +// ENUMs: +// EN Limit the range to 7-bit, i.e. +/- 64 +// DIS Allow full 8-bit range, i.e. +/- 128 +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLIMITRANGE 0x00000001U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLIMITRANGE_M 0x00000001U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLIMITRANGE_S 0U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLIMITRANGE_EN 0x00000001U +#define LRFDMDM32_DEMMISC3_DEMMISC2_PDIFLIMITRANGE_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMDSBU_DEMIQMC0 +// +//***************************************************************************** +// Field: [31:24] DSBUAVGLENGTH +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUAVGLENGTH_W 8U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUAVGLENGTH_M 0xFF000000U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUAVGLENGTH_S 24U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUAVGLENGTH_ALLONES 0xFF000000U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUAVGLENGTH_ALLZEROS 0x00000000U + +// Field: [23:16] DSBUDELAY +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUDELAY_W 8U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUDELAY_M 0x00FF0000U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUDELAY_S 16U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUDELAY_ALLONES 0x00FF0000U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_DSBUDELAY_ALLZEROS 0x00000000U + +// Field: [15:8] GAINFACTOR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMDSBU_DEMIQMC0_GAINFACTOR_W 8U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_GAINFACTOR_M 0x0000FF00U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_GAINFACTOR_S 8U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_GAINFACTOR_ALLONES 0x0000FF00U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_GAINFACTOR_ALLZEROS 0x00000000U + +// Field: [7:0] PHASEFACTOR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMDSBU_DEMIQMC0_PHASEFACTOR_W 8U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_PHASEFACTOR_M 0x000000FFU +#define LRFDMDM32_DEMDSBU_DEMIQMC0_PHASEFACTOR_S 0U +#define LRFDMDM32_DEMDSBU_DEMIQMC0_PHASEFACTOR_ALLONES 0x000000FFU +#define LRFDMDM32_DEMDSBU_DEMIQMC0_PHASEFACTOR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMFIDC0_DEMCODC0 +// +//***************************************************************************** +// Field: [21:20] DEMFIDC0_COMPSEL +// +// ENUMs: +// ACC Compensate with latest accumulator estimate +// MANUAL Use manually programmable values from DEMFIDC1 +// registers +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_COMPSEL_W 2U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_COMPSEL_M 0x00300000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_COMPSEL_S 20U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_COMPSEL_ACC 0x00200000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_COMPSEL_MANUAL 0x00000000U + +// Field: [19:18] DEMFIDC0_ACCPERIOD +// +// ENUMs: +// SMPL512 512 samples +// SMPL128 128 samples +// SMPL32 32 samples +// SMPL8 8 samples +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_W 2U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_M 0x000C0000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_S 18U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_SMPL512 0x000C0000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_SMPL128 0x00080000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_SMPL32 0x00040000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCPERIOD_SMPL8 0x00000000U + +// Field: [17] DEMFIDC0_ACCMODE +// +// ENUMs: +// CONT Generate new DC estimates continuously +// SINGLE Generate a single DC estimate only, then stop +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCMODE 0x00020000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCMODE_M 0x00020000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCMODE_S 17U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCMODE_CONT 0x00020000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCMODE_SINGLE 0x00000000U + +// Field: [16] DEMFIDC0_ACCEN +// +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCEN 0x00010000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCEN_M 0x00010000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCEN_S 16U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCEN_ON 0x00010000U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMFIDC0_ACCEN_OFF 0x00000000U + +// Field: [11] DEMCODC0_ESTSEL +// +// ENUMs: +// IIR Read back latest IIR estimate +// ACC Read back latest accumulator estimate +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ESTSEL 0x00000800U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ESTSEL_M 0x00000800U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ESTSEL_S 11U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ESTSEL_IIR 0x00000800U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ESTSEL_ACC 0x00000000U + +// Field: [10:9] DEMCODC0_COMPSEL +// +// ENUMs: +// IIR Compensate with latest IIR estimate +// ACC Compensate with latest accumulator estimate +// MANUAL Use manually programmable values from DEMCODC1 +// registers +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_W 2U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_M 0x00000600U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_S 9U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_IIR 0x00000600U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_ACC 0x00000400U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_COMPSEL_MANUAL 0x00000000U + +// Field: [8] DEMCODC0_IIRUSEINITIAL +// +// ENUMs: +// EN Use the manual compensation values in DEMCODC1 for +// initialization +// DIS Initialize IIR filter with value zero +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRUSEINITIAL 0x00000100U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRUSEINITIAL_M 0x00000100U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRUSEINITIAL_S 8U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRUSEINITIAL_EN 0x00000100U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRUSEINITIAL_DIS 0x00000000U + +// Field: [7:5] DEMCODC0_IIRGAIN +// +// ENUMs: +// DIV1024 Use 1/1024 IIR adaptation +// DIV512 Use 1/512 IIR adaptation +// DIV256 Use 1/256 IIR adaptation +// DIV128 Use 1/128 IIR adaptation +// DIV64 Use 1/64 IIR adaptation +// DIV32 Use 1/32 IIR adaptation +// DIV16 Use 1/16 IIR adaptation +// OFF Filter disabled +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_W 3U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_M 0x000000E0U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_S 5U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV1024 0x000000E0U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV512 0x000000C0U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV256 0x000000A0U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV128 0x00000080U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV64 0x00000060U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV32 0x00000040U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_DIV16 0x00000020U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIRGAIN_OFF 0x00000000U + +// Field: [4] DEMCODC0_IIREN +// +// ENUMs: +// ON Enable IIR estimator +// OFF Disable IIR estimator +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIREN 0x00000010U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIREN_M 0x00000010U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIREN_S 4U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIREN_ON 0x00000010U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_IIREN_OFF 0x00000000U + +// Field: [3] DEMCODC0_ACCMODE +// +// ENUMs: +// CONT Generate new DC estimates continuously +// SINGLE Generate a single DC estimate only, then stop +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCMODE 0x00000008U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCMODE_M 0x00000008U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCMODE_S 3U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCMODE_CONT 0x00000008U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCMODE_SINGLE 0x00000000U + +// Field: [2:1] DEMCODC0_ACCPERIOD +// +// ENUMs: +// SMPL512 512 samples +// SMPL128 128 samples +// SMPL32 32 samples +// SMPL8 8 samples +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_W 2U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_M 0x00000006U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_S 1U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_SMPL512 0x00000006U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_SMPL128 0x00000004U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_SMPL32 0x00000002U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCPERIOD_SMPL8 0x00000000U + +// Field: [0] DEMCODC0_ACCEN +// +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCEN 0x00000001U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCEN_M 0x00000001U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCEN_S 0U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCEN_ON 0x00000001U +#define LRFDMDM32_DEMFIDC0_DEMCODC0_DEMCODC0_ACCEN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMDSXB0_DEMFEXB0 +// +//***************************************************************************** +// Field: [21] DEMDSXB0_OUT2PASSTHROUGH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT2PASSTHROUGH 0x00200000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT2PASSTHROUGH_M 0x00200000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT2PASSTHROUGH_S 21U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT2PASSTHROUGH_ONE \ + 0x00200000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT2PASSTHROUGH_ZERO \ + 0x00000000U + +// Field: [20] DEMDSXB0_OUT1PASSTHROUGH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT1PASSTHROUGH 0x00100000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT1PASSTHROUGH_M 0x00100000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT1PASSTHROUGH_S 20U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT1PASSTHROUGH_ONE \ + 0x00100000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUT1PASSTHROUGH_ZERO \ + 0x00000000U + +// Field: [19] DEMDSXB0_OUTSRCSEL2 +// +// ENUMs: +// MAFI Source is matched filter (MAFI) +// FIFE Source is fine frequency offset estimator (FIFE) +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL2 0x00080000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL2_M 0x00080000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL2_S 19U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL2_MAFI 0x00080000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL2_FIFE 0x00000000U + +// Field: [18] DEMDSXB0_OUTSRCSEL1 +// +// ENUMs: +// MAFI Source is matched filter (MAFI) +// FIFE Source is fine frequency offset estimator (FIFE) +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL1 0x00040000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL1_M 0x00040000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL1_S 18U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL1_MAFI 0x00040000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_OUTSRCSEL1_FIFE 0x00000000U + +// Field: [17] DEMDSXB0_B2SRCSEL +// +// ENUMs: +// FIFE Source is fine frequency offset estimator (FIFE) +// INPUT Source is crossbar main input +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B2SRCSEL 0x00020000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B2SRCSEL_M 0x00020000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B2SRCSEL_S 17U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B2SRCSEL_FIFE 0x00020000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B2SRCSEL_INPUT 0x00000000U + +// Field: [16] DEMDSXB0_B1SRCSEL +// +// ENUMs: +// MAFI Source is matched filter (MAFI) +// INPUT Source is crossbar main input +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B1SRCSEL 0x00010000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B1SRCSEL_M 0x00010000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B1SRCSEL_S 16U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B1SRCSEL_MAFI 0x00010000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMDSXB0_B1SRCSEL_INPUT 0x00000000U + +// Field: [13] DEMFEXB0_OUT2PASSTHROUGH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2PASSTHROUGH 0x00002000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2PASSTHROUGH_M 0x00002000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2PASSTHROUGH_S 13U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2PASSTHROUGH_ONE \ + 0x00002000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2PASSTHROUGH_ZERO \ + 0x00000000U + +// Field: [12:11] DEMFEXB0_OUT2SRCSEL +// +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is coarse DC remover (CODC) +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_M 0x00001800U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_S 11U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_BDE1 0x00001000U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_CMIX 0x00000800U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT2SRCSEL_CODC 0x00000000U + +// Field: [10] DEMFEXB0_OUT1PASSTHROUGH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1PASSTHROUGH 0x00000400U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1PASSTHROUGH_M 0x00000400U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1PASSTHROUGH_S 10U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1PASSTHROUGH_ONE \ + 0x00000400U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1PASSTHROUGH_ZERO \ + 0x00000000U + +// Field: [9:8] DEMFEXB0_OUT1SRCSEL +// +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is coarse DC remover (CODC) +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_M 0x00000300U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_S 8U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_BDE1 0x00000200U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_CMIX 0x00000100U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_OUT1SRCSEL_CODC 0x00000000U + +// Field: [7:6] DEMFEXB0_B4SRCSEL +// +// ENUMs: +// ONES Source is complex N*Fs/1024 mixer (ONES) +// ZEROS Source is complex N*Fs/1024 mixer (ZEROS) +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B4SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B4SRCSEL_M 0x000000C0U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B4SRCSEL_S 6U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B4SRCSEL_ONES 0x000000C0U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B4SRCSEL_ZEROS 0x00000000U + +// Field: [5:4] DEMFEXB0_B3SRCSEL +// +// ENUMs: +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// CODC Source is complex N*Fs/1024 mixer (CMIX) +// INPUT Source is crossbar main input +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_M 0x00000030U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_S 4U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_CMIX 0x00000020U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_CODC 0x00000010U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B3SRCSEL_INPUT 0x00000000U + +// Field: [3:2] DEMFEXB0_B2SRCSEL +// +// ENUMs: +// BDE1 Source is coarse DC remover (CODC) +// CODC Source is coarse DC remover (CODC) +// INPUT Source is crossbar main input +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_M 0x0000000CU +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_S 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_BDE1 0x00000008U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_CODC 0x00000004U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B2SRCSEL_INPUT 0x00000000U + +// Field: [1:0] DEMFEXB0_B1SRCSEL +// +// ENUMs: +// BDE1 Source is complex N*Fs/1024 mixer (CMIX) +// CMIX Source is complex N*Fs/1024 mixer (CMIX) +// INPUT Source is crossbar main input +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_W 2U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_M 0x00000003U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_S 0U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_BDE1 0x00000002U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_CMIX 0x00000001U +#define LRFDMDM32_DEMDSXB0_DEMFEXB0_DEMFEXB0_B1SRCSEL_INPUT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMMAFI0_DEMFIFE0 +// +//***************************************************************************** +// Field: [31:24] C1C7 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C1C7_W 8U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C1C7_M 0xFF000000U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C1C7_S 24U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C1C7_ALLONES 0xFF000000U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C1C7_ALLZEROS 0x00000000U + +// Field: [23:16] C0C8 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C0C8_W 8U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C0C8_M 0x00FF0000U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C0C8_S 16U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C0C8_ALLONES 0x00FF0000U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_C0C8_ALLZEROS 0x00000000U + +// Field: [11] FINEFOESEL +// +// ENUMs: +// ACC Latest accumulator estimate +// IIR Latest IIR estimate +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FINEFOESEL 0x00000800U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FINEFOESEL_M 0x00000800U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FINEFOESEL_S 11U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FINEFOESEL_ACC 0x00000800U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FINEFOESEL_IIR 0x00000000U + +// Field: [10:9] FOCFFSEL +// +// ENUMs: +// MANUAL Use programmable manual value from register bank. +// (Note: an input register is not implemented, so +// the manual compensation value is tied to '0') +// ACC Compensate with latest accumulator estimate +// IIR Compensate with latest IIR estimate +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_W 2U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_M 0x00000600U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_S 9U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_MANUAL 0x00000400U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_ACC 0x00000200U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_FOCFFSEL_IIR 0x00000000U + +// Field: [8] ACCCNTMODE +// +// ENUMs: +// CONT Generate new frequency offset estimates +// continuously +// SINGLE Generate a single frequency offset estimate only, +// then stop +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCCNTMODE 0x00000100U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCCNTMODE_M 0x00000100U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCCNTMODE_S 8U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCCNTMODE_CONT 0x00000100U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCCNTMODE_SINGLE 0x00000000U + +// Field: [7:6] ACCPERIOD +// +// ENUMs: +// PER512 512 samples +// PER256 256 samples +// PER128 128 samples +// PER64 64 samples +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_W 2U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_M 0x000000C0U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_S 6U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_PER512 0x000000C0U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_PER256 0x00000080U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_PER128 0x00000040U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCPERIOD_PER64 0x00000000U + +// Field: [5] ACCEN +// +// ENUMs: +// ON Enable accumulator estimator +// OFF Disable accumulator estimator +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCEN 0x00000020U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCEN_M 0x00000020U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCEN_S 5U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCEN_ON 0x00000020U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_ACCEN_OFF 0x00000000U + +// Field: [4] IIRUSEINITIAL +// +// ENUMs: +// EN Use the manual compensation value in DEMFIFE1 for +// initialization +// DIS Initialize IIR filter with value zero +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRUSEINITIAL 0x00000010U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRUSEINITIAL_M 0x00000010U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRUSEINITIAL_S 4U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRUSEINITIAL_EN 0x00000010U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRUSEINITIAL_DIS 0x00000000U + +// Field: [3:1] IIRGAIN +// +// ENUMs: +// DIV1024 Use 1/1024 IIR adaptation +// DIV512 Use 1/512 IIR adaptation +// DIV256 Use 1/256 IIR adaptation +// DIV128 Use 1/128 IIR adaptation +// DIV64 Use 1/64 IIR adaptation +// DIV32 Use 1/32 IIR adaptation +// DIV16 Use 1/16 IIR adaptation +// OFF Filter disabled +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_W 3U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_M 0x0000000EU +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_S 1U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV1024 0x0000000EU +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV512 0x0000000CU +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV256 0x0000000AU +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV128 0x00000008U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV64 0x00000006U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV32 0x00000004U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_DIV16 0x00000002U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIRGAIN_OFF 0x00000000U + +// Field: [0] IIREN +// +// ENUMs: +// ON Enable IIR estimator +// OFF Disable IIR estimator +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIREN 0x00000001U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIREN_M 0x00000001U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIREN_S 0U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIREN_ON 0x00000001U +#define LRFDMDM32_DEMMAFI0_DEMFIFE0_IIREN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMMAFI2_DEMMAFI1 +// +//***************************************************************************** +// Field: [24:16] C4 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C4_W 9U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C4_M 0x01FF0000U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C4_S 16U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C4_ALLONES 0x01FF0000U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C4_ALLZEROS 0x00000000U + +// Field: [15:8] C3C5 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C3C5_W 8U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C3C5_M 0x0000FF00U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C3C5_S 8U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C3C5_ALLONES 0x0000FF00U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C3C5_ALLZEROS 0x00000000U + +// Field: [7:0] C2C6 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C2C6_W 8U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C2C6_M 0x000000FFU +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C2C6_S 0U +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C2C6_ALLONES 0x000000FFU +#define LRFDMDM32_DEMMAFI2_DEMMAFI1_C2C6_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMC1BE1_DEMC1BE0 +// +//***************************************************************************** +// Field: [31:24] THRESHOLDB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDB_W 8U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDB_M 0xFF000000U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDB_S 24U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDB_ALLONES 0xFF000000U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDB_ALLZEROS 0x00000000U + +// Field: [23:16] THRESHOLDA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDA_W 8U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDA_M 0x00FF0000U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDA_S 16U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDA_ALLONES 0x00FF0000U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_THRESHOLDA_ALLZEROS 0x00000000U + +// Field: [15:11] MASKB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKB_W 5U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKB_M 0x0000F800U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKB_S 11U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKB_ALLONES 0x0000F800U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKB_ALLZEROS 0x00000000U + +// Field: [10:6] MASKA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKA_W 5U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKA_M 0x000007C0U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKA_S 6U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKA_ALLONES 0x000007C0U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_MASKA_ALLZEROS 0x00000000U + +// Field: [5:4] CASCCONF +// +// ENUMs: +// PARALLEL Connect correlators in parallel +// SERIAL Connect correlators in series (A -> B) +// SINGLE Correlator B not used +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_W 2U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_M 0x00000030U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_S 4U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_PARALLEL 0x00000020U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_SERIAL 0x00000010U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_CASCCONF_SINGLE 0x00000000U + +// Field: [3:0] COPYCONF +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_COPYCONF_W 4U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_COPYCONF_M 0x0000000FU +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_COPYCONF_S 0U +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_COPYCONF_ALLONES 0x0000000FU +#define LRFDMDM32_DEMC1BE1_DEMC1BE0_COPYCONF_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SPARE0_DEMC1BE2 +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SPARE0_DEMC1BE2_VAL_W 16U +#define LRFDMDM32_SPARE0_DEMC1BE2_VAL_M 0xFFFF0000U +#define LRFDMDM32_SPARE0_DEMC1BE2_VAL_S 16U +#define LRFDMDM32_SPARE0_DEMC1BE2_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_SPARE0_DEMC1BE2_VAL_ALLZEROS 0x00000000U + +// Field: [10] PARLOADCONF +// +// ENUMs: +// ATOD Trigger peak event only if peak is highest in +// correlator since search start +// ATOB Trigger peak event on all peaks above threshold +#define LRFDMDM32_SPARE0_DEMC1BE2_PARLOADCONF 0x00000400U +#define LRFDMDM32_SPARE0_DEMC1BE2_PARLOADCONF_M 0x00000400U +#define LRFDMDM32_SPARE0_DEMC1BE2_PARLOADCONF_S 10U +#define LRFDMDM32_SPARE0_DEMC1BE2_PARLOADCONF_ATOD 0x00000400U +#define LRFDMDM32_SPARE0_DEMC1BE2_PARLOADCONF_ATOB 0x00000000U + +// Field: [9:8] PEAKCONF +// +// ENUMs: +// BESTAB Trigger peak event for combined highest peak +// search for corr "A and B" and "D and E" in +// pairs +// BEST Trigger peak event only if peak is highest in +// correlator since search start +// THRESH Trigger peak event on all peaks above threshold +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_W 2U +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_M 0x00000300U +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_S 8U +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_BESTAB 0x00000200U +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_BEST 0x00000100U +#define LRFDMDM32_SPARE0_DEMC1BE2_PEAKCONF_THRESH 0x00000000U + +// Field: [7:0] THRESHOLDC +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SPARE0_DEMC1BE2_THRESHOLDC_W 8U +#define LRFDMDM32_SPARE0_DEMC1BE2_THRESHOLDC_M 0x000000FFU +#define LRFDMDM32_SPARE0_DEMC1BE2_THRESHOLDC_S 0U +#define LRFDMDM32_SPARE0_DEMC1BE2_THRESHOLDC_ALLONES 0x000000FFU +#define LRFDMDM32_SPARE0_DEMC1BE2_THRESHOLDC_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SPARE2_SPARE1 +// +//***************************************************************************** +// Field: [31:16] SPARE2_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SPARE2_SPARE1_SPARE2_VAL_W 16U +#define LRFDMDM32_SPARE2_SPARE1_SPARE2_VAL_M 0xFFFF0000U +#define LRFDMDM32_SPARE2_SPARE1_SPARE2_VAL_S 16U +#define LRFDMDM32_SPARE2_SPARE1_SPARE2_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_SPARE2_SPARE1_SPARE2_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] SPARE1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SPARE2_SPARE1_SPARE1_VAL_W 16U +#define LRFDMDM32_SPARE2_SPARE1_SPARE1_VAL_M 0x0000FFFFU +#define LRFDMDM32_SPARE2_SPARE1_SPARE1_VAL_S 0U +#define LRFDMDM32_SPARE2_SPARE1_SPARE1_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_SPARE2_SPARE1_SPARE1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMSWQU0_SPARE3 +// +//***************************************************************************** +// Field: [23] SYNCMODE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMSWQU0_SPARE3_SYNCMODE 0x00800000U +#define LRFDMDM32_DEMSWQU0_SPARE3_SYNCMODE_M 0x00800000U +#define LRFDMDM32_DEMSWQU0_SPARE3_SYNCMODE_S 23U +#define LRFDMDM32_DEMSWQU0_SPARE3_SYNCMODE_ONE 0x00800000U +#define LRFDMDM32_DEMSWQU0_SPARE3_SYNCMODE_ZERO 0x00000000U + +// Field: [22] AUTOMAFC +// +// ENUMs: +// ON Give control to sync word qualifier +// OFF Keep manual control over MAFC +#define LRFDMDM32_DEMSWQU0_SPARE3_AUTOMAFC 0x00400000U +#define LRFDMDM32_DEMSWQU0_SPARE3_AUTOMAFC_M 0x00400000U +#define LRFDMDM32_DEMSWQU0_SPARE3_AUTOMAFC_S 22U +#define LRFDMDM32_DEMSWQU0_SPARE3_AUTOMAFC_ON 0x00400000U +#define LRFDMDM32_DEMSWQU0_SPARE3_AUTOMAFC_OFF 0x00000000U + +// Field: [21] RUN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_DEMSWQU0_SPARE3_RUN 0x00200000U +#define LRFDMDM32_DEMSWQU0_SPARE3_RUN_M 0x00200000U +#define LRFDMDM32_DEMSWQU0_SPARE3_RUN_S 21U +#define LRFDMDM32_DEMSWQU0_SPARE3_RUN_ON 0x00200000U +#define LRFDMDM32_DEMSWQU0_SPARE3_RUN_OFF 0x00000000U + +// Field: [20:16] REFLEN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWQU0_SPARE3_REFLEN_W 5U +#define LRFDMDM32_DEMSWQU0_SPARE3_REFLEN_M 0x001F0000U +#define LRFDMDM32_DEMSWQU0_SPARE3_REFLEN_S 16U +#define LRFDMDM32_DEMSWQU0_SPARE3_REFLEN_ALLONES 0x001F0000U +#define LRFDMDM32_DEMSWQU0_SPARE3_REFLEN_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWQU0_SPARE3_VAL_W 16U +#define LRFDMDM32_DEMSWQU0_SPARE3_VAL_M 0x0000FFFFU +#define LRFDMDM32_DEMSWQU0_SPARE3_VAL_S 0U +#define LRFDMDM32_DEMSWQU0_SPARE3_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_DEMSWQU0_SPARE3_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMC1BEREF1_DEMC1BEREF0 +// +//***************************************************************************** +// Field: [31:16] CAR31C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR31C16_W 16U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR31C16_M 0xFFFF0000U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR31C16_S 16U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR31C16_ALLONES 0xFFFF0000U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR31C16_ALLZEROS 0x00000000U + +// Field: [15:0] CAR15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR15C0_W 16U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR15C0_M 0x0000FFFFU +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR15C0_S 0U +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR15C0_ALLONES 0x0000FFFFU +#define LRFDMDM32_DEMC1BEREF1_DEMC1BEREF0_CAR15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMC1BEREF3_DEMC1BEREF2 +// +//***************************************************************************** +// Field: [31:16] CBR31C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR31C16_W 16U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR31C16_M 0xFFFF0000U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR31C16_S 16U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR31C16_ALLONES 0xFFFF0000U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR31C16_ALLZEROS 0x00000000U + +// Field: [15:0] CBR15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR15C0_W 16U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR15C0_M 0x0000FFFFU +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR15C0_S 0U +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR15C0_ALLONES 0x0000FFFFU +#define LRFDMDM32_DEMC1BEREF3_DEMC1BEREF2_CBR15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MODPREAMBLE_MODCTRL +// +//***************************************************************************** +// Field: [31:16] WORD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_WORD_W 16U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_WORD_M 0xFFFF0000U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_WORD_S 16U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_WORD_ALLONES 0xFFFF0000U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_WORD_ALLZEROS 0x00000000U + +// Field: [11] DSBUSEL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_DSBUSEL 0x00000800U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_DSBUSEL_M 0x00000800U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_DSBUSEL_S 11U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_DSBUSEL_ONE 0x00000800U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_DSBUSEL_ZERO 0x00000000U + +// Field: [10] HDISMODE +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_HDISMODE 0x00000400U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_HDISMODE_M 0x00000400U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_HDISMODE_S 10U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_HDISMODE_EN 0x00000400U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_HDISMODE_DIS 0x00000000U + +// Field: [9] PARBITQUALEN +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PARBITQUALEN 0x00000200U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PARBITQUALEN_M 0x00000200U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PARBITQUALEN_S 9U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PARBITQUALEN_ON 0x00000200U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PARBITQUALEN_OFF 0x00000000U + +// Field: [8:7] STIMMODE +// +// ENUMs: +// EARLY STIM starts early +// LATE STIM starts late +// NORMAL Normal Mode +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_W 2U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_M 0x00000180U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_S 7U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_EARLY 0x00000100U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_LATE 0x00000080U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_STIMMODE_NORMAL 0x00000000U + +// Field: [6] C1BEMODE +// +// ENUMs: +// EARLYLATE Set the C1BE in special early/late mode +// NORMAL Normal mode +#define LRFDMDM32_MODPREAMBLE_MODCTRL_C1BEMODE 0x00000040U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_C1BEMODE_M 0x00000040U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_C1BEMODE_S 6U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_C1BEMODE_EARLYLATE 0x00000040U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_C1BEMODE_NORMAL 0x00000000U + +// Field: [5] SOFTPDIFFMODE +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTPDIFFMODE 0x00000020U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTPDIFFMODE_M 0x00000020U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTPDIFFMODE_S 5U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTPDIFFMODE_EN 0x00000020U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTPDIFFMODE_DIS 0x00000000U + +// Field: [4] SOFTTXENABLE +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTTXENABLE 0x00000010U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTTXENABLE_M 0x00000010U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTTXENABLE_S 4U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTTXENABLE_ON 0x00000010U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_SOFTTXENABLE_OFF 0x00000000U + +// Field: [3] FECENABLE +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FECENABLE 0x00000008U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FECENABLE_M 0x00000008U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FECENABLE_S 3U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FECENABLE_ON 0x00000008U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FECENABLE_OFF 0x00000000U + +// Field: [2] FEC5TERMINATE +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FEC5TERMINATE 0x00000004U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FEC5TERMINATE_M 0x00000004U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FEC5TERMINATE_S 2U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FEC5TERMINATE_ON 0x00000004U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_FEC5TERMINATE_OFF 0x00000000U + +// Field: [1] TONEINSERT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_TONEINSERT 0x00000002U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_TONEINSERT_M 0x00000002U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_TONEINSERT_S 1U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_TONEINSERT_EN 0x00000002U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_TONEINSERT_DIS 0x00000000U + +// Field: [0] PREAMBLEINSERT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PREAMBLEINSERT 0x00000001U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PREAMBLEINSERT_M 0x00000001U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PREAMBLEINSERT_S 0U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PREAMBLEINSERT_EN 0x00000001U +#define LRFDMDM32_MODPREAMBLE_MODCTRL_PREAMBLEINSERT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMFRAC1_DEMFRAC0 +// +//***************************************************************************** +// Field: [27:16] P27C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P27C16_W 12U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P27C16_M 0x0FFF0000U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P27C16_S 16U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P27C16_ALLONES 0x0FFF0000U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P27C16_ALLZEROS 0x00000000U + +// Field: [15:0] P15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P15C0_W 16U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P15C0_M 0x0000FFFFU +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P15C0_S 0U +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P15C0_ALLONES 0x0000FFFFU +#define LRFDMDM32_DEMFRAC1_DEMFRAC0_P15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMFRAC3_DEMFRAC2 +// +//***************************************************************************** +// Field: [27:16] Q27C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q27C16_W 12U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q27C16_M 0x0FFF0000U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q27C16_S 16U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q27C16_ALLONES 0x0FFF0000U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q27C16_ALLZEROS 0x00000000U + +// Field: [15:0] Q15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q15C0_W 16U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q15C0_M 0x0000FFFFU +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q15C0_S 0U +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q15C0_ALLONES 0x0000FFFFU +#define LRFDMDM32_DEMFRAC3_DEMFRAC2_Q15C0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMCODC2_DEMCODC1 +// +//***************************************************************************** +// Field: [28:16] COMPQVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPQVAL_W 13U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPQVAL_M 0x1FFF0000U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPQVAL_S 16U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPQVAL_ALLONES 0x1FFF0000U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPQVAL_ALLZEROS 0x00000000U + +// Field: [12:0] COMPIVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPIVAL_W 13U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPIVAL_M 0x00001FFFU +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPIVAL_S 0U +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPIVAL_ALLONES 0x00001FFFU +#define LRFDMDM32_DEMCODC2_DEMCODC1_COMPIVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMFIDC2_DEMFIDC1 +// +//***************************************************************************** +// Field: [28:16] COMPQVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPQVAL_W 13U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPQVAL_M 0x1FFF0000U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPQVAL_S 16U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPQVAL_ALLONES 0x1FFF0000U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPQVAL_ALLZEROS 0x00000000U + +// Field: [12:0] COMPIVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPIVAL_W 13U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPIVAL_M 0x00001FFFU +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPIVAL_S 0U +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPIVAL_ALLONES 0x00001FFFU +#define LRFDMDM32_DEMFIDC2_DEMFIDC1_COMPIVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMMAFC0_DEMFIFE1 +// +//***************************************************************************** +// Field: [23:16] COMPVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_COMPVAL_W 8U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_COMPVAL_M 0x00FF0000U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_COMPVAL_S 16U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_COMPVAL_ALLONES 0x00FF0000U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_COMPVAL_ALLZEROS 0x00000000U + +// Field: [7:0] FOCFBREGVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_FOCFBREGVAL_W 8U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_FOCFBREGVAL_M 0x000000FFU +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_FOCFBREGVAL_S 0U +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_FOCFBREGVAL_ALLONES 0x000000FFU +#define LRFDMDM32_DEMMAFC0_DEMFIFE1_FOCFBREGVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMSWIMBAL_DEMMAFI4 +// +//***************************************************************************** +// Field: [31:24] IMBALB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALB_W 8U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALB_M 0xFF000000U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALB_S 24U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALB_ALLONES 0xFF000000U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALB_ALLZEROS 0x00000000U + +// Field: [23:16] IMBALA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALA_W 8U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALA_M 0x00FF0000U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALA_S 16U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALA_ALLONES 0x00FF0000U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_IMBALA_ALLZEROS 0x00000000U + +// Field: [7:0] TERMVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_TERMVAL_W 8U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_TERMVAL_M 0x000000FFU +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_TERMVAL_S 0U +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_TERMVAL_ALLONES 0x000000FFU +#define LRFDMDM32_DEMSWIMBAL_DEMMAFI4_TERMVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMDEBUG_DEMSOFTPDIFF +// +//***************************************************************************** +// Field: [27:25] LOOPBACKPIN +// +// ENUMs: +// GPI7 GPI7 connected to loopback +// GPI6 GPI6 connected to loopback +// GPI5 GPI5 connected to loopback +// GPI4 GPI4 connected to loopback +// GPI3 GPI3 connected to loopback +// GPI2 GPI2 connected to loopback +// GPI1 GPI1 connected to loopback +// GPI0 GPI0 connected to loopback +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_W 3U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_M 0x0E000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_S 25U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI7 0x0E000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI6 0x0C000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI5 0x0A000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI4 0x08000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI3 0x06000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI2 0x04000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI1 0x02000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKPIN_GPI0 0x00000000U + +// Field: [24] DECSTAGETRIGGER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGETRIGGER 0x01000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGETRIGGER_M 0x01000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGETRIGGER_S 24U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGETRIGGER_ONE 0x01000000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGETRIGGER_ZERO 0x00000000U + +// Field: [23:21] DECSTAGEDEBUG +// +// ENUMs: +// SOFD Dump SOFD output samples +// STIM Dump STIM output samples +// MAFC Dump MAFC output samples +// C1BE Dump C1BE correlator A value (truncated to 8 LSBs +// only, may overflow if correlator value is +// +128). +// MAFI Dump MAFI output samples +// FIFE Dump PDIF output samples +// PDIF Dump PDIF output samples +// NOSEL No source selected +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_W 3U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_M 0x00E00000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_S 21U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_SOFD 0x00E00000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_STIM 0x00C00000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_MAFC 0x00A00000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_C1BE 0x00800000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_MAFI 0x00600000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_FIFE 0x00400000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_PDIF 0x00200000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_DECSTAGEDEBUG_NOSEL 0x00000000U + +// Field: [20] FRONTENDTRIGGER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDTRIGGER 0x00100000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDTRIGGER_M 0x00100000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDTRIGGER_S 20U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDTRIGGER_ONE 0x00100000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDTRIGGER_ZERO 0x00000000U + +// Field: [19:17] FRONTENDDEBUG +// +// ENUMs: +// FIDC Dump FRAC output samples +// FRAC Dump FRAC output samples +// CHFI Dump CHFI output samples +// BDE2 Dump BDE2 output samples +// FEXB2 Dump FEXB output #2 samples, as selected by +// DEMFEXB0.OUT2SRCSEL register +// BDE1 Dump BDE1 output samples +// IQMC Dump IQMC output samples +// NOSEL No source selected +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_W 3U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_M 0x000E0000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_S 17U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_FIDC 0x000E0000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_FRAC 0x000C0000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_CHFI 0x000A0000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_BDE2 0x00080000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_FEXB2 0x00060000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_BDE1 0x00040000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_IQMC 0x00020000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_FRONTENDDEBUG_NOSEL 0x00000000U + +// Field: [16] LOOPBACKMODE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKMODE 0x00010000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKMODE_M 0x00010000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKMODE_S 16U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKMODE_ONE 0x00010000U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_LOOPBACKMODE_ZERO 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_VAL_W 8U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_VAL_M 0x000000FFU +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_VAL_S 0U +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_DEMDEBUG_DEMSOFTPDIFF_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_VITCOMPUTE_VITCTRL +// +//***************************************************************************** +// Field: [16] START +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_VITCOMPUTE_VITCTRL_START 0x00010000U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_START_M 0x00010000U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_START_S 16U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_START_ONE 0x00010000U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_START_ZERO 0x00000000U + +// Field: [7:6] METRSEL +// +// ENUMs: +// MLSE Use MLSE Metrics +// SOFD Use SOFD Metrics +// PHAC Use PHAC Metrics +// MET5M Use 5Mbps Metrics +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_W 2U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_M 0x000000C0U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_S 6U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_MLSE 0x000000C0U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_SOFD 0x00000080U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_PHAC 0x00000040U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRSEL_MET5M 0x00000000U + +// Field: [5:2] APMRDBACKSEL +// +// ENUMs: +// APM7 View APM 7 +// APM6 View APM 6 +// APM5 View APM 5 +// APM4 View APM 4 +// APM3 View APM 3 +// APM2 View APM 2 +// APM1 View APM 1 +// APM0 View APM 0 +// NOSEL No selection +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_W 4U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_M 0x0000003CU +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_S 2U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM7 0x0000003CU +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM6 0x00000038U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM5 0x00000034U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM4 0x00000030U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM3 0x0000002CU +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM2 0x00000028U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM1 0x00000024U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_APM0 0x00000020U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_APMRDBACKSEL_NOSEL 0x00000000U + +// Field: [1] ACSITERATIONS +// +// ENUMs: +// CODE23 4 iterations per ACS (4 branches, 2/3 codes) +// CODE12 2 iterations per ACS (2 branches, 1/2 codes) +#define LRFDMDM32_VITCOMPUTE_VITCTRL_ACSITERATIONS 0x00000002U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_ACSITERATIONS_M 0x00000002U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_ACSITERATIONS_S 1U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_ACSITERATIONS_CODE23 0x00000002U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_ACSITERATIONS_CODE12 0x00000000U + +// Field: [0] METRICS +// +// ENUMs: +// SOFT Use soft Metrics (register based) +// HW Use HW metrics as defined by VITCTRL.METRSEL bits +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRICS 0x00000001U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRICS_M 0x00000001U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRICS_S 0U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRICS_SOFT 0x00000001U +#define LRFDMDM32_VITCOMPUTE_VITCTRL_METRICS_HW 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_VITSTATE_VITAPMRDBACK +// +//***************************************************************************** +// Field: [18:16] VITSTATE_VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITSTATE_VALUE_W 3U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITSTATE_VALUE_M 0x00070000U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITSTATE_VALUE_S 16U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITSTATE_VALUE_ALLONES 0x00070000U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITSTATE_VALUE_ALLZEROS 0x00000000U + +// Field: [9:0] VITAPMRDBACK_VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITAPMRDBACK_VALUE_W 10U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITAPMRDBACK_VALUE_M 0x000003FFU +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITAPMRDBACK_VALUE_S 0U +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITAPMRDBACK_VALUE_ALLONES \ + 0x000003FFU +#define LRFDMDM32_VITSTATE_VITAPMRDBACK_VITAPMRDBACK_VALUE_ALLZEROS \ + 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_VITBRMETRIC32_VITBRMETRIC10 +// +//***************************************************************************** +// Field: [31:24] MET3 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET3_W 8U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET3_M 0xFF000000U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET3_S 24U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET3_ALLONES 0xFF000000U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET3_ALLZEROS 0x00000000U + +// Field: [23:16] MET2 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET2_W 8U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET2_M 0x00FF0000U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET2_S 16U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET2_ALLONES 0x00FF0000U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET2_ALLZEROS 0x00000000U + +// Field: [15:8] MET1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET1_W 8U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET1_M 0x0000FF00U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET1_S 8U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET1_ALLONES 0x0000FF00U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET1_ALLZEROS 0x00000000U + +// Field: [7:0] MET0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET0_W 8U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET0_M 0x000000FFU +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET0_S 0U +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET0_ALLONES 0x000000FFU +#define LRFDMDM32_VITBRMETRIC32_VITBRMETRIC10_MET0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_VITBRMETRIC76_VITBRMETRIC54 +// +//***************************************************************************** +// Field: [31:24] MET7 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET7_W 8U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET7_M 0xFF000000U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET7_S 24U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET7_ALLONES 0xFF000000U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET7_ALLZEROS 0x00000000U + +// Field: [23:16] MET6 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET6_W 8U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET6_M 0x00FF0000U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET6_S 16U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET6_ALLONES 0x00FF0000U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET6_ALLZEROS 0x00000000U + +// Field: [15:8] MET5 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET5_W 8U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET5_M 0x0000FF00U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET5_S 8U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET5_ALLONES 0x0000FF00U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET5_ALLZEROS 0x00000000U + +// Field: [7:0] MET4 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET4_W 8U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET4_M 0x000000FFU +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET4_S 0U +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET4_ALLONES 0x000000FFU +#define LRFDMDM32_VITBRMETRIC76_VITBRMETRIC54_MET4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_TIMCTL +// +//***************************************************************************** +// Field: [29:24] CPTSRC +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_TIMCTL_CPTSRC_W 6U +#define LRFDMDM32_TIMCTL_CPTSRC_M 0x3F000000U +#define LRFDMDM32_TIMCTL_CPTSRC_S 24U +#define LRFDMDM32_TIMCTL_CPTSRC_ALLONES 0x3F000000U +#define LRFDMDM32_TIMCTL_CPTSRC_ALLZEROS 0x00000000U + +// Field: [23] CPTCTL +// +// ENUMs: +// EN Enable capture mode for counter +// DIS Disable capture mode for counter +#define LRFDMDM32_TIMCTL_CPTCTL 0x00800000U +#define LRFDMDM32_TIMCTL_CPTCTL_M 0x00800000U +#define LRFDMDM32_TIMCTL_CPTCTL_S 23U +#define LRFDMDM32_TIMCTL_CPTCTL_EN 0x00800000U +#define LRFDMDM32_TIMCTL_CPTCTL_DIS 0x00000000U + +// Field: [22:21] CNTRSRC +// +// ENUMs: +// CLK4BAUDF Use 4xBaud flushed event +// CLK4BAUD Use 4xBaud event +// CLKBAUD Use baud event +// CLK Use clock +#define LRFDMDM32_TIMCTL_CNTRSRC_W 2U +#define LRFDMDM32_TIMCTL_CNTRSRC_M 0x00600000U +#define LRFDMDM32_TIMCTL_CNTRSRC_S 21U +#define LRFDMDM32_TIMCTL_CNTRSRC_CLK4BAUDF 0x00600000U +#define LRFDMDM32_TIMCTL_CNTRSRC_CLK4BAUD 0x00400000U +#define LRFDMDM32_TIMCTL_CNTRSRC_CLKBAUD 0x00200000U +#define LRFDMDM32_TIMCTL_CNTRSRC_CLK 0x00000000U + +// Field: [20] CNTRCLR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_TIMCTL_CNTRCLR 0x00100000U +#define LRFDMDM32_TIMCTL_CNTRCLR_M 0x00100000U +#define LRFDMDM32_TIMCTL_CNTRCLR_S 20U +#define LRFDMDM32_TIMCTL_CNTRCLR_ONE 0x00100000U +#define LRFDMDM32_TIMCTL_CNTRCLR_ZERO 0x00000000U + +// Field: [19] CNTRCTL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_TIMCTL_CNTRCTL 0x00080000U +#define LRFDMDM32_TIMCTL_CNTRCTL_M 0x00080000U +#define LRFDMDM32_TIMCTL_CNTRCTL_S 19U +#define LRFDMDM32_TIMCTL_CNTRCTL_ONE 0x00080000U +#define LRFDMDM32_TIMCTL_CNTRCTL_ZERO 0x00000000U + +// Field: [18:17] TIMSRC +// +// ENUMs: +// CLK4BAUDF 4xBaud flushed +// CLK4BAUD 4xBaud +// CLKBAUD Baud +// CLK Clock +#define LRFDMDM32_TIMCTL_TIMSRC_W 2U +#define LRFDMDM32_TIMCTL_TIMSRC_M 0x00060000U +#define LRFDMDM32_TIMCTL_TIMSRC_S 17U +#define LRFDMDM32_TIMCTL_TIMSRC_CLK4BAUDF 0x00060000U +#define LRFDMDM32_TIMCTL_TIMSRC_CLK4BAUD 0x00040000U +#define LRFDMDM32_TIMCTL_TIMSRC_CLKBAUD 0x00020000U +#define LRFDMDM32_TIMCTL_TIMSRC_CLK 0x00000000U + +// Field: [16] TIMCTL +// +// ENUMs: +// EN Will enable timer +// DIS Will disable timer and clear internal timer value +#define LRFDMDM32_TIMCTL_TIMCTL 0x00010000U +#define LRFDMDM32_TIMCTL_TIMCTL_M 0x00010000U +#define LRFDMDM32_TIMCTL_TIMCTL_S 16U +#define LRFDMDM32_TIMCTL_TIMCTL_EN 0x00010000U +#define LRFDMDM32_TIMCTL_TIMCTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_TIMPER_TIMINC +// +//***************************************************************************** +// Field: [31:16] TIMPER_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_TIMPER_TIMINC_TIMPER_VAL_W 16U +#define LRFDMDM32_TIMPER_TIMINC_TIMPER_VAL_M 0xFFFF0000U +#define LRFDMDM32_TIMPER_TIMINC_TIMPER_VAL_S 16U +#define LRFDMDM32_TIMPER_TIMINC_TIMPER_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_TIMPER_TIMINC_TIMPER_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] TIMINC_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_TIMPER_TIMINC_TIMINC_VAL_W 16U +#define LRFDMDM32_TIMPER_TIMINC_TIMINC_VAL_M 0x0000FFFFU +#define LRFDMDM32_TIMPER_TIMINC_TIMINC_VAL_S 0U +#define LRFDMDM32_TIMPER_TIMINC_TIMINC_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_TIMPER_TIMINC_TIMINC_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_TIMCAPT_TIMCNT +// +//***************************************************************************** +// Field: [31:16] VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_TIMCAPT_TIMCNT_VALUE_W 16U +#define LRFDMDM32_TIMCAPT_TIMCNT_VALUE_M 0xFFFF0000U +#define LRFDMDM32_TIMCAPT_TIMCNT_VALUE_S 16U +#define LRFDMDM32_TIMCAPT_TIMCNT_VALUE_ALLONES 0xFFFF0000U +#define LRFDMDM32_TIMCAPT_TIMCNT_VALUE_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_TIMCAPT_TIMCNT_VAL_W 16U +#define LRFDMDM32_TIMCAPT_TIMCNT_VAL_M 0x0000FFFFU +#define LRFDMDM32_TIMCAPT_TIMCNT_VAL_S 0U +#define LRFDMDM32_TIMCAPT_TIMCNT_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_TIMCAPT_TIMCNT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_COUNT1IN_TIMEBASE +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_COUNT1IN_TIMEBASE_VAL_W 16U +#define LRFDMDM32_COUNT1IN_TIMEBASE_VAL_M 0xFFFF0000U +#define LRFDMDM32_COUNT1IN_TIMEBASE_VAL_S 16U +#define LRFDMDM32_COUNT1IN_TIMEBASE_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_COUNT1IN_TIMEBASE_VAL_ALLZEROS 0x00000000U + +// Field: [0] FLUSH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_COUNT1IN_TIMEBASE_FLUSH 0x00000001U +#define LRFDMDM32_COUNT1IN_TIMEBASE_FLUSH_M 0x00000001U +#define LRFDMDM32_COUNT1IN_TIMEBASE_FLUSH_S 0U +#define LRFDMDM32_COUNT1IN_TIMEBASE_FLUSH_ONE 0x00000001U +#define LRFDMDM32_COUNT1IN_TIMEBASE_FLUSH_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_COUNT1RES +// +//***************************************************************************** +// Field: [4:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_COUNT1RES_VAL_W 5U +#define LRFDMDM32_COUNT1RES_VAL_M 0x0000001FU +#define LRFDMDM32_COUNT1RES_VAL_S 0U +#define LRFDMDM32_COUNT1RES_VAL_ALLONES 0x0000001FU +#define LRFDMDM32_COUNT1RES_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_BRMACC2_BRMACC1 +// +//***************************************************************************** +// Field: [31:24] METRIC11 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC11_W 8U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC11_M 0xFF000000U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC11_S 24U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC11_ALLONES 0xFF000000U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC11_ALLZEROS 0x00000000U + +// Field: [23:16] METRIC10 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC10_W 8U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC10_M 0x00FF0000U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC10_S 16U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC10_ALLONES 0x00FF0000U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC10_ALLZEROS 0x00000000U + +// Field: [15:8] METRIC01 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC01_W 8U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC01_M 0x0000FF00U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC01_S 8U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC01_ALLONES 0x0000FF00U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC01_ALLZEROS 0x00000000U + +// Field: [7:0] METRIC00 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC00_W 8U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC00_M 0x000000FFU +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC00_S 0U +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC00_ALLONES 0x000000FFU +#define LRFDMDM32_BRMACC2_BRMACC1_METRIC00_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MCETRCSTAT_MCETRCCTRL +// +//***************************************************************************** +// Field: [16] BUSY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_BUSY 0x00010000U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_BUSY_M 0x00010000U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_BUSY_S 16U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_BUSY_ONE 0x00010000U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_BUSY_ZERO 0x00000000U + +// Field: [0] SEND +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_SEND 0x00000001U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_SEND_M 0x00000001U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_SEND_S 0U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_SEND_ONE 0x00000001U +#define LRFDMDM32_MCETRCSTAT_MCETRCCTRL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_MCETRCPAR0_MCETRCCMD +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_VAL_W 16U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_VAL_M 0xFFFF0000U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_VAL_S 16U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_VAL_ALLONES 0xFFFF0000U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_VAL_ALLZEROS 0x00000000U + +// Field: [9:8] PARCNT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PARCNT_W 2U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PARCNT_M 0x00000300U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PARCNT_S 8U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PKTHDR_W 8U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PKTHDR_M 0x000000FFU +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PKTHDR_S 0U +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDMDM32_MCETRCPAR0_MCETRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_RDCAPT0_MCETRCPAR1 +// +//***************************************************************************** +// Field: [21] CHFI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CHFI 0x00200000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CHFI_M 0x00200000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CHFI_S 21U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CHFI_ONE 0x00200000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CHFI_ZERO 0x00000000U + +// Field: [20] BDE2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_BDE2 0x00100000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_BDE2_M 0x00100000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_BDE2_S 20U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_BDE2_ONE 0x00100000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_BDE2_ZERO 0x00000000U + +// Field: [19] FIDC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FIDC 0x00080000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FIDC_M 0x00080000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FIDC_S 19U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FIDC_ONE 0x00080000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FIDC_ZERO 0x00000000U + +// Field: [18] FRAC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FRAC 0x00040000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FRAC_M 0x00040000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FRAC_S 18U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FRAC_ONE 0x00040000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_FRAC_ZERO 0x00000000U + +// Field: [17] MGEX +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_MGEX 0x00020000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_MGEX_M 0x00020000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_MGEX_S 17U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_MGEX_ONE 0x00020000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_MGEX_ZERO 0x00000000U + +// Field: [16] CODC +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CODC 0x00010000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CODC_M 0x00010000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CODC_S 16U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CODC_ONE 0x00010000U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_CODC_ZERO 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_VAL_W 16U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_VAL_M 0x0000FFFFU +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_VAL_S 0U +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDMDM32_RDCAPT0_MCETRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_FECAPT0_RDCAPT1 +// +//***************************************************************************** +// Field: [28:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_VAL_W 13U +#define LRFDMDM32_FECAPT0_RDCAPT1_VAL_M 0x1FFF0000U +#define LRFDMDM32_FECAPT0_RDCAPT1_VAL_S 16U +#define LRFDMDM32_FECAPT0_RDCAPT1_VAL_ALLONES 0x1FFF0000U +#define LRFDMDM32_FECAPT0_RDCAPT1_VAL_ALLZEROS 0x00000000U + +// Field: [11] C1BEX2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX2 0x00000800U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX2_M 0x00000800U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX2_S 11U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX2_ONE 0x00000800U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX2_ZERO 0x00000000U + +// Field: [10] C1BEX1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX1 0x00000400U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX1_M 0x00000400U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX1_S 10U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX1_ONE 0x00000400U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX1_ZERO 0x00000000U + +// Field: [9] C1BEX0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX0 0x00000200U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX0_M 0x00000200U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX0_S 9U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX0_ONE 0x00000200U +#define LRFDMDM32_FECAPT0_RDCAPT1_C1BEX0_ZERO 0x00000000U + +// Field: [8] SOFD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_SOFD 0x00000100U +#define LRFDMDM32_FECAPT0_RDCAPT1_SOFD_M 0x00000100U +#define LRFDMDM32_FECAPT0_RDCAPT1_SOFD_S 8U +#define LRFDMDM32_FECAPT0_RDCAPT1_SOFD_ONE 0x00000100U +#define LRFDMDM32_FECAPT0_RDCAPT1_SOFD_ZERO 0x00000000U + +// Field: [7] LQIE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_LQIE 0x00000080U +#define LRFDMDM32_FECAPT0_RDCAPT1_LQIE_M 0x00000080U +#define LRFDMDM32_FECAPT0_RDCAPT1_LQIE_S 7U +#define LRFDMDM32_FECAPT0_RDCAPT1_LQIE_ONE 0x00000080U +#define LRFDMDM32_FECAPT0_RDCAPT1_LQIE_ZERO 0x00000000U + +// Field: [6] STIM +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_STIM 0x00000040U +#define LRFDMDM32_FECAPT0_RDCAPT1_STIM_M 0x00000040U +#define LRFDMDM32_FECAPT0_RDCAPT1_STIM_S 6U +#define LRFDMDM32_FECAPT0_RDCAPT1_STIM_ONE 0x00000040U +#define LRFDMDM32_FECAPT0_RDCAPT1_STIM_ZERO 0x00000000U + +// Field: [5] FIFE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_FIFE 0x00000020U +#define LRFDMDM32_FECAPT0_RDCAPT1_FIFE_M 0x00000020U +#define LRFDMDM32_FECAPT0_RDCAPT1_FIFE_S 5U +#define LRFDMDM32_FECAPT0_RDCAPT1_FIFE_ONE 0x00000020U +#define LRFDMDM32_FECAPT0_RDCAPT1_FIFE_ZERO 0x00000000U + +// Field: [4] PDIF +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_PDIF 0x00000010U +#define LRFDMDM32_FECAPT0_RDCAPT1_PDIF_M 0x00000010U +#define LRFDMDM32_FECAPT0_RDCAPT1_PDIF_S 4U +#define LRFDMDM32_FECAPT0_RDCAPT1_PDIF_ONE 0x00000010U +#define LRFDMDM32_FECAPT0_RDCAPT1_PDIF_ZERO 0x00000000U + +// Field: [3] CA2P +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_CA2P 0x00000008U +#define LRFDMDM32_FECAPT0_RDCAPT1_CA2P_M 0x00000008U +#define LRFDMDM32_FECAPT0_RDCAPT1_CA2P_S 3U +#define LRFDMDM32_FECAPT0_RDCAPT1_CA2P_ONE 0x00000008U +#define LRFDMDM32_FECAPT0_RDCAPT1_CA2P_ZERO 0x00000000U + +// Field: [2] MAFI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_MAFI 0x00000004U +#define LRFDMDM32_FECAPT0_RDCAPT1_MAFI_M 0x00000004U +#define LRFDMDM32_FECAPT0_RDCAPT1_MAFI_S 2U +#define LRFDMDM32_FECAPT0_RDCAPT1_MAFI_ONE 0x00000004U +#define LRFDMDM32_FECAPT0_RDCAPT1_MAFI_ZERO 0x00000000U + +// Field: [1] DSBU +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_DSBU 0x00000002U +#define LRFDMDM32_FECAPT0_RDCAPT1_DSBU_M 0x00000002U +#define LRFDMDM32_FECAPT0_RDCAPT1_DSBU_S 1U +#define LRFDMDM32_FECAPT0_RDCAPT1_DSBU_ONE 0x00000002U +#define LRFDMDM32_FECAPT0_RDCAPT1_DSBU_ZERO 0x00000000U + +// Field: [0] MLSEBIT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_FECAPT0_RDCAPT1_MLSEBIT 0x00000001U +#define LRFDMDM32_FECAPT0_RDCAPT1_MLSEBIT_M 0x00000001U +#define LRFDMDM32_FECAPT0_RDCAPT1_MLSEBIT_S 0U +#define LRFDMDM32_FECAPT0_RDCAPT1_MLSEBIT_ONE 0x00000001U +#define LRFDMDM32_FECAPT0_RDCAPT1_MLSEBIT_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DSCAPT0_FECAPT1 +// +//***************************************************************************** +// Field: [23:16] DSCAPT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DSCAPT0_FECAPT1_DSCAPT0_VAL_W 8U +#define LRFDMDM32_DSCAPT0_FECAPT1_DSCAPT0_VAL_M 0x00FF0000U +#define LRFDMDM32_DSCAPT0_FECAPT1_DSCAPT0_VAL_S 16U +#define LRFDMDM32_DSCAPT0_FECAPT1_DSCAPT0_VAL_ALLONES 0x00FF0000U +#define LRFDMDM32_DSCAPT0_FECAPT1_DSCAPT0_VAL_ALLZEROS 0x00000000U + +// Field: [12:0] FECAPT1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DSCAPT0_FECAPT1_FECAPT1_VAL_W 13U +#define LRFDMDM32_DSCAPT0_FECAPT1_FECAPT1_VAL_M 0x00001FFFU +#define LRFDMDM32_DSCAPT0_FECAPT1_FECAPT1_VAL_S 0U +#define LRFDMDM32_DSCAPT0_FECAPT1_FECAPT1_VAL_ALLONES 0x00001FFFU +#define LRFDMDM32_DSCAPT0_FECAPT1_FECAPT1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DSCAPT2_DSCAPT1 +// +//***************************************************************************** +// Field: [23:16] DSCAPT2_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT2_VAL_W 8U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT2_VAL_M 0x00FF0000U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT2_VAL_S 16U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT2_VAL_ALLONES 0x00FF0000U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT2_VAL_ALLZEROS 0x00000000U + +// Field: [7:0] DSCAPT1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT1_VAL_W 8U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT1_VAL_M 0x000000FFU +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT1_VAL_S 0U +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT1_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_DSCAPT2_DSCAPT1_DSCAPT1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_DEMSWQU1_DSCAPT3 +// +//***************************************************************************** +// Field: [25:18] MAFCCOMPVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWQU1_DSCAPT3_MAFCCOMPVAL_W 8U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_MAFCCOMPVAL_M 0x03FC0000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_MAFCCOMPVAL_S 18U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_MAFCCOMPVAL_ALLONES 0x03FC0000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_MAFCCOMPVAL_ALLZEROS 0x00000000U + +// Field: [17] SWSEL +// +// ENUMs: +// B The C1BE emitted a correlator B peak event and +// SWQU selected sync word B for qualification +// test +// A The C1BE emitted a correlator A peak event and +// SWQU selected sync word A for qualification +// test (or no SWQU sync word test has been +// performed yet) +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SWSEL 0x00020000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SWSEL_M 0x00020000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SWSEL_S 17U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SWSEL_B 0x00020000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SWSEL_A 0x00000000U + +// Field: [16] SYNCED +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SYNCED 0x00010000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SYNCED_M 0x00010000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SYNCED_S 16U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SYNCED_ONE 0x00010000U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_SYNCED_ZERO 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_DEMSWQU1_DSCAPT3_VAL_W 8U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_VAL_M 0x000000FFU +#define LRFDMDM32_DEMSWQU1_DSCAPT3_VAL_S 0U +#define LRFDMDM32_DEMSWQU1_DSCAPT3_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_DEMSWQU1_DSCAPT3_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_GPOCTRL1_GPOCTRL0 +// +//***************************************************************************** +// Field: [31:30] HWCLKSTRETCH +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKSTRETCH_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKSTRETCH_M 0xC0000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKSTRETCH_S 30U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKSTRETCH_ONE 0x40000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKSTRETCH_ZERO 0x00000000U + +// Field: [29:27] HWCLKMUX1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX1_W 3U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX1_M 0x38000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX1_S 27U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX1_ONE 0x08000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX1_ZERO 0x00000000U + +// Field: [26:24] HWCLKMUX0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX0_W 3U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX0_M 0x07000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX0_S 24U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX0_ONE 0x01000000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_HWCLKMUX0_ZERO 0x00000000U + +// Field: [23:16] SW +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_SW_W 8U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_SW_M 0x00FF0000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_SW_S 16U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_SW_ONE 0x00010000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_SW_ZERO 0x00000000U + +// Field: [15:14] GPO7 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// TOPSM_WAIT Output hardware clk +// SW7 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_M 0x0000C000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_S 14U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_THREE 0x0000C000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_TWO 0x00008000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_TOPSM_WAIT 0x00004000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO7_SW7 0x00000000U + +// Field: [13:12] GPO6 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// TRANSPARENT_OUT The bit is 1 +// SW6 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_M 0x00003000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_S 12U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_THREE 0x00003000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_TWO 0x00002000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_TRANSPARENT_OUT 0x00001000U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO6_SW6 0x00000000U + +// Field: [11:10] GPO5 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// DEM_OUT_WORD The bit is 1 +// SW5 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_M 0x00000C00U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_S 10U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_THREE 0x00000C00U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_TWO 0x00000800U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_DEM_OUT_WORD 0x00000400U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO5_SW5 0x00000000U + +// Field: [9:8] GPO4 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_C The bit is 1 +// SW4 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_M 0x00000300U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_S 8U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_THREE 0x00000300U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_TWO 0x00000200U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_CORR_PEAK_C 0x00000100U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO4_SW4 0x00000000U + +// Field: [7:6] GPO3 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_B The bit is 1 +// SW3 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_M 0x000000C0U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_S 6U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_THREE 0x000000C0U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_TWO 0x00000080U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_CORR_PEAK_B 0x00000040U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO3_SW3 0x00000000U + +// Field: [5:4] GPO2 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// CORR_PEAK_A The bit is 1 +// SW2 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_M 0x00000030U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_S 4U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_THREE 0x00000030U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_TWO 0x00000020U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_CORR_PEAK_A 0x00000010U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO2_SW2 0x00000000U + +// Field: [3:2] GPO1 +// +// ENUMs: +// THREE HW Source 3 +// TWO HW source 2 +// HWCLK1 Output Loopback symbol on pin MDMGPO1 +// SW1 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_M 0x0000000CU +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_S 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_THREE 0x0000000CU +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_TWO 0x00000008U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_HWCLK1 0x00000004U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO1_SW1 0x00000000U + +// Field: [1:0] GPO0 +// +// ENUMs: +// THREE HW Source 3 +// LOOPBACK HW source 2 +// HWCLK0 Output hardware clock on pin MDMGPO0 +// SW0 Output GPOCTRL1.SW +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_W 2U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_M 0x00000003U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_S 0U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_THREE 0x00000003U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_LOOPBACK 0x00000002U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_HWCLK0 0x00000001U +#define LRFDMDM32_GPOCTRL1_GPOCTRL0_GPO0_SW0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_RFEMAXRSSI_RFERSSI +// +//***************************************************************************** +// Field: [23:16] RFEMAXRSSI_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFEMAXRSSI_VAL_W 8U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFEMAXRSSI_VAL_M 0x00FF0000U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFEMAXRSSI_VAL_S 16U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFEMAXRSSI_VAL_ALLONES 0x00FF0000U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFEMAXRSSI_VAL_ALLZEROS 0x00000000U + +// Field: [7:0] RFERSSI_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFERSSI_VAL_W 8U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFERSSI_VAL_M 0x000000FFU +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFERSSI_VAL_S 0U +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFERSSI_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_RFEMAXRSSI_RFERSSI_RFERSSI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SYNC0_RFEDBGAIN +// +//***************************************************************************** +// Field: [31:16] SWA15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYNC0_RFEDBGAIN_SWA15C0_W 16U +#define LRFDMDM32_SYNC0_RFEDBGAIN_SWA15C0_M 0xFFFF0000U +#define LRFDMDM32_SYNC0_RFEDBGAIN_SWA15C0_S 16U +#define LRFDMDM32_SYNC0_RFEDBGAIN_SWA15C0_ALLONES 0xFFFF0000U +#define LRFDMDM32_SYNC0_RFEDBGAIN_SWA15C0_ALLZEROS 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYNC0_RFEDBGAIN_VAL_W 8U +#define LRFDMDM32_SYNC0_RFEDBGAIN_VAL_M 0x000000FFU +#define LRFDMDM32_SYNC0_RFEDBGAIN_VAL_S 0U +#define LRFDMDM32_SYNC0_RFEDBGAIN_VAL_ALLONES 0x000000FFU +#define LRFDMDM32_SYNC0_RFEDBGAIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SYNC2_SYNC1 +// +//***************************************************************************** +// Field: [31:16] SWB15C0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYNC2_SYNC1_SWB15C0_W 16U +#define LRFDMDM32_SYNC2_SYNC1_SWB15C0_M 0xFFFF0000U +#define LRFDMDM32_SYNC2_SYNC1_SWB15C0_S 16U +#define LRFDMDM32_SYNC2_SYNC1_SWB15C0_ALLONES 0xFFFF0000U +#define LRFDMDM32_SYNC2_SYNC1_SWB15C0_ALLZEROS 0x00000000U + +// Field: [15:0] SWA31C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYNC2_SYNC1_SWA31C16_W 16U +#define LRFDMDM32_SYNC2_SYNC1_SWA31C16_M 0x0000FFFFU +#define LRFDMDM32_SYNC2_SYNC1_SWA31C16_S 0U +#define LRFDMDM32_SYNC2_SYNC1_SWA31C16_ALLONES 0x0000FFFFU +#define LRFDMDM32_SYNC2_SYNC1_SWA31C16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDMDM32_O_SYNC3 +// +//***************************************************************************** +// Field: [15:0] SWB31C16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDMDM32_SYNC3_SWB31C16_W 16U +#define LRFDMDM32_SYNC3_SWB31C16_M 0x0000FFFFU +#define LRFDMDM32_SYNC3_SWB31C16_S 0U +#define LRFDMDM32_SYNC3_SWB31C16_ALLONES 0x0000FFFFU +#define LRFDMDM32_SYNC3_SWB31C16_ALLZEROS 0x00000000U + + +#endif // __LRFDMDM32__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe.h new file mode 100644 index 00000000..4b21474d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe.h @@ -0,0 +1,4495 @@ +/****************************************************************************** +* Filename: hw_lrfdpbe_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDPBE_H__ +#define __HW_LRFDPBE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDPBE component +// +//***************************************************************************** +// Packet Building Engine Enable Register +#define LRFDPBE_O_ENABLE 0x00000000U + +// PBE program source select register +#define LRFDPBE_O_FWSRC 0x00000004U + +// Packet Building Engine Initialization Register +#define LRFDPBE_O_INIT 0x00000008U + +// Packet Building Engine (PBE) Strobe Register 0 +#define LRFDPBE_O_STROBES0 0x0000000CU + +// Interrupt generate register +#define LRFDPBE_O_IRQ 0x00000010U + +// PBE Event Flag Register 0 +#define LRFDPBE_O_EVT0 0x00000014U + +// PBE Event Flag Register 1 +#define LRFDPBE_O_EVT1 0x00000018U + +// PBE Event Mask Register 0 +#define LRFDPBE_O_EVTMSK0 0x0000001CU + +// PBE Event Mask Register 1 +#define LRFDPBE_O_EVTMSK1 0x00000020U + +// PBE Event Clear Register 0 +#define LRFDPBE_O_EVTCLR0 0x00000024U + +// PBE Event Mask Register 1 +#define LRFDPBE_O_EVTCLR1 0x00000028U + +// Packet Building Engine Power-down Register +#define LRFDPBE_O_PDREQ 0x0000002CU + +// PBE API Command Register +#define LRFDPBE_O_API 0x00000030U + +// PBE-to-MCE Send Data Register +#define LRFDPBE_O_MCEDATOUT0 0x00000034U + +// MCE-to-PBE Receive Data Register +#define LRFDPBE_O_MCEDATIN0 0x00000038U + +// PBE-to-MCE Send Command Register +#define LRFDPBE_O_MCECMDOUT 0x0000003CU + +// MCE-to-PBE Receive Command Register +#define LRFDPBE_O_MCECMDIN 0x00000040U + +// Modem API Command Register +#define LRFDPBE_O_MDMAPI 0x00000044U + +// Modem Command Status Register +#define LRFDPBE_O_MDMMSGBOX 0x00000048U + +// Frequency Offset +#define LRFDPBE_O_FREQ 0x0000004CU + +// Link quality indicator +#define LRFDPBE_O_MDMLQI 0x00000050U + +// PBE-to-RFE Send Data Register +#define LRFDPBE_O_RFEDATOUT0 0x00000054U + +// RFE-to-PBE Receive Data Register +#define LRFDPBE_O_RFEDATIN0 0x00000058U + +// PBE-to-RFE Send Command Register +#define LRFDPBE_O_RFECMDOUT 0x0000005CU + +// RFE-to-PBE Receive Command Register +#define LRFDPBE_O_RFECMDIN 0x00000060U + +// RFE API Command Register +#define LRFDPBE_O_RFEAPI 0x00000064U + +// RFE Command Parameter 0 +#define LRFDPBE_O_RFECMDPAR0 0x00000068U + +// RFE Command Parameter 1 +#define LRFDPBE_O_RFECMDPAR1 0x0000006CU + +// RFE Command Status and Message Box Register +#define LRFDPBE_O_RFEMSGBOX 0x00000070U + +// RSSI Value Register +#define LRFDPBE_O_RFERSSI 0x00000074U + +// RSSI Maximum Value Register +#define LRFDPBE_O_RFERSSIMAX 0x00000078U + +// RF front-end gain value +#define LRFDPBE_O_RFERFGAIN 0x0000007CU + +// Modem Sync Word Register 0 +#define LRFDPBE_O_MDMSYNCAL 0x00000080U + +// Modem Sync Word Register 1 +#define LRFDPBE_O_MDMSYNCAH 0x00000084U + +// Modem Sync Word Register 2 +#define LRFDPBE_O_MDMSYNCBL 0x00000088U + +// Modem Sync Word Register 3 +#define LRFDPBE_O_MDMSYNCBH 0x0000008CU + +// Modem API Command Parameter 0 +#define LRFDPBE_O_MDMCMDPAR0 0x00000090U + +// Modem API Command Parameter 1 +#define LRFDPBE_O_MDMCMDPAR1 0x00000094U + +// Modem API Command Parameter 2 +#define LRFDPBE_O_MDMCMDPAR2 0x00000098U + +// LFSR 0 Polynomial Definition +#define LRFDPBE_O_POLY0L 0x000000A0U + +// LFSR 0 Polynomial Definition +#define LRFDPBE_O_POLY0H 0x000000A4U + +// LFSR 1 Polynomial Definition +#define LRFDPBE_O_POLY1L 0x000000A8U + +// LFSR 1 Polynomial Definition +#define LRFDPBE_O_POLY1H 0x000000ACU + +// Packet Handler Accelerator Config Register +#define LRFDPBE_O_PHACFG 0x000000B0U + +// FIFO configuration register +#define LRFDPBE_O_FCFG0 0x000000B4U + +// FIFO configuration register +#define LRFDPBE_O_FCFG1 0x000000B8U + +// FIFO configuration register +#define LRFDPBE_O_FCFG2 0x000000BCU + +// FIFO configuration register +#define LRFDPBE_O_FCFG3 0x000000C0U + +// FIFO configuration register +#define LRFDPBE_O_FCFG4 0x000000C4U + +// FIFO configuration register +#define LRFDPBE_O_FCFG5 0x000000C8U + +// FIFO write pointer +#define LRFDPBE_O_RXFWBTHRS 0x000000CCU + +// FIFO read pointer +#define LRFDPBE_O_RXFRBTHRS 0x000000D0U + +// FIFO write pointer +#define LRFDPBE_O_TXFWBTHRS 0x000000D4U + +// FIFO read pointer +#define LRFDPBE_O_TXFRBTHRS 0x000000D8U + +// PBE Timer Control Register +#define LRFDPBE_O_TIMCTL 0x000000DCU + +// Prescaler setting for timer 0 and timer 1 +#define LRFDPBE_O_TIMPRE 0x000000E0U + +// PBE Timer Period Configuration +#define LRFDPBE_O_TIMPER0 0x000000E4U + +// PBE Timer Period Configuration +#define LRFDPBE_O_TIMPER1 0x000000E8U + +// PBE Counter Capture Value +#define LRFDPBE_O_TIMCAPT0 0x000000ECU + +// PBE Counter Capture Value +#define LRFDPBE_O_TIMCAPT1 0x000000F0U + +// PBE Tracer Send Trigger Register +#define LRFDPBE_O_TRCCTL 0x00000100U + +// PBE Tracer Status Register +#define LRFDPBE_O_TRCSTAT 0x00000104U + +// PBE Tracer Commmand Register +#define LRFDPBE_O_TRCCMD 0x00000108U + +// PBE Tracer Command Parameter Register 0 +#define LRFDPBE_O_TRCPAR0 0x0000010CU + +// PBE Tracer Command Parameter Register 1 +#define LRFDPBE_O_TRCPAR1 0x00000110U + +// PBE Direct GPO control register +#define LRFDPBE_O_GPOCTRL 0x00000114U + +// Modem FIFO Write Register +#define LRFDPBE_O_MDMFWR 0x00000118U + +// Modem FIFO Read Register +#define LRFDPBE_O_MDMFRD 0x0000011CU + +// Modem FIFO Write Configuration +#define LRFDPBE_O_MDMFWRCTL 0x00000120U + +// Modem FIFO Read Configuration +#define LRFDPBE_O_MDMFRDCTL 0x00000124U + +// Modem FIFO Configuration for watermark thresholds +#define LRFDPBE_O_MDMFCFG 0x00000128U + +// Modem FIFO Status Flags +#define LRFDPBE_O_MDMFSTA 0x0000012CU + +// Packet Handler Accelerator Status +#define LRFDPBE_O_PHASTA 0x00000134U + +// LFSR 0 Current Value +#define LRFDPBE_O_LFSR0L 0x00000138U + +// LFSR 0 Current Value +#define LRFDPBE_O_LFSR0H 0x0000013CU + +// LFSR 0 Current Value, Bit-reversed +#define LRFDPBE_O_LFSR0BRL 0x00000140U + +// LFSR 0 Current Value, Bit-reversed +#define LRFDPBE_O_LFSR0BRH 0x00000144U + +// LFSR 1 Current Value +#define LRFDPBE_O_LFSR1L 0x00000148U + +// LFSR 1 Current Value +#define LRFDPBE_O_LFSR1H 0x0000014CU + +// LFSR 1 Current Value, Bit-reversed +#define LRFDPBE_O_LFSR1BRL 0x00000150U + +// LFSR 1 Current Value, Bit-reversed +#define LRFDPBE_O_LFSR1BRH 0x00000154U + +// LFSR 0 Input, LSB First +#define LRFDPBE_O_LFSR0INL 0x00000158U + +// Control input size of LSFR 0 +#define LRFDPBE_O_LFSR0N 0x0000015CU + +// LFSR 0 Input, MSB First +#define LRFDPBE_O_LFSR0INM 0x00000160U + +// LFSR 0 Output +#define LRFDPBE_O_PHAOUT0 0x00000164U + +// LFSR 1 Input, LSB First +#define LRFDPBE_O_LFSR1INL 0x00000168U + +// Controls input size of LFSR 1 +#define LRFDPBE_O_LFSR1N 0x0000016CU + +// LFSR 1 Input, MSB First +#define LRFDPBE_O_LFSR1INM 0x00000170U + +// LFSR 0 Output, Bit-reversed +#define LRFDPBE_O_PHAOUT0BR 0x00000174U + +// Systimer capture value +#define LRFDPBE_O_SYSTIM0L 0x00000180U + +// Systimer capture value +#define LRFDPBE_O_SYSTIM0H 0x00000184U + +// Systimer capture value +#define LRFDPBE_O_SYSTIM1L 0x00000188U + +// Systimer capture value +#define LRFDPBE_O_SYSTIM1H 0x0000018CU + +// Systimer capture value +#define LRFDPBE_O_SYSTIM2L 0x00000190U + +// Systimer capture value +#define LRFDPBE_O_SYSTIM2H 0x00000194U + +// PBE Direct GPI Status +#define LRFDPBE_O_GPI 0x00000198U + +// The FIFO command register +#define LRFDPBE_O_FCMD 0x000001A0U + +// FIFO status register +#define LRFDPBE_O_FSTAT 0x000001A4U + +// FIFO write pointer +#define LRFDPBE_O_RXFWP 0x000001A8U + +// FIFO read pointer +#define LRFDPBE_O_RXFRP 0x000001ACU + +// Rx FIFO start of written package +#define LRFDPBE_O_RXFSWP 0x000001B0U + +// Rxfifo start of read package. +#define LRFDPBE_O_RXFSRP 0x000001B4U + +// TXFIFO write pointer +#define LRFDPBE_O_TXFWP 0x000001B8U + +// TXFIFO read pointer +#define LRFDPBE_O_TXFRP 0x000001BCU + +// TXFIFO start of written package +#define LRFDPBE_O_TXFSWP 0x000001C0U + +// TXFIFO start of read package. +#define LRFDPBE_O_TXFSRP 0x000001C4U + +// The amount of bytes which are deallocated and not yet written. +#define LRFDPBE_O_RXFWRITABLE 0x000001C8U + +// The amount of bytes which are comitted and not yet read. +#define LRFDPBE_O_RXFREADABLE 0x000001CCU + +// The amount of bytes which are deallocated and not yet written. +#define LRFDPBE_O_TXFWRITABLE 0x000001D0U + +// The amount of bytes which are comitted and not yet read. +#define LRFDPBE_O_TXFREADABLE 0x000001D4U + +// FIFO read access register +#define LRFDPBE_O_RXFBRD 0x000001D8U + +// FIFO access register +#define LRFDPBE_O_RXFBWR 0x000001DCU + +// FIFO read access register +#define LRFDPBE_O_TXFBRD 0x000001E0U + +// FIFO access register +#define LRFDPBE_O_TXFBWR 0x000001E4U + +// FIFO read access register +#define LRFDPBE_O_RXFHRD 0x000001E8U + +// FIFO access register +#define LRFDPBE_O_RXFHWR 0x000001ECU + +// FIFO read access register +#define LRFDPBE_O_TXFHRD 0x000001F0U + +// FIFO access register +#define LRFDPBE_O_TXFHWR 0x000001F4U + +//***************************************************************************** +// +// Register: LRFDPBE_O_ENABLE +// +//***************************************************************************** +// Field: [2] MDMF +// +// Modem fifo, OR'ed with equivalent siganl in modem +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_ENABLE_MDMF 0x00000004U +#define LRFDPBE_ENABLE_MDMF_M 0x00000004U +#define LRFDPBE_ENABLE_MDMF_S 2U +#define LRFDPBE_ENABLE_MDMF_EN 0x00000004U +#define LRFDPBE_ENABLE_MDMF_DIS 0x00000000U + +// Field: [1] LOCTIM +// +// Enables the Local timer +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_ENABLE_LOCTIM 0x00000002U +#define LRFDPBE_ENABLE_LOCTIM_M 0x00000002U +#define LRFDPBE_ENABLE_LOCTIM_S 1U +#define LRFDPBE_ENABLE_LOCTIM_EN 0x00000002U +#define LRFDPBE_ENABLE_LOCTIM_DIS 0x00000000U + +// Field: [0] TOPSM +// +// Enables the TOPsm (PBE) +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_ENABLE_TOPSM 0x00000001U +#define LRFDPBE_ENABLE_TOPSM_M 0x00000001U +#define LRFDPBE_ENABLE_TOPSM_S 0U +#define LRFDPBE_ENABLE_TOPSM_EN 0x00000001U +#define LRFDPBE_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FWSRC +// +//***************************************************************************** +// Field: [2] DATARAM +// +// Selects which RAM will be used for data storage +// ENUMs: +// S2RRAM Use S2RRAM for data +// PBERAM Use PBERAM for data +#define LRFDPBE_FWSRC_DATARAM 0x00000004U +#define LRFDPBE_FWSRC_DATARAM_M 0x00000004U +#define LRFDPBE_FWSRC_DATARAM_S 2U +#define LRFDPBE_FWSRC_DATARAM_S2RRAM 0x00000004U +#define LRFDPBE_FWSRC_DATARAM_PBERAM 0x00000000U + +// Field: [1] FWRAM +// +// Select which RAM we run FW from +// ENUMs: +// S2RRAM Run code from S2RRAM +// PBERAM Run code from PBERAM +#define LRFDPBE_FWSRC_FWRAM 0x00000002U +#define LRFDPBE_FWSRC_FWRAM_M 0x00000002U +#define LRFDPBE_FWSRC_FWRAM_S 1U +#define LRFDPBE_FWSRC_FWRAM_S2RRAM 0x00000002U +#define LRFDPBE_FWSRC_FWRAM_PBERAM 0x00000000U + +// Field: [0] BANK +// +// Sets the MSB of the address to the memory holding the program. +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDPBE_FWSRC_BANK 0x00000001U +#define LRFDPBE_FWSRC_BANK_M 0x00000001U +#define LRFDPBE_FWSRC_BANK_S 0U +#define LRFDPBE_FWSRC_BANK_ONE 0x00000001U +#define LRFDPBE_FWSRC_BANK_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_INIT +// +//***************************************************************************** +// Field: [4] RFE +// +// Do an INIT of the TOPSM in RFE, OR'ed with equivalent signal in RFE +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_INIT_RFE 0x00000010U +#define LRFDPBE_INIT_RFE_M 0x00000010U +#define LRFDPBE_INIT_RFE_S 4U +#define LRFDPBE_INIT_RFE_RESET 0x00000010U +#define LRFDPBE_INIT_RFE_NO_EFFECT 0x00000000U + +// Field: [3] MDM +// +// Do an INIT of the TOPSM in MDM, OR'ed with equivalent signal in MDM +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_INIT_MDM 0x00000008U +#define LRFDPBE_INIT_MDM_M 0x00000008U +#define LRFDPBE_INIT_MDM_S 3U +#define LRFDPBE_INIT_MDM_RESET 0x00000008U +#define LRFDPBE_INIT_MDM_NO_EFFECT 0x00000000U + +// Field: [2] MDMF +// +// Modem FIFO, OR'ed with equivalent signal in MDM +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_INIT_MDMF 0x00000004U +#define LRFDPBE_INIT_MDMF_M 0x00000004U +#define LRFDPBE_INIT_MDMF_S 2U +#define LRFDPBE_INIT_MDMF_RESET 0x00000004U +#define LRFDPBE_INIT_MDMF_NO_EFFECT 0x00000000U + +// Field: [1] LOCTIM +// +// Synch reset Local timer +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_INIT_LOCTIM 0x00000002U +#define LRFDPBE_INIT_LOCTIM_M 0x00000002U +#define LRFDPBE_INIT_LOCTIM_S 1U +#define LRFDPBE_INIT_LOCTIM_RESET 0x00000002U +#define LRFDPBE_INIT_LOCTIM_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// Synch reset TOPsm (PBE) +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_INIT_TOPSM 0x00000001U +#define LRFDPBE_INIT_TOPSM_M 0x00000001U +#define LRFDPBE_INIT_TOPSM_S 0U +#define LRFDPBE_INIT_TOPSM_RESET 0x00000001U +#define LRFDPBE_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_STROBES0 +// +//***************************************************************************** +// Field: [6] TIMCAPT1 +// +// PBE timer 1 capture strobe +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_STROBES0_TIMCAPT1 0x00000040U +#define LRFDPBE_STROBES0_TIMCAPT1_M 0x00000040U +#define LRFDPBE_STROBES0_TIMCAPT1_S 6U +#define LRFDPBE_STROBES0_TIMCAPT1_ONE 0x00000040U +#define LRFDPBE_STROBES0_TIMCAPT1_ZERO 0x00000000U + +// Field: [5] TIMCAPT0 +// +// PBE timer 0 capture strobe +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_STROBES0_TIMCAPT0 0x00000020U +#define LRFDPBE_STROBES0_TIMCAPT0_M 0x00000020U +#define LRFDPBE_STROBES0_TIMCAPT0_S 5U +#define LRFDPBE_STROBES0_TIMCAPT0_ONE 0x00000020U +#define LRFDPBE_STROBES0_TIMCAPT0_ZERO 0x00000000U + +// Field: [4] S2RTRIG +// +// Arm/Trigger the S2R module +// ENUMs: +// ARM The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_STROBES0_S2RTRIG 0x00000010U +#define LRFDPBE_STROBES0_S2RTRIG_M 0x00000010U +#define LRFDPBE_STROBES0_S2RTRIG_S 4U +#define LRFDPBE_STROBES0_S2RTRIG_ARM 0x00000010U +#define LRFDPBE_STROBES0_S2RTRIG_NO_EFFECT 0x00000000U + +// Field: [3] DMATRIG +// +// FW triggered DMA transfer +// ENUMs: +// ARM The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE_STROBES0_DMATRIG 0x00000008U +#define LRFDPBE_STROBES0_DMATRIG_M 0x00000008U +#define LRFDPBE_STROBES0_DMATRIG_S 3U +#define LRFDPBE_STROBES0_DMATRIG_ARM 0x00000008U +#define LRFDPBE_STROBES0_DMATRIG_NO_EFFECT 0x00000000U + +// Field: [2] SYSTCAPT2 +// +// Systimer capture 2 strobe 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_STROBES0_SYSTCAPT2 0x00000004U +#define LRFDPBE_STROBES0_SYSTCAPT2_M 0x00000004U +#define LRFDPBE_STROBES0_SYSTCAPT2_S 2U +#define LRFDPBE_STROBES0_SYSTCAPT2_ONE 0x00000004U +#define LRFDPBE_STROBES0_SYSTCAPT2_ZERO 0x00000000U + +// Field: [1] SYSTCAPT1 +// +// Systimer capture1 strobe 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_STROBES0_SYSTCAPT1 0x00000002U +#define LRFDPBE_STROBES0_SYSTCAPT1_M 0x00000002U +#define LRFDPBE_STROBES0_SYSTCAPT1_S 1U +#define LRFDPBE_STROBES0_SYSTCAPT1_ONE 0x00000002U +#define LRFDPBE_STROBES0_SYSTCAPT1_ZERO 0x00000000U + +// Field: [0] SYSTCAPT0 +// +// Systimer capture 0 strobe 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_STROBES0_SYSTCAPT0 0x00000001U +#define LRFDPBE_STROBES0_SYSTCAPT0_M 0x00000001U +#define LRFDPBE_STROBES0_SYSTCAPT0_S 0U +#define LRFDPBE_STROBES0_SYSTCAPT0_ONE 0x00000001U +#define LRFDPBE_STROBES0_SYSTCAPT0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_IRQ +// +//***************************************************************************** +// Field: [15] SOFT15 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT15 0x00008000U +#define LRFDPBE_IRQ_SOFT15_M 0x00008000U +#define LRFDPBE_IRQ_SOFT15_S 15U +#define LRFDPBE_IRQ_SOFT15_ON 0x00008000U +#define LRFDPBE_IRQ_SOFT15_OFF 0x00000000U + +// Field: [14] SOFT14 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT14 0x00004000U +#define LRFDPBE_IRQ_SOFT14_M 0x00004000U +#define LRFDPBE_IRQ_SOFT14_S 14U +#define LRFDPBE_IRQ_SOFT14_ON 0x00004000U +#define LRFDPBE_IRQ_SOFT14_OFF 0x00000000U + +// Field: [13] SOFT13 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT13 0x00002000U +#define LRFDPBE_IRQ_SOFT13_M 0x00002000U +#define LRFDPBE_IRQ_SOFT13_S 13U +#define LRFDPBE_IRQ_SOFT13_ON 0x00002000U +#define LRFDPBE_IRQ_SOFT13_OFF 0x00000000U + +// Field: [12] SOFT12 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT12 0x00001000U +#define LRFDPBE_IRQ_SOFT12_M 0x00001000U +#define LRFDPBE_IRQ_SOFT12_S 12U +#define LRFDPBE_IRQ_SOFT12_ON 0x00001000U +#define LRFDPBE_IRQ_SOFT12_OFF 0x00000000U + +// Field: [11] SOFT11 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT11 0x00000800U +#define LRFDPBE_IRQ_SOFT11_M 0x00000800U +#define LRFDPBE_IRQ_SOFT11_S 11U +#define LRFDPBE_IRQ_SOFT11_ON 0x00000800U +#define LRFDPBE_IRQ_SOFT11_OFF 0x00000000U + +// Field: [10] SOFT10 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT10 0x00000400U +#define LRFDPBE_IRQ_SOFT10_M 0x00000400U +#define LRFDPBE_IRQ_SOFT10_S 10U +#define LRFDPBE_IRQ_SOFT10_ON 0x00000400U +#define LRFDPBE_IRQ_SOFT10_OFF 0x00000000U + +// Field: [9] SOFT9 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT9 0x00000200U +#define LRFDPBE_IRQ_SOFT9_M 0x00000200U +#define LRFDPBE_IRQ_SOFT9_S 9U +#define LRFDPBE_IRQ_SOFT9_ON 0x00000200U +#define LRFDPBE_IRQ_SOFT9_OFF 0x00000000U + +// Field: [8] SOFT8 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT8 0x00000100U +#define LRFDPBE_IRQ_SOFT8_M 0x00000100U +#define LRFDPBE_IRQ_SOFT8_S 8U +#define LRFDPBE_IRQ_SOFT8_ON 0x00000100U +#define LRFDPBE_IRQ_SOFT8_OFF 0x00000000U + +// Field: [7] SOFT7 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT7 0x00000080U +#define LRFDPBE_IRQ_SOFT7_M 0x00000080U +#define LRFDPBE_IRQ_SOFT7_S 7U +#define LRFDPBE_IRQ_SOFT7_ON 0x00000080U +#define LRFDPBE_IRQ_SOFT7_OFF 0x00000000U + +// Field: [6] SOFT6 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT6 0x00000040U +#define LRFDPBE_IRQ_SOFT6_M 0x00000040U +#define LRFDPBE_IRQ_SOFT6_S 6U +#define LRFDPBE_IRQ_SOFT6_ON 0x00000040U +#define LRFDPBE_IRQ_SOFT6_OFF 0x00000000U + +// Field: [5] SOFT5 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT5 0x00000020U +#define LRFDPBE_IRQ_SOFT5_M 0x00000020U +#define LRFDPBE_IRQ_SOFT5_S 5U +#define LRFDPBE_IRQ_SOFT5_ON 0x00000020U +#define LRFDPBE_IRQ_SOFT5_OFF 0x00000000U + +// Field: [4] SOFT4 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT4 0x00000010U +#define LRFDPBE_IRQ_SOFT4_M 0x00000010U +#define LRFDPBE_IRQ_SOFT4_S 4U +#define LRFDPBE_IRQ_SOFT4_ON 0x00000010U +#define LRFDPBE_IRQ_SOFT4_OFF 0x00000000U + +// Field: [3] SOFT3 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT3 0x00000008U +#define LRFDPBE_IRQ_SOFT3_M 0x00000008U +#define LRFDPBE_IRQ_SOFT3_S 3U +#define LRFDPBE_IRQ_SOFT3_ON 0x00000008U +#define LRFDPBE_IRQ_SOFT3_OFF 0x00000000U + +// Field: [2] SOFT2 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT2 0x00000004U +#define LRFDPBE_IRQ_SOFT2_M 0x00000004U +#define LRFDPBE_IRQ_SOFT2_S 2U +#define LRFDPBE_IRQ_SOFT2_ON 0x00000004U +#define LRFDPBE_IRQ_SOFT2_OFF 0x00000000U + +// Field: [1] SOFT1 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT1 0x00000002U +#define LRFDPBE_IRQ_SOFT1_M 0x00000002U +#define LRFDPBE_IRQ_SOFT1_S 1U +#define LRFDPBE_IRQ_SOFT1_ON 0x00000002U +#define LRFDPBE_IRQ_SOFT1_OFF 0x00000000U + +// Field: [0] SOFT0 +// +// Software defined interrupt +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_IRQ_SOFT0 0x00000001U +#define LRFDPBE_IRQ_SOFT0_M 0x00000001U +#define LRFDPBE_IRQ_SOFT0_S 0U +#define LRFDPBE_IRQ_SOFT0_ON 0x00000001U +#define LRFDPBE_IRQ_SOFT0_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVT0 +// +//***************************************************************************** +// Field: [15] MDMFAEMPTY +// +// Modem fifo is emptied below the empty threshold +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_MDMFAEMPTY 0x00008000U +#define LRFDPBE_EVT0_MDMFAEMPTY_M 0x00008000U +#define LRFDPBE_EVT0_MDMFAEMPTY_S 15U +#define LRFDPBE_EVT0_MDMFAEMPTY_ONE 0x00008000U +#define LRFDPBE_EVT0_MDMFAEMPTY_ZERO 0x00000000U + +// Field: [14] S2RSTOP +// +// S2R has written to the STOP_ADDRESS location +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_S2RSTOP 0x00004000U +#define LRFDPBE_EVT0_S2RSTOP_M 0x00004000U +#define LRFDPBE_EVT0_S2RSTOP_S 14U +#define LRFDPBE_EVT0_S2RSTOP_ONE 0x00004000U +#define LRFDPBE_EVT0_S2RSTOP_ZERO 0x00000000U + +// Field: [13] FIFOERR +// +// Error event from fifo +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_FIFOERR 0x00002000U +#define LRFDPBE_EVT0_FIFOERR_M 0x00002000U +#define LRFDPBE_EVT0_FIFOERR_S 13U +#define LRFDPBE_EVT0_FIFOERR_ONE 0x00002000U +#define LRFDPBE_EVT0_FIFOERR_ZERO 0x00000000U + +// Field: [12] MDMFAFULL +// +// Modem fifo is filled above the threshold +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_MDMFAFULL 0x00001000U +#define LRFDPBE_EVT0_MDMFAFULL_M 0x00001000U +#define LRFDPBE_EVT0_MDMFAFULL_S 12U +#define LRFDPBE_EVT0_MDMFAFULL_ONE 0x00001000U +#define LRFDPBE_EVT0_MDMFAFULL_ZERO 0x00000000U + +// Field: [11] SYSTCMP2 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_SYSTCMP2 0x00000800U +#define LRFDPBE_EVT0_SYSTCMP2_M 0x00000800U +#define LRFDPBE_EVT0_SYSTCMP2_S 11U +#define LRFDPBE_EVT0_SYSTCMP2_ONE 0x00000800U +#define LRFDPBE_EVT0_SYSTCMP2_ZERO 0x00000000U + +// Field: [10] SYSTCMP1 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_SYSTCMP1 0x00000400U +#define LRFDPBE_EVT0_SYSTCMP1_M 0x00000400U +#define LRFDPBE_EVT0_SYSTCMP1_S 10U +#define LRFDPBE_EVT0_SYSTCMP1_ONE 0x00000400U +#define LRFDPBE_EVT0_SYSTCMP1_ZERO 0x00000000U + +// Field: [9] SYSTCMP0 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_SYSTCMP0 0x00000200U +#define LRFDPBE_EVT0_SYSTCMP0_M 0x00000200U +#define LRFDPBE_EVT0_SYSTCMP0_S 9U +#define LRFDPBE_EVT0_SYSTCMP0_ONE 0x00000200U +#define LRFDPBE_EVT0_SYSTCMP0_ZERO 0x00000000U + +// Field: [8] MDMMSGBOX +// +// New command status from MCE received in MDMMSGBOX register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_MDMMSGBOX 0x00000100U +#define LRFDPBE_EVT0_MDMMSGBOX_M 0x00000100U +#define LRFDPBE_EVT0_MDMMSGBOX_S 8U +#define LRFDPBE_EVT0_MDMMSGBOX_ONE 0x00000100U +#define LRFDPBE_EVT0_MDMMSGBOX_ZERO 0x00000000U + +// Field: [7] RFEMSGBOX +// +// New command status from RFE received in RFEMSGBOX register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_RFEMSGBOX 0x00000080U +#define LRFDPBE_EVT0_RFEMSGBOX_M 0x00000080U +#define LRFDPBE_EVT0_RFEMSGBOX_S 7U +#define LRFDPBE_EVT0_RFEMSGBOX_ONE 0x00000080U +#define LRFDPBE_EVT0_RFEMSGBOX_ZERO 0x00000000U + +// Field: [6] RFEDAT +// +// New data from RFE received in RFEDATIN0 register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_RFEDAT 0x00000040U +#define LRFDPBE_EVT0_RFEDAT_M 0x00000040U +#define LRFDPBE_EVT0_RFEDAT_S 6U +#define LRFDPBE_EVT0_RFEDAT_ONE 0x00000040U +#define LRFDPBE_EVT0_RFEDAT_ZERO 0x00000000U + +// Field: [5] RFECMD +// +// New command from RFE received in RFECMDIN register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_RFECMD 0x00000020U +#define LRFDPBE_EVT0_RFECMD_M 0x00000020U +#define LRFDPBE_EVT0_RFECMD_S 5U +#define LRFDPBE_EVT0_RFECMD_ONE 0x00000020U +#define LRFDPBE_EVT0_RFECMD_ZERO 0x00000000U + +// Field: [4] MDMDAT +// +// New data from MCE received in MCEDATIN0 register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_MDMDAT 0x00000010U +#define LRFDPBE_EVT0_MDMDAT_M 0x00000010U +#define LRFDPBE_EVT0_MDMDAT_S 4U +#define LRFDPBE_EVT0_MDMDAT_ONE 0x00000010U +#define LRFDPBE_EVT0_MDMDAT_ZERO 0x00000000U + +// Field: [3] MDMCMD +// +// New command from MCE received in MCECMDIN register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_MDMCMD 0x00000008U +#define LRFDPBE_EVT0_MDMCMD_M 0x00000008U +#define LRFDPBE_EVT0_MDMCMD_S 3U +#define LRFDPBE_EVT0_MDMCMD_ONE 0x00000008U +#define LRFDPBE_EVT0_MDMCMD_ZERO 0x00000000U + +// Field: [2] TIMER1 +// +// Counter value reached in local timer. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_TIMER1 0x00000004U +#define LRFDPBE_EVT0_TIMER1_M 0x00000004U +#define LRFDPBE_EVT0_TIMER1_S 2U +#define LRFDPBE_EVT0_TIMER1_ONE 0x00000004U +#define LRFDPBE_EVT0_TIMER1_ZERO 0x00000000U + +// Field: [1] TIMER0 +// +// Timer period expired in local timer. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_TIMER0 0x00000002U +#define LRFDPBE_EVT0_TIMER0_M 0x00000002U +#define LRFDPBE_EVT0_TIMER0_S 1U +#define LRFDPBE_EVT0_TIMER0_ONE 0x00000002U +#define LRFDPBE_EVT0_TIMER0_ZERO 0x00000000U + +// Field: [0] PBEAPI +// +// New command from CPE has been written in API register. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT0_PBEAPI 0x00000001U +#define LRFDPBE_EVT0_PBEAPI_M 0x00000001U +#define LRFDPBE_EVT0_PBEAPI_S 0U +#define LRFDPBE_EVT0_PBEAPI_ONE 0x00000001U +#define LRFDPBE_EVT0_PBEAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVT1 +// +//***************************************************************************** +// Field: [12] TXRDBTHR +// +// The TX FIFO contains TXFRBTHRS or more readable bytes. +// ENUMs: +// MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE_EVT1_TXRDBTHR 0x00001000U +#define LRFDPBE_EVT1_TXRDBTHR_M 0x00001000U +#define LRFDPBE_EVT1_TXRDBTHR_S 12U +#define LRFDPBE_EVT1_TXRDBTHR_MET 0x00001000U +#define LRFDPBE_EVT1_TXRDBTHR_BELOW 0x00000000U + +// Field: [11] TXWRBTHR +// +// The TX FIFO contains TXFWBTHRS or more writable bytes. +// ENUMs: +// MET The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE_EVT1_TXWRBTHR 0x00000800U +#define LRFDPBE_EVT1_TXWRBTHR_M 0x00000800U +#define LRFDPBE_EVT1_TXWRBTHR_S 11U +#define LRFDPBE_EVT1_TXWRBTHR_MET 0x00000800U +#define LRFDPBE_EVT1_TXWRBTHR_BELOW 0x00000000U + +// Field: [10] RXRDBTHR +// +// The RX FIFO contains RXFRBTHRS or more readable bytes. +// ENUMs: +// MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE_EVT1_RXRDBTHR 0x00000400U +#define LRFDPBE_EVT1_RXRDBTHR_M 0x00000400U +#define LRFDPBE_EVT1_RXRDBTHR_S 10U +#define LRFDPBE_EVT1_RXRDBTHR_MET 0x00000400U +#define LRFDPBE_EVT1_RXRDBTHR_BELOW 0x00000000U + +// Field: [9] RXWRBTHR +// +// The RX FIFO contains RXFWBTHRS or more writable bytes. +// ENUMs: +// MET The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// BELOW The RX FIFO contains less than the threshold +// RXFWBTHRS writable bytes. +#define LRFDPBE_EVT1_RXWRBTHR 0x00000200U +#define LRFDPBE_EVT1_RXWRBTHR_M 0x00000200U +#define LRFDPBE_EVT1_RXWRBTHR_S 9U +#define LRFDPBE_EVT1_RXWRBTHR_MET 0x00000200U +#define LRFDPBE_EVT1_RXWRBTHR_BELOW 0x00000000U + +// Field: [8] MDMPROG +// +// Programmable event from modem +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_MDMPROG 0x00000100U +#define LRFDPBE_EVT1_MDMPROG_M 0x00000100U +#define LRFDPBE_EVT1_MDMPROG_S 8U +#define LRFDPBE_EVT1_MDMPROG_ONE 0x00000100U +#define LRFDPBE_EVT1_MDMPROG_ZERO 0x00000000U + +// Field: [7] PBEGPI7 +// +// External input event line GPI7 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI7 0x00000080U +#define LRFDPBE_EVT1_PBEGPI7_M 0x00000080U +#define LRFDPBE_EVT1_PBEGPI7_S 7U +#define LRFDPBE_EVT1_PBEGPI7_ONE 0x00000080U +#define LRFDPBE_EVT1_PBEGPI7_ZERO 0x00000000U + +// Field: [6] PBEGPI6 +// +// External input event line GPI6 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI6 0x00000040U +#define LRFDPBE_EVT1_PBEGPI6_M 0x00000040U +#define LRFDPBE_EVT1_PBEGPI6_S 6U +#define LRFDPBE_EVT1_PBEGPI6_ONE 0x00000040U +#define LRFDPBE_EVT1_PBEGPI6_ZERO 0x00000000U + +// Field: [5] PBEGPI5 +// +// External input event line GPI5 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI5 0x00000020U +#define LRFDPBE_EVT1_PBEGPI5_M 0x00000020U +#define LRFDPBE_EVT1_PBEGPI5_S 5U +#define LRFDPBE_EVT1_PBEGPI5_ONE 0x00000020U +#define LRFDPBE_EVT1_PBEGPI5_ZERO 0x00000000U + +// Field: [4] PBEGPI4 +// +// External input event line GPI4 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI4 0x00000010U +#define LRFDPBE_EVT1_PBEGPI4_M 0x00000010U +#define LRFDPBE_EVT1_PBEGPI4_S 4U +#define LRFDPBE_EVT1_PBEGPI4_ONE 0x00000010U +#define LRFDPBE_EVT1_PBEGPI4_ZERO 0x00000000U + +// Field: [3] PBEGPI3 +// +// External input event line GPI3 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI3 0x00000008U +#define LRFDPBE_EVT1_PBEGPI3_M 0x00000008U +#define LRFDPBE_EVT1_PBEGPI3_S 3U +#define LRFDPBE_EVT1_PBEGPI3_ONE 0x00000008U +#define LRFDPBE_EVT1_PBEGPI3_ZERO 0x00000000U + +// Field: [2] PBEGPI2 +// +// External input event line GPI2 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI2 0x00000004U +#define LRFDPBE_EVT1_PBEGPI2_M 0x00000004U +#define LRFDPBE_EVT1_PBEGPI2_S 2U +#define LRFDPBE_EVT1_PBEGPI2_ONE 0x00000004U +#define LRFDPBE_EVT1_PBEGPI2_ZERO 0x00000000U + +// Field: [1] PBEGPI1 +// +// External input event line GPI1 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI1 0x00000002U +#define LRFDPBE_EVT1_PBEGPI1_M 0x00000002U +#define LRFDPBE_EVT1_PBEGPI1_S 1U +#define LRFDPBE_EVT1_PBEGPI1_ONE 0x00000002U +#define LRFDPBE_EVT1_PBEGPI1_ZERO 0x00000000U + +// Field: [0] PBEGPI0 +// +// External input event line GPI0 from IOC. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_EVT1_PBEGPI0 0x00000001U +#define LRFDPBE_EVT1_PBEGPI0_M 0x00000001U +#define LRFDPBE_EVT1_PBEGPI0_S 0U +#define LRFDPBE_EVT1_PBEGPI0_ONE 0x00000001U +#define LRFDPBE_EVT1_PBEGPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVTMSK0 +// +//***************************************************************************** +// Field: [15] MDMFAEMPTY +// +// Enable mask for event EVT0.MDMFAEMPTY +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_MDMFAEMPTY 0x00008000U +#define LRFDPBE_EVTMSK0_MDMFAEMPTY_M 0x00008000U +#define LRFDPBE_EVTMSK0_MDMFAEMPTY_S 15U +#define LRFDPBE_EVTMSK0_MDMFAEMPTY_EN 0x00008000U +#define LRFDPBE_EVTMSK0_MDMFAEMPTY_DIS 0x00000000U + +// Field: [14] S2RSTOP +// +// Enable mask for event EVT0.S2RSTOP +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_S2RSTOP 0x00004000U +#define LRFDPBE_EVTMSK0_S2RSTOP_M 0x00004000U +#define LRFDPBE_EVTMSK0_S2RSTOP_S 14U +#define LRFDPBE_EVTMSK0_S2RSTOP_EN 0x00004000U +#define LRFDPBE_EVTMSK0_S2RSTOP_DIS 0x00000000U + +// Field: [13] FIFOERR +// +// Enable mask for event EVT0.FIFOERR +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_FIFOERR 0x00002000U +#define LRFDPBE_EVTMSK0_FIFOERR_M 0x00002000U +#define LRFDPBE_EVTMSK0_FIFOERR_S 13U +#define LRFDPBE_EVTMSK0_FIFOERR_EN 0x00002000U +#define LRFDPBE_EVTMSK0_FIFOERR_DIS 0x00000000U + +// Field: [12] MDMFAFULL +// +// Enable mask for event EVT0.MDMFAFULL +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_MDMFAFULL 0x00001000U +#define LRFDPBE_EVTMSK0_MDMFAFULL_M 0x00001000U +#define LRFDPBE_EVTMSK0_MDMFAFULL_S 12U +#define LRFDPBE_EVTMSK0_MDMFAFULL_EN 0x00001000U +#define LRFDPBE_EVTMSK0_MDMFAFULL_DIS 0x00000000U + +// Field: [11] SYSTCMP2 +// +// Enable mask for event EVT0.SYSTCMP2 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_SYSTCMP2 0x00000800U +#define LRFDPBE_EVTMSK0_SYSTCMP2_M 0x00000800U +#define LRFDPBE_EVTMSK0_SYSTCMP2_S 11U +#define LRFDPBE_EVTMSK0_SYSTCMP2_EN 0x00000800U +#define LRFDPBE_EVTMSK0_SYSTCMP2_DIS 0x00000000U + +// Field: [10] SYSTCMP1 +// +// Enable mask for event EVT0.SYSTCMP1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_SYSTCMP1 0x00000400U +#define LRFDPBE_EVTMSK0_SYSTCMP1_M 0x00000400U +#define LRFDPBE_EVTMSK0_SYSTCMP1_S 10U +#define LRFDPBE_EVTMSK0_SYSTCMP1_EN 0x00000400U +#define LRFDPBE_EVTMSK0_SYSTCMP1_DIS 0x00000000U + +// Field: [9] SYSTCMP0 +// +// Enable mask for event EVT0.SYSTCMP0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_SYSTCMP0 0x00000200U +#define LRFDPBE_EVTMSK0_SYSTCMP0_M 0x00000200U +#define LRFDPBE_EVTMSK0_SYSTCMP0_S 9U +#define LRFDPBE_EVTMSK0_SYSTCMP0_EN 0x00000200U +#define LRFDPBE_EVTMSK0_SYSTCMP0_DIS 0x00000000U + +// Field: [8] MDMMSGBOX +// +// Enable mask for event EVT0.MDMMSGBOX +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_MDMMSGBOX 0x00000100U +#define LRFDPBE_EVTMSK0_MDMMSGBOX_M 0x00000100U +#define LRFDPBE_EVTMSK0_MDMMSGBOX_S 8U +#define LRFDPBE_EVTMSK0_MDMMSGBOX_EN 0x00000100U +#define LRFDPBE_EVTMSK0_MDMMSGBOX_DIS 0x00000000U + +// Field: [7] RFEMSGBOX +// +// Enable mask for event EVT0.RFEMSGBOX +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_RFEMSGBOX 0x00000080U +#define LRFDPBE_EVTMSK0_RFEMSGBOX_M 0x00000080U +#define LRFDPBE_EVTMSK0_RFEMSGBOX_S 7U +#define LRFDPBE_EVTMSK0_RFEMSGBOX_EN 0x00000080U +#define LRFDPBE_EVTMSK0_RFEMSGBOX_DIS 0x00000000U + +// Field: [6] RFEDAT +// +// Enable mask for event EVT0.RFEDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_RFEDAT 0x00000040U +#define LRFDPBE_EVTMSK0_RFEDAT_M 0x00000040U +#define LRFDPBE_EVTMSK0_RFEDAT_S 6U +#define LRFDPBE_EVTMSK0_RFEDAT_EN 0x00000040U +#define LRFDPBE_EVTMSK0_RFEDAT_DIS 0x00000000U + +// Field: [5] RFECMD +// +// Enable mask for event EVT0.RFECMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_RFECMD 0x00000020U +#define LRFDPBE_EVTMSK0_RFECMD_M 0x00000020U +#define LRFDPBE_EVTMSK0_RFECMD_S 5U +#define LRFDPBE_EVTMSK0_RFECMD_EN 0x00000020U +#define LRFDPBE_EVTMSK0_RFECMD_DIS 0x00000000U + +// Field: [4] MDMDAT +// +// Enable mask for event EVT0.MDMDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_MDMDAT 0x00000010U +#define LRFDPBE_EVTMSK0_MDMDAT_M 0x00000010U +#define LRFDPBE_EVTMSK0_MDMDAT_S 4U +#define LRFDPBE_EVTMSK0_MDMDAT_EN 0x00000010U +#define LRFDPBE_EVTMSK0_MDMDAT_DIS 0x00000000U + +// Field: [3] MDMCMD +// +// Enable mask for event EVT0.MDMCMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_MDMCMD 0x00000008U +#define LRFDPBE_EVTMSK0_MDMCMD_M 0x00000008U +#define LRFDPBE_EVTMSK0_MDMCMD_S 3U +#define LRFDPBE_EVTMSK0_MDMCMD_EN 0x00000008U +#define LRFDPBE_EVTMSK0_MDMCMD_DIS 0x00000000U + +// Field: [2] TIMER1 +// +// Enable mask for event EVT0.TIMER1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_TIMER1 0x00000004U +#define LRFDPBE_EVTMSK0_TIMER1_M 0x00000004U +#define LRFDPBE_EVTMSK0_TIMER1_S 2U +#define LRFDPBE_EVTMSK0_TIMER1_EN 0x00000004U +#define LRFDPBE_EVTMSK0_TIMER1_DIS 0x00000000U + +// Field: [1] TIMER0 +// +// Enable mask for event EVT0.TIMER0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_TIMER0 0x00000002U +#define LRFDPBE_EVTMSK0_TIMER0_M 0x00000002U +#define LRFDPBE_EVTMSK0_TIMER0_S 1U +#define LRFDPBE_EVTMSK0_TIMER0_EN 0x00000002U +#define LRFDPBE_EVTMSK0_TIMER0_DIS 0x00000000U + +// Field: [0] PBEAPI +// +// Enable mask for event EVT0.PBEAPI +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK0_PBEAPI 0x00000001U +#define LRFDPBE_EVTMSK0_PBEAPI_M 0x00000001U +#define LRFDPBE_EVTMSK0_PBEAPI_S 0U +#define LRFDPBE_EVTMSK0_PBEAPI_EN 0x00000001U +#define LRFDPBE_EVTMSK0_PBEAPI_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVTMSK1 +// +//***************************************************************************** +// Field: [12] TXRDBTHR +// +// Enable mask for event EVT0.TXRDBTHR +// ENUMs: +// EN The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE_EVTMSK1_TXRDBTHR 0x00001000U +#define LRFDPBE_EVTMSK1_TXRDBTHR_M 0x00001000U +#define LRFDPBE_EVTMSK1_TXRDBTHR_S 12U +#define LRFDPBE_EVTMSK1_TXRDBTHR_EN 0x00001000U +#define LRFDPBE_EVTMSK1_TXRDBTHR_DIS 0x00000000U + +// Field: [11] TXWRBTHR +// +// Enable mask for event EVT0.TXWRBTHR +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE_EVTMSK1_TXWRBTHR 0x00000800U +#define LRFDPBE_EVTMSK1_TXWRBTHR_M 0x00000800U +#define LRFDPBE_EVTMSK1_TXWRBTHR_S 11U +#define LRFDPBE_EVTMSK1_TXWRBTHR_EN 0x00000800U +#define LRFDPBE_EVTMSK1_TXWRBTHR_DIS 0x00000000U + +// Field: [10] RXRDBTHR +// +// Enable mask for event EVT0.RXRDBTHR +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE_EVTMSK1_RXRDBTHR 0x00000400U +#define LRFDPBE_EVTMSK1_RXRDBTHR_M 0x00000400U +#define LRFDPBE_EVTMSK1_RXRDBTHR_S 10U +#define LRFDPBE_EVTMSK1_RXRDBTHR_EN 0x00000400U +#define LRFDPBE_EVTMSK1_RXRDBTHR_DIS 0x00000000U + +// Field: [9] RXWRBTHR +// +// Enable mask for event EVT0.RXWRBTHR +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE_EVTMSK1_RXWRBTHR 0x00000200U +#define LRFDPBE_EVTMSK1_RXWRBTHR_M 0x00000200U +#define LRFDPBE_EVTMSK1_RXWRBTHR_S 9U +#define LRFDPBE_EVTMSK1_RXWRBTHR_EN 0x00000200U +#define LRFDPBE_EVTMSK1_RXWRBTHR_DIS 0x00000000U + +// Field: [8] MDMPROG +// +// Enable mask for event EVT0.MDMPROG +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_MDMPROG 0x00000100U +#define LRFDPBE_EVTMSK1_MDMPROG_M 0x00000100U +#define LRFDPBE_EVTMSK1_MDMPROG_S 8U +#define LRFDPBE_EVTMSK1_MDMPROG_EN 0x00000100U +#define LRFDPBE_EVTMSK1_MDMPROG_DIS 0x00000000U + +// Field: [7] PBEGPI7 +// +// Enable mask for event EVT0.PBEGPI7 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI7 0x00000080U +#define LRFDPBE_EVTMSK1_PBEGPI7_M 0x00000080U +#define LRFDPBE_EVTMSK1_PBEGPI7_S 7U +#define LRFDPBE_EVTMSK1_PBEGPI7_EN 0x00000080U +#define LRFDPBE_EVTMSK1_PBEGPI7_DIS 0x00000000U + +// Field: [6] PBEGPI6 +// +// Enable mask for event EVT0.PBEGPI6 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI6 0x00000040U +#define LRFDPBE_EVTMSK1_PBEGPI6_M 0x00000040U +#define LRFDPBE_EVTMSK1_PBEGPI6_S 6U +#define LRFDPBE_EVTMSK1_PBEGPI6_EN 0x00000040U +#define LRFDPBE_EVTMSK1_PBEGPI6_DIS 0x00000000U + +// Field: [5] PBEGPI5 +// +// Enable mask for event EVT0.PBEGPI5 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI5 0x00000020U +#define LRFDPBE_EVTMSK1_PBEGPI5_M 0x00000020U +#define LRFDPBE_EVTMSK1_PBEGPI5_S 5U +#define LRFDPBE_EVTMSK1_PBEGPI5_EN 0x00000020U +#define LRFDPBE_EVTMSK1_PBEGPI5_DIS 0x00000000U + +// Field: [4] PBEGPI4 +// +// Enable mask for event EVT0.PBEGPI4 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI4 0x00000010U +#define LRFDPBE_EVTMSK1_PBEGPI4_M 0x00000010U +#define LRFDPBE_EVTMSK1_PBEGPI4_S 4U +#define LRFDPBE_EVTMSK1_PBEGPI4_EN 0x00000010U +#define LRFDPBE_EVTMSK1_PBEGPI4_DIS 0x00000000U + +// Field: [3] PBEGPI3 +// +// Enable mask for event EVT0.PBEGPI3 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI3 0x00000008U +#define LRFDPBE_EVTMSK1_PBEGPI3_M 0x00000008U +#define LRFDPBE_EVTMSK1_PBEGPI3_S 3U +#define LRFDPBE_EVTMSK1_PBEGPI3_EN 0x00000008U +#define LRFDPBE_EVTMSK1_PBEGPI3_DIS 0x00000000U + +// Field: [2] PBEGPI2 +// +// Enable mask for event EVT0.PBEGPI2 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI2 0x00000004U +#define LRFDPBE_EVTMSK1_PBEGPI2_M 0x00000004U +#define LRFDPBE_EVTMSK1_PBEGPI2_S 2U +#define LRFDPBE_EVTMSK1_PBEGPI2_EN 0x00000004U +#define LRFDPBE_EVTMSK1_PBEGPI2_DIS 0x00000000U + +// Field: [1] PBEGPI1 +// +// Enable mask for event EVT0.PBEGPI1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI1 0x00000002U +#define LRFDPBE_EVTMSK1_PBEGPI1_M 0x00000002U +#define LRFDPBE_EVTMSK1_PBEGPI1_S 1U +#define LRFDPBE_EVTMSK1_PBEGPI1_EN 0x00000002U +#define LRFDPBE_EVTMSK1_PBEGPI1_DIS 0x00000000U + +// Field: [0] PBEGPI0 +// +// Enable mask for event EVT0.PBEGPI0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE_EVTMSK1_PBEGPI0 0x00000001U +#define LRFDPBE_EVTMSK1_PBEGPI0_M 0x00000001U +#define LRFDPBE_EVTMSK1_PBEGPI0_S 0U +#define LRFDPBE_EVTMSK1_PBEGPI0_EN 0x00000001U +#define LRFDPBE_EVTMSK1_PBEGPI0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVTCLR0 +// +//***************************************************************************** +// Field: [15] MDMFAEMPTY +// +// Clear event EVT0.MDMFAEMPTY +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_MDMFAEMPTY 0x00008000U +#define LRFDPBE_EVTCLR0_MDMFAEMPTY_M 0x00008000U +#define LRFDPBE_EVTCLR0_MDMFAEMPTY_S 15U +#define LRFDPBE_EVTCLR0_MDMFAEMPTY_CLEAR 0x00008000U +#define LRFDPBE_EVTCLR0_MDMFAEMPTY_RETAIN 0x00000000U + +// Field: [14] S2RSTOP +// +// Clear event EVT0.S2RSTOP +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_S2RSTOP 0x00004000U +#define LRFDPBE_EVTCLR0_S2RSTOP_M 0x00004000U +#define LRFDPBE_EVTCLR0_S2RSTOP_S 14U +#define LRFDPBE_EVTCLR0_S2RSTOP_CLEAR 0x00004000U +#define LRFDPBE_EVTCLR0_S2RSTOP_RETAIN 0x00000000U + +// Field: [13] FIFOERR +// +// Clear event EVT0.FIFOERR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_FIFOERR 0x00002000U +#define LRFDPBE_EVTCLR0_FIFOERR_M 0x00002000U +#define LRFDPBE_EVTCLR0_FIFOERR_S 13U +#define LRFDPBE_EVTCLR0_FIFOERR_CLEAR 0x00002000U +#define LRFDPBE_EVTCLR0_FIFOERR_RETAIN 0x00000000U + +// Field: [12] MDMFAFULL +// +// Clear event EVT0.MDMFAFULL +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_MDMFAFULL 0x00001000U +#define LRFDPBE_EVTCLR0_MDMFAFULL_M 0x00001000U +#define LRFDPBE_EVTCLR0_MDMFAFULL_S 12U +#define LRFDPBE_EVTCLR0_MDMFAFULL_CLEAR 0x00001000U +#define LRFDPBE_EVTCLR0_MDMFAFULL_RETAIN 0x00000000U + +// Field: [11] SYSTCMP2 +// +// Clear event EVT0.SYSTCMP2 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_SYSTCMP2 0x00000800U +#define LRFDPBE_EVTCLR0_SYSTCMP2_M 0x00000800U +#define LRFDPBE_EVTCLR0_SYSTCMP2_S 11U +#define LRFDPBE_EVTCLR0_SYSTCMP2_CLEAR 0x00000800U +#define LRFDPBE_EVTCLR0_SYSTCMP2_RETAIN 0x00000000U + +// Field: [10] SYSTCMP1 +// +// Clear event EVT0.SYSTCMP1 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_SYSTCMP1 0x00000400U +#define LRFDPBE_EVTCLR0_SYSTCMP1_M 0x00000400U +#define LRFDPBE_EVTCLR0_SYSTCMP1_S 10U +#define LRFDPBE_EVTCLR0_SYSTCMP1_CLEAR 0x00000400U +#define LRFDPBE_EVTCLR0_SYSTCMP1_RETAIN 0x00000000U + +// Field: [9] SYSTCMP0 +// +// Clear event EVT0.SYSTCMP0 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_SYSTCMP0 0x00000200U +#define LRFDPBE_EVTCLR0_SYSTCMP0_M 0x00000200U +#define LRFDPBE_EVTCLR0_SYSTCMP0_S 9U +#define LRFDPBE_EVTCLR0_SYSTCMP0_CLEAR 0x00000200U +#define LRFDPBE_EVTCLR0_SYSTCMP0_RETAIN 0x00000000U + +// Field: [8] MDMMSGBOX +// +// Clear event EVT0.MDMMSGBOX +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_MDMMSGBOX 0x00000100U +#define LRFDPBE_EVTCLR0_MDMMSGBOX_M 0x00000100U +#define LRFDPBE_EVTCLR0_MDMMSGBOX_S 8U +#define LRFDPBE_EVTCLR0_MDMMSGBOX_CLEAR 0x00000100U +#define LRFDPBE_EVTCLR0_MDMMSGBOX_RETAIN 0x00000000U + +// Field: [7] RFEMSGBOX +// +// Clear event EVT0.RFEMSGBOX +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_RFEMSGBOX 0x00000080U +#define LRFDPBE_EVTCLR0_RFEMSGBOX_M 0x00000080U +#define LRFDPBE_EVTCLR0_RFEMSGBOX_S 7U +#define LRFDPBE_EVTCLR0_RFEMSGBOX_CLEAR 0x00000080U +#define LRFDPBE_EVTCLR0_RFEMSGBOX_RETAIN 0x00000000U + +// Field: [6] RFEDAT +// +// Clear event EVT0.RFEDAT +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_RFEDAT 0x00000040U +#define LRFDPBE_EVTCLR0_RFEDAT_M 0x00000040U +#define LRFDPBE_EVTCLR0_RFEDAT_S 6U +#define LRFDPBE_EVTCLR0_RFEDAT_CLEAR 0x00000040U +#define LRFDPBE_EVTCLR0_RFEDAT_RETAIN 0x00000000U + +// Field: [5] RFECMD +// +// Clear event EVT0.RFECMD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_RFECMD 0x00000020U +#define LRFDPBE_EVTCLR0_RFECMD_M 0x00000020U +#define LRFDPBE_EVTCLR0_RFECMD_S 5U +#define LRFDPBE_EVTCLR0_RFECMD_CLEAR 0x00000020U +#define LRFDPBE_EVTCLR0_RFECMD_RETAIN 0x00000000U + +// Field: [4] MDMDAT +// +// Clear event EVT0.MDMDAT +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_MDMDAT 0x00000010U +#define LRFDPBE_EVTCLR0_MDMDAT_M 0x00000010U +#define LRFDPBE_EVTCLR0_MDMDAT_S 4U +#define LRFDPBE_EVTCLR0_MDMDAT_CLEAR 0x00000010U +#define LRFDPBE_EVTCLR0_MDMDAT_RETAIN 0x00000000U + +// Field: [3] MDMCMD +// +// Clear event EVT0.MDMCMD +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_MDMCMD 0x00000008U +#define LRFDPBE_EVTCLR0_MDMCMD_M 0x00000008U +#define LRFDPBE_EVTCLR0_MDMCMD_S 3U +#define LRFDPBE_EVTCLR0_MDMCMD_CLEAR 0x00000008U +#define LRFDPBE_EVTCLR0_MDMCMD_RETAIN 0x00000000U + +// Field: [2] TIMER1 +// +// Clear event EVT0.TIMER1 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_TIMER1 0x00000004U +#define LRFDPBE_EVTCLR0_TIMER1_M 0x00000004U +#define LRFDPBE_EVTCLR0_TIMER1_S 2U +#define LRFDPBE_EVTCLR0_TIMER1_CLEAR 0x00000004U +#define LRFDPBE_EVTCLR0_TIMER1_RETAIN 0x00000000U + +// Field: [1] TIMER0 +// +// Clear event EVT0.TIMER0 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_TIMER0 0x00000002U +#define LRFDPBE_EVTCLR0_TIMER0_M 0x00000002U +#define LRFDPBE_EVTCLR0_TIMER0_S 1U +#define LRFDPBE_EVTCLR0_TIMER0_CLEAR 0x00000002U +#define LRFDPBE_EVTCLR0_TIMER0_RETAIN 0x00000000U + +// Field: [0] PBEAPI +// +// Clear event EVT0.PBEAPI +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR0_PBEAPI 0x00000001U +#define LRFDPBE_EVTCLR0_PBEAPI_M 0x00000001U +#define LRFDPBE_EVTCLR0_PBEAPI_S 0U +#define LRFDPBE_EVTCLR0_PBEAPI_CLEAR 0x00000001U +#define LRFDPBE_EVTCLR0_PBEAPI_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_EVTCLR1 +// +//***************************************************************************** +// Field: [12] TXRDBTHR +// +// Clear event EVT0.TXRDBTHR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_TXRDBTHR 0x00001000U +#define LRFDPBE_EVTCLR1_TXRDBTHR_M 0x00001000U +#define LRFDPBE_EVTCLR1_TXRDBTHR_S 12U +#define LRFDPBE_EVTCLR1_TXRDBTHR_CLEAR 0x00001000U +#define LRFDPBE_EVTCLR1_TXRDBTHR_RETAIN 0x00000000U + +// Field: [11] TXWRBTHR +// +// Clear event EVT0.TXWRBTHR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_TXWRBTHR 0x00000800U +#define LRFDPBE_EVTCLR1_TXWRBTHR_M 0x00000800U +#define LRFDPBE_EVTCLR1_TXWRBTHR_S 11U +#define LRFDPBE_EVTCLR1_TXWRBTHR_CLEAR 0x00000800U +#define LRFDPBE_EVTCLR1_TXWRBTHR_RETAIN 0x00000000U + +// Field: [10] RXRDBTHR +// +// Clear event EVT0.RXRDBTHR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_RXRDBTHR 0x00000400U +#define LRFDPBE_EVTCLR1_RXRDBTHR_M 0x00000400U +#define LRFDPBE_EVTCLR1_RXRDBTHR_S 10U +#define LRFDPBE_EVTCLR1_RXRDBTHR_CLEAR 0x00000400U +#define LRFDPBE_EVTCLR1_RXRDBTHR_RETAIN 0x00000000U + +// Field: [9] RXWRBTHR +// +// Clear event EVT0.RXWRBTHR +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_RXWRBTHR 0x00000200U +#define LRFDPBE_EVTCLR1_RXWRBTHR_M 0x00000200U +#define LRFDPBE_EVTCLR1_RXWRBTHR_S 9U +#define LRFDPBE_EVTCLR1_RXWRBTHR_CLEAR 0x00000200U +#define LRFDPBE_EVTCLR1_RXWRBTHR_RETAIN 0x00000000U + +// Field: [8] MDMPROG +// +// Clear event EVT0.MDMPROG +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_MDMPROG 0x00000100U +#define LRFDPBE_EVTCLR1_MDMPROG_M 0x00000100U +#define LRFDPBE_EVTCLR1_MDMPROG_S 8U +#define LRFDPBE_EVTCLR1_MDMPROG_CLEAR 0x00000100U +#define LRFDPBE_EVTCLR1_MDMPROG_RETAIN 0x00000000U + +// Field: [7] PBEGPI7 +// +// Clear event EVT0.PBEGPI7 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI7 0x00000080U +#define LRFDPBE_EVTCLR1_PBEGPI7_M 0x00000080U +#define LRFDPBE_EVTCLR1_PBEGPI7_S 7U +#define LRFDPBE_EVTCLR1_PBEGPI7_CLEAR 0x00000080U +#define LRFDPBE_EVTCLR1_PBEGPI7_RETAIN 0x00000000U + +// Field: [6] PBEGPI6 +// +// Clear event EVT0.PBEGPI6 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI6 0x00000040U +#define LRFDPBE_EVTCLR1_PBEGPI6_M 0x00000040U +#define LRFDPBE_EVTCLR1_PBEGPI6_S 6U +#define LRFDPBE_EVTCLR1_PBEGPI6_CLEAR 0x00000040U +#define LRFDPBE_EVTCLR1_PBEGPI6_RETAIN 0x00000000U + +// Field: [5] PBEGPI5 +// +// Clear event EVT0.PBEGPI5 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI5 0x00000020U +#define LRFDPBE_EVTCLR1_PBEGPI5_M 0x00000020U +#define LRFDPBE_EVTCLR1_PBEGPI5_S 5U +#define LRFDPBE_EVTCLR1_PBEGPI5_CLEAR 0x00000020U +#define LRFDPBE_EVTCLR1_PBEGPI5_RETAIN 0x00000000U + +// Field: [4] PBEGPI4 +// +// Clear event EVT0.PBEGPI4 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI4 0x00000010U +#define LRFDPBE_EVTCLR1_PBEGPI4_M 0x00000010U +#define LRFDPBE_EVTCLR1_PBEGPI4_S 4U +#define LRFDPBE_EVTCLR1_PBEGPI4_CLEAR 0x00000010U +#define LRFDPBE_EVTCLR1_PBEGPI4_RETAIN 0x00000000U + +// Field: [3] PBEGPI3 +// +// Clear event EVT0.PBEGPI3 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI3 0x00000008U +#define LRFDPBE_EVTCLR1_PBEGPI3_M 0x00000008U +#define LRFDPBE_EVTCLR1_PBEGPI3_S 3U +#define LRFDPBE_EVTCLR1_PBEGPI3_CLEAR 0x00000008U +#define LRFDPBE_EVTCLR1_PBEGPI3_RETAIN 0x00000000U + +// Field: [2] PBEGPI2 +// +// Clear event EVT0.PBEGPI2 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI2 0x00000004U +#define LRFDPBE_EVTCLR1_PBEGPI2_M 0x00000004U +#define LRFDPBE_EVTCLR1_PBEGPI2_S 2U +#define LRFDPBE_EVTCLR1_PBEGPI2_CLEAR 0x00000004U +#define LRFDPBE_EVTCLR1_PBEGPI2_RETAIN 0x00000000U + +// Field: [1] PBEGPI1 +// +// Clear event EVT0.PBEGPI1 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI1 0x00000002U +#define LRFDPBE_EVTCLR1_PBEGPI1_M 0x00000002U +#define LRFDPBE_EVTCLR1_PBEGPI1_S 1U +#define LRFDPBE_EVTCLR1_PBEGPI1_CLEAR 0x00000002U +#define LRFDPBE_EVTCLR1_PBEGPI1_RETAIN 0x00000000U + +// Field: [0] PBEGPI0 +// +// Clear event EVT0.PBEGPI0 +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE_EVTCLR1_PBEGPI0 0x00000001U +#define LRFDPBE_EVTCLR1_PBEGPI0_M 0x00000001U +#define LRFDPBE_EVTCLR1_PBEGPI0_S 0U +#define LRFDPBE_EVTCLR1_PBEGPI0_CLEAR 0x00000001U +#define LRFDPBE_EVTCLR1_PBEGPI0_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_PDREQ +// +//***************************************************************************** +// Field: [0] TOPSMPDREQ +// +// Requests power down for TOPsm core. If the TOPsm has an ongoing memory +// access, the hardware will safely gate the clock after the transaction has +// completed. +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE_PDREQ_TOPSMPDREQ 0x00000001U +#define LRFDPBE_PDREQ_TOPSMPDREQ_M 0x00000001U +#define LRFDPBE_PDREQ_TOPSMPDREQ_S 0U +#define LRFDPBE_PDREQ_TOPSMPDREQ_ON 0x00000001U +#define LRFDPBE_PDREQ_TOPSMPDREQ_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_API +// +//***************************************************************************** +// Field: [4:0] PBECMD +// +// PBE Command +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_API_PBECMD_W 5U +#define LRFDPBE_API_PBECMD_M 0x0000001FU +#define LRFDPBE_API_PBECMD_S 0U +#define LRFDPBE_API_PBECMD_ALLONES 0x0000001FU +#define LRFDPBE_API_PBECMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MCEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to the MCE. Writing to this register will trigger an event in +// the MCE, and the data value written here will be readable in +// LRFDMDM:PBEDATIN0 register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MCEDATOUT0_VAL_W 16U +#define LRFDPBE_MCEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDPBE_MCEDATOUT0_VAL_S 0U +#define LRFDPBE_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_MCEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MCEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from MCE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MCEDATIN0_VAL_W 16U +#define LRFDPBE_MCEDATIN0_VAL_M 0x0000FFFFU +#define LRFDPBE_MCEDATIN0_VAL_S 0U +#define LRFDPBE_MCEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_MCEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MCECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to the MCE. Writing to this register will trigger an event +// in the MCE, and the command value written here will be readable in +// LRFDMDM:PBECMDIN register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MCECMDOUT_VAL_W 4U +#define LRFDPBE_MCECMDOUT_VAL_M 0x0000000FU +#define LRFDPBE_MCECMDOUT_VAL_S 0U +#define LRFDPBE_MCECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDPBE_MCECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MCECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from MCE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MCECMDIN_VAL_W 4U +#define LRFDPBE_MCECMDIN_VAL_M 0x0000000FU +#define LRFDPBE_MCECMDIN_VAL_S 0U +#define LRFDPBE_MCECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDPBE_MCECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMAPI +// +//***************************************************************************** +// Field: [7:4] PROTOCOLID +// +// Protocol ID +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMAPI_PROTOCOLID_W 4U +#define LRFDPBE_MDMAPI_PROTOCOLID_M 0x000000F0U +#define LRFDPBE_MDMAPI_PROTOCOLID_S 4U +#define LRFDPBE_MDMAPI_PROTOCOLID_ALLONES 0x000000F0U +#define LRFDPBE_MDMAPI_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [3:0] MDMCMD +// +// Modem command +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMAPI_MDMCMD_W 4U +#define LRFDPBE_MDMAPI_MDMCMD_M 0x0000000FU +#define LRFDPBE_MDMAPI_MDMCMD_S 0U +#define LRFDPBE_MDMAPI_MDMCMD_ALLONES 0x0000000FU +#define LRFDPBE_MDMAPI_MDMCMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMMSGBOX +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Diverse status, error, report bits from MCE. Controlled by software. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMMSGBOX_VALUE_W 8U +#define LRFDPBE_MDMMSGBOX_VALUE_M 0x000000FFU +#define LRFDPBE_MDMMSGBOX_VALUE_S 0U +#define LRFDPBE_MDMMSGBOX_VALUE_ALLONES 0x000000FFU +#define LRFDPBE_MDMMSGBOX_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FREQ +// +//***************************************************************************** +// Field: [15:0] OFFSET +// +// Frequency Offset from MCE. Controlled by software. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_FREQ_OFFSET_W 16U +#define LRFDPBE_FREQ_OFFSET_M 0x0000FFFFU +#define LRFDPBE_FREQ_OFFSET_S 0U +#define LRFDPBE_FREQ_OFFSET_ALLONES 0x0000FFFFU +#define LRFDPBE_FREQ_OFFSET_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMLQI +// +//***************************************************************************** +// Field: [7:0] VAL +// +// LQI status from MCE. Controlled by software. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMLQI_VAL_W 8U +#define LRFDPBE_MDMLQI_VAL_M 0x000000FFU +#define LRFDPBE_MDMLQI_VAL_S 0U +#define LRFDPBE_MDMLQI_VAL_ALLONES 0x000000FFU +#define LRFDPBE_MDMLQI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to the RFE. Writing to this register will trigger an event in +// the RFE, and the data value written here will be readable in +// LRFDRFE:PBEDATIN0 register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFEDATOUT0_VAL_W 16U +#define LRFDPBE_RFEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDPBE_RFEDATOUT0_VAL_S 0U +#define LRFDPBE_RFEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_RFEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from RFE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFEDATIN0_VAL_W 16U +#define LRFDPBE_RFEDATIN0_VAL_M 0x0000FFFFU +#define LRFDPBE_RFEDATIN0_VAL_S 0U +#define LRFDPBE_RFEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_RFEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to the RFE. Writing to this register will trigger an event +// in the RFE, and the command value written here will be readable in +// LRFDRFE:PBECMDIN register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFECMDOUT_VAL_W 4U +#define LRFDPBE_RFECMDOUT_VAL_M 0x0000000FU +#define LRFDPBE_RFECMDOUT_VAL_S 0U +#define LRFDPBE_RFECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDPBE_RFECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from RFE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFECMDIN_VAL_W 4U +#define LRFDPBE_RFECMDIN_VAL_M 0x0000000FU +#define LRFDPBE_RFECMDIN_VAL_S 0U +#define LRFDPBE_RFECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDPBE_RFECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFEAPI +// +//***************************************************************************** +// Field: [7:4] PROTOCOLID +// +// Protocol ID +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFEAPI_PROTOCOLID_W 4U +#define LRFDPBE_RFEAPI_PROTOCOLID_M 0x000000F0U +#define LRFDPBE_RFEAPI_PROTOCOLID_S 4U +#define LRFDPBE_RFEAPI_PROTOCOLID_ALLONES 0x000000F0U +#define LRFDPBE_RFEAPI_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [3:0] RFECMD +// +// RFE Command +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFEAPI_RFECMD_W 4U +#define LRFDPBE_RFEAPI_RFECMD_M 0x0000000FU +#define LRFDPBE_RFEAPI_RFECMD_S 0U +#define LRFDPBE_RFEAPI_RFECMD_ALLONES 0x0000000FU +#define LRFDPBE_RFEAPI_RFECMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFECMDPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFECMDPAR0_VAL_W 16U +#define LRFDPBE_RFECMDPAR0_VAL_M 0x0000FFFFU +#define LRFDPBE_RFECMDPAR0_VAL_S 0U +#define LRFDPBE_RFECMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_RFECMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFECMDPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFECMDPAR1_VAL_W 16U +#define LRFDPBE_RFECMDPAR1_VAL_M 0x0000FFFFU +#define LRFDPBE_RFECMDPAR1_VAL_S 0U +#define LRFDPBE_RFECMDPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_RFECMDPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFEMSGBOX +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Diverse status, error, report bits from RFE +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFEMSGBOX_VAL_W 8U +#define LRFDPBE_RFEMSGBOX_VAL_M 0x000000FFU +#define LRFDPBE_RFEMSGBOX_VAL_S 0U +#define LRFDPBE_RFEMSGBOX_VAL_ALLONES 0x000000FFU +#define LRFDPBE_RFEMSGBOX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFERSSI +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Current RSSI value (signed). If this register reads as -128 (0x80) it means +// that the value is not yet valid. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFERSSI_VAL_W 8U +#define LRFDPBE_RFERSSI_VAL_M 0x000000FFU +#define LRFDPBE_RFERSSI_VAL_S 0U +#define LRFDPBE_RFERSSI_VAL_ALLONES 0x000000FFU +#define LRFDPBE_RFERSSI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFERSSIMAX +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Maximum RSSI value since start of measurements cycle. If this field reads as +// -128 (0x80) it means that the value is not yet valid. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFERSSIMAX_VAL_W 8U +#define LRFDPBE_RFERSSIMAX_VAL_M 0x000000FFU +#define LRFDPBE_RFERSSIMAX_VAL_S 0U +#define LRFDPBE_RFERSSIMAX_VAL_ALLONES 0x000000FFU +#define LRFDPBE_RFERSSIMAX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RFERFGAIN +// +//***************************************************************************** +// Field: [7:0] DBGAIN +// +// Current RF front-end gain, in dB +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RFERFGAIN_DBGAIN_W 8U +#define LRFDPBE_RFERFGAIN_DBGAIN_M 0x000000FFU +#define LRFDPBE_RFERFGAIN_DBGAIN_S 0U +#define LRFDPBE_RFERFGAIN_DBGAIN_ALLONES 0x000000FFU +#define LRFDPBE_RFERFGAIN_DBGAIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMSYNCAL +// +//***************************************************************************** +// Field: [15:0] SWALSB +// +// Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as +// most signicant bits of sync word A. The sync word is expected to be +// transmitted/received in lsb to msb order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMSYNCAL_SWALSB_W 16U +#define LRFDPBE_MDMSYNCAL_SWALSB_M 0x0000FFFFU +#define LRFDPBE_MDMSYNCAL_SWALSB_S 0U +#define LRFDPBE_MDMSYNCAL_SWALSB_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMSYNCAL_SWALSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMSYNCAH +// +//***************************************************************************** +// Field: [15:0] SWAMSB +// +// Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word A. The sync word is expected to be +// transmitted/received in lsb to msb order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMSYNCAH_SWAMSB_W 16U +#define LRFDPBE_MDMSYNCAH_SWAMSB_M 0x0000FFFFU +#define LRFDPBE_MDMSYNCAH_SWAMSB_S 0U +#define LRFDPBE_MDMSYNCAH_SWAMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMSYNCAH_SWAMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMSYNCBL +// +//***************************************************************************** +// Field: [15:0] SWBLSB +// +// Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word B. The sync word is expected to be +// transmitted/received in lsb to msb order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMSYNCBL_SWBLSB_W 16U +#define LRFDPBE_MDMSYNCBL_SWBLSB_M 0x0000FFFFU +#define LRFDPBE_MDMSYNCBL_SWBLSB_S 0U +#define LRFDPBE_MDMSYNCBL_SWBLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMSYNCBL_SWBLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMSYNCBH +// +//***************************************************************************** +// Field: [15:0] SWBMSB +// +// Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as +// most significant bits of sync word B. The sync word is expected to be +// transmitted/received in lsb to msb order. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMSYNCBH_SWBMSB_W 16U +#define LRFDPBE_MDMSYNCBH_SWBMSB_M 0x0000FFFFU +#define LRFDPBE_MDMSYNCBH_SWBMSB_S 0U +#define LRFDPBE_MDMSYNCBH_SWBMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMSYNCBH_SWBMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMCMDPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0. Software defined function. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMCMDPAR0_VAL_W 16U +#define LRFDPBE_MDMCMDPAR0_VAL_M 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR0_VAL_S 0U +#define LRFDPBE_MDMCMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMCMDPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1. Software defined function. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMCMDPAR1_VAL_W 16U +#define LRFDPBE_MDMCMDPAR1_VAL_M 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR1_VAL_S 0U +#define LRFDPBE_MDMCMDPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMCMDPAR2 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 2. Software defined function. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMCMDPAR2_VAL_W 16U +#define LRFDPBE_MDMCMDPAR2_VAL_M 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR2_VAL_S 0U +#define LRFDPBE_MDMCMDPAR2_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMCMDPAR2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_POLY0L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 0 polynomial taps, lower half +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_POLY0L_VALLSB_W 16U +#define LRFDPBE_POLY0L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_POLY0L_VALLSB_S 0U +#define LRFDPBE_POLY0L_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_POLY0L_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_POLY0H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 0 polynomial taps, upper half +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_POLY0H_VALMSB_W 16U +#define LRFDPBE_POLY0H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_POLY0H_VALMSB_S 0U +#define LRFDPBE_POLY0H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_POLY0H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_POLY1L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 1 polynomial taps, low part +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_POLY1L_VALLSB_W 16U +#define LRFDPBE_POLY1L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_POLY1L_VALLSB_S 0U +#define LRFDPBE_POLY1L_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_POLY1L_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_POLY1H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 1 polynomial taps, high part +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_POLY1H_VALMSB_W 16U +#define LRFDPBE_POLY1H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_POLY1H_VALMSB_S 0U +#define LRFDPBE_POLY1H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_POLY1H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_PHACFG +// +//***************************************************************************** +// Field: [2:1] MODE1 +// +// Dual LFSR operating mode +// ENUMs: +// PARAL LFSR0 and LFSR1 are operated in parallel +// CASC LFSR0 whitener is followed by LFSR1 CRC +// INDEP LFSR0 and LFSR1 are operated independently +#define LRFDPBE_PHACFG_MODE1_W 2U +#define LRFDPBE_PHACFG_MODE1_M 0x00000006U +#define LRFDPBE_PHACFG_MODE1_S 1U +#define LRFDPBE_PHACFG_MODE1_PARAL 0x00000004U +#define LRFDPBE_PHACFG_MODE1_CASC 0x00000002U +#define LRFDPBE_PHACFG_MODE1_INDEP 0x00000000U + +// Field: [0] MODE0 +// +// LFSR 0 operating mode +// ENUMs: +// WHITE LFSR 0 is in whitening mode +// CRC LFSR 0 is in CRC mode +#define LRFDPBE_PHACFG_MODE0 0x00000001U +#define LRFDPBE_PHACFG_MODE0_M 0x00000001U +#define LRFDPBE_PHACFG_MODE0_S 0U +#define LRFDPBE_PHACFG_MODE0_WHITE 0x00000001U +#define LRFDPBE_PHACFG_MODE0_CRC 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG0 +// +//***************************************************************************** +// Field: [7] TXIRQMET +// +// Select source for pbe_irq(17) +// ENUMs: +// TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable +// bytes. +#define LRFDPBE_FCFG0_TXIRQMET 0x00000080U +#define LRFDPBE_FCFG0_TXIRQMET_M 0x00000080U +#define LRFDPBE_FCFG0_TXIRQMET_S 7U +#define LRFDPBE_FCFG0_TXIRQMET_TXRDBTHR 0x00000080U +#define LRFDPBE_FCFG0_TXIRQMET_TXWRBTHR 0x00000000U + +// Field: [6] RXIRQMET +// +// Select source for pbe_irq(16) +// ENUMs: +// RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable +// bytes. +#define LRFDPBE_FCFG0_RXIRQMET 0x00000040U +#define LRFDPBE_FCFG0_RXIRQMET_M 0x00000040U +#define LRFDPBE_FCFG0_RXIRQMET_S 6U +#define LRFDPBE_FCFG0_RXIRQMET_RXWRBTHR 0x00000040U +#define LRFDPBE_FCFG0_RXIRQMET_RXRDBTHR 0x00000000U + +// Field: [5] TXACOM +// +// Automatic FIFO commit configuration +// ENUMs: +// EN Always set TXSWP := TXWP +// DIS commit TXFIFO only on command 0x95 +#define LRFDPBE_FCFG0_TXACOM 0x00000020U +#define LRFDPBE_FCFG0_TXACOM_M 0x00000020U +#define LRFDPBE_FCFG0_TXACOM_S 5U +#define LRFDPBE_FCFG0_TXACOM_EN 0x00000020U +#define LRFDPBE_FCFG0_TXACOM_DIS 0x00000000U + +// Field: [4] TXADEAL +// +// Automatic deallocation setting +// ENUMs: +// EN Always set TXFSRP := TXFRP. +// DIS Deallocate TXFIFO only on command 0x92 +#define LRFDPBE_FCFG0_TXADEAL 0x00000010U +#define LRFDPBE_FCFG0_TXADEAL_M 0x00000010U +#define LRFDPBE_FCFG0_TXADEAL_S 4U +#define LRFDPBE_FCFG0_TXADEAL_EN 0x00000010U +#define LRFDPBE_FCFG0_TXADEAL_DIS 0x00000000U + +// Field: [1] RXACOM +// +// Automatic FIFO commit configuration +// ENUMs: +// EN Always set RXFSWP := RXFWP +// DIS commit rxfifo only on command 0x85 +#define LRFDPBE_FCFG0_RXACOM 0x00000002U +#define LRFDPBE_FCFG0_RXACOM_M 0x00000002U +#define LRFDPBE_FCFG0_RXACOM_S 1U +#define LRFDPBE_FCFG0_RXACOM_EN 0x00000002U +#define LRFDPBE_FCFG0_RXACOM_DIS 0x00000000U + +// Field: [0] RXADEAL +// +// Automatic deallocation setting +// ENUMs: +// EN Always set RXFSRP := RXFRP. +// DIS Deallocate RXFIFO only on command 0x82 +#define LRFDPBE_FCFG0_RXADEAL 0x00000001U +#define LRFDPBE_FCFG0_RXADEAL_M 0x00000001U +#define LRFDPBE_FCFG0_RXADEAL_S 0U +#define LRFDPBE_FCFG0_RXADEAL_EN 0x00000001U +#define LRFDPBE_FCFG0_RXADEAL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG1 +// +//***************************************************************************** +// Field: [8:0] TXSTRT +// +// FIFO start address, offset from start of BUFRAM. Address is 32-bit word +// address (not byte address) +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE_FCFG1_TXSTRT_W 9U +#define LRFDPBE_FCFG1_TXSTRT_M 0x000001FFU +#define LRFDPBE_FCFG1_TXSTRT_S 0U +#define LRFDPBE_FCFG1_TXSTRT_ONES 0x000001FFU +#define LRFDPBE_FCFG1_TXSTRT_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG2 +// +//***************************************************************************** +// Field: [10:8] TXHSIZE +// +// Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, +// for both RX FIFO and TX FIFO. +// ENUMs: +// WORD MCU receives IRQ when the TX FIFO contains more or +// equal amount of data than the configured +// threshold. +// HALFW MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +// BYTE MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +#define LRFDPBE_FCFG2_TXHSIZE_W 3U +#define LRFDPBE_FCFG2_TXHSIZE_M 0x00000700U +#define LRFDPBE_FCFG2_TXHSIZE_S 8U +#define LRFDPBE_FCFG2_TXHSIZE_WORD 0x00000200U +#define LRFDPBE_FCFG2_TXHSIZE_HALFW 0x00000100U +#define LRFDPBE_FCFG2_TXHSIZE_BYTE 0x00000000U + +// Field: [7:0] TXSIZE +// +// TXFIFO size in number of 32-bit words +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE_FCFG2_TXSIZE_W 8U +#define LRFDPBE_FCFG2_TXSIZE_M 0x000000FFU +#define LRFDPBE_FCFG2_TXSIZE_S 0U +#define LRFDPBE_FCFG2_TXSIZE_ONES 0x000000FFU +#define LRFDPBE_FCFG2_TXSIZE_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG3 +// +//***************************************************************************** +// Field: [8:0] RXSTRT +// +// FIFO start address, offset from start of BUFRAM. Address is 32-bit word +// adress (not byte address) +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE_FCFG3_RXSTRT_W 9U +#define LRFDPBE_FCFG3_RXSTRT_M 0x000001FFU +#define LRFDPBE_FCFG3_RXSTRT_S 0U +#define LRFDPBE_FCFG3_RXSTRT_ONES 0x000001FFU +#define LRFDPBE_FCFG3_RXSTRT_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG4 +// +//***************************************************************************** +// Field: [10:8] RXHSIZE +// +// Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, +// for both RX FIFO and TX FIFO. +// ENUMs: +// WORD MCU receives IRQ when the TX FIFO contains more or +// equal amount of data than the configured +// threshold. +// HALFW MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +// BYTE MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +#define LRFDPBE_FCFG4_RXHSIZE_W 3U +#define LRFDPBE_FCFG4_RXHSIZE_M 0x00000700U +#define LRFDPBE_FCFG4_RXHSIZE_S 8U +#define LRFDPBE_FCFG4_RXHSIZE_WORD 0x00000200U +#define LRFDPBE_FCFG4_RXHSIZE_HALFW 0x00000100U +#define LRFDPBE_FCFG4_RXHSIZE_BYTE 0x00000000U + +// Field: [7:0] RXSIZE +// +// RXFIFO size in number of 32-bit words +// ENUMs: +// ONES Always set RXFSWP := RXFWP +// ZEROS commit rxfifo only on command 0x85 +#define LRFDPBE_FCFG4_RXSIZE_W 8U +#define LRFDPBE_FCFG4_RXSIZE_M 0x000000FFU +#define LRFDPBE_FCFG4_RXSIZE_S 0U +#define LRFDPBE_FCFG4_RXSIZE_ONES 0x000000FFU +#define LRFDPBE_FCFG4_RXSIZE_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCFG5 +// +//***************************************************************************** +// Field: [8:6] DMASREQ +// +// DMA trigger select. Triggers DMA when selected trigger occurs. Note that it +// is a mix of pulse type and level type triggers +// ENUMs: +// TXFIFOFREE The TX FIFO contains FCFG2_TXHSIZE or more +// writable bytes. +// TXFIFOMD The TX FIFO contains FCFG2_TXHSIZE or more +// readable bytes. +// RXFIFOFREE The RX FIFO contains FCFG4_RXHSIZE or more +// writable bytes. +// RXFIFOMD The RX FIFO contains FCFG4_RXHSIZE or more +// readable bytes. +// NONE No triggers generated +#define LRFDPBE_FCFG5_DMASREQ_W 3U +#define LRFDPBE_FCFG5_DMASREQ_M 0x000001C0U +#define LRFDPBE_FCFG5_DMASREQ_S 6U +#define LRFDPBE_FCFG5_DMASREQ_TXFIFOFREE 0x00000100U +#define LRFDPBE_FCFG5_DMASREQ_TXFIFOMD 0x000000C0U +#define LRFDPBE_FCFG5_DMASREQ_RXFIFOFREE 0x00000080U +#define LRFDPBE_FCFG5_DMASREQ_RXFIFOMD 0x00000040U +#define LRFDPBE_FCFG5_DMASREQ_NONE 0x00000000U + +// Field: [4:0] DMAREQ +// +// DMA trigger select. Triggers DMA when selected trigger occurs. Note that it +// is a mix of pulse type and level type triggers +// ENUMs: +// TXFIFO_COMMIT TXFIFO is committed +// TXFIFO_DISCARD TXFIFO is discarded +// TXFIFO_RETRY TXFIFO is retried +// TXFIFO_DEALLOC TXFIFO is deallocated +// TXFIFO_RESET TXFIFO is reset +// TXWRBTHR_MET The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// TXRDBTHR_MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// RXFIFO_COMMIT RXFIFO is committed +// RXFIFO_DISCARD RXFIFO is discarded +// RXFIFO_RETRY RXFIFO is retried +// RXFIFO_DEALLOC RXFIFO is deallocated +// RXFIFO_RESET RXFIFO is reset +// RXWRBTHR_MET The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// RXRDBTHR_MET The RX FIFO contains RXFRBTHRS or more readable +// bytes. +// NONE No triggers generated +#define LRFDPBE_FCFG5_DMAREQ_W 5U +#define LRFDPBE_FCFG5_DMAREQ_M 0x0000001FU +#define LRFDPBE_FCFG5_DMAREQ_S 0U +#define LRFDPBE_FCFG5_DMAREQ_TXFIFO_COMMIT 0x0000000FU +#define LRFDPBE_FCFG5_DMAREQ_TXFIFO_DISCARD 0x0000000EU +#define LRFDPBE_FCFG5_DMAREQ_TXFIFO_RETRY 0x0000000DU +#define LRFDPBE_FCFG5_DMAREQ_TXFIFO_DEALLOC 0x0000000CU +#define LRFDPBE_FCFG5_DMAREQ_TXFIFO_RESET 0x0000000BU +#define LRFDPBE_FCFG5_DMAREQ_TXWRBTHR_MET 0x0000000AU +#define LRFDPBE_FCFG5_DMAREQ_TXRDBTHR_MET 0x00000009U +#define LRFDPBE_FCFG5_DMAREQ_RXFIFO_COMMIT 0x00000007U +#define LRFDPBE_FCFG5_DMAREQ_RXFIFO_DISCARD 0x00000006U +#define LRFDPBE_FCFG5_DMAREQ_RXFIFO_RETRY 0x00000005U +#define LRFDPBE_FCFG5_DMAREQ_RXFIFO_DEALLOC 0x00000004U +#define LRFDPBE_FCFG5_DMAREQ_RXFIFO_RESET 0x00000003U +#define LRFDPBE_FCFG5_DMAREQ_RXWRBTHR_MET 0x00000002U +#define LRFDPBE_FCFG5_DMAREQ_RXRDBTHR_MET 0x00000001U +#define LRFDPBE_FCFG5_DMAREQ_NONE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFWBTHRS +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFWBTHRS_BYTES_W 10U +#define LRFDPBE_RXFWBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE_RXFWBTHRS_BYTES_S 0U +#define LRFDPBE_RXFWBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_RXFWBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFRBTHRS +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFRBTHRS_BYTES_W 10U +#define LRFDPBE_RXFRBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE_RXFRBTHRS_BYTES_S 0U +#define LRFDPBE_RXFRBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_RXFRBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFWBTHRS +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFWBTHRS_BYTES_W 10U +#define LRFDPBE_TXFWBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE_TXFWBTHRS_BYTES_S 0U +#define LRFDPBE_TXFWBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_TXFWBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFRBTHRS +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFRBTHRS_BYTES_W 10U +#define LRFDPBE_TXFRBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE_TXFRBTHRS_BYTES_S 0U +#define LRFDPBE_TXFRBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_TXFRBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMCTL +// +//***************************************************************************** +// Field: [15:11] CPTSRC1 +// +// Selects bit number from event bus to use for a counter capture. Event number +// in range 0 to 31 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMCTL_CPTSRC1_W 5U +#define LRFDPBE_TIMCTL_CPTSRC1_M 0x0000F800U +#define LRFDPBE_TIMCTL_CPTSRC1_S 11U +#define LRFDPBE_TIMCTL_CPTSRC1_ALLONES 0x0000F800U +#define LRFDPBE_TIMCTL_CPTSRC1_ALLZEROS 0x00000000U + +// Field: [10] ENCPT1 +// +// Enable timer capture on event. Upon a capture event, the timer value will be +// captured in TIMCAPT register. The timer value can always be captured using +// the STROBES0.TIMCAPT1 +// ENUMs: +// ON Enable capture mode for counter +// OFF Disable capture mode for counter +#define LRFDPBE_TIMCTL_ENCPT1 0x00000400U +#define LRFDPBE_TIMCTL_ENCPT1_M 0x00000400U +#define LRFDPBE_TIMCTL_ENCPT1_S 10U +#define LRFDPBE_TIMCTL_ENCPT1_ON 0x00000400U +#define LRFDPBE_TIMCTL_ENCPT1_OFF 0x00000000U + +// Field: [9] SRC1 +// +// Select timer tick source for timer +// ENUMs: +// PRE1 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDPBE_TIMCTL_SRC1 0x00000200U +#define LRFDPBE_TIMCTL_SRC1_M 0x00000200U +#define LRFDPBE_TIMCTL_SRC1_S 9U +#define LRFDPBE_TIMCTL_SRC1_PRE1 0x00000200U +#define LRFDPBE_TIMCTL_SRC1_CLK 0x00000000U + +// Field: [8] EN1 +// +// Enable 16-bit timer1. It will generate a timer interrupt after TIMPER1 timer +// ticks. +// ENUMs: +// ON Will enable timer +// OFF Will disable timer and clear internal timer value +#define LRFDPBE_TIMCTL_EN1 0x00000100U +#define LRFDPBE_TIMCTL_EN1_M 0x00000100U +#define LRFDPBE_TIMCTL_EN1_S 8U +#define LRFDPBE_TIMCTL_EN1_ON 0x00000100U +#define LRFDPBE_TIMCTL_EN1_OFF 0x00000000U + +// Field: [7:3] CPTSRC0 +// +// Selects bit number from event bus to use for a counter capture. Event number +// in range 0 to 31 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMCTL_CPTSRC0_W 5U +#define LRFDPBE_TIMCTL_CPTSRC0_M 0x000000F8U +#define LRFDPBE_TIMCTL_CPTSRC0_S 3U +#define LRFDPBE_TIMCTL_CPTSRC0_ALLONES 0x000000F8U +#define LRFDPBE_TIMCTL_CPTSRC0_ALLZEROS 0x00000000U + +// Field: [2] ENCPT0 +// +// Enable timer capture on event. Upon a capture event, the timer value will be +// captured in TIMCAPT register. The timer value can always be captured using +// the STROBES0.TIMCAPT0 +// ENUMs: +// ON Enable capture mode for counter +// OFF Disable capture mode for counter +#define LRFDPBE_TIMCTL_ENCPT0 0x00000004U +#define LRFDPBE_TIMCTL_ENCPT0_M 0x00000004U +#define LRFDPBE_TIMCTL_ENCPT0_S 2U +#define LRFDPBE_TIMCTL_ENCPT0_ON 0x00000004U +#define LRFDPBE_TIMCTL_ENCPT0_OFF 0x00000000U + +// Field: [1] SRC0 +// +// Select timer tick source for timer +// ENUMs: +// PRE0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDPBE_TIMCTL_SRC0 0x00000002U +#define LRFDPBE_TIMCTL_SRC0_M 0x00000002U +#define LRFDPBE_TIMCTL_SRC0_S 1U +#define LRFDPBE_TIMCTL_SRC0_PRE0 0x00000002U +#define LRFDPBE_TIMCTL_SRC0_CLK 0x00000000U + +// Field: [0] EN0 +// +// Enable 16-bit timer0. It will generate a timer interrupt after TIMPER0 timer +// ticks. Note that the internal timer value is not readable from the PBE. +// ENUMs: +// ON Will enable timer +// OFF Will disable timer and clear internal timer value +#define LRFDPBE_TIMCTL_EN0 0x00000001U +#define LRFDPBE_TIMCTL_EN0_M 0x00000001U +#define LRFDPBE_TIMCTL_EN0_S 0U +#define LRFDPBE_TIMCTL_EN0_ON 0x00000001U +#define LRFDPBE_TIMCTL_EN0_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMPRE +// +//***************************************************************************** +// Field: [13:8] PRE1 +// +// Prescaler setting for timer 1, timer speed will be reduced to clk/(PRE1+1) +// ENUMs: +// DIV64 DIV64 mode +// NO_DIV No prescaling +#define LRFDPBE_TIMPRE_PRE1_W 6U +#define LRFDPBE_TIMPRE_PRE1_M 0x00003F00U +#define LRFDPBE_TIMPRE_PRE1_S 8U +#define LRFDPBE_TIMPRE_PRE1_DIV64 0x00003F00U +#define LRFDPBE_TIMPRE_PRE1_NO_DIV 0x00000000U + +// Field: [5:0] PRE0 +// +// Prescaler setting for timer 0, timer speed will be reduced to clk/(PRE0+1) +// ENUMs: +// DIV64 DIV64 mode +// NO_DIV No prescaling +#define LRFDPBE_TIMPRE_PRE0_W 6U +#define LRFDPBE_TIMPRE_PRE0_M 0x0000003FU +#define LRFDPBE_TIMPRE_PRE0_S 0U +#define LRFDPBE_TIMPRE_PRE0_DIV64 0x0000003FU +#define LRFDPBE_TIMPRE_PRE0_NO_DIV 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMPER0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Configurable 16 bit period that can be used for either the timer or the +// counter. In timer context, when timer value reach the timer period (i.e. it +// expires) a TIMER_IRQ event will occur, and the timer will restart from zero +// (until the timer is manually disabled). In counter context, a COUNTER_IRQ +// event will occur when the counter is equal to or higher than the period +// value. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMPER0_VAL_W 16U +#define LRFDPBE_TIMPER0_VAL_M 0x0000FFFFU +#define LRFDPBE_TIMPER0_VAL_S 0U +#define LRFDPBE_TIMPER0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_TIMPER0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMPER1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Configurable 16 bit period that can be used for either the timer or the +// counter. In timer context, when timer value reach the timer period (i.e. it +// expires) a TIMER_IRQ event will occur, and the timer will restart from zero +// (until the timer is manually disabled). In counter context, a COUNTER_IRQ +// event will occur when the counter is equal to or higher than the period +// value. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMPER1_VAL_W 16U +#define LRFDPBE_TIMPER1_VAL_M 0x0000FFFFU +#define LRFDPBE_TIMPER1_VAL_S 0U +#define LRFDPBE_TIMPER1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_TIMPER1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMCAPT0 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Captured value of counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMCAPT0_VALUE_W 16U +#define LRFDPBE_TIMCAPT0_VALUE_M 0x0000FFFFU +#define LRFDPBE_TIMCAPT0_VALUE_S 0U +#define LRFDPBE_TIMCAPT0_VALUE_ALLONES 0x0000FFFFU +#define LRFDPBE_TIMCAPT0_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TIMCAPT1 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Captured value of counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TIMCAPT1_VALUE_W 16U +#define LRFDPBE_TIMCAPT1_VALUE_M 0x0000FFFFU +#define LRFDPBE_TIMCAPT1_VALUE_S 0U +#define LRFDPBE_TIMCAPT1_VALUE_ALLONES 0x0000FFFFU +#define LRFDPBE_TIMCAPT1_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TRCCTL +// +//***************************************************************************** +// Field: [0] SEND +// +// Sends a command to the tracer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_TRCCTL_SEND 0x00000001U +#define LRFDPBE_TRCCTL_SEND_M 0x00000001U +#define LRFDPBE_TRCCTL_SEND_S 0U +#define LRFDPBE_TRCCTL_SEND_ONE 0x00000001U +#define LRFDPBE_TRCCTL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TRCSTAT +// +//***************************************************************************** +// Field: [0] BUSY +// +// Checks if the tracer is busy +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_TRCSTAT_BUSY 0x00000001U +#define LRFDPBE_TRCSTAT_BUSY_M 0x00000001U +#define LRFDPBE_TRCSTAT_BUSY_S 0U +#define LRFDPBE_TRCSTAT_BUSY_ONE 0x00000001U +#define LRFDPBE_TRCSTAT_BUSY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TRCCMD +// +//***************************************************************************** +// Field: [9:8] PARCNT +// +// Number of parameters +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TRCCMD_PARCNT_W 2U +#define LRFDPBE_TRCCMD_PARCNT_M 0x00000300U +#define LRFDPBE_TRCCMD_PARCNT_S 8U +#define LRFDPBE_TRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDPBE_TRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// Packet header +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TRCCMD_PKTHDR_W 8U +#define LRFDPBE_TRCCMD_PKTHDR_M 0x000000FFU +#define LRFDPBE_TRCCMD_PKTHDR_S 0U +#define LRFDPBE_TRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDPBE_TRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TRCPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TRCPAR0_VAL_W 16U +#define LRFDPBE_TRCPAR0_VAL_M 0x0000FFFFU +#define LRFDPBE_TRCPAR0_VAL_S 0U +#define LRFDPBE_TRCPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_TRCPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TRCPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TRCPAR1_VAL_W 16U +#define LRFDPBE_TRCPAR1_VAL_M 0x0000FFFFU +#define LRFDPBE_TRCPAR1_VAL_S 0U +#define LRFDPBE_TRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_TRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_GPOCTRL +// +//***************************************************************************** +// Field: [7] GPO7 +// +// Control GPO7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO7 0x00000080U +#define LRFDPBE_GPOCTRL_GPO7_M 0x00000080U +#define LRFDPBE_GPOCTRL_GPO7_S 7U +#define LRFDPBE_GPOCTRL_GPO7_ONE 0x00000080U +#define LRFDPBE_GPOCTRL_GPO7_ZERO 0x00000000U + +// Field: [6] GPO6 +// +// Control GPO6 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO6 0x00000040U +#define LRFDPBE_GPOCTRL_GPO6_M 0x00000040U +#define LRFDPBE_GPOCTRL_GPO6_S 6U +#define LRFDPBE_GPOCTRL_GPO6_ONE 0x00000040U +#define LRFDPBE_GPOCTRL_GPO6_ZERO 0x00000000U + +// Field: [5] GPO5 +// +// Control GPO5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO5 0x00000020U +#define LRFDPBE_GPOCTRL_GPO5_M 0x00000020U +#define LRFDPBE_GPOCTRL_GPO5_S 5U +#define LRFDPBE_GPOCTRL_GPO5_ONE 0x00000020U +#define LRFDPBE_GPOCTRL_GPO5_ZERO 0x00000000U + +// Field: [4] GPO4 +// +// Control GPO4 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO4 0x00000010U +#define LRFDPBE_GPOCTRL_GPO4_M 0x00000010U +#define LRFDPBE_GPOCTRL_GPO4_S 4U +#define LRFDPBE_GPOCTRL_GPO4_ONE 0x00000010U +#define LRFDPBE_GPOCTRL_GPO4_ZERO 0x00000000U + +// Field: [3] GPO3 +// +// Control GPO3 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO3 0x00000008U +#define LRFDPBE_GPOCTRL_GPO3_M 0x00000008U +#define LRFDPBE_GPOCTRL_GPO3_S 3U +#define LRFDPBE_GPOCTRL_GPO3_ONE 0x00000008U +#define LRFDPBE_GPOCTRL_GPO3_ZERO 0x00000000U + +// Field: [2] GPO2 +// +// Control GPO2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO2 0x00000004U +#define LRFDPBE_GPOCTRL_GPO2_M 0x00000004U +#define LRFDPBE_GPOCTRL_GPO2_S 2U +#define LRFDPBE_GPOCTRL_GPO2_ONE 0x00000004U +#define LRFDPBE_GPOCTRL_GPO2_ZERO 0x00000000U + +// Field: [1] GPO1 +// +// Control GPO1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO1 0x00000002U +#define LRFDPBE_GPOCTRL_GPO1_M 0x00000002U +#define LRFDPBE_GPOCTRL_GPO1_S 1U +#define LRFDPBE_GPOCTRL_GPO1_ONE 0x00000002U +#define LRFDPBE_GPOCTRL_GPO1_ZERO 0x00000000U + +// Field: [0] GPO0 +// +// Control GPO0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPOCTRL_GPO0 0x00000001U +#define LRFDPBE_GPOCTRL_GPO0_M 0x00000001U +#define LRFDPBE_GPOCTRL_GPO0_S 0U +#define LRFDPBE_GPOCTRL_GPO0_ONE 0x00000001U +#define LRFDPBE_GPOCTRL_GPO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFWR +// +//***************************************************************************** +// Field: [15:0] PAYLOADIN +// +// FIFO write port. The actual port size is configurable in LRFDMDM:FIFOWRCTRL. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMFWR_PAYLOADIN_W 16U +#define LRFDPBE_MDMFWR_PAYLOADIN_M 0x0000FFFFU +#define LRFDPBE_MDMFWR_PAYLOADIN_S 0U +#define LRFDPBE_MDMFWR_PAYLOADIN_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMFWR_PAYLOADIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFRD +// +//***************************************************************************** +// Field: [15:0] PAYLOADOUT +// +// FIFO read port. The actual port size is configurable in LRFDMDM:FIFORDCTRL. +// A new value is read by writing LRFDMDM:FIFOWR.PAYLOADIN. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMFRD_PAYLOADOUT_W 16U +#define LRFDPBE_MDMFRD_PAYLOADOUT_M 0x0000FFFFU +#define LRFDPBE_MDMFRD_PAYLOADOUT_S 0U +#define LRFDPBE_MDMFRD_PAYLOADOUT_ALLONES 0x0000FFFFU +#define LRFDPBE_MDMFRD_PAYLOADOUT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFWRCTL +// +//***************************************************************************** +// Field: [3:0] WORDSZWR +// +// Actual bits in every word write access +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDPBE_MDMFWRCTL_WORDSZWR_W 4U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_M 0x0000000FU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_S 0U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS16 0x0000000FU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS15 0x0000000EU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS14 0x0000000DU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS13 0x0000000CU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS12 0x0000000BU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS11 0x0000000AU +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS10 0x00000009U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS9 0x00000008U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS8 0x00000007U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS7 0x00000006U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS6 0x00000005U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS5 0x00000004U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS4 0x00000003U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS3 0x00000002U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS2 0x00000001U +#define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFRDCTL +// +//***************************************************************************** +// Field: [3:0] WORDSZRD +// +// Actual bits in every word read access +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDPBE_MDMFRDCTL_WORDSZRD_W 4U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_M 0x0000000FU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_S 0U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS16 0x0000000FU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS15 0x0000000EU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS14 0x0000000DU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS13 0x0000000CU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS12 0x0000000BU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS11 0x0000000AU +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS10 0x00000009U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS9 0x00000008U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS8 0x00000007U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS7 0x00000006U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS6 0x00000005U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS5 0x00000004U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS4 0x00000003U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS3 0x00000002U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS2 0x00000001U +#define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFCFG +// +//***************************************************************************** +// Field: [15:8] AFULLTHR +// +// Almost full threshold value in bits. This threshold affects the +// LRFDMDM:FIFOSTA.ALMOSTFULL and LRFDMDM:FIFOSTA.TXREADY status bits. The FIFO +// can hold up to 64 bits. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMFCFG_AFULLTHR_W 8U +#define LRFDPBE_MDMFCFG_AFULLTHR_M 0x0000FF00U +#define LRFDPBE_MDMFCFG_AFULLTHR_S 8U +#define LRFDPBE_MDMFCFG_AFULLTHR_ALLONES 0x0000FF00U +#define LRFDPBE_MDMFCFG_AFULLTHR_ALLZEROS 0x00000000U + +// Field: [7:0] AEMPTYTHR +// +// Almost empty threshold in bits. This threshold affects the +// LRFDMDM:FIFOSTA.ALMOSTEMPTY and LRFDMDM:FIFOSTA.RXVALID status bits. The +// FIFO can hold up to 64 bits. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_MDMFCFG_AEMPTYTHR_W 8U +#define LRFDPBE_MDMFCFG_AEMPTYTHR_M 0x000000FFU +#define LRFDPBE_MDMFCFG_AEMPTYTHR_S 0U +#define LRFDPBE_MDMFCFG_AEMPTYTHR_ALLONES 0x000000FFU +#define LRFDPBE_MDMFCFG_AEMPTYTHR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_MDMFSTA +// +//***************************************************************************** +// Field: [5] OVFL +// +// FIFO overflow error. If this flag is asserted the modem FIFO must be +// re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it. Note that +// re-initializing will flush the FIFO. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_OVFL 0x00000020U +#define LRFDPBE_MDMFSTA_OVFL_M 0x00000020U +#define LRFDPBE_MDMFSTA_OVFL_S 5U +#define LRFDPBE_MDMFSTA_OVFL_ONE 0x00000020U +#define LRFDPBE_MDMFSTA_OVFL_ZERO 0x00000000U + +// Field: [4] ALMOSTFULL +// +// FIFO is almost full. Asserts when the FIFO fill level is above the almost +// full threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_ALMOSTFULL 0x00000010U +#define LRFDPBE_MDMFSTA_ALMOSTFULL_M 0x00000010U +#define LRFDPBE_MDMFSTA_ALMOSTFULL_S 4U +#define LRFDPBE_MDMFSTA_ALMOSTFULL_ONE 0x00000010U +#define LRFDPBE_MDMFSTA_ALMOSTFULL_ZERO 0x00000000U + +// Field: [3] ALMOSTEMPTY +// +// FIFO is almost empty. Asserts when the FIFO fill level is below the almost +// empty threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_ALMOSTEMPTY 0x00000008U +#define LRFDPBE_MDMFSTA_ALMOSTEMPTY_M 0x00000008U +#define LRFDPBE_MDMFSTA_ALMOSTEMPTY_S 3U +#define LRFDPBE_MDMFSTA_ALMOSTEMPTY_ONE 0x00000008U +#define LRFDPBE_MDMFSTA_ALMOSTEMPTY_ZERO 0x00000000U + +// Field: [2] UNFL +// +// FIFO underflow error. If this flag is asserted the modem FIFO must be +// re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_UNFL 0x00000004U +#define LRFDPBE_MDMFSTA_UNFL_M 0x00000004U +#define LRFDPBE_MDMFSTA_UNFL_S 2U +#define LRFDPBE_MDMFSTA_UNFL_ONE 0x00000004U +#define LRFDPBE_MDMFSTA_UNFL_ZERO 0x00000000U + +// Field: [1] RXVALID +// +// A full data word is valid and can be read in LRFDMDM:FIFORD register read +// port. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_RXVALID 0x00000002U +#define LRFDPBE_MDMFSTA_RXVALID_M 0x00000002U +#define LRFDPBE_MDMFSTA_RXVALID_S 1U +#define LRFDPBE_MDMFSTA_RXVALID_ONE 0x00000002U +#define LRFDPBE_MDMFSTA_RXVALID_ZERO 0x00000000U + +// Field: [0] TXREADY +// +// The LRFDMDM:FIFOWR register write port is ready to receive a data word. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_MDMFSTA_TXREADY 0x00000001U +#define LRFDPBE_MDMFSTA_TXREADY_M 0x00000001U +#define LRFDPBE_MDMFSTA_TXREADY_S 0U +#define LRFDPBE_MDMFSTA_TXREADY_ONE 0x00000001U +#define LRFDPBE_MDMFSTA_TXREADY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_PHASTA +// +//***************************************************************************** +// Field: [1:0] BUSY +// +// Status busy flags. +// ENUMs: +// BUSY LFSR n sub-engine busy +// IDLE LFSR n sub-engine idle +#define LRFDPBE_PHASTA_BUSY_W 2U +#define LRFDPBE_PHASTA_BUSY_M 0x00000003U +#define LRFDPBE_PHASTA_BUSY_S 0U +#define LRFDPBE_PHASTA_BUSY_BUSY 0x00000001U +#define LRFDPBE_PHASTA_BUSY_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 0 low part value, bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0L_VALLSB_W 16U +#define LRFDPBE_LFSR0L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_LFSR0L_VALLSB_S 0U +#define LRFDPBE_LFSR0L_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR0L_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 0 high part value, bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0H_VALMSB_W 16U +#define LRFDPBE_LFSR0H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_LFSR0H_VALMSB_S 0U +#define LRFDPBE_LFSR0H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR0H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0BRL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 0 value, bit reversed order bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0BRL_VALLSB_W 16U +#define LRFDPBE_LFSR0BRL_VALLSB_M 0x0000FFFFU +#define LRFDPBE_LFSR0BRL_VALLSB_S 0U +#define LRFDPBE_LFSR0BRL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR0BRL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0BRH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 0 value, bit reversed order bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0BRH_VALMSB_W 16U +#define LRFDPBE_LFSR0BRH_VALMSB_M 0x0000FFFFU +#define LRFDPBE_LFSR0BRH_VALMSB_S 0U +#define LRFDPBE_LFSR0BRH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR0BRH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 1 low part value, bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1L_VALLSB_W 16U +#define LRFDPBE_LFSR1L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_LFSR1L_VALLSB_S 0U +#define LRFDPBE_LFSR1L_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR1L_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 1 high part value, bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1H_VALMSB_W 16U +#define LRFDPBE_LFSR1H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_LFSR1H_VALMSB_S 0U +#define LRFDPBE_LFSR1H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR1H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1BRL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// LFSR 1 value, bit reversed order bits 15:0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1BRL_VALLSB_W 16U +#define LRFDPBE_LFSR1BRL_VALLSB_M 0x0000FFFFU +#define LRFDPBE_LFSR1BRL_VALLSB_S 0U +#define LRFDPBE_LFSR1BRL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR1BRL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1BRH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// LFSR 1 value, bit reversed order bits 31:16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1BRH_VALMSB_W 16U +#define LRFDPBE_LFSR1BRH_VALMSB_M 0x0000FFFFU +#define LRFDPBE_LFSR1BRH_VALMSB_S 0U +#define LRFDPBE_LFSR1BRH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDPBE_LFSR1BRH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0INL +// +//***************************************************************************** +// Field: [15:0] VAL +// +// LFSR 0 input value LSB first +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0INL_VAL_W 16U +#define LRFDPBE_LFSR0INL_VAL_M 0x0000FFFFU +#define LRFDPBE_LFSR0INL_VAL_S 0U +#define LRFDPBE_LFSR0INL_VAL_ALLONES 0x00000003U +#define LRFDPBE_LFSR0INL_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0N +// +//***************************************************************************** +// Field: [3:0] SIZE +// +// Number of bits to clock into LSFR0 upon next write to LFSR0INL or LFSR0INM +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR0N_SIZE_W 4U +#define LRFDPBE_LFSR0N_SIZE_M 0x0000000FU +#define LRFDPBE_LFSR0N_SIZE_S 0U +#define LRFDPBE_LFSR0N_SIZE_ALLONES 0x0000000FU +#define LRFDPBE_LFSR0N_SIZE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR0INM +// +//***************************************************************************** +// Field: [15:0] VAL +// +// LFSR 0 input value MSB first +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_LFSR0INM_VAL_W 16U +#define LRFDPBE_LFSR0INM_VAL_M 0x0000FFFFU +#define LRFDPBE_LFSR0INM_VAL_S 0U +#define LRFDPBE_LFSR0INM_VAL_ONE 0x00000001U +#define LRFDPBE_LFSR0INM_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_PHAOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Output value of LFSR0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_PHAOUT0_VAL_W 16U +#define LRFDPBE_PHAOUT0_VAL_M 0x0000FFFFU +#define LRFDPBE_PHAOUT0_VAL_S 0U +#define LRFDPBE_PHAOUT0_VAL_ALLONES 0x0000DCD7U +#define LRFDPBE_PHAOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1INL +// +//***************************************************************************** +// Field: [15:0] VAL +// +// LFSR 1 input value LSB first +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1INL_VAL_W 16U +#define LRFDPBE_LFSR1INL_VAL_M 0x0000FFFFU +#define LRFDPBE_LFSR1INL_VAL_S 0U +#define LRFDPBE_LFSR1INL_VAL_ALLONES 0x00000003U +#define LRFDPBE_LFSR1INL_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1N +// +//***************************************************************************** +// Field: [3:0] SIZE +// +// Number of bits to clock into LSFR1 upon next write to LFSR1INL or LFSR1INM +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_LFSR1N_SIZE_W 4U +#define LRFDPBE_LFSR1N_SIZE_M 0x0000000FU +#define LRFDPBE_LFSR1N_SIZE_S 0U +#define LRFDPBE_LFSR1N_SIZE_ALLONES 0x0000000FU +#define LRFDPBE_LFSR1N_SIZE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_LFSR1INM +// +//***************************************************************************** +// Field: [15:0] VAL +// +// LFSR 1 input value MSB first +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_LFSR1INM_VAL_W 16U +#define LRFDPBE_LFSR1INM_VAL_M 0x0000FFFFU +#define LRFDPBE_LFSR1INM_VAL_S 0U +#define LRFDPBE_LFSR1INM_VAL_ONE 0x00000001U +#define LRFDPBE_LFSR1INM_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_PHAOUT0BR +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Output value of LFSR0 in bit reversed order +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_PHAOUT0BR_VAL_W 16U +#define LRFDPBE_PHAOUT0BR_VAL_M 0x0000FFFFU +#define LRFDPBE_PHAOUT0BR_VAL_S 0U +#define LRFDPBE_PHAOUT0BR_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE_PHAOUT0BR_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM0L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// SYSTIM0 capture low part value, bits 15:0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM0L_VALLSB_W 16U +#define LRFDPBE_SYSTIM0L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM0L_VALLSB_S 0U +#define LRFDPBE_SYSTIM0L_VALLSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM0L_VALLSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM0H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// SYSTIM0 capture high part value, bits 31:16 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM0H_VALMSB_W 16U +#define LRFDPBE_SYSTIM0H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM0H_VALMSB_S 0U +#define LRFDPBE_SYSTIM0H_VALMSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM0H_VALMSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM1L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// SYSTIM1 capture low part value, bits 15:0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM1L_VALLSB_W 16U +#define LRFDPBE_SYSTIM1L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM1L_VALLSB_S 0U +#define LRFDPBE_SYSTIM1L_VALLSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM1L_VALLSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM1H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// SYSTIM1 capture high part value, bits 31:16 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM1H_VALMSB_W 16U +#define LRFDPBE_SYSTIM1H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM1H_VALMSB_S 0U +#define LRFDPBE_SYSTIM1H_VALMSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM1H_VALMSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM2L +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// SYSTIM2 capture low part value, bits 15:0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM2L_VALLSB_W 16U +#define LRFDPBE_SYSTIM2L_VALLSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM2L_VALLSB_S 0U +#define LRFDPBE_SYSTIM2L_VALLSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM2L_VALLSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_SYSTIM2H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// SYSTIM2 capture high part value, bits 31:16 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_SYSTIM2H_VALMSB_W 16U +#define LRFDPBE_SYSTIM2H_VALMSB_M 0x0000FFFFU +#define LRFDPBE_SYSTIM2H_VALMSB_S 0U +#define LRFDPBE_SYSTIM2H_VALMSB_ONE 0x00000001U +#define LRFDPBE_SYSTIM2H_VALMSB_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_GPI +// +//***************************************************************************** +// Field: [7] GPI7 +// +// Control GPI7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI7 0x00000080U +#define LRFDPBE_GPI_GPI7_M 0x00000080U +#define LRFDPBE_GPI_GPI7_S 7U +#define LRFDPBE_GPI_GPI7_ONE 0x00000080U +#define LRFDPBE_GPI_GPI7_ZERO 0x00000000U + +// Field: [6] GPI6 +// +// Control GPI6 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI6 0x00000040U +#define LRFDPBE_GPI_GPI6_M 0x00000040U +#define LRFDPBE_GPI_GPI6_S 6U +#define LRFDPBE_GPI_GPI6_ONE 0x00000040U +#define LRFDPBE_GPI_GPI6_ZERO 0x00000000U + +// Field: [5] GPI5 +// +// Control GPI5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI5 0x00000020U +#define LRFDPBE_GPI_GPI5_M 0x00000020U +#define LRFDPBE_GPI_GPI5_S 5U +#define LRFDPBE_GPI_GPI5_ONE 0x00000020U +#define LRFDPBE_GPI_GPI5_ZERO 0x00000000U + +// Field: [4] GPI4 +// +// Control GPI4 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI4 0x00000010U +#define LRFDPBE_GPI_GPI4_M 0x00000010U +#define LRFDPBE_GPI_GPI4_S 4U +#define LRFDPBE_GPI_GPI4_ONE 0x00000010U +#define LRFDPBE_GPI_GPI4_ZERO 0x00000000U + +// Field: [3] GPI3 +// +// Control GPI3 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI3 0x00000008U +#define LRFDPBE_GPI_GPI3_M 0x00000008U +#define LRFDPBE_GPI_GPI3_S 3U +#define LRFDPBE_GPI_GPI3_ONE 0x00000008U +#define LRFDPBE_GPI_GPI3_ZERO 0x00000000U + +// Field: [2] GPI2 +// +// Control GPI2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI2 0x00000004U +#define LRFDPBE_GPI_GPI2_M 0x00000004U +#define LRFDPBE_GPI_GPI2_S 2U +#define LRFDPBE_GPI_GPI2_ONE 0x00000004U +#define LRFDPBE_GPI_GPI2_ZERO 0x00000000U + +// Field: [1] GPI1 +// +// Control GPI1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI1 0x00000002U +#define LRFDPBE_GPI_GPI1_M 0x00000002U +#define LRFDPBE_GPI_GPI1_S 1U +#define LRFDPBE_GPI_GPI1_ONE 0x00000002U +#define LRFDPBE_GPI_GPI1_ZERO 0x00000000U + +// Field: [0] GPI0 +// +// Control GPI0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE_GPI_GPI0 0x00000001U +#define LRFDPBE_GPI_GPI0_M 0x00000001U +#define LRFDPBE_GPI_GPI0_S 0U +#define LRFDPBE_GPI_GPI0_ONE 0x00000001U +#define LRFDPBE_GPI_GPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FCMD +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Command either RX or TX FIFO or both. Strobe signals which clear after +// write. +// ENUMs: +// FIFO_COMMIT Commit both FIFOs +// FIFO_DISCARD Discard both FIFOs +// FIFO_RETRY Retry both FIFOs +// FIFO_DEALLOC Deallocate both FIFOS +// FIFO_RESET Reset (empty) both FIFOs +// RXFIFO_RETRY Retry rxfifo. This sets RXFRP := RXFSRP +// RXFIFO_DISCARD Discard rxfifo. This sets RXFWP := RXFSWP +// RXFIFO_COMMIT Commit rxfifo. This sets RXFSWP := RXFWP +// TXFIFO_RESET Reset (empty) txfifo. Set TXF* := 0 +// TXFIFO_DEALLOC Deallocate txfifo. This sets TXFSRP := TXFRP. +// TXFIFO_RETRY Retry txfifo. This sets TXFRP := TXFSRP +// TXFIFO_DISCARD Discard txfifo. This sets TXFWP := TXFSWP +// TXFIFO_COMMIT Commit txfifo. This sets TXFSWP := TXFWP +// RXFIFO_DEALLOC Deallocate rxfifo. This sets RXFSRP := RXFRP. +// RXFIFO_RESET Reset (empty) rxfifo. Set RXF* := 0 +#define LRFDPBE_FCMD_DATA_W 8U +#define LRFDPBE_FCMD_DATA_M 0x000000FFU +#define LRFDPBE_FCMD_DATA_S 0U +#define LRFDPBE_FCMD_DATA_FIFO_COMMIT 0x0000000FU +#define LRFDPBE_FCMD_DATA_FIFO_DISCARD 0x0000000EU +#define LRFDPBE_FCMD_DATA_FIFO_RETRY 0x0000000DU +#define LRFDPBE_FCMD_DATA_FIFO_DEALLOC 0x0000000CU +#define LRFDPBE_FCMD_DATA_FIFO_RESET 0x0000000BU +#define LRFDPBE_FCMD_DATA_RXFIFO_RETRY 0x0000000AU +#define LRFDPBE_FCMD_DATA_RXFIFO_DISCARD 0x00000009U +#define LRFDPBE_FCMD_DATA_RXFIFO_COMMIT 0x00000008U +#define LRFDPBE_FCMD_DATA_TXFIFO_RESET 0x00000007U +#define LRFDPBE_FCMD_DATA_TXFIFO_DEALLOC 0x00000006U +#define LRFDPBE_FCMD_DATA_TXFIFO_RETRY 0x00000005U +#define LRFDPBE_FCMD_DATA_TXFIFO_DISCARD 0x00000004U +#define LRFDPBE_FCMD_DATA_TXFIFO_COMMIT 0x00000003U +#define LRFDPBE_FCMD_DATA_RXFIFO_DEALLOC 0x00000002U +#define LRFDPBE_FCMD_DATA_RXFIFO_RESET 0x00000001U + +//***************************************************************************** +// +// Register: LRFDPBE_O_FSTAT +// +//***************************************************************************** +// Field: [11] TXUNFL +// +// Underflow occurred in the TX FIFO. +// ENUMs: +// TRUE Underflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE_FSTAT_TXUNFL 0x00000800U +#define LRFDPBE_FSTAT_TXUNFL_M 0x00000800U +#define LRFDPBE_FSTAT_TXUNFL_S 11U +#define LRFDPBE_FSTAT_TXUNFL_TRUE 0x00000800U +#define LRFDPBE_FSTAT_TXUNFL_FALSE 0x00000000U + +// Field: [10] TXOVFL +// +// Overflow occurred in the TX FIFO. +// ENUMs: +// TRUE Overflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE_FSTAT_TXOVFL 0x00000400U +#define LRFDPBE_FSTAT_TXOVFL_M 0x00000400U +#define LRFDPBE_FSTAT_TXOVFL_S 10U +#define LRFDPBE_FSTAT_TXOVFL_TRUE 0x00000400U +#define LRFDPBE_FSTAT_TXOVFL_FALSE 0x00000000U + +// Field: [9] TXEMPTY +// +// TXFIFO empty flag +// ENUMs: +// TRUE TXFIFO is empty +// FALSE TXFIFO is not empty +#define LRFDPBE_FSTAT_TXEMPTY 0x00000200U +#define LRFDPBE_FSTAT_TXEMPTY_M 0x00000200U +#define LRFDPBE_FSTAT_TXEMPTY_S 9U +#define LRFDPBE_FSTAT_TXEMPTY_TRUE 0x00000200U +#define LRFDPBE_FSTAT_TXEMPTY_FALSE 0x00000000U + +// Field: [8] TXFULL +// +// TXFIFO full flag +// ENUMs: +// TRUE TXFIFO is full +// FALSE TXFIFO is not full +#define LRFDPBE_FSTAT_TXFULL 0x00000100U +#define LRFDPBE_FSTAT_TXFULL_M 0x00000100U +#define LRFDPBE_FSTAT_TXFULL_S 8U +#define LRFDPBE_FSTAT_TXFULL_TRUE 0x00000100U +#define LRFDPBE_FSTAT_TXFULL_FALSE 0x00000000U + +// Field: [3] RXUNFL +// +// Underflow occurred in the RX FIFO. +// ENUMs: +// TRUE Underflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE_FSTAT_RXUNFL 0x00000008U +#define LRFDPBE_FSTAT_RXUNFL_M 0x00000008U +#define LRFDPBE_FSTAT_RXUNFL_S 3U +#define LRFDPBE_FSTAT_RXUNFL_TRUE 0x00000008U +#define LRFDPBE_FSTAT_RXUNFL_FALSE 0x00000000U + +// Field: [2] RXOVFL +// +// Overflow occurred in the RX FIFO. +// ENUMs: +// TRUE Overflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE_FSTAT_RXOVFL 0x00000004U +#define LRFDPBE_FSTAT_RXOVFL_M 0x00000004U +#define LRFDPBE_FSTAT_RXOVFL_S 2U +#define LRFDPBE_FSTAT_RXOVFL_TRUE 0x00000004U +#define LRFDPBE_FSTAT_RXOVFL_FALSE 0x00000000U + +// Field: [1] RXEMPTY +// +// RXFIFO empty flag +// ENUMs: +// TRUE RXFIFO is empty +// FALSE RXFIFO is not empty +#define LRFDPBE_FSTAT_RXEMPTY 0x00000002U +#define LRFDPBE_FSTAT_RXEMPTY_M 0x00000002U +#define LRFDPBE_FSTAT_RXEMPTY_S 1U +#define LRFDPBE_FSTAT_RXEMPTY_TRUE 0x00000002U +#define LRFDPBE_FSTAT_RXEMPTY_FALSE 0x00000000U + +// Field: [0] RXFULL +// +// RXFIFO full flag +// ENUMs: +// TRUE RXFIFO is full +// FALSE RXFIFO is not full +#define LRFDPBE_FSTAT_RXFULL 0x00000001U +#define LRFDPBE_FSTAT_RXFULL_M 0x00000001U +#define LRFDPBE_FSTAT_RXFULL_S 0U +#define LRFDPBE_FSTAT_RXFULL_TRUE 0x00000001U +#define LRFDPBE_FSTAT_RXFULL_FALSE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFWP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Write pointer +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFWP_PTR_W 10U +#define LRFDPBE_RXFWP_PTR_M 0x000003FFU +#define LRFDPBE_RXFWP_PTR_S 0U +#define LRFDPBE_RXFWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_RXFWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFRP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Read pointer +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFRP_PTR_W 10U +#define LRFDPBE_RXFRP_PTR_M 0x000003FFU +#define LRFDPBE_RXFRP_PTR_S 0U +#define LRFDPBE_RXFRP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_RXFRP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFSWP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Pointer to start of written package +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFSWP_PTR_W 10U +#define LRFDPBE_RXFSWP_PTR_M 0x000003FFU +#define LRFDPBE_RXFSWP_PTR_S 0U +#define LRFDPBE_RXFSWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_RXFSWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFSRP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Pointer to start of read package +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFSRP_PTR_W 10U +#define LRFDPBE_RXFSRP_PTR_M 0x000003FFU +#define LRFDPBE_RXFSRP_PTR_S 0U +#define LRFDPBE_RXFSRP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_RXFSRP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFWP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Write pointer +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFWP_PTR_W 10U +#define LRFDPBE_TXFWP_PTR_M 0x000003FFU +#define LRFDPBE_TXFWP_PTR_S 0U +#define LRFDPBE_TXFWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_TXFWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFRP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Read pointer +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFRP_PTR_W 10U +#define LRFDPBE_TXFRP_PTR_M 0x000003FFU +#define LRFDPBE_TXFRP_PTR_S 0U +#define LRFDPBE_TXFRP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_TXFRP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFSWP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Pointer to start of written package +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFSWP_PTR_W 10U +#define LRFDPBE_TXFSWP_PTR_M 0x000003FFU +#define LRFDPBE_TXFSWP_PTR_S 0U +#define LRFDPBE_TXFSWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE_TXFSWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFSRP +// +//***************************************************************************** +// Field: [9:0] PTR +// +// Pointer to start of read package +// ENUMs: +// ALLONES_2 All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFSRP_PTR_W 10U +#define LRFDPBE_TXFSRP_PTR_M 0x000003FFU +#define LRFDPBE_TXFSRP_PTR_S 0U +#define LRFDPBE_TXFSRP_PTR_ALLONES_2 0x000003FFU +#define LRFDPBE_TXFSRP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFWRITABLE +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// The amount of writable bytes for the RX FIFO may be directly read here +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFWRITABLE_BYTES_W 10U +#define LRFDPBE_RXFWRITABLE_BYTES_M 0x000003FFU +#define LRFDPBE_RXFWRITABLE_BYTES_S 0U +#define LRFDPBE_RXFWRITABLE_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_RXFWRITABLE_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFREADABLE +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// The amount of readable bytes for the RX FIFO may be directly read here +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFREADABLE_BYTES_W 10U +#define LRFDPBE_RXFREADABLE_BYTES_M 0x000003FFU +#define LRFDPBE_RXFREADABLE_BYTES_S 0U +#define LRFDPBE_RXFREADABLE_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_RXFREADABLE_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFWRITABLE +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// The amount of writable bytes for the TX FIFO may be directly read here +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFWRITABLE_BYTES_W 10U +#define LRFDPBE_TXFWRITABLE_BYTES_M 0x000003FFU +#define LRFDPBE_TXFWRITABLE_BYTES_S 0U +#define LRFDPBE_TXFWRITABLE_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_TXFWRITABLE_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFREADABLE +// +//***************************************************************************** +// Field: [9:0] BYTES +// +// The amount of readable bytes for the TX FIFO may be directly read here +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFREADABLE_BYTES_W 10U +#define LRFDPBE_TXFREADABLE_BYTES_M 0x000003FFU +#define LRFDPBE_TXFREADABLE_BYTES_S 0U +#define LRFDPBE_TXFREADABLE_BYTES_ALLONES 0x000003FFU +#define LRFDPBE_TXFREADABLE_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFBRD +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data to be read +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFBRD_DATA_W 8U +#define LRFDPBE_RXFBRD_DATA_M 0x000000FFU +#define LRFDPBE_RXFBRD_DATA_S 0U +#define LRFDPBE_RXFBRD_DATA_ALLONES 0x000000FFU +#define LRFDPBE_RXFBRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFBWR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data to be written +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFBWR_DATA_W 8U +#define LRFDPBE_RXFBWR_DATA_M 0x000000FFU +#define LRFDPBE_RXFBWR_DATA_S 0U +#define LRFDPBE_RXFBWR_DATA_ALLONES 0x000000FFU +#define LRFDPBE_RXFBWR_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFBRD +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data to be read +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFBRD_DATA_W 8U +#define LRFDPBE_TXFBRD_DATA_M 0x000000FFU +#define LRFDPBE_TXFBRD_DATA_S 0U +#define LRFDPBE_TXFBRD_DATA_ALLONES 0x000000FFU +#define LRFDPBE_TXFBRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFBWR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data to be written +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFBWR_DATA_W 8U +#define LRFDPBE_TXFBWR_DATA_M 0x000000FFU +#define LRFDPBE_TXFBWR_DATA_S 0U +#define LRFDPBE_TXFBWR_DATA_ALLONES 0x000000FFU +#define LRFDPBE_TXFBWR_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFHRD +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Data to be read +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFHRD_DATA_W 16U +#define LRFDPBE_RXFHRD_DATA_M 0x0000FFFFU +#define LRFDPBE_RXFHRD_DATA_S 0U +#define LRFDPBE_RXFHRD_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE_RXFHRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_RXFHWR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Data to be written +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_RXFHWR_DATA_W 16U +#define LRFDPBE_RXFHWR_DATA_M 0x0000FFFFU +#define LRFDPBE_RXFHWR_DATA_S 0U +#define LRFDPBE_RXFHWR_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE_RXFHWR_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFHRD +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Data to be read +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFHRD_DATA_W 16U +#define LRFDPBE_TXFHRD_DATA_M 0x0000FFFFU +#define LRFDPBE_TXFHRD_DATA_S 0U +#define LRFDPBE_TXFHRD_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE_TXFHRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE_O_TXFHWR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Data to be written +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE_TXFHWR_DATA_W 16U +#define LRFDPBE_TXFHWR_DATA_M 0x0000FFFFU +#define LRFDPBE_TXFHWR_DATA_S 0U +#define LRFDPBE_TXFHWR_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE_TXFHWR_DATA_ALLZEROS 0x00000000U + + +#endif // __LRFDPBE__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe32.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe32.h new file mode 100644 index 00000000..f4e15204 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdpbe32.h @@ -0,0 +1,3599 @@ +/****************************************************************************** +* Filename: hw_lrfdpbe32_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDPBE32_H__ +#define __HW_LRFDPBE32_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDPBE32 component +// +//***************************************************************************** +// Packet Building Engine Enable Register +#define LRFDPBE32_O_FWSRC_ENABLE 0x00000000U + +// Packet Building Engine Initialization Register +#define LRFDPBE32_O_STROBES0_INIT 0x00000004U + +// Interrupt generate register +#define LRFDPBE32_O_EVT0_IRQ 0x00000008U + +// PBE Event Flag Register 1 +#define LRFDPBE32_O_EVTMSK0_EVT1 0x0000000CU + +// PBE Event Mask Register 1 +#define LRFDPBE32_O_EVTCLR0_EVTMSK1 0x00000010U + +// PBE Event Mask Register 1 +#define LRFDPBE32_O_PDREQ_EVTCLR1 0x00000014U + +// PBE API Command Register +#define LRFDPBE32_O_MCEDATOUT0_API 0x00000018U + +// MCE-to-PBE Receive Data Register +#define LRFDPBE32_O_MCECMDOUT_MCEDATIN0 0x0000001CU + +// MCE-to-PBE Receive Command Register +#define LRFDPBE32_O_MDMAPI_MCECMDIN 0x00000020U + +// Modem Command Status Register +#define LRFDPBE32_O_FREQ_MDMMSGBOX 0x00000024U + +// Link quality indicator +#define LRFDPBE32_O_RFEDATOUT0_MDMLQI 0x00000028U + +// RFE-to-PBE Receive Data Register +#define LRFDPBE32_O_RFECMDOUT_RFEDATIN0 0x0000002CU + +// RFE-to-PBE Receive Command Register +#define LRFDPBE32_O_RFEAPI_RFECMDIN 0x00000030U + +// RFE Command Parameter 0 +#define LRFDPBE32_O_RFECMDPAR1_RFECMDPAR0 0x00000034U + +// RFE Command Status and Message Box Register +#define LRFDPBE32_O_RFERSSI_RFEMSGBOX 0x00000038U + +// RSSI Maximum Value Register +#define LRFDPBE32_O_RFERFGAIN_RFERSSIMAX 0x0000003CU + +// Modem Sync Word Register 0 +#define LRFDPBE32_O_MDMSYNCA 0x00000040U + +// Modem Sync Word Register 2 +#define LRFDPBE32_O_MDMSYNCB 0x00000044U + +// Modem API Command Parameter 0 +#define LRFDPBE32_O_MDMCMDPAR1_MDMCMDPAR0 0x00000048U + +// Modem API Command Parameter 2 +#define LRFDPBE32_O_MDMCMDPAR2 0x0000004CU + +// LFSR 0 Polynomial Definition +#define LRFDPBE32_O_POLY0 0x00000050U + +// LFSR 1 Polynomial Definition +#define LRFDPBE32_O_POLY1 0x00000054U + +// Packet Handler Accelerator Config Register +#define LRFDPBE32_O_FCFG0_PHACFG 0x00000058U + +// FIFO configuration register +#define LRFDPBE32_O_FCFG2_FCFG1 0x0000005CU + +// FIFO configuration register +#define LRFDPBE32_O_FCFG4_FCFG3 0x00000060U + +// FIFO configuration register +#define LRFDPBE32_O_RXFWBTHRS_FCFG5 0x00000064U + +// FIFO read pointer +#define LRFDPBE32_O_TXFWBTHRS_RXFRBTHRS 0x00000068U + +// FIFO read pointer +#define LRFDPBE32_O_TIMCTL_TXFRBTHRS 0x0000006CU + +// Prescaler setting for timer 0 and timer 1 +#define LRFDPBE32_O_TIMPER0_TIMPRE 0x00000070U + +// PBE Timer Period Configuration +#define LRFDPBE32_O_TIMCAPT0_TIMPER1 0x00000074U + +// PBE Counter Capture Value +#define LRFDPBE32_O_TIMCAPT1 0x00000078U + +// PBE Tracer Send Trigger Register +#define LRFDPBE32_O_TRCSTAT_TRCCTL 0x00000080U + +// PBE Tracer Commmand Register +#define LRFDPBE32_O_TRCPAR0_TRCCMD 0x00000084U + +// PBE Tracer Command Parameter Register 1 +#define LRFDPBE32_O_GPOCTRL_TRCPAR1 0x00000088U + +// Modem FIFO Write Register +#define LRFDPBE32_O_MDMFRD_MDMFWR 0x0000008CU + +// Modem FIFO Write Configuration +#define LRFDPBE32_O_MDMFRDCTL_MDMFWRCTL 0x00000090U + +// Modem FIFO Configuration for watermark thresholds +#define LRFDPBE32_O_MDMFSTA_MDMFCFG 0x00000094U + +// Packet Handler Accelerator Status +#define LRFDPBE32_O_PHASTA 0x00000098U + +// LFSR 0 Current Value +#define LRFDPBE32_O_LFSR0 0x0000009CU + +// LFSR 0 Current Value, Bit-reversed +#define LRFDPBE32_O_LFSR0BR 0x000000A0U + +// LFSR 1 Current Value +#define LRFDPBE32_O_LFSR1 0x000000A4U + +// LFSR 1 Current Value, Bit-reversed +#define LRFDPBE32_O_LFSR1BR 0x000000A8U + +// LFSR 0 Input, LSB First +#define LRFDPBE32_O_LFSR0N_LFSR0INL 0x000000ACU + +// LFSR 0 Input, MSB First +#define LRFDPBE32_O_PHAOUT0_LFSR0INM 0x000000B0U + +// LFSR 1 Input, LSB First +#define LRFDPBE32_O_LFSR1N_LFSR1INL 0x000000B4U + +// LFSR 1 Input, MSB First +#define LRFDPBE32_O_PHAOUT0BR_LFSR1INM 0x000000B8U + +// Systimer capture value +#define LRFDPBE32_O_SYSTIM0 0x000000C0U + +// Systimer capture value +#define LRFDPBE32_O_SYSTIM1 0x000000C4U + +// Systimer capture value +#define LRFDPBE32_O_SYSTIM2 0x000000C8U + +// PBE Direct GPI Status +#define LRFDPBE32_O_GPI 0x000000CCU + +// The FIFO command register +#define LRFDPBE32_O_FSTAT_FCMD 0x000000D0U + +// FIFO write pointer +#define LRFDPBE32_O_RXFRP_RXFWP 0x000000D4U + +// Rx FIFO start of written package +#define LRFDPBE32_O_RXFSRP_RXFSWP 0x000000D8U + +// TXFIFO write pointer +#define LRFDPBE32_O_TXFRP_TXFWP 0x000000DCU + +// TXFIFO start of written package +#define LRFDPBE32_O_TXFSRP_TXFSWP 0x000000E0U + +// The amount of bytes which are deallocated and not yet written. +#define LRFDPBE32_O_RXFREADABLE_RXFWRITABLE 0x000000E4U + +// The amount of bytes which are deallocated and not yet written. +#define LRFDPBE32_O_TXFREADABLE_TXFWRITABLE 0x000000E8U + +// FIFO read access register +#define LRFDPBE32_O_RXFBWR_RXFBRD 0x000000ECU + +// FIFO read access register +#define LRFDPBE32_O_TXFBWR_TXFBRD 0x000000F0U + +// FIFO read access register +#define LRFDPBE32_O_RXFHWR_RXFHRD 0x000000F4U + +// FIFO read access register +#define LRFDPBE32_O_TXFHWR_TXFHRD 0x000000F8U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FWSRC_ENABLE +// +//***************************************************************************** +// Field: [18] DATARAM +// +// ENUMs: +// S2RRAM Use S2RRAM for data +// PBERAM Use PBERAM for data +#define LRFDPBE32_FWSRC_ENABLE_DATARAM 0x00040000U +#define LRFDPBE32_FWSRC_ENABLE_DATARAM_M 0x00040000U +#define LRFDPBE32_FWSRC_ENABLE_DATARAM_S 18U +#define LRFDPBE32_FWSRC_ENABLE_DATARAM_S2RRAM 0x00040000U +#define LRFDPBE32_FWSRC_ENABLE_DATARAM_PBERAM 0x00000000U + +// Field: [17] FWRAM +// +// ENUMs: +// S2RRAM Run code from S2RRAM +// PBERAM Run code from PBERAM +#define LRFDPBE32_FWSRC_ENABLE_FWRAM 0x00020000U +#define LRFDPBE32_FWSRC_ENABLE_FWRAM_M 0x00020000U +#define LRFDPBE32_FWSRC_ENABLE_FWRAM_S 17U +#define LRFDPBE32_FWSRC_ENABLE_FWRAM_S2RRAM 0x00020000U +#define LRFDPBE32_FWSRC_ENABLE_FWRAM_PBERAM 0x00000000U + +// Field: [16] BANK +// +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDPBE32_FWSRC_ENABLE_BANK 0x00010000U +#define LRFDPBE32_FWSRC_ENABLE_BANK_M 0x00010000U +#define LRFDPBE32_FWSRC_ENABLE_BANK_S 16U +#define LRFDPBE32_FWSRC_ENABLE_BANK_ONE 0x00010000U +#define LRFDPBE32_FWSRC_ENABLE_BANK_ZERO 0x00000000U + +// Field: [2] MDMF +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_FWSRC_ENABLE_MDMF 0x00000004U +#define LRFDPBE32_FWSRC_ENABLE_MDMF_M 0x00000004U +#define LRFDPBE32_FWSRC_ENABLE_MDMF_S 2U +#define LRFDPBE32_FWSRC_ENABLE_MDMF_EN 0x00000004U +#define LRFDPBE32_FWSRC_ENABLE_MDMF_DIS 0x00000000U + +// Field: [1] LOCTIM +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_FWSRC_ENABLE_LOCTIM 0x00000002U +#define LRFDPBE32_FWSRC_ENABLE_LOCTIM_M 0x00000002U +#define LRFDPBE32_FWSRC_ENABLE_LOCTIM_S 1U +#define LRFDPBE32_FWSRC_ENABLE_LOCTIM_EN 0x00000002U +#define LRFDPBE32_FWSRC_ENABLE_LOCTIM_DIS 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_FWSRC_ENABLE_TOPSM 0x00000001U +#define LRFDPBE32_FWSRC_ENABLE_TOPSM_M 0x00000001U +#define LRFDPBE32_FWSRC_ENABLE_TOPSM_S 0U +#define LRFDPBE32_FWSRC_ENABLE_TOPSM_EN 0x00000001U +#define LRFDPBE32_FWSRC_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_STROBES0_INIT +// +//***************************************************************************** +// Field: [22] TIMCAPT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_STROBES0_INIT_TIMCAPT1 0x00400000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT1_M 0x00400000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT1_S 22U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT1_ONE 0x00400000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT1_ZERO 0x00000000U + +// Field: [21] TIMCAPT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_STROBES0_INIT_TIMCAPT0 0x00200000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT0_M 0x00200000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT0_S 21U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT0_ONE 0x00200000U +#define LRFDPBE32_STROBES0_INIT_TIMCAPT0_ZERO 0x00000000U + +// Field: [20] S2RTRIG +// +// ENUMs: +// ARM The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_S2RTRIG 0x00100000U +#define LRFDPBE32_STROBES0_INIT_S2RTRIG_M 0x00100000U +#define LRFDPBE32_STROBES0_INIT_S2RTRIG_S 20U +#define LRFDPBE32_STROBES0_INIT_S2RTRIG_ARM 0x00100000U +#define LRFDPBE32_STROBES0_INIT_S2RTRIG_NO_EFFECT 0x00000000U + +// Field: [19] DMATRIG +// +// ENUMs: +// ARM The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_DMATRIG 0x00080000U +#define LRFDPBE32_STROBES0_INIT_DMATRIG_M 0x00080000U +#define LRFDPBE32_STROBES0_INIT_DMATRIG_S 19U +#define LRFDPBE32_STROBES0_INIT_DMATRIG_ARM 0x00080000U +#define LRFDPBE32_STROBES0_INIT_DMATRIG_NO_EFFECT 0x00000000U + +// Field: [18] SYSTCAPT2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT2 0x00040000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_M 0x00040000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_S 18U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_ONE 0x00040000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_ZERO 0x00000000U + +// Field: [17] SYSTCAPT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT1 0x00020000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_M 0x00020000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_S 17U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_ONE 0x00020000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_ZERO 0x00000000U + +// Field: [16] SYSTCAPT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT0 0x00010000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_M 0x00010000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_S 16U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_ONE 0x00010000U +#define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_ZERO 0x00000000U + +// Field: [4] RFE +// +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_RFE 0x00000010U +#define LRFDPBE32_STROBES0_INIT_RFE_M 0x00000010U +#define LRFDPBE32_STROBES0_INIT_RFE_S 4U +#define LRFDPBE32_STROBES0_INIT_RFE_RESET 0x00000010U +#define LRFDPBE32_STROBES0_INIT_RFE_NO_EFFECT 0x00000000U + +// Field: [3] MDM +// +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_MDM 0x00000008U +#define LRFDPBE32_STROBES0_INIT_MDM_M 0x00000008U +#define LRFDPBE32_STROBES0_INIT_MDM_S 3U +#define LRFDPBE32_STROBES0_INIT_MDM_RESET 0x00000008U +#define LRFDPBE32_STROBES0_INIT_MDM_NO_EFFECT 0x00000000U + +// Field: [2] MDMF +// +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_MDMF 0x00000004U +#define LRFDPBE32_STROBES0_INIT_MDMF_M 0x00000004U +#define LRFDPBE32_STROBES0_INIT_MDMF_S 2U +#define LRFDPBE32_STROBES0_INIT_MDMF_RESET 0x00000004U +#define LRFDPBE32_STROBES0_INIT_MDMF_NO_EFFECT 0x00000000U + +// Field: [1] LOCTIM +// +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_LOCTIM 0x00000002U +#define LRFDPBE32_STROBES0_INIT_LOCTIM_M 0x00000002U +#define LRFDPBE32_STROBES0_INIT_LOCTIM_S 1U +#define LRFDPBE32_STROBES0_INIT_LOCTIM_RESET 0x00000002U +#define LRFDPBE32_STROBES0_INIT_LOCTIM_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// RESET The bit is 1 +// NO_EFFECT The bit is 0 +#define LRFDPBE32_STROBES0_INIT_TOPSM 0x00000001U +#define LRFDPBE32_STROBES0_INIT_TOPSM_M 0x00000001U +#define LRFDPBE32_STROBES0_INIT_TOPSM_S 0U +#define LRFDPBE32_STROBES0_INIT_TOPSM_RESET 0x00000001U +#define LRFDPBE32_STROBES0_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_EVT0_IRQ +// +//***************************************************************************** +// Field: [31] MDMFAEMPTY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY 0x80000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_M 0x80000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_S 31U +#define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_ONE 0x80000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_ZERO 0x00000000U + +// Field: [30] S2RSTOP +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_S2RSTOP 0x40000000U +#define LRFDPBE32_EVT0_IRQ_S2RSTOP_M 0x40000000U +#define LRFDPBE32_EVT0_IRQ_S2RSTOP_S 30U +#define LRFDPBE32_EVT0_IRQ_S2RSTOP_ONE 0x40000000U +#define LRFDPBE32_EVT0_IRQ_S2RSTOP_ZERO 0x00000000U + +// Field: [29] FIFOERR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_FIFOERR 0x20000000U +#define LRFDPBE32_EVT0_IRQ_FIFOERR_M 0x20000000U +#define LRFDPBE32_EVT0_IRQ_FIFOERR_S 29U +#define LRFDPBE32_EVT0_IRQ_FIFOERR_ONE 0x20000000U +#define LRFDPBE32_EVT0_IRQ_FIFOERR_ZERO 0x00000000U + +// Field: [28] MDMFAFULL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_MDMFAFULL 0x10000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAFULL_M 0x10000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAFULL_S 28U +#define LRFDPBE32_EVT0_IRQ_MDMFAFULL_ONE 0x10000000U +#define LRFDPBE32_EVT0_IRQ_MDMFAFULL_ZERO 0x00000000U + +// Field: [27] SYSTCMP2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SYSTCMP2 0x08000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP2_M 0x08000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP2_S 27U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP2_ONE 0x08000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP2_ZERO 0x00000000U + +// Field: [26] SYSTCMP1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SYSTCMP1 0x04000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP1_M 0x04000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP1_S 26U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP1_ONE 0x04000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP1_ZERO 0x00000000U + +// Field: [25] SYSTCMP0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SYSTCMP0 0x02000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP0_M 0x02000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP0_S 25U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP0_ONE 0x02000000U +#define LRFDPBE32_EVT0_IRQ_SYSTCMP0_ZERO 0x00000000U + +// Field: [24] MDMMSGBOX +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_MDMMSGBOX 0x01000000U +#define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_M 0x01000000U +#define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_S 24U +#define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_ONE 0x01000000U +#define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_ZERO 0x00000000U + +// Field: [23] RFEMSGBOX +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_RFEMSGBOX 0x00800000U +#define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_M 0x00800000U +#define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_S 23U +#define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_ONE 0x00800000U +#define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_ZERO 0x00000000U + +// Field: [22] RFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_RFEDAT 0x00400000U +#define LRFDPBE32_EVT0_IRQ_RFEDAT_M 0x00400000U +#define LRFDPBE32_EVT0_IRQ_RFEDAT_S 22U +#define LRFDPBE32_EVT0_IRQ_RFEDAT_ONE 0x00400000U +#define LRFDPBE32_EVT0_IRQ_RFEDAT_ZERO 0x00000000U + +// Field: [21] RFECMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_RFECMD 0x00200000U +#define LRFDPBE32_EVT0_IRQ_RFECMD_M 0x00200000U +#define LRFDPBE32_EVT0_IRQ_RFECMD_S 21U +#define LRFDPBE32_EVT0_IRQ_RFECMD_ONE 0x00200000U +#define LRFDPBE32_EVT0_IRQ_RFECMD_ZERO 0x00000000U + +// Field: [20] MDMDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_MDMDAT 0x00100000U +#define LRFDPBE32_EVT0_IRQ_MDMDAT_M 0x00100000U +#define LRFDPBE32_EVT0_IRQ_MDMDAT_S 20U +#define LRFDPBE32_EVT0_IRQ_MDMDAT_ONE 0x00100000U +#define LRFDPBE32_EVT0_IRQ_MDMDAT_ZERO 0x00000000U + +// Field: [19] MDMCMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_MDMCMD 0x00080000U +#define LRFDPBE32_EVT0_IRQ_MDMCMD_M 0x00080000U +#define LRFDPBE32_EVT0_IRQ_MDMCMD_S 19U +#define LRFDPBE32_EVT0_IRQ_MDMCMD_ONE 0x00080000U +#define LRFDPBE32_EVT0_IRQ_MDMCMD_ZERO 0x00000000U + +// Field: [18] TIMER1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_TIMER1 0x00040000U +#define LRFDPBE32_EVT0_IRQ_TIMER1_M 0x00040000U +#define LRFDPBE32_EVT0_IRQ_TIMER1_S 18U +#define LRFDPBE32_EVT0_IRQ_TIMER1_ONE 0x00040000U +#define LRFDPBE32_EVT0_IRQ_TIMER1_ZERO 0x00000000U + +// Field: [17] TIMER0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_TIMER0 0x00020000U +#define LRFDPBE32_EVT0_IRQ_TIMER0_M 0x00020000U +#define LRFDPBE32_EVT0_IRQ_TIMER0_S 17U +#define LRFDPBE32_EVT0_IRQ_TIMER0_ONE 0x00020000U +#define LRFDPBE32_EVT0_IRQ_TIMER0_ZERO 0x00000000U + +// Field: [16] PBEAPI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVT0_IRQ_PBEAPI 0x00010000U +#define LRFDPBE32_EVT0_IRQ_PBEAPI_M 0x00010000U +#define LRFDPBE32_EVT0_IRQ_PBEAPI_S 16U +#define LRFDPBE32_EVT0_IRQ_PBEAPI_ONE 0x00010000U +#define LRFDPBE32_EVT0_IRQ_PBEAPI_ZERO 0x00000000U + +// Field: [15] SOFT15 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT15 0x00008000U +#define LRFDPBE32_EVT0_IRQ_SOFT15_M 0x00008000U +#define LRFDPBE32_EVT0_IRQ_SOFT15_S 15U +#define LRFDPBE32_EVT0_IRQ_SOFT15_ON 0x00008000U +#define LRFDPBE32_EVT0_IRQ_SOFT15_OFF 0x00000000U + +// Field: [14] SOFT14 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT14 0x00004000U +#define LRFDPBE32_EVT0_IRQ_SOFT14_M 0x00004000U +#define LRFDPBE32_EVT0_IRQ_SOFT14_S 14U +#define LRFDPBE32_EVT0_IRQ_SOFT14_ON 0x00004000U +#define LRFDPBE32_EVT0_IRQ_SOFT14_OFF 0x00000000U + +// Field: [13] SOFT13 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT13 0x00002000U +#define LRFDPBE32_EVT0_IRQ_SOFT13_M 0x00002000U +#define LRFDPBE32_EVT0_IRQ_SOFT13_S 13U +#define LRFDPBE32_EVT0_IRQ_SOFT13_ON 0x00002000U +#define LRFDPBE32_EVT0_IRQ_SOFT13_OFF 0x00000000U + +// Field: [12] SOFT12 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT12 0x00001000U +#define LRFDPBE32_EVT0_IRQ_SOFT12_M 0x00001000U +#define LRFDPBE32_EVT0_IRQ_SOFT12_S 12U +#define LRFDPBE32_EVT0_IRQ_SOFT12_ON 0x00001000U +#define LRFDPBE32_EVT0_IRQ_SOFT12_OFF 0x00000000U + +// Field: [11] SOFT11 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT11 0x00000800U +#define LRFDPBE32_EVT0_IRQ_SOFT11_M 0x00000800U +#define LRFDPBE32_EVT0_IRQ_SOFT11_S 11U +#define LRFDPBE32_EVT0_IRQ_SOFT11_ON 0x00000800U +#define LRFDPBE32_EVT0_IRQ_SOFT11_OFF 0x00000000U + +// Field: [10] SOFT10 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT10 0x00000400U +#define LRFDPBE32_EVT0_IRQ_SOFT10_M 0x00000400U +#define LRFDPBE32_EVT0_IRQ_SOFT10_S 10U +#define LRFDPBE32_EVT0_IRQ_SOFT10_ON 0x00000400U +#define LRFDPBE32_EVT0_IRQ_SOFT10_OFF 0x00000000U + +// Field: [9] SOFT9 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT9 0x00000200U +#define LRFDPBE32_EVT0_IRQ_SOFT9_M 0x00000200U +#define LRFDPBE32_EVT0_IRQ_SOFT9_S 9U +#define LRFDPBE32_EVT0_IRQ_SOFT9_ON 0x00000200U +#define LRFDPBE32_EVT0_IRQ_SOFT9_OFF 0x00000000U + +// Field: [8] SOFT8 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT8 0x00000100U +#define LRFDPBE32_EVT0_IRQ_SOFT8_M 0x00000100U +#define LRFDPBE32_EVT0_IRQ_SOFT8_S 8U +#define LRFDPBE32_EVT0_IRQ_SOFT8_ON 0x00000100U +#define LRFDPBE32_EVT0_IRQ_SOFT8_OFF 0x00000000U + +// Field: [7] SOFT7 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT7 0x00000080U +#define LRFDPBE32_EVT0_IRQ_SOFT7_M 0x00000080U +#define LRFDPBE32_EVT0_IRQ_SOFT7_S 7U +#define LRFDPBE32_EVT0_IRQ_SOFT7_ON 0x00000080U +#define LRFDPBE32_EVT0_IRQ_SOFT7_OFF 0x00000000U + +// Field: [6] SOFT6 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT6 0x00000040U +#define LRFDPBE32_EVT0_IRQ_SOFT6_M 0x00000040U +#define LRFDPBE32_EVT0_IRQ_SOFT6_S 6U +#define LRFDPBE32_EVT0_IRQ_SOFT6_ON 0x00000040U +#define LRFDPBE32_EVT0_IRQ_SOFT6_OFF 0x00000000U + +// Field: [5] SOFT5 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT5 0x00000020U +#define LRFDPBE32_EVT0_IRQ_SOFT5_M 0x00000020U +#define LRFDPBE32_EVT0_IRQ_SOFT5_S 5U +#define LRFDPBE32_EVT0_IRQ_SOFT5_ON 0x00000020U +#define LRFDPBE32_EVT0_IRQ_SOFT5_OFF 0x00000000U + +// Field: [4] SOFT4 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT4 0x00000010U +#define LRFDPBE32_EVT0_IRQ_SOFT4_M 0x00000010U +#define LRFDPBE32_EVT0_IRQ_SOFT4_S 4U +#define LRFDPBE32_EVT0_IRQ_SOFT4_ON 0x00000010U +#define LRFDPBE32_EVT0_IRQ_SOFT4_OFF 0x00000000U + +// Field: [3] SOFT3 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT3 0x00000008U +#define LRFDPBE32_EVT0_IRQ_SOFT3_M 0x00000008U +#define LRFDPBE32_EVT0_IRQ_SOFT3_S 3U +#define LRFDPBE32_EVT0_IRQ_SOFT3_ON 0x00000008U +#define LRFDPBE32_EVT0_IRQ_SOFT3_OFF 0x00000000U + +// Field: [2] SOFT2 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT2 0x00000004U +#define LRFDPBE32_EVT0_IRQ_SOFT2_M 0x00000004U +#define LRFDPBE32_EVT0_IRQ_SOFT2_S 2U +#define LRFDPBE32_EVT0_IRQ_SOFT2_ON 0x00000004U +#define LRFDPBE32_EVT0_IRQ_SOFT2_OFF 0x00000000U + +// Field: [1] SOFT1 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT1 0x00000002U +#define LRFDPBE32_EVT0_IRQ_SOFT1_M 0x00000002U +#define LRFDPBE32_EVT0_IRQ_SOFT1_S 1U +#define LRFDPBE32_EVT0_IRQ_SOFT1_ON 0x00000002U +#define LRFDPBE32_EVT0_IRQ_SOFT1_OFF 0x00000000U + +// Field: [0] SOFT0 +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_EVT0_IRQ_SOFT0 0x00000001U +#define LRFDPBE32_EVT0_IRQ_SOFT0_M 0x00000001U +#define LRFDPBE32_EVT0_IRQ_SOFT0_S 0U +#define LRFDPBE32_EVT0_IRQ_SOFT0_ON 0x00000001U +#define LRFDPBE32_EVT0_IRQ_SOFT0_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_EVTMSK0_EVT1 +// +//***************************************************************************** +// Field: [31] MDMFAEMPTY +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY 0x80000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_M 0x80000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_S 31U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_EN 0x80000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_DIS 0x00000000U + +// Field: [30] S2RSTOP +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP 0x40000000U +#define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_M 0x40000000U +#define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_S 30U +#define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_EN 0x40000000U +#define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_DIS 0x00000000U + +// Field: [29] FIFOERR +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_FIFOERR 0x20000000U +#define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_M 0x20000000U +#define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_S 29U +#define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_EN 0x20000000U +#define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_DIS 0x00000000U + +// Field: [28] MDMFAFULL +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL 0x10000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_M 0x10000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_S 28U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_EN 0x10000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_DIS 0x00000000U + +// Field: [27] SYSTCMP2 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2 0x08000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_M 0x08000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_S 27U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_EN 0x08000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_DIS 0x00000000U + +// Field: [26] SYSTCMP1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1 0x04000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_M 0x04000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_S 26U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_EN 0x04000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_DIS 0x00000000U + +// Field: [25] SYSTCMP0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0 0x02000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_M 0x02000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_S 25U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_EN 0x02000000U +#define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_DIS 0x00000000U + +// Field: [24] MDMMSGBOX +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX 0x01000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_M 0x01000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_S 24U +#define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_EN 0x01000000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_DIS 0x00000000U + +// Field: [23] RFEMSGBOX +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX 0x00800000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_M 0x00800000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_S 23U +#define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_EN 0x00800000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_DIS 0x00000000U + +// Field: [22] RFEDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_RFEDAT 0x00400000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_M 0x00400000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_S 22U +#define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_EN 0x00400000U +#define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_DIS 0x00000000U + +// Field: [21] RFECMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_RFECMD 0x00200000U +#define LRFDPBE32_EVTMSK0_EVT1_RFECMD_M 0x00200000U +#define LRFDPBE32_EVTMSK0_EVT1_RFECMD_S 21U +#define LRFDPBE32_EVTMSK0_EVT1_RFECMD_EN 0x00200000U +#define LRFDPBE32_EVTMSK0_EVT1_RFECMD_DIS 0x00000000U + +// Field: [20] MDMDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMDAT 0x00100000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_M 0x00100000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_S 20U +#define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_EN 0x00100000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_DIS 0x00000000U + +// Field: [19] MDMCMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMCMD 0x00080000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_M 0x00080000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_S 19U +#define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_EN 0x00080000U +#define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_DIS 0x00000000U + +// Field: [18] TIMER1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_TIMER1 0x00040000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER1_M 0x00040000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER1_S 18U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER1_EN 0x00040000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER1_DIS 0x00000000U + +// Field: [17] TIMER0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_TIMER0 0x00020000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER0_M 0x00020000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER0_S 17U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER0_EN 0x00020000U +#define LRFDPBE32_EVTMSK0_EVT1_TIMER0_DIS 0x00000000U + +// Field: [16] PBEAPI +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEAPI 0x00010000U +#define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_M 0x00010000U +#define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_S 16U +#define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_EN 0x00010000U +#define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_DIS 0x00000000U + +// Field: [12] TXRDBTHR +// +// ENUMs: +// MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR 0x00001000U +#define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_M 0x00001000U +#define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_S 12U +#define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_MET 0x00001000U +#define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_BELOW 0x00000000U + +// Field: [11] TXWRBTHR +// +// ENUMs: +// MET The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR 0x00000800U +#define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_M 0x00000800U +#define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_S 11U +#define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_MET 0x00000800U +#define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_BELOW 0x00000000U + +// Field: [10] RXRDBTHR +// +// ENUMs: +// MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// BELOW The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR 0x00000400U +#define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_M 0x00000400U +#define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_S 10U +#define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_MET 0x00000400U +#define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_BELOW 0x00000000U + +// Field: [9] RXWRBTHR +// +// ENUMs: +// MET The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// BELOW The RX FIFO contains less than the threshold +// RXFWBTHRS writable bytes. +#define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR 0x00000200U +#define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_M 0x00000200U +#define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_S 9U +#define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_MET 0x00000200U +#define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_BELOW 0x00000000U + +// Field: [8] MDMPROG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_MDMPROG 0x00000100U +#define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_M 0x00000100U +#define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_S 8U +#define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_ONE 0x00000100U +#define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_ZERO 0x00000000U + +// Field: [7] PBEGPI7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7 0x00000080U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_M 0x00000080U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_S 7U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_ONE 0x00000080U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_ZERO 0x00000000U + +// Field: [6] PBEGPI6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6 0x00000040U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_M 0x00000040U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_S 6U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_ONE 0x00000040U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_ZERO 0x00000000U + +// Field: [5] PBEGPI5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5 0x00000020U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_M 0x00000020U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_S 5U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_ONE 0x00000020U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_ZERO 0x00000000U + +// Field: [4] PBEGPI4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4 0x00000010U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_M 0x00000010U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_S 4U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_ONE 0x00000010U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_ZERO 0x00000000U + +// Field: [3] PBEGPI3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3 0x00000008U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_M 0x00000008U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_S 3U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_ONE 0x00000008U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_ZERO 0x00000000U + +// Field: [2] PBEGPI2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2 0x00000004U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_M 0x00000004U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_S 2U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_ONE 0x00000004U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_ZERO 0x00000000U + +// Field: [1] PBEGPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1 0x00000002U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_M 0x00000002U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_S 1U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_ONE 0x00000002U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_ZERO 0x00000000U + +// Field: [0] PBEGPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0 0x00000001U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_M 0x00000001U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_S 0U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_ONE 0x00000001U +#define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_EVTCLR0_EVTMSK1 +// +//***************************************************************************** +// Field: [31] MDMFAEMPTY +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY 0x80000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_M 0x80000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_S 31U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_CLEAR 0x80000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_RETAIN 0x00000000U + +// Field: [30] S2RSTOP +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP 0x40000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_M 0x40000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_S 30U +#define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_CLEAR 0x40000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_RETAIN 0x00000000U + +// Field: [29] FIFOERR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR 0x20000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_M 0x20000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_S 29U +#define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_CLEAR 0x20000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_RETAIN 0x00000000U + +// Field: [28] MDMFAFULL +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL 0x10000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_M 0x10000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_S 28U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_CLEAR 0x10000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_RETAIN 0x00000000U + +// Field: [27] SYSTCMP2 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2 0x08000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_M 0x08000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_S 27U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_CLEAR 0x08000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_RETAIN 0x00000000U + +// Field: [26] SYSTCMP1 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1 0x04000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_M 0x04000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_S 26U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_CLEAR 0x04000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_RETAIN 0x00000000U + +// Field: [25] SYSTCMP0 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0 0x02000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_M 0x02000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_S 25U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_CLEAR 0x02000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_RETAIN 0x00000000U + +// Field: [24] MDMMSGBOX +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX 0x01000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_M 0x01000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_S 24U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_CLEAR 0x01000000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_RETAIN 0x00000000U + +// Field: [23] RFEMSGBOX +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX 0x00800000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_M 0x00800000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_S 23U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_CLEAR 0x00800000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_RETAIN 0x00000000U + +// Field: [22] RFEDAT +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT 0x00400000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_M 0x00400000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_S 22U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_CLEAR 0x00400000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_RETAIN 0x00000000U + +// Field: [21] RFECMD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD 0x00200000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_M 0x00200000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_S 21U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_CLEAR 0x00200000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_RETAIN 0x00000000U + +// Field: [20] MDMDAT +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT 0x00100000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_M 0x00100000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_S 20U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_CLEAR 0x00100000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_RETAIN 0x00000000U + +// Field: [19] MDMCMD +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD 0x00080000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_M 0x00080000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_S 19U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_CLEAR 0x00080000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_RETAIN 0x00000000U + +// Field: [18] TIMER1 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1 0x00040000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_M 0x00040000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_S 18U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_CLEAR 0x00040000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_RETAIN 0x00000000U + +// Field: [17] TIMER0 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0 0x00020000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_M 0x00020000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_S 17U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_CLEAR 0x00020000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_RETAIN 0x00000000U + +// Field: [16] PBEAPI +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI 0x00010000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_M 0x00010000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_S 16U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_CLEAR 0x00010000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_RETAIN 0x00000000U + +// Field: [12] TXRDBTHR +// +// ENUMs: +// EN The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFRBTHRS readable bytes. +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR 0x00001000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_M 0x00001000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_S 12U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_EN 0x00001000U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_DIS 0x00000000U + +// Field: [11] TXWRBTHR +// +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR 0x00000800U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_M 0x00000800U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_S 11U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_EN 0x00000800U +#define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_DIS 0x00000000U + +// Field: [10] RXRDBTHR +// +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR 0x00000400U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_M 0x00000400U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_S 10U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_EN 0x00000400U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_DIS 0x00000000U + +// Field: [9] RXWRBTHR +// +// ENUMs: +// EN The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// DIS The TX FIFO contains less than the threshold +// TXFWBTHRS writable bytes. +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR 0x00000200U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_M 0x00000200U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_S 9U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_EN 0x00000200U +#define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_DIS 0x00000000U + +// Field: [8] MDMPROG +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG 0x00000100U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_M 0x00000100U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_S 8U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_EN 0x00000100U +#define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_DIS 0x00000000U + +// Field: [7] PBEGPI7 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7 0x00000080U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_M 0x00000080U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_S 7U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_EN 0x00000080U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_DIS 0x00000000U + +// Field: [6] PBEGPI6 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6 0x00000040U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_M 0x00000040U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_S 6U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_EN 0x00000040U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_DIS 0x00000000U + +// Field: [5] PBEGPI5 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5 0x00000020U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_M 0x00000020U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_S 5U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_EN 0x00000020U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_DIS 0x00000000U + +// Field: [4] PBEGPI4 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4 0x00000010U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_M 0x00000010U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_S 4U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_EN 0x00000010U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_DIS 0x00000000U + +// Field: [3] PBEGPI3 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3 0x00000008U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_M 0x00000008U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_S 3U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_EN 0x00000008U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_DIS 0x00000000U + +// Field: [2] PBEGPI2 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2 0x00000004U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_M 0x00000004U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_S 2U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_EN 0x00000004U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_DIS 0x00000000U + +// Field: [1] PBEGPI1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1 0x00000002U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_M 0x00000002U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_S 1U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_EN 0x00000002U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_DIS 0x00000000U + +// Field: [0] PBEGPI0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0 0x00000001U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_M 0x00000001U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_S 0U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_EN 0x00000001U +#define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_PDREQ_EVTCLR1 +// +//***************************************************************************** +// Field: [16] TOPSMPDREQ +// +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ 0x00010000U +#define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_M 0x00010000U +#define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_S 16U +#define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_ON 0x00010000U +#define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_OFF 0x00000000U + +// Field: [12] TXRDBTHR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR 0x00001000U +#define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_M 0x00001000U +#define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_S 12U +#define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_CLEAR 0x00001000U +#define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_RETAIN 0x00000000U + +// Field: [11] TXWRBTHR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR 0x00000800U +#define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_M 0x00000800U +#define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_S 11U +#define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_CLEAR 0x00000800U +#define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_RETAIN 0x00000000U + +// Field: [10] RXRDBTHR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR 0x00000400U +#define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_M 0x00000400U +#define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_S 10U +#define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_CLEAR 0x00000400U +#define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_RETAIN 0x00000000U + +// Field: [9] RXWRBTHR +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR 0x00000200U +#define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_M 0x00000200U +#define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_S 9U +#define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_CLEAR 0x00000200U +#define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_RETAIN 0x00000000U + +// Field: [8] MDMPROG +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG 0x00000100U +#define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_M 0x00000100U +#define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_S 8U +#define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_CLEAR 0x00000100U +#define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_RETAIN 0x00000000U + +// Field: [7] PBEGPI7 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7 0x00000080U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_M 0x00000080U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_S 7U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_CLEAR 0x00000080U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_RETAIN 0x00000000U + +// Field: [6] PBEGPI6 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6 0x00000040U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_M 0x00000040U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_S 6U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_CLEAR 0x00000040U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_RETAIN 0x00000000U + +// Field: [5] PBEGPI5 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5 0x00000020U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_M 0x00000020U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_S 5U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_CLEAR 0x00000020U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_RETAIN 0x00000000U + +// Field: [4] PBEGPI4 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4 0x00000010U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_M 0x00000010U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_S 4U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_CLEAR 0x00000010U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_RETAIN 0x00000000U + +// Field: [3] PBEGPI3 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3 0x00000008U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_M 0x00000008U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_S 3U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_CLEAR 0x00000008U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_RETAIN 0x00000000U + +// Field: [2] PBEGPI2 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2 0x00000004U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_M 0x00000004U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_S 2U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_CLEAR 0x00000004U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_RETAIN 0x00000000U + +// Field: [1] PBEGPI1 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1 0x00000002U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_M 0x00000002U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_S 1U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_CLEAR 0x00000002U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_RETAIN 0x00000000U + +// Field: [0] PBEGPI0 +// +// ENUMs: +// CLEAR The bit is 1 +// RETAIN The bit is 0 +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0 0x00000001U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_M 0x00000001U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_S 0U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_CLEAR 0x00000001U +#define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_RETAIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MCEDATOUT0_API +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MCEDATOUT0_API_VAL_W 16U +#define LRFDPBE32_MCEDATOUT0_API_VAL_M 0xFFFF0000U +#define LRFDPBE32_MCEDATOUT0_API_VAL_S 16U +#define LRFDPBE32_MCEDATOUT0_API_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_MCEDATOUT0_API_VAL_ALLZEROS 0x00000000U + +// Field: [4:0] PBECMD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MCEDATOUT0_API_PBECMD_W 5U +#define LRFDPBE32_MCEDATOUT0_API_PBECMD_M 0x0000001FU +#define LRFDPBE32_MCEDATOUT0_API_PBECMD_S 0U +#define LRFDPBE32_MCEDATOUT0_API_PBECMD_ALLONES 0x0000001FU +#define LRFDPBE32_MCEDATOUT0_API_PBECMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MCECMDOUT_MCEDATIN0 +// +//***************************************************************************** +// Field: [19:16] MCECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_W 4U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_M 0x000F0000U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_S 16U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_ALLONES 0x000F0000U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] MCEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_W 16U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_M 0x0000FFFFU +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_S 0U +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMAPI_MCECMDIN +// +//***************************************************************************** +// Field: [23:20] PROTOCOLID +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_W 4U +#define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_M 0x00F00000U +#define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_S 20U +#define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_ALLONES 0x00F00000U +#define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [19:16] MDMCMD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_W 4U +#define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_M 0x000F0000U +#define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_S 16U +#define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_ALLONES 0x000F0000U +#define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_ALLZEROS 0x00000000U + +// Field: [3:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMAPI_MCECMDIN_VAL_W 4U +#define LRFDPBE32_MDMAPI_MCECMDIN_VAL_M 0x0000000FU +#define LRFDPBE32_MDMAPI_MCECMDIN_VAL_S 0U +#define LRFDPBE32_MDMAPI_MCECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDPBE32_MDMAPI_MCECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FREQ_MDMMSGBOX +// +//***************************************************************************** +// Field: [31:16] OFFSET +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_W 16U +#define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_M 0xFFFF0000U +#define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_S 16U +#define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_ALLONES 0xFFFF0000U +#define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_ALLZEROS 0x00000000U + +// Field: [7:0] VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_W 8U +#define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_M 0x000000FFU +#define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_S 0U +#define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_ALLONES 0x000000FFU +#define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFEDATOUT0_MDMLQI +// +//***************************************************************************** +// Field: [31:16] RFEDATOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_W 16U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_M 0xFFFF0000U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_S 16U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_ALLZEROS 0x00000000U + +// Field: [7:0] MDMLQI_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_W 8U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_M 0x000000FFU +#define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_S 0U +#define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_ALLONES 0x000000FFU +#define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFECMDOUT_RFEDATIN0 +// +//***************************************************************************** +// Field: [19:16] RFECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_W 4U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_M 0x000F0000U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_S 16U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_ALLONES 0x000F0000U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] RFEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_W 16U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_M 0x0000FFFFU +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_S 0U +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFEAPI_RFECMDIN +// +//***************************************************************************** +// Field: [23:20] PROTOCOLID +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_W 4U +#define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_M 0x00F00000U +#define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_S 20U +#define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_ALLONES 0x00F00000U +#define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [19:16] RFECMD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_W 4U +#define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_M 0x000F0000U +#define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_S 16U +#define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_ALLONES 0x000F0000U +#define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_ALLZEROS 0x00000000U + +// Field: [3:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFEAPI_RFECMDIN_VAL_W 4U +#define LRFDPBE32_RFEAPI_RFECMDIN_VAL_M 0x0000000FU +#define LRFDPBE32_RFEAPI_RFECMDIN_VAL_S 0U +#define LRFDPBE32_RFEAPI_RFECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDPBE32_RFEAPI_RFECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFECMDPAR1_RFECMDPAR0 +// +//***************************************************************************** +// Field: [31:16] RFECMDPAR1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_W 16U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_M 0xFFFF0000U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_S 16U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] RFECMDPAR0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_W 16U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_M 0x0000FFFFU +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_S 0U +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFERSSI_RFEMSGBOX +// +//***************************************************************************** +// Field: [23:16] RFERSSI_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_W 8U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_M 0x00FF0000U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_S 16U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_ALLONES 0x00FF0000U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_ALLZEROS 0x00000000U + +// Field: [7:0] RFEMSGBOX_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_W 8U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_M 0x000000FFU +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_S 0U +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_ALLONES 0x000000FFU +#define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RFERFGAIN_RFERSSIMAX +// +//***************************************************************************** +// Field: [23:16] DBGAIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_W 8U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_M 0x00FF0000U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_S 16U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_ALLONES 0x00FF0000U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_ALLZEROS 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_W 8U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_M 0x000000FFU +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_S 0U +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_ALLONES 0x000000FFU +#define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMSYNCA +// +//***************************************************************************** +// Field: [31:0] SWA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMSYNCA_SWA_W 32U +#define LRFDPBE32_MDMSYNCA_SWA_M 0xFFFFFFFFU +#define LRFDPBE32_MDMSYNCA_SWA_S 0U +#define LRFDPBE32_MDMSYNCA_SWA_ALLONES 0x0000FFFFU +#define LRFDPBE32_MDMSYNCA_SWA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMSYNCB +// +//***************************************************************************** +// Field: [31:0] SWB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMSYNCB_SWB_W 32U +#define LRFDPBE32_MDMSYNCB_SWB_M 0xFFFFFFFFU +#define LRFDPBE32_MDMSYNCB_SWB_S 0U +#define LRFDPBE32_MDMSYNCB_SWB_ALLONES 0x0000FFFFU +#define LRFDPBE32_MDMSYNCB_SWB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMCMDPAR1_MDMCMDPAR0 +// +//***************************************************************************** +// Field: [31:16] MDMCMDPAR1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_W 16U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_M 0xFFFF0000U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_S 16U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] MDMCMDPAR0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_W 16U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_M 0x0000FFFFU +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_S 0U +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMCMDPAR2 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMCMDPAR2_VAL_W 16U +#define LRFDPBE32_MDMCMDPAR2_VAL_M 0x0000FFFFU +#define LRFDPBE32_MDMCMDPAR2_VAL_S 0U +#define LRFDPBE32_MDMCMDPAR2_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_MDMCMDPAR2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_POLY0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_POLY0_VAL_W 32U +#define LRFDPBE32_POLY0_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_POLY0_VAL_S 0U +#define LRFDPBE32_POLY0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_POLY0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_POLY1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_POLY1_VAL_W 32U +#define LRFDPBE32_POLY1_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_POLY1_VAL_S 0U +#define LRFDPBE32_POLY1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_POLY1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FCFG0_PHACFG +// +//***************************************************************************** +// Field: [23] TXIRQMET +// +// ENUMs: +// TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable +// bytes. +#define LRFDPBE32_FCFG0_PHACFG_TXIRQMET 0x00800000U +#define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_M 0x00800000U +#define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_S 23U +#define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_TXRDBTHR 0x00800000U +#define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_TXWRBTHR 0x00000000U + +// Field: [22] RXIRQMET +// +// ENUMs: +// RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable +// bytes. +#define LRFDPBE32_FCFG0_PHACFG_RXIRQMET 0x00400000U +#define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_M 0x00400000U +#define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_S 22U +#define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_RXWRBTHR 0x00400000U +#define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_RXRDBTHR 0x00000000U + +// Field: [21] TXACOM +// +// ENUMs: +// EN Always set TXSWP := TXWP +// DIS commit TXFIFO only on command 0x95 +#define LRFDPBE32_FCFG0_PHACFG_TXACOM 0x00200000U +#define LRFDPBE32_FCFG0_PHACFG_TXACOM_M 0x00200000U +#define LRFDPBE32_FCFG0_PHACFG_TXACOM_S 21U +#define LRFDPBE32_FCFG0_PHACFG_TXACOM_EN 0x00200000U +#define LRFDPBE32_FCFG0_PHACFG_TXACOM_DIS 0x00000000U + +// Field: [20] TXADEAL +// +// ENUMs: +// EN Always set TXFSRP := TXFRP. +// DIS Deallocate TXFIFO only on command 0x92 +#define LRFDPBE32_FCFG0_PHACFG_TXADEAL 0x00100000U +#define LRFDPBE32_FCFG0_PHACFG_TXADEAL_M 0x00100000U +#define LRFDPBE32_FCFG0_PHACFG_TXADEAL_S 20U +#define LRFDPBE32_FCFG0_PHACFG_TXADEAL_EN 0x00100000U +#define LRFDPBE32_FCFG0_PHACFG_TXADEAL_DIS 0x00000000U + +// Field: [17] RXACOM +// +// ENUMs: +// EN Always set RXFSWP := RXFWP +// DIS commit rxfifo only on command 0x85 +#define LRFDPBE32_FCFG0_PHACFG_RXACOM 0x00020000U +#define LRFDPBE32_FCFG0_PHACFG_RXACOM_M 0x00020000U +#define LRFDPBE32_FCFG0_PHACFG_RXACOM_S 17U +#define LRFDPBE32_FCFG0_PHACFG_RXACOM_EN 0x00020000U +#define LRFDPBE32_FCFG0_PHACFG_RXACOM_DIS 0x00000000U + +// Field: [16] RXADEAL +// +// ENUMs: +// EN Always set RXFSRP := RXFRP. +// DIS Deallocate RXFIFO only on command 0x82 +#define LRFDPBE32_FCFG0_PHACFG_RXADEAL 0x00010000U +#define LRFDPBE32_FCFG0_PHACFG_RXADEAL_M 0x00010000U +#define LRFDPBE32_FCFG0_PHACFG_RXADEAL_S 16U +#define LRFDPBE32_FCFG0_PHACFG_RXADEAL_EN 0x00010000U +#define LRFDPBE32_FCFG0_PHACFG_RXADEAL_DIS 0x00000000U + +// Field: [2:1] MODE1 +// +// ENUMs: +// PARAL LFSR0 and LFSR1 are operated in parallel +// CASC LFSR0 whitener is followed by LFSR1 CRC +// INDEP LFSR0 and LFSR1 are operated independently +#define LRFDPBE32_FCFG0_PHACFG_MODE1_W 2U +#define LRFDPBE32_FCFG0_PHACFG_MODE1_M 0x00000006U +#define LRFDPBE32_FCFG0_PHACFG_MODE1_S 1U +#define LRFDPBE32_FCFG0_PHACFG_MODE1_PARAL 0x00000004U +#define LRFDPBE32_FCFG0_PHACFG_MODE1_CASC 0x00000002U +#define LRFDPBE32_FCFG0_PHACFG_MODE1_INDEP 0x00000000U + +// Field: [0] MODE0 +// +// ENUMs: +// WHITE LFSR 0 is in whitening mode +// CRC LFSR 0 is in CRC mode +#define LRFDPBE32_FCFG0_PHACFG_MODE0 0x00000001U +#define LRFDPBE32_FCFG0_PHACFG_MODE0_M 0x00000001U +#define LRFDPBE32_FCFG0_PHACFG_MODE0_S 0U +#define LRFDPBE32_FCFG0_PHACFG_MODE0_WHITE 0x00000001U +#define LRFDPBE32_FCFG0_PHACFG_MODE0_CRC 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FCFG2_FCFG1 +// +//***************************************************************************** +// Field: [26:24] TXHSIZE +// +// ENUMs: +// WORD MCU receives IRQ when the TX FIFO contains more or +// equal amount of data than the configured +// threshold. +// HALFW MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +// BYTE MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_W 3U +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_M 0x07000000U +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_S 24U +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_WORD 0x02000000U +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_HALFW 0x01000000U +#define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_BYTE 0x00000000U + +// Field: [23:16] TXSIZE +// +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE32_FCFG2_FCFG1_TXSIZE_W 8U +#define LRFDPBE32_FCFG2_FCFG1_TXSIZE_M 0x00FF0000U +#define LRFDPBE32_FCFG2_FCFG1_TXSIZE_S 16U +#define LRFDPBE32_FCFG2_FCFG1_TXSIZE_ONES 0x00FF0000U +#define LRFDPBE32_FCFG2_FCFG1_TXSIZE_ZEROS 0x00000000U + +// Field: [8:0] TXSTRT +// +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE32_FCFG2_FCFG1_TXSTRT_W 9U +#define LRFDPBE32_FCFG2_FCFG1_TXSTRT_M 0x000001FFU +#define LRFDPBE32_FCFG2_FCFG1_TXSTRT_S 0U +#define LRFDPBE32_FCFG2_FCFG1_TXSTRT_ONES 0x000001FFU +#define LRFDPBE32_FCFG2_FCFG1_TXSTRT_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FCFG4_FCFG3 +// +//***************************************************************************** +// Field: [26:24] RXHSIZE +// +// ENUMs: +// WORD MCU receives IRQ when the TX FIFO contains more or +// equal amount of data than the configured +// threshold. +// HALFW MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +// BYTE MCU receives IRQ when the TX FIFO contains less +// amount of data than the configured threshold. +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_W 3U +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_M 0x07000000U +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_S 24U +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_WORD 0x02000000U +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_HALFW 0x01000000U +#define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_BYTE 0x00000000U + +// Field: [23:16] RXSIZE +// +// ENUMs: +// ONES Always set RXFSWP := RXFWP +// ZEROS commit rxfifo only on command 0x85 +#define LRFDPBE32_FCFG4_FCFG3_RXSIZE_W 8U +#define LRFDPBE32_FCFG4_FCFG3_RXSIZE_M 0x00FF0000U +#define LRFDPBE32_FCFG4_FCFG3_RXSIZE_S 16U +#define LRFDPBE32_FCFG4_FCFG3_RXSIZE_ONES 0x00FF0000U +#define LRFDPBE32_FCFG4_FCFG3_RXSIZE_ZEROS 0x00000000U + +// Field: [8:0] RXSTRT +// +// ENUMs: +// ONES All bits are 1s +// ZEROS All bits are zero +#define LRFDPBE32_FCFG4_FCFG3_RXSTRT_W 9U +#define LRFDPBE32_FCFG4_FCFG3_RXSTRT_M 0x000001FFU +#define LRFDPBE32_FCFG4_FCFG3_RXSTRT_S 0U +#define LRFDPBE32_FCFG4_FCFG3_RXSTRT_ONES 0x000001FFU +#define LRFDPBE32_FCFG4_FCFG3_RXSTRT_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFWBTHRS_FCFG5 +// +//***************************************************************************** +// Field: [25:16] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_W 10U +#define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_M 0x03FF0000U +#define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_S 16U +#define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_ALLONES 0x03FF0000U +#define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_ALLZEROS 0x00000000U + +// Field: [8:6] DMASREQ +// +// ENUMs: +// TXFIFOFREE The TX FIFO contains FCFG2_TXHSIZE or more +// writable bytes. +// TXFIFOMD The TX FIFO contains FCFG2_TXHSIZE or more +// readable bytes. +// RXFIFOFREE The RX FIFO contains FCFG4_RXHSIZE or more +// writable bytes. +// RXFIFOMD The RX FIFO contains FCFG4_RXHSIZE or more +// readable bytes. +// NONE No triggers generated +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_W 3U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_M 0x000001C0U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_S 6U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_TXFIFOFREE 0x00000100U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_TXFIFOMD 0x000000C0U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_RXFIFOFREE 0x00000080U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_RXFIFOMD 0x00000040U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_NONE 0x00000000U + +// Field: [4:0] DMAREQ +// +// ENUMs: +// TXFIFO_COMMIT TXFIFO is committed +// TXFIFO_DISCARD TXFIFO is discarded +// TXFIFO_RETRY TXFIFO is retried +// TXFIFO_DEALLOC TXFIFO is deallocated +// TXFIFO_RESET TXFIFO is reset +// TXWRBTHR_MET The TX FIFO contains TXFWBTHRS or more writable +// bytes. +// TXRDBTHR_MET The TX FIFO contains TXFRBTHRS or more readable +// bytes. +// RXFIFO_COMMIT RXFIFO is committed +// RXFIFO_DISCARD RXFIFO is discarded +// RXFIFO_RETRY RXFIFO is retried +// RXFIFO_DEALLOC RXFIFO is deallocated +// RXFIFO_RESET RXFIFO is reset +// RXWRBTHR_MET The RX FIFO contains RXFWBTHRS or more writable +// bytes. +// RXRDBTHR_MET The RX FIFO contains RXFRBTHRS or more readable +// bytes. +// NONE No triggers generated +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_W 5U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_M 0x0000001FU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_S 0U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_COMMIT 0x0000000FU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_DISCARD 0x0000000EU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_RETRY 0x0000000DU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_DEALLOC 0x0000000CU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_RESET 0x0000000BU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXWRBTHR_MET 0x0000000AU +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXRDBTHR_MET 0x00000009U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_COMMIT 0x00000007U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_DISCARD 0x00000006U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_RETRY 0x00000005U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_DEALLOC 0x00000004U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_RESET 0x00000003U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXWRBTHR_MET 0x00000002U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXRDBTHR_MET 0x00000001U +#define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_NONE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFWBTHRS_RXFRBTHRS +// +//***************************************************************************** +// Field: [25:16] TXFWBTHRS_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_W 10U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_M 0x03FF0000U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_S 16U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_ALLONES 0x03FF0000U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_ALLZEROS 0x00000000U + +// Field: [9:0] RXFRBTHRS_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_W 10U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_S 0U +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TIMCTL_TXFRBTHRS +// +//***************************************************************************** +// Field: [31:27] CPTSRC1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_W 5U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_M 0xF8000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_S 27U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_ALLONES 0xF8000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_ALLZEROS 0x00000000U + +// Field: [26] ENCPT1 +// +// ENUMs: +// ON Enable capture mode for counter +// OFF Disable capture mode for counter +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1 0x04000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_M 0x04000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_S 26U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_ON 0x04000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_OFF 0x00000000U + +// Field: [25] SRC1 +// +// ENUMs: +// PRE1 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1 0x02000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_M 0x02000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_S 25U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_PRE1 0x02000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_CLK 0x00000000U + +// Field: [24] EN1 +// +// ENUMs: +// ON Will enable timer +// OFF Will disable timer and clear internal timer value +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1 0x01000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_M 0x01000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_S 24U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_ON 0x01000000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_OFF 0x00000000U + +// Field: [23:19] CPTSRC0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_W 5U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_M 0x00F80000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_S 19U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_ALLONES 0x00F80000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_ALLZEROS 0x00000000U + +// Field: [18] ENCPT0 +// +// ENUMs: +// ON Enable capture mode for counter +// OFF Disable capture mode for counter +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0 0x00040000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_M 0x00040000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_S 18U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_ON 0x00040000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_OFF 0x00000000U + +// Field: [17] SRC0 +// +// ENUMs: +// PRE0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0 0x00020000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_M 0x00020000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_S 17U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_PRE0 0x00020000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_CLK 0x00000000U + +// Field: [16] EN0 +// +// ENUMs: +// ON Will enable timer +// OFF Will disable timer and clear internal timer value +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0 0x00010000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_M 0x00010000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_S 16U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_ON 0x00010000U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_OFF 0x00000000U + +// Field: [9:0] BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_W 10U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_M 0x000003FFU +#define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_S 0U +#define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_ALLONES 0x000003FFU +#define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TIMPER0_TIMPRE +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMPER0_TIMPRE_VAL_W 16U +#define LRFDPBE32_TIMPER0_TIMPRE_VAL_M 0xFFFF0000U +#define LRFDPBE32_TIMPER0_TIMPRE_VAL_S 16U +#define LRFDPBE32_TIMPER0_TIMPRE_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_TIMPER0_TIMPRE_VAL_ALLZEROS 0x00000000U + +// Field: [13:8] PRE1 +// +// ENUMs: +// DIV64 DIV64 mode +// NO_DIV No prescaling +#define LRFDPBE32_TIMPER0_TIMPRE_PRE1_W 6U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE1_M 0x00003F00U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE1_S 8U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE1_DIV64 0x00003F00U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE1_NO_DIV 0x00000000U + +// Field: [5:0] PRE0 +// +// ENUMs: +// DIV64 DIV64 mode +// NO_DIV No prescaling +#define LRFDPBE32_TIMPER0_TIMPRE_PRE0_W 6U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE0_M 0x0000003FU +#define LRFDPBE32_TIMPER0_TIMPRE_PRE0_S 0U +#define LRFDPBE32_TIMPER0_TIMPRE_PRE0_DIV64 0x0000003FU +#define LRFDPBE32_TIMPER0_TIMPRE_PRE0_NO_DIV 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TIMCAPT0_TIMPER1 +// +//***************************************************************************** +// Field: [31:16] VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_W 16U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_M 0xFFFF0000U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_S 16U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_ALLONES 0xFFFF0000U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_W 16U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_M 0x0000FFFFU +#define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_S 0U +#define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TIMCAPT1 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TIMCAPT1_VALUE_W 16U +#define LRFDPBE32_TIMCAPT1_VALUE_M 0x0000FFFFU +#define LRFDPBE32_TIMCAPT1_VALUE_S 0U +#define LRFDPBE32_TIMCAPT1_VALUE_ALLONES 0x0000FFFFU +#define LRFDPBE32_TIMCAPT1_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TRCSTAT_TRCCTL +// +//***************************************************************************** +// Field: [16] BUSY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_TRCSTAT_TRCCTL_BUSY 0x00010000U +#define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_M 0x00010000U +#define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_S 16U +#define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_ONE 0x00010000U +#define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_ZERO 0x00000000U + +// Field: [0] SEND +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_TRCSTAT_TRCCTL_SEND 0x00000001U +#define LRFDPBE32_TRCSTAT_TRCCTL_SEND_M 0x00000001U +#define LRFDPBE32_TRCSTAT_TRCCTL_SEND_S 0U +#define LRFDPBE32_TRCSTAT_TRCCTL_SEND_ONE 0x00000001U +#define LRFDPBE32_TRCSTAT_TRCCTL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TRCPAR0_TRCCMD +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TRCPAR0_TRCCMD_VAL_W 16U +#define LRFDPBE32_TRCPAR0_TRCCMD_VAL_M 0xFFFF0000U +#define LRFDPBE32_TRCPAR0_TRCCMD_VAL_S 16U +#define LRFDPBE32_TRCPAR0_TRCCMD_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_TRCPAR0_TRCCMD_VAL_ALLZEROS 0x00000000U + +// Field: [9:8] PARCNT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_W 2U +#define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_M 0x00000300U +#define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_S 8U +#define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_W 8U +#define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_M 0x000000FFU +#define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_S 0U +#define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_GPOCTRL_TRCPAR1 +// +//***************************************************************************** +// Field: [23] GPO7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7 0x00800000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_M 0x00800000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_S 23U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_ONE 0x00800000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_ZERO 0x00000000U + +// Field: [22] GPO6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6 0x00400000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_M 0x00400000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_S 22U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_ONE 0x00400000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_ZERO 0x00000000U + +// Field: [21] GPO5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5 0x00200000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_M 0x00200000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_S 21U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_ONE 0x00200000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_ZERO 0x00000000U + +// Field: [20] GPO4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4 0x00100000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_M 0x00100000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_S 20U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_ONE 0x00100000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_ZERO 0x00000000U + +// Field: [19] GPO3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3 0x00080000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_M 0x00080000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_S 19U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_ONE 0x00080000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_ZERO 0x00000000U + +// Field: [18] GPO2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2 0x00040000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_M 0x00040000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_S 18U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_ONE 0x00040000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_ZERO 0x00000000U + +// Field: [17] GPO1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1 0x00020000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_M 0x00020000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_S 17U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_ONE 0x00020000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_ZERO 0x00000000U + +// Field: [16] GPO0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0 0x00010000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_M 0x00010000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_S 16U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_ONE 0x00010000U +#define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_ZERO 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_W 16U +#define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_M 0x0000FFFFU +#define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_S 0U +#define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMFRD_MDMFWR +// +//***************************************************************************** +// Field: [31:16] PAYLOADOUT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_W 16U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_M 0xFFFF0000U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_S 16U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_ALLONES 0xFFFF0000U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_ALLZEROS 0x00000000U + +// Field: [15:0] PAYLOADIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_W 16U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_M 0x0000FFFFU +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_S 0U +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_ALLONES 0x0000FFFFU +#define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMFRDCTL_MDMFWRCTL +// +//***************************************************************************** +// Field: [19:16] WORDSZRD +// +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_W 4U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_M 0x000F0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_S 16U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS16 0x000F0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS15 0x000E0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS14 0x000D0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS13 0x000C0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS12 0x000B0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS11 0x000A0000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS10 0x00090000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS9 0x00080000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS8 0x00070000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS7 0x00060000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS6 0x00050000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS5 0x00040000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS4 0x00030000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS3 0x00020000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS2 0x00010000U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS1 0x00000000U + +// Field: [3:0] WORDSZWR +// +// ENUMs: +// BITS16 16 bits +// BITS15 15 bits +// BITS14 14 bits +// BITS13 13 bits +// BITS12 12 bits +// BITS11 11 bits +// BITS10 10 bits +// BITS9 9 bits +// BITS8 8 bits +// BITS7 7 bits +// BITS6 6 bits +// BITS5 5 bits +// BITS4 4 bits +// BITS3 3 bits +// BITS2 2 bits +// BITS1 1 bit +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_W 4U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_M 0x0000000FU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_S 0U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS16 0x0000000FU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS15 0x0000000EU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS14 0x0000000DU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS13 0x0000000CU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS12 0x0000000BU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS11 0x0000000AU +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS10 0x00000009U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS9 0x00000008U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS8 0x00000007U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS7 0x00000006U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS6 0x00000005U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS5 0x00000004U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS4 0x00000003U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS3 0x00000002U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS2 0x00000001U +#define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_MDMFSTA_MDMFCFG +// +//***************************************************************************** +// Field: [21] OVFL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL 0x00200000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_M 0x00200000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_S 21U +#define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_ONE 0x00200000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_ZERO 0x00000000U + +// Field: [20] ALMOSTFULL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL 0x00100000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_M 0x00100000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_S 20U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_ONE 0x00100000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_ZERO 0x00000000U + +// Field: [19] ALMOSTEMPTY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY 0x00080000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_M 0x00080000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_S 19U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_ONE 0x00080000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_ZERO 0x00000000U + +// Field: [18] UNFL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL 0x00040000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_M 0x00040000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_S 18U +#define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_ONE 0x00040000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_ZERO 0x00000000U + +// Field: [17] RXVALID +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID 0x00020000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_M 0x00020000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_S 17U +#define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_ONE 0x00020000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_ZERO 0x00000000U + +// Field: [16] TXREADY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY 0x00010000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_M 0x00010000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_S 16U +#define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_ONE 0x00010000U +#define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_ZERO 0x00000000U + +// Field: [15:8] AFULLTHR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_W 8U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_M 0x0000FF00U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_S 8U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_ALLONES 0x0000FF00U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_ALLZEROS 0x00000000U + +// Field: [7:0] AEMPTYTHR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_W 8U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_M 0x000000FFU +#define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_S 0U +#define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_ALLONES 0x000000FFU +#define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_PHASTA +// +//***************************************************************************** +// Field: [17:16] BUSY +// +// ENUMs: +// BUSY LFSR n sub-engine busy +// IDLE LFSR n sub-engine idle +#define LRFDPBE32_PHASTA_BUSY_W 2U +#define LRFDPBE32_PHASTA_BUSY_M 0x00030000U +#define LRFDPBE32_PHASTA_BUSY_S 16U +#define LRFDPBE32_PHASTA_BUSY_BUSY 0x00010000U +#define LRFDPBE32_PHASTA_BUSY_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR0_VAL_W 32U +#define LRFDPBE32_LFSR0_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_LFSR0_VAL_S 0U +#define LRFDPBE32_LFSR0_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_LFSR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR0BR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR0BR_VAL_W 32U +#define LRFDPBE32_LFSR0BR_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_LFSR0BR_VAL_S 0U +#define LRFDPBE32_LFSR0BR_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_LFSR0BR_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR1_VAL_W 32U +#define LRFDPBE32_LFSR1_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_LFSR1_VAL_S 0U +#define LRFDPBE32_LFSR1_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_LFSR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR1BR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR1BR_VAL_W 32U +#define LRFDPBE32_LFSR1BR_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_LFSR1BR_VAL_S 0U +#define LRFDPBE32_LFSR1BR_VAL_ALLONES 0x0000FFFFU +#define LRFDPBE32_LFSR1BR_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR0N_LFSR0INL +// +//***************************************************************************** +// Field: [19:16] SIZE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_W 4U +#define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_M 0x000F0000U +#define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_S 16U +#define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_ALLONES 0x000F0000U +#define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR0N_LFSR0INL_VAL_W 16U +#define LRFDPBE32_LFSR0N_LFSR0INL_VAL_M 0x0000FFFFU +#define LRFDPBE32_LFSR0N_LFSR0INL_VAL_S 0U +#define LRFDPBE32_LFSR0N_LFSR0INL_VAL_ALLONES 0x00000003U +#define LRFDPBE32_LFSR0N_LFSR0INL_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_PHAOUT0_LFSR0INM +// +//***************************************************************************** +// Field: [31:16] PHAOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_W 16U +#define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_M 0xFFFF0000U +#define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_S 16U +#define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_ALLONES 0xDCD70000U +#define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] LFSR0INM_VAL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_W 16U +#define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_M 0x0000FFFFU +#define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_S 0U +#define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_ONE 0x00000001U +#define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_LFSR1N_LFSR1INL +// +//***************************************************************************** +// Field: [19:16] SIZE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_W 4U +#define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_M 0x000F0000U +#define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_S 16U +#define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_ALLONES 0x000F0000U +#define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_LFSR1N_LFSR1INL_VAL_W 16U +#define LRFDPBE32_LFSR1N_LFSR1INL_VAL_M 0x0000FFFFU +#define LRFDPBE32_LFSR1N_LFSR1INL_VAL_S 0U +#define LRFDPBE32_LFSR1N_LFSR1INL_VAL_ALLONES 0x00000003U +#define LRFDPBE32_LFSR1N_LFSR1INL_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_PHAOUT0BR_LFSR1INM +// +//***************************************************************************** +// Field: [31:16] PHAOUT0BR_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_W 16U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_M 0xFFFF0000U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_S 16U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_ALLONES 0xFFFF0000U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] LFSR1INM_VAL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_W 16U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_M 0x0000FFFFU +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_S 0U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_ONE 0x00000001U +#define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_SYSTIM0 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_SYSTIM0_VAL_W 32U +#define LRFDPBE32_SYSTIM0_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_SYSTIM0_VAL_S 0U +#define LRFDPBE32_SYSTIM0_VAL_ONE 0x00000001U +#define LRFDPBE32_SYSTIM0_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_SYSTIM1 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_SYSTIM1_VAL_W 32U +#define LRFDPBE32_SYSTIM1_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_SYSTIM1_VAL_S 0U +#define LRFDPBE32_SYSTIM1_VAL_ONE 0x00000001U +#define LRFDPBE32_SYSTIM1_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_SYSTIM2 +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_SYSTIM2_VAL_W 32U +#define LRFDPBE32_SYSTIM2_VAL_M 0xFFFFFFFFU +#define LRFDPBE32_SYSTIM2_VAL_S 0U +#define LRFDPBE32_SYSTIM2_VAL_ONE 0x00000001U +#define LRFDPBE32_SYSTIM2_VAL_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_GPI +// +//***************************************************************************** +// Field: [7] GPI7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI7 0x00000080U +#define LRFDPBE32_GPI_GPI7_M 0x00000080U +#define LRFDPBE32_GPI_GPI7_S 7U +#define LRFDPBE32_GPI_GPI7_ONE 0x00000080U +#define LRFDPBE32_GPI_GPI7_ZERO 0x00000000U + +// Field: [6] GPI6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI6 0x00000040U +#define LRFDPBE32_GPI_GPI6_M 0x00000040U +#define LRFDPBE32_GPI_GPI6_S 6U +#define LRFDPBE32_GPI_GPI6_ONE 0x00000040U +#define LRFDPBE32_GPI_GPI6_ZERO 0x00000000U + +// Field: [5] GPI5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI5 0x00000020U +#define LRFDPBE32_GPI_GPI5_M 0x00000020U +#define LRFDPBE32_GPI_GPI5_S 5U +#define LRFDPBE32_GPI_GPI5_ONE 0x00000020U +#define LRFDPBE32_GPI_GPI5_ZERO 0x00000000U + +// Field: [4] GPI4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI4 0x00000010U +#define LRFDPBE32_GPI_GPI4_M 0x00000010U +#define LRFDPBE32_GPI_GPI4_S 4U +#define LRFDPBE32_GPI_GPI4_ONE 0x00000010U +#define LRFDPBE32_GPI_GPI4_ZERO 0x00000000U + +// Field: [3] GPI3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI3 0x00000008U +#define LRFDPBE32_GPI_GPI3_M 0x00000008U +#define LRFDPBE32_GPI_GPI3_S 3U +#define LRFDPBE32_GPI_GPI3_ONE 0x00000008U +#define LRFDPBE32_GPI_GPI3_ZERO 0x00000000U + +// Field: [2] GPI2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI2 0x00000004U +#define LRFDPBE32_GPI_GPI2_M 0x00000004U +#define LRFDPBE32_GPI_GPI2_S 2U +#define LRFDPBE32_GPI_GPI2_ONE 0x00000004U +#define LRFDPBE32_GPI_GPI2_ZERO 0x00000000U + +// Field: [1] GPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI1 0x00000002U +#define LRFDPBE32_GPI_GPI1_M 0x00000002U +#define LRFDPBE32_GPI_GPI1_S 1U +#define LRFDPBE32_GPI_GPI1_ONE 0x00000002U +#define LRFDPBE32_GPI_GPI1_ZERO 0x00000000U + +// Field: [0] GPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDPBE32_GPI_GPI0 0x00000001U +#define LRFDPBE32_GPI_GPI0_M 0x00000001U +#define LRFDPBE32_GPI_GPI0_S 0U +#define LRFDPBE32_GPI_GPI0_ONE 0x00000001U +#define LRFDPBE32_GPI_GPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_FSTAT_FCMD +// +//***************************************************************************** +// Field: [27] TXUNFL +// +// ENUMs: +// TRUE Underflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE32_FSTAT_FCMD_TXUNFL 0x08000000U +#define LRFDPBE32_FSTAT_FCMD_TXUNFL_M 0x08000000U +#define LRFDPBE32_FSTAT_FCMD_TXUNFL_S 27U +#define LRFDPBE32_FSTAT_FCMD_TXUNFL_TRUE 0x08000000U +#define LRFDPBE32_FSTAT_FCMD_TXUNFL_FALSE 0x00000000U + +// Field: [26] TXOVFL +// +// ENUMs: +// TRUE Overflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE32_FSTAT_FCMD_TXOVFL 0x04000000U +#define LRFDPBE32_FSTAT_FCMD_TXOVFL_M 0x04000000U +#define LRFDPBE32_FSTAT_FCMD_TXOVFL_S 26U +#define LRFDPBE32_FSTAT_FCMD_TXOVFL_TRUE 0x04000000U +#define LRFDPBE32_FSTAT_FCMD_TXOVFL_FALSE 0x00000000U + +// Field: [25] TXEMPTY +// +// ENUMs: +// TRUE TXFIFO is empty +// FALSE TXFIFO is not empty +#define LRFDPBE32_FSTAT_FCMD_TXEMPTY 0x02000000U +#define LRFDPBE32_FSTAT_FCMD_TXEMPTY_M 0x02000000U +#define LRFDPBE32_FSTAT_FCMD_TXEMPTY_S 25U +#define LRFDPBE32_FSTAT_FCMD_TXEMPTY_TRUE 0x02000000U +#define LRFDPBE32_FSTAT_FCMD_TXEMPTY_FALSE 0x00000000U + +// Field: [24] TXFULL +// +// ENUMs: +// TRUE TXFIFO is full +// FALSE TXFIFO is not full +#define LRFDPBE32_FSTAT_FCMD_TXFULL 0x01000000U +#define LRFDPBE32_FSTAT_FCMD_TXFULL_M 0x01000000U +#define LRFDPBE32_FSTAT_FCMD_TXFULL_S 24U +#define LRFDPBE32_FSTAT_FCMD_TXFULL_TRUE 0x01000000U +#define LRFDPBE32_FSTAT_FCMD_TXFULL_FALSE 0x00000000U + +// Field: [19] RXUNFL +// +// ENUMs: +// TRUE Underflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE32_FSTAT_FCMD_RXUNFL 0x00080000U +#define LRFDPBE32_FSTAT_FCMD_RXUNFL_M 0x00080000U +#define LRFDPBE32_FSTAT_FCMD_RXUNFL_S 19U +#define LRFDPBE32_FSTAT_FCMD_RXUNFL_TRUE 0x00080000U +#define LRFDPBE32_FSTAT_FCMD_RXUNFL_FALSE 0x00000000U + +// Field: [18] RXOVFL +// +// ENUMs: +// TRUE Overflow has occurred +// FALSE Normal operation ensues +#define LRFDPBE32_FSTAT_FCMD_RXOVFL 0x00040000U +#define LRFDPBE32_FSTAT_FCMD_RXOVFL_M 0x00040000U +#define LRFDPBE32_FSTAT_FCMD_RXOVFL_S 18U +#define LRFDPBE32_FSTAT_FCMD_RXOVFL_TRUE 0x00040000U +#define LRFDPBE32_FSTAT_FCMD_RXOVFL_FALSE 0x00000000U + +// Field: [17] RXEMPTY +// +// ENUMs: +// TRUE RXFIFO is empty +// FALSE RXFIFO is not empty +#define LRFDPBE32_FSTAT_FCMD_RXEMPTY 0x00020000U +#define LRFDPBE32_FSTAT_FCMD_RXEMPTY_M 0x00020000U +#define LRFDPBE32_FSTAT_FCMD_RXEMPTY_S 17U +#define LRFDPBE32_FSTAT_FCMD_RXEMPTY_TRUE 0x00020000U +#define LRFDPBE32_FSTAT_FCMD_RXEMPTY_FALSE 0x00000000U + +// Field: [16] RXFULL +// +// ENUMs: +// TRUE RXFIFO is full +// FALSE RXFIFO is not full +#define LRFDPBE32_FSTAT_FCMD_RXFULL 0x00010000U +#define LRFDPBE32_FSTAT_FCMD_RXFULL_M 0x00010000U +#define LRFDPBE32_FSTAT_FCMD_RXFULL_S 16U +#define LRFDPBE32_FSTAT_FCMD_RXFULL_TRUE 0x00010000U +#define LRFDPBE32_FSTAT_FCMD_RXFULL_FALSE 0x00000000U + +// Field: [7:0] DATA +// +// ENUMs: +// FIFO_COMMIT Commit both FIFOs +// FIFO_DISCARD Discard both FIFOs +// FIFO_RETRY Retry both FIFOs +// FIFO_DEALLOC Deallocate both FIFOS +// FIFO_RESET Reset (empty) both FIFOs +// RXFIFO_RETRY Retry rxfifo. This sets RXFRP := RXFSRP +// RXFIFO_DISCARD Discard rxfifo. This sets RXFWP := RXFSWP +// RXFIFO_COMMIT Commit rxfifo. This sets RXFSWP := RXFWP +// TXFIFO_RESET Reset (empty) txfifo. Set TXF* := 0 +// TXFIFO_DEALLOC Deallocate txfifo. This sets TXFSRP := TXFRP. +// TXFIFO_RETRY Retry txfifo. This sets TXFRP := TXFSRP +// TXFIFO_DISCARD Discard txfifo. This sets TXFWP := TXFSWP +// TXFIFO_COMMIT Commit txfifo. This sets TXFSWP := TXFWP +// RXFIFO_DEALLOC Deallocate rxfifo. This sets RXFSRP := RXFRP. +// RXFIFO_RESET Reset (empty) rxfifo. Set RXF* := 0 +#define LRFDPBE32_FSTAT_FCMD_DATA_W 8U +#define LRFDPBE32_FSTAT_FCMD_DATA_M 0x000000FFU +#define LRFDPBE32_FSTAT_FCMD_DATA_S 0U +#define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_COMMIT 0x0000000FU +#define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_DISCARD 0x0000000EU +#define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_RETRY 0x0000000DU +#define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_DEALLOC 0x0000000CU +#define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_RESET 0x0000000BU +#define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_RETRY 0x0000000AU +#define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_DISCARD 0x00000009U +#define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_COMMIT 0x00000008U +#define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_RESET 0x00000007U +#define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_DEALLOC 0x00000006U +#define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_RETRY 0x00000005U +#define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_DISCARD 0x00000004U +#define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_COMMIT 0x00000003U +#define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_DEALLOC 0x00000002U +#define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_RESET 0x00000001U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFRP_RXFWP +// +//***************************************************************************** +// Field: [25:16] RXFRP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_W 10U +#define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_M 0x03FF0000U +#define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_S 16U +#define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_ALLONES 0x03FF0000U +#define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_ALLZEROS 0x00000000U + +// Field: [9:0] RXFWP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_W 10U +#define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_M 0x000003FFU +#define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_S 0U +#define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFSRP_RXFSWP +// +//***************************************************************************** +// Field: [25:16] RXFSRP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_W 10U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_M 0x03FF0000U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_S 16U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_ALLONES 0x03FF0000U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_ALLZEROS 0x00000000U + +// Field: [9:0] RXFSWP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_W 10U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_M 0x000003FFU +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_S 0U +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFRP_TXFWP +// +//***************************************************************************** +// Field: [25:16] TXFRP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_W 10U +#define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_M 0x03FF0000U +#define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_S 16U +#define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_ALLONES 0x03FF0000U +#define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_ALLZEROS 0x00000000U + +// Field: [9:0] TXFWP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_W 10U +#define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_M 0x000003FFU +#define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_S 0U +#define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFSRP_TXFSWP +// +//***************************************************************************** +// Field: [25:16] TXFSRP_PTR +// +// ENUMs: +// ALLONES_2 All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_W 10U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_M 0x03FF0000U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_S 16U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_ALLONES_2 0x03FF0000U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_ALLZEROS 0x00000000U + +// Field: [9:0] TXFSWP_PTR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_W 10U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_M 0x000003FFU +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_S 0U +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_ALLONES 0x000003FFU +#define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFREADABLE_RXFWRITABLE +// +//***************************************************************************** +// Field: [25:16] RXFREADABLE_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_W 10U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_M 0x03FF0000U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_S 16U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_ALLONES \ + 0x03FF0000U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_ALLZEROS \ + 0x00000000U + +// Field: [9:0] RXFWRITABLE_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_W 10U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_M 0x000003FFU +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_S 0U +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_ALLONES \ + 0x000003FFU +#define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_ALLZEROS \ + 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFREADABLE_TXFWRITABLE +// +//***************************************************************************** +// Field: [25:16] TXFREADABLE_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_W 10U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_M 0x03FF0000U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_S 16U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_ALLONES \ + 0x03FF0000U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_ALLZEROS \ + 0x00000000U + +// Field: [9:0] TXFWRITABLE_BYTES +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_W 10U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_M 0x000003FFU +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_S 0U +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_ALLONES \ + 0x000003FFU +#define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_ALLZEROS \ + 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFBWR_RXFBRD +// +//***************************************************************************** +// Field: [23:16] RXFBWR_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_W 8U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_M 0x00FF0000U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_S 16U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_ALLONES 0x00FF0000U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_ALLZEROS 0x00000000U + +// Field: [7:0] RXFBRD_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_W 8U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_M 0x000000FFU +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_S 0U +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_ALLONES 0x000000FFU +#define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFBWR_TXFBRD +// +//***************************************************************************** +// Field: [23:16] TXFBWR_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_W 8U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_M 0x00FF0000U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_S 16U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_ALLONES 0x00FF0000U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_ALLZEROS 0x00000000U + +// Field: [7:0] TXFBRD_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_W 8U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_M 0x000000FFU +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_S 0U +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_ALLONES 0x000000FFU +#define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_RXFHWR_RXFHRD +// +//***************************************************************************** +// Field: [31:16] RXFHWR_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_W 16U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_M 0xFFFF0000U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_S 16U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_ALLONES 0xFFFF0000U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_ALLZEROS 0x00000000U + +// Field: [15:0] RXFHRD_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_W 16U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_M 0x0000FFFFU +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_S 0U +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDPBE32_O_TXFHWR_TXFHRD +// +//***************************************************************************** +// Field: [31:16] TXFHWR_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_W 16U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_M 0xFFFF0000U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_S 16U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_ALLONES 0xFFFF0000U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_ALLZEROS 0x00000000U + +// Field: [15:0] TXFHRD_DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_W 16U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_M 0x0000FFFFU +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_S 0U +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_ALLONES 0x0000FFFFU +#define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_ALLZEROS 0x00000000U + + +#endif // __LRFDPBE32__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe.h new file mode 100644 index 00000000..bfc4dd0d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe.h @@ -0,0 +1,8223 @@ +/****************************************************************************** +* Filename: hw_lrfdrfe_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDRFE_H__ +#define __HW_LRFDRFE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDRFE component +// +//***************************************************************************** +// RF Engine Enable Register +#define LRFDRFE_O_ENABLE 0x00000000U + +// RFE Program Source Select Register +#define LRFDRFE_O_FWSRC 0x00000004U + +// RF Engine Initialization Register +#define LRFDRFE_O_INIT 0x00000008U + +// RF Engine Power-down Register +#define LRFDRFE_O_PDREQ 0x0000000CU + +// RFE Event Flag Register 0 +#define LRFDRFE_O_EVT0 0x00000010U + +// RFE Event Flag Register 1 +#define LRFDRFE_O_EVT1 0x00000014U + +// RFE Event Mask Register 0 +#define LRFDRFE_O_EVTMSK0 0x00000018U + +// RFE Event Mask Register 1 +#define LRFDRFE_O_EVTMSK1 0x0000001CU + +// RFE Event Clear Register 0 +#define LRFDRFE_O_EVTCLR0 0x00000020U + +// RFE Event Clear Register 1 +#define LRFDRFE_O_EVTCLR1 0x00000024U + +// Status of the HFXT +#define LRFDRFE_O_HFXTSTAT 0x00000028U + +// RF state indication +#define LRFDRFE_O_RFSTATE 0x00000030U + +// RFE API Command Register +#define LRFDRFE_O_API 0x00000048U + +// RFE Command Parameter 0 +#define LRFDRFE_O_CMDPAR0 0x0000004CU + +// RFE Command Parameter 1 +#define LRFDRFE_O_CMDPAR1 0x00000050U + +// RFE Command Status and Message Box Register +#define LRFDRFE_O_MSGBOX 0x00000054U + +// RFE-to-MCE Send Data Register +#define LRFDRFE_O_MCEDATOUT0 0x00000058U + +// MCE-to-RFE Receive Data Register +#define LRFDRFE_O_MCEDATIN0 0x0000005CU + +// RFE-to-MCE Send Command Register +#define LRFDRFE_O_MCECMDOUT 0x00000060U + +// MCE-to-RFE Receive Command Register +#define LRFDRFE_O_MCECMDIN 0x00000064U + +// RFE-to-PBE Send Data Register +#define LRFDRFE_O_PBEDATOUT0 0x00000068U + +// PBE-to-RFE Receive Data Register +#define LRFDRFE_O_PBEDATIN0 0x0000006CU + +// RFE-to-PBE Send Command Register +#define LRFDRFE_O_PBECMDOUT 0x00000070U + +// PBE-to-RFE Receive Command Register +#define LRFDRFE_O_PBECMDIN 0x00000074U + +// RFE FW Strobe Register +#define LRFDRFE_O_STRB 0x00000078U + +// Controls automatic comparison of magnitude with threshold +#define LRFDRFE_O_MAGNTHRCFG 0x00000080U + +// Threshold to compare the magnacc amplitude with, which accumulator is used +// in the compare is controled by MAGNTHRCFG +#define LRFDRFE_O_MAGNTHR 0x00000084U + +// RSSI Offset Adjustment Register +#define LRFDRFE_O_RSSIOFFSET 0x00000088U + +// Gain Control Register +#define LRFDRFE_O_GAINCTL 0x0000008CU + +// Magnitude estimator 0 control register +#define LRFDRFE_O_MAGNCTL0 0x00000090U + +// Magnitude estimator 1 control register +#define LRFDRFE_O_MAGNCTL1 0x00000094U + +// Spare Value +#define LRFDRFE_O_SPARE0 0x00000098U + +// Spare Value +#define LRFDRFE_O_SPARE1 0x0000009CU + +// Spare Value +#define LRFDRFE_O_SPARE2 0x000000A0U + +// Spare Value +#define LRFDRFE_O_SPARE3 0x000000A4U + +// Spare Value +#define LRFDRFE_O_SPARE4 0x000000A8U + +// Spare Value +#define LRFDRFE_O_SPARE5 0x000000ACU + +// LNA control +#define LRFDRFE_O_LNA 0x000000B0U + +// IFAMPRFLDO control +#define LRFDRFE_O_IFAMPRFLDO 0x000000B4U + +// PA control register +#define LRFDRFE_O_PA0 0x000000B8U + +// PA control register +#define LRFDRFE_O_PA1 0x000000BCU + +// ULNA control, TRX only +#define LRFDRFE_O_ULNA 0x000000C0U + +// IFADC0 configuration register +#define LRFDRFE_O_IFADC0 0x000000C4U + +// IFADC configuration register +#define LRFDRFE_O_IFADC1 0x000000C8U + +// IFADC configuration register +#define LRFDRFE_O_IFADCLF 0x000000CCU + +// IFADC configuration register +#define LRFDRFE_O_IFADCQUANT 0x000000D0U + +// IFADC configuration register +#define LRFDRFE_O_IFADCALDO 0x000000D4U + +// IFADCLDO configuration register +#define LRFDRFE_O_IFADCDLDO 0x000000D8U + +// IFADCTST configuration register +#define LRFDRFE_O_IFADCTST 0x000000DCU + +// Analog test register +#define LRFDRFE_O_ATSTREFL 0x000000E0U + +// Analog test register +#define LRFDRFE_O_ATSTREFH 0x000000E4U + +// DCO Control +#define LRFDRFE_O_DCO 0x000000E8U + +// Divider Control +#define LRFDRFE_O_DIV 0x000000ECU + +// LDO control +#define LRFDRFE_O_DIVLDO 0x000000F0U + +// LDO control +#define LRFDRFE_O_TDCLDO 0x000000F4U + +// LDO control +#define LRFDRFE_O_DCOLDO0 0x000000F8U + +// LDO control +#define LRFDRFE_O_DCOLDO1 0x000000FCU + +// Predivider configuration +#define LRFDRFE_O_PRE0 0x00000100U + +// Predivider configuration +#define LRFDRFE_O_PRE1 0x00000104U + +// Predivider configuration +#define LRFDRFE_O_PRE2 0x00000108U + +// Predivider configuration +#define LRFDRFE_O_PRE3 0x0000010CU + +// Calibration Configuration 0 +#define LRFDRFE_O_CAL0 0x00000110U + +// Calibration Configuration 1 +#define LRFDRFE_O_CAL1 0x00000114U + +// Calibration Configuration 2 +#define LRFDRFE_O_CAL2 0x00000118U + +// Calibration Configuration 3 +#define LRFDRFE_O_CAL3 0x0000011CU + +// SDM and Delay Configuration +#define LRFDRFE_O_MISC0 0x00000120U + +// SDM and Delay Configuration +#define LRFDRFE_O_MISC1 0x00000124U + +// Loop Filter Configuration +#define LRFDRFE_O_LF0 0x00000128U + +// Loop Filter Configuration +#define LRFDRFE_O_LF1 0x0000012CU + +// Phase Configuration +#define LRFDRFE_O_PHEDISC 0x00000130U + +// Phase Configuration +#define LRFDRFE_O_PHINIT 0x00000134U + +// PLL Monitor Configuration +#define LRFDRFE_O_PLLMON0 0x00000138U + +// PLL Monitor Configuration +#define LRFDRFE_O_PLLMON1 0x0000013CU + +// Modulator Configuration +#define LRFDRFE_O_MOD0 0x00000140U + +// Modulator Configuration +#define LRFDRFE_O_MOD1 0x00000144U + +// Digital TX Configuration 0 +#define LRFDRFE_O_DTX0 0x00000148U + +// Digital TX Configuration 1 +#define LRFDRFE_O_DTX1 0x0000014CU + +// Digital TX Configuration 2 +#define LRFDRFE_O_DTX2 0x00000150U + +// Digital TX Configuration 3 +#define LRFDRFE_O_DTX3 0x00000154U + +// Digital TX Configuration 4 +#define LRFDRFE_O_DTX4 0x00000158U + +// Digital TX Configuration 5 +#define LRFDRFE_O_DTX5 0x0000015CU + +// Digital TX Configuration 6 +#define LRFDRFE_O_DTX6 0x00000160U + +// Digital TX Configuration 7 +#define LRFDRFE_O_DTX7 0x00000164U + +// Digital TX Configuration 8 +#define LRFDRFE_O_DTX8 0x00000168U + +// Digital TX Configuration 9 +#define LRFDRFE_O_DTX9 0x0000016CU + +// Digital TX Configuration 10 +#define LRFDRFE_O_DTX10 0x00000170U + +// Digital TX Configuration 11 +#define LRFDRFE_O_DTX11 0x00000174U + +// PLL M0 +#define LRFDRFE_O_PLLM0L 0x00000178U + +// PLL M0 +#define LRFDRFE_O_PLLM0H 0x0000017CU + +// PLL M1 +#define LRFDRFE_O_PLLM1L 0x00000180U + +// PLL M1 +#define LRFDRFE_O_PLLM1H 0x00000184U + +// Calibration M +#define LRFDRFE_O_CALMCRS 0x00000188U + +// Calibration M +#define LRFDRFE_O_CALMMID 0x0000018CU + +// REFCLK Prescaler Load Value +#define LRFDRFE_O_REFDIV 0x00000190U + +// DLO control register 0 +#define LRFDRFE_O_DLOCTL0 0x00000198U + +// DLO control register 1 +#define LRFDRFE_O_DLOCTL1 0x000001A0U + +// DCO Override +#define LRFDRFE_O_DCOOVR0 0x000001A8U + +// DCO Override +#define LRFDRFE_O_DCOOVR1 0x000001ACU + +// Data test +#define LRFDRFE_O_DTST 0x000001B0U + +// FSM and IRQ flags +#define LRFDRFE_O_DLOEV 0x000001B4U + +// DTST read +#define LRFDRFE_O_DTSTRD 0x000001B8U + +// DCO frequency span +#define LRFDRFE_O_FDCOSPANLSB 0x000001BCU + +// DCO frequency span +#define LRFDRFE_O_FDCOSPANMSB 0x000001C0U + +// TDC Calibration +#define LRFDRFE_O_TDCCAL 0x000001C4U + +// Calibration Code +#define LRFDRFE_O_CALRES 0x000001C8U + +// RFE Direct GPI Status +#define LRFDRFE_O_GPI 0x000001CCU + +// Math accellerator input value +#define LRFDRFE_O_MATHACCELIN 0x000001D0U + +// Lin2Log output register +#define LRFDRFE_O_LIN2LOGOUT 0x000001D4U + +// Divide by three output register +#define LRFDRFE_O_DIVBY3OUT 0x000001D8U + +// RFE Timer and Counter Control Register +#define LRFDRFE_O_TIMCTL 0x000001DCU + +// RFE Counter Increment Configuration +#define LRFDRFE_O_TIMINC 0x000001E0U + +// RFE Timer/Counter Period Configuration +#define LRFDRFE_O_TIMPER 0x000001E4U + +// RFE Counter Value +#define LRFDRFE_O_TIMCNT 0x000001E8U + +// RFE Counter Capture Value +#define LRFDRFE_O_TIMCAPT 0x000001ECU + +// RFE Tracer Send Trigger Register +#define LRFDRFE_O_TRCCTRL 0x000001F0U + +// RFE Tracer Status Register +#define LRFDRFE_O_TRCSTAT 0x000001F4U + +// RFE Tracer Commmand Register +#define LRFDRFE_O_TRCCMD 0x000001F8U + +// RFE Tracer Command Parameter Register 0 +#define LRFDRFE_O_TRCPAR0 0x000001FCU + +// RFE Tracer Command Parameter Register 1 +#define LRFDRFE_O_TRCPAR1 0x00000200U + +// RFE Direct GPO control register +#define LRFDRFE_O_GPOCTL 0x00000204U + +// Analog Isolation Control +#define LRFDRFE_O_ANAISOCTL 0x00000208U + +// Divider Control +#define LRFDRFE_O_DIVCTL 0x0000020CU + +// RX Frontend control register +#define LRFDRFE_O_RXCTRL 0x00000210U + +// Magnitude estimator 0 accumulator value +#define LRFDRFE_O_MAGNACC0 0x00000214U + +// Magnitude estimator 1 accumulator value +#define LRFDRFE_O_MAGNACC1 0x00000218U + +// RSSI Value Register +#define LRFDRFE_O_RSSI 0x0000021CU + +// RSSI Maximum Value Register +#define LRFDRFE_O_RSSIMAX 0x00000220U + +// RF front-end gain value +#define LRFDRFE_O_RFGAIN 0x00000224U + +// IFADC status +#define LRFDRFE_O_IFADCSTAT 0x00000228U + +// Serial Divider Status Register +#define LRFDRFE_O_DIVSTA 0x0000022CU + +// Serial Divider Dividend Register +#define LRFDRFE_O_DIVIDENDL 0x00000230U + +// Serial Divider Dividend Register +#define LRFDRFE_O_DIVIDENDH 0x00000234U + +// Serial Divider Divisor Register +#define LRFDRFE_O_DIVISORL 0x00000238U + +// Serial Divider Divisor Register +#define LRFDRFE_O_DIVISORH 0x0000023CU + +// Serial Divider Quotient Register +#define LRFDRFE_O_QUOTIENTL 0x00000240U + +// Serial Divider Quotient Register +#define LRFDRFE_O_QUOTIENTH 0x00000244U + +// Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB +#define LRFDRFE_O_PRODUCTL 0x00000248U + +// Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB +#define LRFDRFE_O_PRODUCTH 0x0000024CU + +// Serial Multiplier Status Register +#define LRFDRFE_O_MULTSTA 0x00000250U + +// Serial Multiplier Control Register +#define LRFDRFE_O_MULTCFG 0x00000258U + +//***************************************************************************** +// +// Register: LRFDRFE_O_ENABLE +// +//***************************************************************************** +// Field: [3] ACC1 +// +// Enables the Magnitude Accumulator 1 +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE_ENABLE_ACC1 0x00000008U +#define LRFDRFE_ENABLE_ACC1_M 0x00000008U +#define LRFDRFE_ENABLE_ACC1_S 3U +#define LRFDRFE_ENABLE_ACC1_EN 0x00000008U +#define LRFDRFE_ENABLE_ACC1_DIS 0x00000000U + +// Field: [2] ACC0 +// +// Enables the Magnitude Accumulator 0 +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE_ENABLE_ACC0 0x00000004U +#define LRFDRFE_ENABLE_ACC0_M 0x00000004U +#define LRFDRFE_ENABLE_ACC0_S 2U +#define LRFDRFE_ENABLE_ACC0_EN 0x00000004U +#define LRFDRFE_ENABLE_ACC0_DIS 0x00000000U + +// Field: [1] LOCTIM +// +// Enables the Local timer +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE_ENABLE_LOCTIM 0x00000002U +#define LRFDRFE_ENABLE_LOCTIM_M 0x00000002U +#define LRFDRFE_ENABLE_LOCTIM_S 1U +#define LRFDRFE_ENABLE_LOCTIM_EN 0x00000002U +#define LRFDRFE_ENABLE_LOCTIM_DIS 0x00000000U + +// Field: [0] TOPSM +// +// Enables the TOPsm (RFE) +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE_ENABLE_TOPSM 0x00000001U +#define LRFDRFE_ENABLE_TOPSM_M 0x00000001U +#define LRFDRFE_ENABLE_TOPSM_S 0U +#define LRFDRFE_ENABLE_TOPSM_EN 0x00000001U +#define LRFDRFE_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_FWSRC +// +//***************************************************************************** +// Field: [2] DATARAM +// +// Selects RAM to use for data storage +// ENUMs: +// S2RRAM Use S2RRAM for data +// RFERAM Use RFERAM for data +#define LRFDRFE_FWSRC_DATARAM 0x00000004U +#define LRFDRFE_FWSRC_DATARAM_M 0x00000004U +#define LRFDRFE_FWSRC_DATARAM_S 2U +#define LRFDRFE_FWSRC_DATARAM_S2RRAM 0x00000004U +#define LRFDRFE_FWSRC_DATARAM_RFERAM 0x00000000U + +// Field: [1] FWRAM +// +// Selects RAM to use for program memory +// ENUMs: +// S2RRAM Run code from S2RRAM +// RFERAM Run code from RFERAM +#define LRFDRFE_FWSRC_FWRAM 0x00000002U +#define LRFDRFE_FWSRC_FWRAM_M 0x00000002U +#define LRFDRFE_FWSRC_FWRAM_S 1U +#define LRFDRFE_FWSRC_FWRAM_S2RRAM 0x00000002U +#define LRFDRFE_FWSRC_FWRAM_RFERAM 0x00000000U + +// Field: [0] BANK +// +// Selects 2K bank within the program memory as FW source. +// This controls MSB of address line towards program memory. +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDRFE_FWSRC_BANK 0x00000001U +#define LRFDRFE_FWSRC_BANK_M 0x00000001U +#define LRFDRFE_FWSRC_BANK_S 0U +#define LRFDRFE_FWSRC_BANK_ONE 0x00000001U +#define LRFDRFE_FWSRC_BANK_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_INIT +// +//***************************************************************************** +// Field: [3] ACC1 +// +// Synchronous reset to magnitude accumulator 1 +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE_INIT_ACC1 0x00000008U +#define LRFDRFE_INIT_ACC1_M 0x00000008U +#define LRFDRFE_INIT_ACC1_S 3U +#define LRFDRFE_INIT_ACC1_RESET 0x00000008U +#define LRFDRFE_INIT_ACC1_NO_EFFECT 0x00000000U + +// Field: [2] ACC0 +// +// Synchronous reset to magnitude accumulator 0 +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE_INIT_ACC0 0x00000004U +#define LRFDRFE_INIT_ACC0_M 0x00000004U +#define LRFDRFE_INIT_ACC0_S 2U +#define LRFDRFE_INIT_ACC0_RESET 0x00000004U +#define LRFDRFE_INIT_ACC0_NO_EFFECT 0x00000000U + +// Field: [1] LOCTIM +// +// Synchronous reset to local timer +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE_INIT_LOCTIM 0x00000002U +#define LRFDRFE_INIT_LOCTIM_M 0x00000002U +#define LRFDRFE_INIT_LOCTIM_S 1U +#define LRFDRFE_INIT_LOCTIM_RESET 0x00000002U +#define LRFDRFE_INIT_LOCTIM_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// Synchronous reset to TOPsm (RFE) +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE_INIT_TOPSM 0x00000001U +#define LRFDRFE_INIT_TOPSM_M 0x00000001U +#define LRFDRFE_INIT_TOPSM_S 0U +#define LRFDRFE_INIT_TOPSM_RESET 0x00000001U +#define LRFDRFE_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PDREQ +// +//***************************************************************************** +// Field: [0] TOPSMPDREQ +// +// Requests power down for TOPsm core. If the TOPsm has an ongoing memory +// access, the hardware will safely gate the clock after the transaction has +// completed. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_PDREQ_TOPSMPDREQ 0x00000001U +#define LRFDRFE_PDREQ_TOPSMPDREQ_M 0x00000001U +#define LRFDRFE_PDREQ_TOPSMPDREQ_S 0U +#define LRFDRFE_PDREQ_TOPSMPDREQ_ONE 0x00000001U +#define LRFDRFE_PDREQ_TOPSMPDREQ_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVT0 +// +//***************************************************************************** +// Field: [14] MAGNTHR +// +// Magnitude accumulator amplitude is above MAGNTHR theshold +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_MAGNTHR 0x00004000U +#define LRFDRFE_EVT0_MAGNTHR_M 0x00004000U +#define LRFDRFE_EVT0_MAGNTHR_S 14U +#define LRFDRFE_EVT0_MAGNTHR_ONE 0x00004000U +#define LRFDRFE_EVT0_MAGNTHR_ZERO 0x00000000U + +// Field: [13] S2RSTOP +// +// S2R has written to LRFDS2R:STOP.ADDR +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_S2RSTOP 0x00002000U +#define LRFDRFE_EVT0_S2RSTOP_M 0x00002000U +#define LRFDRFE_EVT0_S2RSTOP_S 13U +#define LRFDRFE_EVT0_S2RSTOP_ONE 0x00002000U +#define LRFDRFE_EVT0_S2RSTOP_ZERO 0x00000000U + +// Field: [12] SYSTCMP2 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_SYSTCMP2 0x00001000U +#define LRFDRFE_EVT0_SYSTCMP2_M 0x00001000U +#define LRFDRFE_EVT0_SYSTCMP2_S 12U +#define LRFDRFE_EVT0_SYSTCMP2_ONE 0x00001000U +#define LRFDRFE_EVT0_SYSTCMP2_ZERO 0x00000000U + +// Field: [11] SYSTCMP1 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_SYSTCMP1 0x00000800U +#define LRFDRFE_EVT0_SYSTCMP1_M 0x00000800U +#define LRFDRFE_EVT0_SYSTCMP1_S 11U +#define LRFDRFE_EVT0_SYSTCMP1_ONE 0x00000800U +#define LRFDRFE_EVT0_SYSTCMP1_ZERO 0x00000000U + +// Field: [10] SYSTCMP0 +// +// Systimer compare event +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_SYSTCMP0 0x00000400U +#define LRFDRFE_EVT0_SYSTCMP0_M 0x00000400U +#define LRFDRFE_EVT0_SYSTCMP0_S 10U +#define LRFDRFE_EVT0_SYSTCMP0_ONE 0x00000400U +#define LRFDRFE_EVT0_SYSTCMP0_ZERO 0x00000000U + +// Field: [9] PBERFEDAT +// +// New data from PBE in PBEDATIN0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_PBERFEDAT 0x00000200U +#define LRFDRFE_EVT0_PBERFEDAT_M 0x00000200U +#define LRFDRFE_EVT0_PBERFEDAT_S 9U +#define LRFDRFE_EVT0_PBERFEDAT_ONE 0x00000200U +#define LRFDRFE_EVT0_PBERFEDAT_ZERO 0x00000000U + +// Field: [8] MDMRFEDAT +// +// New data from MCE in MCEDATIN0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_MDMRFEDAT 0x00000100U +#define LRFDRFE_EVT0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE_EVT0_MDMRFEDAT_S 8U +#define LRFDRFE_EVT0_MDMRFEDAT_ONE 0x00000100U +#define LRFDRFE_EVT0_MDMRFEDAT_ZERO 0x00000000U + +// Field: [7] DLO +// +// Event from DLO state machine +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_DLO 0x00000080U +#define LRFDRFE_EVT0_DLO_M 0x00000080U +#define LRFDRFE_EVT0_DLO_S 7U +#define LRFDRFE_EVT0_DLO_ONE 0x00000080U +#define LRFDRFE_EVT0_DLO_ZERO 0x00000000U + +// Field: [6] PBECMD +// +// New command from PBE in PBECMDIN +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_PBECMD 0x00000040U +#define LRFDRFE_EVT0_PBECMD_M 0x00000040U +#define LRFDRFE_EVT0_PBECMD_S 6U +#define LRFDRFE_EVT0_PBECMD_ONE 0x00000040U +#define LRFDRFE_EVT0_PBECMD_ZERO 0x00000000U + +// Field: [5] COUNTER +// +// Counter value reached in local timer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_COUNTER 0x00000020U +#define LRFDRFE_EVT0_COUNTER_M 0x00000020U +#define LRFDRFE_EVT0_COUNTER_S 5U +#define LRFDRFE_EVT0_COUNTER_ONE 0x00000020U +#define LRFDRFE_EVT0_COUNTER_ZERO 0x00000000U + +// Field: [4] MDMCMD +// +// New command from MCE in MCECMDIN +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_MDMCMD 0x00000010U +#define LRFDRFE_EVT0_MDMCMD_M 0x00000010U +#define LRFDRFE_EVT0_MDMCMD_S 4U +#define LRFDRFE_EVT0_MDMCMD_ONE 0x00000010U +#define LRFDRFE_EVT0_MDMCMD_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// Accumulation period completed in magnitude accumulator 1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_ACC1 0x00000008U +#define LRFDRFE_EVT0_ACC1_M 0x00000008U +#define LRFDRFE_EVT0_ACC1_S 3U +#define LRFDRFE_EVT0_ACC1_ONE 0x00000008U +#define LRFDRFE_EVT0_ACC1_ZERO 0x00000000U + +// Field: [2] ACC0 +// +// Accumulation period completed in magnitude accumulator 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_ACC0 0x00000004U +#define LRFDRFE_EVT0_ACC0_M 0x00000004U +#define LRFDRFE_EVT0_ACC0_S 2U +#define LRFDRFE_EVT0_ACC0_ONE 0x00000004U +#define LRFDRFE_EVT0_ACC0_ZERO 0x00000000U + +// Field: [1] TIMER +// +// Timer period expired in local timer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_TIMER 0x00000002U +#define LRFDRFE_EVT0_TIMER_M 0x00000002U +#define LRFDRFE_EVT0_TIMER_S 1U +#define LRFDRFE_EVT0_TIMER_ONE 0x00000002U +#define LRFDRFE_EVT0_TIMER_ZERO 0x00000000U + +// Field: [0] RFEAPI +// +// New RFE API availabe in API +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT0_RFEAPI 0x00000001U +#define LRFDRFE_EVT0_RFEAPI_M 0x00000001U +#define LRFDRFE_EVT0_RFEAPI_S 0U +#define LRFDRFE_EVT0_RFEAPI_ONE 0x00000001U +#define LRFDRFE_EVT0_RFEAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVT1 +// +//***************************************************************************** +// Field: [13] PREREFCLK +// +// Prescaled REFCLK event, controlled by DCOCTL0.LOOPUPD +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_PREREFCLK 0x00002000U +#define LRFDRFE_EVT1_PREREFCLK_M 0x00002000U +#define LRFDRFE_EVT1_PREREFCLK_S 13U +#define LRFDRFE_EVT1_PREREFCLK_ONE 0x00002000U +#define LRFDRFE_EVT1_PREREFCLK_ZERO 0x00000000U + +// Field: [12] REFCLK +// +// REFCLK event from DLO +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_REFCLK 0x00001000U +#define LRFDRFE_EVT1_REFCLK_M 0x00001000U +#define LRFDRFE_EVT1_REFCLK_S 12U +#define LRFDRFE_EVT1_REFCLK_ONE 0x00001000U +#define LRFDRFE_EVT1_REFCLK_ZERO 0x00000000U + +// Field: [11] FBLWTHR +// +// Finecode below programmed threshold event from DLO state machine +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_FBLWTHR 0x00000800U +#define LRFDRFE_EVT1_FBLWTHR_M 0x00000800U +#define LRFDRFE_EVT1_FBLWTHR_S 11U +#define LRFDRFE_EVT1_FBLWTHR_ONE 0x00000800U +#define LRFDRFE_EVT1_FBLWTHR_ZERO 0x00000000U + +// Field: [10] FABVTHR +// +// Finecode above programmed threshold event from DLO state machine +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_FABVTHR 0x00000400U +#define LRFDRFE_EVT1_FABVTHR_M 0x00000400U +#define LRFDRFE_EVT1_FABVTHR_S 10U +#define LRFDRFE_EVT1_FABVTHR_ONE 0x00000400U +#define LRFDRFE_EVT1_FABVTHR_ZERO 0x00000000U + +// Field: [9] LOCK +// +// Lock event from DLO state machine +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_LOCK 0x00000200U +#define LRFDRFE_EVT1_LOCK_M 0x00000200U +#define LRFDRFE_EVT1_LOCK_S 9U +#define LRFDRFE_EVT1_LOCK_ONE 0x00000200U +#define LRFDRFE_EVT1_LOCK_ZERO 0x00000000U + +// Field: [8] LOL +// +// Loss of lock event from DLO state machine +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_LOL 0x00000100U +#define LRFDRFE_EVT1_LOL_M 0x00000100U +#define LRFDRFE_EVT1_LOL_S 8U +#define LRFDRFE_EVT1_LOL_ONE 0x00000100U +#define LRFDRFE_EVT1_LOL_ZERO 0x00000000U + +// Field: [7] GPI7 +// +// External input event line GPI7 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI7 0x00000080U +#define LRFDRFE_EVT1_GPI7_M 0x00000080U +#define LRFDRFE_EVT1_GPI7_S 7U +#define LRFDRFE_EVT1_GPI7_ONE 0x00000080U +#define LRFDRFE_EVT1_GPI7_ZERO 0x00000000U + +// Field: [6] GPI6 +// +// External input event line GPI6 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI6 0x00000040U +#define LRFDRFE_EVT1_GPI6_M 0x00000040U +#define LRFDRFE_EVT1_GPI6_S 6U +#define LRFDRFE_EVT1_GPI6_ONE 0x00000040U +#define LRFDRFE_EVT1_GPI6_ZERO 0x00000000U + +// Field: [5] GPI5 +// +// External input event line GPI5 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI5 0x00000020U +#define LRFDRFE_EVT1_GPI5_M 0x00000020U +#define LRFDRFE_EVT1_GPI5_S 5U +#define LRFDRFE_EVT1_GPI5_ONE 0x00000020U +#define LRFDRFE_EVT1_GPI5_ZERO 0x00000000U + +// Field: [4] GPI4 +// +// External input event line GPI4 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI4 0x00000010U +#define LRFDRFE_EVT1_GPI4_M 0x00000010U +#define LRFDRFE_EVT1_GPI4_S 4U +#define LRFDRFE_EVT1_GPI4_ONE 0x00000010U +#define LRFDRFE_EVT1_GPI4_ZERO 0x00000000U + +// Field: [3] GPI3 +// +// External input event line GPI3 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI3 0x00000008U +#define LRFDRFE_EVT1_GPI3_M 0x00000008U +#define LRFDRFE_EVT1_GPI3_S 3U +#define LRFDRFE_EVT1_GPI3_ONE 0x00000008U +#define LRFDRFE_EVT1_GPI3_ZERO 0x00000000U + +// Field: [2] GPI2 +// +// External input event line GPI2 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI2 0x00000004U +#define LRFDRFE_EVT1_GPI2_M 0x00000004U +#define LRFDRFE_EVT1_GPI2_S 2U +#define LRFDRFE_EVT1_GPI2_ONE 0x00000004U +#define LRFDRFE_EVT1_GPI2_ZERO 0x00000000U + +// Field: [1] GPI1 +// +// External input event line GPI1 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI1 0x00000002U +#define LRFDRFE_EVT1_GPI1_M 0x00000002U +#define LRFDRFE_EVT1_GPI1_S 1U +#define LRFDRFE_EVT1_GPI1_ONE 0x00000002U +#define LRFDRFE_EVT1_GPI1_ZERO 0x00000000U + +// Field: [0] GPI0 +// +// External input event line GPI0 from IOC +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVT1_GPI0 0x00000001U +#define LRFDRFE_EVT1_GPI0_M 0x00000001U +#define LRFDRFE_EVT1_GPI0_S 0U +#define LRFDRFE_EVT1_GPI0_ONE 0x00000001U +#define LRFDRFE_EVT1_GPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVTMSK0 +// +//***************************************************************************** +// Field: [14] MAGNTHR +// +// Enable mask for event EVT0.MAGNTHR +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_MAGNTHR 0x00004000U +#define LRFDRFE_EVTMSK0_MAGNTHR_M 0x00004000U +#define LRFDRFE_EVTMSK0_MAGNTHR_S 14U +#define LRFDRFE_EVTMSK0_MAGNTHR_EN 0x00004000U +#define LRFDRFE_EVTMSK0_MAGNTHR_DIS 0x00000000U + +// Field: [13] S2RSTOP +// +// Enable mask for event EVT0.S2RSTOP +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_S2RSTOP 0x00002000U +#define LRFDRFE_EVTMSK0_S2RSTOP_M 0x00002000U +#define LRFDRFE_EVTMSK0_S2RSTOP_S 13U +#define LRFDRFE_EVTMSK0_S2RSTOP_EN 0x00002000U +#define LRFDRFE_EVTMSK0_S2RSTOP_DIS 0x00000000U + +// Field: [12] SYSTCMP2 +// +// Enable mask for event EVT0.SYSTCMP2 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_SYSTCMP2 0x00001000U +#define LRFDRFE_EVTMSK0_SYSTCMP2_M 0x00001000U +#define LRFDRFE_EVTMSK0_SYSTCMP2_S 12U +#define LRFDRFE_EVTMSK0_SYSTCMP2_EN 0x00001000U +#define LRFDRFE_EVTMSK0_SYSTCMP2_DIS 0x00000000U + +// Field: [11] SYSTCMP1 +// +// Enable mask for event EVT0.SYSTCMP1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_SYSTCMP1 0x00000800U +#define LRFDRFE_EVTMSK0_SYSTCMP1_M 0x00000800U +#define LRFDRFE_EVTMSK0_SYSTCMP1_S 11U +#define LRFDRFE_EVTMSK0_SYSTCMP1_EN 0x00000800U +#define LRFDRFE_EVTMSK0_SYSTCMP1_DIS 0x00000000U + +// Field: [10] SYSTCMP0 +// +// Enable mask for event EVT0.SYSTCMP0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_SYSTCMP0 0x00000400U +#define LRFDRFE_EVTMSK0_SYSTCMP0_M 0x00000400U +#define LRFDRFE_EVTMSK0_SYSTCMP0_S 10U +#define LRFDRFE_EVTMSK0_SYSTCMP0_EN 0x00000400U +#define LRFDRFE_EVTMSK0_SYSTCMP0_DIS 0x00000000U + +// Field: [9] PBERFEDAT +// +// Enable mask for event EVT0.PBERFEDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_PBERFEDAT 0x00000200U +#define LRFDRFE_EVTMSK0_PBERFEDAT_M 0x00000200U +#define LRFDRFE_EVTMSK0_PBERFEDAT_S 9U +#define LRFDRFE_EVTMSK0_PBERFEDAT_EN 0x00000200U +#define LRFDRFE_EVTMSK0_PBERFEDAT_DIS 0x00000000U + +// Field: [8] MDMRFEDAT +// +// Enable mask for event EVT0.MDMRFEDAT +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_MDMRFEDAT 0x00000100U +#define LRFDRFE_EVTMSK0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE_EVTMSK0_MDMRFEDAT_S 8U +#define LRFDRFE_EVTMSK0_MDMRFEDAT_EN 0x00000100U +#define LRFDRFE_EVTMSK0_MDMRFEDAT_DIS 0x00000000U + +// Field: [7] DLO +// +// Enable mask for event EVT0.DLO +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_DLO 0x00000080U +#define LRFDRFE_EVTMSK0_DLO_M 0x00000080U +#define LRFDRFE_EVTMSK0_DLO_S 7U +#define LRFDRFE_EVTMSK0_DLO_EN 0x00000080U +#define LRFDRFE_EVTMSK0_DLO_DIS 0x00000000U + +// Field: [6] PBECMD +// +// Enable mask for event EVT0.PBECMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_PBECMD 0x00000040U +#define LRFDRFE_EVTMSK0_PBECMD_M 0x00000040U +#define LRFDRFE_EVTMSK0_PBECMD_S 6U +#define LRFDRFE_EVTMSK0_PBECMD_EN 0x00000040U +#define LRFDRFE_EVTMSK0_PBECMD_DIS 0x00000000U + +// Field: [5] COUNTER +// +// Enable mask for event EVT0.COUNTER +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_COUNTER 0x00000020U +#define LRFDRFE_EVTMSK0_COUNTER_M 0x00000020U +#define LRFDRFE_EVTMSK0_COUNTER_S 5U +#define LRFDRFE_EVTMSK0_COUNTER_EN 0x00000020U +#define LRFDRFE_EVTMSK0_COUNTER_DIS 0x00000000U + +// Field: [4] MDMCMD +// +// Enable mask for event EVT0.MDMCMD +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_MDMCMD 0x00000010U +#define LRFDRFE_EVTMSK0_MDMCMD_M 0x00000010U +#define LRFDRFE_EVTMSK0_MDMCMD_S 4U +#define LRFDRFE_EVTMSK0_MDMCMD_EN 0x00000010U +#define LRFDRFE_EVTMSK0_MDMCMD_DIS 0x00000000U + +// Field: [3] ACC1 +// +// Enable mask for event EVT0.ACC1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_ACC1 0x00000008U +#define LRFDRFE_EVTMSK0_ACC1_M 0x00000008U +#define LRFDRFE_EVTMSK0_ACC1_S 3U +#define LRFDRFE_EVTMSK0_ACC1_EN 0x00000008U +#define LRFDRFE_EVTMSK0_ACC1_DIS 0x00000000U + +// Field: [2] ACC0 +// +// Enable mask for event EVT0.ACC0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_ACC0 0x00000004U +#define LRFDRFE_EVTMSK0_ACC0_M 0x00000004U +#define LRFDRFE_EVTMSK0_ACC0_S 2U +#define LRFDRFE_EVTMSK0_ACC0_EN 0x00000004U +#define LRFDRFE_EVTMSK0_ACC0_DIS 0x00000000U + +// Field: [1] TIMER +// +// Enable mask for event EVT0.TIMER +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_TIMER 0x00000002U +#define LRFDRFE_EVTMSK0_TIMER_M 0x00000002U +#define LRFDRFE_EVTMSK0_TIMER_S 1U +#define LRFDRFE_EVTMSK0_TIMER_EN 0x00000002U +#define LRFDRFE_EVTMSK0_TIMER_DIS 0x00000000U + +// Field: [0] RFEAPI +// +// Enable mask for event EVT0.RFEAPI +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK0_RFEAPI 0x00000001U +#define LRFDRFE_EVTMSK0_RFEAPI_M 0x00000001U +#define LRFDRFE_EVTMSK0_RFEAPI_S 0U +#define LRFDRFE_EVTMSK0_RFEAPI_EN 0x00000001U +#define LRFDRFE_EVTMSK0_RFEAPI_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVTMSK1 +// +//***************************************************************************** +// Field: [13] PREREFCLK +// +// Enable mask for event EVT1.PREREFCLK +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_PREREFCLK 0x00002000U +#define LRFDRFE_EVTMSK1_PREREFCLK_M 0x00002000U +#define LRFDRFE_EVTMSK1_PREREFCLK_S 13U +#define LRFDRFE_EVTMSK1_PREREFCLK_EN 0x00002000U +#define LRFDRFE_EVTMSK1_PREREFCLK_DIS 0x00000000U + +// Field: [12] REFCLK +// +// Enable mask for event EVT1.REFCLK +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_REFCLK 0x00001000U +#define LRFDRFE_EVTMSK1_REFCLK_M 0x00001000U +#define LRFDRFE_EVTMSK1_REFCLK_S 12U +#define LRFDRFE_EVTMSK1_REFCLK_EN 0x00001000U +#define LRFDRFE_EVTMSK1_REFCLK_DIS 0x00000000U + +// Field: [11] FBLWTHR +// +// Enable mask for event EVT1.FBLWTHR +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_FBLWTHR 0x00000800U +#define LRFDRFE_EVTMSK1_FBLWTHR_M 0x00000800U +#define LRFDRFE_EVTMSK1_FBLWTHR_S 11U +#define LRFDRFE_EVTMSK1_FBLWTHR_EN 0x00000800U +#define LRFDRFE_EVTMSK1_FBLWTHR_DIS 0x00000000U + +// Field: [10] FABVTHR +// +// Enable mask for event EVT1.FABVTHR +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_FABVTHR 0x00000400U +#define LRFDRFE_EVTMSK1_FABVTHR_M 0x00000400U +#define LRFDRFE_EVTMSK1_FABVTHR_S 10U +#define LRFDRFE_EVTMSK1_FABVTHR_EN 0x00000400U +#define LRFDRFE_EVTMSK1_FABVTHR_DIS 0x00000000U + +// Field: [9] LOCK +// +// Enable mask for event EVT1.LOCK +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_LOCK 0x00000200U +#define LRFDRFE_EVTMSK1_LOCK_M 0x00000200U +#define LRFDRFE_EVTMSK1_LOCK_S 9U +#define LRFDRFE_EVTMSK1_LOCK_EN 0x00000200U +#define LRFDRFE_EVTMSK1_LOCK_DIS 0x00000000U + +// Field: [8] LOL +// +// Enable mask for event EVT1.LOL +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_LOL 0x00000100U +#define LRFDRFE_EVTMSK1_LOL_M 0x00000100U +#define LRFDRFE_EVTMSK1_LOL_S 8U +#define LRFDRFE_EVTMSK1_LOL_EN 0x00000100U +#define LRFDRFE_EVTMSK1_LOL_DIS 0x00000000U + +// Field: [7] GPI7 +// +// Enable mask for event EVT1.GPI7 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI7 0x00000080U +#define LRFDRFE_EVTMSK1_GPI7_M 0x00000080U +#define LRFDRFE_EVTMSK1_GPI7_S 7U +#define LRFDRFE_EVTMSK1_GPI7_EN 0x00000080U +#define LRFDRFE_EVTMSK1_GPI7_DIS 0x00000000U + +// Field: [6] GPI6 +// +// Enable mask for event EVT1.GPI6 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI6 0x00000040U +#define LRFDRFE_EVTMSK1_GPI6_M 0x00000040U +#define LRFDRFE_EVTMSK1_GPI6_S 6U +#define LRFDRFE_EVTMSK1_GPI6_EN 0x00000040U +#define LRFDRFE_EVTMSK1_GPI6_DIS 0x00000000U + +// Field: [5] GPI5 +// +// Enable mask for event EVT1.GPI5 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI5 0x00000020U +#define LRFDRFE_EVTMSK1_GPI5_M 0x00000020U +#define LRFDRFE_EVTMSK1_GPI5_S 5U +#define LRFDRFE_EVTMSK1_GPI5_EN 0x00000020U +#define LRFDRFE_EVTMSK1_GPI5_DIS 0x00000000U + +// Field: [4] GPI4 +// +// Enable mask for event EVT1.GPI4 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI4 0x00000010U +#define LRFDRFE_EVTMSK1_GPI4_M 0x00000010U +#define LRFDRFE_EVTMSK1_GPI4_S 4U +#define LRFDRFE_EVTMSK1_GPI4_EN 0x00000010U +#define LRFDRFE_EVTMSK1_GPI4_DIS 0x00000000U + +// Field: [3] GPI3 +// +// Enable mask for event EVT1.GPI3 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI3 0x00000008U +#define LRFDRFE_EVTMSK1_GPI3_M 0x00000008U +#define LRFDRFE_EVTMSK1_GPI3_S 3U +#define LRFDRFE_EVTMSK1_GPI3_EN 0x00000008U +#define LRFDRFE_EVTMSK1_GPI3_DIS 0x00000000U + +// Field: [2] GPI2 +// +// Enable mask for event EVT1.GPI2 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI2 0x00000004U +#define LRFDRFE_EVTMSK1_GPI2_M 0x00000004U +#define LRFDRFE_EVTMSK1_GPI2_S 2U +#define LRFDRFE_EVTMSK1_GPI2_EN 0x00000004U +#define LRFDRFE_EVTMSK1_GPI2_DIS 0x00000000U + +// Field: [1] GPI1 +// +// Enable mask for event EVT1.GPI1 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI1 0x00000002U +#define LRFDRFE_EVTMSK1_GPI1_M 0x00000002U +#define LRFDRFE_EVTMSK1_GPI1_S 1U +#define LRFDRFE_EVTMSK1_GPI1_EN 0x00000002U +#define LRFDRFE_EVTMSK1_GPI1_DIS 0x00000000U + +// Field: [0] GPI0 +// +// Enable mask for event EVT1.GPI0 +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_EVTMSK1_GPI0 0x00000001U +#define LRFDRFE_EVTMSK1_GPI0_M 0x00000001U +#define LRFDRFE_EVTMSK1_GPI0_S 0U +#define LRFDRFE_EVTMSK1_GPI0_EN 0x00000001U +#define LRFDRFE_EVTMSK1_GPI0_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVTCLR0 +// +//***************************************************************************** +// Field: [14] MAGNTHR +// +// Clear event EVT0.MAGNTHR +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_MAGNTHR 0x00004000U +#define LRFDRFE_EVTCLR0_MAGNTHR_M 0x00004000U +#define LRFDRFE_EVTCLR0_MAGNTHR_S 14U +#define LRFDRFE_EVTCLR0_MAGNTHR_ONE 0x00004000U +#define LRFDRFE_EVTCLR0_MAGNTHR_ZERO 0x00000000U + +// Field: [13] S2RSTOP +// +// Clear event EVT0.S2RSTOP +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_S2RSTOP 0x00002000U +#define LRFDRFE_EVTCLR0_S2RSTOP_M 0x00002000U +#define LRFDRFE_EVTCLR0_S2RSTOP_S 13U +#define LRFDRFE_EVTCLR0_S2RSTOP_ONE 0x00002000U +#define LRFDRFE_EVTCLR0_S2RSTOP_ZERO 0x00000000U + +// Field: [12] SYSTCMP2 +// +// Clear event EVT0.SYSTCMP2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_SYSTCMP2 0x00001000U +#define LRFDRFE_EVTCLR0_SYSTCMP2_M 0x00001000U +#define LRFDRFE_EVTCLR0_SYSTCMP2_S 12U +#define LRFDRFE_EVTCLR0_SYSTCMP2_ONE 0x00001000U +#define LRFDRFE_EVTCLR0_SYSTCMP2_ZERO 0x00000000U + +// Field: [11] SYSTCMP1 +// +// Clear event EVT0.SYSTCMP1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_SYSTCMP1 0x00000800U +#define LRFDRFE_EVTCLR0_SYSTCMP1_M 0x00000800U +#define LRFDRFE_EVTCLR0_SYSTCMP1_S 11U +#define LRFDRFE_EVTCLR0_SYSTCMP1_ONE 0x00000800U +#define LRFDRFE_EVTCLR0_SYSTCMP1_ZERO 0x00000000U + +// Field: [10] SYSTCMP0 +// +// Clear event EVT0.SYSTCMP0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_SYSTCMP0 0x00000400U +#define LRFDRFE_EVTCLR0_SYSTCMP0_M 0x00000400U +#define LRFDRFE_EVTCLR0_SYSTCMP0_S 10U +#define LRFDRFE_EVTCLR0_SYSTCMP0_ONE 0x00000400U +#define LRFDRFE_EVTCLR0_SYSTCMP0_ZERO 0x00000000U + +// Field: [9] PBERFEDAT +// +// Clear event EVT0.PBERFEDAT +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_PBERFEDAT 0x00000200U +#define LRFDRFE_EVTCLR0_PBERFEDAT_M 0x00000200U +#define LRFDRFE_EVTCLR0_PBERFEDAT_S 9U +#define LRFDRFE_EVTCLR0_PBERFEDAT_ONE 0x00000200U +#define LRFDRFE_EVTCLR0_PBERFEDAT_ZERO 0x00000000U + +// Field: [8] MDMRFEDAT +// +// Clear event EVT0.MDMRFEDAT +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_MDMRFEDAT 0x00000100U +#define LRFDRFE_EVTCLR0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE_EVTCLR0_MDMRFEDAT_S 8U +#define LRFDRFE_EVTCLR0_MDMRFEDAT_ONE 0x00000100U +#define LRFDRFE_EVTCLR0_MDMRFEDAT_ZERO 0x00000000U + +// Field: [7] DLO +// +// Clear event EVT0.DLO +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_DLO 0x00000080U +#define LRFDRFE_EVTCLR0_DLO_M 0x00000080U +#define LRFDRFE_EVTCLR0_DLO_S 7U +#define LRFDRFE_EVTCLR0_DLO_ONE 0x00000080U +#define LRFDRFE_EVTCLR0_DLO_ZERO 0x00000000U + +// Field: [6] PBECMD +// +// Clear event EVT0.PBECMD +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_PBECMD 0x00000040U +#define LRFDRFE_EVTCLR0_PBECMD_M 0x00000040U +#define LRFDRFE_EVTCLR0_PBECMD_S 6U +#define LRFDRFE_EVTCLR0_PBECMD_ONE 0x00000040U +#define LRFDRFE_EVTCLR0_PBECMD_ZERO 0x00000000U + +// Field: [5] COUNTER +// +// Clear event EVT0.COUNTER +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_COUNTER 0x00000020U +#define LRFDRFE_EVTCLR0_COUNTER_M 0x00000020U +#define LRFDRFE_EVTCLR0_COUNTER_S 5U +#define LRFDRFE_EVTCLR0_COUNTER_ONE 0x00000020U +#define LRFDRFE_EVTCLR0_COUNTER_ZERO 0x00000000U + +// Field: [4] MDMCMD +// +// Clear event EVT0.MDMCMD +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_MDMCMD 0x00000010U +#define LRFDRFE_EVTCLR0_MDMCMD_M 0x00000010U +#define LRFDRFE_EVTCLR0_MDMCMD_S 4U +#define LRFDRFE_EVTCLR0_MDMCMD_ONE 0x00000010U +#define LRFDRFE_EVTCLR0_MDMCMD_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// Clear event EVT0.ACC1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_ACC1 0x00000008U +#define LRFDRFE_EVTCLR0_ACC1_M 0x00000008U +#define LRFDRFE_EVTCLR0_ACC1_S 3U +#define LRFDRFE_EVTCLR0_ACC1_ONE 0x00000008U +#define LRFDRFE_EVTCLR0_ACC1_ZERO 0x00000000U + +// Field: [2] ACC0 +// +// Clear event EVT0.ACC0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_ACC0 0x00000004U +#define LRFDRFE_EVTCLR0_ACC0_M 0x00000004U +#define LRFDRFE_EVTCLR0_ACC0_S 2U +#define LRFDRFE_EVTCLR0_ACC0_ONE 0x00000004U +#define LRFDRFE_EVTCLR0_ACC0_ZERO 0x00000000U + +// Field: [1] TIMER +// +// Clear event EVT0.TIMER +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_TIMER 0x00000002U +#define LRFDRFE_EVTCLR0_TIMER_M 0x00000002U +#define LRFDRFE_EVTCLR0_TIMER_S 1U +#define LRFDRFE_EVTCLR0_TIMER_ONE 0x00000002U +#define LRFDRFE_EVTCLR0_TIMER_ZERO 0x00000000U + +// Field: [0] RFEAPI +// +// Clear event EVT0.RFEAPI +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR0_RFEAPI 0x00000001U +#define LRFDRFE_EVTCLR0_RFEAPI_M 0x00000001U +#define LRFDRFE_EVTCLR0_RFEAPI_S 0U +#define LRFDRFE_EVTCLR0_RFEAPI_ONE 0x00000001U +#define LRFDRFE_EVTCLR0_RFEAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_EVTCLR1 +// +//***************************************************************************** +// Field: [13] PREREFCLK +// +// Clear event EVT1.PREREFCLK +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_PREREFCLK 0x00002000U +#define LRFDRFE_EVTCLR1_PREREFCLK_M 0x00002000U +#define LRFDRFE_EVTCLR1_PREREFCLK_S 13U +#define LRFDRFE_EVTCLR1_PREREFCLK_ONE 0x00002000U +#define LRFDRFE_EVTCLR1_PREREFCLK_ZERO 0x00000000U + +// Field: [12] REFCLK +// +// Clear event EVT1.REFCLK +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_REFCLK 0x00001000U +#define LRFDRFE_EVTCLR1_REFCLK_M 0x00001000U +#define LRFDRFE_EVTCLR1_REFCLK_S 12U +#define LRFDRFE_EVTCLR1_REFCLK_ONE 0x00001000U +#define LRFDRFE_EVTCLR1_REFCLK_ZERO 0x00000000U + +// Field: [11] FBLWTHR +// +// Clear event EVT1.FBLWTHR +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_FBLWTHR 0x00000800U +#define LRFDRFE_EVTCLR1_FBLWTHR_M 0x00000800U +#define LRFDRFE_EVTCLR1_FBLWTHR_S 11U +#define LRFDRFE_EVTCLR1_FBLWTHR_ONE 0x00000800U +#define LRFDRFE_EVTCLR1_FBLWTHR_ZERO 0x00000000U + +// Field: [10] FABVTHR +// +// Clear event EVT1.FABVTHR +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_FABVTHR 0x00000400U +#define LRFDRFE_EVTCLR1_FABVTHR_M 0x00000400U +#define LRFDRFE_EVTCLR1_FABVTHR_S 10U +#define LRFDRFE_EVTCLR1_FABVTHR_ONE 0x00000400U +#define LRFDRFE_EVTCLR1_FABVTHR_ZERO 0x00000000U + +// Field: [9] LOCK +// +// Clear event EVT1.LOCK +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_LOCK 0x00000200U +#define LRFDRFE_EVTCLR1_LOCK_M 0x00000200U +#define LRFDRFE_EVTCLR1_LOCK_S 9U +#define LRFDRFE_EVTCLR1_LOCK_ONE 0x00000200U +#define LRFDRFE_EVTCLR1_LOCK_ZERO 0x00000000U + +// Field: [8] LOL +// +// Clear event EVT1.LOL +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_LOL 0x00000100U +#define LRFDRFE_EVTCLR1_LOL_M 0x00000100U +#define LRFDRFE_EVTCLR1_LOL_S 8U +#define LRFDRFE_EVTCLR1_LOL_ONE 0x00000100U +#define LRFDRFE_EVTCLR1_LOL_ZERO 0x00000000U + +// Field: [7] GPI7 +// +// Clear event EVT1.GPI7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI7 0x00000080U +#define LRFDRFE_EVTCLR1_GPI7_M 0x00000080U +#define LRFDRFE_EVTCLR1_GPI7_S 7U +#define LRFDRFE_EVTCLR1_GPI7_ONE 0x00000080U +#define LRFDRFE_EVTCLR1_GPI7_ZERO 0x00000000U + +// Field: [6] GPI6 +// +// Clear event EVT1.GPI6 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI6 0x00000040U +#define LRFDRFE_EVTCLR1_GPI6_M 0x00000040U +#define LRFDRFE_EVTCLR1_GPI6_S 6U +#define LRFDRFE_EVTCLR1_GPI6_ONE 0x00000040U +#define LRFDRFE_EVTCLR1_GPI6_ZERO 0x00000000U + +// Field: [5] GPI5 +// +// Clear event EVT1.GPI5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI5 0x00000020U +#define LRFDRFE_EVTCLR1_GPI5_M 0x00000020U +#define LRFDRFE_EVTCLR1_GPI5_S 5U +#define LRFDRFE_EVTCLR1_GPI5_ONE 0x00000020U +#define LRFDRFE_EVTCLR1_GPI5_ZERO 0x00000000U + +// Field: [4] GPI4 +// +// Clear event EVT1.GPI4 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI4 0x00000010U +#define LRFDRFE_EVTCLR1_GPI4_M 0x00000010U +#define LRFDRFE_EVTCLR1_GPI4_S 4U +#define LRFDRFE_EVTCLR1_GPI4_ONE 0x00000010U +#define LRFDRFE_EVTCLR1_GPI4_ZERO 0x00000000U + +// Field: [3] GPI3 +// +// Clear event EVT1.GPI3 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI3 0x00000008U +#define LRFDRFE_EVTCLR1_GPI3_M 0x00000008U +#define LRFDRFE_EVTCLR1_GPI3_S 3U +#define LRFDRFE_EVTCLR1_GPI3_ONE 0x00000008U +#define LRFDRFE_EVTCLR1_GPI3_ZERO 0x00000000U + +// Field: [2] GPI2 +// +// Clear event EVT1.GPI2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI2 0x00000004U +#define LRFDRFE_EVTCLR1_GPI2_M 0x00000004U +#define LRFDRFE_EVTCLR1_GPI2_S 2U +#define LRFDRFE_EVTCLR1_GPI2_ONE 0x00000004U +#define LRFDRFE_EVTCLR1_GPI2_ZERO 0x00000000U + +// Field: [1] GPI1 +// +// Clear event EVT1.GPI1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI1 0x00000002U +#define LRFDRFE_EVTCLR1_GPI1_M 0x00000002U +#define LRFDRFE_EVTCLR1_GPI1_S 1U +#define LRFDRFE_EVTCLR1_GPI1_ONE 0x00000002U +#define LRFDRFE_EVTCLR1_GPI1_ZERO 0x00000000U + +// Field: [0] GPI0 +// +// Clear event EVT1.GPI0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_EVTCLR1_GPI0 0x00000001U +#define LRFDRFE_EVTCLR1_GPI0_M 0x00000001U +#define LRFDRFE_EVTCLR1_GPI0_S 0U +#define LRFDRFE_EVTCLR1_GPI0_ONE 0x00000001U +#define LRFDRFE_EVTCLR1_GPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_HFXTSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// HFXT RF qualification +// ENUMs: +// QUAL Clock signal is qualified +// NONQUAL Clock signal is not qualified +#define LRFDRFE_HFXTSTAT_STAT 0x00000001U +#define LRFDRFE_HFXTSTAT_STAT_M 0x00000001U +#define LRFDRFE_HFXTSTAT_STAT_S 0U +#define LRFDRFE_HFXTSTAT_STAT_QUAL 0x00000001U +#define LRFDRFE_HFXTSTAT_STAT_NONQUAL 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RFSTATE +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Radio Status +// ENUMs: +// RX RX is active +// TX TX is active +// SYNTH Synth is running +// IDLE Radio is idle +#define LRFDRFE_RFSTATE_VAL_W 4U +#define LRFDRFE_RFSTATE_VAL_M 0x0000000FU +#define LRFDRFE_RFSTATE_VAL_S 0U +#define LRFDRFE_RFSTATE_VAL_RX 0x00000003U +#define LRFDRFE_RFSTATE_VAL_TX 0x00000002U +#define LRFDRFE_RFSTATE_VAL_SYNTH 0x00000001U +#define LRFDRFE_RFSTATE_VAL_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_API +// +//***************************************************************************** +// Field: [7:4] PROTOCOLID +// +// Protocol ID +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_API_PROTOCOLID_W 4U +#define LRFDRFE_API_PROTOCOLID_M 0x000000F0U +#define LRFDRFE_API_PROTOCOLID_S 4U +#define LRFDRFE_API_PROTOCOLID_ALLONES 0x000000F0U +#define LRFDRFE_API_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [3:0] RFECMD +// +// RFE Command +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All bits are 0 +#define LRFDRFE_API_RFECMD_W 4U +#define LRFDRFE_API_RFECMD_M 0x0000000FU +#define LRFDRFE_API_RFECMD_S 0U +#define LRFDRFE_API_RFECMD_ALLONES 0x0000000FU +#define LRFDRFE_API_RFECMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CMDPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CMDPAR0_VAL_W 16U +#define LRFDRFE_CMDPAR0_VAL_M 0x0000FFFFU +#define LRFDRFE_CMDPAR0_VAL_S 0U +#define LRFDRFE_CMDPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_CMDPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CMDPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CMDPAR1_VAL_W 16U +#define LRFDRFE_CMDPAR1_VAL_M 0x0000FFFFU +#define LRFDRFE_CMDPAR1_VAL_S 0U +#define LRFDRFE_CMDPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_CMDPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MSGBOX +// +//***************************************************************************** +// Field: [7:0] VAL +// +// RFE status as responser to API execution. +// +// Field is readable to PBE in LRFDPBE:RFEMSGBOX. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MSGBOX_VAL_W 8U +#define LRFDRFE_MSGBOX_VAL_M 0x000000FFU +#define LRFDRFE_MSGBOX_VAL_S 0U +#define LRFDRFE_MSGBOX_VAL_ALLONES 0x000000FFU +#define LRFDRFE_MSGBOX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MCEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to MCE. +// +// Write VAL to send data to MCE. A write triggers an LRFDMDM:EVT0.RFEDAT event +// in MCE. MCE reads VAL in LRFDMDM:RFEDATIN0. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MCEDATOUT0_VAL_W 16U +#define LRFDRFE_MCEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDRFE_MCEDATOUT0_VAL_S 0U +#define LRFDRFE_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_MCEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MCEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from MCE. +// +// Read data that MCE writes to LRFDMDM:RFEDATAOUT0. A write to +// LRFDMDM:RFEDATAOUT0 sets EVT0.MDMRFEDAT event. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MCEDATIN0_VAL_W 16U +#define LRFDRFE_MCEDATIN0_VAL_M 0x0000FFFFU +#define LRFDRFE_MCEDATIN0_VAL_S 0U +#define LRFDRFE_MCEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_MCEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MCECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to the MCE. +// +// A write to this register tiggers LRFDMDM:EVT1.RFECMD MCE event, and the +// command becomes readable to MCE in LRFDMDM:RFECMDIN. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MCECMDOUT_VAL_W 4U +#define LRFDRFE_MCECMDOUT_VAL_M 0x0000000FU +#define LRFDRFE_MCECMDOUT_VAL_S 0U +#define LRFDRFE_MCECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDRFE_MCECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MCECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from MCE. +// +// MCE writes LRFDMDM:RFECMDOUT to send a command to RFE. This action sets +// EVT0.MDMCMD RFE event. RFE reads command from MCECMDIN. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MCECMDIN_VAL_W 4U +#define LRFDRFE_MCECMDIN_VAL_M 0x0000000FU +#define LRFDRFE_MCECMDIN_VAL_S 0U +#define LRFDRFE_MCECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDRFE_MCECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PBEDATOUT0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data to send to PBE. +// +// Write VAL to send data to PBE. A write triggers an LRFDPBE:EVT0.RFEDAT event +// in PBE. PBE reads VAL in LRFDPBE:RFEDATIN0. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PBEDATOUT0_VAL_W 16U +#define LRFDRFE_PBEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDRFE_PBEDATOUT0_VAL_S 0U +#define LRFDRFE_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_PBEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PBEDATIN0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Data received from PBE. +// +// Read data that PBE writes to LRFDPBE:RFEDATAOUT0. A write to +// LRFDPBE:RFEDATAOUT0 sets EVT0.PBERFEDAT event. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PBEDATIN0_VAL_W 16U +#define LRFDRFE_PBEDATIN0_VAL_M 0x0000FFFFU +#define LRFDRFE_PBEDATIN0_VAL_S 0U +#define LRFDRFE_PBEDATIN0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_PBEDATIN0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PBECMDOUT +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command to send to the PBE. +// +// A write to this register tiggers LRFDPBE:EVT0.RFECMD PBE event, and the +// command becomes readable to PBE in LRFDPBE:RFECMDIN. +// +// +// Command to send to the PBE. Writing to this register will trigger an event +// in the PBE, and the command value written here will be readable in +// LRFDPBE:RFECMDIN register. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PBECMDOUT_VAL_W 4U +#define LRFDRFE_PBECMDOUT_VAL_M 0x0000000FU +#define LRFDRFE_PBECMDOUT_VAL_S 0U +#define LRFDRFE_PBECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDRFE_PBECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PBECMDIN +// +//***************************************************************************** +// Field: [3:0] VAL +// +// Command received from PBE. +// +// PBE writes LRFDPBE:RFECMDOUT to send a command to RFE. This action sets +// EVT0.PBECMD RFE event. RFE reads command from PBECMDIN. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PBECMDIN_VAL_W 4U +#define LRFDRFE_PBECMDIN_VAL_M 0x0000000FU +#define LRFDRFE_PBECMDIN_VAL_S 0U +#define LRFDRFE_PBECMDIN_VAL_ALLONES 0x0000000FU +#define LRFDRFE_PBECMDIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_STRB +// +//***************************************************************************** +// Field: [7] S2RTRG +// +// LRFDS2R arm/trigger +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_S2RTRG 0x00000080U +#define LRFDRFE_STRB_S2RTRG_M 0x00000080U +#define LRFDRFE_STRB_S2RTRG_S 7U +#define LRFDRFE_STRB_S2RTRG_ONE 0x00000080U +#define LRFDRFE_STRB_S2RTRG_ZERO 0x00000000U + +// Field: [6] DMATRG +// +// DMA transfer trigger +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_DMATRG 0x00000040U +#define LRFDRFE_STRB_DMATRG_M 0x00000040U +#define LRFDRFE_STRB_DMATRG_S 6U +#define LRFDRFE_STRB_DMATRG_ONE 0x00000040U +#define LRFDRFE_STRB_DMATRG_ZERO 0x00000000U + +// Field: [5] SYSTCPT2 +// +// Systimer capture event 2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_SYSTCPT2 0x00000020U +#define LRFDRFE_STRB_SYSTCPT2_M 0x00000020U +#define LRFDRFE_STRB_SYSTCPT2_S 5U +#define LRFDRFE_STRB_SYSTCPT2_ONE 0x00000020U +#define LRFDRFE_STRB_SYSTCPT2_ZERO 0x00000000U + +// Field: [4] SYSTCPT1 +// +// Systimer capture event 1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_SYSTCPT1 0x00000010U +#define LRFDRFE_STRB_SYSTCPT1_M 0x00000010U +#define LRFDRFE_STRB_SYSTCPT1_S 4U +#define LRFDRFE_STRB_SYSTCPT1_ONE 0x00000010U +#define LRFDRFE_STRB_SYSTCPT1_ZERO 0x00000000U + +// Field: [3] SYSTCPT0 +// +// Systimer capture event 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_SYSTCPT0 0x00000008U +#define LRFDRFE_STRB_SYSTCPT0_M 0x00000008U +#define LRFDRFE_STRB_SYSTCPT0_S 3U +#define LRFDRFE_STRB_SYSTCPT0_ONE 0x00000008U +#define LRFDRFE_STRB_SYSTCPT0_ZERO 0x00000000U + +// Field: [2] EVT1 +// +// Event 1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_EVT1 0x00000004U +#define LRFDRFE_STRB_EVT1_M 0x00000004U +#define LRFDRFE_STRB_EVT1_S 2U +#define LRFDRFE_STRB_EVT1_ONE 0x00000004U +#define LRFDRFE_STRB_EVT1_ZERO 0x00000000U + +// Field: [1] EVT0 +// +// Event 0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_STRB_EVT0 0x00000002U +#define LRFDRFE_STRB_EVT0_M 0x00000002U +#define LRFDRFE_STRB_EVT0_S 1U +#define LRFDRFE_STRB_EVT0_ONE 0x00000002U +#define LRFDRFE_STRB_EVT0_ZERO 0x00000000U + +// Field: [0] CMDDONE +// +// Command done indication +// ENUMs: +// YES The bit is 1 +// NO The bit is 0 +#define LRFDRFE_STRB_CMDDONE 0x00000001U +#define LRFDRFE_STRB_CMDDONE_M 0x00000001U +#define LRFDRFE_STRB_CMDDONE_S 0U +#define LRFDRFE_STRB_CMDDONE_YES 0x00000001U +#define LRFDRFE_STRB_CMDDONE_NO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNTHRCFG +// +//***************************************************************************** +// Field: [1] SEL +// +// Selects what MAGNACC is used in the compare with the threshold in MAGNTHR. +// ENUMs: +// MAGNACC1 Use MAGNACC1 in the compare against the theshold +// in MANGTHR +// MAGNACC0 Use MAGNACC0 in the compare against the theshold +// in MANGTHR +#define LRFDRFE_MAGNTHRCFG_SEL 0x00000002U +#define LRFDRFE_MAGNTHRCFG_SEL_M 0x00000002U +#define LRFDRFE_MAGNTHRCFG_SEL_S 1U +#define LRFDRFE_MAGNTHRCFG_SEL_MAGNACC1 0x00000002U +#define LRFDRFE_MAGNTHRCFG_SEL_MAGNACC0 0x00000000U + +// Field: [0] CTL +// +// Controls automatic comparison of magnitude with threshold +// ENUMs: +// EN Enable automatic comparison of magntude with +// threshold (input of lin2log is driven by HW) +// DIS Disable automatic comparison with threshold (input +// of lin2log is driven by FW) +#define LRFDRFE_MAGNTHRCFG_CTL 0x00000001U +#define LRFDRFE_MAGNTHRCFG_CTL_M 0x00000001U +#define LRFDRFE_MAGNTHRCFG_CTL_S 0U +#define LRFDRFE_MAGNTHRCFG_CTL_EN 0x00000001U +#define LRFDRFE_MAGNTHRCFG_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNTHR +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Magnitude threshold value +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MAGNTHR_VAL_W 8U +#define LRFDRFE_MAGNTHR_VAL_M 0x000000FFU +#define LRFDRFE_MAGNTHR_VAL_S 0U +#define LRFDRFE_MAGNTHR_VAL_ALLONES 0x000000FFU +#define LRFDRFE_MAGNTHR_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RSSIOFFSET +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Offset to convert to dBm (unsigned). This is used by the RFE to adjust its +// RSSI calculations. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_RSSIOFFSET_VAL_W 8U +#define LRFDRFE_RSSIOFFSET_VAL_M 0x000000FFU +#define LRFDRFE_RSSIOFFSET_VAL_S 0U +#define LRFDRFE_RSSIOFFSET_VAL_ALLONES 0x000000FFU +#define LRFDRFE_RSSIOFFSET_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_GAINCTL +// +//***************************************************************************** +// Field: [3:2] BDE2DVGA +// +// DVGA settings for BDE2. +// +// The DVGA control for BDE2 is shared with the MCE in its +// LRFDMDM:DEMMISC3.BDE2DVGA field. +// Software should determine who uses them. Please note that if both processors +// attempt to control it, the resulting setting will be the two settings ORed +// together. +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDRFE_GAINCTL_BDE2DVGA_W 2U +#define LRFDRFE_GAINCTL_BDE2DVGA_M 0x0000000CU +#define LRFDRFE_GAINCTL_BDE2DVGA_S 2U +#define LRFDRFE_GAINCTL_BDE2DVGA_GAIN8 0x0000000CU +#define LRFDRFE_GAINCTL_BDE2DVGA_GAIN4 0x00000008U +#define LRFDRFE_GAINCTL_BDE2DVGA_GAIN2 0x00000004U +#define LRFDRFE_GAINCTL_BDE2DVGA_GAIN1 0x00000000U + +// Field: [1:0] BDE1DVGA +// +// DVGA settings for BDE1. +// +// The DVGA control for BDE1 is shared with the MCE in its +// LRFDMDM:DEMMISC3.BDE1DVGA field. +// Software should determine who uses them. Please note that if both processors +// attempt to control it, the resulting setting will be the two settings ORed +// together. +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDRFE_GAINCTL_BDE1DVGA_W 2U +#define LRFDRFE_GAINCTL_BDE1DVGA_M 0x00000003U +#define LRFDRFE_GAINCTL_BDE1DVGA_S 0U +#define LRFDRFE_GAINCTL_BDE1DVGA_GAIN8 0x00000003U +#define LRFDRFE_GAINCTL_BDE1DVGA_GAIN4 0x00000002U +#define LRFDRFE_GAINCTL_BDE1DVGA_GAIN2 0x00000001U +#define LRFDRFE_GAINCTL_BDE1DVGA_GAIN1 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNCTL0 +// +//***************************************************************************** +// Field: [12] PERMODE +// +// Measurement type +// ENUMs: +// PERIODIC Periodic mode +// ONESHOT One-shot mode +#define LRFDRFE_MAGNCTL0_PERMODE 0x00001000U +#define LRFDRFE_MAGNCTL0_PERMODE_M 0x00001000U +#define LRFDRFE_MAGNCTL0_PERMODE_S 12U +#define LRFDRFE_MAGNCTL0_PERMODE_PERIODIC 0x00001000U +#define LRFDRFE_MAGNCTL0_PERMODE_ONESHOT 0x00000000U + +// Field: [11:8] SCL +// +// Scaling factor +// +// Scaling factor = 1/2^(SCL). +// ENUMs: +// DIV256 1/256 +// DIV128 1/128 +// DIV64 1/64 +// DIV32 1/32 +// DIV16 1/16 +// DIV8 +// DIV4 +// DIV2 +// DIV1 1/1 (no scaling) +#define LRFDRFE_MAGNCTL0_SCL_W 4U +#define LRFDRFE_MAGNCTL0_SCL_M 0x00000F00U +#define LRFDRFE_MAGNCTL0_SCL_S 8U +#define LRFDRFE_MAGNCTL0_SCL_DIV256 0x00000800U +#define LRFDRFE_MAGNCTL0_SCL_DIV128 0x00000700U +#define LRFDRFE_MAGNCTL0_SCL_DIV64 0x00000600U +#define LRFDRFE_MAGNCTL0_SCL_DIV32 0x00000500U +#define LRFDRFE_MAGNCTL0_SCL_DIV16 0x00000400U +#define LRFDRFE_MAGNCTL0_SCL_DIV8 0x00000300U +#define LRFDRFE_MAGNCTL0_SCL_DIV4 0x00000200U +#define LRFDRFE_MAGNCTL0_SCL_DIV2 0x00000100U +#define LRFDRFE_MAGNCTL0_SCL_DIV1 0x00000000U + +// Field: [7:0] PER +// +// Accumulation period in incoming samples +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MAGNCTL0_PER_W 8U +#define LRFDRFE_MAGNCTL0_PER_M 0x000000FFU +#define LRFDRFE_MAGNCTL0_PER_S 0U +#define LRFDRFE_MAGNCTL0_PER_ALLONES 0x000000FFU +#define LRFDRFE_MAGNCTL0_PER_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNCTL1 +// +//***************************************************************************** +// Field: [12] PERMODE +// +// Measurement type +// ENUMs: +// PERIODIC Periodic mode +// ONESHOT One-shot mode +#define LRFDRFE_MAGNCTL1_PERMODE 0x00001000U +#define LRFDRFE_MAGNCTL1_PERMODE_M 0x00001000U +#define LRFDRFE_MAGNCTL1_PERMODE_S 12U +#define LRFDRFE_MAGNCTL1_PERMODE_PERIODIC 0x00001000U +#define LRFDRFE_MAGNCTL1_PERMODE_ONESHOT 0x00000000U + +// Field: [11:8] SCL +// +// Scaling factor +// +// Scaling factor = 1/2^(SCL). +// ENUMs: +// DIV256 1/256 +// DIV128 1/128 +// DIV64 1/64 +// DIV32 1/32 +// DIV16 1/16 +// DIV8 +// DIV4 +// DIV2 +// DIV1 1/1 (no scaling) +#define LRFDRFE_MAGNCTL1_SCL_W 4U +#define LRFDRFE_MAGNCTL1_SCL_M 0x00000F00U +#define LRFDRFE_MAGNCTL1_SCL_S 8U +#define LRFDRFE_MAGNCTL1_SCL_DIV256 0x00000800U +#define LRFDRFE_MAGNCTL1_SCL_DIV128 0x00000700U +#define LRFDRFE_MAGNCTL1_SCL_DIV64 0x00000600U +#define LRFDRFE_MAGNCTL1_SCL_DIV32 0x00000500U +#define LRFDRFE_MAGNCTL1_SCL_DIV16 0x00000400U +#define LRFDRFE_MAGNCTL1_SCL_DIV8 0x00000300U +#define LRFDRFE_MAGNCTL1_SCL_DIV4 0x00000200U +#define LRFDRFE_MAGNCTL1_SCL_DIV2 0x00000100U +#define LRFDRFE_MAGNCTL1_SCL_DIV1 0x00000000U + +// Field: [7:0] PER +// +// Accumulation period in incoming samples +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MAGNCTL1_PER_W 8U +#define LRFDRFE_MAGNCTL1_PER_M 0x000000FFU +#define LRFDRFE_MAGNCTL1_PER_S 0U +#define LRFDRFE_MAGNCTL1_PER_ALLONES 0x000000FFU +#define LRFDRFE_MAGNCTL1_PER_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE0_VAL_W 16U +#define LRFDRFE_SPARE0_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE0_VAL_S 0U +#define LRFDRFE_SPARE0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE1_VAL_W 16U +#define LRFDRFE_SPARE1_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE1_VAL_S 0U +#define LRFDRFE_SPARE1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE2 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE2_VAL_W 16U +#define LRFDRFE_SPARE2_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE2_VAL_S 0U +#define LRFDRFE_SPARE2_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE3 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE3_VAL_W 16U +#define LRFDRFE_SPARE3_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE3_VAL_S 0U +#define LRFDRFE_SPARE3_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE3_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE4 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE4_VAL_W 16U +#define LRFDRFE_SPARE4_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE4_VAL_S 0U +#define LRFDRFE_SPARE4_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE4_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_SPARE5 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Spare register for use by firmware +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_SPARE5_VAL_W 16U +#define LRFDRFE_SPARE5_VAL_M 0x0000FFFFU +#define LRFDRFE_SPARE5_VAL_S 0U +#define LRFDRFE_SPARE5_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_SPARE5_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_LNA +// +//***************************************************************************** +// Field: [15:8] SPARE +// +// Spare bits to analog reserved for future use +// ENUMs: +// EN Enable IFAMP +// DIS Disable IFAMP +#define LRFDRFE_LNA_SPARE_W 8U +#define LRFDRFE_LNA_SPARE_M 0x0000FF00U +#define LRFDRFE_LNA_SPARE_S 8U +#define LRFDRFE_LNA_SPARE_EN 0x00000100U +#define LRFDRFE_LNA_SPARE_DIS 0x00000000U + +// Field: [7:4] TRIM +// +// LNA trim +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_LNA_TRIM_W 4U +#define LRFDRFE_LNA_TRIM_M 0x000000F0U +#define LRFDRFE_LNA_TRIM_S 4U +#define LRFDRFE_LNA_TRIM_ONES 0x000000F0U +#define LRFDRFE_LNA_TRIM_ZEROS 0x00000000U + +// Field: [3] BIAS +// +// BIAS current selection +// ENUMs: +// INT IPTAT bias currents are from bias circuit inside +// LRF_FRONTEND +// BGAP IPTAT bias currents are from bandgap +#define LRFDRFE_LNA_BIAS 0x00000008U +#define LRFDRFE_LNA_BIAS_M 0x00000008U +#define LRFDRFE_LNA_BIAS_S 3U +#define LRFDRFE_LNA_BIAS_INT 0x00000008U +#define LRFDRFE_LNA_BIAS_BGAP 0x00000000U + +// Field: [2:1] IB +// +// LNA bias current control +// +// IB is trimmed at probe. Default is 1. +// ENUMs: +// MAX Maximum IB +// MIN Minimum IB +#define LRFDRFE_LNA_IB_W 2U +#define LRFDRFE_LNA_IB_M 0x00000006U +#define LRFDRFE_LNA_IB_S 1U +#define LRFDRFE_LNA_IB_MAX 0x00000006U +#define LRFDRFE_LNA_IB_MIN 0x00000000U + +// Field: [0] EN +// +// LNA enable +// ENUMs: +// ON Enable LNA +// OFF Disable LNA +#define LRFDRFE_LNA_EN 0x00000001U +#define LRFDRFE_LNA_EN_M 0x00000001U +#define LRFDRFE_LNA_EN_S 0U +#define LRFDRFE_LNA_EN_ON 0x00000001U +#define LRFDRFE_LNA_EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFAMPRFLDO +// +//***************************************************************************** +// Field: [15:9] TRIM +// +// RFLDO output voltage trim +// +// Default value: 84 (1.3V), 127 = Bypass. +// ENUMs: +// BYPASS Regulator is in bypass mode +// MAX Maximum output voltage +// MIN Minimum output voltage +#define LRFDRFE_IFAMPRFLDO_TRIM_W 7U +#define LRFDRFE_IFAMPRFLDO_TRIM_M 0x0000FE00U +#define LRFDRFE_IFAMPRFLDO_TRIM_S 9U +#define LRFDRFE_IFAMPRFLDO_TRIM_BYPASS 0x0000FE00U +#define LRFDRFE_IFAMPRFLDO_TRIM_MAX 0x0000FC00U +#define LRFDRFE_IFAMPRFLDO_TRIM_MIN 0x00000000U + +// Field: [8] EN +// +// Regulator enable +// ENUMs: +// EN Enable regulator +// DIS Disable regulator +#define LRFDRFE_IFAMPRFLDO_EN 0x00000100U +#define LRFDRFE_IFAMPRFLDO_EN_M 0x00000100U +#define LRFDRFE_IFAMPRFLDO_EN_S 8U +#define LRFDRFE_IFAMPRFLDO_EN_EN 0x00000100U +#define LRFDRFE_IFAMPRFLDO_EN_DIS 0x00000000U + +// Field: [7:4] AAFCAP +// +// AAF capacitor control +// ENUMs: +// MAX Largest capacitance on IFAMP output. Low BW +// MIN Smallest capacitance on IFAMP output. High BW. +#define LRFDRFE_IFAMPRFLDO_AAFCAP_W 4U +#define LRFDRFE_IFAMPRFLDO_AAFCAP_M 0x000000F0U +#define LRFDRFE_IFAMPRFLDO_AAFCAP_S 4U +#define LRFDRFE_IFAMPRFLDO_AAFCAP_MAX 0x000000F0U +#define LRFDRFE_IFAMPRFLDO_AAFCAP_MIN 0x00000000U + +// Field: [3:1] IFAMPIB +// +// IFAMP bias current control +// +// Default is 2. +// ENUMs: +// MAX Max IB +// MIN Minimum IB +#define LRFDRFE_IFAMPRFLDO_IFAMPIB_W 3U +#define LRFDRFE_IFAMPRFLDO_IFAMPIB_M 0x0000000EU +#define LRFDRFE_IFAMPRFLDO_IFAMPIB_S 1U +#define LRFDRFE_IFAMPRFLDO_IFAMPIB_MAX 0x0000000EU +#define LRFDRFE_IFAMPRFLDO_IFAMPIB_MIN 0x00000000U + +// Field: [0] IFAMP +// +// IFAMP enable +// ENUMs: +// EN Enable IFAMP +// DIS Disable IFAMP +#define LRFDRFE_IFAMPRFLDO_IFAMP 0x00000001U +#define LRFDRFE_IFAMPRFLDO_IFAMP_M 0x00000001U +#define LRFDRFE_IFAMPRFLDO_IFAMP_S 0U +#define LRFDRFE_IFAMPRFLDO_IFAMP_EN 0x00000001U +#define LRFDRFE_IFAMPRFLDO_IFAMP_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PA0 +// +//***************************************************************************** +// Field: [15] SPARE15 +// +// Reserved +// ENUMs: +// ONE Bit is one +// ZERO Bit is 0 +#define LRFDRFE_PA0_SPARE15 0x00008000U +#define LRFDRFE_PA0_SPARE15_M 0x00008000U +#define LRFDRFE_PA0_SPARE15_S 15U +#define LRFDRFE_PA0_SPARE15_ONE 0x00008000U +#define LRFDRFE_PA0_SPARE15_ZERO 0x00000000U + +// Field: [14] MODE +// +// PA power mode +// ENUMs: +// HIGH High power mode, max 8 dBm +// LOW Low power mode, max 3 dBm +#define LRFDRFE_PA0_MODE 0x00004000U +#define LRFDRFE_PA0_MODE_M 0x00004000U +#define LRFDRFE_PA0_MODE_S 14U +#define LRFDRFE_PA0_MODE_HIGH 0x00004000U +#define LRFDRFE_PA0_MODE_LOW 0x00000000U + +// Field: [13:11] GAIN +// +// Gain control in 8dBm PA 1st stage +// ENUMs: +// MAX Maximum gain +// MIN Minimum gain +#define LRFDRFE_PA0_GAIN_W 3U +#define LRFDRFE_PA0_GAIN_M 0x00003800U +#define LRFDRFE_PA0_GAIN_S 11U +#define LRFDRFE_PA0_GAIN_MAX 0x00003800U +#define LRFDRFE_PA0_GAIN_MIN 0x00000000U + +// Field: [10:5] IB +// +// PA power control +// ENUMs: +// MAX Maximum output power +// MIN Minimum output power +#define LRFDRFE_PA0_IB_W 6U +#define LRFDRFE_PA0_IB_M 0x000007E0U +#define LRFDRFE_PA0_IB_S 5U +#define LRFDRFE_PA0_IB_MAX 0x000007E0U +#define LRFDRFE_PA0_IB_MIN 0x00000000U + +// Field: [4:0] TRIM +// +// Bias Current Trim +// +// Setting shall provide constant output power over process and temperature. +// Current changes linearily with setting. +// +// Default value: 16 +// ENUMs: +// MAX Maximum bias current +// MIN Minimum bias current +#define LRFDRFE_PA0_TRIM_W 5U +#define LRFDRFE_PA0_TRIM_M 0x0000001FU +#define LRFDRFE_PA0_TRIM_S 0U +#define LRFDRFE_PA0_TRIM_MAX 0x0000001FU +#define LRFDRFE_PA0_TRIM_MIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PA1 +// +//***************************************************************************** +// Field: [15:7] SPARE +// +// Spare bits to analog, reserved for future use. +// ENUMs: +// MAX Longest ramp time +// MIN Shortest ramp time +#define LRFDRFE_PA1_SPARE_W 9U +#define LRFDRFE_PA1_SPARE_M 0x0000FF80U +#define LRFDRFE_PA1_SPARE_S 7U +#define LRFDRFE_PA1_SPARE_MAX 0x00000180U +#define LRFDRFE_PA1_SPARE_MIN 0x00000000U + +// Field: [6] MIXATST +// +// Control of mixer outputs through ATEST +// ENUMs: +// EN Mixers are available on ATEST +// DIS Mixers are not available on ATEST +#define LRFDRFE_PA1_MIXATST 0x00000040U +#define LRFDRFE_PA1_MIXATST_M 0x00000040U +#define LRFDRFE_PA1_MIXATST_S 6U +#define LRFDRFE_PA1_MIXATST_EN 0x00000040U +#define LRFDRFE_PA1_MIXATST_DIS 0x00000000U + +// Field: [5] LDOITST +// +// Control of current test signal through ITEST +// ENUMs: +// EN Current test signal is available through ITEST +// DIS Current test signal not available through ITEST +#define LRFDRFE_PA1_LDOITST 0x00000020U +#define LRFDRFE_PA1_LDOITST_M 0x00000020U +#define LRFDRFE_PA1_LDOITST_S 5U +#define LRFDRFE_PA1_LDOITST_EN 0x00000020U +#define LRFDRFE_PA1_LDOITST_DIS 0x00000000U + +// Field: [4] LDOATST +// +// Control of LDO output voltage through ATEST +// ENUMs: +// EN LDO output voltage is available through ATEST +// DIS LDO output voltage not available through ATEST +#define LRFDRFE_PA1_LDOATST 0x00000010U +#define LRFDRFE_PA1_LDOATST_M 0x00000010U +#define LRFDRFE_PA1_LDOATST_S 4U +#define LRFDRFE_PA1_LDOATST_EN 0x00000010U +#define LRFDRFE_PA1_LDOATST_DIS 0x00000000U + +// Field: [3:2] RC +// +// Adjustment of on/off PA ramp time. +// ENUMs: +// MAX Longest ramp time +// MIN Shortest ramp time +#define LRFDRFE_PA1_RC_W 2U +#define LRFDRFE_PA1_RC_M 0x0000000CU +#define LRFDRFE_PA1_RC_S 2U +#define LRFDRFE_PA1_RC_MAX 0x0000000CU +#define LRFDRFE_PA1_RC_MIN 0x00000000U + +// Field: [1] RAMP +// +// PA RAMP control +// +// Field can be set together with EN to ramp PA on. +// Field must be cleared before EN to ramp PA down. +// ENUMs: +// UP Ramp up +// DOWN Ramp down +#define LRFDRFE_PA1_RAMP 0x00000002U +#define LRFDRFE_PA1_RAMP_M 0x00000002U +#define LRFDRFE_PA1_RAMP_S 1U +#define LRFDRFE_PA1_RAMP_UP 0x00000002U +#define LRFDRFE_PA1_RAMP_DOWN 0x00000000U + +// Field: [0] EN +// +// PA enable +// ENUMs: +// EN Enable PA +// DIS Disable PA +#define LRFDRFE_PA1_EN 0x00000001U +#define LRFDRFE_PA1_EN_M 0x00000001U +#define LRFDRFE_PA1_EN_S 0U +#define LRFDRFE_PA1_EN_EN 0x00000001U +#define LRFDRFE_PA1_EN_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_ULNA +// +//***************************************************************************** +// Field: [15:0] SPARE +// +// Reserved for future use +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_ULNA_SPARE_W 16U +#define LRFDRFE_ULNA_SPARE_M 0x0000FFFFU +#define LRFDRFE_ULNA_SPARE_S 0U +#define LRFDRFE_ULNA_SPARE_ALLONES 0x0000FFFFU +#define LRFDRFE_ULNA_SPARE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADC0 +// +//***************************************************************************** +// Field: [15] EXTCLK +// +// IFADC external clock control +// +// IFADC can use external clock from pad. +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_IFADC0_EXTCLK 0x00008000U +#define LRFDRFE_IFADC0_EXTCLK_M 0x00008000U +#define LRFDRFE_IFADC0_EXTCLK_S 15U +#define LRFDRFE_IFADC0_EXTCLK_EN 0x00008000U +#define LRFDRFE_IFADC0_EXTCLK_DIS 0x00000000U + +// Field: [14:12] DITHERTRIM +// +// Dither current trim +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADC0_DITHERTRIM_W 3U +#define LRFDRFE_IFADC0_DITHERTRIM_M 0x00007000U +#define LRFDRFE_IFADC0_DITHERTRIM_S 12U +#define LRFDRFE_IFADC0_DITHERTRIM_ONES 0x00007000U +#define LRFDRFE_IFADC0_DITHERTRIM_ZEROS 0x00000000U + +// Field: [11:10] DITHEREN +// +// Dither control +// +// Enable a random noise generator to inject weak pseudo random noise into the +// ADC loop to randomize and smooth out possible idle tones. +// NOTE: This field may only change during DTC-reset or while the clock is +// inactive! +// ENUMs: +// ENG All the bits are 1 +// ENSD All the bits are 1 +// ENS All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE_IFADC0_DITHEREN_W 2U +#define LRFDRFE_IFADC0_DITHEREN_M 0x00000C00U +#define LRFDRFE_IFADC0_DITHEREN_S 10U +#define LRFDRFE_IFADC0_DITHEREN_ENG 0x00000C00U +#define LRFDRFE_IFADC0_DITHEREN_ENSD 0x00000800U +#define LRFDRFE_IFADC0_DITHEREN_ENS 0x00000400U +#define LRFDRFE_IFADC0_DITHEREN_DIS 0x00000000U + +// Field: [9] ADCIEN +// +// I modulator control +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_IFADC0_ADCIEN 0x00000200U +#define LRFDRFE_IFADC0_ADCIEN_M 0x00000200U +#define LRFDRFE_IFADC0_ADCIEN_S 9U +#define LRFDRFE_IFADC0_ADCIEN_EN 0x00000200U +#define LRFDRFE_IFADC0_ADCIEN_DIS 0x00000000U + +// Field: [8] ADCQEN +// +// Q modulator control +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE_IFADC0_ADCQEN 0x00000100U +#define LRFDRFE_IFADC0_ADCQEN_M 0x00000100U +#define LRFDRFE_IFADC0_ADCQEN_S 8U +#define LRFDRFE_IFADC0_ADCQEN_EN 0x00000100U +#define LRFDRFE_IFADC0_ADCQEN_DIS 0x00000000U + +// Field: [7:4] INT2ADJ +// +// GM trim +// +// Trims the gm cell for the second integrator. Larger value means lower gm. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADC0_INT2ADJ_W 4U +#define LRFDRFE_IFADC0_INT2ADJ_M 0x000000F0U +#define LRFDRFE_IFADC0_INT2ADJ_S 4U +#define LRFDRFE_IFADC0_INT2ADJ_ONES 0x000000F0U +#define LRFDRFE_IFADC0_INT2ADJ_ZEROS 0x00000000U + +// Field: [3:2] AAFCAP +// +// AAF bandwidth trim +// ENUMs: +// ENG All the bits are 1 +// ENSD All the bits are 1 +// ENS All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE_IFADC0_AAFCAP_W 2U +#define LRFDRFE_IFADC0_AAFCAP_M 0x0000000CU +#define LRFDRFE_IFADC0_AAFCAP_S 2U +#define LRFDRFE_IFADC0_AAFCAP_ENG 0x0000000CU +#define LRFDRFE_IFADC0_AAFCAP_ENSD 0x00000008U +#define LRFDRFE_IFADC0_AAFCAP_ENS 0x00000004U +#define LRFDRFE_IFADC0_AAFCAP_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADC1 +// +//***************************************************************************** +// Field: [15] NRZ +// +// Internal feedback DAC mode +// ENUMs: +// EN The feedback DAC uses NRZ mode. (Default) +// DIS The feedback DAC uses RZ mode +#define LRFDRFE_IFADC1_NRZ 0x00008000U +#define LRFDRFE_IFADC1_NRZ_M 0x00008000U +#define LRFDRFE_IFADC1_NRZ_S 15U +#define LRFDRFE_IFADC1_NRZ_EN 0x00008000U +#define LRFDRFE_IFADC1_NRZ_DIS 0x00000000U + +// Field: [14:9] TRIM +// +// Feedback DAC trim +// +// Larger trim means larger current. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADC1_TRIM_W 6U +#define LRFDRFE_IFADC1_TRIM_M 0x00007E00U +#define LRFDRFE_IFADC1_TRIM_S 9U +#define LRFDRFE_IFADC1_TRIM_ONES 0x00007E00U +#define LRFDRFE_IFADC1_TRIM_ZEROS 0x00000000U + +// Field: [7] RSTN +// +// IFADC DTC reset +// ENUMs: +// DIS DTCs are not reset +// EN DTCs are reset +#define LRFDRFE_IFADC1_RSTN 0x00000080U +#define LRFDRFE_IFADC1_RSTN_M 0x00000080U +#define LRFDRFE_IFADC1_RSTN_S 7U +#define LRFDRFE_IFADC1_RSTN_DIS 0x00000080U +#define LRFDRFE_IFADC1_RSTN_EN 0x00000000U + +// Field: [6] CLKGEN +// +// IFADC clock generator +// ENUMs: +// EN Internal clock generator module is enabled +// DIS Internal clock generator module is disabled +#define LRFDRFE_IFADC1_CLKGEN 0x00000040U +#define LRFDRFE_IFADC1_CLKGEN_M 0x00000040U +#define LRFDRFE_IFADC1_CLKGEN_S 6U +#define LRFDRFE_IFADC1_CLKGEN_EN 0x00000040U +#define LRFDRFE_IFADC1_CLKGEN_DIS 0x00000000U + +// Field: [5] ADCDIGCLK +// +// IFADC clock to decimator +// ENUMs: +// EN Clock to decimator enabled +// DIS Clock to decimator disabled +#define LRFDRFE_IFADC1_ADCDIGCLK 0x00000020U +#define LRFDRFE_IFADC1_ADCDIGCLK_M 0x00000020U +#define LRFDRFE_IFADC1_ADCDIGCLK_S 5U +#define LRFDRFE_IFADC1_ADCDIGCLK_EN 0x00000020U +#define LRFDRFE_IFADC1_ADCDIGCLK_DIS 0x00000000U + +// Field: [4] ADCLFSROUT +// +// ADC test mode +// ENUMs: +// EN The LFSR test output is connected to the ADC +// output +// DIS The quantizer output is connected to the ADC +// output +#define LRFDRFE_IFADC1_ADCLFSROUT 0x00000010U +#define LRFDRFE_IFADC1_ADCLFSROUT_M 0x00000010U +#define LRFDRFE_IFADC1_ADCLFSROUT_S 4U +#define LRFDRFE_IFADC1_ADCLFSROUT_EN 0x00000010U +#define LRFDRFE_IFADC1_ADCLFSROUT_DIS 0x00000000U + +// Field: [3:1] LPFTSTMODE +// +// Currently not in use. For future test mode implementations. +// ENUMs: +// EN All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE_IFADC1_LPFTSTMODE_W 3U +#define LRFDRFE_IFADC1_LPFTSTMODE_M 0x0000000EU +#define LRFDRFE_IFADC1_LPFTSTMODE_S 1U +#define LRFDRFE_IFADC1_LPFTSTMODE_EN 0x00000002U +#define LRFDRFE_IFADC1_LPFTSTMODE_DIS 0x00000000U + +// Field: [0] INVCLKOUT +// +// Control phase inversion of IFADC clock output +// ENUMs: +// EN Invert IFADC output clock phase (default) +// DIS Keep default IFADC output clock phase +#define LRFDRFE_IFADC1_INVCLKOUT 0x00000001U +#define LRFDRFE_IFADC1_INVCLKOUT_M 0x00000001U +#define LRFDRFE_IFADC1_INVCLKOUT_S 0U +#define LRFDRFE_IFADC1_INVCLKOUT_EN 0x00000001U +#define LRFDRFE_IFADC1_INVCLKOUT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCLF +// +//***************************************************************************** +// Field: [15:12] FF3 +// +// GM trim for the third feedforward cell +// +// Larger trim means lower gm. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCLF_FF3_W 4U +#define LRFDRFE_IFADCLF_FF3_M 0x0000F000U +#define LRFDRFE_IFADCLF_FF3_S 12U +#define LRFDRFE_IFADCLF_FF3_ONES 0x0000F000U +#define LRFDRFE_IFADCLF_FF3_ZEROS 0x00000000U + +// Field: [11:8] FF2 +// +// GM trim for the second feedforward cell +// +// Larger trim means lower gm. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCLF_FF2_W 4U +#define LRFDRFE_IFADCLF_FF2_M 0x00000F00U +#define LRFDRFE_IFADCLF_FF2_S 8U +#define LRFDRFE_IFADCLF_FF2_ONES 0x00000F00U +#define LRFDRFE_IFADCLF_FF2_ZEROS 0x00000000U + +// Field: [7:4] FF1 +// +// GM trim for the first feedforward cell +// +// Larger trim means lower gm. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCLF_FF1_W 4U +#define LRFDRFE_IFADCLF_FF1_M 0x000000F0U +#define LRFDRFE_IFADCLF_FF1_S 4U +#define LRFDRFE_IFADCLF_FF1_ONES 0x000000F0U +#define LRFDRFE_IFADCLF_FF1_ZEROS 0x00000000U + +// Field: [3:0] INT3 +// +// GM trim for the third integrator +// +// Larger trim means lower gm. +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCLF_INT3_W 4U +#define LRFDRFE_IFADCLF_INT3_M 0x0000000FU +#define LRFDRFE_IFADCLF_INT3_S 0U +#define LRFDRFE_IFADCLF_INT3_ONES 0x0000000FU +#define LRFDRFE_IFADCLF_INT3_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCQUANT +// +//***************************************************************************** +// Field: [15:14] CLKDLYTRIM +// +// Currently not in use. 2 bit signal to program the clock delay in the clock +// generator circuit. +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE_IFADCQUANT_CLKDLYTRIM_W 2U +#define LRFDRFE_IFADCQUANT_CLKDLYTRIM_M 0x0000C000U +#define LRFDRFE_IFADCQUANT_CLKDLYTRIM_S 14U +#define LRFDRFE_IFADCQUANT_CLKDLYTRIM_ONES 0x0000C000U +#define LRFDRFE_IFADCQUANT_CLKDLYTRIM_ZEROS 0x00000000U + +// Field: [13:9] DBGCALVALIN +// +// Input test calibration value to quantizer calibration block, used in debug +// mode. +// ENUMs: +// ONES All the bits are ONES +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCQUANT_DBGCALVALIN_W 5U +#define LRFDRFE_IFADCQUANT_DBGCALVALIN_M 0x00003E00U +#define LRFDRFE_IFADCQUANT_DBGCALVALIN_S 9U +#define LRFDRFE_IFADCQUANT_DBGCALVALIN_ONES 0x00003E00U +#define LRFDRFE_IFADCQUANT_DBGCALVALIN_ZEROS 0x00000000U + +// Field: [8] DBGCALLEG +// +// Select which leg to observe in calibration debug mode +// ENUMs: +// NEG Negative leg +// POS Positive leg +#define LRFDRFE_IFADCQUANT_DBGCALLEG 0x00000100U +#define LRFDRFE_IFADCQUANT_DBGCALLEG_M 0x00000100U +#define LRFDRFE_IFADCQUANT_DBGCALLEG_S 8U +#define LRFDRFE_IFADCQUANT_DBGCALLEG_NEG 0x00000100U +#define LRFDRFE_IFADCQUANT_DBGCALLEG_POS 0x00000000U + +// Field: [7:6] DBGCALMQ +// +// Quantizer calibration mode for Q modulator +// +// This signal should have a large stability window, and is for internal use +// only! +// ENUMs: +// DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode. +// DBGCAL_QMODP Enable quantizer calibration mode for Positive +// comparator in Q modulator. +// DBGCAL_QMODN Enable quantizer calibration mode for Negative +// comparator in Q modulator. +// DBGCAL_QMODZ Disable quantizer calibration mode.(Default) +#define LRFDRFE_IFADCQUANT_DBGCALMQ_W 2U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_M 0x000000C0U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_S 6U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODB 0x000000C0U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODP 0x00000080U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODN 0x00000040U +#define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODZ 0x00000000U + +// Field: [5:4] DBGCALMI +// +// Quantizer calibration mode for I modulator. +// +// This signal should have a large stability window, and is for internal use +// only! +// ENUMs: +// DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode. +// DBGCAL_IMODP Enable quantizer calibration mode for Positive +// comparator in I modulator. +// DBGCAL_IMODN Enable quantizer calibration mode for Negative +// comparator in I modulator. +// DBGCAL_IMODZ Disable quantizer calibration mode.(Default) +#define LRFDRFE_IFADCQUANT_DBGCALMI_W 2U +#define LRFDRFE_IFADCQUANT_DBGCALMI_M 0x00000030U +#define LRFDRFE_IFADCQUANT_DBGCALMI_S 4U +#define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODB 0x00000030U +#define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODP 0x00000020U +#define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODN 0x00000010U +#define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODZ 0x00000000U + +// Field: [3] AUTOCAL +// +// Auto calibration +// ENUMs: +// EN Enable the auto calibration logic (Default) +// DIS Disable the auto calibration logic +#define LRFDRFE_IFADCQUANT_AUTOCAL 0x00000008U +#define LRFDRFE_IFADCQUANT_AUTOCAL_M 0x00000008U +#define LRFDRFE_IFADCQUANT_AUTOCAL_S 3U +#define LRFDRFE_IFADCQUANT_AUTOCAL_EN 0x00000008U +#define LRFDRFE_IFADCQUANT_AUTOCAL_DIS 0x00000000U + +// Field: [2:0] QUANTTHR +// +// Quantizer treshold voltage trim +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE_IFADCQUANT_QUANTTHR_W 3U +#define LRFDRFE_IFADCQUANT_QUANTTHR_M 0x00000007U +#define LRFDRFE_IFADCQUANT_QUANTTHR_S 0U +#define LRFDRFE_IFADCQUANT_QUANTTHR_ONES 0x00000007U +#define LRFDRFE_IFADCQUANT_QUANTTHR_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCALDO +// +//***************************************************************************** +// Field: [15] ATESTVSSANA +// +// Connect VSSANA to atest +// ENUMs: +// EN Connected +// DIS Not connected +#define LRFDRFE_IFADCALDO_ATESTVSSANA 0x00008000U +#define LRFDRFE_IFADCALDO_ATESTVSSANA_M 0x00008000U +#define LRFDRFE_IFADCALDO_ATESTVSSANA_S 15U +#define LRFDRFE_IFADCALDO_ATESTVSSANA_EN 0x00008000U +#define LRFDRFE_IFADCALDO_ATESTVSSANA_DIS 0x00000000U + +// Field: [13:8] TRIMOUT +// +// Select which leg to observe in calibration debug mode +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE_IFADCALDO_TRIMOUT_W 6U +#define LRFDRFE_IFADCALDO_TRIMOUT_M 0x00003F00U +#define LRFDRFE_IFADCALDO_TRIMOUT_S 8U +#define LRFDRFE_IFADCALDO_TRIMOUT_ONES 0x00003F00U +#define LRFDRFE_IFADCALDO_TRIMOUT_ZEROS 0x00000000U + +// Field: [7] DUMMY +// +// Enable dummy load to improve performance for low load currents +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_DUMMY 0x00000080U +#define LRFDRFE_IFADCALDO_DUMMY_M 0x00000080U +#define LRFDRFE_IFADCALDO_DUMMY_S 7U +#define LRFDRFE_IFADCALDO_DUMMY_EN 0x00000080U +#define LRFDRFE_IFADCALDO_DUMMY_DIS 0x00000000U + +// Field: [6] ATESTOUT +// +// Connect LDO output voltage to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_ATESTOUT 0x00000040U +#define LRFDRFE_IFADCALDO_ATESTOUT_M 0x00000040U +#define LRFDRFE_IFADCALDO_ATESTOUT_S 6U +#define LRFDRFE_IFADCALDO_ATESTOUT_EN 0x00000040U +#define LRFDRFE_IFADCALDO_ATESTOUT_DIS 0x00000000U + +// Field: [5] ATSTLDOFB +// +// Connect LDO feedback to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_ATSTLDOFB 0x00000020U +#define LRFDRFE_IFADCALDO_ATSTLDOFB_M 0x00000020U +#define LRFDRFE_IFADCALDO_ATSTLDOFB_S 5U +#define LRFDRFE_IFADCALDO_ATSTLDOFB_EN 0x00000020U +#define LRFDRFE_IFADCALDO_ATSTLDOFB_DIS 0x00000000U + +// Field: [4] ATESTERRAMP +// +// Connect the error amplifier output to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_ATESTERRAMP 0x00000010U +#define LRFDRFE_IFADCALDO_ATESTERRAMP_M 0x00000010U +#define LRFDRFE_IFADCALDO_ATESTERRAMP_S 4U +#define LRFDRFE_IFADCALDO_ATESTERRAMP_EN 0x00000010U +#define LRFDRFE_IFADCALDO_ATESTERRAMP_DIS 0x00000000U + +// Field: [3] ITEST +// +// Connect test current to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_ITEST 0x00000008U +#define LRFDRFE_IFADCALDO_ITEST_M 0x00000008U +#define LRFDRFE_IFADCALDO_ITEST_S 3U +#define LRFDRFE_IFADCALDO_ITEST_EN 0x00000008U +#define LRFDRFE_IFADCALDO_ITEST_DIS 0x00000000U + +// Field: [2] BYPASS +// +// Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled +// to use bypass. +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_BYPASS 0x00000004U +#define LRFDRFE_IFADCALDO_BYPASS_M 0x00000004U +#define LRFDRFE_IFADCALDO_BYPASS_S 2U +#define LRFDRFE_IFADCALDO_BYPASS_EN 0x00000004U +#define LRFDRFE_IFADCALDO_BYPASS_DIS 0x00000000U + +// Field: [1] CLAMP +// +// Clamp the LDO output with diodes to ground +// +// Not used by analog when CTL or BYPASS are set. +// ENUMs: +// EN Enabled +// DIS Disabled. The LDO output is shorted to ground when +// disabled. +#define LRFDRFE_IFADCALDO_CLAMP 0x00000002U +#define LRFDRFE_IFADCALDO_CLAMP_M 0x00000002U +#define LRFDRFE_IFADCALDO_CLAMP_S 1U +#define LRFDRFE_IFADCALDO_CLAMP_EN 0x00000002U +#define LRFDRFE_IFADCALDO_CLAMP_DIS 0x00000000U + +// Field: [0] CTL +// +// Enable regulator for supplying analog domain of the adc +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCALDO_CTL 0x00000001U +#define LRFDRFE_IFADCALDO_CTL_M 0x00000001U +#define LRFDRFE_IFADCALDO_CTL_S 0U +#define LRFDRFE_IFADCALDO_CTL_EN 0x00000001U +#define LRFDRFE_IFADCALDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCDLDO +// +//***************************************************************************** +// Field: [13:8] TRIMOUT +// +// Select which leg to observe in calibration debug mode +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE_IFADCDLDO_TRIMOUT_W 6U +#define LRFDRFE_IFADCDLDO_TRIMOUT_M 0x00003F00U +#define LRFDRFE_IFADCDLDO_TRIMOUT_S 8U +#define LRFDRFE_IFADCDLDO_TRIMOUT_ONES 0x00003F00U +#define LRFDRFE_IFADCDLDO_TRIMOUT_ZEROS 0x00000000U + +// Field: [7] DUMMY +// +// Enable dummy load to improve performance for low load currents +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_DUMMY 0x00000080U +#define LRFDRFE_IFADCDLDO_DUMMY_M 0x00000080U +#define LRFDRFE_IFADCDLDO_DUMMY_S 7U +#define LRFDRFE_IFADCDLDO_DUMMY_EN 0x00000080U +#define LRFDRFE_IFADCDLDO_DUMMY_DIS 0x00000000U + +// Field: [6] ATESTOUT +// +// Connect LDO output voltage to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_ATESTOUT 0x00000040U +#define LRFDRFE_IFADCDLDO_ATESTOUT_M 0x00000040U +#define LRFDRFE_IFADCDLDO_ATESTOUT_S 6U +#define LRFDRFE_IFADCDLDO_ATESTOUT_EN 0x00000040U +#define LRFDRFE_IFADCDLDO_ATESTOUT_DIS 0x00000000U + +// Field: [5] ATSTBGP +// +// Connect bandgap voltage to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_ATSTBGP 0x00000020U +#define LRFDRFE_IFADCDLDO_ATSTBGP_M 0x00000020U +#define LRFDRFE_IFADCDLDO_ATSTBGP_S 5U +#define LRFDRFE_IFADCDLDO_ATSTBGP_EN 0x00000020U +#define LRFDRFE_IFADCDLDO_ATSTBGP_DIS 0x00000000U + +// Field: [4] ATESTERRAMP +// +// Connect the error amplifier output to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_ATESTERRAMP 0x00000010U +#define LRFDRFE_IFADCDLDO_ATESTERRAMP_M 0x00000010U +#define LRFDRFE_IFADCDLDO_ATESTERRAMP_S 4U +#define LRFDRFE_IFADCDLDO_ATESTERRAMP_EN 0x00000010U +#define LRFDRFE_IFADCDLDO_ATESTERRAMP_DIS 0x00000000U + +// Field: [3] ITEST +// +// Connect test current to ATEST +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_ITEST 0x00000008U +#define LRFDRFE_IFADCDLDO_ITEST_M 0x00000008U +#define LRFDRFE_IFADCDLDO_ITEST_S 3U +#define LRFDRFE_IFADCDLDO_ITEST_EN 0x00000008U +#define LRFDRFE_IFADCDLDO_ITEST_DIS 0x00000000U + +// Field: [2] BYPASS +// +// Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled +// to use bypass. +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_BYPASS 0x00000004U +#define LRFDRFE_IFADCDLDO_BYPASS_M 0x00000004U +#define LRFDRFE_IFADCDLDO_BYPASS_S 2U +#define LRFDRFE_IFADCDLDO_BYPASS_EN 0x00000004U +#define LRFDRFE_IFADCDLDO_BYPASS_DIS 0x00000000U + +// Field: [1] CLAMP +// +// Clamp the LDO output with diodes to ground +// +// Not used by analog when CTL or BYPASS are set. +// ENUMs: +// EN Enabled +// DIS Disabled. The LDO output is shorted to ground when +// disabled. +#define LRFDRFE_IFADCDLDO_CLAMP 0x00000002U +#define LRFDRFE_IFADCDLDO_CLAMP_M 0x00000002U +#define LRFDRFE_IFADCDLDO_CLAMP_S 1U +#define LRFDRFE_IFADCDLDO_CLAMP_EN 0x00000002U +#define LRFDRFE_IFADCDLDO_CLAMP_DIS 0x00000000U + +// Field: [0] CTL +// +// Enable regulator for supplying digital domain of the adc +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCDLDO_CTL 0x00000001U +#define LRFDRFE_IFADCDLDO_CTL_M 0x00000001U +#define LRFDRFE_IFADCDLDO_CTL_S 0U +#define LRFDRFE_IFADCDLDO_CTL_EN 0x00000001U +#define LRFDRFE_IFADCDLDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCTST +// +//***************************************************************************** +// Field: [7] EXTCURR +// +// Drive an external current +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_IFADCTST_EXTCURR 0x00000080U +#define LRFDRFE_IFADCTST_EXTCURR_M 0x00000080U +#define LRFDRFE_IFADCTST_EXTCURR_S 7U +#define LRFDRFE_IFADCTST_EXTCURR_EN 0x00000080U +#define LRFDRFE_IFADCTST_EXTCURR_DIS 0x00000000U + +// Field: [6] QCALDBIQ +// +// Comparator select for calibration data output +// +// Also look at the description of IFADCQUANT. +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE_IFADCTST_QCALDBIQ 0x00000040U +#define LRFDRFE_IFADCTST_QCALDBIQ_M 0x00000040U +#define LRFDRFE_IFADCTST_QCALDBIQ_S 6U +#define LRFDRFE_IFADCTST_QCALDBIQ_COMP1 0x00000040U +#define LRFDRFE_IFADCTST_QCALDBIQ_COMP0 0x00000000U + +// Field: [5] QCALDBC +// +// Select which quantizer comparator to mux out calibration data from +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE_IFADCTST_QCALDBC 0x00000020U +#define LRFDRFE_IFADCTST_QCALDBC_M 0x00000020U +#define LRFDRFE_IFADCTST_QCALDBC_S 5U +#define LRFDRFE_IFADCTST_QCALDBC_COMP1 0x00000020U +#define LRFDRFE_IFADCTST_QCALDBC_COMP0 0x00000000U + +// Field: [4:0] SEL +// +// Select which internal net to probe via atb. This bus goes to a 6-32 bit +// decoder. +// ENUMs: +// EXTCLKN1 External ADC clock through ADC_TEST_N (N1 +// internally). The the clock should be a 200MHz +// sine wave (it is divided internally to 100MHz). +// NONE ADC_TEST_P and ADC_TEST_N tristated (Default) +#define LRFDRFE_IFADCTST_SEL_W 5U +#define LRFDRFE_IFADCTST_SEL_M 0x0000001FU +#define LRFDRFE_IFADCTST_SEL_S 0U +#define LRFDRFE_IFADCTST_SEL_EXTCLKN1 0x0000001FU +#define LRFDRFE_IFADCTST_SEL_NONE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_ATSTREFL +// +//***************************************************************************** +// Field: [15:0] MUXLSB +// +// ATEST mux 0 control +// ENUMs: +// IFADC_ATB IFADC ATB +// LDO_VTEST LDO_VTEST vtest out, current +// LDO_ITEST LDO_ITEST itest out, current +// PA_PEAK_OUTN PA peak detector output n +// PA_PEAK_OUTP PA peak detector output p +// MIX_OUTQN MIX outqn, voltage +// MIX_OUTQP MIX outqp, voltage +// MIX_OUTIN MIX outin, voltage +// MIX_OUTIP MIX outip, voltage +// FE_OUTIN_2 Frontend IF outin, voltage +// FE_OUTIP_2 Frontend IF outip, voltage +// FE_OUTQN Frontend IF outqn, voltage +// FE_OUTQP Frontend IF outqp, voltage +// FE_OUTIN Frontend IF outin, voltage +// FE_OUTIP Frontend IF outip, voltage +// DIS No atest selected +#define LRFDRFE_ATSTREFL_MUXLSB_W 16U +#define LRFDRFE_ATSTREFL_MUXLSB_M 0x0000FFFFU +#define LRFDRFE_ATSTREFL_MUXLSB_S 0U +#define LRFDRFE_ATSTREFL_MUXLSB_IFADC_ATB 0x00008000U +#define LRFDRFE_ATSTREFL_MUXLSB_LDO_VTEST 0x00004000U +#define LRFDRFE_ATSTREFL_MUXLSB_LDO_ITEST 0x00002000U +#define LRFDRFE_ATSTREFL_MUXLSB_PA_PEAK_OUTN 0x00000800U +#define LRFDRFE_ATSTREFL_MUXLSB_PA_PEAK_OUTP 0x00000400U +#define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTQN 0x00000200U +#define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTQP 0x00000100U +#define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTIN 0x00000080U +#define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTIP 0x00000040U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIN_2 0x00000020U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIP_2 0x00000010U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTQN 0x00000008U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTQP 0x00000004U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIN 0x00000002U +#define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIP 0x00000001U +#define LRFDRFE_ATSTREFL_MUXLSB_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_ATSTREFH +// +//***************************************************************************** +// Field: [15] VREFBPDIS +// +// Bandgap reference bypass control +// ENUMs: +// BPDIS Bandgap reference bypass disabled +// BPEN Bandgap reference bypass enabled. +#define LRFDRFE_ATSTREFH_VREFBPDIS 0x00008000U +#define LRFDRFE_ATSTREFH_VREFBPDIS_M 0x00008000U +#define LRFDRFE_ATSTREFH_VREFBPDIS_S 15U +#define LRFDRFE_ATSTREFH_VREFBPDIS_BPDIS 0x00008000U +#define LRFDRFE_ATSTREFH_VREFBPDIS_BPEN 0x00000000U + +// Field: [14:10] IREFTRIM +// +// LRF bias current trim +// ENUMs: +// ONES All bits are ones +// ZEROS All bits are zero +#define LRFDRFE_ATSTREFH_IREFTRIM_W 5U +#define LRFDRFE_ATSTREFH_IREFTRIM_M 0x00007C00U +#define LRFDRFE_ATSTREFH_IREFTRIM_S 10U +#define LRFDRFE_ATSTREFH_IREFTRIM_ONES 0x00007C00U +#define LRFDRFE_ATSTREFH_IREFTRIM_ZEROS 0x00000000U + +// Field: [9] BIAS +// +// LRF reference system control +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE_ATSTREFH_BIAS 0x00000200U +#define LRFDRFE_ATSTREFH_BIAS_M 0x00000200U +#define LRFDRFE_ATSTREFH_BIAS_S 9U +#define LRFDRFE_ATSTREFH_BIAS_EN 0x00000200U +#define LRFDRFE_ATSTREFH_BIAS_DIS 0x00000000U + +// Field: [8] OUTPUT2 +// +// ATEST output 2 control +// ENUMs: +// EN The output is enabled +// DIS Output is disabled +#define LRFDRFE_ATSTREFH_OUTPUT2 0x00000100U +#define LRFDRFE_ATSTREFH_OUTPUT2_M 0x00000100U +#define LRFDRFE_ATSTREFH_OUTPUT2_S 8U +#define LRFDRFE_ATSTREFH_OUTPUT2_EN 0x00000100U +#define LRFDRFE_ATSTREFH_OUTPUT2_DIS 0x00000000U + +// Field: [7] OUTPUT1 +// +// ATEST output 1 control +// ENUMs: +// EN The output is enabled +// DIS Output is disabled +#define LRFDRFE_ATSTREFH_OUTPUT1 0x00000080U +#define LRFDRFE_ATSTREFH_OUTPUT1_M 0x00000080U +#define LRFDRFE_ATSTREFH_OUTPUT1_S 7U +#define LRFDRFE_ATSTREFH_OUTPUT1_EN 0x00000080U +#define LRFDRFE_ATSTREFH_OUTPUT1_DIS 0x00000000U + +// Field: [6:0] MUXMSB +// +// ATEST mux 2 control +// ENUMs: +// DIVBUF_NMOS_BIAS DIVBUF DC bias voltage for nmos switches +// DIVBUF_PMOS_BIAS DIVBUF DC bias voltage for pmos switches +// REFSYS_IREF REFSYS 4 uA output +// IFADC_ATB IFADC ATB +// DIS No atest selected +#define LRFDRFE_ATSTREFH_MUXMSB_W 7U +#define LRFDRFE_ATSTREFH_MUXMSB_M 0x0000007FU +#define LRFDRFE_ATSTREFH_MUXMSB_S 0U +#define LRFDRFE_ATSTREFH_MUXMSB_DIVBUF_NMOS_BIAS 0x00000010U +#define LRFDRFE_ATSTREFH_MUXMSB_DIVBUF_PMOS_BIAS 0x00000008U +#define LRFDRFE_ATSTREFH_MUXMSB_REFSYS_IREF 0x00000004U +#define LRFDRFE_ATSTREFH_MUXMSB_IFADC_ATB 0x00000001U +#define LRFDRFE_ATSTREFH_MUXMSB_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DCO +// +//***************************************************************************** +// Field: [10:9] MTDCSPARE +// +// Spare bits to MTDC +// ENUMs: +// DIS DIVIDER = 4 (for test purposes only) +// EN DIVIDER = 2 +#define LRFDRFE_DCO_MTDCSPARE_W 2U +#define LRFDRFE_DCO_MTDCSPARE_M 0x00000600U +#define LRFDRFE_DCO_MTDCSPARE_S 9U +#define LRFDRFE_DCO_MTDCSPARE_DIS 0x00000200U +#define LRFDRFE_DCO_MTDCSPARE_EN 0x00000000U + +// Field: [8:7] SPARE7 +// +// Spare +// ENUMs: +// ONE Bit is one +// ZERO Bit is zero +#define LRFDRFE_DCO_SPARE7_W 2U +#define LRFDRFE_DCO_SPARE7_M 0x00000180U +#define LRFDRFE_DCO_SPARE7_S 7U +#define LRFDRFE_DCO_SPARE7_ONE 0x00000080U +#define LRFDRFE_DCO_SPARE7_ZERO 0x00000000U + +// Field: [6:3] TAILRESTRIM +// +// Trim bits to set DCO-amplitude. +// +// 0x0: Disable DCO +// 0x1: Min DCO amplitude (min-current) +// 0xF: Max DCO amplitude (max current) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DCO_TAILRESTRIM_W 4U +#define LRFDRFE_DCO_TAILRESTRIM_M 0x00000078U +#define LRFDRFE_DCO_TAILRESTRIM_S 3U +#define LRFDRFE_DCO_TAILRESTRIM_ALLONES 0x00000078U +#define LRFDRFE_DCO_TAILRESTRIM_ALLZEROS 0x00000000U + +// Field: [2] RTRIMCAP +// +// RTRIM resistor cap control +// +// Field enables cap across RTRIM resistor. This can improve phase-noise in +// some conditions, but can also result in DCO-instability (Not used). +// +// INTERNAL NOTE: +// renamed from EN_BIAS_CAP +// ENUMs: +// EN Enable +// DIS Disable(default) +#define LRFDRFE_DCO_RTRIMCAP 0x00000004U +#define LRFDRFE_DCO_RTRIMCAP_M 0x00000004U +#define LRFDRFE_DCO_RTRIMCAP_S 2U +#define LRFDRFE_DCO_RTRIMCAP_EN 0x00000004U +#define LRFDRFE_DCO_RTRIMCAP_DIS 0x00000000U + +// Field: [1] CNRCAP +// +// Corner-lots frequency tuning control +// ENUMs: +// _50MHZ 50 MHz +// DEFAULT Default +#define LRFDRFE_DCO_CNRCAP 0x00000002U +#define LRFDRFE_DCO_CNRCAP_M 0x00000002U +#define LRFDRFE_DCO_CNRCAP_S 1U +#define LRFDRFE_DCO_CNRCAP__50MHZ 0x00000002U +#define LRFDRFE_DCO_CNRCAP_DEFAULT 0x00000000U + +// Field: [0] CRSCAPCM +// +// Coarse cap common mode control +// +// INTERNAL NOTE: +// *renamed from CAP_CM +// ENUMs: +// REDUCED Reduced common mode for greater reliability +// DEFAULT Default +#define LRFDRFE_DCO_CRSCAPCM 0x00000001U +#define LRFDRFE_DCO_CRSCAPCM_M 0x00000001U +#define LRFDRFE_DCO_CRSCAPCM_S 0U +#define LRFDRFE_DCO_CRSCAPCM_REDUCED 0x00000001U +#define LRFDRFE_DCO_CRSCAPCM_DEFAULT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIV +// +//***************************************************************************** +// Field: [15] PDET +// +// Adds 50mV to PM and NM bias voltages +// ENUMs: +// EN Peak detektor mode enabled, used in production +// test +// DIS Peak detector mode disabled, normal functional +// mode +#define LRFDRFE_DIV_PDET 0x00008000U +#define LRFDRFE_DIV_PDET_M 0x00008000U +#define LRFDRFE_DIV_PDET_S 15U +#define LRFDRFE_DIV_PDET_EN 0x00008000U +#define LRFDRFE_DIV_PDET_DIS 0x00000000U + +// Field: [14:12] NMIREFTRIM +// +// Trim code for NMOS-Bias Voltage in the divider. +// +// 0x0: Min Speed +// 0x7: Max Speed +// +// Default value: 0x4 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIV_NMIREFTRIM_W 3U +#define LRFDRFE_DIV_NMIREFTRIM_M 0x00007000U +#define LRFDRFE_DIV_NMIREFTRIM_S 12U +#define LRFDRFE_DIV_NMIREFTRIM_ALLONES 0x00007000U +#define LRFDRFE_DIV_NMIREFTRIM_ALLZEROS 0x00000000U + +// Field: [11:9] PMIREFTRIM +// +// Trim code for PMOS-Bias Voltage in the divider. +// +// 0x0: Min Speed +// 0x7: Max Speed +// +// Default value: 0x4 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIV_PMIREFTRIM_W 3U +#define LRFDRFE_DIV_PMIREFTRIM_M 0x00000E00U +#define LRFDRFE_DIV_PMIREFTRIM_S 9U +#define LRFDRFE_DIV_PMIREFTRIM_ALLONES 0x00000E00U +#define LRFDRFE_DIV_PMIREFTRIM_ALLZEROS 0x00000000U + +// Field: [8] TXBBOOST +// +// Not connected +// ENUMs: +// INCREASED High drive strength +// DEFAULT Default drive strength +#define LRFDRFE_DIV_TXBBOOST 0x00000100U +#define LRFDRFE_DIV_TXBBOOST_M 0x00000100U +#define LRFDRFE_DIV_TXBBOOST_S 8U +#define LRFDRFE_DIV_TXBBOOST_INCREASED 0x00000100U +#define LRFDRFE_DIV_TXBBOOST_DEFAULT 0x00000000U + +// Field: [7] S1GFRC +// +// Not connected +// ENUMs: +// EN Enable force S1G power switch +// DIS Disable force S1G power switch +#define LRFDRFE_DIV_S1GFRC 0x00000080U +#define LRFDRFE_DIV_S1GFRC_M 0x00000080U +#define LRFDRFE_DIV_S1GFRC_S 7U +#define LRFDRFE_DIV_S1GFRC_EN 0x00000080U +#define LRFDRFE_DIV_S1GFRC_DIS 0x00000000U + +// Field: [6:5] BUFGAIN +// +// Not connected +// ENUMs: +// _60_PST 60% of maximum gain +// DONT_USE Same as _80_PST +// _80_PST 80% of maximum gain +// MAX Maximum gain (default) +#define LRFDRFE_DIV_BUFGAIN_W 2U +#define LRFDRFE_DIV_BUFGAIN_M 0x00000060U +#define LRFDRFE_DIV_BUFGAIN_S 5U +#define LRFDRFE_DIV_BUFGAIN__60_PST 0x00000060U +#define LRFDRFE_DIV_BUFGAIN_DONT_USE 0x00000040U +#define LRFDRFE_DIV_BUFGAIN__80_PST 0x00000020U +#define LRFDRFE_DIV_BUFGAIN_MAX 0x00000000U + +// Field: [4] BIAS +// +// Not connected +// ENUMs: +// DEFAULT Default bias +// ALTERNATIVE Alternative bias (for test purposes) +#define LRFDRFE_DIV_BIAS 0x00000010U +#define LRFDRFE_DIV_BIAS_M 0x00000010U +#define LRFDRFE_DIV_BIAS_S 4U +#define LRFDRFE_DIV_BIAS_DEFAULT 0x00000010U +#define LRFDRFE_DIV_BIAS_ALTERNATIVE 0x00000000U + +// Field: [3] OUT +// +// Divider output +// +// Enable divider outputs to either sub-1GHz front-end or to 2.4 GHz front-end +// when any of the following equals ENABLE: +// - DIVCTL.RXPH0DIV +// - DIVCTL.RXPH90DIV +// - DIVCTL.TXPH0DIV +// - DIVCTL.TXPH180DIV +// ENUMs: +// FE_2G4 Enable outputs going to 2.4GHz front-end +// FE_S1G Enable outputs going to sub-1GHz front-end +#define LRFDRFE_DIV_OUT 0x00000008U +#define LRFDRFE_DIV_OUT_M 0x00000008U +#define LRFDRFE_DIV_OUT_S 3U +#define LRFDRFE_DIV_OUT_FE_2G4 0x00000008U +#define LRFDRFE_DIV_OUT_FE_S1G 0x00000000U + +// Field: [2:0] RATIO +// +// Divider ratio +// +// Field sets the divider ratio between DCO frequency, FDCO, and radio +// frequency, FRF. +// +// FRF = FDCO / DIVIDER +// ENUMs: +// DIV30 DIVIDER = 30 +// DIV15 DIVIDER = 15 +// DIV10 DIVIDER = 10 +// DIV5 DIVIDER = 5 +// DIV12 DIVIDER = 12 +// DIV6 DIVIDER = 6 +// DIV4 DIVIDER = 4 (for test purposes only) +// DIV2 DIVIDER = 2 +#define LRFDRFE_DIV_RATIO_W 3U +#define LRFDRFE_DIV_RATIO_M 0x00000007U +#define LRFDRFE_DIV_RATIO_S 0U +#define LRFDRFE_DIV_RATIO_DIV30 0x00000007U +#define LRFDRFE_DIV_RATIO_DIV15 0x00000006U +#define LRFDRFE_DIV_RATIO_DIV10 0x00000005U +#define LRFDRFE_DIV_RATIO_DIV5 0x00000004U +#define LRFDRFE_DIV_RATIO_DIV12 0x00000003U +#define LRFDRFE_DIV_RATIO_DIV6 0x00000002U +#define LRFDRFE_DIV_RATIO_DIV4 0x00000001U +#define LRFDRFE_DIV_RATIO_DIV2 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVLDO +// +//***************************************************************************** +// Field: [15] SPARE15 +// +// Spare bit +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_DIVLDO_SPARE15 0x00008000U +#define LRFDRFE_DIVLDO_SPARE15_M 0x00008000U +#define LRFDRFE_DIVLDO_SPARE15_S 15U +#define LRFDRFE_DIVLDO_SPARE15_ONES 0x00008000U +#define LRFDRFE_DIVLDO_SPARE15_ZEROS 0x00000000U + +// Field: [14:8] VOUTTRIM +// +// VOUT trim code +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_DIVLDO_VOUTTRIM_W 7U +#define LRFDRFE_DIVLDO_VOUTTRIM_M 0x00007F00U +#define LRFDRFE_DIVLDO_VOUTTRIM_S 8U +#define LRFDRFE_DIVLDO_VOUTTRIM_ONES 0x00007F00U +#define LRFDRFE_DIVLDO_VOUTTRIM_ZEROS 0x00000000U + +// Field: [7] ITST +// +// ITEST block control +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE_DIVLDO_ITST 0x00000080U +#define LRFDRFE_DIVLDO_ITST_M 0x00000080U +#define LRFDRFE_DIVLDO_ITST_S 7U +#define LRFDRFE_DIVLDO_ITST_EN 0x00000080U +#define LRFDRFE_DIVLDO_ITST_DIS 0x00000000U + +// Field: [6:4] TMUX +// +// TMUX control bits +// ENUMs: +// VDDR ATEST output is VDDR +// LDO_OUT ATEST output is LDO output +// GND ATEST output is grounded +// OFF Normal mode +#define LRFDRFE_DIVLDO_TMUX_W 3U +#define LRFDRFE_DIVLDO_TMUX_M 0x00000070U +#define LRFDRFE_DIVLDO_TMUX_S 4U +#define LRFDRFE_DIVLDO_TMUX_VDDR 0x00000040U +#define LRFDRFE_DIVLDO_TMUX_LDO_OUT 0x00000020U +#define LRFDRFE_DIVLDO_TMUX_GND 0x00000010U +#define LRFDRFE_DIVLDO_TMUX_OFF 0x00000000U + +// Field: [3] SPARE3 +// +// Spare bit +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DIVLDO_SPARE3 0x00000008U +#define LRFDRFE_DIVLDO_SPARE3_M 0x00000008U +#define LRFDRFE_DIVLDO_SPARE3_S 3U +#define LRFDRFE_DIVLDO_SPARE3_ONE 0x00000008U +#define LRFDRFE_DIVLDO_SPARE3_ZERO 0x00000000U + +// Field: [2] MODE +// +// High BW operation control +// ENUMs: +// FAST Regulator in high bandwidth mode +// NORM Regular low bandwidth of LDO +#define LRFDRFE_DIVLDO_MODE 0x00000004U +#define LRFDRFE_DIVLDO_MODE_M 0x00000004U +#define LRFDRFE_DIVLDO_MODE_S 2U +#define LRFDRFE_DIVLDO_MODE_FAST 0x00000004U +#define LRFDRFE_DIVLDO_MODE_NORM 0x00000000U + +// Field: [1] BYPASS +// +// Regulator bypass +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE_DIVLDO_BYPASS 0x00000002U +#define LRFDRFE_DIVLDO_BYPASS_M 0x00000002U +#define LRFDRFE_DIVLDO_BYPASS_S 1U +#define LRFDRFE_DIVLDO_BYPASS_EN 0x00000002U +#define LRFDRFE_DIVLDO_BYPASS_DIS 0x00000000U + +// Field: [0] CTL +// +// Regulator control +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE_DIVLDO_CTL 0x00000001U +#define LRFDRFE_DIVLDO_CTL_M 0x00000001U +#define LRFDRFE_DIVLDO_CTL_S 0U +#define LRFDRFE_DIVLDO_CTL_EN 0x00000001U +#define LRFDRFE_DIVLDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TDCLDO +// +//***************************************************************************** +// Field: [15] ITESTCTL +// +// ITEST control +// +// When enabled, it is possible to check current thorugh PASSFET. Scaled down +// 110:1 +// ENUMs: +// EN ITEST enabled +// DIS ITEST Disabled +#define LRFDRFE_TDCLDO_ITESTCTL 0x00008000U +#define LRFDRFE_TDCLDO_ITESTCTL_M 0x00008000U +#define LRFDRFE_TDCLDO_ITESTCTL_S 15U +#define LRFDRFE_TDCLDO_ITESTCTL_EN 0x00008000U +#define LRFDRFE_TDCLDO_ITESTCTL_DIS 0x00000000U + +// Field: [14:8] VOUTTRIM +// +// VOUT trim code +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_TDCLDO_VOUTTRIM_W 7U +#define LRFDRFE_TDCLDO_VOUTTRIM_M 0x00007F00U +#define LRFDRFE_TDCLDO_VOUTTRIM_S 8U +#define LRFDRFE_TDCLDO_VOUTTRIM_ONES 0x00007F00U +#define LRFDRFE_TDCLDO_VOUTTRIM_ZEROS 0x00000000U + +// Field: [7] ITESTBUFCTL +// +// ITEST BUFF block control +// +// When enabled, it is possible to check current through buffer, scaled down +// 12:1. +// ENUMs: +// EN ITEST mode in buffer is enabled +// DIS ITEST mode in buffer is disabled +#define LRFDRFE_TDCLDO_ITESTBUFCTL 0x00000080U +#define LRFDRFE_TDCLDO_ITESTBUFCTL_M 0x00000080U +#define LRFDRFE_TDCLDO_ITESTBUFCTL_S 7U +#define LRFDRFE_TDCLDO_ITESTBUFCTL_EN 0x00000080U +#define LRFDRFE_TDCLDO_ITESTBUFCTL_DIS 0x00000000U + +// Field: [6:4] TMUX +// +// TMUX control bits +// ENUMs: +// VSSA ATEST output is VSSA +// LDO_OUT ATEST output is LDO output +// VDDA ATEST output is VDDA +// OFF Normal mode +#define LRFDRFE_TDCLDO_TMUX_W 3U +#define LRFDRFE_TDCLDO_TMUX_M 0x00000070U +#define LRFDRFE_TDCLDO_TMUX_S 4U +#define LRFDRFE_TDCLDO_TMUX_VSSA 0x00000040U +#define LRFDRFE_TDCLDO_TMUX_LDO_OUT 0x00000020U +#define LRFDRFE_TDCLDO_TMUX_VDDA 0x00000010U +#define LRFDRFE_TDCLDO_TMUX_OFF 0x00000000U + +// Field: [3] PDSEL +// +// Selects between resistor or diode stack PD +// ENUMs: +// DIODE Diode stack +// R R (default) +#define LRFDRFE_TDCLDO_PDSEL 0x00000008U +#define LRFDRFE_TDCLDO_PDSEL_M 0x00000008U +#define LRFDRFE_TDCLDO_PDSEL_S 3U +#define LRFDRFE_TDCLDO_PDSEL_DIODE 0x00000008U +#define LRFDRFE_TDCLDO_PDSEL_R 0x00000000U + +// Field: [2] MODE +// +// High BW operation control +// +// Increase BW of slow loop (by increasing quiescent current). +// ENUMs: +// FAST Regulator in high bandwidth mode +// NORM Regular low bandwidth of LDO +#define LRFDRFE_TDCLDO_MODE 0x00000004U +#define LRFDRFE_TDCLDO_MODE_M 0x00000004U +#define LRFDRFE_TDCLDO_MODE_S 2U +#define LRFDRFE_TDCLDO_MODE_FAST 0x00000004U +#define LRFDRFE_TDCLDO_MODE_NORM 0x00000000U + +// Field: [1] BYPASS +// +// Regulator bypass +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE_TDCLDO_BYPASS 0x00000002U +#define LRFDRFE_TDCLDO_BYPASS_M 0x00000002U +#define LRFDRFE_TDCLDO_BYPASS_S 1U +#define LRFDRFE_TDCLDO_BYPASS_EN 0x00000002U +#define LRFDRFE_TDCLDO_BYPASS_DIS 0x00000000U + +// Field: [0] CTL +// +// Regulator control +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE_TDCLDO_CTL 0x00000001U +#define LRFDRFE_TDCLDO_CTL_M 0x00000001U +#define LRFDRFE_TDCLDO_CTL_S 0U +#define LRFDRFE_TDCLDO_CTL_EN 0x00000001U +#define LRFDRFE_TDCLDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DCOLDO0 +// +//***************************************************************************** +// Field: [15:14] ITST +// +// ITEST block control +// ENUMs: +// BOTH Enable both pass transistors +// SECOND Enable second pass transistor +// FIRST Enable first pass transistor +// DIS Regulator is disabled +#define LRFDRFE_DCOLDO0_ITST_W 2U +#define LRFDRFE_DCOLDO0_ITST_M 0x0000C000U +#define LRFDRFE_DCOLDO0_ITST_S 14U +#define LRFDRFE_DCOLDO0_ITST_BOTH 0x0000C000U +#define LRFDRFE_DCOLDO0_ITST_SECOND 0x00008000U +#define LRFDRFE_DCOLDO0_ITST_FIRST 0x00004000U +#define LRFDRFE_DCOLDO0_ITST_DIS 0x00000000U + +// Field: [13:8] SECONDTRIM +// +// Trim for second LDO +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_DCOLDO0_SECONDTRIM_W 6U +#define LRFDRFE_DCOLDO0_SECONDTRIM_M 0x00003F00U +#define LRFDRFE_DCOLDO0_SECONDTRIM_S 8U +#define LRFDRFE_DCOLDO0_SECONDTRIM_ONES 0x00003F00U +#define LRFDRFE_DCOLDO0_SECONDTRIM_ZEROS 0x00000000U + +// Field: [7:4] FIRSTTRIM +// +// TRIM for first LDO +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_DCOLDO0_FIRSTTRIM_W 4U +#define LRFDRFE_DCOLDO0_FIRSTTRIM_M 0x000000F0U +#define LRFDRFE_DCOLDO0_FIRSTTRIM_S 4U +#define LRFDRFE_DCOLDO0_FIRSTTRIM_ONES 0x000000F0U +#define LRFDRFE_DCOLDO0_FIRSTTRIM_ZEROS 0x00000000U + +// Field: [3] PDN +// +// Pulldown control +// ENUMs: +// EN Pulldown +// DIS No Pulldown +#define LRFDRFE_DCOLDO0_PDN 0x00000008U +#define LRFDRFE_DCOLDO0_PDN_M 0x00000008U +#define LRFDRFE_DCOLDO0_PDN_S 3U +#define LRFDRFE_DCOLDO0_PDN_EN 0x00000008U +#define LRFDRFE_DCOLDO0_PDN_DIS 0x00000000U + +// Field: [2] BYPFIRST +// +// Bypass first regulator +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE_DCOLDO0_BYPFIRST 0x00000004U +#define LRFDRFE_DCOLDO0_BYPFIRST_M 0x00000004U +#define LRFDRFE_DCOLDO0_BYPFIRST_S 2U +#define LRFDRFE_DCOLDO0_BYPFIRST_EN 0x00000004U +#define LRFDRFE_DCOLDO0_BYPFIRST_DIS 0x00000000U + +// Field: [1] BYPBOTH +// +// Bypass LDO (both) +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE_DCOLDO0_BYPBOTH 0x00000002U +#define LRFDRFE_DCOLDO0_BYPBOTH_M 0x00000002U +#define LRFDRFE_DCOLDO0_BYPBOTH_S 1U +#define LRFDRFE_DCOLDO0_BYPBOTH_EN 0x00000002U +#define LRFDRFE_DCOLDO0_BYPBOTH_DIS 0x00000000U + +// Field: [0] CTL +// +// Regulator control +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE_DCOLDO0_CTL 0x00000001U +#define LRFDRFE_DCOLDO0_CTL_M 0x00000001U +#define LRFDRFE_DCOLDO0_CTL_S 0U +#define LRFDRFE_DCOLDO0_CTL_EN 0x00000001U +#define LRFDRFE_DCOLDO0_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DCOLDO1 +// +//***************************************************************************** +// Field: [10] REFSRC +// +// Select clock source to PLL +// ENUMs: +// BAW PLL clock source is BAW +// XTAL PLL clock source is XTAL +#define LRFDRFE_DCOLDO1_REFSRC 0x00000400U +#define LRFDRFE_DCOLDO1_REFSRC_M 0x00000400U +#define LRFDRFE_DCOLDO1_REFSRC_S 10U +#define LRFDRFE_DCOLDO1_REFSRC_BAW 0x00000400U +#define LRFDRFE_DCOLDO1_REFSRC_XTAL 0x00000000U + +// Field: [9:8] DIVATST +// +// Divider ATEST control +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_DCOLDO1_DIVATST_W 2U +#define LRFDRFE_DCOLDO1_DIVATST_M 0x00000300U +#define LRFDRFE_DCOLDO1_DIVATST_S 8U +#define LRFDRFE_DCOLDO1_DIVATST_ONES 0x00000300U +#define LRFDRFE_DCOLDO1_DIVATST_ZEROS 0x00000000U + +// Field: [7] PERFM +// +// Performance mode control +// +// When enabled, the LDO uses more current to reduce flicker noise. +// ENUMs: +// EN Enabled (performance) +// DIS Disabled (normal) +#define LRFDRFE_DCOLDO1_PERFM 0x00000080U +#define LRFDRFE_DCOLDO1_PERFM_M 0x00000080U +#define LRFDRFE_DCOLDO1_PERFM_S 7U +#define LRFDRFE_DCOLDO1_PERFM_EN 0x00000080U +#define LRFDRFE_DCOLDO1_PERFM_DIS 0x00000000U + +// Field: [6] CHRGFILT +// +// Charge the filters +// ENUMs: +// EN Charging enabled +// DIS Charging disabled, normal operation +#define LRFDRFE_DCOLDO1_CHRGFILT 0x00000040U +#define LRFDRFE_DCOLDO1_CHRGFILT_M 0x00000040U +#define LRFDRFE_DCOLDO1_CHRGFILT_S 6U +#define LRFDRFE_DCOLDO1_CHRGFILT_EN 0x00000040U +#define LRFDRFE_DCOLDO1_CHRGFILT_DIS 0x00000000U + +// Field: [5:0] ATST +// +// ATEST block control +// ENUMs: +// VSSANA VSSANA +// FIRST_OUT First LDO output +// LDO_OUT LDO output +#define LRFDRFE_DCOLDO1_ATST_W 6U +#define LRFDRFE_DCOLDO1_ATST_M 0x0000003FU +#define LRFDRFE_DCOLDO1_ATST_S 0U +#define LRFDRFE_DCOLDO1_ATST_VSSANA 0x00000020U +#define LRFDRFE_DCOLDO1_ATST_FIRST_OUT 0x00000001U +#define LRFDRFE_DCOLDO1_ATST_LDO_OUT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRE0 +// +//***************************************************************************** +// Field: [15:14] SPARE14 +// +// SPARE14 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE0_SPARE14_W 2U +#define LRFDRFE_PRE0_SPARE14_M 0x0000C000U +#define LRFDRFE_PRE0_SPARE14_S 14U +#define LRFDRFE_PRE0_SPARE14_ALLONES 0x0000C000U +#define LRFDRFE_PRE0_SPARE14_ALLZEROS 0x00000000U + +// Field: [13:8] PLLDIV1 +// +// PLL reference frequency divider 1 +// +// The value of DLOCTL0.LOOPUPD decides if this reference frequency is used. +// +// FREFCLK = FXTAL / PLLDIV1 +// +// Examples: +// 0: Illegal setting +// 1: Illegal setting +// 2: Divide by 2 +// ... +// 63: Divide by 63 +// +// FREFCLK must be higher than or equal to 1 MHz in closed-loop state. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE0_PLLDIV1_W 6U +#define LRFDRFE_PRE0_PLLDIV1_M 0x00003F00U +#define LRFDRFE_PRE0_PLLDIV1_S 8U +#define LRFDRFE_PRE0_PLLDIV1_ALLONES 0x00003F00U +#define LRFDRFE_PRE0_PLLDIV1_ALLZEROS 0x00000000U + +// Field: [7:6] SPARE6 +// +// SPARE6 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE0_SPARE6_W 2U +#define LRFDRFE_PRE0_SPARE6_M 0x000000C0U +#define LRFDRFE_PRE0_SPARE6_S 6U +#define LRFDRFE_PRE0_SPARE6_ALLONES 0x000000C0U +#define LRFDRFE_PRE0_SPARE6_ALLZEROS 0x00000000U + +// Field: [5:0] PLLDIV0 +// +// PLL reference frequency divider 0 +// +// The value of DLOCTL0.LOOPUPD decides if this reference frequency is used. +// +// FREFCLK = FXTAL / PLLDIV0 +// +// Examples: +// 0: Illegal setting +// 1: Illegal setting +// 2: Divide by 2 +// ... +// 63: Divide by 63 +// +// FREFCLK must be higher than or equal to 1 MHz in closed-loop state. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE0_PLLDIV0_W 6U +#define LRFDRFE_PRE0_PLLDIV0_M 0x0000003FU +#define LRFDRFE_PRE0_PLLDIV0_S 0U +#define LRFDRFE_PRE0_PLLDIV0_ALLONES 0x0000003FU +#define LRFDRFE_PRE0_PLLDIV0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRE1 +// +//***************************************************************************** +// Field: [15:14] IIRBW +// +// Loop IIR filter bandwidth +// ENUMs: +// K16 K=16 +// K8 +// K4 +// K2 +#define LRFDRFE_PRE1_IIRBW_W 2U +#define LRFDRFE_PRE1_IIRBW_M 0x0000C000U +#define LRFDRFE_PRE1_IIRBW_S 14U +#define LRFDRFE_PRE1_IIRBW_K16 0x0000C000U +#define LRFDRFE_PRE1_IIRBW_K8 0x00008000U +#define LRFDRFE_PRE1_IIRBW_K4 0x00004000U +#define LRFDRFE_PRE1_IIRBW_K2 0x00000000U + +// Field: [13] IIRORD +// +// IIR order +// ENUMs: +// SECOND Select second order IIR filter +// FIRST Select first order IIR filter +#define LRFDRFE_PRE1_IIRORD 0x00002000U +#define LRFDRFE_PRE1_IIRORD_M 0x00002000U +#define LRFDRFE_PRE1_IIRORD_S 13U +#define LRFDRFE_PRE1_IIRORD_SECOND 0x00002000U +#define LRFDRFE_PRE1_IIRORD_FIRST 0x00000000U + +// Field: [12:8] IIRDIV +// +// IIR divider +// +// FIIRCLK = FCKVD64 / (IIRDIV+1) +// +// Examples: +// +// 0: Clock is ckvd64/1 +// 1: Clock is ckvd64/2 +// ... +// 31: Clock is ckvd64/32 +// +// INTERNAL NOTE: +// * See the implementation spec for formula. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE1_IIRDIV_W 5U +#define LRFDRFE_PRE1_IIRDIV_M 0x00001F00U +#define LRFDRFE_PRE1_IIRDIV_S 8U +#define LRFDRFE_PRE1_IIRDIV_ALLONES 0x00001F00U +#define LRFDRFE_PRE1_IIRDIV_ALLZEROS 0x00000000U + +// Field: [6] CALHSDDC +// +// TDC calibration setting for HSDDC +// ENUMs: +// GATE Duty-cycling given by HSDDC +// NOGATE No duty-cycling +#define LRFDRFE_PRE1_CALHSDDC 0x00000040U +#define LRFDRFE_PRE1_CALHSDDC_M 0x00000040U +#define LRFDRFE_PRE1_CALHSDDC_S 6U +#define LRFDRFE_PRE1_CALHSDDC_GATE 0x00000040U +#define LRFDRFE_PRE1_CALHSDDC_NOGATE 0x00000000U + +// Field: [5:0] HSDDC +// +// TDC high-speed digital duty cycle +// +// The TDC high-speed clock can always run or be duty cycled to save current +// consumption. The minimum ON-time equals the reference clock source period +// (PER). In this case, the clock starts to toggle 1/2 * PER before positive +// edge of reference clock. If the clock runs for two periods, it starts to +// toggle 1.5 * PER before the positve edge of the reference clock. In any +// case, it toggles during the high time of reference clock source. +// +// The field value must not be set higher than the minimum binary value of the +// active reference clock divider. +// +// Encoding: +// 0: Enable clock to TDC always +// 1: Enable clock to TDC always +// 2: Enable clock to TDC for 1 PER +// 3. Enable clock to TDC for 2 PER +// ... +// 63: Enable clock to TDC for 62 PER +// +// INTERNAL NOTE: +// * Value of 2 shall be used to save current consumption as long as there is +// no or acceptable power noise/TDC modulation generated by this setting. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE1_HSDDC_W 6U +#define LRFDRFE_PRE1_HSDDC_M 0x0000003FU +#define LRFDRFE_PRE1_HSDDC_S 0U +#define LRFDRFE_PRE1_HSDDC_ALLONES 0x0000003FU +#define LRFDRFE_PRE1_HSDDC_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRE2 +// +//***************************************************************************** +// Field: [15:12] MIDCALDIVLSB +// +// Mid calibration divider LSB +// +// This field determines the reference frequency used during the mid SAR +// calibration stages, according to: +// +// FREFCLK = FXTAL / MIDCALDIV +// +// Field encoding is unsigned integer: +// 0-7: Illegal setting +// 8: Divide by 8 +// 9: Divide by 9 +// .. +// 1023: Divide by 1023 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE2_MIDCALDIVLSB_W 4U +#define LRFDRFE_PRE2_MIDCALDIVLSB_M 0x0000F000U +#define LRFDRFE_PRE2_MIDCALDIVLSB_S 12U +#define LRFDRFE_PRE2_MIDCALDIVLSB_ALLONES 0x0000F000U +#define LRFDRFE_PRE2_MIDCALDIVLSB_ALLZEROS 0x00000000U + +// Field: [11:6] CRSCALDIV +// +// Coarse calibration divider +// +// This field determines the reference frequency used during the coarse SAR +// calibration stages, according to: +// +// FREFCLK = FXTAL / CRSCALDIV +// +// Field encoding is unsigned integer: +// 0-7: Illegal setting +// 8: Divide by 8 +// 9: Divide by 9 +// .. +// 63: Divide by 63 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE2_CRSCALDIV_W 6U +#define LRFDRFE_PRE2_CRSCALDIV_M 0x00000FC0U +#define LRFDRFE_PRE2_CRSCALDIV_S 6U +#define LRFDRFE_PRE2_CRSCALDIV_ALLONES 0x00000FC0U +#define LRFDRFE_PRE2_CRSCALDIV_ALLZEROS 0x00000000U + +// Field: [5:0] FSMDIV +// +// FSM divider +// +// This field determines the clock frequency for FSM traversal through states +// that does not affect calibration, according to: +// +// FFSM = FXTAL / FSMDIV +// +// Field encoding is unsigned integer: +// 0-3: Illegal setting +// 4: Divide by 4 +// 5: Divide by 5 +// .. +// 63: Divide by 63 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE2_FSMDIV_W 6U +#define LRFDRFE_PRE2_FSMDIV_M 0x0000003FU +#define LRFDRFE_PRE2_FSMDIV_S 0U +#define LRFDRFE_PRE2_FSMDIV_ALLONES 0x0000003FU +#define LRFDRFE_PRE2_FSMDIV_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRE3 +// +//***************************************************************************** +// Field: [15:5] FINECALDIV +// +// Fine calibration divider +// +// This field determines the reference frequency used to measure the DCO gain +// (KDCO), according to: +// +// FREFCLK = FXTAL / FINECALDIV +// +// Field encoding is unsigned integer: +// 0-7: Illegal setting +// 8: Divide by 8 +// 9: Divide by 9 +// .. +// 4095: Divide by 4095 +// +// Use a lower reference frequency to increases the KDCO estimation accuracy at +// the cost of increased calibration time. The KDCO estimation takes +// approximately 2 periods of the configured frequency. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE3_FINECALDIV_W 11U +#define LRFDRFE_PRE3_FINECALDIV_M 0x0000FFE0U +#define LRFDRFE_PRE3_FINECALDIV_S 5U +#define LRFDRFE_PRE3_FINECALDIV_ALLONES 0x0000FFE0U +#define LRFDRFE_PRE3_FINECALDIV_ALLZEROS 0x00000000U + +// Field: [4:0] MIDCALDIVMSB +// +// Mid calibration divider MSB +// +// This field determines the reference frequency used during the mid SAR +// calibration stages, according to: +// +// FREFCLK = FXTAL / MIDCALDIV +// +// Field encoding is unsigned integer: +// 0-7: Illegal setting +// 8: Divide by 8 +// 9: Divide by 9 +// .. +// 1023: Divide by 1023 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRE3_MIDCALDIVMSB_W 5U +#define LRFDRFE_PRE3_MIDCALDIVMSB_M 0x0000001FU +#define LRFDRFE_PRE3_MIDCALDIVMSB_S 0U +#define LRFDRFE_PRE3_MIDCALDIVMSB_ALLONES 0x0000001FU +#define LRFDRFE_PRE3_MIDCALDIVMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CAL0 +// +//***************************************************************************** +// Field: [15] SPARE15 +// +// SPARE15 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_CAL0_SPARE15 0x00008000U +#define LRFDRFE_CAL0_SPARE15_M 0x00008000U +#define LRFDRFE_CAL0_SPARE15_S 15U +#define LRFDRFE_CAL0_SPARE15_ONE 0x00008000U +#define LRFDRFE_CAL0_SPARE15_ZERO 0x00000000U + +// Field: [14:8] FCSTART +// +// Fine code start +// +// Fine code applied to DCO during all calibration states except during KDCO +// estimation. The start code is then applied to DCO at start of phase +// aquisition in state PLL_ST. Ensure that value is the aritmetic mean of +// CAL1.FCBOT and CAL1.FCTOP. +// +// Field encoding is <7u>. +// +// INTERNAL NOTE: +// * The value specified as start code will not be applied when moving from +// open-loop to closed-loop PLL mode. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL0_FCSTART_W 7U +#define LRFDRFE_CAL0_FCSTART_M 0x00007F00U +#define LRFDRFE_CAL0_FCSTART_S 8U +#define LRFDRFE_CAL0_FCSTART_ALLONES 0x00007F00U +#define LRFDRFE_CAL0_FCSTART_ALLZEROS 0x00000000U + +// Field: [7] CRS +// +// Coarse calibration control +// ENUMs: +// EN Enable coarse calibration +// DIS Disable coarse calibration +#define LRFDRFE_CAL0_CRS 0x00000080U +#define LRFDRFE_CAL0_CRS_M 0x00000080U +#define LRFDRFE_CAL0_CRS_S 7U +#define LRFDRFE_CAL0_CRS_EN 0x00000080U +#define LRFDRFE_CAL0_CRS_DIS 0x00000000U + +// Field: [6] MID +// +// Mid calibration control +// ENUMs: +// EN Enable mid calibration +// DIS Disable mid calibration +#define LRFDRFE_CAL0_MID 0x00000040U +#define LRFDRFE_CAL0_MID_M 0x00000040U +#define LRFDRFE_CAL0_MID_S 6U +#define LRFDRFE_CAL0_MID_EN 0x00000040U +#define LRFDRFE_CAL0_MID_DIS 0x00000000U + +// Field: [5] KTDC +// +// KTDC estimation control +// +// It's necessary to estimate the TDC gain to compute its' inverse, +// CAL2.KTDCINV. The latter is used to normalize TDC integer result into +// fractional CKVD periods. +// ENUMs: +// EN Enable TDC estimation +// DIS Disable TDC estimation +#define LRFDRFE_CAL0_KTDC 0x00000020U +#define LRFDRFE_CAL0_KTDC_M 0x00000020U +#define LRFDRFE_CAL0_KTDC_S 5U +#define LRFDRFE_CAL0_KTDC_EN 0x00000020U +#define LRFDRFE_CAL0_KTDC_DIS 0x00000000U + +// Field: [4] KDCO +// +// KDCO estimation control +// ENUMs: +// EN Enable KDCO estimation +// DIS Disable KDCO estimation +#define LRFDRFE_CAL0_KDCO 0x00000010U +#define LRFDRFE_CAL0_KDCO_M 0x00000010U +#define LRFDRFE_CAL0_KDCO_S 4U +#define LRFDRFE_CAL0_KDCO_EN 0x00000010U +#define LRFDRFE_CAL0_KDCO_DIS 0x00000000U + +// Field: [3:2] TDCAVG +// +// TDC average control +// +// During TDC calibration the TDC measures a pulse of DLOCTL0.TDCSTOP duration. +// The measurement is repeated 2^CAL0.TDCAVG times by the FSM and the +// individual TDC results are accumulated and the final result is available in +// TDCCAL.VAL. +// ENUMs: +// REPEAT_8_TIMES Repeat measurement 8 times +// REPEAT_4_TIMES Repeat measurement 4 times +// REPEAT_2_TIMES Repeat measurement 2 times +// REPEAT_1_TIME Repeat measurement 1 time +#define LRFDRFE_CAL0_TDCAVG_W 2U +#define LRFDRFE_CAL0_TDCAVG_M 0x0000000CU +#define LRFDRFE_CAL0_TDCAVG_S 2U +#define LRFDRFE_CAL0_TDCAVG_REPEAT_8_TIMES 0x0000000CU +#define LRFDRFE_CAL0_TDCAVG_REPEAT_4_TIMES 0x00000008U +#define LRFDRFE_CAL0_TDCAVG_REPEAT_2_TIMES 0x00000004U +#define LRFDRFE_CAL0_TDCAVG_REPEAT_1_TIME 0x00000000U + +// Field: [1:0] TDC_SPARE +// +// TDC spare bits +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL0_TDC_SPARE_W 2U +#define LRFDRFE_CAL0_TDC_SPARE_M 0x00000003U +#define LRFDRFE_CAL0_TDC_SPARE_S 0U +#define LRFDRFE_CAL0_TDC_SPARE_ALLONES 0x00000003U +#define LRFDRFE_CAL0_TDC_SPARE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CAL1 +// +//***************************************************************************** +// Field: [15] SPARE15 +// +// SPARE15 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_CAL1_SPARE15 0x00008000U +#define LRFDRFE_CAL1_SPARE15_M 0x00008000U +#define LRFDRFE_CAL1_SPARE15_S 15U +#define LRFDRFE_CAL1_SPARE15_ONE 0x00008000U +#define LRFDRFE_CAL1_SPARE15_ZERO 0x00000000U + +// Field: [14:8] FCTOP +// +// Fine code top +// +// Fine code applied to DCO during KDCO estimation in FSM state FINE_TOP_ST. +// Ensure that CAL0.FCSTART value is the aritmetic mean of CAL1.FCBOT and this +// value. +// +// Field encoding is <7u>. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL1_FCTOP_W 7U +#define LRFDRFE_CAL1_FCTOP_M 0x00007F00U +#define LRFDRFE_CAL1_FCTOP_S 8U +#define LRFDRFE_CAL1_FCTOP_ALLONES 0x00007F00U +#define LRFDRFE_CAL1_FCTOP_ALLZEROS 0x00000000U + +// Field: [7] SPARE7 +// +// SPARE7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_CAL1_SPARE7 0x00000080U +#define LRFDRFE_CAL1_SPARE7_M 0x00000080U +#define LRFDRFE_CAL1_SPARE7_S 7U +#define LRFDRFE_CAL1_SPARE7_ONE 0x00000080U +#define LRFDRFE_CAL1_SPARE7_ZERO 0x00000000U + +// Field: [6:0] FCBOT +// +// Fine code bottom +// +// Fine code applied to DCO during KDCO estimation in FSM state FINE_BOT_ST. +// Ensure that CAL0.FCSTART value is the aritmetic mean of this value and +// CAL1.FCTOP. +// +// Field encoding is <7u>. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL1_FCBOT_W 7U +#define LRFDRFE_CAL1_FCBOT_M 0x0000007FU +#define LRFDRFE_CAL1_FCBOT_S 0U +#define LRFDRFE_CAL1_FCBOT_ALLONES 0x0000007FU +#define LRFDRFE_CAL1_FCBOT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CAL2 +// +//***************************************************************************** +// Field: [15:0] KTDCINV +// +// KTDC inverse +// +// FW updates field with the inverse KTDC value before it enables KDCO +// estimation. KTDC value is availble in TDCCAL.VAL. +// +// One CKVD clock period is normalized to phase of 2^16, hence FW calculates +// field value according to: +// +// KTDCINV = 2^(16+CAL0.TDCAVG+DLOCTL0.TDCSTOP)/TDCCAL.VAL +// +// Encoding is <0.16u>. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL2_KTDCINV_W 16U +#define LRFDRFE_CAL2_KTDCINV_M 0x0000FFFFU +#define LRFDRFE_CAL2_KTDCINV_S 0U +#define LRFDRFE_CAL2_KTDCINV_ALLONES 0x0000FFFFU +#define LRFDRFE_CAL2_KTDCINV_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CAL3 +// +//***************************************************************************** +// Field: [15:0] DTXGAIN +// +// Addition path gain +// +// The modulator resolution is given by: +// +// MOD_RES = FRF / 2^(21+MOD0.CANPTHGAIN) Hz/LSB +// +// This resolution is achieved when DC gain in addition and cancellation paths +// are equal. To achieve this condition, the addtion path gain must account for +// the estimated KDCO according to: +// +// DTXGAIN = 2^14 * MOD_RES / KDCO = FRF / KDCO / 2^(7+MOD0.CANPTHGAIN) +// +// Encoding is <2.14u>. +// +// INTERNAL NOTE: +// * The shortest calibration time (1 MHz Fref) for KDCO estimation will give +// around 0.2% uncertainty on the KDCO estimate, worst case. The resolution of +// this field is 2^-14, and hence resolution is not limiting the quality. For +// 25 kHz calibration time, the resolution is also better than the uncertainty. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CAL3_DTXGAIN_W 16U +#define LRFDRFE_CAL3_DTXGAIN_M 0x0000FFFFU +#define LRFDRFE_CAL3_DTXGAIN_S 0U +#define LRFDRFE_CAL3_DTXGAIN_ALLONES 0x0000FFFFU +#define LRFDRFE_CAL3_DTXGAIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MISC0 +// +//***************************************************************************** +// Field: [13] PHCPT +// +// Phase capture mode +// +// Field decides if the phase capture mechanism is synchronous to phase valid +// signal or not. Default is synchronous mode (0). +// ENUMs: +// ASYNC Phase capture mode is asyncrhonous +// SYNC Phase capture mode is synchronous +#define LRFDRFE_MISC0_PHCPT 0x00002000U +#define LRFDRFE_MISC0_PHCPT_M 0x00002000U +#define LRFDRFE_MISC0_PHCPT_S 13U +#define LRFDRFE_MISC0_PHCPT_ASYNC 0x00002000U +#define LRFDRFE_MISC0_PHCPT_SYNC 0x00000000U + +// Field: [12] TDCCALCORR +// +// Detect and correct errors in TDC value during calibration +// +// Value shall remain static after DLOCTL0.RSTN equals 1. +// ENUMs: +// EN Enable TDC error correction inside DLO. +// DIS Disable TDC error correction inside DLO. +#define LRFDRFE_MISC0_TDCCALCORR 0x00001000U +#define LRFDRFE_MISC0_TDCCALCORR_M 0x00001000U +#define LRFDRFE_MISC0_TDCCALCORR_S 12U +#define LRFDRFE_MISC0_TDCCALCORR_EN 0x00001000U +#define LRFDRFE_MISC0_TDCCALCORR_DIS 0x00000000U + +// Field: [11] TDCMSBCORR +// +// TDC MSB error correction control +// +// Value shall remain static after DLOCTL0.RSTN equals 1. +// ENUMs: +// EN Enable TDC error correction inside DLO. +// DIS Disable TDC error correction inside DLO. +#define LRFDRFE_MISC0_TDCMSBCORR 0x00000800U +#define LRFDRFE_MISC0_TDCMSBCORR_M 0x00000800U +#define LRFDRFE_MISC0_TDCMSBCORR_S 11U +#define LRFDRFE_MISC0_TDCMSBCORR_EN 0x00000800U +#define LRFDRFE_MISC0_TDCMSBCORR_DIS 0x00000000U + +// Field: [10] SDMDEM +// +// SDM dynamic element matching control +// ENUMs: +// EN Enable dynamic element matching (recommended) +// DIS Disable dynamic element matching +#define LRFDRFE_MISC0_SDMDEM 0x00000400U +#define LRFDRFE_MISC0_SDMDEM_M 0x00000400U +#define LRFDRFE_MISC0_SDMDEM_S 10U +#define LRFDRFE_MISC0_SDMDEM_EN 0x00000400U +#define LRFDRFE_MISC0_SDMDEM_DIS 0x00000000U + +// Field: [9:8] DLYSDM +// +// SDM delay match configuration +// +// Fine tune latency for integer part of fine code. The delay should match +// delay through SDM. +// ENUMs: +// CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods +// CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods +// CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period +// CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods +#define LRFDRFE_MISC0_DLYSDM_W 2U +#define LRFDRFE_MISC0_DLYSDM_M 0x00000300U +#define LRFDRFE_MISC0_DLYSDM_S 8U +#define LRFDRFE_MISC0_DLYSDM_CKVD16_3_PER 0x00000300U +#define LRFDRFE_MISC0_DLYSDM_CKVD16_2_PER 0x00000200U +#define LRFDRFE_MISC0_DLYSDM_CKVD16_1_PER 0x00000100U +#define LRFDRFE_MISC0_DLYSDM_CKVD16_0_PER 0x00000000U + +// Field: [6] DLYPHVALID +// +// Phase valid delay +// ENUMs: +// CKVD16_1_PER Delays the variable phase capture and hence the +// phase error calculation with 1 CKVD16 clock +// period. +// CKVD16_0_PER No additional delay on variable phase capture. +#define LRFDRFE_MISC0_DLYPHVALID 0x00000040U +#define LRFDRFE_MISC0_DLYPHVALID_M 0x00000040U +#define LRFDRFE_MISC0_DLYPHVALID_S 6U +#define LRFDRFE_MISC0_DLYPHVALID_CKVD16_1_PER 0x00000040U +#define LRFDRFE_MISC0_DLYPHVALID_CKVD16_0_PER 0x00000000U + +// Field: [5:4] DLYCANCRS +// +// Cancellation path coarse delay +// +// Coarse tune latency for cancellation path in relation to the addition path +// (when modulating). The final delay is the sum of coarse delay and fine +// delay. +// ENUMs: +// CKVD64_3_PER Delay by 3 CKVD64 clock periods +// CKVD64_2_PER Delay by 2 CKVD64 clock periods +// CKVD64_1_PER Delay by 1 CKVD64 clock period +// CKVD64_0_PER Delay by 0 CKVD64 clock periods +#define LRFDRFE_MISC0_DLYCANCRS_W 2U +#define LRFDRFE_MISC0_DLYCANCRS_M 0x00000030U +#define LRFDRFE_MISC0_DLYCANCRS_S 4U +#define LRFDRFE_MISC0_DLYCANCRS_CKVD64_3_PER 0x00000030U +#define LRFDRFE_MISC0_DLYCANCRS_CKVD64_2_PER 0x00000020U +#define LRFDRFE_MISC0_DLYCANCRS_CKVD64_1_PER 0x00000010U +#define LRFDRFE_MISC0_DLYCANCRS_CKVD64_0_PER 0x00000000U + +// Field: [3:2] DLYCANFINE +// +// Cancellation path fine delay +// +// Fine tune latency for cancellation path in relation to the addition path +// (when modulating). The final delay is the sum of coarse delay and fine +// delay. +// ENUMs: +// CKVD16_4_PER Delay by 4 CKVD16 clock periods +// CKVD16_3_PER Delay by 3 CKVD16 clock periods +// CKVD16_2_PER Delay by 2 CKVD16 clock period +// CKVD16_1_PER Delay by 1 CKVD16 clock periods +#define LRFDRFE_MISC0_DLYCANFINE_W 2U +#define LRFDRFE_MISC0_DLYCANFINE_M 0x0000000CU +#define LRFDRFE_MISC0_DLYCANFINE_S 2U +#define LRFDRFE_MISC0_DLYCANFINE_CKVD16_4_PER 0x0000000CU +#define LRFDRFE_MISC0_DLYCANFINE_CKVD16_3_PER 0x00000008U +#define LRFDRFE_MISC0_DLYCANFINE_CKVD16_2_PER 0x00000004U +#define LRFDRFE_MISC0_DLYCANFINE_CKVD16_1_PER 0x00000000U + +// Field: [1:0] DLYADD +// +// Addition path delay +// +// Field specifies additional latency on the modulation data towards antenna. +// ENUMs: +// CKVD64_3_PER Delay by 3 CKVD64 clock periods +// CKVD64_2_PER Delay by 2 CKVD64 clock periods +// CKVD64_1_PER Delay by 1 CKVD64 clock period +// CKVD64_0_PER Delay by 0 CKVD64 clock periods +#define LRFDRFE_MISC0_DLYADD_W 2U +#define LRFDRFE_MISC0_DLYADD_M 0x00000003U +#define LRFDRFE_MISC0_DLYADD_S 0U +#define LRFDRFE_MISC0_DLYADD_CKVD64_3_PER 0x00000003U +#define LRFDRFE_MISC0_DLYADD_CKVD64_2_PER 0x00000002U +#define LRFDRFE_MISC0_DLYADD_CKVD64_1_PER 0x00000001U +#define LRFDRFE_MISC0_DLYADD_CKVD64_0_PER 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MISC1 +// +//***************************************************************************** +// Field: [14] FCDEMCLK +// +// Bitmask to enable additive terms in INL correction +// +// See implementation spec for details +// ENUMs: +// CKVD64 ckvd64 clock used for update upper and lower DWA +// DEM +// CKCD16 ckvd16 clock used for update upper and lower DWA +// DEM +#define LRFDRFE_MISC1_FCDEMCLK 0x00004000U +#define LRFDRFE_MISC1_FCDEMCLK_M 0x00004000U +#define LRFDRFE_MISC1_FCDEMCLK_S 14U +#define LRFDRFE_MISC1_FCDEMCLK_CKVD64 0x00004000U +#define LRFDRFE_MISC1_FCDEMCLK_CKCD16 0x00000000U + +// Field: [13:12] FCDEMUPD +// +// Configures dynamic element matching of fine code +// ENUMs: +// SDM_XOR_PH_ERR phase_error[0] xor SDM[1] +// SDM SDM[1] (this value depends on DEM for SDM) +// PH_ERR phase_error[0]. (Phase error is 6.11s ) +// DEFAULT Default: Update both DWAs always at rising edge of +// selected clock +#define LRFDRFE_MISC1_FCDEMUPD_W 2U +#define LRFDRFE_MISC1_FCDEMUPD_M 0x00003000U +#define LRFDRFE_MISC1_FCDEMUPD_S 12U +#define LRFDRFE_MISC1_FCDEMUPD_SDM_XOR_PH_ERR 0x00003000U +#define LRFDRFE_MISC1_FCDEMUPD_SDM 0x00002000U +#define LRFDRFE_MISC1_FCDEMUPD_PH_ERR 0x00001000U +#define LRFDRFE_MISC1_FCDEMUPD_DEFAULT 0x00000000U + +// Field: [11:6] TDCINL +// +// Bitmask to enable additive terms in INL correction +// +// See implementation spec for details +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE_MISC1_TDCINL_W 6U +#define LRFDRFE_MISC1_TDCINL_M 0x00000FC0U +#define LRFDRFE_MISC1_TDCINL_S 6U +#define LRFDRFE_MISC1_TDCINL_ONES 0x00000FC0U +#define LRFDRFE_MISC1_TDCINL_ZEROS 0x00000000U + +// Field: [5] TDCINLCTL +// +// Enables INL correction of TDC +// ENUMs: +// EN Enables INL correction of TDC +// DIS Disabled INL correction +#define LRFDRFE_MISC1_TDCINLCTL 0x00000020U +#define LRFDRFE_MISC1_TDCINLCTL_M 0x00000020U +#define LRFDRFE_MISC1_TDCINLCTL_S 5U +#define LRFDRFE_MISC1_TDCINLCTL_EN 0x00000020U +#define LRFDRFE_MISC1_TDCINLCTL_DIS 0x00000000U + +// Field: [4] PHINIT +// +// Decides if there is known phase relationship between reference clock and RF +// ENUMs: +// UNKNOWN Unknown phase +// KNOWN Known phase +#define LRFDRFE_MISC1_PHINIT 0x00000010U +#define LRFDRFE_MISC1_PHINIT_M 0x00000010U +#define LRFDRFE_MISC1_PHINIT_S 4U +#define LRFDRFE_MISC1_PHINIT_UNKNOWN 0x00000010U +#define LRFDRFE_MISC1_PHINIT_KNOWN 0x00000000U + +// Field: [3] SDMOOVRCTL +// +// Force SDMOOVR towards DCO +// ENUMs: +// EN Enable SDM output override +// DIS Disable SDM output override +#define LRFDRFE_MISC1_SDMOOVRCTL 0x00000008U +#define LRFDRFE_MISC1_SDMOOVRCTL_M 0x00000008U +#define LRFDRFE_MISC1_SDMOOVRCTL_S 3U +#define LRFDRFE_MISC1_SDMOOVRCTL_EN 0x00000008U +#define LRFDRFE_MISC1_SDMOOVRCTL_DIS 0x00000000U + +// Field: [2:0] SDMOOVR +// +// SDM output code override +// +// When MISC1.SDMOOVRCTL = EN, field value overrides the 3-bit SDM output to +// DCO. +// When MISC1.SDMOOVRCTL = DIS, SDM takes 8-bit input and modulates the 3-bit +// output to DCO. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MISC1_SDMOOVR_W 3U +#define LRFDRFE_MISC1_SDMOOVR_M 0x00000007U +#define LRFDRFE_MISC1_SDMOOVR_S 0U +#define LRFDRFE_MISC1_SDMOOVR_ALLONES 0x00000007U +#define LRFDRFE_MISC1_SDMOOVR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_LF0 +// +//***************************************************************************** +// Field: [12] KIPREC +// +// FIR integral gain precision +// +// When numerical value of KI is lower than 16-1/256, high precision can be +// enabled. +// FIR loop filter gets reinitialized with the current value whenever: +// - DLO moves from calibration operation to closed-loop state. +// - DLO moves from open-loop operation to closed-loop operation. +// - DLO is in closed-loop operation and there is a change on loop control set. +// See DLOCTL0.LOOPUPD. +// ENUMs: +// HIGH KI encoding is <4.08> +// LOW KI encoding is <12.0u> +#define LRFDRFE_LF0_KIPREC 0x00001000U +#define LRFDRFE_LF0_KIPREC_M 0x00001000U +#define LRFDRFE_LF0_KIPREC_S 12U +#define LRFDRFE_LF0_KIPREC_HIGH 0x00001000U +#define LRFDRFE_LF0_KIPREC_LOW 0x00000000U + +// Field: [11:0] KI +// +// FIR integral gain +// +// Field sets the integral gain in the FIR loop filter. +// +// FIR_KI = pi^2 * f3db^2 / (FREF * KDCO * DF^2) +// +// where DF is the desired damping factor. Lower damping factor gives lower +// phase margin in the loop. Typically damping factors in the range 0.75 to 1 +// is used. Note that equations above become more accurate when DF > 1. +// +// Encoding is given by KIPREC setting. Examples: +// +// When KIPREC = 0: +// +// 0x000: KI = 0 +// 0x001: KI = 1 +// 0xFFF: KI = 4095 +// +// When KIPREC = 1: +// +// 0x000: KI = 0x0.00 = 0.0 +// 0x001: KI = 0x0.01 = 0.00390625 +// 0x002: KI = 0x0.02 = 0.0078125 +// 0x004: KI = 0x0.40 = 0.25 +// 0x008: KI = 0x0.80 = 0.5 +// 0xFF0: KI = 0xF.F0 = 15.9375 +// 0xFFF: KI = 0xF.FF = 15.99609375 +// +// FIR loop filter gets reinitialized with the current value whenever: +// - DLO moves from calibration operation to closed-loop state. +// - DLO moves from open-loop operation to closed-loop operation. +// - DLO is in closed-loop operation and there is a change on loop control set. +// See DLOCTL0.LOOPUPD. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_LF0_KI_W 12U +#define LRFDRFE_LF0_KI_M 0x00000FFFU +#define LRFDRFE_LF0_KI_S 0U +#define LRFDRFE_LF0_KI_ALLONES 0x00000FFFU +#define LRFDRFE_LF0_KI_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_LF1 +// +//***************************************************************************** +// Field: [13:0] KP +// +// FIR proportional gain +// +// Field sets the proportional gain in FIR loop filter. +// +// FIR_KP = 2*pi* f3db / KDCO +// +// Encoding is <14.0u>: +// 0x0000: Minimum proportional gain +// 0x3FFF: Maximum proportional gain +// +// FIR loop filter gets reinitialized with the current value whenever DLO moves +// from calibration or open-loop operation to closed-loop operation. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_LF1_KP_W 14U +#define LRFDRFE_LF1_KP_M 0x00003FFFU +#define LRFDRFE_LF1_KP_S 0U +#define LRFDRFE_LF1_KP_ALLONES 0x00003FFFU +#define LRFDRFE_LF1_KP_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PHEDISC +// +//***************************************************************************** +// Field: [13:10] CNT +// +// Phase error discard count +// +// When phase error discarding is enabled, FIR loop filter does not update if: +// +// abs(phase error) > PHEDISC_THR / 64 +// +// Update loop if this happens for CNT consecutive REFCLK periods. +// +// Set DLOCTL1.PHEDISC = EN to enable phase error discarding. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PHEDISC_CNT_W 4U +#define LRFDRFE_PHEDISC_CNT_M 0x00003C00U +#define LRFDRFE_PHEDISC_CNT_S 10U +#define LRFDRFE_PHEDISC_CNT_ALLONES 0x00003C00U +#define LRFDRFE_PHEDISC_CNT_ALLZEROS 0x00000000U + +// Field: [9:0] THR +// +// Phase error discard threshold +// +// When phase error discarding is enabled, FIR loop filter does not update if: +// +// abs(phase error) > PHEDISC_THR / 64 +// +// Update loop if this happens for CNT consecutive REFCLK periods. +// +// Set DLOCTL1.PHEDISC = EN to enable phase error discarding. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PHEDISC_THR_W 10U +#define LRFDRFE_PHEDISC_THR_M 0x000003FFU +#define LRFDRFE_PHEDISC_THR_S 0U +#define LRFDRFE_PHEDISC_THR_ALLONES 0x000003FFU +#define LRFDRFE_PHEDISC_THR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PHINIT +// +//***************************************************************************** +// Field: [7:0] OFF +// +// Reference phase offset +// +// Field initializes phase offset between CKVD and reference clock. +// +// Encoding of field is <0.8u>. +// +// Examples: +// 0x40: 25% of CKVD clock period +// 0x80: 50% of CKVD clock period +// 0xC0: 75% of CKVD clock period +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PHINIT_OFF_W 8U +#define LRFDRFE_PHINIT_OFF_M 0x000000FFU +#define LRFDRFE_PHINIT_OFF_S 0U +#define LRFDRFE_PHINIT_OFF_ALLONES 0x000000FFU +#define LRFDRFE_PHINIT_OFF_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLMON0 +// +//***************************************************************************** +// Field: [15:14] PHELOLCNT +// +// Phase error lock loss count +// +// Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2: +// +// - for PHELOLCNT consecutive periods of REFCLK . +// - and loop filter fincode overflows or underflows. +// +// When either of these conditions occur DLOEV.LOL flag gets set in REFCLK +// domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for +// further description. +// ENUMs: +// REFCLK_128_PER Threshold count is 128 REFCLK periods +// REFCLK_64_PER Threshold count is 64 REFCLK periods +// REFCLK_32_PER Threshold count is 32 REFCLK periods +// REFCLK_16_PER Threshold count is 16 REFCLK periods +#define LRFDRFE_PLLMON0_PHELOLCNT_W 2U +#define LRFDRFE_PLLMON0_PHELOLCNT_M 0x0000C000U +#define LRFDRFE_PLLMON0_PHELOLCNT_S 14U +#define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_128_PER 0x0000C000U +#define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_64_PER 0x00008000U +#define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_32_PER 0x00004000U +#define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_16_PER 0x00000000U + +// Field: [13:8] PHELOLTHR +// +// Phase error lock loss threshold +// +// Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2: +// +// - for PLLMON0.PHELOLCNT consecutive periods of REFCLK . +// - and loop filter fincode overflows or underflows. +// +// When either of these conditions occur DLOEV.LOL flag gets set in REFCLK +// domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for +// further description. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLMON0_PHELOLTHR_W 6U +#define LRFDRFE_PLLMON0_PHELOLTHR_M 0x00003F00U +#define LRFDRFE_PLLMON0_PHELOLTHR_S 8U +#define LRFDRFE_PLLMON0_PHELOLTHR_ALLONES 0x00003F00U +#define LRFDRFE_PLLMON0_PHELOLTHR_ALLZEROS 0x00000000U + +// Field: [6:0] FCTHR +// +// Fine code threshold +// +// Field sets two symmetric thresholds, with encoding <7.8u>: +// FCLWTHR = {FCTHR, 8'b0} +// FCUPTHR = {8'b0111111 - FCTHR), 8'b1} +// +// The PLL monitor compares the final 15-bit fine code sent to DCO and SDM to +// these thresholds: +// +// When fine code > FCUPTHR, DLOEV.FCABVTHR flag gets set in REFCLK domain. +// When fine code < FCLWTHR, DLOEV.FCBLWTHR flag gets set in REFCLK domain. +// +// In both cases synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for +// further description. +// +// INTERNAL NOTE: +// * default value should be 0 so that detector is effectively disabled for any +// fine code. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLMON0_FCTHR_W 7U +#define LRFDRFE_PLLMON0_FCTHR_M 0x0000007FU +#define LRFDRFE_PLLMON0_FCTHR_S 0U +#define LRFDRFE_PLLMON0_FCTHR_ALLONES 0x0000007FU +#define LRFDRFE_PLLMON0_FCTHR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLMON1 +// +//***************************************************************************** +// Field: [12:8] PHELOCKCNT +// +// Phase error lock count +// +// Declare lock for PLL if: +// +// abs(phase error) < PHELOCKTHR / 64 +// +// for PHELOCKCNT*4 consecutive periods of default REFCLK. When this happens +// DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is +// asserted. See DLOCTL1.PLLMON for further description. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLMON1_PHELOCKCNT_W 5U +#define LRFDRFE_PLLMON1_PHELOCKCNT_M 0x00001F00U +#define LRFDRFE_PLLMON1_PHELOCKCNT_S 8U +#define LRFDRFE_PLLMON1_PHELOCKCNT_ALLONES 0x00001F00U +#define LRFDRFE_PLLMON1_PHELOCKCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PHELOCKTHR +// +// Phase error lock threshold +// +// Declare lock for PLL if: +// +// abs(phase error) < PHELOCKTHR / 64 +// +// for PHELOCKCNT *4 consecutive periods of default REFCLK.When this happens +// DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is +// asserted. See DLOCTL1.PLLMON for further description. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLMON1_PHELOCKTHR_W 8U +#define LRFDRFE_PLLMON1_PHELOCKTHR_M 0x000000FFU +#define LRFDRFE_PLLMON1_PHELOCKTHR_S 0U +#define LRFDRFE_PLLMON1_PHELOCKTHR_ALLONES 0x000000FFU +#define LRFDRFE_PLLMON1_PHELOCKTHR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MOD0 +// +//***************************************************************************** +// Field: [12:11] SCHEME +// +// Scheme +// +// Field sets the modulation scheme of the DLO +// ENUMs: +// TWO_POINT_MOD_FRF 2-point modulation with FRF resolution +// +// MOD_RES = FRF / +// 2^(21+CANPTHGAIN) +// +// Scheme supports both open +// -and closed-loop operation. Scheme allows wider +// modulation bandwiths than INLOOP_MOD_FRF. +// INLOOP_MOD_FRF In-loop modulation with FRF resolution +// +// MOD_RES = FRF / +// 2^(21+CANPTHGAIN) +// INLOOP_MOD_FREF In-loop modulation with FREF resolution +// +// MOD_RES = FREF / +// (DIVIDER/2) / 2^(15+CANPTHGAIN) +// +// DIV.RATIO determines +// DIVIDER configuration. Scheme only supports +// closed-loop operation. +// NC No connect +// +// Modulator output does not +// add to frequencey control word from PLL. +#define LRFDRFE_MOD0_SCHEME_W 2U +#define LRFDRFE_MOD0_SCHEME_M 0x00001800U +#define LRFDRFE_MOD0_SCHEME_S 11U +#define LRFDRFE_MOD0_SCHEME_TWO_POINT_MOD_FRF 0x00001800U +#define LRFDRFE_MOD0_SCHEME_INLOOP_MOD_FRF 0x00001000U +#define LRFDRFE_MOD0_SCHEME_INLOOP_MOD_FREF 0x00000800U +#define LRFDRFE_MOD0_SCHEME_NC 0x00000000U + +// Field: [10:8] SYMSHP +// +// Symbol shaper +// ENUMs: +// CHIRP Chirp modulation +// SHAPEDZIGBEE Use Shaped 802.15.4 modulation +// PCWSPSK Use piecewise linear PSK shaper defined by +// SHAPECFG* registers. +// ZIGBEE Use unshaped zigbee +// SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* +// registers. +#define LRFDRFE_MOD0_SYMSHP_W 3U +#define LRFDRFE_MOD0_SYMSHP_M 0x00000700U +#define LRFDRFE_MOD0_SYMSHP_S 8U +#define LRFDRFE_MOD0_SYMSHP_CHIRP 0x00000400U +#define LRFDRFE_MOD0_SYMSHP_SHAPEDZIGBEE 0x00000300U +#define LRFDRFE_MOD0_SYMSHP_PCWSPSK 0x00000200U +#define LRFDRFE_MOD0_SYMSHP_ZIGBEE 0x00000100U +#define LRFDRFE_MOD0_SYMSHP_SHAPEDFSK 0x00000000U + +// Field: [7:6] CANPTHGAIN +// +// Cancellation path gain +// +// The cancellation phase is scaled by a configurable gain, which effectively +// sets the modulator frequency control word resolution. To calculate the +// resolution, use the binary value of this field in equations in SCHEME. +// ENUMs: +// TWO_POW_M_18 POW(2,-18) +// TWO_POW_M_17 POW(2,-17) +// TWO_POW_M_16 POW(2,-16) +// TWO_POW_M_15 POW(2,-15) +#define LRFDRFE_MOD0_CANPTHGAIN_W 2U +#define LRFDRFE_MOD0_CANPTHGAIN_M 0x000000C0U +#define LRFDRFE_MOD0_CANPTHGAIN_S 6U +#define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_18 0x000000C0U +#define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_17 0x00000080U +#define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_16 0x00000040U +#define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_15 0x00000000U + +// Field: [5:4] SHPGAIN +// +// Shape gain +// +// Field sets the scaling factor for shape elements in DTX0 - DTX5. Both the +// scaling factor and shape element values are generated offline for a certain +// frequency deviation. +// +// INTERNAL NOTE: +// * Please refer to +// https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Architecture/Radio%20System/cc26xx_modem_spec.doc +// for how the SHPGAIN and shape elements together defines the frequency +// deviation for different modes. +// * The scaling factor is is really as follows: +// X1 = DIV_BY_4 +// X2 = DIV_BY_2 +// X4 = DIV_BY_1 +// X8 = DIV_BY_0P5 +// Will not update to reflect this as the matlab gain output === SHPGAIN. +// ENUMs: +// X8 Shape gain = 8 +// X4 Shape gain = 4 +// X2 Shape gain = 2 +// X1 Shape gain = 1 +#define LRFDRFE_MOD0_SHPGAIN_W 2U +#define LRFDRFE_MOD0_SHPGAIN_M 0x00000030U +#define LRFDRFE_MOD0_SHPGAIN_S 4U +#define LRFDRFE_MOD0_SHPGAIN_X8 0x00000030U +#define LRFDRFE_MOD0_SHPGAIN_X4 0x00000020U +#define LRFDRFE_MOD0_SHPGAIN_X2 0x00000010U +#define LRFDRFE_MOD0_SHPGAIN_X1 0x00000000U + +// Field: [3:2] INTPFACT +// +// Interpolation factor +// +// Field sets the interpolation factor of the shape filter. +// +// INTERNAL NOTE: +// Please refer to +// https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Architecture/Radio%20System/cc26xx_modem_spec.doc +// for more detailed description. +// ENUMs: +// ILLEGAL1 Illegal, unsupported setting +// INTP_BY_32 Interpolate by 32 +// INTP_BY_16 Interpolate by 16 +// ILLEGAL0 Illegal, unsupported setting +#define LRFDRFE_MOD0_INTPFACT_W 2U +#define LRFDRFE_MOD0_INTPFACT_M 0x0000000CU +#define LRFDRFE_MOD0_INTPFACT_S 2U +#define LRFDRFE_MOD0_INTPFACT_ILLEGAL1 0x0000000CU +#define LRFDRFE_MOD0_INTPFACT_INTP_BY_32 0x00000008U +#define LRFDRFE_MOD0_INTPFACT_INTP_BY_16 0x00000004U +#define LRFDRFE_MOD0_INTPFACT_ILLEGAL0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MOD1 +// +//***************************************************************************** +// Field: [11:0] FOFF +// +// Frequency Offset +// +// Field configures the optional intermediate frequency (IF) used in TX or RX. +// +// IF = FRF / 2^(21+CANPTHGAIN) * FOFF +// +// Encoding is <12.0s>. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MOD1_FOFF_W 12U +#define LRFDRFE_MOD1_FOFF_M 0x00000FFFU +#define LRFDRFE_MOD1_FOFF_S 0U +#define LRFDRFE_MOD1_FOFF_ALLONES 0x00000FFFU +#define LRFDRFE_MOD1_FOFF_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX0 +// +//***************************************************************************** +// Field: [15:8] SHP1 +// +// Shape element 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX0_SHP1_W 8U +#define LRFDRFE_DTX0_SHP1_M 0x0000FF00U +#define LRFDRFE_DTX0_SHP1_S 8U +#define LRFDRFE_DTX0_SHP1_ALLONES 0x0000FF00U +#define LRFDRFE_DTX0_SHP1_ALLZEROS 0x00000000U + +// Field: [7:0] SHP0 +// +// Shape element 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX0_SHP0_W 8U +#define LRFDRFE_DTX0_SHP0_M 0x000000FFU +#define LRFDRFE_DTX0_SHP0_S 0U +#define LRFDRFE_DTX0_SHP0_ALLONES 0x000000FFU +#define LRFDRFE_DTX0_SHP0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX1 +// +//***************************************************************************** +// Field: [15:8] SHP3 +// +// Shape element 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX1_SHP3_W 8U +#define LRFDRFE_DTX1_SHP3_M 0x0000FF00U +#define LRFDRFE_DTX1_SHP3_S 8U +#define LRFDRFE_DTX1_SHP3_ALLONES 0x0000FF00U +#define LRFDRFE_DTX1_SHP3_ALLZEROS 0x00000000U + +// Field: [7:0] SHP2 +// +// Shape element 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX1_SHP2_W 8U +#define LRFDRFE_DTX1_SHP2_M 0x000000FFU +#define LRFDRFE_DTX1_SHP2_S 0U +#define LRFDRFE_DTX1_SHP2_ALLONES 0x000000FFU +#define LRFDRFE_DTX1_SHP2_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX2 +// +//***************************************************************************** +// Field: [15:8] SHP5 +// +// Shape element 5 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX2_SHP5_W 8U +#define LRFDRFE_DTX2_SHP5_M 0x0000FF00U +#define LRFDRFE_DTX2_SHP5_S 8U +#define LRFDRFE_DTX2_SHP5_ALLONES 0x0000FF00U +#define LRFDRFE_DTX2_SHP5_ALLZEROS 0x00000000U + +// Field: [7:0] SHP4 +// +// Shape element 4 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX2_SHP4_W 8U +#define LRFDRFE_DTX2_SHP4_M 0x000000FFU +#define LRFDRFE_DTX2_SHP4_S 0U +#define LRFDRFE_DTX2_SHP4_ALLONES 0x000000FFU +#define LRFDRFE_DTX2_SHP4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX3 +// +//***************************************************************************** +// Field: [15:8] SHP7 +// +// Shape element 7 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX3_SHP7_W 8U +#define LRFDRFE_DTX3_SHP7_M 0x0000FF00U +#define LRFDRFE_DTX3_SHP7_S 8U +#define LRFDRFE_DTX3_SHP7_ALLONES 0x0000FF00U +#define LRFDRFE_DTX3_SHP7_ALLZEROS 0x00000000U + +// Field: [7:0] SHP6 +// +// Shape element 6 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX3_SHP6_W 8U +#define LRFDRFE_DTX3_SHP6_M 0x000000FFU +#define LRFDRFE_DTX3_SHP6_S 0U +#define LRFDRFE_DTX3_SHP6_ALLONES 0x000000FFU +#define LRFDRFE_DTX3_SHP6_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX4 +// +//***************************************************************************** +// Field: [15:8] SHP9 +// +// Shape element 9 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX4_SHP9_W 8U +#define LRFDRFE_DTX4_SHP9_M 0x0000FF00U +#define LRFDRFE_DTX4_SHP9_S 8U +#define LRFDRFE_DTX4_SHP9_ALLONES 0x0000FF00U +#define LRFDRFE_DTX4_SHP9_ALLZEROS 0x00000000U + +// Field: [7:0] SHP8 +// +// Shape element 8 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX4_SHP8_W 8U +#define LRFDRFE_DTX4_SHP8_M 0x000000FFU +#define LRFDRFE_DTX4_SHP8_S 0U +#define LRFDRFE_DTX4_SHP8_ALLONES 0x000000FFU +#define LRFDRFE_DTX4_SHP8_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX5 +// +//***************************************************************************** +// Field: [15:8] SHP11 +// +// Shape element 11 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX5_SHP11_W 8U +#define LRFDRFE_DTX5_SHP11_M 0x0000FF00U +#define LRFDRFE_DTX5_SHP11_S 8U +#define LRFDRFE_DTX5_SHP11_ALLONES 0x0000FF00U +#define LRFDRFE_DTX5_SHP11_ALLZEROS 0x00000000U + +// Field: [7:0] SHP10 +// +// Shape element 10 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX5_SHP10_W 8U +#define LRFDRFE_DTX5_SHP10_M 0x000000FFU +#define LRFDRFE_DTX5_SHP10_S 0U +#define LRFDRFE_DTX5_SHP10_ALLONES 0x000000FFU +#define LRFDRFE_DTX5_SHP10_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX6 +// +//***************************************************************************** +// Field: [15:8] SHP13 +// +// Shape element 13 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX6_SHP13_W 8U +#define LRFDRFE_DTX6_SHP13_M 0x0000FF00U +#define LRFDRFE_DTX6_SHP13_S 8U +#define LRFDRFE_DTX6_SHP13_ALLONES 0x0000FF00U +#define LRFDRFE_DTX6_SHP13_ALLZEROS 0x00000000U + +// Field: [7:0] SHP12 +// +// Shape element 12 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX6_SHP12_W 8U +#define LRFDRFE_DTX6_SHP12_M 0x000000FFU +#define LRFDRFE_DTX6_SHP12_S 0U +#define LRFDRFE_DTX6_SHP12_ALLONES 0x000000FFU +#define LRFDRFE_DTX6_SHP12_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX7 +// +//***************************************************************************** +// Field: [15:8] SHP15 +// +// Shape element 15 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX7_SHP15_W 8U +#define LRFDRFE_DTX7_SHP15_M 0x0000FF00U +#define LRFDRFE_DTX7_SHP15_S 8U +#define LRFDRFE_DTX7_SHP15_ALLONES 0x0000FF00U +#define LRFDRFE_DTX7_SHP15_ALLZEROS 0x00000000U + +// Field: [7:0] SHP14 +// +// Shape element 14 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX7_SHP14_W 8U +#define LRFDRFE_DTX7_SHP14_M 0x000000FFU +#define LRFDRFE_DTX7_SHP14_S 0U +#define LRFDRFE_DTX7_SHP14_ALLONES 0x000000FFU +#define LRFDRFE_DTX7_SHP14_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX8 +// +//***************************************************************************** +// Field: [15:8] SHP17 +// +// Shape element 17 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX8_SHP17_W 8U +#define LRFDRFE_DTX8_SHP17_M 0x0000FF00U +#define LRFDRFE_DTX8_SHP17_S 8U +#define LRFDRFE_DTX8_SHP17_ALLONES 0x0000FF00U +#define LRFDRFE_DTX8_SHP17_ALLZEROS 0x00000000U + +// Field: [7:0] SHP16 +// +// Shape element 16 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX8_SHP16_W 8U +#define LRFDRFE_DTX8_SHP16_M 0x000000FFU +#define LRFDRFE_DTX8_SHP16_S 0U +#define LRFDRFE_DTX8_SHP16_ALLONES 0x000000FFU +#define LRFDRFE_DTX8_SHP16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX9 +// +//***************************************************************************** +// Field: [15:8] SHP19 +// +// Shape element 19 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX9_SHP19_W 8U +#define LRFDRFE_DTX9_SHP19_M 0x0000FF00U +#define LRFDRFE_DTX9_SHP19_S 8U +#define LRFDRFE_DTX9_SHP19_ALLONES 0x0000FF00U +#define LRFDRFE_DTX9_SHP19_ALLZEROS 0x00000000U + +// Field: [7:0] SHP18 +// +// Shape element 18 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX9_SHP18_W 8U +#define LRFDRFE_DTX9_SHP18_M 0x000000FFU +#define LRFDRFE_DTX9_SHP18_S 0U +#define LRFDRFE_DTX9_SHP18_ALLONES 0x000000FFU +#define LRFDRFE_DTX9_SHP18_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX10 +// +//***************************************************************************** +// Field: [15:8] SHP21 +// +// Shape element 21 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX10_SHP21_W 8U +#define LRFDRFE_DTX10_SHP21_M 0x0000FF00U +#define LRFDRFE_DTX10_SHP21_S 8U +#define LRFDRFE_DTX10_SHP21_ALLONES 0x0000FF00U +#define LRFDRFE_DTX10_SHP21_ALLZEROS 0x00000000U + +// Field: [7:0] SHP20 +// +// Shape element 20 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX10_SHP20_W 8U +#define LRFDRFE_DTX10_SHP20_M 0x000000FFU +#define LRFDRFE_DTX10_SHP20_S 0U +#define LRFDRFE_DTX10_SHP20_ALLONES 0x000000FFU +#define LRFDRFE_DTX10_SHP20_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTX11 +// +//***************************************************************************** +// Field: [15:8] SHP23 +// +// Shape element 23 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX11_SHP23_W 8U +#define LRFDRFE_DTX11_SHP23_M 0x0000FF00U +#define LRFDRFE_DTX11_SHP23_S 8U +#define LRFDRFE_DTX11_SHP23_ALLONES 0x0000FF00U +#define LRFDRFE_DTX11_SHP23_ALLZEROS 0x00000000U + +// Field: [7:0] SHP22 +// +// Shape element 22 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTX11_SHP22_W 8U +#define LRFDRFE_DTX11_SHP22_M 0x000000FFU +#define LRFDRFE_DTX11_SHP22_S 0U +#define LRFDRFE_DTX11_SHP22_ALLONES 0x000000FFU +#define LRFDRFE_DTX11_SHP22_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLM0L +// +//***************************************************************************** +// Field: [15:2] VALLSB +// +// PLLM0 value +// +// Field sets the desired output frequency of the PLL, FRF, using the default +// PLL reference frequency, according to: +// +// M-value = FRF * (DIVIDER/2) / FREF0 +// +// Field encoding is <12.18u> +// +// PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER. +// +// INTERNAL NOTE: +// * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM0L_VALLSB_W 14U +#define LRFDRFE_PLLM0L_VALLSB_M 0x0000FFFCU +#define LRFDRFE_PLLM0L_VALLSB_S 2U +#define LRFDRFE_PLLM0L_VALLSB_ALLONES 0x0000FFFCU +#define LRFDRFE_PLLM0L_VALLSB_ALLZEROS 0x00000000U + +// Field: [1:0] SPARE0 +// +// SPARE0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM0L_SPARE0_W 2U +#define LRFDRFE_PLLM0L_SPARE0_M 0x00000003U +#define LRFDRFE_PLLM0L_SPARE0_S 0U +#define LRFDRFE_PLLM0L_SPARE0_ALLONES 0x00000003U +#define LRFDRFE_PLLM0L_SPARE0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLM0H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// PLLM0 value +// +// Field sets the desired output frequency of the PLL, FRF, using the default +// PLL reference frequency, according to: +// +// M-value = FRF * (DIVIDER/2) / FREF0 +// +// Field encoding is <12.18u> +// +// PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER. +// +// INTERNAL NOTE: +// * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM0H_VALMSB_W 16U +#define LRFDRFE_PLLM0H_VALMSB_M 0x0000FFFFU +#define LRFDRFE_PLLM0H_VALMSB_S 0U +#define LRFDRFE_PLLM0H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_PLLM0H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLM1L +// +//***************************************************************************** +// Field: [15:2] VALLSB +// +// PLLM1 value +// +// Field sets the desired output frequency of the PLL, FRF, using the default +// PLL reference frequency, according to: +// +// M-value = FRF * (DIVIDER/2) / FREF1 +// +// Field encoding is <12.18u> +// +// PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER. +// +// INTERNAL NOTE: +// * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM1L_VALLSB_W 14U +#define LRFDRFE_PLLM1L_VALLSB_M 0x0000FFFCU +#define LRFDRFE_PLLM1L_VALLSB_S 2U +#define LRFDRFE_PLLM1L_VALLSB_ALLONES 0x0000FFFCU +#define LRFDRFE_PLLM1L_VALLSB_ALLZEROS 0x00000000U + +// Field: [1:0] SPARE0 +// +// SPARE0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM1L_SPARE0_W 2U +#define LRFDRFE_PLLM1L_SPARE0_M 0x00000003U +#define LRFDRFE_PLLM1L_SPARE0_S 0U +#define LRFDRFE_PLLM1L_SPARE0_ALLONES 0x00000003U +#define LRFDRFE_PLLM1L_SPARE0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PLLM1H +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// PLLM1 value +// +// Field sets the desired output frequency of the PLL, FRF, using the default +// PLL reference frequency, according to: +// +// M-value = FRF * (DIVIDER/2) / FREF1 +// +// Field encoding is <12.18u> +// +// PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER. +// +// INTERNAL NOTE: +// * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PLLM1H_VALMSB_W 16U +#define LRFDRFE_PLLM1H_VALMSB_M 0x0000FFFFU +#define LRFDRFE_PLLM1H_VALMSB_S 0U +#define LRFDRFE_PLLM1H_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_PLLM1H_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CALMCRS +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Coarse SAR m-value +// +// Field sets the desired output frequency of the PLL, FRF, during coarse SAR, +// according to: +// +// VAL = FRF * (DIVIDER/2) / COARSE_CALIB_FREF +// +// Field encoding is <16u>. +// +// PRE2.CRSCALDIV determines COARSE_CALIB_FREF. DIV.RATIO determines DIVIDER. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CALMCRS_VAL_W 16U +#define LRFDRFE_CALMCRS_VAL_M 0x0000FFFFU +#define LRFDRFE_CALMCRS_VAL_S 0U +#define LRFDRFE_CALMCRS_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_CALMCRS_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CALMMID +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Mid SAR m-value +// +// Field sets the desired output frequency of the PLL, FRF, during mid SAR, +// according to: +// +// VAL = FRF * (DIVIDER/2) / MID_CALIB_FREF +// +// Field encoding is <16u>. +// +// PRE2.MIDCALDIVLSB and PRE3.MIDCALDIVMSB determines MID_CALIB_FREF. +// DIV.RATIO determines DIVIDER. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CALMMID_VAL_W 16U +#define LRFDRFE_CALMMID_VAL_M 0x0000FFFFU +#define LRFDRFE_CALMMID_VAL_S 0U +#define LRFDRFE_CALMMID_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_CALMMID_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_REFDIV +// +//***************************************************************************** +// Field: [15:0] LOAD +// +// Load value for 16-bit REFCLK prescaler +// +// The REFCLK prescaler is used when DLOCTL0.LOOPUPD bit-2 = 1. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_REFDIV_LOAD_W 16U +#define LRFDRFE_REFDIV_LOAD_M 0x0000FFFFU +#define LRFDRFE_REFDIV_LOAD_S 0U +#define LRFDRFE_REFDIV_LOAD_ALLONES 0x0000FFFFU +#define LRFDRFE_REFDIV_LOAD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DLOCTL0 +// +//***************************************************************************** +// Field: [10:8] TDCSTOP +// +// TDC stop configuration +// +// During TDC calibration the value specifies the pulse duration used to +// calculate the TDC gain as number of CKVD periods (2 / FDCO). Value +// effectively sets the resolution of the FW-calculated CAL2.KTDCINV. +// +// Otherwise, the TDC stop delay is programmable in units of CKVD clock +// periods. The stop delay is either static or randomly decided per reference +// clock period. The latter is referred to as TDC stop-time dithering. +// +// 000: TDC stops when flop 0 becomes 1. During TDC calibration pulse length is +// 1 CKVD period. +// 001: TDC stops when flop 1 becomes 1. During TDC calibration pulse length is +// 2 CKVD periods. +// 010: TDC stops when flop 2 becomes 1. During TDC calibration pulse length is +// 3 CKVD periods. +// 011: TDC stops when flop 3 becomes 1. During TDC calibration pulse length is +// 4 CKVD periods. +// 1xx: TDC stops when a randomly chosen flop becomes 1. Do not use for TDC +// calibration. +// ENUMs: +// OPEN Open-loop operation +// CLOSED Closed-loop operation +#define LRFDRFE_DLOCTL0_TDCSTOP_W 3U +#define LRFDRFE_DLOCTL0_TDCSTOP_M 0x00000700U +#define LRFDRFE_DLOCTL0_TDCSTOP_S 8U +#define LRFDRFE_DLOCTL0_TDCSTOP_OPEN 0x00000100U +#define LRFDRFE_DLOCTL0_TDCSTOP_CLOSED 0x00000000U + +// Field: [7] DTSTXTAL +// +// XTALBAW DTST interface control +// +// Configure DTST interface in DTST when interface is disabled. +// ENUMs: +// ONE Enable XTALBAW DTST interface +// ZERO Disable XTALBAW DTST interface +#define LRFDRFE_DLOCTL0_DTSTXTAL 0x00000080U +#define LRFDRFE_DLOCTL0_DTSTXTAL_M 0x00000080U +#define LRFDRFE_DLOCTL0_DTSTXTAL_S 7U +#define LRFDRFE_DLOCTL0_DTSTXTAL_ONE 0x00000080U +#define LRFDRFE_DLOCTL0_DTSTXTAL_ZERO 0x00000000U + +// Field: [6:4] LOOPUPD +// +// Loop update control +// +// The PLL frequency and loop dynamics are controlled through a set of +// configurations of coarse and mid codes, TCD gain, reference clock divider, +// and feedback divider(PLLM). Registers for PLLM and reference clock dividers +// are duplicated to support REFCLK dithering, and/or loop BW gearing. These +// are set 0 and set 1. It is also possible to update all configurations at +// certain events to move the frequency around in the tuning range, and adjust +// the loop bandwidth at the same time. Basically: +// - bit-0: Static control set select (manual switch-FW) +// 0 : select control set 0. +// 1 : select control set 1. +// - bit-1: Dithering select (automatic switch-LFSR) +// 0: Functionality unused. +// 1: LFSR single bit output is used to select control set according to +// bit-0 select rules. Average F_REFCLK to be used in Ki equation is the +// harmonic mean, F_REFCLK = 2/[1/F_REFCLK0 + 1/F_REFCLK1]. +// - bit-2: Timer select (automatic switch-prescaler) +// 0: Functionality unused. +// 1: On every REFDIV.LOAD REFCLK event DLO toggles the control set select. +// FW can update the one not used. +// +// There are restrictions on legal settings and transitions. +// +// INTERNAL NOTE: +// See the implementation specification for explicit details and rules when +// using this register. +// ENUMs: +// ALT Use alternate REF (PLLM1) +// DEF Use default FREF (PLLM0) +#define LRFDRFE_DLOCTL0_LOOPUPD_W 3U +#define LRFDRFE_DLOCTL0_LOOPUPD_M 0x00000070U +#define LRFDRFE_DLOCTL0_LOOPUPD_S 4U +#define LRFDRFE_DLOCTL0_LOOPUPD_ALT 0x00000010U +#define LRFDRFE_DLOCTL0_LOOPUPD_DEF 0x00000000U + +// Field: [3] PH3 +// +// Lock aquisition / calibration phase 3 control +// ENUMs: +// START Close the loop to aquire phase lock, i.e. phase 3 +// of calibration routine. +// HALT Halt DLO FSM after DCO frequency span measurement +// +// When DLO and RFE runs +// KDCO estimation, RFE must compute KDCO from the +// frequency span, and calculate loop filter +// settings to use before lock aquisition. +#define LRFDRFE_DLOCTL0_PH3 0x00000008U +#define LRFDRFE_DLOCTL0_PH3_M 0x00000008U +#define LRFDRFE_DLOCTL0_PH3_S 3U +#define LRFDRFE_DLOCTL0_PH3_START 0x00000008U +#define LRFDRFE_DLOCTL0_PH3_HALT 0x00000000U + +// Field: [2] PH2 +// +// KDCO estimation / calibration phase 2 control +// ENUMs: +// START Start KDCO estimation, i.e. phase 2 of calibration +// routine. +// HALT Halt DLO FSM after TDC calibration measurement +// +// When DLO and RFE runs TDC +// calibration, RFE must use calibration +// measurement to calculcate CAL2.KTDCINV. +#define LRFDRFE_DLOCTL0_PH2 0x00000004U +#define LRFDRFE_DLOCTL0_PH2_M 0x00000004U +#define LRFDRFE_DLOCTL0_PH2_S 2U +#define LRFDRFE_DLOCTL0_PH2_START 0x00000004U +#define LRFDRFE_DLOCTL0_PH2_HALT 0x00000000U + +// Field: [1] LOOPMODE +// +// Loop mode control +// ENUMs: +// OPEN Open-loop operation +// CLOSED Closed-loop operation +#define LRFDRFE_DLOCTL0_LOOPMODE 0x00000002U +#define LRFDRFE_DLOCTL0_LOOPMODE_M 0x00000002U +#define LRFDRFE_DLOCTL0_LOOPMODE_S 1U +#define LRFDRFE_DLOCTL0_LOOPMODE_OPEN 0x00000002U +#define LRFDRFE_DLOCTL0_LOOPMODE_CLOSED 0x00000000U + +// Field: [0] RSTN +// +// DLO reset +// +// DLO active low reset. The DLO has several static inputs that all needs to be +// set prior to releasing reset. +// +// INTERNAL NOTE: +// * Consult with LRFDLO implementation specification to see classification of +// static, pseudo-static, and dynamic inputs. +// ENUMs: +// ACTIVE DLO is not held in reset +// RESET DLO is reset +#define LRFDRFE_DLOCTL0_RSTN 0x00000001U +#define LRFDRFE_DLOCTL0_RSTN_M 0x00000001U +#define LRFDRFE_DLOCTL0_RSTN_S 0U +#define LRFDRFE_DLOCTL0_RSTN_ACTIVE 0x00000001U +#define LRFDRFE_DLOCTL0_RSTN_RESET 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DLOCTL1 +// +//***************************************************************************** +// Field: [15] DCO +// +// DCO control +// ENUMs: +// EN Enable DCO +// DIS Disable DCO +#define LRFDRFE_DLOCTL1_DCO 0x00008000U +#define LRFDRFE_DLOCTL1_DCO_M 0x00008000U +#define LRFDRFE_DLOCTL1_DCO_S 15U +#define LRFDRFE_DLOCTL1_DCO_EN 0x00008000U +#define LRFDRFE_DLOCTL1_DCO_DIS 0x00000000U + +// Field: [7] FCDEM +// +// Finecode dynamic element match control +// ENUMs: +// EN Enable DEM +// DIS Disable DEM +#define LRFDRFE_DLOCTL1_FCDEM 0x00000080U +#define LRFDRFE_DLOCTL1_FCDEM_M 0x00000080U +#define LRFDRFE_DLOCTL1_FCDEM_S 7U +#define LRFDRFE_DLOCTL1_FCDEM_EN 0x00000080U +#define LRFDRFE_DLOCTL1_FCDEM_DIS 0x00000000U + +// Field: [6] DTSTCKVD +// +// CKVD DTST interface control +// +// Configure DTST interface in DTST when interface is disabled. +// ENUMs: +// ONE Enable CKVD DTST interface +// ZERO Disable CKVD DTST interface +#define LRFDRFE_DLOCTL1_DTSTCKVD 0x00000040U +#define LRFDRFE_DLOCTL1_DTSTCKVD_M 0x00000040U +#define LRFDRFE_DLOCTL1_DTSTCKVD_S 6U +#define LRFDRFE_DLOCTL1_DTSTCKVD_ONE 0x00000040U +#define LRFDRFE_DLOCTL1_DTSTCKVD_ZERO 0x00000000U + +// Field: [5] PHEDISC +// +// Phase error discarding control +// +// Feature discards large phase errors from propagating into the loop filter. +// PHEDISC configures the behavior. +// ENUMs: +// EN Enable phase error discard function +// DIS Disable phase error discard function +#define LRFDRFE_DLOCTL1_PHEDISC 0x00000020U +#define LRFDRFE_DLOCTL1_PHEDISC_M 0x00000020U +#define LRFDRFE_DLOCTL1_PHEDISC_S 5U +#define LRFDRFE_DLOCTL1_PHEDISC_EN 0x00000020U +#define LRFDRFE_DLOCTL1_PHEDISC_DIS 0x00000000U + +// Field: [4] PLLMON +// +// PLL monitor control +// +// The PLL monitor detects the following PLL states in the variable clock +// domain: +// - Lock (static) +// - Loss of lock (dynamic) +// - Fine code above threshold (static) +// - Fine code below threshold (static) +// +// The monitor signals the occurence of these conditions to the reference clock +// domain. This domain does positive edge detection for lock and loss-of-lock +// events, and synchronizes the threshold events. The IRQ to modem is high +// whenever reference clock domain events are high. +// +// The lock and loss-of-lock flags are cleared individually in the reference +// clock domain. Disable the PLL monitor to reset the all event flags in the +// variable clock domain. PLL Lock and Loss of Lock flags are automatically +// cleared in the variable clock domain when transitioning from open-loop to +// closed-loop operation. +// +// To clear Lock and Loss of Lock flags using this field, the DLO must operate +// in closed-loop mode, and a new value must be stable for at least 2 REFCLK +// periods. +// +// Keep PLL monitor disabled during the calibration states. +// ENUMs: +// EN Enable PLL monitor +// DIS Disable and reset PLL monitor +#define LRFDRFE_DLOCTL1_PLLMON 0x00000010U +#define LRFDRFE_DLOCTL1_PLLMON_M 0x00000010U +#define LRFDRFE_DLOCTL1_PLLMON_S 4U +#define LRFDRFE_DLOCTL1_PLLMON_EN 0x00000010U +#define LRFDRFE_DLOCTL1_PLLMON_DIS 0x00000000U + +// Field: [3] IIR +// +// IIR control +// +// Do not enable during lock aquisition. +// ENUMs: +// EN Enable IIR filter +// DIS Disable IIR filter +#define LRFDRFE_DLOCTL1_IIR 0x00000008U +#define LRFDRFE_DLOCTL1_IIR_M 0x00000008U +#define LRFDRFE_DLOCTL1_IIR_S 3U +#define LRFDRFE_DLOCTL1_IIR_EN 0x00000008U +#define LRFDRFE_DLOCTL1_IIR_DIS 0x00000000U + +// Field: [2] MOD +// +// Modulator control +// +// Enable of MODISF (Modulator's Interpolating Shaping Filter) +// ENUMs: +// EN Enable MODISF +// DIS Disable MODISF +#define LRFDRFE_DLOCTL1_MOD 0x00000004U +#define LRFDRFE_DLOCTL1_MOD_M 0x00000004U +#define LRFDRFE_DLOCTL1_MOD_S 2U +#define LRFDRFE_DLOCTL1_MOD_EN 0x00000004U +#define LRFDRFE_DLOCTL1_MOD_DIS 0x00000000U + +// Field: [1] MODINIT +// +// Modulator Initialization +// ENUMs: +// ACTIVATE Activate MODISF initialization +// DEACTIVATE Deactivate MODISF initialization +#define LRFDRFE_DLOCTL1_MODINIT 0x00000002U +#define LRFDRFE_DLOCTL1_MODINIT_M 0x00000002U +#define LRFDRFE_DLOCTL1_MODINIT_S 1U +#define LRFDRFE_DLOCTL1_MODINIT_ACTIVATE 0x00000002U +#define LRFDRFE_DLOCTL1_MODINIT_DEACTIVATE 0x00000000U + +// Field: [0] MTDCRSTN +// +// MTDC reset +// ENUMs: +// ACTIVE Release MTDC reset +// RESET Reset MTDC +#define LRFDRFE_DLOCTL1_MTDCRSTN 0x00000001U +#define LRFDRFE_DLOCTL1_MTDCRSTN_M 0x00000001U +#define LRFDRFE_DLOCTL1_MTDCRSTN_S 0U +#define LRFDRFE_DLOCTL1_MTDCRSTN_ACTIVE 0x00000001U +#define LRFDRFE_DLOCTL1_MTDCRSTN_RESET 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DCOOVR0 +// +//***************************************************************************** +// Field: [13:8] MIDCODE +// +// Mid code override +// +// When MIDCTL equals EN, field value overrides the DCO mid code, which sets +// the DCO mid row and column control. Special encoding: +// MIDCODE[5:4]: +// 00: DCO mid row = 15 +// 01: DCO mid row = 7 +// 10: DCO mid row = 3 +// 11: DCO mid row = 1 +// +// DCO mid column = 15-to_integer(MIDCODE[3:0]) +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DCOOVR0_MIDCODE_W 6U +#define LRFDRFE_DCOOVR0_MIDCODE_M 0x00003F00U +#define LRFDRFE_DCOOVR0_MIDCODE_S 8U +#define LRFDRFE_DCOOVR0_MIDCODE_ALLONES 0x00003F00U +#define LRFDRFE_DCOOVR0_MIDCODE_ALLZEROS 0x00000000U + +// Field: [7:4] CRSCODE +// +// Coarse code override +// +// When CRSCTL equals EN, field value overrides the DCO coarse control. This is +// required during debug and when coarse calibration is skipped, or we want to +// use other values during startup of ALO. Encoding is <4.0u>: +// +// 0xFF: min frequency +// … +// 0x00: max frequency +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DCOOVR0_CRSCODE_W 4U +#define LRFDRFE_DCOOVR0_CRSCODE_M 0x000000F0U +#define LRFDRFE_DCOOVR0_CRSCODE_S 4U +#define LRFDRFE_DCOOVR0_CRSCODE_ALLONES 0x000000F0U +#define LRFDRFE_DCOOVR0_CRSCODE_ALLZEROS 0x00000000U + +// Field: [3] FINECTL +// +// Fine code override control +// ENUMs: +// EN Enable fine code override +// DIS Disable fine code override +#define LRFDRFE_DCOOVR0_FINECTL 0x00000008U +#define LRFDRFE_DCOOVR0_FINECTL_M 0x00000008U +#define LRFDRFE_DCOOVR0_FINECTL_S 3U +#define LRFDRFE_DCOOVR0_FINECTL_EN 0x00000008U +#define LRFDRFE_DCOOVR0_FINECTL_DIS 0x00000000U + +// Field: [2] SDMICTL +// +// SDM input code override control +// ENUMs: +// EN Enable SDM input code override +// DIS Disable SDM input code override +#define LRFDRFE_DCOOVR0_SDMICTL 0x00000004U +#define LRFDRFE_DCOOVR0_SDMICTL_M 0x00000004U +#define LRFDRFE_DCOOVR0_SDMICTL_S 2U +#define LRFDRFE_DCOOVR0_SDMICTL_EN 0x00000004U +#define LRFDRFE_DCOOVR0_SDMICTL_DIS 0x00000000U + +// Field: [1] MIDCTL +// +// Mid code override control +// ENUMs: +// EN Enable mid code override +// DIS Disable mid code override +#define LRFDRFE_DCOOVR0_MIDCTL 0x00000002U +#define LRFDRFE_DCOOVR0_MIDCTL_M 0x00000002U +#define LRFDRFE_DCOOVR0_MIDCTL_S 1U +#define LRFDRFE_DCOOVR0_MIDCTL_EN 0x00000002U +#define LRFDRFE_DCOOVR0_MIDCTL_DIS 0x00000000U + +// Field: [0] CRSCTL +// +// Coarse code override +// ENUMs: +// EN Enable coarse code override +// DIS Disable coarse code override +#define LRFDRFE_DCOOVR0_CRSCTL 0x00000001U +#define LRFDRFE_DCOOVR0_CRSCTL_M 0x00000001U +#define LRFDRFE_DCOOVR0_CRSCTL_S 0U +#define LRFDRFE_DCOOVR0_CRSCTL_EN 0x00000001U +#define LRFDRFE_DCOOVR0_CRSCTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DCOOVR1 +// +//***************************************************************************** +// Field: [14:8] FINECODE +// +// Fine code override +// +// When DCOOVR0.FINECTL equals EN, field value overrides the integer part of +// DCO fine code . +// +// Encoding is <7.0u>: +// 0x00: Min +// ... +// 0x7F: MAX +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DCOOVR1_FINECODE_W 7U +#define LRFDRFE_DCOOVR1_FINECODE_M 0x00007F00U +#define LRFDRFE_DCOOVR1_FINECODE_S 8U +#define LRFDRFE_DCOOVR1_FINECODE_ALLONES 0x00007F00U +#define LRFDRFE_DCOOVR1_FINECODE_ALLZEROS 0x00000000U + +// Field: [7:0] SDMICODE +// +// SDM input code override +// +// When DCOOVR0.SDMICTL equals EN, field value overrides the fractional part of +// DCO fine code to SDM. Encoding is <0.8u>: +// 0x00: 0 +// ... +// 0x7F: 0.99609375 +// +// The fractional value is added to the integer part. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DCOOVR1_SDMICODE_W 8U +#define LRFDRFE_DCOOVR1_SDMICODE_M 0x000000FFU +#define LRFDRFE_DCOOVR1_SDMICODE_S 0U +#define LRFDRFE_DCOOVR1_SDMICODE_ALLONES 0x000000FFU +#define LRFDRFE_DCOOVR1_SDMICODE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTST +// +//***************************************************************************** +// Field: [14:11] SPARE11 +// +// SPARE111 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTST_SPARE11_W 4U +#define LRFDRFE_DTST_SPARE11_M 0x00007800U +#define LRFDRFE_DTST_SPARE11_S 11U +#define LRFDRFE_DTST_SPARE11_ALLONES 0x00007800U +#define LRFDRFE_DTST_SPARE11_ALLZEROS 0x00000000U + +// Field: [10:8] VARTGLDLY +// +// Variable domain toggle delay +// +// Field sets delay on toggle launch compared to data launch. CLK equals launch +// clock for signal selected in SIG. It can be eiter CKVD16 or reference clock. +// ENUMs: +// CLK_7_PER Toggle lags data by 7 CKVD16 periods. +// CLK_6_PER Toggle lags data by 6 CKVD16 periods. +// CLK_5_PER Toggle lags data by 5 CKVD16 periods. +// CLK_4_PER Toggle lags data by 4 CKVD16 periods. +// CLK_3_PER Toggle lags data by 3 CKVD16 periods. +// CLK_2_PER Toggle lags data by 2 CKVD16 periods. +// CLK_1_PER Toggle lags data by 1 CKVD16 periods. +// CLK_0_PER Toggle lags data by 0 CKVD16 periods. +#define LRFDRFE_DTST_VARTGLDLY_W 3U +#define LRFDRFE_DTST_VARTGLDLY_M 0x00000700U +#define LRFDRFE_DTST_VARTGLDLY_S 8U +#define LRFDRFE_DTST_VARTGLDLY_CLK_7_PER 0x00000700U +#define LRFDRFE_DTST_VARTGLDLY_CLK_6_PER 0x00000600U +#define LRFDRFE_DTST_VARTGLDLY_CLK_5_PER 0x00000500U +#define LRFDRFE_DTST_VARTGLDLY_CLK_4_PER 0x00000400U +#define LRFDRFE_DTST_VARTGLDLY_CLK_3_PER 0x00000300U +#define LRFDRFE_DTST_VARTGLDLY_CLK_2_PER 0x00000200U +#define LRFDRFE_DTST_VARTGLDLY_CLK_1_PER 0x00000100U +#define LRFDRFE_DTST_VARTGLDLY_CLK_0_PER 0x00000000U + +// Field: [7] REFTGLDLY +// +// Reference domain toggle delay +// +// Field sets delay on toggle launch compared to data launch. CLK equals launch +// clock for signal selected in SIG. It can be eiter CKVD16 or reference clock. +// ENUMs: +// CLK_1_PER Toggle lags data by 1 HFXT/BAW periods. +// CLK_0_PER Toggle lags data by 0 HFXT/BAW periods. +#define LRFDRFE_DTST_REFTGLDLY 0x00000080U +#define LRFDRFE_DTST_REFTGLDLY_M 0x00000080U +#define LRFDRFE_DTST_REFTGLDLY_S 7U +#define LRFDRFE_DTST_REFTGLDLY_CLK_1_PER 0x00000080U +#define LRFDRFE_DTST_REFTGLDLY_CLK_0_PER 0x00000000U + +// Field: [6] TRNSEQ +// +// Trainer sequence control +// +// When trainer sequence is enabled, dtst data will not reflect SIG +// configuration. Instead, it will toggle between 0x5555 and 0xAAAA for every +// update uof the data specified by SIG. +// ENUMs: +// EN Enable trainer sequence +// DIS Disable trainer sequence +#define LRFDRFE_DTST_TRNSEQ 0x00000040U +#define LRFDRFE_DTST_TRNSEQ_M 0x00000040U +#define LRFDRFE_DTST_TRNSEQ_S 6U +#define LRFDRFE_DTST_TRNSEQ_EN 0x00000040U +#define LRFDRFE_DTST_TRNSEQ_DIS 0x00000000U + +// Field: [5] SPARE5 +// +// SPARE5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DTST_SPARE5 0x00000020U +#define LRFDRFE_DTST_SPARE5_M 0x00000020U +#define LRFDRFE_DTST_SPARE5_S 5U +#define LRFDRFE_DTST_SPARE5_ONE 0x00000020U +#define LRFDRFE_DTST_SPARE5_ZERO 0x00000000U + +// Field: [4:0] SIG +// +// Signal Configuration +// +// Selects which signal to route to DTST data port. Any change to MSB may +// cause modem to detect false toggle. Hence, the first sample must be +// discarded in modem after a change to MSB. +// +// Whenever signal po_tdc_stop_dly_sel is sampled, discard the first three +// samples. +// +// All bits in dtst_data vector originates from the same reference clock edge, +// unless otherwise noted. +// ENUMs: +// VAR_NC_15 dtst_data = 0x0000 +// VAR_NC_14 dtst_data = 0x0000 +// VAR_NC_13 dtst_data = 0x0000 +// VAR_NC_12 dtst_data = 0x0000 +// VAR_NC_11 dtst_data = 0x0000 +// VAR_LOOP_UPD_FINECODE dtst_data : +// +// [15] : +// (u_pll/pll_loop_update) +// [14:0] : +// u_pll/po_ckvd16_finecode_pll +// VAR_LOCK_FINECODE dtst_data : +// +// [15] : +// (u_pll/po_ckvd48_pllmon_lock XOR +// u_pll/po_ckvd48_pllmon_lol) +// [14:0] : +// u_pll/po_ckvd16_finecode_pll +// VAR_MPX_CAN dtst_data : +// +// [15] : u_mpx/freq_can[16] +// [14:0] : +// u_mpx/freq_can[14:0] +// +// Format is 1.15s. This +// field holds how much phase DTX adds to DCO per +// reference frequency. This is a slice of the +// signals that goes to u_pll which is 3.18s. +// Hence, wrapping can occur. +// VAR_TDCSTOP_STATUS_TDC dtst_data : +// +// [15:14] : +// po_tdc_stop_dly_sel +// [13] : +// u_pll/pi_tdc_msb_error +// [12] : +// u_pll/pll_loop_update +// [11] : +// (u_pll/po_ckvd48_pllmon_lock XOR +// u_pll/po_ckvd48_pllmon_lol) +// [10:0]: +// u_pll/pi_tdc_data +// +// Note that [12:11] are +// samples from previous reference clock edge. +// VAR_TDCSTOP_PHERR dtst_data : +// +// [15:14] : +// po_tdc_stop_dly_sel +// [13] +// u_pll/phase_error[16] +// [12:0]: +// u_pll/phase_error[12:0] +// +// [13:0] : phase_error. +// Format is 3.11s. +// VAR_PH_COMP_PHERR_TDCSTOPdtst_data : +// +// [15:14] : +// po_tdc_stop_dly_sel +// [13] : +// u_pll/phase_error[16] +// [12:9]: +// u_pll/phase_error[11:8] +// [8:0] : +// u_pll/var_phase[14: 6] +// +// [13:9] : phase error. +// Format is 2.3s. +// [8:0] : variable phase. +// Format is 4.5u. +// VAR_PH_TDCCORR dtst_data : +// +// [15] ; +// u_pll/pi_tdc_msb_error +// [14:11] : +// u_pll/pi_pi_cnt_lsb +// [10:0] : +// u_pll/tdc_data_corr +// VAR_PH_RAW dtst_data : +// +// [15] ; +// u_pll/pi_tdc_msb_error +// [14:11] : +// u_pll/pi_pi_cnt_lsb +// [10:0] : +// u_pll/pi_tdc_data +// VAR_PHERR_LOWER dtst_data : +// +// [15] : +// u_pll/phase_error[16] +// [14:0] : +// u_pll/phase_error[14:0] +// +// Format is 5.11s. Phase +// error wraps if if too large. +// VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1] +// +// Format is 6.10s. +// VAR_NC_0 dtst_data = 0x0000 +// REF_NC_15 dtst_data = 0x0000 +// REF_NC_14 dtst_data = 0x0000 +// REF_NC_13 dtst_data = 0x0000 +// REF_NC_12 dtst_data = 0x0000 +// REF_NC_11 dtst_data = 0x0000 +// REF_NC_10 dtst_data = 0x0000 +// REF_NC_9 dtst_data = 0x0000 +// REF_NC_8 dtst_data = 0x0000 +// REF_NC_7 dtst_data = 0x0000 +// REF_NC_6 dtst_data = 0x0000 +// REF_NC_5 dtst_data = 0x0000 +// REF_NC_4 dtst_data = 0x0000 +// REF_NC_3 dtst_data = 0x0000 +// REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag +// +// Format is14.2u. The +// signal is only updated for frequency +// measurements that affect the calibration +// result. +// REF_FSMCAL dtst_data : +// +// [15] : '0' +// [14] : +// u_fsm/pi_pll_lock_ind +// [13:10] : +// u_fsm/po_dsts_fsm_state +// [9:6] : +// u_fsm/po_dtst_fsm_coarse +// [5:0] : +// u_fsm/po_dtst_fsm_mid +// REF_NC_0 dtst_data = 0x0000 +#define LRFDRFE_DTST_SIG_W 5U +#define LRFDRFE_DTST_SIG_M 0x0000001FU +#define LRFDRFE_DTST_SIG_S 0U +#define LRFDRFE_DTST_SIG_VAR_NC_15 0x0000001FU +#define LRFDRFE_DTST_SIG_VAR_NC_14 0x0000001EU +#define LRFDRFE_DTST_SIG_VAR_NC_13 0x0000001DU +#define LRFDRFE_DTST_SIG_VAR_NC_12 0x0000001CU +#define LRFDRFE_DTST_SIG_VAR_NC_11 0x0000001BU +#define LRFDRFE_DTST_SIG_VAR_LOOP_UPD_FINECODE 0x0000001AU +#define LRFDRFE_DTST_SIG_VAR_LOCK_FINECODE 0x00000019U +#define LRFDRFE_DTST_SIG_VAR_MPX_CAN 0x00000018U +#define LRFDRFE_DTST_SIG_VAR_TDCSTOP_STATUS_TDC 0x00000017U +#define LRFDRFE_DTST_SIG_VAR_TDCSTOP_PHERR 0x00000016U +#define LRFDRFE_DTST_SIG_VAR_PH_COMP_PHERR_TDCSTOP 0x00000015U +#define LRFDRFE_DTST_SIG_VAR_PH_TDCCORR 0x00000014U +#define LRFDRFE_DTST_SIG_VAR_PH_RAW 0x00000013U +#define LRFDRFE_DTST_SIG_VAR_PHERR_LOWER 0x00000012U +#define LRFDRFE_DTST_SIG_VAR_PHERR_UPPER 0x00000011U +#define LRFDRFE_DTST_SIG_VAR_NC_0 0x00000010U +#define LRFDRFE_DTST_SIG_REF_NC_15 0x0000000FU +#define LRFDRFE_DTST_SIG_REF_NC_14 0x0000000EU +#define LRFDRFE_DTST_SIG_REF_NC_13 0x0000000DU +#define LRFDRFE_DTST_SIG_REF_NC_12 0x0000000CU +#define LRFDRFE_DTST_SIG_REF_NC_11 0x0000000BU +#define LRFDRFE_DTST_SIG_REF_NC_10 0x0000000AU +#define LRFDRFE_DTST_SIG_REF_NC_9 0x00000009U +#define LRFDRFE_DTST_SIG_REF_NC_8 0x00000008U +#define LRFDRFE_DTST_SIG_REF_NC_7 0x00000007U +#define LRFDRFE_DTST_SIG_REF_NC_6 0x00000006U +#define LRFDRFE_DTST_SIG_REF_NC_5 0x00000005U +#define LRFDRFE_DTST_SIG_REF_NC_4 0x00000004U +#define LRFDRFE_DTST_SIG_REF_NC_3 0x00000003U +#define LRFDRFE_DTST_SIG_REF_FERR_MAG 0x00000002U +#define LRFDRFE_DTST_SIG_REF_FSMCAL 0x00000001U +#define LRFDRFE_DTST_SIG_REF_NC_0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DLOEV +// +//***************************************************************************** +// Field: [7] LOCK +// +// Lock +// +// PLLMON1.PHELOCKCNT and PLLMON1.PHELOCKTHR configures the behaviour. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DLOEV_LOCK 0x00000080U +#define LRFDRFE_DLOEV_LOCK_M 0x00000080U +#define LRFDRFE_DLOEV_LOCK_S 7U +#define LRFDRFE_DLOEV_LOCK_ONE 0x00000080U +#define LRFDRFE_DLOEV_LOCK_ZERO 0x00000000U + +// Field: [6] LOL +// +// Loss of lock +// +// PLLMON0.PHELOLCNT and PLLMON0.PHELOLTHR configures the behaviour. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DLOEV_LOL 0x00000040U +#define LRFDRFE_DLOEV_LOL_M 0x00000040U +#define LRFDRFE_DLOEV_LOL_S 6U +#define LRFDRFE_DLOEV_LOL_ONE 0x00000040U +#define LRFDRFE_DLOEV_LOL_ZERO 0x00000000U + +// Field: [5] FCABVTHR +// +// Finecode above threshold +// +// PLLMON0.FCTHR sets threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DLOEV_FCABVTHR 0x00000020U +#define LRFDRFE_DLOEV_FCABVTHR_M 0x00000020U +#define LRFDRFE_DLOEV_FCABVTHR_S 5U +#define LRFDRFE_DLOEV_FCABVTHR_ONE 0x00000020U +#define LRFDRFE_DLOEV_FCABVTHR_ZERO 0x00000000U + +// Field: [4] FCBLWTHR +// +// Finecode below threshold +// +// PLLMON0.FCTHR sets threshold. +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DLOEV_FCBLWTHR 0x00000010U +#define LRFDRFE_DLOEV_FCBLWTHR_M 0x00000010U +#define LRFDRFE_DLOEV_FCBLWTHR_S 4U +#define LRFDRFE_DLOEV_FCBLWTHR_ONE 0x00000010U +#define LRFDRFE_DLOEV_FCBLWTHR_ZERO 0x00000000U + +// Field: [3:0] STATE +// +// DLO FSM state +// +// INTERNAL NOTE: +// See implementation specification for details. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DLOEV_STATE_W 4U +#define LRFDRFE_DLOEV_STATE_M 0x0000000FU +#define LRFDRFE_DLOEV_STATE_S 0U +#define LRFDRFE_DLOEV_STATE_ALLONES 0x0000000FU +#define LRFDRFE_DLOEV_STATE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DTSTRD +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Data selected by DTST.SIG when the DTST interface is enabled. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DTSTRD_DATA_W 16U +#define LRFDRFE_DTSTRD_DATA_M 0x0000FFFFU +#define LRFDRFE_DTSTRD_DATA_S 0U +#define LRFDRFE_DTSTRD_DATA_ALLONES 0x0000FFFFU +#define LRFDRFE_DTSTRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_FDCOSPANLSB +// +//***************************************************************************** +// Field: [15:0] VAL +// +// DCO frequency span +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_FDCOSPANLSB_VAL_W 16U +#define LRFDRFE_FDCOSPANLSB_VAL_M 0x0000FFFFU +#define LRFDRFE_FDCOSPANLSB_VAL_S 0U +#define LRFDRFE_FDCOSPANLSB_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_FDCOSPANLSB_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_FDCOSPANMSB +// +//***************************************************************************** +// Field: [2:0] VAL +// +// DCO frequency span +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_FDCOSPANMSB_VAL_W 3U +#define LRFDRFE_FDCOSPANMSB_VAL_M 0x00000007U +#define LRFDRFE_FDCOSPANMSB_VAL_S 0U +#define LRFDRFE_FDCOSPANMSB_VAL_ALLONES 0x00000007U +#define LRFDRFE_FDCOSPANMSB_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TDCCAL +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Value +// +// Sum of inverter delays calculated by HW at the end of the TDC calibration. +// The number of delays summed is controlled by CAL0.TDCAVG and +// DLOCTL0.TDCSTOP. FW uses value to calculate CAL2.KTDCINV. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TDCCAL_VAL_W 16U +#define LRFDRFE_TDCCAL_VAL_M 0x0000FFFFU +#define LRFDRFE_TDCCAL_VAL_S 0U +#define LRFDRFE_TDCCAL_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TDCCAL_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_CALRES +// +//***************************************************************************** +// Field: [9:4] MIDCODE +// +// Calibrated mid code +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CALRES_MIDCODE_W 6U +#define LRFDRFE_CALRES_MIDCODE_M 0x000003F0U +#define LRFDRFE_CALRES_MIDCODE_S 4U +#define LRFDRFE_CALRES_MIDCODE_ALLONES 0x000003F0U +#define LRFDRFE_CALRES_MIDCODE_ALLZEROS 0x00000000U + +// Field: [3:0] CRSCODE +// +// Calibrated coarse code +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_CALRES_CRSCODE_W 4U +#define LRFDRFE_CALRES_CRSCODE_M 0x0000000FU +#define LRFDRFE_CALRES_CRSCODE_S 0U +#define LRFDRFE_CALRES_CRSCODE_ALLONES 0x0000000FU +#define LRFDRFE_CALRES_CRSCODE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_GPI +// +//***************************************************************************** +// Field: [7] GPI7 +// +// Control GPI7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI7 0x00000080U +#define LRFDRFE_GPI_GPI7_M 0x00000080U +#define LRFDRFE_GPI_GPI7_S 7U +#define LRFDRFE_GPI_GPI7_ONE 0x00000080U +#define LRFDRFE_GPI_GPI7_ZERO 0x00000000U + +// Field: [6] GPI6 +// +// Control GPI6 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI6 0x00000040U +#define LRFDRFE_GPI_GPI6_M 0x00000040U +#define LRFDRFE_GPI_GPI6_S 6U +#define LRFDRFE_GPI_GPI6_ONE 0x00000040U +#define LRFDRFE_GPI_GPI6_ZERO 0x00000000U + +// Field: [5] GPI5 +// +// Control GPI5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI5 0x00000020U +#define LRFDRFE_GPI_GPI5_M 0x00000020U +#define LRFDRFE_GPI_GPI5_S 5U +#define LRFDRFE_GPI_GPI5_ONE 0x00000020U +#define LRFDRFE_GPI_GPI5_ZERO 0x00000000U + +// Field: [4] GPI4 +// +// Control GPI4 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI4 0x00000010U +#define LRFDRFE_GPI_GPI4_M 0x00000010U +#define LRFDRFE_GPI_GPI4_S 4U +#define LRFDRFE_GPI_GPI4_ONE 0x00000010U +#define LRFDRFE_GPI_GPI4_ZERO 0x00000000U + +// Field: [3] GPI3 +// +// Control GPI3 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI3 0x00000008U +#define LRFDRFE_GPI_GPI3_M 0x00000008U +#define LRFDRFE_GPI_GPI3_S 3U +#define LRFDRFE_GPI_GPI3_ONE 0x00000008U +#define LRFDRFE_GPI_GPI3_ZERO 0x00000000U + +// Field: [2] GPI2 +// +// Control GPI2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI2 0x00000004U +#define LRFDRFE_GPI_GPI2_M 0x00000004U +#define LRFDRFE_GPI_GPI2_S 2U +#define LRFDRFE_GPI_GPI2_ONE 0x00000004U +#define LRFDRFE_GPI_GPI2_ZERO 0x00000000U + +// Field: [1] GPI1 +// +// Control GPI1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI1 0x00000002U +#define LRFDRFE_GPI_GPI1_M 0x00000002U +#define LRFDRFE_GPI_GPI1_S 1U +#define LRFDRFE_GPI_GPI1_ONE 0x00000002U +#define LRFDRFE_GPI_GPI1_ZERO 0x00000000U + +// Field: [0] GPI0 +// +// Control GPI0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPI_GPI0 0x00000001U +#define LRFDRFE_GPI_GPI0_M 0x00000001U +#define LRFDRFE_GPI_GPI0_S 0U +#define LRFDRFE_GPI_GPI0_ONE 0x00000001U +#define LRFDRFE_GPI_GPI0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MATHACCELIN +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Input value in linear units +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MATHACCELIN_VAL_W 16U +#define LRFDRFE_MATHACCELIN_VAL_M 0x0000FFFFU +#define LRFDRFE_MATHACCELIN_VAL_S 0U +#define LRFDRFE_MATHACCELIN_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_MATHACCELIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_LIN2LOGOUT +// +//***************************************************************************** +// Field: [6:0] LOGVAL +// +// Logarithmic output value +// +// Logaritmic value of MATHACCELIN.VAL. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_LIN2LOGOUT_LOGVAL_W 7U +#define LRFDRFE_LIN2LOGOUT_LOGVAL_M 0x0000007FU +#define LRFDRFE_LIN2LOGOUT_LOGVAL_S 0U +#define LRFDRFE_LIN2LOGOUT_LOGVAL_ALLONES 0x0000007FU +#define LRFDRFE_LIN2LOGOUT_LOGVAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVBY3OUT +// +//***************************************************************************** +// Field: [3:0] DIV3 +// +// Divider output value +// +// Calculation performed: MATHACCELIN.VAL/3 +// +// Supports input values <= 46, higher values are saturated. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIVBY3OUT_DIV3_W 4U +#define LRFDRFE_DIVBY3OUT_DIV3_M 0x0000000FU +#define LRFDRFE_DIVBY3OUT_DIV3_S 0U +#define LRFDRFE_DIVBY3OUT_DIV3_ALLONES 0x0000000FU +#define LRFDRFE_DIVBY3OUT_DIV3_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TIMCTL +// +//***************************************************************************** +// Field: [13:8] CPTSRC +// +// Event capture source +// +// Index selects the corresponding event from RFE event bus, EVT0 and EVT1. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TIMCTL_CPTSRC_W 6U +#define LRFDRFE_TIMCTL_CPTSRC_M 0x00003F00U +#define LRFDRFE_TIMCTL_CPTSRC_S 8U +#define LRFDRFE_TIMCTL_CPTSRC_ALLONES 0x00003F00U +#define LRFDRFE_TIMCTL_CPTSRC_ALLZEROS 0x00000000U + +// Field: [7] CPTCTL +// +// Counter capture control +// +// Upon selected capture event, the counter value will be captured into +// TIMCAPT. +// ENUMs: +// EN Enable counter capture mode +// DIS Disable counter capture mode +#define LRFDRFE_TIMCTL_CPTCTL 0x00000080U +#define LRFDRFE_TIMCTL_CPTCTL_M 0x00000080U +#define LRFDRFE_TIMCTL_CPTCTL_S 7U +#define LRFDRFE_TIMCTL_CPTCTL_EN 0x00000080U +#define LRFDRFE_TIMCTL_CPTCTL_DIS 0x00000000U + +// Field: [6:5] CNTRSRC +// +// Counter event source +// ENUMs: +// FREF Count FREF ticks +// MAGN1 Use magnitude estimator 1 data enable +// MAGN0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDRFE_TIMCTL_CNTRSRC_W 2U +#define LRFDRFE_TIMCTL_CNTRSRC_M 0x00000060U +#define LRFDRFE_TIMCTL_CNTRSRC_S 5U +#define LRFDRFE_TIMCTL_CNTRSRC_FREF 0x00000060U +#define LRFDRFE_TIMCTL_CNTRSRC_MAGN1 0x00000040U +#define LRFDRFE_TIMCTL_CNTRSRC_MAGN0 0x00000020U +#define LRFDRFE_TIMCTL_CNTRSRC_CLK 0x00000000U + +// Field: [4] CNTRCLR +// +// Counter clear value in TIMCNT. +// ENUMs: +// ONE Clear counter value +// ZERO No action +#define LRFDRFE_TIMCTL_CNTRCLR 0x00000010U +#define LRFDRFE_TIMCTL_CNTRCLR_M 0x00000010U +#define LRFDRFE_TIMCTL_CNTRCLR_S 4U +#define LRFDRFE_TIMCTL_CNTRCLR_ONE 0x00000010U +#define LRFDRFE_TIMCTL_CNTRCLR_ZERO 0x00000000U + +// Field: [3] CNTRCTL +// +// 16-bit counter control +// +// The counter will continue from its current value. +// ENUMs: +// EN Enable counter +// DIS Disable counter +#define LRFDRFE_TIMCTL_CNTRCTL 0x00000008U +#define LRFDRFE_TIMCTL_CNTRCTL_M 0x00000008U +#define LRFDRFE_TIMCTL_CNTRCTL_S 3U +#define LRFDRFE_TIMCTL_CNTRCTL_EN 0x00000008U +#define LRFDRFE_TIMCTL_CNTRCTL_DIS 0x00000000U + +// Field: [2:1] TIMSRC +// +// Timer tick source +// ENUMs: +// FREF Count FREF ticks +// MAGN1 Use magnitude estimator 1 data enable +// MAGN0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDRFE_TIMCTL_TIMSRC_W 2U +#define LRFDRFE_TIMCTL_TIMSRC_M 0x00000006U +#define LRFDRFE_TIMCTL_TIMSRC_S 1U +#define LRFDRFE_TIMCTL_TIMSRC_FREF 0x00000006U +#define LRFDRFE_TIMCTL_TIMSRC_MAGN1 0x00000004U +#define LRFDRFE_TIMCTL_TIMSRC_MAGN0 0x00000002U +#define LRFDRFE_TIMCTL_TIMSRC_CLK 0x00000000U + +// Field: [0] TIMCTL +// +// 16-bit timer control +// +// It will generate a timer interrupt after TIMPER timer ticks. Note that the +// internal timer value is not readable from the RFE. If this is needed the +// counter should be used instead of the timer. +// ENUMs: +// EN Enable timer +// DIS Disable timer and clear internal timer value +#define LRFDRFE_TIMCTL_TIMCTL 0x00000001U +#define LRFDRFE_TIMCTL_TIMCTL_M 0x00000001U +#define LRFDRFE_TIMCTL_TIMCTL_S 0U +#define LRFDRFE_TIMCTL_TIMCTL_EN 0x00000001U +#define LRFDRFE_TIMCTL_TIMCTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TIMINC +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Programmable increment for the counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TIMINC_VAL_W 16U +#define LRFDRFE_TIMINC_VAL_M 0x0000FFFFU +#define LRFDRFE_TIMINC_VAL_S 0U +#define LRFDRFE_TIMINC_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TIMINC_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TIMPER +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Configurable 16 bit period that can be used for either the timer or the +// counter. In timer context, when timer value reach the timer period (i.e. it +// expires) a TIMER_IRQ event will occur, and the timer will restart from zero +// (until the timer is manually disabled). In counter context, a COUNTER_IRQ +// event will occur when the counter is equal to or higher than the period +// value. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TIMPER_VAL_W 16U +#define LRFDRFE_TIMPER_VAL_M 0x0000FFFFU +#define LRFDRFE_TIMPER_VAL_S 0U +#define LRFDRFE_TIMPER_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TIMPER_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TIMCNT +// +//***************************************************************************** +// Field: [15:0] VAL +// +// 16 bit value of counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TIMCNT_VAL_W 16U +#define LRFDRFE_TIMCNT_VAL_M 0x0000FFFFU +#define LRFDRFE_TIMCNT_VAL_S 0U +#define LRFDRFE_TIMCNT_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TIMCNT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TIMCAPT +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Captured value of counter +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TIMCAPT_VALUE_W 16U +#define LRFDRFE_TIMCAPT_VALUE_M 0x0000FFFFU +#define LRFDRFE_TIMCAPT_VALUE_S 0U +#define LRFDRFE_TIMCAPT_VALUE_ALLONES 0x0000FFFFU +#define LRFDRFE_TIMCAPT_VALUE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TRCCTRL +// +//***************************************************************************** +// Field: [0] SEND +// +// Sends a command to the tracer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_TRCCTRL_SEND 0x00000001U +#define LRFDRFE_TRCCTRL_SEND_M 0x00000001U +#define LRFDRFE_TRCCTRL_SEND_S 0U +#define LRFDRFE_TRCCTRL_SEND_ONE 0x00000001U +#define LRFDRFE_TRCCTRL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TRCSTAT +// +//***************************************************************************** +// Field: [0] BUSY +// +// Tracer busy status +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_TRCSTAT_BUSY 0x00000001U +#define LRFDRFE_TRCSTAT_BUSY_M 0x00000001U +#define LRFDRFE_TRCSTAT_BUSY_S 0U +#define LRFDRFE_TRCSTAT_BUSY_ONE 0x00000001U +#define LRFDRFE_TRCSTAT_BUSY_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TRCCMD +// +//***************************************************************************** +// Field: [9:8] PARCNT +// +// Number of parameters +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TRCCMD_PARCNT_W 2U +#define LRFDRFE_TRCCMD_PARCNT_M 0x00000300U +#define LRFDRFE_TRCCMD_PARCNT_S 8U +#define LRFDRFE_TRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDRFE_TRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// Packet header +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TRCCMD_PKTHDR_W 8U +#define LRFDRFE_TRCCMD_PKTHDR_M 0x000000FFU +#define LRFDRFE_TRCCMD_PKTHDR_S 0U +#define LRFDRFE_TRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDRFE_TRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TRCPAR0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 0 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TRCPAR0_VAL_W 16U +#define LRFDRFE_TRCPAR0_VAL_M 0x0000FFFFU +#define LRFDRFE_TRCPAR0_VAL_S 0U +#define LRFDRFE_TRCPAR0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TRCPAR0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_TRCPAR1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Parameter 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_TRCPAR1_VAL_W 16U +#define LRFDRFE_TRCPAR1_VAL_M 0x0000FFFFU +#define LRFDRFE_TRCPAR1_VAL_S 0U +#define LRFDRFE_TRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_TRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_GPOCTL +// +//***************************************************************************** +// Field: [15] SEL7 +// +// Select GPO7 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO7 +#define LRFDRFE_GPOCTL_SEL7 0x00008000U +#define LRFDRFE_GPOCTL_SEL7_M 0x00008000U +#define LRFDRFE_GPOCTL_SEL7_S 15U +#define LRFDRFE_GPOCTL_SEL7_HW 0x00008000U +#define LRFDRFE_GPOCTL_SEL7_SW 0x00000000U + +// Field: [14] SEL6 +// +// Select GPO6 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO6 +#define LRFDRFE_GPOCTL_SEL6 0x00004000U +#define LRFDRFE_GPOCTL_SEL6_M 0x00004000U +#define LRFDRFE_GPOCTL_SEL6_S 14U +#define LRFDRFE_GPOCTL_SEL6_HW 0x00004000U +#define LRFDRFE_GPOCTL_SEL6_SW 0x00000000U + +// Field: [13] SEL5 +// +// Select GPO5 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO5 +#define LRFDRFE_GPOCTL_SEL5 0x00002000U +#define LRFDRFE_GPOCTL_SEL5_M 0x00002000U +#define LRFDRFE_GPOCTL_SEL5_S 13U +#define LRFDRFE_GPOCTL_SEL5_HW 0x00002000U +#define LRFDRFE_GPOCTL_SEL5_SW 0x00000000U + +// Field: [12] SEL4 +// +// Select GPO4 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO4 +#define LRFDRFE_GPOCTL_SEL4 0x00001000U +#define LRFDRFE_GPOCTL_SEL4_M 0x00001000U +#define LRFDRFE_GPOCTL_SEL4_S 12U +#define LRFDRFE_GPOCTL_SEL4_HW 0x00001000U +#define LRFDRFE_GPOCTL_SEL4_SW 0x00000000U + +// Field: [11] SEL3 +// +// Select GPO3 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO3 +#define LRFDRFE_GPOCTL_SEL3 0x00000800U +#define LRFDRFE_GPOCTL_SEL3_M 0x00000800U +#define LRFDRFE_GPOCTL_SEL3_S 11U +#define LRFDRFE_GPOCTL_SEL3_HW 0x00000800U +#define LRFDRFE_GPOCTL_SEL3_SW 0x00000000U + +// Field: [10] SEL2 +// +// Select GPO2 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO2 +#define LRFDRFE_GPOCTL_SEL2 0x00000400U +#define LRFDRFE_GPOCTL_SEL2_M 0x00000400U +#define LRFDRFE_GPOCTL_SEL2_S 10U +#define LRFDRFE_GPOCTL_SEL2_HW 0x00000400U +#define LRFDRFE_GPOCTL_SEL2_SW 0x00000000U + +// Field: [9] SEL1 +// +// Select GPO1 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO1 +#define LRFDRFE_GPOCTL_SEL1 0x00000200U +#define LRFDRFE_GPOCTL_SEL1_M 0x00000200U +#define LRFDRFE_GPOCTL_SEL1_S 9U +#define LRFDRFE_GPOCTL_SEL1_HW 0x00000200U +#define LRFDRFE_GPOCTL_SEL1_SW 0x00000000U + +// Field: [8] SEL0 +// +// Select GPO0 source +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO0 +#define LRFDRFE_GPOCTL_SEL0 0x00000100U +#define LRFDRFE_GPOCTL_SEL0_M 0x00000100U +#define LRFDRFE_GPOCTL_SEL0_S 8U +#define LRFDRFE_GPOCTL_SEL0_HW 0x00000100U +#define LRFDRFE_GPOCTL_SEL0_SW 0x00000000U + +// Field: [7] GPO7 +// +// Control GPO7 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO7 0x00000080U +#define LRFDRFE_GPOCTL_GPO7_M 0x00000080U +#define LRFDRFE_GPOCTL_GPO7_S 7U +#define LRFDRFE_GPOCTL_GPO7_ONE 0x00000080U +#define LRFDRFE_GPOCTL_GPO7_ZERO 0x00000000U + +// Field: [6] GPO6 +// +// Control GPO6 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO6 0x00000040U +#define LRFDRFE_GPOCTL_GPO6_M 0x00000040U +#define LRFDRFE_GPOCTL_GPO6_S 6U +#define LRFDRFE_GPOCTL_GPO6_ONE 0x00000040U +#define LRFDRFE_GPOCTL_GPO6_ZERO 0x00000000U + +// Field: [5] GPO5 +// +// Control GPO5 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO5 0x00000020U +#define LRFDRFE_GPOCTL_GPO5_M 0x00000020U +#define LRFDRFE_GPOCTL_GPO5_S 5U +#define LRFDRFE_GPOCTL_GPO5_ONE 0x00000020U +#define LRFDRFE_GPOCTL_GPO5_ZERO 0x00000000U + +// Field: [4] GPO4 +// +// Control GPO4 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO4 0x00000010U +#define LRFDRFE_GPOCTL_GPO4_M 0x00000010U +#define LRFDRFE_GPOCTL_GPO4_S 4U +#define LRFDRFE_GPOCTL_GPO4_ONE 0x00000010U +#define LRFDRFE_GPOCTL_GPO4_ZERO 0x00000000U + +// Field: [3] GPO3 +// +// Control GPO3 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO3 0x00000008U +#define LRFDRFE_GPOCTL_GPO3_M 0x00000008U +#define LRFDRFE_GPOCTL_GPO3_S 3U +#define LRFDRFE_GPOCTL_GPO3_ONE 0x00000008U +#define LRFDRFE_GPOCTL_GPO3_ZERO 0x00000000U + +// Field: [2] GPO2 +// +// Control GPO2 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO2 0x00000004U +#define LRFDRFE_GPOCTL_GPO2_M 0x00000004U +#define LRFDRFE_GPOCTL_GPO2_S 2U +#define LRFDRFE_GPOCTL_GPO2_ONE 0x00000004U +#define LRFDRFE_GPOCTL_GPO2_ZERO 0x00000000U + +// Field: [1] GPO1 +// +// Control GPO1 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO1 0x00000002U +#define LRFDRFE_GPOCTL_GPO1_M 0x00000002U +#define LRFDRFE_GPOCTL_GPO1_S 1U +#define LRFDRFE_GPOCTL_GPO1_ONE 0x00000002U +#define LRFDRFE_GPOCTL_GPO1_ZERO 0x00000000U + +// Field: [0] GPO0 +// +// Control GPO0 +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_GPOCTL_GPO0 0x00000001U +#define LRFDRFE_GPOCTL_GPO0_M 0x00000001U +#define LRFDRFE_GPOCTL_GPO0_S 0U +#define LRFDRFE_GPOCTL_GPO0_ONE 0x00000001U +#define LRFDRFE_GPOCTL_GPO0_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_ANAISOCTL +// +//***************************************************************************** +// Field: [4] ADCDIGRSTN +// +// Active low reset of ADC clock domain within Modem +// ENUMs: +// ACTIVE Don't reset +// RESET Reset +#define LRFDRFE_ANAISOCTL_ADCDIGRSTN 0x00000010U +#define LRFDRFE_ANAISOCTL_ADCDIGRSTN_M 0x00000010U +#define LRFDRFE_ANAISOCTL_ADCDIGRSTN_S 4U +#define LRFDRFE_ANAISOCTL_ADCDIGRSTN_ACTIVE 0x00000010U +#define LRFDRFE_ANAISOCTL_ADCDIGRSTN_RESET 0x00000000U + +// Field: [3] IFADC2SVTISO +// +// Isolation between IFADC and Modem +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE_ANAISOCTL_IFADC2SVTISO 0x00000008U +#define LRFDRFE_ANAISOCTL_IFADC2SVTISO_M 0x00000008U +#define LRFDRFE_ANAISOCTL_IFADC2SVTISO_S 3U +#define LRFDRFE_ANAISOCTL_IFADC2SVTISO_ISOLATE 0x00000008U +#define LRFDRFE_ANAISOCTL_IFADC2SVTISO_CONNECT 0x00000000U + +// Field: [2] DIV2IFADCISO +// +// Isolation between DIVBUF and IFADC +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE_ANAISOCTL_DIV2IFADCISO 0x00000004U +#define LRFDRFE_ANAISOCTL_DIV2IFADCISO_M 0x00000004U +#define LRFDRFE_ANAISOCTL_DIV2IFADCISO_S 2U +#define LRFDRFE_ANAISOCTL_DIV2IFADCISO_ISOLATE 0x00000004U +#define LRFDRFE_ANAISOCTL_DIV2IFADCISO_CONNECT 0x00000000U + +// Field: [1] MTDC2SVTISO +// +// Isolation between MTDC and Modem +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE_ANAISOCTL_MTDC2SVTISO 0x00000002U +#define LRFDRFE_ANAISOCTL_MTDC2SVTISO_M 0x00000002U +#define LRFDRFE_ANAISOCTL_MTDC2SVTISO_S 1U +#define LRFDRFE_ANAISOCTL_MTDC2SVTISO_ISOLATE 0x00000002U +#define LRFDRFE_ANAISOCTL_MTDC2SVTISO_CONNECT 0x00000000U + +// Field: [0] DIV2MTDCISO +// +// Isolation between DIVBUF and MTDC +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE_ANAISOCTL_DIV2MTDCISO 0x00000001U +#define LRFDRFE_ANAISOCTL_DIV2MTDCISO_M 0x00000001U +#define LRFDRFE_ANAISOCTL_DIV2MTDCISO_S 0U +#define LRFDRFE_ANAISOCTL_DIV2MTDCISO_ISOLATE 0x00000001U +#define LRFDRFE_ANAISOCTL_DIV2MTDCISO_CONNECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVCTL +// +//***************************************************************************** +// Field: [15] DIV2PH180 +// +// DIV2 PH180 path control +// +// Enable DIV2 PH180 path +// INTERNAL NOTE: +// renamed from EN_DIV2_PH180 +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE_DIVCTL_DIV2PH180 0x00008000U +#define LRFDRFE_DIVCTL_DIV2PH180_M 0x00008000U +#define LRFDRFE_DIVCTL_DIV2PH180_S 15U +#define LRFDRFE_DIVCTL_DIV2PH180_EN 0x00008000U +#define LRFDRFE_DIVCTL_DIV2PH180_DIS 0x00000000U + +// Field: [14] DIV2PH0 +// +// DIV2 PH0 path control +// +// Enable DIV2 PH0 path +// INTERNAL NOTE: +// renamed from EN_DIV2_PH0 +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE_DIVCTL_DIV2PH0 0x00004000U +#define LRFDRFE_DIVCTL_DIV2PH0_M 0x00004000U +#define LRFDRFE_DIVCTL_DIV2PH0_S 14U +#define LRFDRFE_DIVCTL_DIV2PH0_EN 0x00004000U +#define LRFDRFE_DIVCTL_DIV2PH0_DIS 0x00000000U + +// Field: [13] DIV2PH270 +// +// DIV2 PH270 path control +// +// Enable DIV2 PH270 path +// +// INTERNAL NOTE: +// renamed from EN_DIV2_PH270 +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE_DIVCTL_DIV2PH270 0x00002000U +#define LRFDRFE_DIVCTL_DIV2PH270_M 0x00002000U +#define LRFDRFE_DIVCTL_DIV2PH270_S 13U +#define LRFDRFE_DIVCTL_DIV2PH270_EN 0x00002000U +#define LRFDRFE_DIVCTL_DIV2PH270_DIS 0x00000000U + +// Field: [12] DIV2PH90 +// +// DIV2 PH90 path control +// +// Enable DIV2 PH90 path +// INTERNAL NOTE: +// renamed from EN_DIV2_PH90 +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE_DIVCTL_DIV2PH90 0x00001000U +#define LRFDRFE_DIVCTL_DIV2PH90_M 0x00001000U +#define LRFDRFE_DIVCTL_DIV2PH90_S 12U +#define LRFDRFE_DIVCTL_DIV2PH90_EN 0x00001000U +#define LRFDRFE_DIVCTL_DIV2PH90_DIS 0x00000000U + +// Field: [11] SPARE11 +// +// Reserved +// ENUMs: +// ONE Bit is one +// ZERO Bit is 0 +#define LRFDRFE_DIVCTL_SPARE11 0x00000800U +#define LRFDRFE_DIVCTL_SPARE11_M 0x00000800U +#define LRFDRFE_DIVCTL_SPARE11_S 11U +#define LRFDRFE_DIVCTL_SPARE11_ONE 0x00000800U +#define LRFDRFE_DIVCTL_SPARE11_ZERO 0x00000000U + +// Field: [10] S1G20DBMMUX +// +// Not connected +// ENUMs: +// DISABLE Disable mux +// ENABLEN Enable mux +#define LRFDRFE_DIVCTL_S1G20DBMMUX 0x00000400U +#define LRFDRFE_DIVCTL_S1G20DBMMUX_M 0x00000400U +#define LRFDRFE_DIVCTL_S1G20DBMMUX_S 10U +#define LRFDRFE_DIVCTL_S1G20DBMMUX_DISABLE 0x00000400U +#define LRFDRFE_DIVCTL_S1G20DBMMUX_ENABLEN 0x00000000U + +// Field: [9] ADCDIV +// +// ADC divider control +// +// Field enables divider that generates IFADC clock. +// +// INTERNAL NOTE: +// Renamed from EN_ADC +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_ADCDIV 0x00000200U +#define LRFDRFE_DIVCTL_ADCDIV_M 0x00000200U +#define LRFDRFE_DIVCTL_ADCDIV_S 9U +#define LRFDRFE_DIVCTL_ADCDIV_EN 0x00000200U +#define LRFDRFE_DIVCTL_ADCDIV_DIS 0x00000000U + +// Field: [8] ENSYNTH +// +// Enables CKVD clock to MTDC +// ENUMs: +// EN Clock is enabled +// DIS Clock is disabled +#define LRFDRFE_DIVCTL_ENSYNTH 0x00000100U +#define LRFDRFE_DIVCTL_ENSYNTH_M 0x00000100U +#define LRFDRFE_DIVCTL_ENSYNTH_S 8U +#define LRFDRFE_DIVCTL_ENSYNTH_EN 0x00000100U +#define LRFDRFE_DIVCTL_ENSYNTH_DIS 0x00000000U + +// Field: [7] TXPH18020DBMDIV +// +// Not connected +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_TXPH18020DBMDIV 0x00000080U +#define LRFDRFE_DIVCTL_TXPH18020DBMDIV_M 0x00000080U +#define LRFDRFE_DIVCTL_TXPH18020DBMDIV_S 7U +#define LRFDRFE_DIVCTL_TXPH18020DBMDIV_EN 0x00000080U +#define LRFDRFE_DIVCTL_TXPH18020DBMDIV_DIS 0x00000000U + +// Field: [6] TXPH020DBMDIV +// +// Not connected +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_TXPH020DBMDIV 0x00000040U +#define LRFDRFE_DIVCTL_TXPH020DBMDIV_M 0x00000040U +#define LRFDRFE_DIVCTL_TXPH020DBMDIV_S 6U +#define LRFDRFE_DIVCTL_TXPH020DBMDIV_EN 0x00000040U +#define LRFDRFE_DIVCTL_TXPH020DBMDIV_DIS 0x00000000U + +// Field: [5] TXPH180DIV +// +// TX 180-phase divider control +// +// Field enables divider that generates inverted TX RF signal to PA. +// +// INTERNAL NOTE: +// renamed from EN_TX_PH180, there is no such thing as a TX clock +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_TXPH180DIV 0x00000020U +#define LRFDRFE_DIVCTL_TXPH180DIV_M 0x00000020U +#define LRFDRFE_DIVCTL_TXPH180DIV_S 5U +#define LRFDRFE_DIVCTL_TXPH180DIV_EN 0x00000020U +#define LRFDRFE_DIVCTL_TXPH180DIV_DIS 0x00000000U + +// Field: [4] TXPH0DIV +// +// TX 0-phase divider control +// +// Field enables divider that generates TX RF signal to PA. +// +// INTERNAL NOTE: +// renamed from EN_TX_PH0, there is no such thing as a TX clock +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_TXPH0DIV 0x00000010U +#define LRFDRFE_DIVCTL_TXPH0DIV_M 0x00000010U +#define LRFDRFE_DIVCTL_TXPH0DIV_S 4U +#define LRFDRFE_DIVCTL_TXPH0DIV_EN 0x00000010U +#define LRFDRFE_DIVCTL_TXPH0DIV_DIS 0x00000000U + +// Field: [3] RXPH90DIV +// +// RX quadrature-phase LO divider control +// +// Field enables quadrature-phase RX LO divider. +// +// INTERNAL NOTE: +// renamed form EN_RX_Q, Oddgeir mentioned that original text was wrong wrt +// phase. +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_RXPH90DIV 0x00000008U +#define LRFDRFE_DIVCTL_RXPH90DIV_M 0x00000008U +#define LRFDRFE_DIVCTL_RXPH90DIV_S 3U +#define LRFDRFE_DIVCTL_RXPH90DIV_EN 0x00000008U +#define LRFDRFE_DIVCTL_RXPH90DIV_DIS 0x00000000U + +// Field: [2] RXPH0DIV +// +// RX in-phase LO divider control +// +// Field enables in-phase RX LO divider. +// +// INTERNAL NOTE: +// renamed form EN_RX_I, Oddgeir mentioned that original text was wrong wrt +// phase. +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE_DIVCTL_RXPH0DIV 0x00000004U +#define LRFDRFE_DIVCTL_RXPH0DIV_M 0x00000004U +#define LRFDRFE_DIVCTL_RXPH0DIV_S 2U +#define LRFDRFE_DIVCTL_RXPH0DIV_EN 0x00000004U +#define LRFDRFE_DIVCTL_RXPH0DIV_DIS 0x00000000U + +// Field: [1] Spare1 +// +// Not connected, not used in LRF +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_DIVCTL_SPARE1 0x00000002U +#define LRFDRFE_DIVCTL_SPARE1_M 0x00000002U +#define LRFDRFE_DIVCTL_SPARE1_S 1U +#define LRFDRFE_DIVCTL_SPARE1_ONE 0x00000002U +#define LRFDRFE_DIVCTL_SPARE1_ZERO 0x00000000U + +// Field: [0] EN +// +// Divider enable +// ENUMs: +// ON Enable divider +// OFF Disable divider +#define LRFDRFE_DIVCTL_EN 0x00000001U +#define LRFDRFE_DIVCTL_EN_M 0x00000001U +#define LRFDRFE_DIVCTL_EN_S 0U +#define LRFDRFE_DIVCTL_EN_ON 0x00000001U +#define LRFDRFE_DIVCTL_EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RXCTRL +// +//***************************************************************************** +// Field: [12] SPARE +// +// Reserved for future use +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE_RXCTRL_SPARE 0x00001000U +#define LRFDRFE_RXCTRL_SPARE_M 0x00001000U +#define LRFDRFE_RXCTRL_SPARE_S 12U +#define LRFDRFE_RXCTRL_SPARE_ONE 0x00001000U +#define LRFDRFE_RXCTRL_SPARE_ZERO 0x00000000U + +// Field: [11:9] ATTN +// +// Attenuator Control +// ENUMs: +// _21DB 21dB attenuation +// _18DB 18dB attenuation +// _15DB 15dB attenuation +// _12DB 12dB attenuation +// _9DB 9dB attenuation +// _6DB 6dB attenuation +// _3DB 3dB attenuation +// NOATT No attenuation +#define LRFDRFE_RXCTRL_ATTN_W 3U +#define LRFDRFE_RXCTRL_ATTN_M 0x00000E00U +#define LRFDRFE_RXCTRL_ATTN_S 9U +#define LRFDRFE_RXCTRL_ATTN__21DB 0x00000E00U +#define LRFDRFE_RXCTRL_ATTN__18DB 0x00000C00U +#define LRFDRFE_RXCTRL_ATTN__15DB 0x00000A00U +#define LRFDRFE_RXCTRL_ATTN__12DB 0x00000800U +#define LRFDRFE_RXCTRL_ATTN__9DB 0x00000600U +#define LRFDRFE_RXCTRL_ATTN__6DB 0x00000400U +#define LRFDRFE_RXCTRL_ATTN__3DB 0x00000200U +#define LRFDRFE_RXCTRL_ATTN_NOATT 0x00000000U + +// Field: [8:4] IFAMPGC +// +// IFAMP Gain Control +// ENUMs: +// MAX Set IFAMP gain to MAX +// MIN3DB Set gain to MAX - 3 dB +// MIN6DB Set gain to MAX - 6 dB +// MIN9DB Set gain to MAX - 9 dB +// MIN12DB Set gain to MAX - 12 dB +// MIN15DB Set gain to MAX - 15 dB +#define LRFDRFE_RXCTRL_IFAMPGC_W 5U +#define LRFDRFE_RXCTRL_IFAMPGC_M 0x000001F0U +#define LRFDRFE_RXCTRL_IFAMPGC_S 4U +#define LRFDRFE_RXCTRL_IFAMPGC_MAX 0x000001F0U +#define LRFDRFE_RXCTRL_IFAMPGC_MIN3DB 0x000000F0U +#define LRFDRFE_RXCTRL_IFAMPGC_MIN6DB 0x00000070U +#define LRFDRFE_RXCTRL_IFAMPGC_MIN9DB 0x00000030U +#define LRFDRFE_RXCTRL_IFAMPGC_MIN12DB 0x00000010U +#define LRFDRFE_RXCTRL_IFAMPGC_MIN15DB 0x00000000U + +// Field: [3:0] LNAGAIN +// +// LNA Gain Control +// ENUMs: +// MAX Set gain to MAX +// MIN3DB Set gain to MAX - 3 dB +// MIN6DB Set gain to MAX - 6 dB +// MIN9DB Set gain to MAX - 9 dB +// MIN12DB Set gain to MAX - 12 dB +#define LRFDRFE_RXCTRL_LNAGAIN_W 4U +#define LRFDRFE_RXCTRL_LNAGAIN_M 0x0000000FU +#define LRFDRFE_RXCTRL_LNAGAIN_S 0U +#define LRFDRFE_RXCTRL_LNAGAIN_MAX 0x0000000FU +#define LRFDRFE_RXCTRL_LNAGAIN_MIN3DB 0x00000007U +#define LRFDRFE_RXCTRL_LNAGAIN_MIN6DB 0x00000003U +#define LRFDRFE_RXCTRL_LNAGAIN_MIN9DB 0x00000001U +#define LRFDRFE_RXCTRL_LNAGAIN_MIN12DB 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNACC0 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Accumulated magnitude over the period +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MAGNACC0_VAL_W 16U +#define LRFDRFE_MAGNACC0_VAL_M 0x0000FFFFU +#define LRFDRFE_MAGNACC0_VAL_S 0U +#define LRFDRFE_MAGNACC0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_MAGNACC0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MAGNACC1 +// +//***************************************************************************** +// Field: [15:0] VAL +// +// Accumulated magnitude over the period +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_MAGNACC1_VAL_W 16U +#define LRFDRFE_MAGNACC1_VAL_M 0x0000FFFFU +#define LRFDRFE_MAGNACC1_VAL_S 0U +#define LRFDRFE_MAGNACC1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE_MAGNACC1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RSSI +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Current RSSI value (signed). If this register reads as -128 (0x80) it means +// that the value is not yet valid. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_RSSI_VAL_W 8U +#define LRFDRFE_RSSI_VAL_M 0x000000FFU +#define LRFDRFE_RSSI_VAL_S 0U +#define LRFDRFE_RSSI_VAL_ALLONES 0x000000FFU +#define LRFDRFE_RSSI_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RSSIMAX +// +//***************************************************************************** +// Field: [7:0] VAL +// +// Maximum RSSI value since start of measurements cycle. If this field reads as +// -128 (0x80) it means that the value is not yet valid. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_RSSIMAX_VAL_W 8U +#define LRFDRFE_RSSIMAX_VAL_M 0x000000FFU +#define LRFDRFE_RSSIMAX_VAL_S 0U +#define LRFDRFE_RSSIMAX_VAL_ALLONES 0x000000FFU +#define LRFDRFE_RSSIMAX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_RFGAIN +// +//***************************************************************************** +// Field: [7:0] DBGAIN +// +// Current RF front-end gain, in dB +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_RFGAIN_DBGAIN_W 8U +#define LRFDRFE_RFGAIN_DBGAIN_M 0x000000FFU +#define LRFDRFE_RFGAIN_DBGAIN_S 0U +#define LRFDRFE_RFGAIN_DBGAIN_ALLONES 0x000000FFU +#define LRFDRFE_RFGAIN_DBGAIN_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_IFADCSTAT +// +//***************************************************************************** +// Field: [6:2] QUANTCALVAL +// +// Result of quantizer calibration. Valid only when calibration is done +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE_IFADCSTAT_QUANTCALVAL_W 5U +#define LRFDRFE_IFADCSTAT_QUANTCALVAL_M 0x0000007CU +#define LRFDRFE_IFADCSTAT_QUANTCALVAL_S 2U +#define LRFDRFE_IFADCSTAT_QUANTCALVAL_COMP1 0x00000004U +#define LRFDRFE_IFADCSTAT_QUANTCALVAL_COMP0 0x00000000U + +// Field: [1] QUANTCALDONE +// +// Status of the quantizer calibration +// ENUMs: +// READY Calibration is complete +// NOT_READY Calibration is not finished +#define LRFDRFE_IFADCSTAT_QUANTCALDONE 0x00000002U +#define LRFDRFE_IFADCSTAT_QUANTCALDONE_M 0x00000002U +#define LRFDRFE_IFADCSTAT_QUANTCALDONE_S 1U +#define LRFDRFE_IFADCSTAT_QUANTCALDONE_READY 0x00000002U +#define LRFDRFE_IFADCSTAT_QUANTCALDONE_NOT_READY 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVSTA +// +//***************************************************************************** +// Field: [0] STAT +// +// Indicates status of serial divider +// ENUMs: +// BUSY Serial divider is busy and result is not available +// yet +// IDLE Serial divider is idle +#define LRFDRFE_DIVSTA_STAT 0x00000001U +#define LRFDRFE_DIVSTA_STAT_M 0x00000001U +#define LRFDRFE_DIVSTA_STAT_S 0U +#define LRFDRFE_DIVSTA_STAT_BUSY 0x00000001U +#define LRFDRFE_DIVSTA_STAT_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVIDENDL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// Dividend input (write only, reads as 0x0). +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIVIDENDL_VALLSB_W 16U +#define LRFDRFE_DIVIDENDL_VALLSB_M 0x0000FFFFU +#define LRFDRFE_DIVIDENDL_VALLSB_S 0U +#define LRFDRFE_DIVIDENDL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDRFE_DIVIDENDL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVIDENDH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// Dividend input (write only, reads as 0x0). +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIVIDENDH_VALMSB_W 16U +#define LRFDRFE_DIVIDENDH_VALMSB_M 0x0000FFFFU +#define LRFDRFE_DIVIDENDH_VALMSB_S 0U +#define LRFDRFE_DIVIDENDH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_DIVIDENDH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVISORL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// Divisor input. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIVISORL_VALLSB_W 16U +#define LRFDRFE_DIVISORL_VALLSB_M 0x0000FFFFU +#define LRFDRFE_DIVISORL_VALLSB_S 0U +#define LRFDRFE_DIVISORL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDRFE_DIVISORL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_DIVISORH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// Divisor input +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_DIVISORH_VALMSB_W 16U +#define LRFDRFE_DIVISORH_VALMSB_M 0x0000FFFFU +#define LRFDRFE_DIVISORH_VALMSB_S 0U +#define LRFDRFE_DIVISORH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_DIVISORH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_QUOTIENTL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// Quotient output +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_QUOTIENTL_VALLSB_W 16U +#define LRFDRFE_QUOTIENTL_VALLSB_M 0x0000FFFFU +#define LRFDRFE_QUOTIENTL_VALLSB_S 0U +#define LRFDRFE_QUOTIENTL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDRFE_QUOTIENTL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_QUOTIENTH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// Quotient output +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_QUOTIENTH_VALMSB_W 16U +#define LRFDRFE_QUOTIENTH_VALMSB_M 0x0000FFFFU +#define LRFDRFE_QUOTIENTH_VALMSB_S 0U +#define LRFDRFE_QUOTIENTH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_QUOTIENTH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRODUCTL +// +//***************************************************************************** +// Field: [15:0] VALLSB +// +// Product of DIVISORL_VALLSB and DIVISORH_VALMSB +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRODUCTL_VALLSB_W 16U +#define LRFDRFE_PRODUCTL_VALLSB_M 0x0000FFFFU +#define LRFDRFE_PRODUCTL_VALLSB_S 0U +#define LRFDRFE_PRODUCTL_VALLSB_ALLONES 0x0000FFFFU +#define LRFDRFE_PRODUCTL_VALLSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_PRODUCTH +// +//***************************************************************************** +// Field: [15:0] VALMSB +// +// Upper 16-bit of DIVISORL.VALLSB multiplied by DIVISORH.VALMSB +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE_PRODUCTH_VALMSB_W 16U +#define LRFDRFE_PRODUCTH_VALMSB_M 0x0000FFFFU +#define LRFDRFE_PRODUCTH_VALMSB_S 0U +#define LRFDRFE_PRODUCTH_VALMSB_ALLONES 0x0000FFFFU +#define LRFDRFE_PRODUCTH_VALMSB_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MULTSTA +// +//***************************************************************************** +// Field: [0] STAT +// +// Multiplier result ready / HW multiplier idle +// ENUMs: +// BUSY Multiplier is busy, result is not ready yet +// IDLE Multiplier is idle +#define LRFDRFE_MULTSTA_STAT 0x00000001U +#define LRFDRFE_MULTSTA_STAT_M 0x00000001U +#define LRFDRFE_MULTSTA_STAT_S 0U +#define LRFDRFE_MULTSTA_STAT_BUSY 0x00000001U +#define LRFDRFE_MULTSTA_STAT_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE_O_MULTCFG +// +//***************************************************************************** +// Field: [0] MODE +// +// Controls unsigned / signed mode of serial multiplier +// ENUMs: +// SIGNED Multiplier assumes inputs are signed numbers +// UNSIGNED Multiplier assumes inputs are unsigned numbers +#define LRFDRFE_MULTCFG_MODE 0x00000001U +#define LRFDRFE_MULTCFG_MODE_M 0x00000001U +#define LRFDRFE_MULTCFG_MODE_S 0U +#define LRFDRFE_MULTCFG_MODE_SIGNED 0x00000001U +#define LRFDRFE_MULTCFG_MODE_UNSIGNED 0x00000000U + + +#endif // __LRFDRFE__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe32.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe32.h new file mode 100644 index 00000000..9aa133b0 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrfe32.h @@ -0,0 +1,6236 @@ +/****************************************************************************** +* Filename: hw_lrfdrfe32_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDRFE32_H__ +#define __HW_LRFDRFE32_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDRFE32 component +// +//***************************************************************************** +// RF Engine Enable Register +#define LRFDRFE32_O_FWSRC_ENABLE 0x00000000U + +// RF Engine Initialization Register +#define LRFDRFE32_O_PDREQ_INIT 0x00000004U + +// RFE Event Flag Register 0 +#define LRFDRFE32_O_EVT1_EVT0 0x00000008U + +// RFE Event Mask Register 0 +#define LRFDRFE32_O_EVTMSK1_EVTMSK0 0x0000000CU + +// RFE Event Clear Register 0 +#define LRFDRFE32_O_EVTCLR1_EVTCLR0 0x00000010U + +// Status of the HFXT +#define LRFDRFE32_O_HFXTSTAT 0x00000014U + +// RF state indication +#define LRFDRFE32_O_RFSTATE 0x00000018U + +// RFE API Command Register +#define LRFDRFE32_O_CMDPAR0_API 0x00000024U + +// RFE Command Parameter 1 +#define LRFDRFE32_O_MSGBOX_CMDPAR1 0x00000028U + +// RFE-to-MCE Send Data Register +#define LRFDRFE32_O_MCEDATIN0_MCEDATOUT0 0x0000002CU + +// RFE-to-MCE Send Command Register +#define LRFDRFE32_O_MCECMDIN_MCECMDOUT 0x00000030U + +// RFE-to-PBE Send Data Register +#define LRFDRFE32_O_PBEDATIN0_PBEDATOUT0 0x00000034U + +// RFE-to-PBE Send Command Register +#define LRFDRFE32_O_PBECMDIN_PBECMDOUT 0x00000038U + +// RFE FW Strobe Register +#define LRFDRFE32_O_STRB 0x0000003CU + +// Controls automatic comparison of magnitude with threshold +#define LRFDRFE32_O_MAGNTHR_MAGNTHRCFG 0x00000040U + +// RSSI Offset Adjustment Register +#define LRFDRFE32_O_GAINCTL_RSSIOFFSET 0x00000044U + +// Magnitude estimator 0 control register +#define LRFDRFE32_O_MAGNCTL1_MAGNCTL0 0x00000048U + +// Spare Value +#define LRFDRFE32_O_SPARE1_SPARE0 0x0000004CU + +// Spare Value +#define LRFDRFE32_O_SPARE3_SPARE2 0x00000050U + +// Spare Value +#define LRFDRFE32_O_SPARE5_SPARE4 0x00000054U + +// LNA control +#define LRFDRFE32_O_IFAMPRFLDO_LNA 0x00000058U + +// PA control register +#define LRFDRFE32_O_PA1_PA0 0x0000005CU + +// ULNA control, TRX only +#define LRFDRFE32_O_IFADC0_ULNA 0x00000060U + +// IFADC configuration register +#define LRFDRFE32_O_IFADCLF_IFADC1 0x00000064U + +// IFADC configuration register +#define LRFDRFE32_O_IFADCALDO_IFADCQUANT 0x00000068U + +// IFADCLDO configuration register +#define LRFDRFE32_O_IFADCTST_IFADCDLDO 0x0000006CU + +// Analog test register +#define LRFDRFE32_O_ATSTREF 0x00000070U + +// DCO Control +#define LRFDRFE32_O_DIV_DCO 0x00000074U + +// LDO control +#define LRFDRFE32_O_TDCLDO_DIVLDO 0x00000078U + +// LDO control +#define LRFDRFE32_O_DCOLDO1_DCOLDO0 0x0000007CU + +// Predivider configuration +#define LRFDRFE32_O_PRE1_PRE0 0x00000080U + +// Predivider configuration +#define LRFDRFE32_O_PRE3_PRE2 0x00000084U + +// Calibration Configuration 0 +#define LRFDRFE32_O_CAL1_CAL0 0x00000088U + +// Calibration Configuration 2 +#define LRFDRFE32_O_CAL3_CAL2 0x0000008CU + +// SDM and Delay Configuration +#define LRFDRFE32_O_MISC1_MISC0 0x00000090U + +// Loop Filter Configuration +#define LRFDRFE32_O_LF1_LF0 0x00000094U + +// Phase Configuration +#define LRFDRFE32_O_PHINIT_PHEDISC 0x00000098U + +// PLL Monitor Configuration +#define LRFDRFE32_O_PLLMON1_PLLMON0 0x0000009CU + +// Modulator Configuration +#define LRFDRFE32_O_MOD1_MOD0 0x000000A0U + +// Digital TX Configuration 0 +#define LRFDRFE32_O_DTX1_DTX0 0x000000A4U + +// Digital TX Configuration 2 +#define LRFDRFE32_O_DTX3_DTX2 0x000000A8U + +// Digital TX Configuration 4 +#define LRFDRFE32_O_DTX5_DTX4 0x000000ACU + +// Digital TX Configuration 6 +#define LRFDRFE32_O_DTX7_DTX6 0x000000B0U + +// Digital TX Configuration 8 +#define LRFDRFE32_O_DTX9_DTX8 0x000000B4U + +// Digital TX Configuration 10 +#define LRFDRFE32_O_DTX11_DTX10 0x000000B8U + +// PLL M0 +#define LRFDRFE32_O_PLLM0 0x000000BCU + +// PLL M1 +#define LRFDRFE32_O_PLLM1 0x000000C0U + +// Calibration M +#define LRFDRFE32_O_CALMMID_CALMCRS 0x000000C4U + +// REFCLK Prescaler Load Value +#define LRFDRFE32_O_REFDIV 0x000000C8U + +// DLO control register 0 +#define LRFDRFE32_O_DLOCTL0 0x000000CCU + +// DLO control register 1 +#define LRFDRFE32_O_DLOCTL1 0x000000D0U + +// DCO Override +#define LRFDRFE32_O_DCOOVR1_DCOOVR0 0x000000D4U + +// Data test +#define LRFDRFE32_O_DLOEV_DTST 0x000000D8U + +// DTST read +#define LRFDRFE32_O_FDCOSPANLSB_DTSTRD 0x000000DCU + +// DCO frequency span +#define LRFDRFE32_O_TDCCAL_FDCOSPANMSB 0x000000E0U + +// Calibration Code +#define LRFDRFE32_O_GPI_CALRES 0x000000E4U + +// Math accellerator input value +#define LRFDRFE32_O_LIN2LOGOUT_MATHACCELIN 0x000000E8U + +// Divide by three output register +#define LRFDRFE32_O_TIMCTL_DIVBY3OUT 0x000000ECU + +// RFE Counter Increment Configuration +#define LRFDRFE32_O_TIMPER_TIMINC 0x000000F0U + +// RFE Counter Value +#define LRFDRFE32_O_TIMCAPT_TIMCNT 0x000000F4U + +// RFE Tracer Send Trigger Register +#define LRFDRFE32_O_TRCSTAT_TRCCTRL 0x000000F8U + +// RFE Tracer Commmand Register +#define LRFDRFE32_O_TRCPAR0_TRCCMD 0x000000FCU + +// RFE Tracer Command Parameter Register 1 +#define LRFDRFE32_O_GPOCTL_TRCPAR1 0x00000100U + +// Analog Isolation Control +#define LRFDRFE32_O_DIVCTL_ANAISOCTL 0x00000104U + +// RX Frontend control register +#define LRFDRFE32_O_MAGNACC0_RXCTRL 0x00000108U + +// Magnitude estimator 1 accumulator value +#define LRFDRFE32_O_RSSI_MAGNACC1 0x0000010CU + +// RSSI Maximum Value Register +#define LRFDRFE32_O_RFGAIN_RSSIMAX 0x00000110U + +// IFADC status +#define LRFDRFE32_O_DIVSTA_IFADCSTAT 0x00000114U + +// Serial Divider Dividend Register +#define LRFDRFE32_O_DIVIDEND 0x00000118U + +// Serial Divider Divisor Register +#define LRFDRFE32_O_DIVISOR 0x0000011CU + +// Serial Divider Quotient Register +#define LRFDRFE32_O_QUOTIENT 0x00000120U + +// Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB +#define LRFDRFE32_O_PRODUCT 0x00000124U + +// Serial Multiplier Status Register +#define LRFDRFE32_O_MULTSTA 0x00000128U + +// Serial Multiplier Control Register +#define LRFDRFE32_O_MULTCFG 0x0000012CU + +//***************************************************************************** +// +// Register: LRFDRFE32_O_FWSRC_ENABLE +// +//***************************************************************************** +// Field: [18] DATARAM +// +// ENUMs: +// S2RRAM Use S2RRAM for data +// RFERAM Use RFERAM for data +#define LRFDRFE32_FWSRC_ENABLE_DATARAM 0x00040000U +#define LRFDRFE32_FWSRC_ENABLE_DATARAM_M 0x00040000U +#define LRFDRFE32_FWSRC_ENABLE_DATARAM_S 18U +#define LRFDRFE32_FWSRC_ENABLE_DATARAM_S2RRAM 0x00040000U +#define LRFDRFE32_FWSRC_ENABLE_DATARAM_RFERAM 0x00000000U + +// Field: [17] FWRAM +// +// ENUMs: +// S2RRAM Run code from S2RRAM +// RFERAM Run code from RFERAM +#define LRFDRFE32_FWSRC_ENABLE_FWRAM 0x00020000U +#define LRFDRFE32_FWSRC_ENABLE_FWRAM_M 0x00020000U +#define LRFDRFE32_FWSRC_ENABLE_FWRAM_S 17U +#define LRFDRFE32_FWSRC_ENABLE_FWRAM_S2RRAM 0x00020000U +#define LRFDRFE32_FWSRC_ENABLE_FWRAM_RFERAM 0x00000000U + +// Field: [16] BANK +// +// ENUMs: +// ONE Run code from bank 1 +// ZERO Run code from bank 0 +#define LRFDRFE32_FWSRC_ENABLE_BANK 0x00010000U +#define LRFDRFE32_FWSRC_ENABLE_BANK_M 0x00010000U +#define LRFDRFE32_FWSRC_ENABLE_BANK_S 16U +#define LRFDRFE32_FWSRC_ENABLE_BANK_ONE 0x00010000U +#define LRFDRFE32_FWSRC_ENABLE_BANK_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE32_FWSRC_ENABLE_ACC1 0x00000008U +#define LRFDRFE32_FWSRC_ENABLE_ACC1_M 0x00000008U +#define LRFDRFE32_FWSRC_ENABLE_ACC1_S 3U +#define LRFDRFE32_FWSRC_ENABLE_ACC1_EN 0x00000008U +#define LRFDRFE32_FWSRC_ENABLE_ACC1_DIS 0x00000000U + +// Field: [2] ACC0 +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE32_FWSRC_ENABLE_ACC0 0x00000004U +#define LRFDRFE32_FWSRC_ENABLE_ACC0_M 0x00000004U +#define LRFDRFE32_FWSRC_ENABLE_ACC0_S 2U +#define LRFDRFE32_FWSRC_ENABLE_ACC0_EN 0x00000004U +#define LRFDRFE32_FWSRC_ENABLE_ACC0_DIS 0x00000000U + +// Field: [1] LOCTIM +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE32_FWSRC_ENABLE_LOCTIM 0x00000002U +#define LRFDRFE32_FWSRC_ENABLE_LOCTIM_M 0x00000002U +#define LRFDRFE32_FWSRC_ENABLE_LOCTIM_S 1U +#define LRFDRFE32_FWSRC_ENABLE_LOCTIM_EN 0x00000002U +#define LRFDRFE32_FWSRC_ENABLE_LOCTIM_DIS 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// EN Enable +// DIS Disable +#define LRFDRFE32_FWSRC_ENABLE_TOPSM 0x00000001U +#define LRFDRFE32_FWSRC_ENABLE_TOPSM_M 0x00000001U +#define LRFDRFE32_FWSRC_ENABLE_TOPSM_S 0U +#define LRFDRFE32_FWSRC_ENABLE_TOPSM_EN 0x00000001U +#define LRFDRFE32_FWSRC_ENABLE_TOPSM_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PDREQ_INIT +// +//***************************************************************************** +// Field: [16] TOPSMPDREQ +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ 0x00010000U +#define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_M 0x00010000U +#define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_S 16U +#define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_ONE 0x00010000U +#define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE32_PDREQ_INIT_ACC1 0x00000008U +#define LRFDRFE32_PDREQ_INIT_ACC1_M 0x00000008U +#define LRFDRFE32_PDREQ_INIT_ACC1_S 3U +#define LRFDRFE32_PDREQ_INIT_ACC1_RESET 0x00000008U +#define LRFDRFE32_PDREQ_INIT_ACC1_NO_EFFECT 0x00000000U + +// Field: [2] ACC0 +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE32_PDREQ_INIT_ACC0 0x00000004U +#define LRFDRFE32_PDREQ_INIT_ACC0_M 0x00000004U +#define LRFDRFE32_PDREQ_INIT_ACC0_S 2U +#define LRFDRFE32_PDREQ_INIT_ACC0_RESET 0x00000004U +#define LRFDRFE32_PDREQ_INIT_ACC0_NO_EFFECT 0x00000000U + +// Field: [1] LOCTIM +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE32_PDREQ_INIT_LOCTIM 0x00000002U +#define LRFDRFE32_PDREQ_INIT_LOCTIM_M 0x00000002U +#define LRFDRFE32_PDREQ_INIT_LOCTIM_S 1U +#define LRFDRFE32_PDREQ_INIT_LOCTIM_RESET 0x00000002U +#define LRFDRFE32_PDREQ_INIT_LOCTIM_NO_EFFECT 0x00000000U + +// Field: [0] TOPSM +// +// ENUMs: +// RESET Reset module +// NO_EFFECT No effect +#define LRFDRFE32_PDREQ_INIT_TOPSM 0x00000001U +#define LRFDRFE32_PDREQ_INIT_TOPSM_M 0x00000001U +#define LRFDRFE32_PDREQ_INIT_TOPSM_S 0U +#define LRFDRFE32_PDREQ_INIT_TOPSM_RESET 0x00000001U +#define LRFDRFE32_PDREQ_INIT_TOPSM_NO_EFFECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_EVT1_EVT0 +// +//***************************************************************************** +// Field: [29] PREREFCLK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_PREREFCLK 0x20000000U +#define LRFDRFE32_EVT1_EVT0_PREREFCLK_M 0x20000000U +#define LRFDRFE32_EVT1_EVT0_PREREFCLK_S 29U +#define LRFDRFE32_EVT1_EVT0_PREREFCLK_ONE 0x20000000U +#define LRFDRFE32_EVT1_EVT0_PREREFCLK_ZERO 0x00000000U + +// Field: [28] REFCLK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_REFCLK 0x10000000U +#define LRFDRFE32_EVT1_EVT0_REFCLK_M 0x10000000U +#define LRFDRFE32_EVT1_EVT0_REFCLK_S 28U +#define LRFDRFE32_EVT1_EVT0_REFCLK_ONE 0x10000000U +#define LRFDRFE32_EVT1_EVT0_REFCLK_ZERO 0x00000000U + +// Field: [27] FBLWTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_FBLWTHR 0x08000000U +#define LRFDRFE32_EVT1_EVT0_FBLWTHR_M 0x08000000U +#define LRFDRFE32_EVT1_EVT0_FBLWTHR_S 27U +#define LRFDRFE32_EVT1_EVT0_FBLWTHR_ONE 0x08000000U +#define LRFDRFE32_EVT1_EVT0_FBLWTHR_ZERO 0x00000000U + +// Field: [26] FABVTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_FABVTHR 0x04000000U +#define LRFDRFE32_EVT1_EVT0_FABVTHR_M 0x04000000U +#define LRFDRFE32_EVT1_EVT0_FABVTHR_S 26U +#define LRFDRFE32_EVT1_EVT0_FABVTHR_ONE 0x04000000U +#define LRFDRFE32_EVT1_EVT0_FABVTHR_ZERO 0x00000000U + +// Field: [25] LOCK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_LOCK 0x02000000U +#define LRFDRFE32_EVT1_EVT0_LOCK_M 0x02000000U +#define LRFDRFE32_EVT1_EVT0_LOCK_S 25U +#define LRFDRFE32_EVT1_EVT0_LOCK_ONE 0x02000000U +#define LRFDRFE32_EVT1_EVT0_LOCK_ZERO 0x00000000U + +// Field: [24] LOL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_LOL 0x01000000U +#define LRFDRFE32_EVT1_EVT0_LOL_M 0x01000000U +#define LRFDRFE32_EVT1_EVT0_LOL_S 24U +#define LRFDRFE32_EVT1_EVT0_LOL_ONE 0x01000000U +#define LRFDRFE32_EVT1_EVT0_LOL_ZERO 0x00000000U + +// Field: [23] GPI7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI7 0x00800000U +#define LRFDRFE32_EVT1_EVT0_GPI7_M 0x00800000U +#define LRFDRFE32_EVT1_EVT0_GPI7_S 23U +#define LRFDRFE32_EVT1_EVT0_GPI7_ONE 0x00800000U +#define LRFDRFE32_EVT1_EVT0_GPI7_ZERO 0x00000000U + +// Field: [22] GPI6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI6 0x00400000U +#define LRFDRFE32_EVT1_EVT0_GPI6_M 0x00400000U +#define LRFDRFE32_EVT1_EVT0_GPI6_S 22U +#define LRFDRFE32_EVT1_EVT0_GPI6_ONE 0x00400000U +#define LRFDRFE32_EVT1_EVT0_GPI6_ZERO 0x00000000U + +// Field: [21] GPI5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI5 0x00200000U +#define LRFDRFE32_EVT1_EVT0_GPI5_M 0x00200000U +#define LRFDRFE32_EVT1_EVT0_GPI5_S 21U +#define LRFDRFE32_EVT1_EVT0_GPI5_ONE 0x00200000U +#define LRFDRFE32_EVT1_EVT0_GPI5_ZERO 0x00000000U + +// Field: [20] GPI4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI4 0x00100000U +#define LRFDRFE32_EVT1_EVT0_GPI4_M 0x00100000U +#define LRFDRFE32_EVT1_EVT0_GPI4_S 20U +#define LRFDRFE32_EVT1_EVT0_GPI4_ONE 0x00100000U +#define LRFDRFE32_EVT1_EVT0_GPI4_ZERO 0x00000000U + +// Field: [19] GPI3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI3 0x00080000U +#define LRFDRFE32_EVT1_EVT0_GPI3_M 0x00080000U +#define LRFDRFE32_EVT1_EVT0_GPI3_S 19U +#define LRFDRFE32_EVT1_EVT0_GPI3_ONE 0x00080000U +#define LRFDRFE32_EVT1_EVT0_GPI3_ZERO 0x00000000U + +// Field: [18] GPI2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI2 0x00040000U +#define LRFDRFE32_EVT1_EVT0_GPI2_M 0x00040000U +#define LRFDRFE32_EVT1_EVT0_GPI2_S 18U +#define LRFDRFE32_EVT1_EVT0_GPI2_ONE 0x00040000U +#define LRFDRFE32_EVT1_EVT0_GPI2_ZERO 0x00000000U + +// Field: [17] GPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI1 0x00020000U +#define LRFDRFE32_EVT1_EVT0_GPI1_M 0x00020000U +#define LRFDRFE32_EVT1_EVT0_GPI1_S 17U +#define LRFDRFE32_EVT1_EVT0_GPI1_ONE 0x00020000U +#define LRFDRFE32_EVT1_EVT0_GPI1_ZERO 0x00000000U + +// Field: [16] GPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_GPI0 0x00010000U +#define LRFDRFE32_EVT1_EVT0_GPI0_M 0x00010000U +#define LRFDRFE32_EVT1_EVT0_GPI0_S 16U +#define LRFDRFE32_EVT1_EVT0_GPI0_ONE 0x00010000U +#define LRFDRFE32_EVT1_EVT0_GPI0_ZERO 0x00000000U + +// Field: [14] MAGNTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_MAGNTHR 0x00004000U +#define LRFDRFE32_EVT1_EVT0_MAGNTHR_M 0x00004000U +#define LRFDRFE32_EVT1_EVT0_MAGNTHR_S 14U +#define LRFDRFE32_EVT1_EVT0_MAGNTHR_ONE 0x00004000U +#define LRFDRFE32_EVT1_EVT0_MAGNTHR_ZERO 0x00000000U + +// Field: [13] S2RSTOP +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_S2RSTOP 0x00002000U +#define LRFDRFE32_EVT1_EVT0_S2RSTOP_M 0x00002000U +#define LRFDRFE32_EVT1_EVT0_S2RSTOP_S 13U +#define LRFDRFE32_EVT1_EVT0_S2RSTOP_ONE 0x00002000U +#define LRFDRFE32_EVT1_EVT0_S2RSTOP_ZERO 0x00000000U + +// Field: [12] SYSTCMP2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_SYSTCMP2 0x00001000U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP2_M 0x00001000U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP2_S 12U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP2_ONE 0x00001000U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP2_ZERO 0x00000000U + +// Field: [11] SYSTCMP1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_SYSTCMP1 0x00000800U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP1_M 0x00000800U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP1_S 11U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP1_ONE 0x00000800U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP1_ZERO 0x00000000U + +// Field: [10] SYSTCMP0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_SYSTCMP0 0x00000400U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP0_M 0x00000400U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP0_S 10U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP0_ONE 0x00000400U +#define LRFDRFE32_EVT1_EVT0_SYSTCMP0_ZERO 0x00000000U + +// Field: [9] PBERFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_PBERFEDAT 0x00000200U +#define LRFDRFE32_EVT1_EVT0_PBERFEDAT_M 0x00000200U +#define LRFDRFE32_EVT1_EVT0_PBERFEDAT_S 9U +#define LRFDRFE32_EVT1_EVT0_PBERFEDAT_ONE 0x00000200U +#define LRFDRFE32_EVT1_EVT0_PBERFEDAT_ZERO 0x00000000U + +// Field: [8] MDMRFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_MDMRFEDAT 0x00000100U +#define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_S 8U +#define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_ONE 0x00000100U +#define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_ZERO 0x00000000U + +// Field: [7] DLO +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_DLO 0x00000080U +#define LRFDRFE32_EVT1_EVT0_DLO_M 0x00000080U +#define LRFDRFE32_EVT1_EVT0_DLO_S 7U +#define LRFDRFE32_EVT1_EVT0_DLO_ONE 0x00000080U +#define LRFDRFE32_EVT1_EVT0_DLO_ZERO 0x00000000U + +// Field: [6] PBECMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_PBECMD 0x00000040U +#define LRFDRFE32_EVT1_EVT0_PBECMD_M 0x00000040U +#define LRFDRFE32_EVT1_EVT0_PBECMD_S 6U +#define LRFDRFE32_EVT1_EVT0_PBECMD_ONE 0x00000040U +#define LRFDRFE32_EVT1_EVT0_PBECMD_ZERO 0x00000000U + +// Field: [5] COUNTER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_COUNTER 0x00000020U +#define LRFDRFE32_EVT1_EVT0_COUNTER_M 0x00000020U +#define LRFDRFE32_EVT1_EVT0_COUNTER_S 5U +#define LRFDRFE32_EVT1_EVT0_COUNTER_ONE 0x00000020U +#define LRFDRFE32_EVT1_EVT0_COUNTER_ZERO 0x00000000U + +// Field: [4] MDMCMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_MDMCMD 0x00000010U +#define LRFDRFE32_EVT1_EVT0_MDMCMD_M 0x00000010U +#define LRFDRFE32_EVT1_EVT0_MDMCMD_S 4U +#define LRFDRFE32_EVT1_EVT0_MDMCMD_ONE 0x00000010U +#define LRFDRFE32_EVT1_EVT0_MDMCMD_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_ACC1 0x00000008U +#define LRFDRFE32_EVT1_EVT0_ACC1_M 0x00000008U +#define LRFDRFE32_EVT1_EVT0_ACC1_S 3U +#define LRFDRFE32_EVT1_EVT0_ACC1_ONE 0x00000008U +#define LRFDRFE32_EVT1_EVT0_ACC1_ZERO 0x00000000U + +// Field: [2] ACC0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_ACC0 0x00000004U +#define LRFDRFE32_EVT1_EVT0_ACC0_M 0x00000004U +#define LRFDRFE32_EVT1_EVT0_ACC0_S 2U +#define LRFDRFE32_EVT1_EVT0_ACC0_ONE 0x00000004U +#define LRFDRFE32_EVT1_EVT0_ACC0_ZERO 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_TIMER 0x00000002U +#define LRFDRFE32_EVT1_EVT0_TIMER_M 0x00000002U +#define LRFDRFE32_EVT1_EVT0_TIMER_S 1U +#define LRFDRFE32_EVT1_EVT0_TIMER_ONE 0x00000002U +#define LRFDRFE32_EVT1_EVT0_TIMER_ZERO 0x00000000U + +// Field: [0] RFEAPI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVT1_EVT0_RFEAPI 0x00000001U +#define LRFDRFE32_EVT1_EVT0_RFEAPI_M 0x00000001U +#define LRFDRFE32_EVT1_EVT0_RFEAPI_S 0U +#define LRFDRFE32_EVT1_EVT0_RFEAPI_ONE 0x00000001U +#define LRFDRFE32_EVT1_EVT0_RFEAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_EVTMSK1_EVTMSK0 +// +//***************************************************************************** +// Field: [29] PREREFCLK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK 0x20000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_M 0x20000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_S 29U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_EN 0x20000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_DIS 0x00000000U + +// Field: [28] REFCLK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK 0x10000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_M 0x10000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_S 28U +#define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_EN 0x10000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_DIS 0x00000000U + +// Field: [27] FBLWTHR +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR 0x08000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_M 0x08000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_S 27U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_EN 0x08000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_DIS 0x00000000U + +// Field: [26] FABVTHR +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR 0x04000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_M 0x04000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_S 26U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_EN 0x04000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_DIS 0x00000000U + +// Field: [25] LOCK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK 0x02000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_M 0x02000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_S 25U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_EN 0x02000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_DIS 0x00000000U + +// Field: [24] LOL +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOL 0x01000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_M 0x01000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_S 24U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_EN 0x01000000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_DIS 0x00000000U + +// Field: [23] GPI7 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7 0x00800000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_M 0x00800000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_S 23U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_EN 0x00800000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_DIS 0x00000000U + +// Field: [22] GPI6 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6 0x00400000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_M 0x00400000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_S 22U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_EN 0x00400000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_DIS 0x00000000U + +// Field: [21] GPI5 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5 0x00200000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_M 0x00200000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_S 21U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_EN 0x00200000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_DIS 0x00000000U + +// Field: [20] GPI4 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4 0x00100000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_M 0x00100000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_S 20U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_EN 0x00100000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_DIS 0x00000000U + +// Field: [19] GPI3 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3 0x00080000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_M 0x00080000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_S 19U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_EN 0x00080000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_DIS 0x00000000U + +// Field: [18] GPI2 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2 0x00040000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_M 0x00040000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_S 18U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_EN 0x00040000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_DIS 0x00000000U + +// Field: [17] GPI1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1 0x00020000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_M 0x00020000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_S 17U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_EN 0x00020000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_DIS 0x00000000U + +// Field: [16] GPI0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0 0x00010000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_M 0x00010000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_S 16U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_EN 0x00010000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_DIS 0x00000000U + +// Field: [14] MAGNTHR +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR 0x00004000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_M 0x00004000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_S 14U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_EN 0x00004000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_DIS 0x00000000U + +// Field: [13] S2RSTOP +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP 0x00002000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_M 0x00002000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_S 13U +#define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_EN 0x00002000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_DIS 0x00000000U + +// Field: [12] SYSTCMP2 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2 0x00001000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_M 0x00001000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_S 12U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_EN 0x00001000U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_DIS 0x00000000U + +// Field: [11] SYSTCMP1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1 0x00000800U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_M 0x00000800U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_S 11U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_EN 0x00000800U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_DIS 0x00000000U + +// Field: [10] SYSTCMP0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0 0x00000400U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_M 0x00000400U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_S 10U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_EN 0x00000400U +#define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_DIS 0x00000000U + +// Field: [9] PBERFEDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT 0x00000200U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_M 0x00000200U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_S 9U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_EN 0x00000200U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_DIS 0x00000000U + +// Field: [8] MDMRFEDAT +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT 0x00000100U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_S 8U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_EN 0x00000100U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_DIS 0x00000000U + +// Field: [7] DLO +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_DLO 0x00000080U +#define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_M 0x00000080U +#define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_S 7U +#define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_EN 0x00000080U +#define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_DIS 0x00000000U + +// Field: [6] PBECMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD 0x00000040U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_M 0x00000040U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_S 6U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_EN 0x00000040U +#define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_DIS 0x00000000U + +// Field: [5] COUNTER +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER 0x00000020U +#define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_M 0x00000020U +#define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_S 5U +#define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_EN 0x00000020U +#define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_DIS 0x00000000U + +// Field: [4] MDMCMD +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD 0x00000010U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_M 0x00000010U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_S 4U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_EN 0x00000010U +#define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_DIS 0x00000000U + +// Field: [3] ACC1 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1 0x00000008U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_M 0x00000008U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_S 3U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_EN 0x00000008U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_DIS 0x00000000U + +// Field: [2] ACC0 +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0 0x00000004U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_M 0x00000004U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_S 2U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_EN 0x00000004U +#define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_DIS 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER 0x00000002U +#define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_M 0x00000002U +#define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_S 1U +#define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_EN 0x00000002U +#define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_DIS 0x00000000U + +// Field: [0] RFEAPI +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI 0x00000001U +#define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_M 0x00000001U +#define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_S 0U +#define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_EN 0x00000001U +#define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_EVTCLR1_EVTCLR0 +// +//***************************************************************************** +// Field: [29] PREREFCLK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK 0x20000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_M 0x20000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_S 29U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_ONE 0x20000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_ZERO 0x00000000U + +// Field: [28] REFCLK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK 0x10000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_M 0x10000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_S 28U +#define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_ONE 0x10000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_ZERO 0x00000000U + +// Field: [27] FBLWTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR 0x08000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_M 0x08000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_S 27U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_ONE 0x08000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_ZERO 0x00000000U + +// Field: [26] FABVTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR 0x04000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_M 0x04000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_S 26U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_ONE 0x04000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_ZERO 0x00000000U + +// Field: [25] LOCK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK 0x02000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_M 0x02000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_S 25U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_ONE 0x02000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_ZERO 0x00000000U + +// Field: [24] LOL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOL 0x01000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_M 0x01000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_S 24U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_ONE 0x01000000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_ZERO 0x00000000U + +// Field: [23] GPI7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7 0x00800000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_M 0x00800000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_S 23U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_ONE 0x00800000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_ZERO 0x00000000U + +// Field: [22] GPI6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6 0x00400000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_M 0x00400000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_S 22U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_ONE 0x00400000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_ZERO 0x00000000U + +// Field: [21] GPI5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5 0x00200000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_M 0x00200000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_S 21U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_ONE 0x00200000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_ZERO 0x00000000U + +// Field: [20] GPI4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4 0x00100000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_M 0x00100000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_S 20U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_ONE 0x00100000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_ZERO 0x00000000U + +// Field: [19] GPI3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3 0x00080000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_M 0x00080000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_S 19U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_ONE 0x00080000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_ZERO 0x00000000U + +// Field: [18] GPI2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2 0x00040000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_M 0x00040000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_S 18U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_ONE 0x00040000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_ZERO 0x00000000U + +// Field: [17] GPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1 0x00020000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_M 0x00020000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_S 17U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_ONE 0x00020000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_ZERO 0x00000000U + +// Field: [16] GPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0 0x00010000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_M 0x00010000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_S 16U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_ONE 0x00010000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_ZERO 0x00000000U + +// Field: [14] MAGNTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR 0x00004000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_M 0x00004000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_S 14U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_ONE 0x00004000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_ZERO 0x00000000U + +// Field: [13] S2RSTOP +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP 0x00002000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_M 0x00002000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_S 13U +#define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_ONE 0x00002000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_ZERO 0x00000000U + +// Field: [12] SYSTCMP2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2 0x00001000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_M 0x00001000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_S 12U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_ONE 0x00001000U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_ZERO 0x00000000U + +// Field: [11] SYSTCMP1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1 0x00000800U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_M 0x00000800U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_S 11U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_ONE 0x00000800U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_ZERO 0x00000000U + +// Field: [10] SYSTCMP0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0 0x00000400U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_M 0x00000400U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_S 10U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_ONE 0x00000400U +#define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_ZERO 0x00000000U + +// Field: [9] PBERFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT 0x00000200U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_M 0x00000200U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_S 9U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_ONE 0x00000200U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_ZERO 0x00000000U + +// Field: [8] MDMRFEDAT +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT 0x00000100U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_M 0x00000100U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_S 8U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_ONE 0x00000100U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_ZERO 0x00000000U + +// Field: [7] DLO +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_DLO 0x00000080U +#define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_M 0x00000080U +#define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_S 7U +#define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_ONE 0x00000080U +#define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_ZERO 0x00000000U + +// Field: [6] PBECMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD 0x00000040U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_M 0x00000040U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_S 6U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_ONE 0x00000040U +#define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_ZERO 0x00000000U + +// Field: [5] COUNTER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER 0x00000020U +#define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_M 0x00000020U +#define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_S 5U +#define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_ONE 0x00000020U +#define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_ZERO 0x00000000U + +// Field: [4] MDMCMD +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD 0x00000010U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_M 0x00000010U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_S 4U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_ONE 0x00000010U +#define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_ZERO 0x00000000U + +// Field: [3] ACC1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1 0x00000008U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_M 0x00000008U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_S 3U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_ONE 0x00000008U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_ZERO 0x00000000U + +// Field: [2] ACC0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0 0x00000004U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_M 0x00000004U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_S 2U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_ONE 0x00000004U +#define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_ZERO 0x00000000U + +// Field: [1] TIMER +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER 0x00000002U +#define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_M 0x00000002U +#define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_S 1U +#define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_ONE 0x00000002U +#define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_ZERO 0x00000000U + +// Field: [0] RFEAPI +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI 0x00000001U +#define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_M 0x00000001U +#define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_S 0U +#define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_ONE 0x00000001U +#define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_HFXTSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// ENUMs: +// QUAL Clock signal is qualified +// NONQUAL Clock signal is not qualified +#define LRFDRFE32_HFXTSTAT_STAT 0x00000001U +#define LRFDRFE32_HFXTSTAT_STAT_M 0x00000001U +#define LRFDRFE32_HFXTSTAT_STAT_S 0U +#define LRFDRFE32_HFXTSTAT_STAT_QUAL 0x00000001U +#define LRFDRFE32_HFXTSTAT_STAT_NONQUAL 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_RFSTATE +// +//***************************************************************************** +// Field: [3:0] VAL +// +// ENUMs: +// RX RX is active +// TX TX is active +// SYNTH Synth is running +// IDLE Radio is idle +#define LRFDRFE32_RFSTATE_VAL_W 4U +#define LRFDRFE32_RFSTATE_VAL_M 0x0000000FU +#define LRFDRFE32_RFSTATE_VAL_S 0U +#define LRFDRFE32_RFSTATE_VAL_RX 0x00000003U +#define LRFDRFE32_RFSTATE_VAL_TX 0x00000002U +#define LRFDRFE32_RFSTATE_VAL_SYNTH 0x00000001U +#define LRFDRFE32_RFSTATE_VAL_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_CMDPAR0_API +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CMDPAR0_API_VAL_W 16U +#define LRFDRFE32_CMDPAR0_API_VAL_M 0xFFFF0000U +#define LRFDRFE32_CMDPAR0_API_VAL_S 16U +#define LRFDRFE32_CMDPAR0_API_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_CMDPAR0_API_VAL_ALLZEROS 0x00000000U + +// Field: [7:4] PROTOCOLID +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CMDPAR0_API_PROTOCOLID_W 4U +#define LRFDRFE32_CMDPAR0_API_PROTOCOLID_M 0x000000F0U +#define LRFDRFE32_CMDPAR0_API_PROTOCOLID_S 4U +#define LRFDRFE32_CMDPAR0_API_PROTOCOLID_ALLONES 0x000000F0U +#define LRFDRFE32_CMDPAR0_API_PROTOCOLID_ALLZEROS 0x00000000U + +// Field: [3:0] RFECMD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All bits are 0 +#define LRFDRFE32_CMDPAR0_API_RFECMD_W 4U +#define LRFDRFE32_CMDPAR0_API_RFECMD_M 0x0000000FU +#define LRFDRFE32_CMDPAR0_API_RFECMD_S 0U +#define LRFDRFE32_CMDPAR0_API_RFECMD_ALLONES 0x0000000FU +#define LRFDRFE32_CMDPAR0_API_RFECMD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MSGBOX_CMDPAR1 +// +//***************************************************************************** +// Field: [23:16] MSGBOX_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_W 8U +#define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_M 0x00FF0000U +#define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_S 16U +#define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_ALLONES 0x00FF0000U +#define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] CMDPAR1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_W 16U +#define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_M 0x0000FFFFU +#define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_S 0U +#define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MCEDATIN0_MCEDATOUT0 +// +//***************************************************************************** +// Field: [31:16] MCEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_W 16U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_M 0xFFFF0000U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_S 16U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] MCEDATOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_W 16U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_S 0U +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MCECMDIN_MCECMDOUT +// +//***************************************************************************** +// Field: [19:16] MCECMDIN_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_W 4U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_M 0x000F0000U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_S 16U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_ALLONES 0x000F0000U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_ALLZEROS 0x00000000U + +// Field: [3:0] MCECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_W 4U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_M 0x0000000FU +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_S 0U +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PBEDATIN0_PBEDATOUT0 +// +//***************************************************************************** +// Field: [31:16] PBEDATIN0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_W 16U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_M 0xFFFF0000U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_S 16U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] PBEDATOUT0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_W 16U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_M 0x0000FFFFU +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_S 0U +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PBECMDIN_PBECMDOUT +// +//***************************************************************************** +// Field: [19:16] PBECMDIN_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_W 4U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_M 0x000F0000U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_S 16U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLONES 0x000F0000U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLZEROS 0x00000000U + +// Field: [3:0] PBECMDOUT_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_W 4U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_M 0x0000000FU +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_S 0U +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLONES 0x0000000FU +#define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_STRB +// +//***************************************************************************** +// Field: [7] S2RTRG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_S2RTRG 0x00000080U +#define LRFDRFE32_STRB_S2RTRG_M 0x00000080U +#define LRFDRFE32_STRB_S2RTRG_S 7U +#define LRFDRFE32_STRB_S2RTRG_ONE 0x00000080U +#define LRFDRFE32_STRB_S2RTRG_ZERO 0x00000000U + +// Field: [6] DMATRG +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_DMATRG 0x00000040U +#define LRFDRFE32_STRB_DMATRG_M 0x00000040U +#define LRFDRFE32_STRB_DMATRG_S 6U +#define LRFDRFE32_STRB_DMATRG_ONE 0x00000040U +#define LRFDRFE32_STRB_DMATRG_ZERO 0x00000000U + +// Field: [5] SYSTCPT2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_SYSTCPT2 0x00000020U +#define LRFDRFE32_STRB_SYSTCPT2_M 0x00000020U +#define LRFDRFE32_STRB_SYSTCPT2_S 5U +#define LRFDRFE32_STRB_SYSTCPT2_ONE 0x00000020U +#define LRFDRFE32_STRB_SYSTCPT2_ZERO 0x00000000U + +// Field: [4] SYSTCPT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_SYSTCPT1 0x00000010U +#define LRFDRFE32_STRB_SYSTCPT1_M 0x00000010U +#define LRFDRFE32_STRB_SYSTCPT1_S 4U +#define LRFDRFE32_STRB_SYSTCPT1_ONE 0x00000010U +#define LRFDRFE32_STRB_SYSTCPT1_ZERO 0x00000000U + +// Field: [3] SYSTCPT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_SYSTCPT0 0x00000008U +#define LRFDRFE32_STRB_SYSTCPT0_M 0x00000008U +#define LRFDRFE32_STRB_SYSTCPT0_S 3U +#define LRFDRFE32_STRB_SYSTCPT0_ONE 0x00000008U +#define LRFDRFE32_STRB_SYSTCPT0_ZERO 0x00000000U + +// Field: [2] EVT1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_EVT1 0x00000004U +#define LRFDRFE32_STRB_EVT1_M 0x00000004U +#define LRFDRFE32_STRB_EVT1_S 2U +#define LRFDRFE32_STRB_EVT1_ONE 0x00000004U +#define LRFDRFE32_STRB_EVT1_ZERO 0x00000000U + +// Field: [1] EVT0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_STRB_EVT0 0x00000002U +#define LRFDRFE32_STRB_EVT0_M 0x00000002U +#define LRFDRFE32_STRB_EVT0_S 1U +#define LRFDRFE32_STRB_EVT0_ONE 0x00000002U +#define LRFDRFE32_STRB_EVT0_ZERO 0x00000000U + +// Field: [0] CMDDONE +// +// ENUMs: +// YES The bit is 1 +// NO The bit is 0 +#define LRFDRFE32_STRB_CMDDONE 0x00000001U +#define LRFDRFE32_STRB_CMDDONE_M 0x00000001U +#define LRFDRFE32_STRB_CMDDONE_S 0U +#define LRFDRFE32_STRB_CMDDONE_YES 0x00000001U +#define LRFDRFE32_STRB_CMDDONE_NO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MAGNTHR_MAGNTHRCFG +// +//***************************************************************************** +// Field: [23:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_W 8U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_M 0x00FF0000U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_S 16U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_ALLONES 0x00FF0000U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_ALLZEROS 0x00000000U + +// Field: [1] SEL +// +// ENUMs: +// MAGNACC1 Use MAGNACC1 in the compare against the theshold +// in MANGTHR +// MAGNACC0 Use MAGNACC0 in the compare against the theshold +// in MANGTHR +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL 0x00000002U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_M 0x00000002U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_S 1U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_MAGNACC1 0x00000002U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_MAGNACC0 0x00000000U + +// Field: [0] CTL +// +// ENUMs: +// EN Enable automatic comparison of magntude with +// threshold (input of lin2log is driven by HW) +// DIS Disable automatic comparison with threshold (input +// of lin2log is driven by FW) +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL 0x00000001U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_M 0x00000001U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_S 0U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_EN 0x00000001U +#define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_GAINCTL_RSSIOFFSET +// +//***************************************************************************** +// Field: [19:18] BDE2DVGA +// +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_W 2U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_M 0x000C0000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_S 18U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN8 0x000C0000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN4 0x00080000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN2 0x00040000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN1 0x00000000U + +// Field: [17:16] BDE1DVGA +// +// ENUMs: +// GAIN8 Gain 8 +// GAIN4 Gain 4 +// GAIN2 Gain 2 +// GAIN1 Gain 1 +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_W 2U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_M 0x00030000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_S 16U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN8 0x00030000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN4 0x00020000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN2 0x00010000U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN1 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_W 8U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_M 0x000000FFU +#define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_S 0U +#define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_ALLONES 0x000000FFU +#define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MAGNCTL1_MAGNCTL0 +// +//***************************************************************************** +// Field: [28] MAGNCTL1_PERMODE +// +// ENUMs: +// PERIODIC Periodic mode +// ONESHOT One-shot mode +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE 0x10000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_M 0x10000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_S 28U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_PERIODIC 0x10000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_ONESHOT 0x00000000U + +// Field: [27:24] MAGNCTL1_SCL +// +// ENUMs: +// DIV256 1/256 +// DIV128 1/128 +// DIV64 1/64 +// DIV32 1/32 +// DIV16 1/16 +// DIV8 +// DIV4 +// DIV2 +// DIV1 1/1 (no scaling) +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_W 4U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_M 0x0F000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_S 24U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV256 0x08000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV128 0x07000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV64 0x06000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV32 0x05000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV16 0x04000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV8 0x03000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV4 0x02000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV2 0x01000000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV1 0x00000000U + +// Field: [23:16] MAGNCTL1_PER +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_W 8U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_M 0x00FF0000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_S 16U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_ALLONES 0x00FF0000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_ALLZEROS 0x00000000U + +// Field: [12] MAGNCTL0_PERMODE +// +// ENUMs: +// PERIODIC Periodic mode +// ONESHOT One-shot mode +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE 0x00001000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_M 0x00001000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_S 12U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_PERIODIC 0x00001000U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_ONESHOT 0x00000000U + +// Field: [11:8] MAGNCTL0_SCL +// +// ENUMs: +// DIV256 1/256 +// DIV128 1/128 +// DIV64 1/64 +// DIV32 1/32 +// DIV16 1/16 +// DIV8 +// DIV4 +// DIV2 +// DIV1 1/1 (no scaling) +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_W 4U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_M 0x00000F00U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_S 8U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV256 0x00000800U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV128 0x00000700U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV64 0x00000600U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV32 0x00000500U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV16 0x00000400U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV8 0x00000300U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV4 0x00000200U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV2 0x00000100U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV1 0x00000000U + +// Field: [7:0] MAGNCTL0_PER +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_W 8U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_M 0x000000FFU +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_S 0U +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_ALLONES 0x000000FFU +#define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_SPARE1_SPARE0 +// +//***************************************************************************** +// Field: [31:16] SPARE1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_W 16U +#define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_M 0xFFFF0000U +#define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_S 16U +#define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] SPARE0_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_W 16U +#define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_M 0x0000FFFFU +#define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_S 0U +#define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_SPARE3_SPARE2 +// +//***************************************************************************** +// Field: [31:16] SPARE3_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_W 16U +#define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_M 0xFFFF0000U +#define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_S 16U +#define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] SPARE2_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_W 16U +#define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_M 0x0000FFFFU +#define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_S 0U +#define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_SPARE5_SPARE4 +// +//***************************************************************************** +// Field: [31:16] SPARE5_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_W 16U +#define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_M 0xFFFF0000U +#define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_S 16U +#define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] SPARE4_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_W 16U +#define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_M 0x0000FFFFU +#define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_S 0U +#define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_IFAMPRFLDO_LNA +// +//***************************************************************************** +// Field: [31:25] IFAMPRFLDO_TRIM +// +// ENUMs: +// BYPASS Regulator is in bypass mode +// MAX Maximum output voltage +// MIN Minimum output voltage +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_W 7U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_M 0xFE000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_S 25U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_BYPASS 0xFE000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_MAX 0xFC000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_MIN 0x00000000U + +// Field: [24] IFAMPRFLDO_EN +// +// ENUMs: +// EN Enable regulator +// DIS Disable regulator +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN 0x01000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_M 0x01000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_S 24U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_EN 0x01000000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_DIS 0x00000000U + +// Field: [23:20] IFAMPRFLDO_AAFCAP +// +// ENUMs: +// MAX Largest capacitance on IFAMP output. Low BW +// MIN Smallest capacitance on IFAMP output. High BW. +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_W 4U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_M 0x00F00000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_S 20U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_MAX 0x00F00000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_MIN 0x00000000U + +// Field: [19:17] IFAMPRFLDO_IFAMPIB +// +// ENUMs: +// MAX Max IB +// MIN Minimum IB +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_W 3U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_M 0x000E0000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_S 17U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_MAX 0x000E0000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_MIN 0x00000000U + +// Field: [16] IFAMPRFLDO_IFAMP +// +// ENUMs: +// EN Enable IFAMP +// DIS Disable IFAMP +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP 0x00010000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_M 0x00010000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_S 16U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_EN 0x00010000U +#define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_DIS 0x00000000U + +// Field: [15:8] LNA_SPARE +// +// ENUMs: +// EN Enable IFAMP +// DIS Disable IFAMP +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_W 8U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_M 0x0000FF00U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_S 8U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_EN 0x00000100U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_DIS 0x00000000U + +// Field: [7:4] LNA_TRIM +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_W 4U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_M 0x000000F0U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_S 4U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_ONES 0x000000F0U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_ZEROS 0x00000000U + +// Field: [3] LNA_BIAS +// +// ENUMs: +// INT IPTAT bias currents are from bias circuit inside +// LRF_FRONTEND +// BGAP IPTAT bias currents are from bandgap +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS 0x00000008U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_M 0x00000008U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_S 3U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_INT 0x00000008U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_BGAP 0x00000000U + +// Field: [2:1] LNA_IB +// +// ENUMs: +// MAX Maximum IB +// MIN Minimum IB +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_W 2U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_M 0x00000006U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_S 1U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_MAX 0x00000006U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_MIN 0x00000000U + +// Field: [0] LNA_EN +// +// ENUMs: +// ON Enable LNA +// OFF Disable LNA +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN 0x00000001U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_M 0x00000001U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_S 0U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_ON 0x00000001U +#define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PA1_PA0 +// +//***************************************************************************** +// Field: [31:23] SPARE +// +// ENUMs: +// MAX Longest ramp time +// MIN Shortest ramp time +#define LRFDRFE32_PA1_PA0_SPARE_W 9U +#define LRFDRFE32_PA1_PA0_SPARE_M 0xFF800000U +#define LRFDRFE32_PA1_PA0_SPARE_S 23U +#define LRFDRFE32_PA1_PA0_SPARE_MAX 0x01800000U +#define LRFDRFE32_PA1_PA0_SPARE_MIN 0x00000000U + +// Field: [22] MIXATST +// +// ENUMs: +// EN Mixers are available on ATEST +// DIS Mixers are not available on ATEST +#define LRFDRFE32_PA1_PA0_MIXATST 0x00400000U +#define LRFDRFE32_PA1_PA0_MIXATST_M 0x00400000U +#define LRFDRFE32_PA1_PA0_MIXATST_S 22U +#define LRFDRFE32_PA1_PA0_MIXATST_EN 0x00400000U +#define LRFDRFE32_PA1_PA0_MIXATST_DIS 0x00000000U + +// Field: [21] LDOITST +// +// ENUMs: +// EN Current test signal is available through ITEST +// DIS Current test signal not available through ITEST +#define LRFDRFE32_PA1_PA0_LDOITST 0x00200000U +#define LRFDRFE32_PA1_PA0_LDOITST_M 0x00200000U +#define LRFDRFE32_PA1_PA0_LDOITST_S 21U +#define LRFDRFE32_PA1_PA0_LDOITST_EN 0x00200000U +#define LRFDRFE32_PA1_PA0_LDOITST_DIS 0x00000000U + +// Field: [20] LDOATST +// +// ENUMs: +// EN LDO output voltage is available through ATEST +// DIS LDO output voltage not available through ATEST +#define LRFDRFE32_PA1_PA0_LDOATST 0x00100000U +#define LRFDRFE32_PA1_PA0_LDOATST_M 0x00100000U +#define LRFDRFE32_PA1_PA0_LDOATST_S 20U +#define LRFDRFE32_PA1_PA0_LDOATST_EN 0x00100000U +#define LRFDRFE32_PA1_PA0_LDOATST_DIS 0x00000000U + +// Field: [19:18] RC +// +// ENUMs: +// MAX Longest ramp time +// MIN Shortest ramp time +#define LRFDRFE32_PA1_PA0_RC_W 2U +#define LRFDRFE32_PA1_PA0_RC_M 0x000C0000U +#define LRFDRFE32_PA1_PA0_RC_S 18U +#define LRFDRFE32_PA1_PA0_RC_MAX 0x000C0000U +#define LRFDRFE32_PA1_PA0_RC_MIN 0x00000000U + +// Field: [17] RAMP +// +// ENUMs: +// UP Ramp up +// DOWN Ramp down +#define LRFDRFE32_PA1_PA0_RAMP 0x00020000U +#define LRFDRFE32_PA1_PA0_RAMP_M 0x00020000U +#define LRFDRFE32_PA1_PA0_RAMP_S 17U +#define LRFDRFE32_PA1_PA0_RAMP_UP 0x00020000U +#define LRFDRFE32_PA1_PA0_RAMP_DOWN 0x00000000U + +// Field: [16] EN +// +// ENUMs: +// EN Enable PA +// DIS Disable PA +#define LRFDRFE32_PA1_PA0_EN 0x00010000U +#define LRFDRFE32_PA1_PA0_EN_M 0x00010000U +#define LRFDRFE32_PA1_PA0_EN_S 16U +#define LRFDRFE32_PA1_PA0_EN_EN 0x00010000U +#define LRFDRFE32_PA1_PA0_EN_DIS 0x00000000U + +// Field: [15] SPARE15 +// +// ENUMs: +// ONE Bit is one +// ZERO Bit is 0 +#define LRFDRFE32_PA1_PA0_SPARE15 0x00008000U +#define LRFDRFE32_PA1_PA0_SPARE15_M 0x00008000U +#define LRFDRFE32_PA1_PA0_SPARE15_S 15U +#define LRFDRFE32_PA1_PA0_SPARE15_ONE 0x00008000U +#define LRFDRFE32_PA1_PA0_SPARE15_ZERO 0x00000000U + +// Field: [14] MODE +// +// ENUMs: +// HIGH High power mode, max 8 dBm +// LOW Low power mode, max 3 dBm +#define LRFDRFE32_PA1_PA0_MODE 0x00004000U +#define LRFDRFE32_PA1_PA0_MODE_M 0x00004000U +#define LRFDRFE32_PA1_PA0_MODE_S 14U +#define LRFDRFE32_PA1_PA0_MODE_HIGH 0x00004000U +#define LRFDRFE32_PA1_PA0_MODE_LOW 0x00000000U + +// Field: [13:11] GAIN +// +// ENUMs: +// MAX Maximum gain +// MIN Minimum gain +#define LRFDRFE32_PA1_PA0_GAIN_W 3U +#define LRFDRFE32_PA1_PA0_GAIN_M 0x00003800U +#define LRFDRFE32_PA1_PA0_GAIN_S 11U +#define LRFDRFE32_PA1_PA0_GAIN_MAX 0x00003800U +#define LRFDRFE32_PA1_PA0_GAIN_MIN 0x00000000U + +// Field: [10:5] IB +// +// ENUMs: +// MAX Maximum output power +// MIN Minimum output power +#define LRFDRFE32_PA1_PA0_IB_W 6U +#define LRFDRFE32_PA1_PA0_IB_M 0x000007E0U +#define LRFDRFE32_PA1_PA0_IB_S 5U +#define LRFDRFE32_PA1_PA0_IB_MAX 0x000007E0U +#define LRFDRFE32_PA1_PA0_IB_MIN 0x00000000U + +// Field: [4:0] TRIM +// +// ENUMs: +// MAX Maximum bias current +// MIN Minimum bias current +#define LRFDRFE32_PA1_PA0_TRIM_W 5U +#define LRFDRFE32_PA1_PA0_TRIM_M 0x0000001FU +#define LRFDRFE32_PA1_PA0_TRIM_S 0U +#define LRFDRFE32_PA1_PA0_TRIM_MAX 0x0000001FU +#define LRFDRFE32_PA1_PA0_TRIM_MIN 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_IFADC0_ULNA +// +//***************************************************************************** +// Field: [31] EXTCLK +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_IFADC0_ULNA_EXTCLK 0x80000000U +#define LRFDRFE32_IFADC0_ULNA_EXTCLK_M 0x80000000U +#define LRFDRFE32_IFADC0_ULNA_EXTCLK_S 31U +#define LRFDRFE32_IFADC0_ULNA_EXTCLK_EN 0x80000000U +#define LRFDRFE32_IFADC0_ULNA_EXTCLK_DIS 0x00000000U + +// Field: [30:28] DITHERTRIM +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_W 3U +#define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_M 0x70000000U +#define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_S 28U +#define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_ONES 0x70000000U +#define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_ZEROS 0x00000000U + +// Field: [27:26] DITHEREN +// +// ENUMs: +// ENG All the bits are 1 +// ENSD All the bits are 1 +// ENS All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_W 2U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_M 0x0C000000U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_S 26U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENG 0x0C000000U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENSD 0x08000000U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENS 0x04000000U +#define LRFDRFE32_IFADC0_ULNA_DITHEREN_DIS 0x00000000U + +// Field: [25] ADCIEN +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_IFADC0_ULNA_ADCIEN 0x02000000U +#define LRFDRFE32_IFADC0_ULNA_ADCIEN_M 0x02000000U +#define LRFDRFE32_IFADC0_ULNA_ADCIEN_S 25U +#define LRFDRFE32_IFADC0_ULNA_ADCIEN_EN 0x02000000U +#define LRFDRFE32_IFADC0_ULNA_ADCIEN_DIS 0x00000000U + +// Field: [24] ADCQEN +// +// ENUMs: +// EN The bit is 1 +// DIS The bit is 0 +#define LRFDRFE32_IFADC0_ULNA_ADCQEN 0x01000000U +#define LRFDRFE32_IFADC0_ULNA_ADCQEN_M 0x01000000U +#define LRFDRFE32_IFADC0_ULNA_ADCQEN_S 24U +#define LRFDRFE32_IFADC0_ULNA_ADCQEN_EN 0x01000000U +#define LRFDRFE32_IFADC0_ULNA_ADCQEN_DIS 0x00000000U + +// Field: [23:20] INT2ADJ +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADC0_ULNA_INT2ADJ_W 4U +#define LRFDRFE32_IFADC0_ULNA_INT2ADJ_M 0x00F00000U +#define LRFDRFE32_IFADC0_ULNA_INT2ADJ_S 20U +#define LRFDRFE32_IFADC0_ULNA_INT2ADJ_ONES 0x00F00000U +#define LRFDRFE32_IFADC0_ULNA_INT2ADJ_ZEROS 0x00000000U + +// Field: [19:18] AAFCAP +// +// ENUMs: +// ENG All the bits are 1 +// ENSD All the bits are 1 +// ENS All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_W 2U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_M 0x000C0000U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_S 18U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENG 0x000C0000U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENSD 0x00080000U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENS 0x00040000U +#define LRFDRFE32_IFADC0_ULNA_AAFCAP_DIS 0x00000000U + +// Field: [15:0] SPARE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_IFADC0_ULNA_SPARE_W 16U +#define LRFDRFE32_IFADC0_ULNA_SPARE_M 0x0000FFFFU +#define LRFDRFE32_IFADC0_ULNA_SPARE_S 0U +#define LRFDRFE32_IFADC0_ULNA_SPARE_ALLONES 0x0000FFFFU +#define LRFDRFE32_IFADC0_ULNA_SPARE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_IFADCLF_IFADC1 +// +//***************************************************************************** +// Field: [31:28] FF3 +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_FF3_W 4U +#define LRFDRFE32_IFADCLF_IFADC1_FF3_M 0xF0000000U +#define LRFDRFE32_IFADCLF_IFADC1_FF3_S 28U +#define LRFDRFE32_IFADCLF_IFADC1_FF3_ONES 0xF0000000U +#define LRFDRFE32_IFADCLF_IFADC1_FF3_ZEROS 0x00000000U + +// Field: [27:24] FF2 +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_FF2_W 4U +#define LRFDRFE32_IFADCLF_IFADC1_FF2_M 0x0F000000U +#define LRFDRFE32_IFADCLF_IFADC1_FF2_S 24U +#define LRFDRFE32_IFADCLF_IFADC1_FF2_ONES 0x0F000000U +#define LRFDRFE32_IFADCLF_IFADC1_FF2_ZEROS 0x00000000U + +// Field: [23:20] FF1 +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_FF1_W 4U +#define LRFDRFE32_IFADCLF_IFADC1_FF1_M 0x00F00000U +#define LRFDRFE32_IFADCLF_IFADC1_FF1_S 20U +#define LRFDRFE32_IFADCLF_IFADC1_FF1_ONES 0x00F00000U +#define LRFDRFE32_IFADCLF_IFADC1_FF1_ZEROS 0x00000000U + +// Field: [19:16] INT3 +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_INT3_W 4U +#define LRFDRFE32_IFADCLF_IFADC1_INT3_M 0x000F0000U +#define LRFDRFE32_IFADCLF_IFADC1_INT3_S 16U +#define LRFDRFE32_IFADCLF_IFADC1_INT3_ONES 0x000F0000U +#define LRFDRFE32_IFADCLF_IFADC1_INT3_ZEROS 0x00000000U + +// Field: [15] NRZ +// +// ENUMs: +// EN The feedback DAC uses NRZ mode. (Default) +// DIS The feedback DAC uses RZ mode +#define LRFDRFE32_IFADCLF_IFADC1_NRZ 0x00008000U +#define LRFDRFE32_IFADCLF_IFADC1_NRZ_M 0x00008000U +#define LRFDRFE32_IFADCLF_IFADC1_NRZ_S 15U +#define LRFDRFE32_IFADCLF_IFADC1_NRZ_EN 0x00008000U +#define LRFDRFE32_IFADCLF_IFADC1_NRZ_DIS 0x00000000U + +// Field: [14:9] TRIM +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_TRIM_W 6U +#define LRFDRFE32_IFADCLF_IFADC1_TRIM_M 0x00007E00U +#define LRFDRFE32_IFADCLF_IFADC1_TRIM_S 9U +#define LRFDRFE32_IFADCLF_IFADC1_TRIM_ONES 0x00007E00U +#define LRFDRFE32_IFADCLF_IFADC1_TRIM_ZEROS 0x00000000U + +// Field: [7] RSTN +// +// ENUMs: +// DIS DTCs are not reset +// EN DTCs are reset +#define LRFDRFE32_IFADCLF_IFADC1_RSTN 0x00000080U +#define LRFDRFE32_IFADCLF_IFADC1_RSTN_M 0x00000080U +#define LRFDRFE32_IFADCLF_IFADC1_RSTN_S 7U +#define LRFDRFE32_IFADCLF_IFADC1_RSTN_DIS 0x00000080U +#define LRFDRFE32_IFADCLF_IFADC1_RSTN_EN 0x00000000U + +// Field: [6] CLKGEN +// +// ENUMs: +// EN Internal clock generator module is enabled +// DIS Internal clock generator module is disabled +#define LRFDRFE32_IFADCLF_IFADC1_CLKGEN 0x00000040U +#define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_M 0x00000040U +#define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_S 6U +#define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_EN 0x00000040U +#define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_DIS 0x00000000U + +// Field: [5] ADCDIGCLK +// +// ENUMs: +// EN Clock to decimator enabled +// DIS Clock to decimator disabled +#define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK 0x00000020U +#define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_M 0x00000020U +#define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_S 5U +#define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_EN 0x00000020U +#define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_DIS 0x00000000U + +// Field: [4] ADCLFSROUT +// +// ENUMs: +// EN The LFSR test output is connected to the ADC +// output +// DIS The quantizer output is connected to the ADC +// output +#define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT 0x00000010U +#define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_M 0x00000010U +#define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_S 4U +#define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_EN 0x00000010U +#define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_DIS 0x00000000U + +// Field: [3:1] LPFTSTMODE +// +// ENUMs: +// EN All the bits are 1 +// DIS All the bits are 0 +#define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_W 3U +#define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_M 0x0000000EU +#define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_S 1U +#define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_EN 0x00000002U +#define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_DIS 0x00000000U + +// Field: [0] INVCLKOUT +// +// ENUMs: +// EN Invert IFADC output clock phase (default) +// DIS Keep default IFADC output clock phase +#define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT 0x00000001U +#define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_M 0x00000001U +#define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_S 0U +#define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_EN 0x00000001U +#define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_IFADCALDO_IFADCQUANT +// +//***************************************************************************** +// Field: [31] ATESTVSSANA +// +// ENUMs: +// EN Connected +// DIS Not connected +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA 0x80000000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_M 0x80000000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_S 31U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_EN 0x80000000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_DIS 0x00000000U + +// Field: [29:24] TRIMOUT +// +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_W 6U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_M 0x3F000000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_S 24U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_ONES 0x3F000000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_ZEROS 0x00000000U + +// Field: [23] DUMMY +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY 0x00800000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_M 0x00800000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_S 23U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_EN 0x00800000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_DIS 0x00000000U + +// Field: [22] ATESTOUT +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT 0x00400000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_M 0x00400000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_S 22U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_EN 0x00400000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_DIS 0x00000000U + +// Field: [21] ATSTLDOFB +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB 0x00200000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_M 0x00200000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_S 21U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_EN 0x00200000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_DIS 0x00000000U + +// Field: [20] ATESTERRAMP +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP 0x00100000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_M 0x00100000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_S 20U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_EN 0x00100000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_DIS 0x00000000U + +// Field: [19] ITEST +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST 0x00080000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_M 0x00080000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_S 19U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_EN 0x00080000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_DIS 0x00000000U + +// Field: [18] BYPASS +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS 0x00040000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_M 0x00040000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_S 18U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_EN 0x00040000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_DIS 0x00000000U + +// Field: [17] CLAMP +// +// ENUMs: +// EN Enabled +// DIS Disabled. The LDO output is shorted to ground when +// disabled. +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP 0x00020000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_M 0x00020000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_S 17U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_EN 0x00020000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_DIS 0x00000000U + +// Field: [16] CTL +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL 0x00010000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_M 0x00010000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_S 16U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_EN 0x00010000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_DIS 0x00000000U + +// Field: [15:14] CLKDLYTRIM +// +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_W 2U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_M 0x0000C000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_S 14U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_ONES 0x0000C000U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_ZEROS 0x00000000U + +// Field: [13:9] DBGCALVALIN +// +// ENUMs: +// ONES All the bits are ONES +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_W 5U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_M 0x00003E00U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_S 9U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_ONES 0x00003E00U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_ZEROS 0x00000000U + +// Field: [8] DBGCALLEG +// +// ENUMs: +// NEG Negative leg +// POS Positive leg +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG 0x00000100U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_M 0x00000100U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_S 8U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_NEG 0x00000100U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_POS 0x00000000U + +// Field: [7:6] DBGCALMQ +// +// ENUMs: +// DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode. +// DBGCAL_QMODP Enable quantizer calibration mode for Positive +// comparator in Q modulator. +// DBGCAL_QMODN Enable quantizer calibration mode for Negative +// comparator in Q modulator. +// DBGCAL_QMODZ Disable quantizer calibration mode.(Default) +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_W 2U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_M 0x000000C0U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_S 6U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODB 0x000000C0U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODP 0x00000080U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODN 0x00000040U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODZ 0x00000000U + +// Field: [5:4] DBGCALMI +// +// ENUMs: +// DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode. +// DBGCAL_IMODP Enable quantizer calibration mode for Positive +// comparator in I modulator. +// DBGCAL_IMODN Enable quantizer calibration mode for Negative +// comparator in I modulator. +// DBGCAL_IMODZ Disable quantizer calibration mode.(Default) +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_W 2U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_M 0x00000030U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_S 4U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODB 0x00000030U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODP 0x00000020U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODN 0x00000010U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODZ 0x00000000U + +// Field: [3] AUTOCAL +// +// ENUMs: +// EN Enable the auto calibration logic (Default) +// DIS Disable the auto calibration logic +#define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL 0x00000008U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_M 0x00000008U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_S 3U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_EN 0x00000008U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_DIS 0x00000000U + +// Field: [2:0] QUANTTHR +// +// ENUMs: +// ONES All the bits are 1 +// ZEROS All the bits are 0 +#define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_W 3U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_M 0x00000007U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_S 0U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_ONES 0x00000007U +#define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_ZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_IFADCTST_IFADCDLDO +// +//***************************************************************************** +// Field: [23] EXTCURR +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR 0x00800000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_M 0x00800000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_S 23U +#define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_EN 0x00800000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_DIS 0x00000000U + +// Field: [22] QCALDBIQ +// +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ 0x00400000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_M 0x00400000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_S 22U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_COMP1 0x00400000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_COMP0 0x00000000U + +// Field: [21] QCALDBC +// +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC 0x00200000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_M 0x00200000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_S 21U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_COMP1 0x00200000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_COMP0 0x00000000U + +// Field: [20:16] SEL +// +// ENUMs: +// EXTCLKN1 External ADC clock through ADC_TEST_N (N1 +// internally). The the clock should be a 200MHz +// sine wave (it is divided internally to 100MHz). +// NONE ADC_TEST_P and ADC_TEST_N tristated (Default) +#define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_W 5U +#define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_M 0x001F0000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_S 16U +#define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_EXTCLKN1 0x001F0000U +#define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_NONE 0x00000000U + +// Field: [13:8] TRIMOUT +// +// ENUMs: +// ONES All the bits are one +// ZEROS All the bits are zero +#define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_W 6U +#define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_M 0x00003F00U +#define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_S 8U +#define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_ONES 0x00003F00U +#define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_ZEROS 0x00000000U + +// Field: [7] DUMMY +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY 0x00000080U +#define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_M 0x00000080U +#define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_S 7U +#define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_EN 0x00000080U +#define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_DIS 0x00000000U + +// Field: [6] ATESTOUT +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT 0x00000040U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_M 0x00000040U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_S 6U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_EN 0x00000040U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_DIS 0x00000000U + +// Field: [5] ATSTBGP +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP 0x00000020U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_M 0x00000020U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_S 5U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_EN 0x00000020U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_DIS 0x00000000U + +// Field: [4] ATESTERRAMP +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP 0x00000010U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_M 0x00000010U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_S 4U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_EN 0x00000010U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_DIS 0x00000000U + +// Field: [3] ITEST +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST 0x00000008U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_M 0x00000008U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_S 3U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_EN 0x00000008U +#define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_DIS 0x00000000U + +// Field: [2] BYPASS +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS 0x00000004U +#define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_M 0x00000004U +#define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_S 2U +#define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_EN 0x00000004U +#define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_DIS 0x00000000U + +// Field: [1] CLAMP +// +// ENUMs: +// EN Enabled +// DIS Disabled. The LDO output is shorted to ground when +// disabled. +#define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP 0x00000002U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_M 0x00000002U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_S 1U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_EN 0x00000002U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_DIS 0x00000000U + +// Field: [0] CTL +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_IFADCTST_IFADCDLDO_CTL 0x00000001U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_M 0x00000001U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_S 0U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_EN 0x00000001U +#define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_ATSTREF +// +//***************************************************************************** +// Field: [31] VREFBPDIS +// +// ENUMs: +// BPDIS Bandgap reference bypass disabled +// BPEN Bandgap reference bypass enabled. +#define LRFDRFE32_ATSTREF_VREFBPDIS 0x80000000U +#define LRFDRFE32_ATSTREF_VREFBPDIS_M 0x80000000U +#define LRFDRFE32_ATSTREF_VREFBPDIS_S 31U +#define LRFDRFE32_ATSTREF_VREFBPDIS_BPDIS 0x80000000U +#define LRFDRFE32_ATSTREF_VREFBPDIS_BPEN 0x00000000U + +// Field: [30:26] IREFTRIM +// +// ENUMs: +// ONES All bits are ones +// ZEROS All bits are zero +#define LRFDRFE32_ATSTREF_IREFTRIM_W 5U +#define LRFDRFE32_ATSTREF_IREFTRIM_M 0x7C000000U +#define LRFDRFE32_ATSTREF_IREFTRIM_S 26U +#define LRFDRFE32_ATSTREF_IREFTRIM_ONES 0x7C000000U +#define LRFDRFE32_ATSTREF_IREFTRIM_ZEROS 0x00000000U + +// Field: [25] BIAS +// +// ENUMs: +// EN Enabled +// DIS Disabled +#define LRFDRFE32_ATSTREF_BIAS 0x02000000U +#define LRFDRFE32_ATSTREF_BIAS_M 0x02000000U +#define LRFDRFE32_ATSTREF_BIAS_S 25U +#define LRFDRFE32_ATSTREF_BIAS_EN 0x02000000U +#define LRFDRFE32_ATSTREF_BIAS_DIS 0x00000000U + +// Field: [24] OUTPUT2 +// +// ENUMs: +// EN The output is enabled +// DIS Output is disabled +#define LRFDRFE32_ATSTREF_OUTPUT2 0x01000000U +#define LRFDRFE32_ATSTREF_OUTPUT2_M 0x01000000U +#define LRFDRFE32_ATSTREF_OUTPUT2_S 24U +#define LRFDRFE32_ATSTREF_OUTPUT2_EN 0x01000000U +#define LRFDRFE32_ATSTREF_OUTPUT2_DIS 0x00000000U + +// Field: [23] OUTPUT1 +// +// ENUMs: +// EN The output is enabled +// DIS Output is disabled +#define LRFDRFE32_ATSTREF_OUTPUT1 0x00800000U +#define LRFDRFE32_ATSTREF_OUTPUT1_M 0x00800000U +#define LRFDRFE32_ATSTREF_OUTPUT1_S 23U +#define LRFDRFE32_ATSTREF_OUTPUT1_EN 0x00800000U +#define LRFDRFE32_ATSTREF_OUTPUT1_DIS 0x00000000U + +// Field: [22:0] MUX +// +// ENUMs: +// IFADC_ATB IFADC ATB +// LDO_VTEST LDO_VTEST vtest out, current +// LDO_ITEST LDO_ITEST itest out, current +// PA_PEAK_OUTN PA peak detector output n +// PA_PEAK_OUTP PA peak detector output p +// MIX_OUTQN MIX outqn, voltage +// MIX_OUTQP MIX outqp, voltage +// MIX_OUTIN MIX outin, voltage +// MIX_OUTIP MIX outip, voltage +// FE_OUTIN_2 Frontend IF outin, voltage +// FE_OUTIP_2 Frontend IF outip, voltage +// FE_OUTQN Frontend IF outqn, voltage +// FE_OUTQP Frontend IF outqp, voltage +// FE_OUTIN Frontend IF outin, voltage +// FE_OUTIP Frontend IF outip, voltage +// DIS No atest selected +#define LRFDRFE32_ATSTREF_MUX_W 23U +#define LRFDRFE32_ATSTREF_MUX_M 0x007FFFFFU +#define LRFDRFE32_ATSTREF_MUX_S 0U +#define LRFDRFE32_ATSTREF_MUX_IFADC_ATB 0x00008000U +#define LRFDRFE32_ATSTREF_MUX_LDO_VTEST 0x00004000U +#define LRFDRFE32_ATSTREF_MUX_LDO_ITEST 0x00002000U +#define LRFDRFE32_ATSTREF_MUX_PA_PEAK_OUTN 0x00000800U +#define LRFDRFE32_ATSTREF_MUX_PA_PEAK_OUTP 0x00000400U +#define LRFDRFE32_ATSTREF_MUX_MIX_OUTQN 0x00000200U +#define LRFDRFE32_ATSTREF_MUX_MIX_OUTQP 0x00000100U +#define LRFDRFE32_ATSTREF_MUX_MIX_OUTIN 0x00000080U +#define LRFDRFE32_ATSTREF_MUX_MIX_OUTIP 0x00000040U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTIN_2 0x00000020U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTIP_2 0x00000010U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTQN 0x00000008U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTQP 0x00000004U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTIN 0x00000002U +#define LRFDRFE32_ATSTREF_MUX_FE_OUTIP 0x00000001U +#define LRFDRFE32_ATSTREF_MUX_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DIV_DCO +// +//***************************************************************************** +// Field: [31] PDET +// +// ENUMs: +// EN Peak detektor mode enabled, used in production +// test +// DIS Peak detector mode disabled, normal functional +// mode +#define LRFDRFE32_DIV_DCO_PDET 0x80000000U +#define LRFDRFE32_DIV_DCO_PDET_M 0x80000000U +#define LRFDRFE32_DIV_DCO_PDET_S 31U +#define LRFDRFE32_DIV_DCO_PDET_EN 0x80000000U +#define LRFDRFE32_DIV_DCO_PDET_DIS 0x00000000U + +// Field: [30:28] NMIREFTRIM +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DIV_DCO_NMIREFTRIM_W 3U +#define LRFDRFE32_DIV_DCO_NMIREFTRIM_M 0x70000000U +#define LRFDRFE32_DIV_DCO_NMIREFTRIM_S 28U +#define LRFDRFE32_DIV_DCO_NMIREFTRIM_ALLONES 0x70000000U +#define LRFDRFE32_DIV_DCO_NMIREFTRIM_ALLZEROS 0x00000000U + +// Field: [27:25] PMIREFTRIM +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DIV_DCO_PMIREFTRIM_W 3U +#define LRFDRFE32_DIV_DCO_PMIREFTRIM_M 0x0E000000U +#define LRFDRFE32_DIV_DCO_PMIREFTRIM_S 25U +#define LRFDRFE32_DIV_DCO_PMIREFTRIM_ALLONES 0x0E000000U +#define LRFDRFE32_DIV_DCO_PMIREFTRIM_ALLZEROS 0x00000000U + +// Field: [24] TXBBOOST +// +// ENUMs: +// INCREASED High drive strength +// DEFAULT Default drive strength +#define LRFDRFE32_DIV_DCO_TXBBOOST 0x01000000U +#define LRFDRFE32_DIV_DCO_TXBBOOST_M 0x01000000U +#define LRFDRFE32_DIV_DCO_TXBBOOST_S 24U +#define LRFDRFE32_DIV_DCO_TXBBOOST_INCREASED 0x01000000U +#define LRFDRFE32_DIV_DCO_TXBBOOST_DEFAULT 0x00000000U + +// Field: [23] S1GFRC +// +// ENUMs: +// EN Enable force S1G power switch +// DIS Disable force S1G power switch +#define LRFDRFE32_DIV_DCO_S1GFRC 0x00800000U +#define LRFDRFE32_DIV_DCO_S1GFRC_M 0x00800000U +#define LRFDRFE32_DIV_DCO_S1GFRC_S 23U +#define LRFDRFE32_DIV_DCO_S1GFRC_EN 0x00800000U +#define LRFDRFE32_DIV_DCO_S1GFRC_DIS 0x00000000U + +// Field: [22:21] BUFGAIN +// +// ENUMs: +// _60_PST 60% of maximum gain +// DONT_USE Same as _80_PST +// _80_PST 80% of maximum gain +// MAX Maximum gain (default) +#define LRFDRFE32_DIV_DCO_BUFGAIN_W 2U +#define LRFDRFE32_DIV_DCO_BUFGAIN_M 0x00600000U +#define LRFDRFE32_DIV_DCO_BUFGAIN_S 21U +#define LRFDRFE32_DIV_DCO_BUFGAIN__60_PST 0x00600000U +#define LRFDRFE32_DIV_DCO_BUFGAIN_DONT_USE 0x00400000U +#define LRFDRFE32_DIV_DCO_BUFGAIN__80_PST 0x00200000U +#define LRFDRFE32_DIV_DCO_BUFGAIN_MAX 0x00000000U + +// Field: [20] BIAS +// +// ENUMs: +// DEFAULT Default bias +// ALTERNATIVE Alternative bias (for test purposes) +#define LRFDRFE32_DIV_DCO_BIAS 0x00100000U +#define LRFDRFE32_DIV_DCO_BIAS_M 0x00100000U +#define LRFDRFE32_DIV_DCO_BIAS_S 20U +#define LRFDRFE32_DIV_DCO_BIAS_DEFAULT 0x00100000U +#define LRFDRFE32_DIV_DCO_BIAS_ALTERNATIVE 0x00000000U + +// Field: [19] OUT +// +// ENUMs: +// FE_2G4 Enable outputs going to 2.4GHz front-end +// FE_S1G Enable outputs going to sub-1GHz front-end +#define LRFDRFE32_DIV_DCO_OUT 0x00080000U +#define LRFDRFE32_DIV_DCO_OUT_M 0x00080000U +#define LRFDRFE32_DIV_DCO_OUT_S 19U +#define LRFDRFE32_DIV_DCO_OUT_FE_2G4 0x00080000U +#define LRFDRFE32_DIV_DCO_OUT_FE_S1G 0x00000000U + +// Field: [18:16] RATIO +// +// ENUMs: +// DIV30 DIVIDER = 30 +// DIV15 DIVIDER = 15 +// DIV10 DIVIDER = 10 +// DIV5 DIVIDER = 5 +// DIV12 DIVIDER = 12 +// DIV6 DIVIDER = 6 +// DIV4 DIVIDER = 4 (for test purposes only) +// DIV2 DIVIDER = 2 +#define LRFDRFE32_DIV_DCO_RATIO_W 3U +#define LRFDRFE32_DIV_DCO_RATIO_M 0x00070000U +#define LRFDRFE32_DIV_DCO_RATIO_S 16U +#define LRFDRFE32_DIV_DCO_RATIO_DIV30 0x00070000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV15 0x00060000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV10 0x00050000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV5 0x00040000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV12 0x00030000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV6 0x00020000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV4 0x00010000U +#define LRFDRFE32_DIV_DCO_RATIO_DIV2 0x00000000U + +// Field: [10:9] MTDCSPARE +// +// ENUMs: +// DIS DIVIDER = 4 (for test purposes only) +// EN DIVIDER = 2 +#define LRFDRFE32_DIV_DCO_MTDCSPARE_W 2U +#define LRFDRFE32_DIV_DCO_MTDCSPARE_M 0x00000600U +#define LRFDRFE32_DIV_DCO_MTDCSPARE_S 9U +#define LRFDRFE32_DIV_DCO_MTDCSPARE_DIS 0x00000200U +#define LRFDRFE32_DIV_DCO_MTDCSPARE_EN 0x00000000U + +// Field: [8:7] SPARE7 +// +// ENUMs: +// ONE Bit is one +// ZERO Bit is zero +#define LRFDRFE32_DIV_DCO_SPARE7_W 2U +#define LRFDRFE32_DIV_DCO_SPARE7_M 0x00000180U +#define LRFDRFE32_DIV_DCO_SPARE7_S 7U +#define LRFDRFE32_DIV_DCO_SPARE7_ONE 0x00000080U +#define LRFDRFE32_DIV_DCO_SPARE7_ZERO 0x00000000U + +// Field: [6:3] TAILRESTRIM +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DIV_DCO_TAILRESTRIM_W 4U +#define LRFDRFE32_DIV_DCO_TAILRESTRIM_M 0x00000078U +#define LRFDRFE32_DIV_DCO_TAILRESTRIM_S 3U +#define LRFDRFE32_DIV_DCO_TAILRESTRIM_ALLONES 0x00000078U +#define LRFDRFE32_DIV_DCO_TAILRESTRIM_ALLZEROS 0x00000000U + +// Field: [2] RTRIMCAP +// +// ENUMs: +// EN Enable +// DIS Disable(default) +#define LRFDRFE32_DIV_DCO_RTRIMCAP 0x00000004U +#define LRFDRFE32_DIV_DCO_RTRIMCAP_M 0x00000004U +#define LRFDRFE32_DIV_DCO_RTRIMCAP_S 2U +#define LRFDRFE32_DIV_DCO_RTRIMCAP_EN 0x00000004U +#define LRFDRFE32_DIV_DCO_RTRIMCAP_DIS 0x00000000U + +// Field: [1] CNRCAP +// +// ENUMs: +// _50MHZ 50 MHz +// DEFAULT Default +#define LRFDRFE32_DIV_DCO_CNRCAP 0x00000002U +#define LRFDRFE32_DIV_DCO_CNRCAP_M 0x00000002U +#define LRFDRFE32_DIV_DCO_CNRCAP_S 1U +#define LRFDRFE32_DIV_DCO_CNRCAP__50MHZ 0x00000002U +#define LRFDRFE32_DIV_DCO_CNRCAP_DEFAULT 0x00000000U + +// Field: [0] CRSCAPCM +// +// ENUMs: +// REDUCED Reduced common mode for greater reliability +// DEFAULT Default +#define LRFDRFE32_DIV_DCO_CRSCAPCM 0x00000001U +#define LRFDRFE32_DIV_DCO_CRSCAPCM_M 0x00000001U +#define LRFDRFE32_DIV_DCO_CRSCAPCM_S 0U +#define LRFDRFE32_DIV_DCO_CRSCAPCM_REDUCED 0x00000001U +#define LRFDRFE32_DIV_DCO_CRSCAPCM_DEFAULT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TDCLDO_DIVLDO +// +//***************************************************************************** +// Field: [31] TDCLDO_ITESTCTL +// +// ENUMs: +// EN ITEST enabled +// DIS ITEST Disabled +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL 0x80000000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_M 0x80000000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_S 31U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_EN 0x80000000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_DIS 0x00000000U + +// Field: [30:24] TDCLDO_VOUTTRIM +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_W 7U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_M 0x7F000000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_S 24U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_ONES 0x7F000000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_ZEROS 0x00000000U + +// Field: [23] TDCLDO_ITESTBUFCTL +// +// ENUMs: +// EN ITEST mode in buffer is enabled +// DIS ITEST mode in buffer is disabled +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL 0x00800000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_M 0x00800000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_S 23U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_EN 0x00800000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_DIS 0x00000000U + +// Field: [22:20] TDCLDO_TMUX +// +// ENUMs: +// VSSA ATEST output is VSSA +// LDO_OUT ATEST output is LDO output +// VDDA ATEST output is VDDA +// OFF Normal mode +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_W 3U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_M 0x00700000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_S 20U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_VSSA 0x00400000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_LDO_OUT 0x00200000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_VDDA 0x00100000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_OFF 0x00000000U + +// Field: [19] TDCLDO_PDSEL +// +// ENUMs: +// DIODE Diode stack +// R R (default) +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL 0x00080000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_M 0x00080000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_S 19U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_DIODE 0x00080000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_R 0x00000000U + +// Field: [18] TDCLDO_MODE +// +// ENUMs: +// FAST Regulator in high bandwidth mode +// NORM Regular low bandwidth of LDO +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE 0x00040000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_M 0x00040000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_S 18U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_FAST 0x00040000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_NORM 0x00000000U + +// Field: [17] TDCLDO_BYPASS +// +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS 0x00020000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_M 0x00020000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_S 17U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_EN 0x00020000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_DIS 0x00000000U + +// Field: [16] TDCLDO_CTL +// +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL 0x00010000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_M 0x00010000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_S 16U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_EN 0x00010000U +#define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_DIS 0x00000000U + +// Field: [15] DIVLDO_SPARE15 +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15 0x00008000U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_M 0x00008000U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_S 15U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_ONES 0x00008000U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_ZEROS 0x00000000U + +// Field: [14:8] DIVLDO_VOUTTRIM +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_W 7U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_M 0x00007F00U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_S 8U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_ONES 0x00007F00U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_ZEROS 0x00000000U + +// Field: [7] DIVLDO_ITST +// +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST 0x00000080U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_M 0x00000080U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_S 7U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_EN 0x00000080U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_DIS 0x00000000U + +// Field: [6:4] DIVLDO_TMUX +// +// ENUMs: +// VDDR ATEST output is VDDR +// LDO_OUT ATEST output is LDO output +// GND ATEST output is grounded +// OFF Normal mode +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_W 3U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_M 0x00000070U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_S 4U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_VDDR 0x00000040U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_LDO_OUT 0x00000020U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_GND 0x00000010U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_OFF 0x00000000U + +// Field: [3] DIVLDO_SPARE3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3 0x00000008U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_M 0x00000008U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_S 3U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_ONE 0x00000008U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_ZERO 0x00000000U + +// Field: [2] DIVLDO_MODE +// +// ENUMs: +// FAST Regulator in high bandwidth mode +// NORM Regular low bandwidth of LDO +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE 0x00000004U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_M 0x00000004U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_S 2U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_FAST 0x00000004U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_NORM 0x00000000U + +// Field: [1] DIVLDO_BYPASS +// +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS 0x00000002U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_M 0x00000002U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_S 1U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_EN 0x00000002U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_DIS 0x00000000U + +// Field: [0] DIVLDO_CTL +// +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL 0x00000001U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_M 0x00000001U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_S 0U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_EN 0x00000001U +#define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DCOLDO1_DCOLDO0 +// +//***************************************************************************** +// Field: [26] REFSRC +// +// ENUMs: +// BAW PLL clock source is BAW +// XTAL PLL clock source is XTAL +#define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC 0x04000000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_M 0x04000000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_S 26U +#define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_BAW 0x04000000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_XTAL 0x00000000U + +// Field: [25:24] DIVATST +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_W 2U +#define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_M 0x03000000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_S 24U +#define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_ONES 0x03000000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_ZEROS 0x00000000U + +// Field: [23] PERFM +// +// ENUMs: +// EN Enabled (performance) +// DIS Disabled (normal) +#define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM 0x00800000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_M 0x00800000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_S 23U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_EN 0x00800000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_DIS 0x00000000U + +// Field: [22] CHRGFILT +// +// ENUMs: +// EN Charging enabled +// DIS Charging disabled, normal operation +#define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT 0x00400000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_M 0x00400000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_S 22U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_EN 0x00400000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_DIS 0x00000000U + +// Field: [21:16] ATST +// +// ENUMs: +// VSSANA VSSANA +// FIRST_OUT First LDO output +// LDO_OUT LDO output +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_W 6U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_M 0x003F0000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_S 16U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_VSSANA 0x00200000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_FIRST_OUT 0x00010000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_LDO_OUT 0x00000000U + +// Field: [15:14] ITST +// +// ENUMs: +// BOTH Enable both pass transistors +// SECOND Enable second pass transistor +// FIRST Enable first pass transistor +// DIS Regulator is disabled +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_W 2U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_M 0x0000C000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_S 14U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_BOTH 0x0000C000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_SECOND 0x00008000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_FIRST 0x00004000U +#define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_DIS 0x00000000U + +// Field: [13:8] SECONDTRIM +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_W 6U +#define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_M 0x00003F00U +#define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_S 8U +#define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_ONES 0x00003F00U +#define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_ZEROS 0x00000000U + +// Field: [7:4] FIRSTTRIM +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_W 4U +#define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_M 0x000000F0U +#define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_S 4U +#define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_ONES 0x000000F0U +#define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_ZEROS 0x00000000U + +// Field: [3] PDN +// +// ENUMs: +// EN Pulldown +// DIS No Pulldown +#define LRFDRFE32_DCOLDO1_DCOLDO0_PDN 0x00000008U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_M 0x00000008U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_S 3U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_EN 0x00000008U +#define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_DIS 0x00000000U + +// Field: [2] BYPFIRST +// +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST 0x00000004U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_M 0x00000004U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_S 2U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_EN 0x00000004U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_DIS 0x00000000U + +// Field: [1] BYPBOTH +// +// ENUMs: +// EN Regulator is bypassed +// DIS No bypass +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH 0x00000002U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_M 0x00000002U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_S 1U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_EN 0x00000002U +#define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_DIS 0x00000000U + +// Field: [0] CTL +// +// ENUMs: +// EN Regulator is enabled +// DIS Regulator is disabled +#define LRFDRFE32_DCOLDO1_DCOLDO0_CTL 0x00000001U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_M 0x00000001U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_S 0U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_EN 0x00000001U +#define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PRE1_PRE0 +// +//***************************************************************************** +// Field: [31:30] IIRBW +// +// ENUMs: +// K16 K=16 +// K8 +// K4 +// K2 +#define LRFDRFE32_PRE1_PRE0_IIRBW_W 2U +#define LRFDRFE32_PRE1_PRE0_IIRBW_M 0xC0000000U +#define LRFDRFE32_PRE1_PRE0_IIRBW_S 30U +#define LRFDRFE32_PRE1_PRE0_IIRBW_K16 0xC0000000U +#define LRFDRFE32_PRE1_PRE0_IIRBW_K8 0x80000000U +#define LRFDRFE32_PRE1_PRE0_IIRBW_K4 0x40000000U +#define LRFDRFE32_PRE1_PRE0_IIRBW_K2 0x00000000U + +// Field: [29] IIRORD +// +// ENUMs: +// SECOND Select second order IIR filter +// FIRST Select first order IIR filter +#define LRFDRFE32_PRE1_PRE0_IIRORD 0x20000000U +#define LRFDRFE32_PRE1_PRE0_IIRORD_M 0x20000000U +#define LRFDRFE32_PRE1_PRE0_IIRORD_S 29U +#define LRFDRFE32_PRE1_PRE0_IIRORD_SECOND 0x20000000U +#define LRFDRFE32_PRE1_PRE0_IIRORD_FIRST 0x00000000U + +// Field: [28:24] IIRDIV +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_IIRDIV_W 5U +#define LRFDRFE32_PRE1_PRE0_IIRDIV_M 0x1F000000U +#define LRFDRFE32_PRE1_PRE0_IIRDIV_S 24U +#define LRFDRFE32_PRE1_PRE0_IIRDIV_ALLONES 0x1F000000U +#define LRFDRFE32_PRE1_PRE0_IIRDIV_ALLZEROS 0x00000000U + +// Field: [22] CALHSDDC +// +// ENUMs: +// GATE Duty-cycling given by HSDDC +// NOGATE No duty-cycling +#define LRFDRFE32_PRE1_PRE0_CALHSDDC 0x00400000U +#define LRFDRFE32_PRE1_PRE0_CALHSDDC_M 0x00400000U +#define LRFDRFE32_PRE1_PRE0_CALHSDDC_S 22U +#define LRFDRFE32_PRE1_PRE0_CALHSDDC_GATE 0x00400000U +#define LRFDRFE32_PRE1_PRE0_CALHSDDC_NOGATE 0x00000000U + +// Field: [21:16] HSDDC +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_HSDDC_W 6U +#define LRFDRFE32_PRE1_PRE0_HSDDC_M 0x003F0000U +#define LRFDRFE32_PRE1_PRE0_HSDDC_S 16U +#define LRFDRFE32_PRE1_PRE0_HSDDC_ALLONES 0x003F0000U +#define LRFDRFE32_PRE1_PRE0_HSDDC_ALLZEROS 0x00000000U + +// Field: [15:14] SPARE14 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_SPARE14_W 2U +#define LRFDRFE32_PRE1_PRE0_SPARE14_M 0x0000C000U +#define LRFDRFE32_PRE1_PRE0_SPARE14_S 14U +#define LRFDRFE32_PRE1_PRE0_SPARE14_ALLONES 0x0000C000U +#define LRFDRFE32_PRE1_PRE0_SPARE14_ALLZEROS 0x00000000U + +// Field: [13:8] PLLDIV1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_PLLDIV1_W 6U +#define LRFDRFE32_PRE1_PRE0_PLLDIV1_M 0x00003F00U +#define LRFDRFE32_PRE1_PRE0_PLLDIV1_S 8U +#define LRFDRFE32_PRE1_PRE0_PLLDIV1_ALLONES 0x00003F00U +#define LRFDRFE32_PRE1_PRE0_PLLDIV1_ALLZEROS 0x00000000U + +// Field: [7:6] SPARE6 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_SPARE6_W 2U +#define LRFDRFE32_PRE1_PRE0_SPARE6_M 0x000000C0U +#define LRFDRFE32_PRE1_PRE0_SPARE6_S 6U +#define LRFDRFE32_PRE1_PRE0_SPARE6_ALLONES 0x000000C0U +#define LRFDRFE32_PRE1_PRE0_SPARE6_ALLZEROS 0x00000000U + +// Field: [5:0] PLLDIV0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE1_PRE0_PLLDIV0_W 6U +#define LRFDRFE32_PRE1_PRE0_PLLDIV0_M 0x0000003FU +#define LRFDRFE32_PRE1_PRE0_PLLDIV0_S 0U +#define LRFDRFE32_PRE1_PRE0_PLLDIV0_ALLONES 0x0000003FU +#define LRFDRFE32_PRE1_PRE0_PLLDIV0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PRE3_PRE2 +// +//***************************************************************************** +// Field: [31:21] FINECALDIV +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE3_PRE2_FINECALDIV_W 11U +#define LRFDRFE32_PRE3_PRE2_FINECALDIV_M 0xFFE00000U +#define LRFDRFE32_PRE3_PRE2_FINECALDIV_S 21U +#define LRFDRFE32_PRE3_PRE2_FINECALDIV_ALLONES 0xFFE00000U +#define LRFDRFE32_PRE3_PRE2_FINECALDIV_ALLZEROS 0x00000000U + +// Field: [20:16] MIDCALDIVMSB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_W 5U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_M 0x001F0000U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_S 16U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_ALLONES 0x001F0000U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_ALLZEROS 0x00000000U + +// Field: [15:12] MIDCALDIVLSB +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_W 4U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_M 0x0000F000U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_S 12U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_ALLONES 0x0000F000U +#define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_ALLZEROS 0x00000000U + +// Field: [11:6] CRSCALDIV +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE3_PRE2_CRSCALDIV_W 6U +#define LRFDRFE32_PRE3_PRE2_CRSCALDIV_M 0x00000FC0U +#define LRFDRFE32_PRE3_PRE2_CRSCALDIV_S 6U +#define LRFDRFE32_PRE3_PRE2_CRSCALDIV_ALLONES 0x00000FC0U +#define LRFDRFE32_PRE3_PRE2_CRSCALDIV_ALLZEROS 0x00000000U + +// Field: [5:0] FSMDIV +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRE3_PRE2_FSMDIV_W 6U +#define LRFDRFE32_PRE3_PRE2_FSMDIV_M 0x0000003FU +#define LRFDRFE32_PRE3_PRE2_FSMDIV_S 0U +#define LRFDRFE32_PRE3_PRE2_FSMDIV_ALLONES 0x0000003FU +#define LRFDRFE32_PRE3_PRE2_FSMDIV_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_CAL1_CAL0 +// +//***************************************************************************** +// Field: [31] CAL1_SPARE15 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15 0x80000000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_M 0x80000000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_S 31U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_ONE 0x80000000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_ZERO 0x00000000U + +// Field: [30:24] CAL1_FCTOP +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_W 7U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_M 0x7F000000U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_S 24U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_ALLONES 0x7F000000U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_ALLZEROS 0x00000000U + +// Field: [23] CAL1_SPARE7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7 0x00800000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_M 0x00800000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_S 23U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_ONE 0x00800000U +#define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_ZERO 0x00000000U + +// Field: [22:16] CAL1_FCBOT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_W 7U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_M 0x007F0000U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_S 16U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_ALLONES 0x007F0000U +#define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_ALLZEROS 0x00000000U + +// Field: [15] CAL0_SPARE15 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15 0x00008000U +#define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_M 0x00008000U +#define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_S 15U +#define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_ONE 0x00008000U +#define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_ZERO 0x00000000U + +// Field: [14:8] CAL0_FCSTART +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_W 7U +#define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_M 0x00007F00U +#define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_S 8U +#define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_ALLONES 0x00007F00U +#define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_ALLZEROS 0x00000000U + +// Field: [7] CAL0_CRS +// +// ENUMs: +// EN Enable coarse calibration +// DIS Disable coarse calibration +#define LRFDRFE32_CAL1_CAL0_CAL0_CRS 0x00000080U +#define LRFDRFE32_CAL1_CAL0_CAL0_CRS_M 0x00000080U +#define LRFDRFE32_CAL1_CAL0_CAL0_CRS_S 7U +#define LRFDRFE32_CAL1_CAL0_CAL0_CRS_EN 0x00000080U +#define LRFDRFE32_CAL1_CAL0_CAL0_CRS_DIS 0x00000000U + +// Field: [6] CAL0_MID +// +// ENUMs: +// EN Enable mid calibration +// DIS Disable mid calibration +#define LRFDRFE32_CAL1_CAL0_CAL0_MID 0x00000040U +#define LRFDRFE32_CAL1_CAL0_CAL0_MID_M 0x00000040U +#define LRFDRFE32_CAL1_CAL0_CAL0_MID_S 6U +#define LRFDRFE32_CAL1_CAL0_CAL0_MID_EN 0x00000040U +#define LRFDRFE32_CAL1_CAL0_CAL0_MID_DIS 0x00000000U + +// Field: [5] CAL0_KTDC +// +// ENUMs: +// EN Enable TDC estimation +// DIS Disable TDC estimation +#define LRFDRFE32_CAL1_CAL0_CAL0_KTDC 0x00000020U +#define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_M 0x00000020U +#define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_S 5U +#define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_EN 0x00000020U +#define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_DIS 0x00000000U + +// Field: [4] CAL0_KDCO +// +// ENUMs: +// EN Enable KDCO estimation +// DIS Disable KDCO estimation +#define LRFDRFE32_CAL1_CAL0_CAL0_KDCO 0x00000010U +#define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_M 0x00000010U +#define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_S 4U +#define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_EN 0x00000010U +#define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_DIS 0x00000000U + +// Field: [3:2] CAL0_TDCAVG +// +// ENUMs: +// REPEAT_8_TIMES Repeat measurement 8 times +// REPEAT_4_TIMES Repeat measurement 4 times +// REPEAT_2_TIMES Repeat measurement 2 times +// REPEAT_1_TIME Repeat measurement 1 time +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_W 2U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_M 0x0000000CU +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_S 2U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_8_TIMES 0x0000000CU +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_4_TIMES 0x00000008U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_2_TIMES 0x00000004U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_1_TIME 0x00000000U + +// Field: [1:0] CAL0_TDC_SPARE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_W 2U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_M 0x00000003U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_S 0U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_ALLONES 0x00000003U +#define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_CAL3_CAL2 +// +//***************************************************************************** +// Field: [31:16] DTXGAIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL3_CAL2_DTXGAIN_W 16U +#define LRFDRFE32_CAL3_CAL2_DTXGAIN_M 0xFFFF0000U +#define LRFDRFE32_CAL3_CAL2_DTXGAIN_S 16U +#define LRFDRFE32_CAL3_CAL2_DTXGAIN_ALLONES 0xFFFF0000U +#define LRFDRFE32_CAL3_CAL2_DTXGAIN_ALLZEROS 0x00000000U + +// Field: [15:0] KTDCINV +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CAL3_CAL2_KTDCINV_W 16U +#define LRFDRFE32_CAL3_CAL2_KTDCINV_M 0x0000FFFFU +#define LRFDRFE32_CAL3_CAL2_KTDCINV_S 0U +#define LRFDRFE32_CAL3_CAL2_KTDCINV_ALLONES 0x0000FFFFU +#define LRFDRFE32_CAL3_CAL2_KTDCINV_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MISC1_MISC0 +// +//***************************************************************************** +// Field: [30] FCDEMCLK +// +// ENUMs: +// CKVD64 ckvd64 clock used for update upper and lower DWA +// DEM +// CKCD16 ckvd16 clock used for update upper and lower DWA +// DEM +#define LRFDRFE32_MISC1_MISC0_FCDEMCLK 0x40000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMCLK_M 0x40000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMCLK_S 30U +#define LRFDRFE32_MISC1_MISC0_FCDEMCLK_CKVD64 0x40000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMCLK_CKCD16 0x00000000U + +// Field: [29:28] FCDEMUPD +// +// ENUMs: +// SDM_XOR_PH_ERR phase_error[0] xor SDM[1] +// SDM SDM[1] (this value depends on DEM for SDM) +// PH_ERR phase_error[0]. (Phase error is 6.11s ) +// DEFAULT Default: Update both DWAs always at rising edge of +// selected clock +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_W 2U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_M 0x30000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_S 28U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_SDM_XOR_PH_ERR 0x30000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_SDM 0x20000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_PH_ERR 0x10000000U +#define LRFDRFE32_MISC1_MISC0_FCDEMUPD_DEFAULT 0x00000000U + +// Field: [27:22] TDCINL +// +// ENUMs: +// ONES All bits are one +// ZEROS All bits are zero +#define LRFDRFE32_MISC1_MISC0_TDCINL_W 6U +#define LRFDRFE32_MISC1_MISC0_TDCINL_M 0x0FC00000U +#define LRFDRFE32_MISC1_MISC0_TDCINL_S 22U +#define LRFDRFE32_MISC1_MISC0_TDCINL_ONES 0x0FC00000U +#define LRFDRFE32_MISC1_MISC0_TDCINL_ZEROS 0x00000000U + +// Field: [21] TDCINLCTL +// +// ENUMs: +// EN Enables INL correction of TDC +// DIS Disabled INL correction +#define LRFDRFE32_MISC1_MISC0_TDCINLCTL 0x00200000U +#define LRFDRFE32_MISC1_MISC0_TDCINLCTL_M 0x00200000U +#define LRFDRFE32_MISC1_MISC0_TDCINLCTL_S 21U +#define LRFDRFE32_MISC1_MISC0_TDCINLCTL_EN 0x00200000U +#define LRFDRFE32_MISC1_MISC0_TDCINLCTL_DIS 0x00000000U + +// Field: [20] PHINIT +// +// ENUMs: +// UNKNOWN Unknown phase +// KNOWN Known phase +#define LRFDRFE32_MISC1_MISC0_PHINIT 0x00100000U +#define LRFDRFE32_MISC1_MISC0_PHINIT_M 0x00100000U +#define LRFDRFE32_MISC1_MISC0_PHINIT_S 20U +#define LRFDRFE32_MISC1_MISC0_PHINIT_UNKNOWN 0x00100000U +#define LRFDRFE32_MISC1_MISC0_PHINIT_KNOWN 0x00000000U + +// Field: [19] SDMOOVRCTL +// +// ENUMs: +// EN Enable SDM output override +// DIS Disable SDM output override +#define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL 0x00080000U +#define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_M 0x00080000U +#define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_S 19U +#define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_EN 0x00080000U +#define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_DIS 0x00000000U + +// Field: [18:16] SDMOOVR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MISC1_MISC0_SDMOOVR_W 3U +#define LRFDRFE32_MISC1_MISC0_SDMOOVR_M 0x00070000U +#define LRFDRFE32_MISC1_MISC0_SDMOOVR_S 16U +#define LRFDRFE32_MISC1_MISC0_SDMOOVR_ALLONES 0x00070000U +#define LRFDRFE32_MISC1_MISC0_SDMOOVR_ALLZEROS 0x00000000U + +// Field: [13] PHCPT +// +// ENUMs: +// ASYNC Phase capture mode is asyncrhonous +// SYNC Phase capture mode is synchronous +#define LRFDRFE32_MISC1_MISC0_PHCPT 0x00002000U +#define LRFDRFE32_MISC1_MISC0_PHCPT_M 0x00002000U +#define LRFDRFE32_MISC1_MISC0_PHCPT_S 13U +#define LRFDRFE32_MISC1_MISC0_PHCPT_ASYNC 0x00002000U +#define LRFDRFE32_MISC1_MISC0_PHCPT_SYNC 0x00000000U + +// Field: [12] TDCCALCORR +// +// ENUMs: +// EN Enable TDC error correction inside DLO. +// DIS Disable TDC error correction inside DLO. +#define LRFDRFE32_MISC1_MISC0_TDCCALCORR 0x00001000U +#define LRFDRFE32_MISC1_MISC0_TDCCALCORR_M 0x00001000U +#define LRFDRFE32_MISC1_MISC0_TDCCALCORR_S 12U +#define LRFDRFE32_MISC1_MISC0_TDCCALCORR_EN 0x00001000U +#define LRFDRFE32_MISC1_MISC0_TDCCALCORR_DIS 0x00000000U + +// Field: [11] TDCMSBCORR +// +// ENUMs: +// EN Enable TDC error correction inside DLO. +// DIS Disable TDC error correction inside DLO. +#define LRFDRFE32_MISC1_MISC0_TDCMSBCORR 0x00000800U +#define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_M 0x00000800U +#define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_S 11U +#define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_EN 0x00000800U +#define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_DIS 0x00000000U + +// Field: [10] SDMDEM +// +// ENUMs: +// EN Enable dynamic element matching (recommended) +// DIS Disable dynamic element matching +#define LRFDRFE32_MISC1_MISC0_SDMDEM 0x00000400U +#define LRFDRFE32_MISC1_MISC0_SDMDEM_M 0x00000400U +#define LRFDRFE32_MISC1_MISC0_SDMDEM_S 10U +#define LRFDRFE32_MISC1_MISC0_SDMDEM_EN 0x00000400U +#define LRFDRFE32_MISC1_MISC0_SDMDEM_DIS 0x00000000U + +// Field: [9:8] DLYSDM +// +// ENUMs: +// CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods +// CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods +// CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period +// CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods +#define LRFDRFE32_MISC1_MISC0_DLYSDM_W 2U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_M 0x00000300U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_S 8U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_3_PER 0x00000300U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_2_PER 0x00000200U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_1_PER 0x00000100U +#define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_0_PER 0x00000000U + +// Field: [6] DLYPHVALID +// +// ENUMs: +// CKVD16_1_PER Delays the variable phase capture and hence the +// phase error calculation with 1 CKVD16 clock +// period. +// CKVD16_0_PER No additional delay on variable phase capture. +#define LRFDRFE32_MISC1_MISC0_DLYPHVALID 0x00000040U +#define LRFDRFE32_MISC1_MISC0_DLYPHVALID_M 0x00000040U +#define LRFDRFE32_MISC1_MISC0_DLYPHVALID_S 6U +#define LRFDRFE32_MISC1_MISC0_DLYPHVALID_CKVD16_1_PER 0x00000040U +#define LRFDRFE32_MISC1_MISC0_DLYPHVALID_CKVD16_0_PER 0x00000000U + +// Field: [5:4] DLYCANCRS +// +// ENUMs: +// CKVD64_3_PER Delay by 3 CKVD64 clock periods +// CKVD64_2_PER Delay by 2 CKVD64 clock periods +// CKVD64_1_PER Delay by 1 CKVD64 clock period +// CKVD64_0_PER Delay by 0 CKVD64 clock periods +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_W 2U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_M 0x00000030U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_S 4U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_3_PER 0x00000030U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_2_PER 0x00000020U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_1_PER 0x00000010U +#define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_0_PER 0x00000000U + +// Field: [3:2] DLYCANFINE +// +// ENUMs: +// CKVD16_4_PER Delay by 4 CKVD16 clock periods +// CKVD16_3_PER Delay by 3 CKVD16 clock periods +// CKVD16_2_PER Delay by 2 CKVD16 clock period +// CKVD16_1_PER Delay by 1 CKVD16 clock periods +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_W 2U +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_M 0x0000000CU +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_S 2U +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_4_PER 0x0000000CU +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_3_PER 0x00000008U +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_2_PER 0x00000004U +#define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_1_PER 0x00000000U + +// Field: [1:0] DLYADD +// +// ENUMs: +// CKVD64_3_PER Delay by 3 CKVD64 clock periods +// CKVD64_2_PER Delay by 2 CKVD64 clock periods +// CKVD64_1_PER Delay by 1 CKVD64 clock period +// CKVD64_0_PER Delay by 0 CKVD64 clock periods +#define LRFDRFE32_MISC1_MISC0_DLYADD_W 2U +#define LRFDRFE32_MISC1_MISC0_DLYADD_M 0x00000003U +#define LRFDRFE32_MISC1_MISC0_DLYADD_S 0U +#define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_3_PER 0x00000003U +#define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_2_PER 0x00000002U +#define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_1_PER 0x00000001U +#define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_0_PER 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_LF1_LF0 +// +//***************************************************************************** +// Field: [29:16] KP +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_LF1_LF0_KP_W 14U +#define LRFDRFE32_LF1_LF0_KP_M 0x3FFF0000U +#define LRFDRFE32_LF1_LF0_KP_S 16U +#define LRFDRFE32_LF1_LF0_KP_ALLONES 0x3FFF0000U +#define LRFDRFE32_LF1_LF0_KP_ALLZEROS 0x00000000U + +// Field: [12] KIPREC +// +// ENUMs: +// HIGH KI encoding is <4.08> +// LOW KI encoding is <12.0u> +#define LRFDRFE32_LF1_LF0_KIPREC 0x00001000U +#define LRFDRFE32_LF1_LF0_KIPREC_M 0x00001000U +#define LRFDRFE32_LF1_LF0_KIPREC_S 12U +#define LRFDRFE32_LF1_LF0_KIPREC_HIGH 0x00001000U +#define LRFDRFE32_LF1_LF0_KIPREC_LOW 0x00000000U + +// Field: [11:0] KI +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_LF1_LF0_KI_W 12U +#define LRFDRFE32_LF1_LF0_KI_M 0x00000FFFU +#define LRFDRFE32_LF1_LF0_KI_S 0U +#define LRFDRFE32_LF1_LF0_KI_ALLONES 0x00000FFFU +#define LRFDRFE32_LF1_LF0_KI_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PHINIT_PHEDISC +// +//***************************************************************************** +// Field: [23:16] OFF +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PHINIT_PHEDISC_OFF_W 8U +#define LRFDRFE32_PHINIT_PHEDISC_OFF_M 0x00FF0000U +#define LRFDRFE32_PHINIT_PHEDISC_OFF_S 16U +#define LRFDRFE32_PHINIT_PHEDISC_OFF_ALLONES 0x00FF0000U +#define LRFDRFE32_PHINIT_PHEDISC_OFF_ALLZEROS 0x00000000U + +// Field: [13:10] CNT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PHINIT_PHEDISC_CNT_W 4U +#define LRFDRFE32_PHINIT_PHEDISC_CNT_M 0x00003C00U +#define LRFDRFE32_PHINIT_PHEDISC_CNT_S 10U +#define LRFDRFE32_PHINIT_PHEDISC_CNT_ALLONES 0x00003C00U +#define LRFDRFE32_PHINIT_PHEDISC_CNT_ALLZEROS 0x00000000U + +// Field: [9:0] THR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PHINIT_PHEDISC_THR_W 10U +#define LRFDRFE32_PHINIT_PHEDISC_THR_M 0x000003FFU +#define LRFDRFE32_PHINIT_PHEDISC_THR_S 0U +#define LRFDRFE32_PHINIT_PHEDISC_THR_ALLONES 0x000003FFU +#define LRFDRFE32_PHINIT_PHEDISC_THR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PLLMON1_PLLMON0 +// +//***************************************************************************** +// Field: [28:24] PHELOCKCNT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_W 5U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_M 0x1F000000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_S 24U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_ALLONES 0x1F000000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_ALLZEROS 0x00000000U + +// Field: [23:16] PHELOCKTHR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_W 8U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_M 0x00FF0000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_S 16U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_ALLONES 0x00FF0000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_ALLZEROS 0x00000000U + +// Field: [15:14] PHELOLCNT +// +// ENUMs: +// REFCLK_128_PER Threshold count is 128 REFCLK periods +// REFCLK_64_PER Threshold count is 64 REFCLK periods +// REFCLK_32_PER Threshold count is 32 REFCLK periods +// REFCLK_16_PER Threshold count is 16 REFCLK periods +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_W 2U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_M 0x0000C000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_S 14U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_128_PER 0x0000C000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_64_PER 0x00008000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_32_PER 0x00004000U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_16_PER 0x00000000U + +// Field: [13:8] PHELOLTHR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_W 6U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_M 0x00003F00U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_S 8U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_ALLONES 0x00003F00U +#define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_ALLZEROS 0x00000000U + +// Field: [6:0] FCTHR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_W 7U +#define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_M 0x0000007FU +#define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_S 0U +#define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_ALLONES 0x0000007FU +#define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MOD1_MOD0 +// +//***************************************************************************** +// Field: [27:16] FOFF +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MOD1_MOD0_FOFF_W 12U +#define LRFDRFE32_MOD1_MOD0_FOFF_M 0x0FFF0000U +#define LRFDRFE32_MOD1_MOD0_FOFF_S 16U +#define LRFDRFE32_MOD1_MOD0_FOFF_ALLONES 0x0FFF0000U +#define LRFDRFE32_MOD1_MOD0_FOFF_ALLZEROS 0x00000000U + +// Field: [12:11] SCHEME +// +// ENUMs: +// TWO_POINT_MOD_FRF 2-point modulation with FRF resolution MOD_RES = +// FRF / 2^(21+CANPTHGAIN) Scheme supports both +// open -and closed-loop operation. Scheme allows +// wider modulation bandwiths than INLOOP_MOD_FRF. +// INLOOP_MOD_FRF In-loop modulation with FRF resolution MOD_RES = +// FRF / 2^(21+CANPTHGAIN) +// INLOOP_MOD_FREF In-loop modulation with FREF resolution MOD_RES = +// FREF / (DIVIDER/2) / 2^(15+CANPTHGAIN) +// DIV.RATIO determines DIVIDER configuration. +// Scheme only supports closed-loop operation. +// NC No connect Modulator output does not add to +// frequencey control word from PLL. +#define LRFDRFE32_MOD1_MOD0_SCHEME_W 2U +#define LRFDRFE32_MOD1_MOD0_SCHEME_M 0x00001800U +#define LRFDRFE32_MOD1_MOD0_SCHEME_S 11U +#define LRFDRFE32_MOD1_MOD0_SCHEME_TWO_POINT_MOD_FRF 0x00001800U +#define LRFDRFE32_MOD1_MOD0_SCHEME_INLOOP_MOD_FRF 0x00001000U +#define LRFDRFE32_MOD1_MOD0_SCHEME_INLOOP_MOD_FREF 0x00000800U +#define LRFDRFE32_MOD1_MOD0_SCHEME_NC 0x00000000U + +// Field: [10:8] SYMSHP +// +// ENUMs: +// CHIRP Chirp modulation +// SHAPEDZIGBEE Use Shaped 802.15.4 modulation +// PCWSPSK Use piecewise linear PSK shaper defined by +// SHAPECFG* registers. +// ZIGBEE Use unshaped zigbee +// SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* +// registers. +#define LRFDRFE32_MOD1_MOD0_SYMSHP_W 3U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_M 0x00000700U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_S 8U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_CHIRP 0x00000400U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_SHAPEDZIGBEE 0x00000300U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_PCWSPSK 0x00000200U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_ZIGBEE 0x00000100U +#define LRFDRFE32_MOD1_MOD0_SYMSHP_SHAPEDFSK 0x00000000U + +// Field: [7:6] CANPTHGAIN +// +// ENUMs: +// TWO_POW_M_18 POW(2,-18) +// TWO_POW_M_17 POW(2,-17) +// TWO_POW_M_16 POW(2,-16) +// TWO_POW_M_15 POW(2,-15) +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_W 2U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_M 0x000000C0U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_S 6U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_18 0x000000C0U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_17 0x00000080U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_16 0x00000040U +#define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_15 0x00000000U + +// Field: [5:4] SHPGAIN +// +// ENUMs: +// X8 Shape gain = 8 +// X4 Shape gain = 4 +// X2 Shape gain = 2 +// X1 Shape gain = 1 +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_W 2U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_M 0x00000030U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_S 4U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_X8 0x00000030U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_X4 0x00000020U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_X2 0x00000010U +#define LRFDRFE32_MOD1_MOD0_SHPGAIN_X1 0x00000000U + +// Field: [3:2] INTPFACT +// +// ENUMs: +// ILLEGAL1 Illegal, unsupported setting +// INTP_BY_32 Interpolate by 32 +// INTP_BY_16 Interpolate by 16 +// ILLEGAL0 Illegal, unsupported setting +#define LRFDRFE32_MOD1_MOD0_INTPFACT_W 2U +#define LRFDRFE32_MOD1_MOD0_INTPFACT_M 0x0000000CU +#define LRFDRFE32_MOD1_MOD0_INTPFACT_S 2U +#define LRFDRFE32_MOD1_MOD0_INTPFACT_ILLEGAL1 0x0000000CU +#define LRFDRFE32_MOD1_MOD0_INTPFACT_INTP_BY_32 0x00000008U +#define LRFDRFE32_MOD1_MOD0_INTPFACT_INTP_BY_16 0x00000004U +#define LRFDRFE32_MOD1_MOD0_INTPFACT_ILLEGAL0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX1_DTX0 +// +//***************************************************************************** +// Field: [31:24] SHP3 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX1_DTX0_SHP3_W 8U +#define LRFDRFE32_DTX1_DTX0_SHP3_M 0xFF000000U +#define LRFDRFE32_DTX1_DTX0_SHP3_S 24U +#define LRFDRFE32_DTX1_DTX0_SHP3_ALLONES 0xFF000000U +#define LRFDRFE32_DTX1_DTX0_SHP3_ALLZEROS 0x00000000U + +// Field: [23:16] SHP2 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX1_DTX0_SHP2_W 8U +#define LRFDRFE32_DTX1_DTX0_SHP2_M 0x00FF0000U +#define LRFDRFE32_DTX1_DTX0_SHP2_S 16U +#define LRFDRFE32_DTX1_DTX0_SHP2_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX1_DTX0_SHP2_ALLZEROS 0x00000000U + +// Field: [15:8] SHP1 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX1_DTX0_SHP1_W 8U +#define LRFDRFE32_DTX1_DTX0_SHP1_M 0x0000FF00U +#define LRFDRFE32_DTX1_DTX0_SHP1_S 8U +#define LRFDRFE32_DTX1_DTX0_SHP1_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX1_DTX0_SHP1_ALLZEROS 0x00000000U + +// Field: [7:0] SHP0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX1_DTX0_SHP0_W 8U +#define LRFDRFE32_DTX1_DTX0_SHP0_M 0x000000FFU +#define LRFDRFE32_DTX1_DTX0_SHP0_S 0U +#define LRFDRFE32_DTX1_DTX0_SHP0_ALLONES 0x000000FFU +#define LRFDRFE32_DTX1_DTX0_SHP0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX3_DTX2 +// +//***************************************************************************** +// Field: [31:24] SHP7 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX3_DTX2_SHP7_W 8U +#define LRFDRFE32_DTX3_DTX2_SHP7_M 0xFF000000U +#define LRFDRFE32_DTX3_DTX2_SHP7_S 24U +#define LRFDRFE32_DTX3_DTX2_SHP7_ALLONES 0xFF000000U +#define LRFDRFE32_DTX3_DTX2_SHP7_ALLZEROS 0x00000000U + +// Field: [23:16] SHP6 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX3_DTX2_SHP6_W 8U +#define LRFDRFE32_DTX3_DTX2_SHP6_M 0x00FF0000U +#define LRFDRFE32_DTX3_DTX2_SHP6_S 16U +#define LRFDRFE32_DTX3_DTX2_SHP6_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX3_DTX2_SHP6_ALLZEROS 0x00000000U + +// Field: [15:8] SHP5 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX3_DTX2_SHP5_W 8U +#define LRFDRFE32_DTX3_DTX2_SHP5_M 0x0000FF00U +#define LRFDRFE32_DTX3_DTX2_SHP5_S 8U +#define LRFDRFE32_DTX3_DTX2_SHP5_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX3_DTX2_SHP5_ALLZEROS 0x00000000U + +// Field: [7:0] SHP4 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX3_DTX2_SHP4_W 8U +#define LRFDRFE32_DTX3_DTX2_SHP4_M 0x000000FFU +#define LRFDRFE32_DTX3_DTX2_SHP4_S 0U +#define LRFDRFE32_DTX3_DTX2_SHP4_ALLONES 0x000000FFU +#define LRFDRFE32_DTX3_DTX2_SHP4_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX5_DTX4 +// +//***************************************************************************** +// Field: [31:24] SHP11 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX5_DTX4_SHP11_W 8U +#define LRFDRFE32_DTX5_DTX4_SHP11_M 0xFF000000U +#define LRFDRFE32_DTX5_DTX4_SHP11_S 24U +#define LRFDRFE32_DTX5_DTX4_SHP11_ALLONES 0xFF000000U +#define LRFDRFE32_DTX5_DTX4_SHP11_ALLZEROS 0x00000000U + +// Field: [23:16] SHP10 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX5_DTX4_SHP10_W 8U +#define LRFDRFE32_DTX5_DTX4_SHP10_M 0x00FF0000U +#define LRFDRFE32_DTX5_DTX4_SHP10_S 16U +#define LRFDRFE32_DTX5_DTX4_SHP10_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX5_DTX4_SHP10_ALLZEROS 0x00000000U + +// Field: [15:8] SHP9 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX5_DTX4_SHP9_W 8U +#define LRFDRFE32_DTX5_DTX4_SHP9_M 0x0000FF00U +#define LRFDRFE32_DTX5_DTX4_SHP9_S 8U +#define LRFDRFE32_DTX5_DTX4_SHP9_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX5_DTX4_SHP9_ALLZEROS 0x00000000U + +// Field: [7:0] SHP8 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX5_DTX4_SHP8_W 8U +#define LRFDRFE32_DTX5_DTX4_SHP8_M 0x000000FFU +#define LRFDRFE32_DTX5_DTX4_SHP8_S 0U +#define LRFDRFE32_DTX5_DTX4_SHP8_ALLONES 0x000000FFU +#define LRFDRFE32_DTX5_DTX4_SHP8_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX7_DTX6 +// +//***************************************************************************** +// Field: [31:24] SHP15 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX7_DTX6_SHP15_W 8U +#define LRFDRFE32_DTX7_DTX6_SHP15_M 0xFF000000U +#define LRFDRFE32_DTX7_DTX6_SHP15_S 24U +#define LRFDRFE32_DTX7_DTX6_SHP15_ALLONES 0xFF000000U +#define LRFDRFE32_DTX7_DTX6_SHP15_ALLZEROS 0x00000000U + +// Field: [23:16] SHP14 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX7_DTX6_SHP14_W 8U +#define LRFDRFE32_DTX7_DTX6_SHP14_M 0x00FF0000U +#define LRFDRFE32_DTX7_DTX6_SHP14_S 16U +#define LRFDRFE32_DTX7_DTX6_SHP14_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX7_DTX6_SHP14_ALLZEROS 0x00000000U + +// Field: [15:8] SHP13 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX7_DTX6_SHP13_W 8U +#define LRFDRFE32_DTX7_DTX6_SHP13_M 0x0000FF00U +#define LRFDRFE32_DTX7_DTX6_SHP13_S 8U +#define LRFDRFE32_DTX7_DTX6_SHP13_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX7_DTX6_SHP13_ALLZEROS 0x00000000U + +// Field: [7:0] SHP12 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX7_DTX6_SHP12_W 8U +#define LRFDRFE32_DTX7_DTX6_SHP12_M 0x000000FFU +#define LRFDRFE32_DTX7_DTX6_SHP12_S 0U +#define LRFDRFE32_DTX7_DTX6_SHP12_ALLONES 0x000000FFU +#define LRFDRFE32_DTX7_DTX6_SHP12_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX9_DTX8 +// +//***************************************************************************** +// Field: [31:24] SHP19 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX9_DTX8_SHP19_W 8U +#define LRFDRFE32_DTX9_DTX8_SHP19_M 0xFF000000U +#define LRFDRFE32_DTX9_DTX8_SHP19_S 24U +#define LRFDRFE32_DTX9_DTX8_SHP19_ALLONES 0xFF000000U +#define LRFDRFE32_DTX9_DTX8_SHP19_ALLZEROS 0x00000000U + +// Field: [23:16] SHP18 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX9_DTX8_SHP18_W 8U +#define LRFDRFE32_DTX9_DTX8_SHP18_M 0x00FF0000U +#define LRFDRFE32_DTX9_DTX8_SHP18_S 16U +#define LRFDRFE32_DTX9_DTX8_SHP18_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX9_DTX8_SHP18_ALLZEROS 0x00000000U + +// Field: [15:8] SHP17 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX9_DTX8_SHP17_W 8U +#define LRFDRFE32_DTX9_DTX8_SHP17_M 0x0000FF00U +#define LRFDRFE32_DTX9_DTX8_SHP17_S 8U +#define LRFDRFE32_DTX9_DTX8_SHP17_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX9_DTX8_SHP17_ALLZEROS 0x00000000U + +// Field: [7:0] SHP16 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX9_DTX8_SHP16_W 8U +#define LRFDRFE32_DTX9_DTX8_SHP16_M 0x000000FFU +#define LRFDRFE32_DTX9_DTX8_SHP16_S 0U +#define LRFDRFE32_DTX9_DTX8_SHP16_ALLONES 0x000000FFU +#define LRFDRFE32_DTX9_DTX8_SHP16_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DTX11_DTX10 +// +//***************************************************************************** +// Field: [31:24] SHP23 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX11_DTX10_SHP23_W 8U +#define LRFDRFE32_DTX11_DTX10_SHP23_M 0xFF000000U +#define LRFDRFE32_DTX11_DTX10_SHP23_S 24U +#define LRFDRFE32_DTX11_DTX10_SHP23_ALLONES 0xFF000000U +#define LRFDRFE32_DTX11_DTX10_SHP23_ALLZEROS 0x00000000U + +// Field: [23:16] SHP22 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX11_DTX10_SHP22_W 8U +#define LRFDRFE32_DTX11_DTX10_SHP22_M 0x00FF0000U +#define LRFDRFE32_DTX11_DTX10_SHP22_S 16U +#define LRFDRFE32_DTX11_DTX10_SHP22_ALLONES 0x00FF0000U +#define LRFDRFE32_DTX11_DTX10_SHP22_ALLZEROS 0x00000000U + +// Field: [15:8] SHP21 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX11_DTX10_SHP21_W 8U +#define LRFDRFE32_DTX11_DTX10_SHP21_M 0x0000FF00U +#define LRFDRFE32_DTX11_DTX10_SHP21_S 8U +#define LRFDRFE32_DTX11_DTX10_SHP21_ALLONES 0x0000FF00U +#define LRFDRFE32_DTX11_DTX10_SHP21_ALLZEROS 0x00000000U + +// Field: [7:0] SHP20 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DTX11_DTX10_SHP20_W 8U +#define LRFDRFE32_DTX11_DTX10_SHP20_M 0x000000FFU +#define LRFDRFE32_DTX11_DTX10_SHP20_S 0U +#define LRFDRFE32_DTX11_DTX10_SHP20_ALLONES 0x000000FFU +#define LRFDRFE32_DTX11_DTX10_SHP20_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PLLM0 +// +//***************************************************************************** +// Field: [31:2] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLM0_VAL_W 30U +#define LRFDRFE32_PLLM0_VAL_M 0xFFFFFFFCU +#define LRFDRFE32_PLLM0_VAL_S 2U +#define LRFDRFE32_PLLM0_VAL_ALLONES 0x0000FFFCU +#define LRFDRFE32_PLLM0_VAL_ALLZEROS 0x00000000U + +// Field: [1:0] SPARE0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLM0_SPARE0_W 2U +#define LRFDRFE32_PLLM0_SPARE0_M 0x00000003U +#define LRFDRFE32_PLLM0_SPARE0_S 0U +#define LRFDRFE32_PLLM0_SPARE0_ALLONES 0x00000003U +#define LRFDRFE32_PLLM0_SPARE0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PLLM1 +// +//***************************************************************************** +// Field: [31:2] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLM1_VAL_W 30U +#define LRFDRFE32_PLLM1_VAL_M 0xFFFFFFFCU +#define LRFDRFE32_PLLM1_VAL_S 2U +#define LRFDRFE32_PLLM1_VAL_ALLONES 0x0000FFFCU +#define LRFDRFE32_PLLM1_VAL_ALLZEROS 0x00000000U + +// Field: [1:0] SPARE0 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PLLM1_SPARE0_W 2U +#define LRFDRFE32_PLLM1_SPARE0_M 0x00000003U +#define LRFDRFE32_PLLM1_SPARE0_S 0U +#define LRFDRFE32_PLLM1_SPARE0_ALLONES 0x00000003U +#define LRFDRFE32_PLLM1_SPARE0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_CALMMID_CALMCRS +// +//***************************************************************************** +// Field: [31:16] CALMMID_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_W 16U +#define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_M 0xFFFF0000U +#define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_S 16U +#define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] CALMCRS_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_W 16U +#define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_M 0x0000FFFFU +#define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_S 0U +#define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_REFDIV +// +//***************************************************************************** +// Field: [15:0] LOAD +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_REFDIV_LOAD_W 16U +#define LRFDRFE32_REFDIV_LOAD_M 0x0000FFFFU +#define LRFDRFE32_REFDIV_LOAD_S 0U +#define LRFDRFE32_REFDIV_LOAD_ALLONES 0x0000FFFFU +#define LRFDRFE32_REFDIV_LOAD_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DLOCTL0 +// +//***************************************************************************** +// Field: [10:8] TDCSTOP +// +// ENUMs: +// OPEN Open-loop operation +// CLOSED Closed-loop operation +#define LRFDRFE32_DLOCTL0_TDCSTOP_W 3U +#define LRFDRFE32_DLOCTL0_TDCSTOP_M 0x00000700U +#define LRFDRFE32_DLOCTL0_TDCSTOP_S 8U +#define LRFDRFE32_DLOCTL0_TDCSTOP_OPEN 0x00000100U +#define LRFDRFE32_DLOCTL0_TDCSTOP_CLOSED 0x00000000U + +// Field: [7] DTSTXTAL +// +// ENUMs: +// ONE Enable XTALBAW DTST interface +// ZERO Disable XTALBAW DTST interface +#define LRFDRFE32_DLOCTL0_DTSTXTAL 0x00000080U +#define LRFDRFE32_DLOCTL0_DTSTXTAL_M 0x00000080U +#define LRFDRFE32_DLOCTL0_DTSTXTAL_S 7U +#define LRFDRFE32_DLOCTL0_DTSTXTAL_ONE 0x00000080U +#define LRFDRFE32_DLOCTL0_DTSTXTAL_ZERO 0x00000000U + +// Field: [6:4] LOOPUPD +// +// ENUMs: +// ALT Use alternate REF (PLLM1) +// DEF Use default FREF (PLLM0) +#define LRFDRFE32_DLOCTL0_LOOPUPD_W 3U +#define LRFDRFE32_DLOCTL0_LOOPUPD_M 0x00000070U +#define LRFDRFE32_DLOCTL0_LOOPUPD_S 4U +#define LRFDRFE32_DLOCTL0_LOOPUPD_ALT 0x00000010U +#define LRFDRFE32_DLOCTL0_LOOPUPD_DEF 0x00000000U + +// Field: [3] PH3 +// +// ENUMs: +// START Close the loop to aquire phase lock, i.e. phase 3 +// of calibration routine. +// HALT Halt DLO FSM after DCO frequency span measurement +// When DLO and RFE runs KDCO estimation, RFE must +// compute KDCO from the frequency span, and +// calculate loop filter settings to use before +// lock aquisition. +#define LRFDRFE32_DLOCTL0_PH3 0x00000008U +#define LRFDRFE32_DLOCTL0_PH3_M 0x00000008U +#define LRFDRFE32_DLOCTL0_PH3_S 3U +#define LRFDRFE32_DLOCTL0_PH3_START 0x00000008U +#define LRFDRFE32_DLOCTL0_PH3_HALT 0x00000000U + +// Field: [2] PH2 +// +// ENUMs: +// START Start KDCO estimation, i.e. phase 2 of calibration +// routine. +// HALT Halt DLO FSM after TDC calibration measurement +// When DLO and RFE runs TDC calibration, RFE must +// use calibration measurement to calculcate +// CAL2.KTDCINV. +#define LRFDRFE32_DLOCTL0_PH2 0x00000004U +#define LRFDRFE32_DLOCTL0_PH2_M 0x00000004U +#define LRFDRFE32_DLOCTL0_PH2_S 2U +#define LRFDRFE32_DLOCTL0_PH2_START 0x00000004U +#define LRFDRFE32_DLOCTL0_PH2_HALT 0x00000000U + +// Field: [1] LOOPMODE +// +// ENUMs: +// OPEN Open-loop operation +// CLOSED Closed-loop operation +#define LRFDRFE32_DLOCTL0_LOOPMODE 0x00000002U +#define LRFDRFE32_DLOCTL0_LOOPMODE_M 0x00000002U +#define LRFDRFE32_DLOCTL0_LOOPMODE_S 1U +#define LRFDRFE32_DLOCTL0_LOOPMODE_OPEN 0x00000002U +#define LRFDRFE32_DLOCTL0_LOOPMODE_CLOSED 0x00000000U + +// Field: [0] RSTN +// +// ENUMs: +// ACTIVE DLO is not held in reset +// RESET DLO is reset +#define LRFDRFE32_DLOCTL0_RSTN 0x00000001U +#define LRFDRFE32_DLOCTL0_RSTN_M 0x00000001U +#define LRFDRFE32_DLOCTL0_RSTN_S 0U +#define LRFDRFE32_DLOCTL0_RSTN_ACTIVE 0x00000001U +#define LRFDRFE32_DLOCTL0_RSTN_RESET 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DLOCTL1 +// +//***************************************************************************** +// Field: [15] DCO +// +// ENUMs: +// EN Enable DCO +// DIS Disable DCO +#define LRFDRFE32_DLOCTL1_DCO 0x00008000U +#define LRFDRFE32_DLOCTL1_DCO_M 0x00008000U +#define LRFDRFE32_DLOCTL1_DCO_S 15U +#define LRFDRFE32_DLOCTL1_DCO_EN 0x00008000U +#define LRFDRFE32_DLOCTL1_DCO_DIS 0x00000000U + +// Field: [7] FCDEM +// +// ENUMs: +// EN Enable DEM +// DIS Disable DEM +#define LRFDRFE32_DLOCTL1_FCDEM 0x00000080U +#define LRFDRFE32_DLOCTL1_FCDEM_M 0x00000080U +#define LRFDRFE32_DLOCTL1_FCDEM_S 7U +#define LRFDRFE32_DLOCTL1_FCDEM_EN 0x00000080U +#define LRFDRFE32_DLOCTL1_FCDEM_DIS 0x00000000U + +// Field: [6] DTSTCKVD +// +// ENUMs: +// ONE Enable CKVD DTST interface +// ZERO Disable CKVD DTST interface +#define LRFDRFE32_DLOCTL1_DTSTCKVD 0x00000040U +#define LRFDRFE32_DLOCTL1_DTSTCKVD_M 0x00000040U +#define LRFDRFE32_DLOCTL1_DTSTCKVD_S 6U +#define LRFDRFE32_DLOCTL1_DTSTCKVD_ONE 0x00000040U +#define LRFDRFE32_DLOCTL1_DTSTCKVD_ZERO 0x00000000U + +// Field: [5] PHEDISC +// +// ENUMs: +// EN Enable phase error discard function +// DIS Disable phase error discard function +#define LRFDRFE32_DLOCTL1_PHEDISC 0x00000020U +#define LRFDRFE32_DLOCTL1_PHEDISC_M 0x00000020U +#define LRFDRFE32_DLOCTL1_PHEDISC_S 5U +#define LRFDRFE32_DLOCTL1_PHEDISC_EN 0x00000020U +#define LRFDRFE32_DLOCTL1_PHEDISC_DIS 0x00000000U + +// Field: [4] PLLMON +// +// ENUMs: +// EN Enable PLL monitor +// DIS Disable and reset PLL monitor +#define LRFDRFE32_DLOCTL1_PLLMON 0x00000010U +#define LRFDRFE32_DLOCTL1_PLLMON_M 0x00000010U +#define LRFDRFE32_DLOCTL1_PLLMON_S 4U +#define LRFDRFE32_DLOCTL1_PLLMON_EN 0x00000010U +#define LRFDRFE32_DLOCTL1_PLLMON_DIS 0x00000000U + +// Field: [3] IIR +// +// ENUMs: +// EN Enable IIR filter +// DIS Disable IIR filter +#define LRFDRFE32_DLOCTL1_IIR 0x00000008U +#define LRFDRFE32_DLOCTL1_IIR_M 0x00000008U +#define LRFDRFE32_DLOCTL1_IIR_S 3U +#define LRFDRFE32_DLOCTL1_IIR_EN 0x00000008U +#define LRFDRFE32_DLOCTL1_IIR_DIS 0x00000000U + +// Field: [2] MOD +// +// ENUMs: +// EN Enable MODISF +// DIS Disable MODISF +#define LRFDRFE32_DLOCTL1_MOD 0x00000004U +#define LRFDRFE32_DLOCTL1_MOD_M 0x00000004U +#define LRFDRFE32_DLOCTL1_MOD_S 2U +#define LRFDRFE32_DLOCTL1_MOD_EN 0x00000004U +#define LRFDRFE32_DLOCTL1_MOD_DIS 0x00000000U + +// Field: [1] MODINIT +// +// ENUMs: +// ACTIVATE Activate MODISF initialization +// DEACTIVATE Deactivate MODISF initialization +#define LRFDRFE32_DLOCTL1_MODINIT 0x00000002U +#define LRFDRFE32_DLOCTL1_MODINIT_M 0x00000002U +#define LRFDRFE32_DLOCTL1_MODINIT_S 1U +#define LRFDRFE32_DLOCTL1_MODINIT_ACTIVATE 0x00000002U +#define LRFDRFE32_DLOCTL1_MODINIT_DEACTIVATE 0x00000000U + +// Field: [0] MTDCRSTN +// +// ENUMs: +// ACTIVE Release MTDC reset +// RESET Reset MTDC +#define LRFDRFE32_DLOCTL1_MTDCRSTN 0x00000001U +#define LRFDRFE32_DLOCTL1_MTDCRSTN_M 0x00000001U +#define LRFDRFE32_DLOCTL1_MTDCRSTN_S 0U +#define LRFDRFE32_DLOCTL1_MTDCRSTN_ACTIVE 0x00000001U +#define LRFDRFE32_DLOCTL1_MTDCRSTN_RESET 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DCOOVR1_DCOOVR0 +// +//***************************************************************************** +// Field: [30:24] FINECODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_W 7U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_M 0x7F000000U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_S 24U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_ALLONES 0x7F000000U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_ALLZEROS 0x00000000U + +// Field: [23:16] SDMICODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_W 8U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_M 0x00FF0000U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_S 16U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_ALLONES 0x00FF0000U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_ALLZEROS 0x00000000U + +// Field: [13:8] MIDCODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_W 6U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_M 0x00003F00U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_S 8U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_ALLONES 0x00003F00U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_ALLZEROS 0x00000000U + +// Field: [7:4] CRSCODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_W 4U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_M 0x000000F0U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_S 4U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_ALLONES 0x000000F0U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_ALLZEROS 0x00000000U + +// Field: [3] FINECTL +// +// ENUMs: +// EN Enable fine code override +// DIS Disable fine code override +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL 0x00000008U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_M 0x00000008U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_S 3U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_EN 0x00000008U +#define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_DIS 0x00000000U + +// Field: [2] SDMICTL +// +// ENUMs: +// EN Enable SDM input code override +// DIS Disable SDM input code override +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL 0x00000004U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_M 0x00000004U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_S 2U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_EN 0x00000004U +#define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_DIS 0x00000000U + +// Field: [1] MIDCTL +// +// ENUMs: +// EN Enable mid code override +// DIS Disable mid code override +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL 0x00000002U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_M 0x00000002U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_S 1U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_EN 0x00000002U +#define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_DIS 0x00000000U + +// Field: [0] CRSCTL +// +// ENUMs: +// EN Enable coarse code override +// DIS Disable coarse code override +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL 0x00000001U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_M 0x00000001U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_S 0U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_EN 0x00000001U +#define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DLOEV_DTST +// +//***************************************************************************** +// Field: [23] LOCK +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DLOEV_DTST_LOCK 0x00800000U +#define LRFDRFE32_DLOEV_DTST_LOCK_M 0x00800000U +#define LRFDRFE32_DLOEV_DTST_LOCK_S 23U +#define LRFDRFE32_DLOEV_DTST_LOCK_ONE 0x00800000U +#define LRFDRFE32_DLOEV_DTST_LOCK_ZERO 0x00000000U + +// Field: [22] LOL +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DLOEV_DTST_LOL 0x00400000U +#define LRFDRFE32_DLOEV_DTST_LOL_M 0x00400000U +#define LRFDRFE32_DLOEV_DTST_LOL_S 22U +#define LRFDRFE32_DLOEV_DTST_LOL_ONE 0x00400000U +#define LRFDRFE32_DLOEV_DTST_LOL_ZERO 0x00000000U + +// Field: [21] FCABVTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DLOEV_DTST_FCABVTHR 0x00200000U +#define LRFDRFE32_DLOEV_DTST_FCABVTHR_M 0x00200000U +#define LRFDRFE32_DLOEV_DTST_FCABVTHR_S 21U +#define LRFDRFE32_DLOEV_DTST_FCABVTHR_ONE 0x00200000U +#define LRFDRFE32_DLOEV_DTST_FCABVTHR_ZERO 0x00000000U + +// Field: [20] FCBLWTHR +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DLOEV_DTST_FCBLWTHR 0x00100000U +#define LRFDRFE32_DLOEV_DTST_FCBLWTHR_M 0x00100000U +#define LRFDRFE32_DLOEV_DTST_FCBLWTHR_S 20U +#define LRFDRFE32_DLOEV_DTST_FCBLWTHR_ONE 0x00100000U +#define LRFDRFE32_DLOEV_DTST_FCBLWTHR_ZERO 0x00000000U + +// Field: [19:16] STATE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DLOEV_DTST_STATE_W 4U +#define LRFDRFE32_DLOEV_DTST_STATE_M 0x000F0000U +#define LRFDRFE32_DLOEV_DTST_STATE_S 16U +#define LRFDRFE32_DLOEV_DTST_STATE_ALLONES 0x000F0000U +#define LRFDRFE32_DLOEV_DTST_STATE_ALLZEROS 0x00000000U + +// Field: [14:11] SPARE11 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DLOEV_DTST_SPARE11_W 4U +#define LRFDRFE32_DLOEV_DTST_SPARE11_M 0x00007800U +#define LRFDRFE32_DLOEV_DTST_SPARE11_S 11U +#define LRFDRFE32_DLOEV_DTST_SPARE11_ALLONES 0x00007800U +#define LRFDRFE32_DLOEV_DTST_SPARE11_ALLZEROS 0x00000000U + +// Field: [10:8] VARTGLDLY +// +// ENUMs: +// CLK_7_PER Toggle lags data by 7 CKVD16 periods. +// CLK_6_PER Toggle lags data by 6 CKVD16 periods. +// CLK_5_PER Toggle lags data by 5 CKVD16 periods. +// CLK_4_PER Toggle lags data by 4 CKVD16 periods. +// CLK_3_PER Toggle lags data by 3 CKVD16 periods. +// CLK_2_PER Toggle lags data by 2 CKVD16 periods. +// CLK_1_PER Toggle lags data by 1 CKVD16 periods. +// CLK_0_PER Toggle lags data by 0 CKVD16 periods. +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_W 3U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_M 0x00000700U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_S 8U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_7_PER 0x00000700U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_6_PER 0x00000600U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_5_PER 0x00000500U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_4_PER 0x00000400U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_3_PER 0x00000300U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_2_PER 0x00000200U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_1_PER 0x00000100U +#define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_0_PER 0x00000000U + +// Field: [7] REFTGLDLY +// +// ENUMs: +// CLK_1_PER Toggle lags data by 1 HFXT/BAW periods. +// CLK_0_PER Toggle lags data by 0 HFXT/BAW periods. +#define LRFDRFE32_DLOEV_DTST_REFTGLDLY 0x00000080U +#define LRFDRFE32_DLOEV_DTST_REFTGLDLY_M 0x00000080U +#define LRFDRFE32_DLOEV_DTST_REFTGLDLY_S 7U +#define LRFDRFE32_DLOEV_DTST_REFTGLDLY_CLK_1_PER 0x00000080U +#define LRFDRFE32_DLOEV_DTST_REFTGLDLY_CLK_0_PER 0x00000000U + +// Field: [6] TRNSEQ +// +// ENUMs: +// EN Enable trainer sequence +// DIS Disable trainer sequence +#define LRFDRFE32_DLOEV_DTST_TRNSEQ 0x00000040U +#define LRFDRFE32_DLOEV_DTST_TRNSEQ_M 0x00000040U +#define LRFDRFE32_DLOEV_DTST_TRNSEQ_S 6U +#define LRFDRFE32_DLOEV_DTST_TRNSEQ_EN 0x00000040U +#define LRFDRFE32_DLOEV_DTST_TRNSEQ_DIS 0x00000000U + +// Field: [5] SPARE5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DLOEV_DTST_SPARE5 0x00000020U +#define LRFDRFE32_DLOEV_DTST_SPARE5_M 0x00000020U +#define LRFDRFE32_DLOEV_DTST_SPARE5_S 5U +#define LRFDRFE32_DLOEV_DTST_SPARE5_ONE 0x00000020U +#define LRFDRFE32_DLOEV_DTST_SPARE5_ZERO 0x00000000U + +// Field: [4:0] SIG +// +// ENUMs: +// VAR_NC_15 dtst_data = 0x0000 +// VAR_NC_14 dtst_data = 0x0000 +// VAR_NC_13 dtst_data = 0x0000 +// VAR_NC_12 dtst_data = 0x0000 +// VAR_NC_11 dtst_data = 0x0000 +// VAR_LOOP_UPD_FINECODE dtst_data : [15] : (u_pll/pll_loop_update) [14:0] +// : u_pll/po_ckvd16_finecode_pll +// VAR_LOCK_FINECODE dtst_data : [15] : (u_pll/po_ckvd48_pllmon_lock +// XOR u_pll/po_ckvd48_pllmon_lol) [14:0] : +// u_pll/po_ckvd16_finecode_pll +// VAR_MPX_CAN dtst_data : [15] : u_mpx/freq_can[16] [14:0] : +// u_mpx/freq_can[14:0] Format is 1.15s. This +// field holds how much phase DTX adds to DCO per +// reference frequency. This is a slice of the +// signals that goes to u_pll which is 3.18s. +// Hence, wrapping can occur. +// VAR_TDCSTOP_STATUS_TDC dtst_data : [15:14] : po_tdc_stop_dly_sel [13] : +// u_pll/pi_tdc_msb_error [12] : +// u_pll/pll_loop_update [11] : +// (u_pll/po_ckvd48_pllmon_lock XOR +// u_pll/po_ckvd48_pllmon_lol) [10:0]: +// u_pll/pi_tdc_data Note that [12:11] are samples +// from previous reference clock edge. +// VAR_TDCSTOP_PHERR dtst_data : [15:14] : po_tdc_stop_dly_sel [13] +// u_pll/phase_error[16] [12:0]: +// u_pll/phase_error[12:0] [13:0] : phase_error. +// Format is 3.11s. +// VAR_PH_COMP_PHERR_TDCSTOPdtst_data : [15:14] : po_tdc_stop_dly_sel [13] : +// u_pll/phase_error[16] [12:9]: +// u_pll/phase_error[11:8] [8:0] : +// u_pll/var_phase[14: 6] [13:9] : phase error. +// Format is 2.3s. [8:0] : variable phase. Format +// is 4.5u. +// VAR_PH_TDCCORR dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] +// : u_pll/pi_pi_cnt_lsb [10:0] : +// u_pll/tdc_data_corr +// VAR_PH_RAW dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] +// : u_pll/pi_pi_cnt_lsb [10:0] : +// u_pll/pi_tdc_data +// VAR_PHERR_LOWER dtst_data : [15] : u_pll/phase_error[16] [14:0] : +// u_pll/phase_error[14:0] Format is 5.11s. Phase +// error wraps if if too large. +// VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1] Format is +// 6.10s. +// VAR_NC_0 dtst_data = 0x0000 +// REF_NC_15 dtst_data = 0x0000 +// REF_NC_14 dtst_data = 0x0000 +// REF_NC_13 dtst_data = 0x0000 +// REF_NC_12 dtst_data = 0x0000 +// REF_NC_11 dtst_data = 0x0000 +// REF_NC_10 dtst_data = 0x0000 +// REF_NC_9 dtst_data = 0x0000 +// REF_NC_8 dtst_data = 0x0000 +// REF_NC_7 dtst_data = 0x0000 +// REF_NC_6 dtst_data = 0x0000 +// REF_NC_5 dtst_data = 0x0000 +// REF_NC_4 dtst_data = 0x0000 +// REF_NC_3 dtst_data = 0x0000 +// REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag Format +// is14.2u. The signal is only updated for +// frequency measurements that affect the +// calibration result. +// REF_FSMCAL dtst_data : [15] : '0' [14] : +// u_fsm/pi_pll_lock_ind [13:10] : +// u_fsm/po_dsts_fsm_state [9:6] : +// u_fsm/po_dtst_fsm_coarse [5:0] : +// u_fsm/po_dtst_fsm_mid +// REF_NC_0 dtst_data = 0x0000 +#define LRFDRFE32_DLOEV_DTST_SIG_W 5U +#define LRFDRFE32_DLOEV_DTST_SIG_M 0x0000001FU +#define LRFDRFE32_DLOEV_DTST_SIG_S 0U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_15 0x0000001FU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_14 0x0000001EU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_13 0x0000001DU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_12 0x0000001CU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_11 0x0000001BU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_LOOP_UPD_FINECODE 0x0000001AU +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_LOCK_FINECODE 0x00000019U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_MPX_CAN 0x00000018U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_TDCSTOP_STATUS_TDC 0x00000017U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_TDCSTOP_PHERR 0x00000016U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_COMP_PHERR_TDCSTOP 0x00000015U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_TDCCORR 0x00000014U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_RAW 0x00000013U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_PHERR_LOWER 0x00000012U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_PHERR_UPPER 0x00000011U +#define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_0 0x00000010U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_15 0x0000000FU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_14 0x0000000EU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_13 0x0000000DU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_12 0x0000000CU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_11 0x0000000BU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_10 0x0000000AU +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_9 0x00000009U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_8 0x00000008U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_7 0x00000007U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_6 0x00000006U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_5 0x00000005U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_4 0x00000004U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_3 0x00000003U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_FERR_MAG 0x00000002U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_FSMCAL 0x00000001U +#define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_0 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_FDCOSPANLSB_DTSTRD +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_W 16U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_M 0xFFFF0000U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_S 16U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] DATA +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_W 16U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_M 0x0000FFFFU +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_S 0U +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_ALLONES 0x0000FFFFU +#define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TDCCAL_FDCOSPANMSB +// +//***************************************************************************** +// Field: [31:16] TDCCAL_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_W 16U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_M 0xFFFF0000U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_S 16U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_ALLZEROS 0x00000000U + +// Field: [2:0] FDCOSPANMSB_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_W 3U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_M 0x00000007U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_S 0U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_ALLONES 0x00000007U +#define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_GPI_CALRES +// +//***************************************************************************** +// Field: [23] GPI7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI7 0x00800000U +#define LRFDRFE32_GPI_CALRES_GPI7_M 0x00800000U +#define LRFDRFE32_GPI_CALRES_GPI7_S 23U +#define LRFDRFE32_GPI_CALRES_GPI7_ONE 0x00800000U +#define LRFDRFE32_GPI_CALRES_GPI7_ZERO 0x00000000U + +// Field: [22] GPI6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI6 0x00400000U +#define LRFDRFE32_GPI_CALRES_GPI6_M 0x00400000U +#define LRFDRFE32_GPI_CALRES_GPI6_S 22U +#define LRFDRFE32_GPI_CALRES_GPI6_ONE 0x00400000U +#define LRFDRFE32_GPI_CALRES_GPI6_ZERO 0x00000000U + +// Field: [21] GPI5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI5 0x00200000U +#define LRFDRFE32_GPI_CALRES_GPI5_M 0x00200000U +#define LRFDRFE32_GPI_CALRES_GPI5_S 21U +#define LRFDRFE32_GPI_CALRES_GPI5_ONE 0x00200000U +#define LRFDRFE32_GPI_CALRES_GPI5_ZERO 0x00000000U + +// Field: [20] GPI4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI4 0x00100000U +#define LRFDRFE32_GPI_CALRES_GPI4_M 0x00100000U +#define LRFDRFE32_GPI_CALRES_GPI4_S 20U +#define LRFDRFE32_GPI_CALRES_GPI4_ONE 0x00100000U +#define LRFDRFE32_GPI_CALRES_GPI4_ZERO 0x00000000U + +// Field: [19] GPI3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI3 0x00080000U +#define LRFDRFE32_GPI_CALRES_GPI3_M 0x00080000U +#define LRFDRFE32_GPI_CALRES_GPI3_S 19U +#define LRFDRFE32_GPI_CALRES_GPI3_ONE 0x00080000U +#define LRFDRFE32_GPI_CALRES_GPI3_ZERO 0x00000000U + +// Field: [18] GPI2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI2 0x00040000U +#define LRFDRFE32_GPI_CALRES_GPI2_M 0x00040000U +#define LRFDRFE32_GPI_CALRES_GPI2_S 18U +#define LRFDRFE32_GPI_CALRES_GPI2_ONE 0x00040000U +#define LRFDRFE32_GPI_CALRES_GPI2_ZERO 0x00000000U + +// Field: [17] GPI1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI1 0x00020000U +#define LRFDRFE32_GPI_CALRES_GPI1_M 0x00020000U +#define LRFDRFE32_GPI_CALRES_GPI1_S 17U +#define LRFDRFE32_GPI_CALRES_GPI1_ONE 0x00020000U +#define LRFDRFE32_GPI_CALRES_GPI1_ZERO 0x00000000U + +// Field: [16] GPI0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPI_CALRES_GPI0 0x00010000U +#define LRFDRFE32_GPI_CALRES_GPI0_M 0x00010000U +#define LRFDRFE32_GPI_CALRES_GPI0_S 16U +#define LRFDRFE32_GPI_CALRES_GPI0_ONE 0x00010000U +#define LRFDRFE32_GPI_CALRES_GPI0_ZERO 0x00000000U + +// Field: [9:4] MIDCODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_GPI_CALRES_MIDCODE_W 6U +#define LRFDRFE32_GPI_CALRES_MIDCODE_M 0x000003F0U +#define LRFDRFE32_GPI_CALRES_MIDCODE_S 4U +#define LRFDRFE32_GPI_CALRES_MIDCODE_ALLONES 0x000003F0U +#define LRFDRFE32_GPI_CALRES_MIDCODE_ALLZEROS 0x00000000U + +// Field: [3:0] CRSCODE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_GPI_CALRES_CRSCODE_W 4U +#define LRFDRFE32_GPI_CALRES_CRSCODE_M 0x0000000FU +#define LRFDRFE32_GPI_CALRES_CRSCODE_S 0U +#define LRFDRFE32_GPI_CALRES_CRSCODE_ALLONES 0x0000000FU +#define LRFDRFE32_GPI_CALRES_CRSCODE_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_LIN2LOGOUT_MATHACCELIN +// +//***************************************************************************** +// Field: [22:16] LOGVAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_W 7U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_M 0x007F0000U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_S 16U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_ALLONES 0x007F0000U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_W 16U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_M 0x0000FFFFU +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_S 0U +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TIMCTL_DIVBY3OUT +// +//***************************************************************************** +// Field: [29:24] CPTSRC +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_W 6U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_M 0x3F000000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_S 24U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_ALLONES 0x3F000000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_ALLZEROS 0x00000000U + +// Field: [23] CPTCTL +// +// ENUMs: +// EN Enable counter capture mode +// DIS Disable counter capture mode +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL 0x00800000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_M 0x00800000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_S 23U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_EN 0x00800000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_DIS 0x00000000U + +// Field: [22:21] CNTRSRC +// +// ENUMs: +// FREF Count FREF ticks +// MAGN1 Use magnitude estimator 1 data enable +// MAGN0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_W 2U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_M 0x00600000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_S 21U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_FREF 0x00600000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_MAGN1 0x00400000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_MAGN0 0x00200000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_CLK 0x00000000U + +// Field: [20] CNTRCLR +// +// ENUMs: +// ONE Clear counter value +// ZERO No action +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR 0x00100000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_M 0x00100000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_S 20U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_ONE 0x00100000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_ZERO 0x00000000U + +// Field: [19] CNTRCTL +// +// ENUMs: +// EN Enable counter +// DIS Disable counter +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL 0x00080000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_M 0x00080000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_S 19U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_EN 0x00080000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_DIS 0x00000000U + +// Field: [18:17] TIMSRC +// +// ENUMs: +// FREF Count FREF ticks +// MAGN1 Use magnitude estimator 1 data enable +// MAGN0 Use magnitude estimator 0 data enable +// CLK Use clock +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_W 2U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_M 0x00060000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_S 17U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_FREF 0x00060000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_MAGN1 0x00040000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_MAGN0 0x00020000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_CLK 0x00000000U + +// Field: [16] TIMCTL +// +// ENUMs: +// EN Enable timer +// DIS Disable timer and clear internal timer value +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL 0x00010000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_M 0x00010000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_S 16U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_EN 0x00010000U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_DIS 0x00000000U + +// Field: [3:0] DIV3 +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_W 4U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_M 0x0000000FU +#define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_S 0U +#define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_ALLONES 0x0000000FU +#define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TIMPER_TIMINC +// +//***************************************************************************** +// Field: [31:16] TIMPER_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_W 16U +#define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_M 0xFFFF0000U +#define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_S 16U +#define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] TIMINC_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_W 16U +#define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_M 0x0000FFFFU +#define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_S 0U +#define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TIMCAPT_TIMCNT +// +//***************************************************************************** +// Field: [31:16] VALUE +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_W 16U +#define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_M 0xFFFF0000U +#define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_S 16U +#define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_ALLONES 0xFFFF0000U +#define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_ALLZEROS 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TIMCAPT_TIMCNT_VAL_W 16U +#define LRFDRFE32_TIMCAPT_TIMCNT_VAL_M 0x0000FFFFU +#define LRFDRFE32_TIMCAPT_TIMCNT_VAL_S 0U +#define LRFDRFE32_TIMCAPT_TIMCNT_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_TIMCAPT_TIMCNT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TRCSTAT_TRCCTRL +// +//***************************************************************************** +// Field: [16] BUSY +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY 0x00010000U +#define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_M 0x00010000U +#define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_S 16U +#define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_ONE 0x00010000U +#define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_ZERO 0x00000000U + +// Field: [0] SEND +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_TRCSTAT_TRCCTRL_SEND 0x00000001U +#define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_M 0x00000001U +#define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_S 0U +#define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_ONE 0x00000001U +#define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_ZERO 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_TRCPAR0_TRCCMD +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TRCPAR0_TRCCMD_VAL_W 16U +#define LRFDRFE32_TRCPAR0_TRCCMD_VAL_M 0xFFFF0000U +#define LRFDRFE32_TRCPAR0_TRCCMD_VAL_S 16U +#define LRFDRFE32_TRCPAR0_TRCCMD_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_TRCPAR0_TRCCMD_VAL_ALLZEROS 0x00000000U + +// Field: [9:8] PARCNT +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_W 2U +#define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_M 0x00000300U +#define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_S 8U +#define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_ALLONES 0x00000300U +#define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_ALLZEROS 0x00000000U + +// Field: [7:0] PKTHDR +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_W 8U +#define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_M 0x000000FFU +#define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_S 0U +#define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_ALLONES 0x000000FFU +#define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_GPOCTL_TRCPAR1 +// +//***************************************************************************** +// Field: [31] SEL7 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO7 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL7 0x80000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_M 0x80000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_S 31U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_HW 0x80000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_SW 0x00000000U + +// Field: [30] SEL6 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO6 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL6 0x40000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_M 0x40000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_S 30U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_HW 0x40000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_SW 0x00000000U + +// Field: [29] SEL5 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO5 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL5 0x20000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_M 0x20000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_S 29U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_HW 0x20000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_SW 0x00000000U + +// Field: [28] SEL4 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO4 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL4 0x10000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_M 0x10000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_S 28U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_HW 0x10000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_SW 0x00000000U + +// Field: [27] SEL3 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO3 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL3 0x08000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_M 0x08000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_S 27U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_HW 0x08000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_SW 0x00000000U + +// Field: [26] SEL2 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO2 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL2 0x04000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_M 0x04000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_S 26U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_HW 0x04000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_SW 0x00000000U + +// Field: [25] SEL1 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO1 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL1 0x02000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_M 0x02000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_S 25U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_HW 0x02000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_SW 0x00000000U + +// Field: [24] SEL0 +// +// ENUMs: +// HW The pin is controlled by its HW source +// SW The pin is controlled by GPOCTRL.GPO0 +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL0 0x01000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_M 0x01000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_S 24U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_HW 0x01000000U +#define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_SW 0x00000000U + +// Field: [23] GPO7 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO7 0x00800000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_M 0x00800000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_S 23U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_ONE 0x00800000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_ZERO 0x00000000U + +// Field: [22] GPO6 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO6 0x00400000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_M 0x00400000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_S 22U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_ONE 0x00400000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_ZERO 0x00000000U + +// Field: [21] GPO5 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO5 0x00200000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_M 0x00200000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_S 21U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_ONE 0x00200000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_ZERO 0x00000000U + +// Field: [20] GPO4 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO4 0x00100000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_M 0x00100000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_S 20U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_ONE 0x00100000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_ZERO 0x00000000U + +// Field: [19] GPO3 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO3 0x00080000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_M 0x00080000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_S 19U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_ONE 0x00080000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_ZERO 0x00000000U + +// Field: [18] GPO2 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO2 0x00040000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_M 0x00040000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_S 18U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_ONE 0x00040000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_ZERO 0x00000000U + +// Field: [17] GPO1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO1 0x00020000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_M 0x00020000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_S 17U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_ONE 0x00020000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_ZERO 0x00000000U + +// Field: [16] GPO0 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO0 0x00010000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_M 0x00010000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_S 16U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_ONE 0x00010000U +#define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_ZERO 0x00000000U + +// Field: [15:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_GPOCTL_TRCPAR1_VAL_W 16U +#define LRFDRFE32_GPOCTL_TRCPAR1_VAL_M 0x0000FFFFU +#define LRFDRFE32_GPOCTL_TRCPAR1_VAL_S 0U +#define LRFDRFE32_GPOCTL_TRCPAR1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_GPOCTL_TRCPAR1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DIVCTL_ANAISOCTL +// +//***************************************************************************** +// Field: [31] DIV2PH180 +// +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180 0x80000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_M 0x80000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_S 31U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_EN 0x80000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_DIS 0x00000000U + +// Field: [30] DIV2PH0 +// +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0 0x40000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_M 0x40000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_S 30U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_EN 0x40000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_DIS 0x00000000U + +// Field: [29] DIV2PH270 +// +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270 0x20000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_M 0x20000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_S 29U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_EN 0x20000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_DIS 0x00000000U + +// Field: [28] DIV2PH90 +// +// ENUMs: +// EN Enable path +// DIS Disable path +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90 0x10000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_M 0x10000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_S 28U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_EN 0x10000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_DIS 0x00000000U + +// Field: [27] SPARE11 +// +// ENUMs: +// ONE Bit is one +// ZERO Bit is 0 +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11 0x08000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_M 0x08000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_S 27U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_ONE 0x08000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_ZERO 0x00000000U + +// Field: [26] S1G20DBMMUX +// +// ENUMs: +// DISABLE Disable mux +// ENABLEN Enable mux +#define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX 0x04000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_M 0x04000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_S 26U +#define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_DISABLE 0x04000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_ENABLEN 0x00000000U + +// Field: [25] ADCDIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV 0x02000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_M 0x02000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_S 25U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_EN 0x02000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_DIS 0x00000000U + +// Field: [24] ENSYNTH +// +// ENUMs: +// EN Clock is enabled +// DIS Clock is disabled +#define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH 0x01000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_M 0x01000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_S 24U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_EN 0x01000000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_DIS 0x00000000U + +// Field: [23] TXPH18020DBMDIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV 0x00800000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_M 0x00800000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_S 23U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_EN 0x00800000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_DIS 0x00000000U + +// Field: [22] TXPH020DBMDIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV 0x00400000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_M 0x00400000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_S 22U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_EN 0x00400000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_DIS 0x00000000U + +// Field: [21] TXPH180DIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV 0x00200000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_M 0x00200000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_S 21U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_EN 0x00200000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_DIS 0x00000000U + +// Field: [20] TXPH0DIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV 0x00100000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_M 0x00100000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_S 20U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_EN 0x00100000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_DIS 0x00000000U + +// Field: [19] RXPH90DIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV 0x00080000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_M 0x00080000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_S 19U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_EN 0x00080000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_DIS 0x00000000U + +// Field: [18] RXPH0DIV +// +// ENUMs: +// EN Enable divider +// DIS Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV 0x00040000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_M 0x00040000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_S 18U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_EN 0x00040000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_DIS 0x00000000U + +// Field: [17] Spare1 +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1 0x00020000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_M 0x00020000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_S 17U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_ONE 0x00020000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_ZERO 0x00000000U + +// Field: [16] EN +// +// ENUMs: +// ON Enable divider +// OFF Disable divider +#define LRFDRFE32_DIVCTL_ANAISOCTL_EN 0x00010000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_EN_M 0x00010000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_EN_S 16U +#define LRFDRFE32_DIVCTL_ANAISOCTL_EN_ON 0x00010000U +#define LRFDRFE32_DIVCTL_ANAISOCTL_EN_OFF 0x00000000U + +// Field: [4] ADCDIGRSTN +// +// ENUMs: +// ACTIVE Don't reset +// RESET Reset +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN 0x00000010U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_M 0x00000010U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_S 4U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_ACTIVE 0x00000010U +#define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_RESET 0x00000000U + +// Field: [3] IFADC2SVTISO +// +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO 0x00000008U +#define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_M 0x00000008U +#define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_S 3U +#define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_ISOLATE 0x00000008U +#define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_CONNECT 0x00000000U + +// Field: [2] DIV2IFADCISO +// +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO 0x00000004U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_M 0x00000004U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_S 2U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_ISOLATE 0x00000004U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_CONNECT 0x00000000U + +// Field: [1] MTDC2SVTISO +// +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO 0x00000002U +#define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_M 0x00000002U +#define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_S 1U +#define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_ISOLATE 0x00000002U +#define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_CONNECT 0x00000000U + +// Field: [0] DIV2MTDCISO +// +// ENUMs: +// ISOLATE Isolate +// CONNECT Don't isolate +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO 0x00000001U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_M 0x00000001U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_S 0U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_ISOLATE 0x00000001U +#define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_CONNECT 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MAGNACC0_RXCTRL +// +//***************************************************************************** +// Field: [31:16] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_MAGNACC0_RXCTRL_VAL_W 16U +#define LRFDRFE32_MAGNACC0_RXCTRL_VAL_M 0xFFFF0000U +#define LRFDRFE32_MAGNACC0_RXCTRL_VAL_S 16U +#define LRFDRFE32_MAGNACC0_RXCTRL_VAL_ALLONES 0xFFFF0000U +#define LRFDRFE32_MAGNACC0_RXCTRL_VAL_ALLZEROS 0x00000000U + +// Field: [12] SPARE +// +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDRFE32_MAGNACC0_RXCTRL_SPARE 0x00001000U +#define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_M 0x00001000U +#define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_S 12U +#define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_ONE 0x00001000U +#define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_ZERO 0x00000000U + +// Field: [11:9] ATTN +// +// ENUMs: +// _21DB 21dB attenuation +// _18DB 18dB attenuation +// _15DB 15dB attenuation +// _12DB 12dB attenuation +// _9DB 9dB attenuation +// _6DB 6dB attenuation +// _3DB 3dB attenuation +// NOATT No attenuation +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_W 3U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_M 0x00000E00U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_S 9U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__21DB 0x00000E00U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__18DB 0x00000C00U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__15DB 0x00000A00U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__12DB 0x00000800U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__9DB 0x00000600U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__6DB 0x00000400U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__3DB 0x00000200U +#define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_NOATT 0x00000000U + +// Field: [8:4] IFAMPGC +// +// ENUMs: +// MAX Set IFAMP gain to MAX +// MIN3DB Set gain to MAX - 3 dB +// MIN6DB Set gain to MAX - 6 dB +// MIN9DB Set gain to MAX - 9 dB +// MIN12DB Set gain to MAX - 12 dB +// MIN15DB Set gain to MAX - 15 dB +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_W 5U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_M 0x000001F0U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_S 4U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MAX 0x000001F0U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN3DB 0x000000F0U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN6DB 0x00000070U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN9DB 0x00000030U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN12DB 0x00000010U +#define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN15DB 0x00000000U + +// Field: [3:0] LNAGAIN +// +// ENUMs: +// MAX Set gain to MAX +// MIN3DB Set gain to MAX - 3 dB +// MIN6DB Set gain to MAX - 6 dB +// MIN9DB Set gain to MAX - 9 dB +// MIN12DB Set gain to MAX - 12 dB +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_W 4U +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_M 0x0000000FU +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_S 0U +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MAX 0x0000000FU +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN3DB 0x00000007U +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN6DB 0x00000003U +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN9DB 0x00000001U +#define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN12DB 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_RSSI_MAGNACC1 +// +//***************************************************************************** +// Field: [23:16] RSSI_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_W 8U +#define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_M 0x00FF0000U +#define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_S 16U +#define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_ALLONES 0x00FF0000U +#define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_ALLZEROS 0x00000000U + +// Field: [15:0] MAGNACC1_VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_W 16U +#define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_M 0x0000FFFFU +#define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_S 0U +#define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_RFGAIN_RSSIMAX +// +//***************************************************************************** +// Field: [23:16] DBGAIN +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_W 8U +#define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_M 0x00FF0000U +#define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_S 16U +#define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_ALLONES 0x00FF0000U +#define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_ALLZEROS 0x00000000U + +// Field: [7:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_RFGAIN_RSSIMAX_VAL_W 8U +#define LRFDRFE32_RFGAIN_RSSIMAX_VAL_M 0x000000FFU +#define LRFDRFE32_RFGAIN_RSSIMAX_VAL_S 0U +#define LRFDRFE32_RFGAIN_RSSIMAX_VAL_ALLONES 0x000000FFU +#define LRFDRFE32_RFGAIN_RSSIMAX_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DIVSTA_IFADCSTAT +// +//***************************************************************************** +// Field: [16] STAT +// +// ENUMs: +// BUSY Serial divider is busy and result is not available +// yet +// IDLE Serial divider is idle +#define LRFDRFE32_DIVSTA_IFADCSTAT_STAT 0x00010000U +#define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_M 0x00010000U +#define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_S 16U +#define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_BUSY 0x00010000U +#define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_IDLE 0x00000000U + +// Field: [6:2] QUANTCALVAL +// +// ENUMs: +// COMP1 I comparator +// COMP0 Q Comparator +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_W 5U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_M 0x0000007CU +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_S 2U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_COMP1 0x00000004U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_COMP0 0x00000000U + +// Field: [1] QUANTCALDONE +// +// ENUMs: +// READY Calibration is complete +// NOT_READY Calibration is not finished +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE 0x00000002U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_M 0x00000002U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_S 1U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_READY 0x00000002U +#define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_NOT_READY 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DIVIDEND +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DIVIDEND_VAL_W 32U +#define LRFDRFE32_DIVIDEND_VAL_M 0xFFFFFFFFU +#define LRFDRFE32_DIVIDEND_VAL_S 0U +#define LRFDRFE32_DIVIDEND_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_DIVIDEND_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_DIVISOR +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_DIVISOR_VAL_W 32U +#define LRFDRFE32_DIVISOR_VAL_M 0xFFFFFFFFU +#define LRFDRFE32_DIVISOR_VAL_S 0U +#define LRFDRFE32_DIVISOR_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_DIVISOR_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_QUOTIENT +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_QUOTIENT_VAL_W 32U +#define LRFDRFE32_QUOTIENT_VAL_M 0xFFFFFFFFU +#define LRFDRFE32_QUOTIENT_VAL_S 0U +#define LRFDRFE32_QUOTIENT_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_QUOTIENT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_PRODUCT +// +//***************************************************************************** +// Field: [31:0] VAL +// +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDRFE32_PRODUCT_VAL_W 32U +#define LRFDRFE32_PRODUCT_VAL_M 0xFFFFFFFFU +#define LRFDRFE32_PRODUCT_VAL_S 0U +#define LRFDRFE32_PRODUCT_VAL_ALLONES 0x0000FFFFU +#define LRFDRFE32_PRODUCT_VAL_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MULTSTA +// +//***************************************************************************** +// Field: [0] STAT +// +// ENUMs: +// BUSY Multiplier is busy, result is not ready yet +// IDLE Multiplier is idle +#define LRFDRFE32_MULTSTA_STAT 0x00000001U +#define LRFDRFE32_MULTSTA_STAT_M 0x00000001U +#define LRFDRFE32_MULTSTA_STAT_S 0U +#define LRFDRFE32_MULTSTA_STAT_BUSY 0x00000001U +#define LRFDRFE32_MULTSTA_STAT_IDLE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRFE32_O_MULTCFG +// +//***************************************************************************** +// Field: [0] MODE +// +// ENUMs: +// SIGNED Multiplier assumes inputs are signed numbers +// UNSIGNED Multiplier assumes inputs are unsigned numbers +#define LRFDRFE32_MULTCFG_MODE 0x00000001U +#define LRFDRFE32_MULTCFG_MODE_M 0x00000001U +#define LRFDRFE32_MULTCFG_MODE_S 0U +#define LRFDRFE32_MULTCFG_MODE_SIGNED 0x00000001U +#define LRFDRFE32_MULTCFG_MODE_UNSIGNED 0x00000000U + + +#endif // __LRFDRFE32__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h index dd3413c9..97906a01 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdrxf.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* Filename: hw_lrfdrxf_h -****************************************************************************** -* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -******************************************************************************/ - -#ifndef __HW_LRFDRXF_H__ -#define __HW_LRFDRXF_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// LRFDRXF component -// -//***************************************************************************** -// Data to from RXFIFO -#define LRFDRXF_O_RXD 0x00000000U - -//***************************************************************************** -// -// Register: LRFDRXF_O_RXD -// -//***************************************************************************** -// Field: [31:0] DATA -// -// RX FIFO data. When written the register data is pushed to the RX FIFO. When -// read, data is popped from the RX FIFO. When writing or reading this register -// the access size will determine how many bytes are pushed to or popped from -// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the -// access being done. -#define LRFDRXF_RXD_DATA_W 32U -#define LRFDRXF_RXD_DATA_M 0xFFFFFFFFU -#define LRFDRXF_RXD_DATA_S 0U - - -#endif // __LRFDRXF__ +/****************************************************************************** +* Filename: hw_lrfdrxf_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDRXF_H__ +#define __HW_LRFDRXF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDRXF component +// +//***************************************************************************** +// Data to from RXFIFO +#define LRFDRXF_O_RXD 0x00000000U + +//***************************************************************************** +// +// Register: LRFDRXF_O_RXD +// +//***************************************************************************** +// Field: [31:0] DATA +// +// RX FIFO data. When written the register data is pushed to the RX FIFO. When +// read, data is popped from the RX FIFO. When writing or reading this register +// the access size will determine how many bytes are pushed to or popped from +// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the +// access being done. +#define LRFDRXF_RXD_DATA_W 32U +#define LRFDRXF_RXD_DATA_M 0xFFFFFFFFU +#define LRFDRXF_RXD_DATA_S 0U + + +#endif // __LRFDRXF__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfds2r.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfds2r.h new file mode 100644 index 00000000..6b6fc7fe --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfds2r.h @@ -0,0 +1,231 @@ +/****************************************************************************** +* Filename: hw_lrfds2r_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDS2R_H__ +#define __HW_LRFDS2R_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDS2R component +// +//***************************************************************************** +// Sample2RAM Config Register +#define LRFDS2R_O_CFG 0x00000000U + +// Sample2RAM Start Address Register +#define LRFDS2R_O_START 0x00000004U + +// Sample2RAM Stop Address Register +#define LRFDS2R_O_STOP 0x00000008U + +// Sample2RAM Status Register +#define LRFDS2R_O_STAT 0x0000000CU + +// Sample2RAM Trigger Register +#define LRFDS2R_O_TRIG 0x00000010U + +//***************************************************************************** +// +// Register: LRFDS2R_O_CFG +// +//***************************************************************************** +// Field: [5] LAST0 +// +// When this bit is enabled, then the S2R will write all zeros, whenever it +// tries to write the stop address (instead of the regular value) +// ENUMs: +// EN Writing all zeros to stop address is enabled +// DIS Writing all zeros to stop address is disabled +#define LRFDS2R_CFG_LAST0 0x00000020U +#define LRFDS2R_CFG_LAST0_M 0x00000020U +#define LRFDS2R_CFG_LAST0_S 5U +#define LRFDS2R_CFG_LAST0_EN 0x00000020U +#define LRFDS2R_CFG_LAST0_DIS 0x00000000U + +// Field: [4:3] TRIGMODE +// +// Trigger mode +// ENUMs: +// ONEVENT Trigger on event, i.e. fill memory area once, but +// wait for an event from the selected sample +// source. +// PERIODIC Periodic mode, i.e. fill memory area periodically, +// continuing at the start address after reaching +// the stop address, upon a manual trigger. +// ONESHOT One shot mode, i.e. fill memory area once, from +// start to stop address, upon a manual trigger. +#define LRFDS2R_CFG_TRIGMODE_W 2U +#define LRFDS2R_CFG_TRIGMODE_M 0x00000018U +#define LRFDS2R_CFG_TRIGMODE_S 3U +#define LRFDS2R_CFG_TRIGMODE_ONEVENT 0x00000010U +#define LRFDS2R_CFG_TRIGMODE_PERIODIC 0x00000008U +#define LRFDS2R_CFG_TRIGMODE_ONESHOT 0x00000000U + +// Field: [2:1] SEL +// +// Select sample source +// ENUMs: +// DECSTAGE Samples from decode stage mux. The sample source +// is selected in LRFDMDM:DEMDEBUG.DECSTAGEDEBUG +// register. +// FRONTEND Samples from frontend mux. The sample source is +// selected in LRFDMDM:DEMDEBUG.FRONTENDDEBUG +// register. +// ADCDIG Samples from ADCDIG. +// SYNTH Samples from frequency synthesizer's DTST +// interface. +#define LRFDS2R_CFG_SEL_W 2U +#define LRFDS2R_CFG_SEL_M 0x00000006U +#define LRFDS2R_CFG_SEL_S 1U +#define LRFDS2R_CFG_SEL_DECSTAGE 0x00000006U +#define LRFDS2R_CFG_SEL_FRONTEND 0x00000004U +#define LRFDS2R_CFG_SEL_ADCDIG 0x00000002U +#define LRFDS2R_CFG_SEL_SYNTH 0x00000000U + +// Field: [0] CTL +// +// Sample2RAM module enable +// ENUMs: +// EN Enabled +// DIS Not enabled +#define LRFDS2R_CFG_CTL 0x00000001U +#define LRFDS2R_CFG_CTL_M 0x00000001U +#define LRFDS2R_CFG_CTL_S 0U +#define LRFDS2R_CFG_CTL_EN 0x00000001U +#define LRFDS2R_CFG_CTL_DIS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDS2R_O_START +// +//***************************************************************************** +// Field: [12:0] ADDR +// +// Memory start address for where to dump the samples. The address is word +// oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, +// then S2RRAM and then BUFRAM. Also note that S2R has write priority to the +// RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while +// it is running may be unreliable (no arbitration/stall implemented), and +// should be avoided. +// +// 0 -> 1023 : MCERAM +// 1024 -> 2047 : RFERAM +// 2048 -> 3071 : PBERAM +// 3072 -> 4095 : S2RRAM +// 4096 -> 4479 : BUFRAM +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDS2R_START_ADDR_W 13U +#define LRFDS2R_START_ADDR_M 0x00001FFFU +#define LRFDS2R_START_ADDR_S 0U +#define LRFDS2R_START_ADDR_ALLONES 0x00001FFFU +#define LRFDS2R_START_ADDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDS2R_O_STOP +// +//***************************************************************************** +// Field: [12:0] ADDR +// +// Memory start address for where to dump the samples. The address is word +// oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, +// then S2RRAM and then BUFRAM. Also note that S2R has write priority to the +// RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while +// it is running may be unreliable (no arbitration/stall implemented), and +// should be avoided. +// +// 0 -> 1023 : MCERAM +// 1024 -> 2047 : RFERAM +// 2048 -> 3071 : PBERAM +// 3072 -> 4095 : S2RRAM +// 4096 -> 4479 : BUFRAM +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDS2R_STOP_ADDR_W 13U +#define LRFDS2R_STOP_ADDR_M 0x00001FFFU +#define LRFDS2R_STOP_ADDR_S 0U +#define LRFDS2R_STOP_ADDR_ALLONES 0x00001FFFU +#define LRFDS2R_STOP_ADDR_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDS2R_O_STAT +// +//***************************************************************************** +// Field: [27:16] ADDRCNT +// +// Current address counter value +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDS2R_STAT_ADDRCNT_W 12U +#define LRFDS2R_STAT_ADDRCNT_M 0x0FFF0000U +#define LRFDS2R_STAT_ADDRCNT_S 16U +#define LRFDS2R_STAT_ADDRCNT_ALLONES 0x0FFF0000U +#define LRFDS2R_STAT_ADDRCNT_ALLZEROS 0x00000000U + +// Field: [0] RUNNING +// +// S2R running status +// ENUMs: +// TRUE Running +// FALSE Not running +#define LRFDS2R_STAT_RUNNING 0x00000001U +#define LRFDS2R_STAT_RUNNING_M 0x00000001U +#define LRFDS2R_STAT_RUNNING_S 0U +#define LRFDS2R_STAT_RUNNING_TRUE 0x00000001U +#define LRFDS2R_STAT_RUNNING_FALSE 0x00000000U + +//***************************************************************************** +// +// Register: LRFDS2R_O_TRIG +// +//***************************************************************************** +// Field: [0] TRIG +// +// Trigger a new sample capture (or arm it if the trigger mode is trigger on +// event) +// ENUMs: +// ARM Trigger capture or arm module +// NO_EFFECT No effect +#define LRFDS2R_TRIG_TRIG 0x00000001U +#define LRFDS2R_TRIG_TRIG_M 0x00000001U +#define LRFDS2R_TRIG_TRIG_S 0U +#define LRFDS2R_TRIG_TRIG_ARM 0x00000001U +#define LRFDS2R_TRIG_TRIG_NO_EFFECT 0x00000000U + + +#endif // __LRFDS2R__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtrc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtrc.h new file mode 100644 index 00000000..f887b7a9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtrc.h @@ -0,0 +1,429 @@ +/****************************************************************************** +* Filename: hw_lrfdtrc_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDTRC_H__ +#define __HW_LRFDTRC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDTRC component +// +//***************************************************************************** +// Tracer Configuration +#define LRFDTRC_O_CFG 0x00000000U + +// Channel 1 Command Register +#define LRFDTRC_O_CH1CMD 0x00000004U + +// Channel 2 Command Register +#define LRFDTRC_O_CH2CMD 0x00000008U + +// Channel 3 Command Register +#define LRFDTRC_O_CH3CMD 0x0000000CU + +// Channel 1 Parameter 0/1 Register +#define LRFDTRC_O_CH1PAR01 0x00000014U + +// Channel 2 Parameter 0/1 Register +#define LRFDTRC_O_CH2PAR01 0x00000018U + +// Channel 3 Parameter 0/1 Register +#define LRFDTRC_O_CH3PAR01 0x0000001CU + +// Channel 1 Parameter 2/3 Register +#define LRFDTRC_O_CH1PAR23 0x00000024U + +// Channel 2 Parameter 2/3 Register +#define LRFDTRC_O_CH2PAR23 0x00000028U + +// Channel 3 Parameter 2/3 Register +#define LRFDTRC_O_CH3PAR23 0x0000002CU + +//***************************************************************************** +// +// Register: LRFDTRC_O_CFG +// +//***************************************************************************** +// Field: [8:7] PRESCAL +// +// Data rate prescaler for bit clock of the serialized data +// ENUMs: +// DIV4 Divide clock by 4 +// DIV3 Divide clock by 3 +// DIV2 Divide clock by 2 +// DIV1 Divide clock by 1 +#define LRFDTRC_CFG_PRESCAL_W 2U +#define LRFDTRC_CFG_PRESCAL_M 0x00000180U +#define LRFDTRC_CFG_PRESCAL_S 7U +#define LRFDTRC_CFG_PRESCAL_DIV4 0x00000180U +#define LRFDTRC_CFG_PRESCAL_DIV3 0x00000100U +#define LRFDTRC_CFG_PRESCAL_DIV2 0x00000080U +#define LRFDTRC_CFG_PRESCAL_DIV1 0x00000000U + +// Field: [6] TSCLR +// +// Writing 1 to this bit clears the TX timer +// ENUMs: +// ONE The bit is 1 +// ZERO The bit is 0 +#define LRFDTRC_CFG_TSCLR 0x00000040U +#define LRFDTRC_CFG_TSCLR_M 0x00000040U +#define LRFDTRC_CFG_TSCLR_S 6U +#define LRFDTRC_CFG_TSCLR_ONE 0x00000040U +#define LRFDTRC_CFG_TSCLR_ZERO 0x00000000U + +// Field: [5] TSEN +// +// Enables the Timestamp +// ENUMs: +// ON The bit is 1 +// OFF The bit is 0 +#define LRFDTRC_CFG_TSEN 0x00000020U +#define LRFDTRC_CFG_TSEN_M 0x00000020U +#define LRFDTRC_CFG_TSEN_S 5U +#define LRFDTRC_CFG_TSEN_ON 0x00000020U +#define LRFDTRC_CFG_TSEN_OFF 0x00000000U + +// Field: [4:3] CH3EN +// +// Enables CH3 traces +// ENUMs: +// TOPSM Enabled with MCE, MCO and CCE backdoor access +// access +// NORM Enabled in normal mode. Data from bus slave +// interface. +// OFF Disabled. No tracer transfer due to CH3 events +#define LRFDTRC_CFG_CH3EN_W 2U +#define LRFDTRC_CFG_CH3EN_M 0x00000018U +#define LRFDTRC_CFG_CH3EN_S 3U +#define LRFDTRC_CFG_CH3EN_TOPSM 0x00000010U +#define LRFDTRC_CFG_CH3EN_NORM 0x00000008U +#define LRFDTRC_CFG_CH3EN_OFF 0x00000000U + +// Field: [2:1] CH2EN +// +// Enables CH2 traces +// ENUMs: +// TOPSM Enabled with PBE and RFE backdoor access access +// NORM Enabled in normal mode. Data from bus slave +// interface. +// OFF Disabled. No tracer transfer due to CH2 events +#define LRFDTRC_CFG_CH2EN_W 2U +#define LRFDTRC_CFG_CH2EN_M 0x00000006U +#define LRFDTRC_CFG_CH2EN_S 1U +#define LRFDTRC_CFG_CH2EN_TOPSM 0x00000004U +#define LRFDTRC_CFG_CH2EN_NORM 0x00000002U +#define LRFDTRC_CFG_CH2EN_OFF 0x00000000U + +// Field: [0] CH1EN +// +// Enables CH1 traces +// ENUMs: +// NORM Enabled in normal mode. Data from bus slave +// interface. +// OFF Disabled. No tracer transfer due to CH1 events +#define LRFDTRC_CFG_CH1EN 0x00000001U +#define LRFDTRC_CFG_CH1EN_M 0x00000001U +#define LRFDTRC_CFG_CH1EN_S 0U +#define LRFDTRC_CFG_CH1EN_NORM 0x00000001U +#define LRFDTRC_CFG_CH1EN_OFF 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH1CMD +// +//***************************************************************************** +// Field: [15:8] PKTHDR +// +// Header Byte. Reverts back to 0 when ready to transmit. A Write starts a +// transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1CMD_PKTHDR_W 8U +#define LRFDTRC_CH1CMD_PKTHDR_M 0x0000FF00U +#define LRFDTRC_CH1CMD_PKTHDR_S 8U +#define LRFDTRC_CH1CMD_PKTHDR_ALLONES 0x0000FF00U +#define LRFDTRC_CH1CMD_PKTHDR_ALLZEROS 0x00000000U + +// Field: [2:0] PARCNT +// +// Number of parameters to transmit. Reverts back to 0 when ready to transmit. +// A Write starts a transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1CMD_PARCNT_W 3U +#define LRFDTRC_CH1CMD_PARCNT_M 0x00000007U +#define LRFDTRC_CH1CMD_PARCNT_S 0U +#define LRFDTRC_CH1CMD_PARCNT_ALLONES 0x00000007U +#define LRFDTRC_CH1CMD_PARCNT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH2CMD +// +//***************************************************************************** +// Field: [15:8] PKTHDR +// +// Header Byte. Reverts back to 0 when ready to transmit. A Write starts a +// transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2CMD_PKTHDR_W 8U +#define LRFDTRC_CH2CMD_PKTHDR_M 0x0000FF00U +#define LRFDTRC_CH2CMD_PKTHDR_S 8U +#define LRFDTRC_CH2CMD_PKTHDR_ALLONES 0x0000FF00U +#define LRFDTRC_CH2CMD_PKTHDR_ALLZEROS 0x00000000U + +// Field: [2:0] PARCNT +// +// Number of parameters to transmit. Reverts back to 0 when ready to transmit. +// A Write starts a transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2CMD_PARCNT_W 3U +#define LRFDTRC_CH2CMD_PARCNT_M 0x00000007U +#define LRFDTRC_CH2CMD_PARCNT_S 0U +#define LRFDTRC_CH2CMD_PARCNT_ALLONES 0x00000007U +#define LRFDTRC_CH2CMD_PARCNT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH3CMD +// +//***************************************************************************** +// Field: [15:8] PKTHDR +// +// Header Byte. Reverts back to 0 when ready to transmit. A Write starts a +// transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3CMD_PKTHDR_W 8U +#define LRFDTRC_CH3CMD_PKTHDR_M 0x0000FF00U +#define LRFDTRC_CH3CMD_PKTHDR_S 8U +#define LRFDTRC_CH3CMD_PKTHDR_ALLONES 0x0000FF00U +#define LRFDTRC_CH3CMD_PKTHDR_ALLZEROS 0x00000000U + +// Field: [2:0] PARCNT +// +// Number of parameters to transmit. Reverts back to 0 when ready to transmit. +// A Write starts a transmission sequence. +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3CMD_PARCNT_W 3U +#define LRFDTRC_CH3CMD_PARCNT_M 0x00000007U +#define LRFDTRC_CH3CMD_PARCNT_S 0U +#define LRFDTRC_CH3CMD_PARCNT_ALLONES 0x00000007U +#define LRFDTRC_CH3CMD_PARCNT_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH1PAR01 +// +//***************************************************************************** +// Field: [31:16] PAR1 +// +// Parameter 1 for Channel 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1PAR01_PAR1_W 16U +#define LRFDTRC_CH1PAR01_PAR1_M 0xFFFF0000U +#define LRFDTRC_CH1PAR01_PAR1_S 16U +#define LRFDTRC_CH1PAR01_PAR1_ALLONES 0xFFFF0000U +#define LRFDTRC_CH1PAR01_PAR1_ALLZEROS 0x00000000U + +// Field: [15:0] PAR0 +// +// Parameter 0 for Channel 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1PAR01_PAR0_W 16U +#define LRFDTRC_CH1PAR01_PAR0_M 0x0000FFFFU +#define LRFDTRC_CH1PAR01_PAR0_S 0U +#define LRFDTRC_CH1PAR01_PAR0_ALLONES 0x0000FFFFU +#define LRFDTRC_CH1PAR01_PAR0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH2PAR01 +// +//***************************************************************************** +// Field: [31:16] PAR1 +// +// Parameter 1 for Channel 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2PAR01_PAR1_W 16U +#define LRFDTRC_CH2PAR01_PAR1_M 0xFFFF0000U +#define LRFDTRC_CH2PAR01_PAR1_S 16U +#define LRFDTRC_CH2PAR01_PAR1_ALLONES 0xFFFF0000U +#define LRFDTRC_CH2PAR01_PAR1_ALLZEROS 0x00000000U + +// Field: [15:0] PAR0 +// +// Parameter 0 for Channel 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2PAR01_PAR0_W 16U +#define LRFDTRC_CH2PAR01_PAR0_M 0x0000FFFFU +#define LRFDTRC_CH2PAR01_PAR0_S 0U +#define LRFDTRC_CH2PAR01_PAR0_ALLONES 0x0000FFFFU +#define LRFDTRC_CH2PAR01_PAR0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH3PAR01 +// +//***************************************************************************** +// Field: [31:16] PAR1 +// +// Parameter 1 for Channel 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3PAR01_PAR1_W 16U +#define LRFDTRC_CH3PAR01_PAR1_M 0xFFFF0000U +#define LRFDTRC_CH3PAR01_PAR1_S 16U +#define LRFDTRC_CH3PAR01_PAR1_ALLONES 0xFFFF0000U +#define LRFDTRC_CH3PAR01_PAR1_ALLZEROS 0x00000000U + +// Field: [15:0] PAR0 +// +// Parameter 0 for Channel 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3PAR01_PAR0_W 16U +#define LRFDTRC_CH3PAR01_PAR0_M 0x0000FFFFU +#define LRFDTRC_CH3PAR01_PAR0_S 0U +#define LRFDTRC_CH3PAR01_PAR0_ALLONES 0x0000FFFFU +#define LRFDTRC_CH3PAR01_PAR0_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH1PAR23 +// +//***************************************************************************** +// Field: [31:16] PAR3 +// +// Parameter 3 for Channel 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1PAR23_PAR3_W 16U +#define LRFDTRC_CH1PAR23_PAR3_M 0xFFFF0000U +#define LRFDTRC_CH1PAR23_PAR3_S 16U +#define LRFDTRC_CH1PAR23_PAR3_ALLONES 0xFFFF0000U +#define LRFDTRC_CH1PAR23_PAR3_ALLZEROS 0x00000000U + +// Field: [15:0] PAR2 +// +// Parameter 2 for Channel 1 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH1PAR23_PAR2_W 16U +#define LRFDTRC_CH1PAR23_PAR2_M 0x0000FFFFU +#define LRFDTRC_CH1PAR23_PAR2_S 0U +#define LRFDTRC_CH1PAR23_PAR2_ALLONES 0x0000FFFFU +#define LRFDTRC_CH1PAR23_PAR2_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH2PAR23 +// +//***************************************************************************** +// Field: [31:16] PAR3 +// +// Parameter 3 for Channel 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2PAR23_PAR3_W 16U +#define LRFDTRC_CH2PAR23_PAR3_M 0xFFFF0000U +#define LRFDTRC_CH2PAR23_PAR3_S 16U +#define LRFDTRC_CH2PAR23_PAR3_ALLONES 0xFFFF0000U +#define LRFDTRC_CH2PAR23_PAR3_ALLZEROS 0x00000000U + +// Field: [15:0] PAR2 +// +// Parameter 2 for Channel 2 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH2PAR23_PAR2_W 16U +#define LRFDTRC_CH2PAR23_PAR2_M 0x0000FFFFU +#define LRFDTRC_CH2PAR23_PAR2_S 0U +#define LRFDTRC_CH2PAR23_PAR2_ALLONES 0x0000FFFFU +#define LRFDTRC_CH2PAR23_PAR2_ALLZEROS 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTRC_O_CH3PAR23 +// +//***************************************************************************** +// Field: [31:16] PAR3 +// +// Parameter 3 for Channel 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3PAR23_PAR3_W 16U +#define LRFDTRC_CH3PAR23_PAR3_M 0xFFFF0000U +#define LRFDTRC_CH3PAR23_PAR3_S 16U +#define LRFDTRC_CH3PAR23_PAR3_ALLONES 0xFFFF0000U +#define LRFDTRC_CH3PAR23_PAR3_ALLZEROS 0x00000000U + +// Field: [15:0] PAR2 +// +// Parameter 2 for Channel 3 +// ENUMs: +// ALLONES All the bits are 1 +// ALLZEROS All the bits are 0 +#define LRFDTRC_CH3PAR23_PAR2_W 16U +#define LRFDTRC_CH3PAR23_PAR2_M 0x0000FFFFU +#define LRFDTRC_CH3PAR23_PAR2_S 0U +#define LRFDTRC_CH3PAR23_PAR2_ALLONES 0x0000FFFFU +#define LRFDTRC_CH3PAR23_PAR2_ALLZEROS 0x00000000U + + +#endif // __LRFDTRC__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h index d6756c39..a405ee52 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/hw_lrfdtxf.h @@ -1,62 +1,62 @@ -/****************************************************************************** -* Filename: hw_lrfdtxf_h -****************************************************************************** -* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -******************************************************************************/ - -#ifndef __HW_LRFDTXF_H__ -#define __HW_LRFDTXF_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// LRFDTXF component -// -//***************************************************************************** -// Data to from TXFIFO -#define LRFDTXF_O_TXD 0x00000000U - -//***************************************************************************** -// -// Register: LRFDTXF_O_TXD -// -//***************************************************************************** -// Field: [31:0] DATA -// -// TX FIFO data. When written the register data is pushed to the TX FIFO. When -// read, data is popped from the TX FIFO. When writing or reading this register -// the access size will determine how many bytes are pushed to or popped from -// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the -// access being done. -#define LRFDTXF_TXD_DATA_W 32U -#define LRFDTXF_TXD_DATA_M 0xFFFFFFFFU -#define LRFDTXF_TXD_DATA_S 0U - - -#endif // __LRFDTXF__ +/****************************************************************************** +* Filename: hw_lrfdtxf_h +****************************************************************************** +* Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __HW_LRFDTXF_H__ +#define __HW_LRFDTXF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// LRFDTXF component +// +//***************************************************************************** +// Data to from TXFIFO +#define LRFDTXF_O_TXD 0x00000000U + +//***************************************************************************** +// +// Register: LRFDTXF_O_TXD +// +//***************************************************************************** +// Field: [31:0] DATA +// +// TX FIFO data. When written the register data is pushed to the TX FIFO. When +// read, data is popped from the TX FIFO. When writing or reading this register +// the access size will determine how many bytes are pushed to or popped from +// the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the +// access being done. +#define LRFDTXF_TXD_DATA_W 32U +#define LRFDTXF_TXD_DATA_M 0xFFFFFFFFU +#define LRFDTXF_TXD_DATA_S 0U + + +#endif // __LRFDTXF__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_ram_regs.h new file mode 100644 index 00000000..f47ddcbc --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_ram_regs.h @@ -0,0 +1,4504 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:08:59 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5 +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 0b79d4d13cc055db992ad8a96ee84cae10ff93ac +// +// =========================================================================== + + +#ifndef __PBE_BLE5_RAM_REGS_H +#define __PBE_BLE5_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// +#define PBE_BLE5_RAM_O_PHY 0x00000020U + +// +#define PBE_BLE5_RAM_O_PRETXIFS500K 0x00000022U + +// +#define PBE_BLE5_RAM_O_PRETXIFS 0x00000024U + +// +#define PBE_BLE5_RAM_O_PRERXIFS 0x00000026U + +// +#define PBE_BLE5_RAM_O_RXTIMEOUT 0x00000028U + +// +#define PBE_BLE5_RAM_O_SYNTHCALTIMEOUT 0x0000002AU + +// +#define PBE_BLE5_RAM_O_RECALTIMEOUT 0x0000002CU + +// Scanner and Intor use both. Advertiser uses only RPAMODE_PEERADR, it shall be unaffected by RPAMODE_OWNADR. +#define PBE_BLE5_RAM_O_RPAMODE 0x0000002EU + +// Configure Advertiser ENDCAUSE status. +#define PBE_BLE5_RAM_O_RPACONNECT 0x00000030U + +// Configure FIFO usage +#define PBE_BLE5_RAM_O_FIFOCFG 0x00000032U + +// Status for the received packet, appended in the RX FIFO depending on FIFOCFG. +#define PBE_BLE5_RAM_O_STATUSBYTE 0x00000034U + +// +#define PBE_BLE5_RAM_O_NAKHUB 0x00000036U + +// Initialization for the whitener, if 0 the whitener is not used +#define PBE_BLE5_RAM_O_WHITEINIT 0x00000038U + +// Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. It has to be equal or greater. +#define PBE_BLE5_RAM_O_EXTRABYTES 0x0000003AU + +// CRC initialization value Random by Link Layer for Data PDU, 0x555555 for Adv PDU. +#define PBE_BLE5_RAM_O_CRCINITL 0x0000003CU + +// CRC initialization value Random by Link Layer for Data PDU, 0x555555 for Adv PDU. +#define PBE_BLE5_RAM_O_CRCINITH 0x0000003EU + +// Sequencing status +#define PBE_BLE5_RAM_O_SEQSTAT 0x00000040U + +// Back off count +#define PBE_BLE5_RAM_O_BACKOFFCNT 0x00000042U + +// Configure scanner +#define PBE_BLE5_RAM_O_SCANCFG 0x00000044U + +// Extended advertising configuration +#define PBE_BLE5_RAM_O_AECFG 0x00000046U + +// Temporary storage for AE flags +#define PBE_BLE5_RAM_O_AETMP 0x00000048U + +// Temporary storage for RT7_EXT_LENGTH +#define PBE_BLE5_RAM_O_EXTLENTMP 0x0000004AU + +// WinOffset parameter to divide by 4 and write in CONNECT_IND message. This value will be decremented at each systimer event x until transmission of a CONNECT_REQ has started. If the value is decremented from 4, it is set to WINMOD. +#define PBE_BLE5_RAM_O_WINOFFSET 0x0000004CU + +// +#define PBE_BLE5_RAM_O_WINMOD 0x0000004EU + +// Maximum number of payload bytes in a packet. Checked in OP_BLE_TX_RAW and OP_BLE_RX_RAW. PDU TYPE specific lengths are confirmed in addition. +#define PBE_BLE5_RAM_O_MAXLEN 0x00000050U + +// Filter policies +#define PBE_BLE5_RAM_O_FILTPOLICY 0x00000052U + +// Address modes +#define PBE_BLE5_RAM_O_OWNADRTYPE 0x00000054U + +// Address modes +#define PBE_BLE5_RAM_O_PEERADRTYPE 0x00000056U + +// Low part of own address, 16 bits +#define PBE_BLE5_RAM_O_OWNADRL 0x00000058U + +// Middle part of own address, 16 bits +#define PBE_BLE5_RAM_O_OWNADRM 0x0000005AU + +// High part of own address, 16 bits +#define PBE_BLE5_RAM_O_OWNADRH 0x0000005CU + +// +#define PBE_BLE5_RAM_O_TMPADRL 0x0000005EU + +// +#define PBE_BLE5_RAM_O_TMPADRM 0x00000060U + +// +#define PBE_BLE5_RAM_O_TMPADRH 0x00000062U + +// Low part of peer address +#define PBE_BLE5_RAM_O_PEERADRL 0x00000064U + +// Middle part of peer address +#define PBE_BLE5_RAM_O_PEERADRM 0x00000066U + +// High part of peer address +#define PBE_BLE5_RAM_O_PEERADRH 0x00000068U + +// +#define PBE_BLE5_RAM_O_NTXDONE 0x0000006AU + +// +#define PBE_BLE5_RAM_O_NTXACK 0x0000006CU + +// +#define PBE_BLE5_RAM_O_NTXCTLACK 0x0000006EU + +// +#define PBE_BLE5_RAM_O_NTXCTL 0x00000070U + +// +#define PBE_BLE5_RAM_O_NTXRETRANS 0x00000072U + +// +#define PBE_BLE5_RAM_O_NRXNOK 0x00000074U + +// +#define PBE_BLE5_RAM_O_NRXIGNORED 0x00000076U + +// +#define PBE_BLE5_RAM_O_NRXEMPTY 0x00000078U + +// +#define PBE_BLE5_RAM_O_NRXFIFOFULL 0x0000007AU + +// +#define PBE_BLE5_RAM_O_NRXOK 0x0000007CU + +// +#define PBE_BLE5_RAM_O_NTX 0x0000007EU + +// +#define PBE_BLE5_RAM_O_NRXCTL 0x00000080U + +// +#define PBE_BLE5_RAM_O_NRXCTLACK 0x00000082U + +// +#define PBE_BLE5_RAM_O_LASTRSSI 0x00000084U + +// +#define PBE_BLE5_RAM_O_FIRSTRXTIMEOUT 0x00000086U + +// +#define PBE_BLE5_RAM_O_LASTTIMESTAMPL 0x00000088U + +// +#define PBE_BLE5_RAM_O_LASTTIMESTAMPH 0x0000008AU + +// +#define PBE_BLE5_RAM_O_MDCFG 0x0000008CU + +// Configure Advertiser Task Behavior. This configuration determines the control flow of the advertiser command(OP_BLE_ADV) on the PBE_API. More than one bit may be high at the same time. +#define PBE_BLE5_RAM_O_ADVCFG 0x0000008EU + +// Temporary register for storing RSSI +#define PBE_BLE5_RAM_O_TMPRSSI 0x00000090U + +// +#define PBE_BLE5_RAM_O_FIRSTTIMESTAMPL 0x00000094U + +// +#define PBE_BLE5_RAM_O_FIRSTTIMESTAMPH 0x00000096U + +// +#define PBE_BLE5_RAM_O_FL1RESULT 0x00000098U + +// +#define PBE_BLE5_RAM_O_FL1MASK 0x0000009AU + +// +#define PBE_BLE5_RAM_O_FL2RESULT 0x0000009CU + +// +#define PBE_BLE5_RAM_O_FL2MASK 0x0000009EU + +// +#define PBE_BLE5_RAM_O_FLSTAT 0x000000A0U + +// +#define PBE_BLE5_RAM_O_TMPATYPE 0x000000A2U + +// +#define PBE_BLE5_RAM_O_PATTERN 0x000000A4U + +// +#define PBE_BLE5_RAM_O_RFINTERVAL 0x000000A6U + +// +#define PBE_BLE5_RAM_O_NTXTARGET 0x000000A8U + +// combined tx/rx/fs configuration +#define PBE_BLE5_RAM_O_OPCFG 0x000000AAU + +// +#define PBE_BLE5_RAM_O_FL1INFO0 0x000000ACU + +// +#define PBE_BLE5_RAM_O_FL1ADRL0 0x000000AEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM0 0x000000B0U + +// +#define PBE_BLE5_RAM_O_FL1ADRH0 0x000000B2U + +// +#define PBE_BLE5_RAM_O_FL1INFO1 0x000000B4U + +// +#define PBE_BLE5_RAM_O_FL1ADRL1 0x000000B6U + +// +#define PBE_BLE5_RAM_O_FL1ADRM1 0x000000B8U + +// +#define PBE_BLE5_RAM_O_FL1ADRH1 0x000000BAU + +// +#define PBE_BLE5_RAM_O_FL1INFO2 0x000000BCU + +// +#define PBE_BLE5_RAM_O_FL1ADRL2 0x000000BEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM2 0x000000C0U + +// +#define PBE_BLE5_RAM_O_FL1ADRH2 0x000000C2U + +// +#define PBE_BLE5_RAM_O_FL1INFO3 0x000000C4U + +// +#define PBE_BLE5_RAM_O_FL1ADRL3 0x000000C6U + +// +#define PBE_BLE5_RAM_O_FL1ADRM3 0x000000C8U + +// +#define PBE_BLE5_RAM_O_FL1ADRH3 0x000000CAU + +// +#define PBE_BLE5_RAM_O_FL1INFO4 0x000000CCU + +// +#define PBE_BLE5_RAM_O_FL1ADRL4 0x000000CEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM4 0x000000D0U + +// +#define PBE_BLE5_RAM_O_FL1ADRH4 0x000000D2U + +// +#define PBE_BLE5_RAM_O_FL1INFO5 0x000000D4U + +// +#define PBE_BLE5_RAM_O_FL1ADRL5 0x000000D6U + +// +#define PBE_BLE5_RAM_O_FL1ADRM5 0x000000D8U + +// +#define PBE_BLE5_RAM_O_FL1ADRH5 0x000000DAU + +// +#define PBE_BLE5_RAM_O_FL1INFO6 0x000000DCU + +// +#define PBE_BLE5_RAM_O_FL1ADRL6 0x000000DEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM6 0x000000E0U + +// +#define PBE_BLE5_RAM_O_FL1ADRH6 0x000000E2U + +// +#define PBE_BLE5_RAM_O_FL1INFO7 0x000000E4U + +// +#define PBE_BLE5_RAM_O_FL1ADRL7 0x000000E6U + +// +#define PBE_BLE5_RAM_O_FL1ADRM7 0x000000E8U + +// +#define PBE_BLE5_RAM_O_FL1ADRH7 0x000000EAU + +// +#define PBE_BLE5_RAM_O_FL1INFO8 0x000000ECU + +// +#define PBE_BLE5_RAM_O_FL1ADRL8 0x000000EEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM8 0x000000F0U + +// +#define PBE_BLE5_RAM_O_FL1ADRH8 0x000000F2U + +// +#define PBE_BLE5_RAM_O_FL1INFO9 0x000000F4U + +// +#define PBE_BLE5_RAM_O_FL1ADRL9 0x000000F6U + +// +#define PBE_BLE5_RAM_O_FL1ADRM9 0x000000F8U + +// +#define PBE_BLE5_RAM_O_FL1ADRH9 0x000000FAU + +// +#define PBE_BLE5_RAM_O_FL1INFO10 0x000000FCU + +// +#define PBE_BLE5_RAM_O_FL1ADRL10 0x000000FEU + +// +#define PBE_BLE5_RAM_O_FL1ADRM10 0x00000100U + +// +#define PBE_BLE5_RAM_O_FL1ADRH10 0x00000102U + +// +#define PBE_BLE5_RAM_O_FL1INFO11 0x00000104U + +// +#define PBE_BLE5_RAM_O_FL1ADRL11 0x00000106U + +// +#define PBE_BLE5_RAM_O_FL1ADRM11 0x00000108U + +// +#define PBE_BLE5_RAM_O_FL1ADRH11 0x0000010AU + +// +#define PBE_BLE5_RAM_O_FL1INFO12 0x0000010CU + +// +#define PBE_BLE5_RAM_O_FL1ADRL12 0x0000010EU + +// +#define PBE_BLE5_RAM_O_FL1ADRM12 0x00000110U + +// +#define PBE_BLE5_RAM_O_FL1ADRH12 0x00000112U + +// +#define PBE_BLE5_RAM_O_FL1INFO13 0x00000114U + +// +#define PBE_BLE5_RAM_O_FL1ADRL13 0x00000116U + +// +#define PBE_BLE5_RAM_O_FL1ADRM13 0x00000118U + +// +#define PBE_BLE5_RAM_O_FL1ADRH13 0x0000011AU + +// +#define PBE_BLE5_RAM_O_FL1INFO14 0x0000011CU + +// +#define PBE_BLE5_RAM_O_FL1ADRL14 0x0000011EU + +// +#define PBE_BLE5_RAM_O_FL1ADRM14 0x00000120U + +// +#define PBE_BLE5_RAM_O_FL1ADRH14 0x00000122U + +// +#define PBE_BLE5_RAM_O_FL1INFO15 0x00000124U + +// +#define PBE_BLE5_RAM_O_FL1ADRL15 0x00000126U + +// +#define PBE_BLE5_RAM_O_FL1ADRM15 0x00000128U + +// +#define PBE_BLE5_RAM_O_FL1ADRH15 0x0000012AU + +// +#define PBE_BLE5_RAM_O_FL2INFO0 0x0000012CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL0 0x0000012EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM0 0x00000130U + +// +#define PBE_BLE5_RAM_O_FL2ADRH0 0x00000132U + +// +#define PBE_BLE5_RAM_O_FL2INFO1 0x00000134U + +// +#define PBE_BLE5_RAM_O_FL2ADRL1 0x00000136U + +// +#define PBE_BLE5_RAM_O_FL2ADRM1 0x00000138U + +// +#define PBE_BLE5_RAM_O_FL2ADRH1 0x0000013AU + +// +#define PBE_BLE5_RAM_O_FL2INFO2 0x0000013CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL2 0x0000013EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM2 0x00000140U + +// +#define PBE_BLE5_RAM_O_FL2ADRH2 0x00000142U + +// +#define PBE_BLE5_RAM_O_FL2INFO3 0x00000144U + +// +#define PBE_BLE5_RAM_O_FL2ADRL3 0x00000146U + +// +#define PBE_BLE5_RAM_O_FL2ADRM3 0x00000148U + +// +#define PBE_BLE5_RAM_O_FL2ADRH3 0x0000014AU + +// +#define PBE_BLE5_RAM_O_FL2INFO4 0x0000014CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL4 0x0000014EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM4 0x00000150U + +// +#define PBE_BLE5_RAM_O_FL2ADRH4 0x00000152U + +// +#define PBE_BLE5_RAM_O_FL2INFO5 0x00000154U + +// +#define PBE_BLE5_RAM_O_FL2ADRL5 0x00000156U + +// +#define PBE_BLE5_RAM_O_FL2ADRM5 0x00000158U + +// +#define PBE_BLE5_RAM_O_FL2ADRH5 0x0000015AU + +// +#define PBE_BLE5_RAM_O_FL2INFO6 0x0000015CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL6 0x0000015EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM6 0x00000160U + +// +#define PBE_BLE5_RAM_O_FL2ADRH6 0x00000162U + +// +#define PBE_BLE5_RAM_O_FL2INFO7 0x00000164U + +// +#define PBE_BLE5_RAM_O_FL2ADRL7 0x00000166U + +// +#define PBE_BLE5_RAM_O_FL2ADRM7 0x00000168U + +// +#define PBE_BLE5_RAM_O_FL2ADRH7 0x0000016AU + +// +#define PBE_BLE5_RAM_O_FL2INFO8 0x0000016CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL8 0x0000016EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM8 0x00000170U + +// +#define PBE_BLE5_RAM_O_FL2ADRH8 0x00000172U + +// +#define PBE_BLE5_RAM_O_FL2INFO9 0x00000174U + +// +#define PBE_BLE5_RAM_O_FL2ADRL9 0x00000176U + +// +#define PBE_BLE5_RAM_O_FL2ADRM9 0x00000178U + +// +#define PBE_BLE5_RAM_O_FL2ADRH9 0x0000017AU + +// +#define PBE_BLE5_RAM_O_FL2INFO10 0x0000017CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL10 0x0000017EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM10 0x00000180U + +// +#define PBE_BLE5_RAM_O_FL2ADRH10 0x00000182U + +// +#define PBE_BLE5_RAM_O_FL2INFO11 0x00000184U + +// +#define PBE_BLE5_RAM_O_FL2ADRL11 0x00000186U + +// +#define PBE_BLE5_RAM_O_FL2ADRM11 0x00000188U + +// +#define PBE_BLE5_RAM_O_FL2ADRH11 0x0000018AU + +// +#define PBE_BLE5_RAM_O_FL2INFO12 0x0000018CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL12 0x0000018EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM12 0x00000190U + +// +#define PBE_BLE5_RAM_O_FL2ADRH12 0x00000192U + +// +#define PBE_BLE5_RAM_O_FL2INFO13 0x00000194U + +// +#define PBE_BLE5_RAM_O_FL2ADRL13 0x00000196U + +// +#define PBE_BLE5_RAM_O_FL2ADRM13 0x00000198U + +// +#define PBE_BLE5_RAM_O_FL2ADRH13 0x0000019AU + +// +#define PBE_BLE5_RAM_O_FL2INFO14 0x0000019CU + +// +#define PBE_BLE5_RAM_O_FL2ADRL14 0x0000019EU + +// +#define PBE_BLE5_RAM_O_FL2ADRM14 0x000001A0U + +// +#define PBE_BLE5_RAM_O_FL2ADRH14 0x000001A2U + +// +#define PBE_BLE5_RAM_O_FL2INFO15 0x000001A4U + +// +#define PBE_BLE5_RAM_O_FL2ADRL15 0x000001A6U + +// +#define PBE_BLE5_RAM_O_FL2ADRM15 0x000001A8U + +// +#define PBE_BLE5_RAM_O_FL2ADRH15 0x000001AAU + +//****************************************************************************** +// Register: PHY +//****************************************************************************** +// Field: [1:0] sel +// +// Used to pass on the value of the Coding Indicator, +#define PBE_BLE5_RAM_PHY_SEL_W 2U +#define PBE_BLE5_RAM_PHY_SEL_M 0x0003U +#define PBE_BLE5_RAM_PHY_SEL_S 0U +#define PBE_BLE5_RAM_PHY_SEL_1M 0x0000U +#define PBE_BLE5_RAM_PHY_SEL_2M 0x0001U +#define PBE_BLE5_RAM_PHY_SEL_CODED_125K 0x0002U +#define PBE_BLE5_RAM_PHY_SEL_CODED_500K 0x0003U + +//****************************************************************************** +// Register: PRETXIFS500K +//****************************************************************************** +// Field: [15:0] val +// +// For bluetooth long range (BLR) and the 500k data rate only. Base value used after RX to set timer0 for when to start Transmission. +#define PBE_BLE5_RAM_PRETXIFS500K_VAL_W 16U +#define PBE_BLE5_RAM_PRETXIFS500K_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_PRETXIFS500K_VAL_S 0U + +//****************************************************************************** +// Register: PRETXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used after RX to set timer0 for when to start Transmission. +#define PBE_BLE5_RAM_PRETXIFS_VAL_W 16U +#define PBE_BLE5_RAM_PRETXIFS_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_PRETXIFS_VAL_S 0U + +//****************************************************************************** +// Register: PRERXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used after TX to set timer0 for when to start Receiving. +#define PBE_BLE5_RAM_PRERXIFS_VAL_W 16U +#define PBE_BLE5_RAM_PRERXIFS_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_PRERXIFS_VAL_S 0U + +//****************************************************************************** +// Register: RXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// Time to stay in RX before giving up sync search. Only used in T_IFS scenarios. If VAL = 0 then the PBE waits forever or until the CM0 manually interrupts. +#define PBE_BLE5_RAM_RXTIMEOUT_VAL_W 16U +#define PBE_BLE5_RAM_RXTIMEOUT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_RXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: SYNTHCALTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// How many µs the PBE shall set its local timer to wait for the RFE synth calibration. +#define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_W 16U +#define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_SYNTHCALTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: RECALTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// How many µs the PBE shall set its local timer to wait for the RFE synth re-calibration. +#define PBE_BLE5_RAM_RECALTIMEOUT_VAL_W 16U +#define PBE_BLE5_RAM_RECALTIMEOUT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_RECALTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: RPAMODE +//****************************************************************************** +// Field: [3:3] ownadr +// +// Filtering of own (receiver) address +#define PBE_BLE5_RAM_RPAMODE_OWNADR 0x0008U +#define PBE_BLE5_RAM_RPAMODE_OWNADR_M 0x0008U +#define PBE_BLE5_RAM_RPAMODE_OWNADR_S 3U + +// Field: [2:2] peeradr +// +// Filtering of peer (transmitter) address, may use the Filter Accept List +#define PBE_BLE5_RAM_RPAMODE_PEERADR 0x0004U +#define PBE_BLE5_RAM_RPAMODE_PEERADR_M 0x0004U +#define PBE_BLE5_RAM_RPAMODE_PEERADR_S 2U + +//****************************************************************************** +// Register: RPACONNECT +//****************************************************************************** +// Field: [0:0] endadv +// +// +#define PBE_BLE5_RAM_RPACONNECT_ENDADV 0x0001U +#define PBE_BLE5_RAM_RPACONNECT_ENDADV_M 0x0001U +#define PBE_BLE5_RAM_RPACONNECT_ENDADV_S 0U + +//****************************************************************************** +// Register: FIFOCFG +//****************************************************************************** +// Field: [8:8] appendtimestamp +// +// +#define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP 0x0100U +#define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x0100U +#define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_S 8U +#define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_DIS 0x0000U +#define PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_ENA 0x0100U + +// Field: [7:7] appendrssi +// +// +#define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI 0x0080U +#define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M 0x0080U +#define PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_S 7U + +// Field: [6:6] appendfreqest +// +// +#define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST 0x0040U +#define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_M 0x0040U +#define PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_S 6U + +// Field: [5:5] appendlqi +// +// +#define PBE_BLE5_RAM_FIFOCFG_APPENDLQI 0x0020U +#define PBE_BLE5_RAM_FIFOCFG_APPENDLQI_M 0x0020U +#define PBE_BLE5_RAM_FIFOCFG_APPENDLQI_S 5U + +// Field: [4:4] appendstatus +// +// CRCOK, Ignore, Code rate +#define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS 0x0010U +#define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M 0x0010U +#define PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_S 4U + +// Field: [3:3] appendcrc +// +// Append all received crc bits +#define PBE_BLE5_RAM_FIFOCFG_APPENDCRC 0x0008U +#define PBE_BLE5_RAM_FIFOCFG_APPENDCRC_M 0x0008U +#define PBE_BLE5_RAM_FIFOCFG_APPENDCRC_S 3U + +// Field: [2:2] autoflushempty +// +// +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY 0x0004U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_M 0x0004U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_S 2U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_KEEP 0x0000U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_FLUSH 0x0004U + +// Field: [1:1] autoflushign +// +// +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN 0x0002U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0002U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_S 1U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0002U + +// Field: [0:0] autoflushcrc +// +// +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC 0x0001U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0001U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_S 0U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U +#define PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0001U + +//****************************************************************************** +// Register: STATUSBYTE +//****************************************************************************** +// Field: [15:5] reserved +// +// Flags +#define PBE_BLE5_RAM_STATUSBYTE_RESERVED_W 11U +#define PBE_BLE5_RAM_STATUSBYTE_RESERVED_M 0xFFE0U +#define PBE_BLE5_RAM_STATUSBYTE_RESERVED_S 5U + +// Field: [4:4] rpaignored +// +// Ignored due to RPA. +#define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED 0x0010U +#define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED_M 0x0010U +#define PBE_BLE5_RAM_STATUSBYTE_RPAIGNORED_S 4U + +// Field: [3:3] ignored +// +// Ignored due to PID or address. +#define PBE_BLE5_RAM_STATUSBYTE_IGNORED 0x0008U +#define PBE_BLE5_RAM_STATUSBYTE_IGNORED_M 0x0008U +#define PBE_BLE5_RAM_STATUSBYTE_IGNORED_S 3U + +// Field: [2:2] crcerror +// +// CRC check with PHA failed. +#define PBE_BLE5_RAM_STATUSBYTE_CRCERROR 0x0004U +#define PBE_BLE5_RAM_STATUSBYTE_CRCERROR_M 0x0004U +#define PBE_BLE5_RAM_STATUSBYTE_CRCERROR_S 2U + +// Field: [1:0] phy +// +// aka Rate Indicator. +#define PBE_BLE5_RAM_STATUSBYTE_PHY_W 2U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_M 0x0003U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_S 0U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_1M 0x0000U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_2M 0x0001U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_CODED_125K 0x0002U +#define PBE_BLE5_RAM_STATUSBYTE_PHY_CODED_500K 0x0003U + +//****************************************************************************** +// Register: NAKHUB +//****************************************************************************** +// Field: [5:3] nrnaks +// +// How many consecutive NAKS has been received +#define PBE_BLE5_RAM_NAKHUB_NRNAKS_W 3U +#define PBE_BLE5_RAM_NAKHUB_NRNAKS_M 0x0038U +#define PBE_BLE5_RAM_NAKHUB_NRNAKS_S 3U + +// Field: [2:0] maxnak +// +// Maximum number of packets received without a new value of NESN in the same task before the task ends. If both devices find themselves with full RX FIFO or no RX buffer available, they will request the peer to retransmit by transmitting a NAK. This is a sort of livelock loop. If it's 0, do not end the task based on this. +#define PBE_BLE5_RAM_NAKHUB_MAXNAK_W 3U +#define PBE_BLE5_RAM_NAKHUB_MAXNAK_M 0x0007U +#define PBE_BLE5_RAM_NAKHUB_MAXNAK_S 0U + +//****************************************************************************** +// Register: WHITEINIT +//****************************************************************************** +// Field: [15:0] val +// +// Whitener initialization value +#define PBE_BLE5_RAM_WHITEINIT_VAL_W 16U +#define PBE_BLE5_RAM_WHITEINIT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_WHITEINIT_VAL_S 0U + +//****************************************************************************** +// Register: EXTRABYTES +//****************************************************************************** +// Field: [15:0] val +// +// The number of bytes required. +#define PBE_BLE5_RAM_EXTRABYTES_VAL_W 16U +#define PBE_BLE5_RAM_EXTRABYTES_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_EXTRABYTES_VAL_S 0U + +//****************************************************************************** +// Register: CRCINITL +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_BLE5_RAM_CRCINITL_VALLSB_W 16U +#define PBE_BLE5_RAM_CRCINITL_VALLSB_M 0xFFFFU +#define PBE_BLE5_RAM_CRCINITL_VALLSB_S 0U + +//****************************************************************************** +// Register: CRCINITH +//****************************************************************************** +// Field: [15:0] valmsb +// +// +#define PBE_BLE5_RAM_CRCINITH_VALMSB_W 16U +#define PBE_BLE5_RAM_CRCINITH_VALMSB_M 0xFFFFU +#define PBE_BLE5_RAM_CRCINITH_VALMSB_S 0U + +//****************************************************************************** +// Register: SEQSTAT +//****************************************************************************** +// Field: [7:7] ctlackpend +// +// The last successfully received packet was an LL control packet which has not yet been ACK'ed +#define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND 0x0080U +#define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_M 0x0080U +#define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_S 7U +#define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_NO 0x0000U +#define PBE_BLE5_RAM_SEQSTAT_CTLACKPEND_YES 0x0080U + +// Field: [6:6] ctlack +// +// The last received packet was the ACK of an LL control packet +#define PBE_BLE5_RAM_SEQSTAT_CTLACK 0x0040U +#define PBE_BLE5_RAM_SEQSTAT_CTLACK_M 0x0040U +#define PBE_BLE5_RAM_SEQSTAT_CTLACK_S 6U +#define PBE_BLE5_RAM_SEQSTAT_CTLACK_NO 0x0000U +#define PBE_BLE5_RAM_SEQSTAT_CTLACK_YES 0x0040U + +// Field: [5:5] ctltx +// +// The last transmitted packet was an LL control packet (LLID = 11) +#define PBE_BLE5_RAM_SEQSTAT_CTLTX 0x0020U +#define PBE_BLE5_RAM_SEQSTAT_CTLTX_M 0x0020U +#define PBE_BLE5_RAM_SEQSTAT_CTLTX_S 5U +#define PBE_BLE5_RAM_SEQSTAT_CTLTX_NO 0x0000U +#define PBE_BLE5_RAM_SEQSTAT_CTLTX_YES 0x0020U + +// Field: [4:4] empty +// +// The last transmitted packet was an auto-empty packet. +#define PBE_BLE5_RAM_SEQSTAT_EMPTY 0x0010U +#define PBE_BLE5_RAM_SEQSTAT_EMPTY_M 0x0010U +#define PBE_BLE5_RAM_SEQSTAT_EMPTY_S 4U + +// Field: [3:3] firstpkt +// +// Has there been any packets transmitted on this connection +#define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT 0x0008U +#define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_M 0x0008U +#define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_S 3U +#define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_NOT_FIRST 0x0000U +#define PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_FIRST 0x0008U + +// Field: [2:2] nexttxsn +// +// SN in the next message to transmit. +#define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN 0x0004U +#define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN_M 0x0004U +#define PBE_BLE5_RAM_SEQSTAT_NEXTTXSN_S 2U + +// Field: [1:1] lasttxsn +// +// SN in the last message transmitted. +#define PBE_BLE5_RAM_SEQSTAT_LASTTXSN 0x0002U +#define PBE_BLE5_RAM_SEQSTAT_LASTTXSN_M 0x0002U +#define PBE_BLE5_RAM_SEQSTAT_LASTTXSN_S 1U + +// Field: [0:0] lastrxsn +// +// SN in the last message received with CRC OK. +#define PBE_BLE5_RAM_SEQSTAT_LASTRXSN 0x0001U +#define PBE_BLE5_RAM_SEQSTAT_LASTRXSN_M 0x0001U +#define PBE_BLE5_RAM_SEQSTAT_LASTRXSN_S 0U + +//****************************************************************************** +// Register: BACKOFFCNT +//****************************************************************************** +// Field: [15:0] val +// +// MCU writes new value of back-off count for first scanner task after transmission of SCAN_REQ and subsequent reception or attempted reception of SCAN_RSP, or returned value from last scanner task. PBE decrements the back-off count on every correctly received advertising packet that will generate a SCAN_RSP and writes it back at the end of the task. Allowed values: write from MCU: 1–256. Read from MCU: 0–256. +#define PBE_BLE5_RAM_BACKOFFCNT_VAL_W 16U +#define PBE_BLE5_RAM_BACKOFFCNT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_BACKOFFCNT_VAL_S 0U + +//****************************************************************************** +// Register: SCANCFG +//****************************************************************************** +// Field: [0:0] actpass +// +// Configure scan type +#define PBE_BLE5_RAM_SCANCFG_ACTPASS 0x0001U +#define PBE_BLE5_RAM_SCANCFG_ACTPASS_M 0x0001U +#define PBE_BLE5_RAM_SCANCFG_ACTPASS_S 0U +#define PBE_BLE5_RAM_SCANCFG_ACTPASS_PASS 0x0000U +#define PBE_BLE5_RAM_SCANCFG_ACTPASS_ACT 0x0001U + +//****************************************************************************** +// Register: AECFG +//****************************************************************************** +// Field: [5:5] advmode2 +// +// Accept extended advertising packets with ADV_MODE=2 +#define PBE_BLE5_RAM_AECFG_ADVMODE2 0x0020U +#define PBE_BLE5_RAM_AECFG_ADVMODE2_M 0x0020U +#define PBE_BLE5_RAM_AECFG_ADVMODE2_S 5U +#define PBE_BLE5_RAM_AECFG_ADVMODE2_REJECT 0x0000U +#define PBE_BLE5_RAM_AECFG_ADVMODE2_ACCEPT 0x0020U + +// Field: [4:4] advmode1 +// +// Accept extended advertising packets with ADV_MODE=1 +#define PBE_BLE5_RAM_AECFG_ADVMODE1 0x0010U +#define PBE_BLE5_RAM_AECFG_ADVMODE1_M 0x0010U +#define PBE_BLE5_RAM_AECFG_ADVMODE1_S 4U +#define PBE_BLE5_RAM_AECFG_ADVMODE1_REJECT 0x0000U +#define PBE_BLE5_RAM_AECFG_ADVMODE1_ACCEPT 0x0010U + +// Field: [3:3] advmode0 +// +// Accept extended advertising packets with ADV_MODE=0 +#define PBE_BLE5_RAM_AECFG_ADVMODE0 0x0008U +#define PBE_BLE5_RAM_AECFG_ADVMODE0_M 0x0008U +#define PBE_BLE5_RAM_AECFG_ADVMODE0_S 3U +#define PBE_BLE5_RAM_AECFG_ADVMODE0_REJECT 0x0000U +#define PBE_BLE5_RAM_AECFG_ADVMODE0_ACCEPT 0x0008U + +// Field: [2:2] chnl +// +// Current channel type +#define PBE_BLE5_RAM_AECFG_CHNL 0x0004U +#define PBE_BLE5_RAM_AECFG_CHNL_M 0x0004U +#define PBE_BLE5_RAM_AECFG_CHNL_S 2U +#define PBE_BLE5_RAM_AECFG_CHNL_PRIMARY 0x0000U +#define PBE_BLE5_RAM_AECFG_CHNL_SECONDARY 0x0004U + +// Field: [1:1] extended +// +// Extended advertisement enabled +#define PBE_BLE5_RAM_AECFG_EXTENDED 0x0002U +#define PBE_BLE5_RAM_AECFG_EXTENDED_M 0x0002U +#define PBE_BLE5_RAM_AECFG_EXTENDED_S 1U +#define PBE_BLE5_RAM_AECFG_EXTENDED_DIS 0x0000U +#define PBE_BLE5_RAM_AECFG_EXTENDED_EN 0x0002U + +// Field: [0:0] legacy +// +// Legacy advertisement enabled +#define PBE_BLE5_RAM_AECFG_LEGACY 0x0001U +#define PBE_BLE5_RAM_AECFG_LEGACY_M 0x0001U +#define PBE_BLE5_RAM_AECFG_LEGACY_S 0U +#define PBE_BLE5_RAM_AECFG_LEGACY_DIS 0x0000U +#define PBE_BLE5_RAM_AECFG_LEGACY_EN 0x0001U + +//****************************************************************************** +// Register: AETMP +//****************************************************************************** +// Field: [9:9] scannable +// +// +#define PBE_BLE5_RAM_AETMP_SCANNABLE 0x0200U +#define PBE_BLE5_RAM_AETMP_SCANNABLE_M 0x0200U +#define PBE_BLE5_RAM_AETMP_SCANNABLE_S 9U + +// Field: [8:8] connectable +// +// +#define PBE_BLE5_RAM_AETMP_CONNECTABLE 0x0100U +#define PBE_BLE5_RAM_AETMP_CONNECTABLE_M 0x0100U +#define PBE_BLE5_RAM_AETMP_CONNECTABLE_S 8U + +// Field: [7:7] res +// +// +#define PBE_BLE5_RAM_AETMP_RES 0x0080U +#define PBE_BLE5_RAM_AETMP_RES_M 0x0080U +#define PBE_BLE5_RAM_AETMP_RES_S 7U + +// Field: [6:6] txpower +// +// +#define PBE_BLE5_RAM_AETMP_TXPOWER 0x0040U +#define PBE_BLE5_RAM_AETMP_TXPOWER_M 0x0040U +#define PBE_BLE5_RAM_AETMP_TXPOWER_S 6U + +// Field: [5:5] syncinfo +// +// +#define PBE_BLE5_RAM_AETMP_SYNCINFO 0x0020U +#define PBE_BLE5_RAM_AETMP_SYNCINFO_M 0x0020U +#define PBE_BLE5_RAM_AETMP_SYNCINFO_S 5U + +// Field: [4:4] auxptr +// +// +#define PBE_BLE5_RAM_AETMP_AUXPTR 0x0010U +#define PBE_BLE5_RAM_AETMP_AUXPTR_M 0x0010U +#define PBE_BLE5_RAM_AETMP_AUXPTR_S 4U + +// Field: [3:3] adi +// +// +#define PBE_BLE5_RAM_AETMP_ADI 0x0008U +#define PBE_BLE5_RAM_AETMP_ADI_M 0x0008U +#define PBE_BLE5_RAM_AETMP_ADI_S 3U + +// Field: [2:2] cteinfo +// +// +#define PBE_BLE5_RAM_AETMP_CTEINFO 0x0004U +#define PBE_BLE5_RAM_AETMP_CTEINFO_M 0x0004U +#define PBE_BLE5_RAM_AETMP_CTEINFO_S 2U + +// Field: [1:1] targeta +// +// +#define PBE_BLE5_RAM_AETMP_TARGETA 0x0002U +#define PBE_BLE5_RAM_AETMP_TARGETA_M 0x0002U +#define PBE_BLE5_RAM_AETMP_TARGETA_S 1U + +// Field: [0:0] adva +// +// +#define PBE_BLE5_RAM_AETMP_ADVA 0x0001U +#define PBE_BLE5_RAM_AETMP_ADVA_M 0x0001U +#define PBE_BLE5_RAM_AETMP_ADVA_S 0U + +//****************************************************************************** +// Register: EXTLENTMP +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE5_RAM_EXTLENTMP_VAL_W 16U +#define PBE_BLE5_RAM_EXTLENTMP_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_EXTLENTMP_VAL_S 0U + +//****************************************************************************** +// Register: WINOFFSET +//****************************************************************************** +// Field: [15:0] val +// +// The RCL intializes this to the range 4-WINMOD at the start of the intiator operation. +#define PBE_BLE5_RAM_WINOFFSET_VAL_W 16U +#define PBE_BLE5_RAM_WINOFFSET_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_WINOFFSET_VAL_S 0U + +//****************************************************************************** +// Register: WINMOD +//****************************************************************************** +// Field: [15:0] val +// +// The amount of 312.5 us periods in the connection interval (four times the number given by the BLE LL). A value of 0 means that dynamic window offset is disabled. +#define PBE_BLE5_RAM_WINMOD_VAL_W 16U +#define PBE_BLE5_RAM_WINMOD_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_WINMOD_VAL_S 0U + +//****************************************************************************** +// Register: MAXLEN +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE5_RAM_MAXLEN_VAL_W 16U +#define PBE_BLE5_RAM_MAXLEN_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_MAXLEN_VAL_S 0U + +//****************************************************************************** +// Register: FILTPOLICY +//****************************************************************************** +// Field: [4:4] intor +// +// Initiator's filter policy +#define PBE_BLE5_RAM_FILTPOLICY_INTOR 0x0010U +#define PBE_BLE5_RAM_FILTPOLICY_INTOR_M 0x0010U +#define PBE_BLE5_RAM_FILTPOLICY_INTOR_S 4U +#define PBE_BLE5_RAM_FILTPOLICY_INTOR_PEERADR 0x0000U +#define PBE_BLE5_RAM_FILTPOLICY_INTOR_FL2 0x0010U + +// Field: [3:3] extscanner +// +// Extended scanner filter policy. +#define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER 0x0008U +#define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_M 0x0008U +#define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_S 3U +#define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_NORPA 0x0000U +#define PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_ANYRPA 0x0008U + +// Field: [2:2] scanner +// +// Scanner's filter policy +#define PBE_BLE5_RAM_FILTPOLICY_SCANNER 0x0004U +#define PBE_BLE5_RAM_FILTPOLICY_SCANNER_M 0x0004U +#define PBE_BLE5_RAM_FILTPOLICY_SCANNER_S 2U +#define PBE_BLE5_RAM_FILTPOLICY_SCANNER_REJFL1 0x0000U +#define PBE_BLE5_RAM_FILTPOLICY_SCANNER_FL1 0x0004U + +// Field: [1:0] adv +// +// Advertiser's filter policy. Note: The Advertiser's filter policy is ignored during all directed advertiser events, all combinations. +#define PBE_BLE5_RAM_FILTPOLICY_ADV_W 2U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_M 0x0003U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_S 0U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_REJFL1_REJFL2 0x0000U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_FL1_REJFL2 0x0001U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_REJFL1_FL2 0x0002U +#define PBE_BLE5_RAM_FILTPOLICY_ADV_FL1_FL2 0x0003U + +//****************************************************************************** +// Register: OWNADRTYPE +//****************************************************************************** +// Field: [0:0] type +// +// Address in OWNADR +#define PBE_BLE5_RAM_OWNADRTYPE_TYPE 0x0001U +#define PBE_BLE5_RAM_OWNADRTYPE_TYPE_M 0x0001U +#define PBE_BLE5_RAM_OWNADRTYPE_TYPE_S 0U +#define PBE_BLE5_RAM_OWNADRTYPE_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_OWNADRTYPE_TYPE_RANDOM 0x0001U + +//****************************************************************************** +// Register: PEERADRTYPE +//****************************************************************************** +// Field: [0:0] type +// +// Address in PEERADR +#define PBE_BLE5_RAM_PEERADRTYPE_TYPE 0x0001U +#define PBE_BLE5_RAM_PEERADRTYPE_TYPE_M 0x0001U +#define PBE_BLE5_RAM_PEERADRTYPE_TYPE_S 0U +#define PBE_BLE5_RAM_PEERADRTYPE_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_PEERADRTYPE_TYPE_RANDOM 0x0001U + +//****************************************************************************** +// Register: OWNADRL +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_BLE5_RAM_OWNADRL_VALLSB_W 16U +#define PBE_BLE5_RAM_OWNADRL_VALLSB_M 0xFFFFU +#define PBE_BLE5_RAM_OWNADRL_VALLSB_S 0U + +//****************************************************************************** +// Register: OWNADRM +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_BLE5_RAM_OWNADRM_VALLSB_W 16U +#define PBE_BLE5_RAM_OWNADRM_VALLSB_M 0xFFFFU +#define PBE_BLE5_RAM_OWNADRM_VALLSB_S 0U + +//****************************************************************************** +// Register: OWNADRH +//****************************************************************************** +// Field: [15:0] valmsb +// +// +#define PBE_BLE5_RAM_OWNADRH_VALMSB_W 16U +#define PBE_BLE5_RAM_OWNADRH_VALMSB_M 0xFFFFU +#define PBE_BLE5_RAM_OWNADRH_VALMSB_S 0U + +//****************************************************************************** +// Register: TMPADRL +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of temporary address +#define PBE_BLE5_RAM_TMPADRL_VAL_W 16U +#define PBE_BLE5_RAM_TMPADRL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_TMPADRL_VAL_S 0U + +//****************************************************************************** +// Register: TMPADRM +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of temporary address +#define PBE_BLE5_RAM_TMPADRM_VAL_W 16U +#define PBE_BLE5_RAM_TMPADRM_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_TMPADRM_VAL_S 0U + +//****************************************************************************** +// Register: TMPADRH +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of temporary address +#define PBE_BLE5_RAM_TMPADRH_VAL_W 16U +#define PBE_BLE5_RAM_TMPADRH_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_TMPADRH_VAL_S 0U + +//****************************************************************************** +// Register: PEERADRL +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_BLE5_RAM_PEERADRL_VALLSB_W 16U +#define PBE_BLE5_RAM_PEERADRL_VALLSB_M 0xFFFFU +#define PBE_BLE5_RAM_PEERADRL_VALLSB_S 0U + +//****************************************************************************** +// Register: PEERADRM +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_BLE5_RAM_PEERADRM_VALLSB_W 16U +#define PBE_BLE5_RAM_PEERADRM_VALLSB_M 0xFFFFU +#define PBE_BLE5_RAM_PEERADRM_VALLSB_S 0U + +//****************************************************************************** +// Register: PEERADRH +//****************************************************************************** +// Field: [15:0] valmsb +// +// +#define PBE_BLE5_RAM_PEERADRH_VALMSB_W 16U +#define PBE_BLE5_RAM_PEERADRH_VALMSB_M 0xFFFFU +#define PBE_BLE5_RAM_PEERADRH_VALMSB_S 0U + +//****************************************************************************** +// Register: NTXDONE +//****************************************************************************** +// Field: [15:0] val +// +// Number of acknowledgements received on packets from the Tx FIFO +#define PBE_BLE5_RAM_NTXDONE_VAL_W 16U +#define PBE_BLE5_RAM_NTXDONE_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXDONE_VAL_S 0U + +//****************************************************************************** +// Register: NTXACK +//****************************************************************************** +// Field: [15:0] val +// +// Total number of acknowledgement received on transmitted packets +#define PBE_BLE5_RAM_NTXACK_VAL_W 16U +#define PBE_BLE5_RAM_NTXACK_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXACK_VAL_S 0U + +//****************************************************************************** +// Register: NTXCTLACK +//****************************************************************************** +// Field: [15:0] val +// +// Number of acknowledgements received on transmitted LL control packets +#define PBE_BLE5_RAM_NTXCTLACK_VAL_W 16U +#define PBE_BLE5_RAM_NTXCTLACK_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXCTLACK_VAL_S 0U + +//****************************************************************************** +// Register: NTXCTL +//****************************************************************************** +// Field: [15:0] val +// +// Number of unique LL control packets transmitted +#define PBE_BLE5_RAM_NTXCTL_VAL_W 16U +#define PBE_BLE5_RAM_NTXCTL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXCTL_VAL_S 0U + +//****************************************************************************** +// Register: NTXRETRANS +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets transmitted being the same as the previously transmitted packet. +#define PBE_BLE5_RAM_NTXRETRANS_VAL_W 16U +#define PBE_BLE5_RAM_NTXRETRANS_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXRETRANS_VAL_S 0U + +//****************************************************************************** +// Register: NRXNOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC error +#define PBE_BLE5_RAM_NRXNOK_VAL_W 16U +#define PBE_BLE5_RAM_NRXNOK_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXNOK_VAL_S 0U + +//****************************************************************************** +// Register: NRXIGNORED +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC OK, but to be ignored by the MCU +#define PBE_BLE5_RAM_NRXIGNORED_VAL_W 16U +#define PBE_BLE5_RAM_NRXIGNORED_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXIGNORED_VAL_S 0U + +//****************************************************************************** +// Register: NRXEMPTY +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC OK and length zero +#define PBE_BLE5_RAM_NRXEMPTY_VAL_W 16U +#define PBE_BLE5_RAM_NRXEMPTY_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXEMPTY_VAL_S 0U + +//****************************************************************************** +// Register: NRXFIFOFULL +//****************************************************************************** +// Field: [15:0] val +// +// Number of received packets discarded because the Rx FIFO was full +#define PBE_BLE5_RAM_NRXFIFOFULL_VAL_W 16U +#define PBE_BLE5_RAM_NRXFIFOFULL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXFIFOFULL_VAL_S 0U + +//****************************************************************************** +// Register: NRXOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of non-empty packets received with CRC OK and not to be ignored by the MCU +#define PBE_BLE5_RAM_NRXOK_VAL_W 16U +#define PBE_BLE5_RAM_NRXOK_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXOK_VAL_S 0U + +//****************************************************************************** +// Register: NTX +//****************************************************************************** +// Field: [15:0] val +// +// Total number of packets transmitted in the task +#define PBE_BLE5_RAM_NTX_VAL_W 16U +#define PBE_BLE5_RAM_NTX_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTX_VAL_S 0U + +//****************************************************************************** +// Register: NRXCTL +//****************************************************************************** +// Field: [15:0] val +// +// Number of LL control packets correctly received (also included in NRXOK) +#define PBE_BLE5_RAM_NRXCTL_VAL_W 16U +#define PBE_BLE5_RAM_NRXCTL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXCTL_VAL_S 0U + +//****************************************************************************** +// Register: NRXCTLACK +//****************************************************************************** +// Field: [15:0] val +// +// Total number of acknowledgement transmitted on received LL control packets. +#define PBE_BLE5_RAM_NRXCTLACK_VAL_W 16U +#define PBE_BLE5_RAM_NRXCTLACK_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NRXCTLACK_VAL_S 0U + +//****************************************************************************** +// Register: LASTRSSI +//****************************************************************************** +// Field: [15:0] val +// +// RSSI of last packet received in task +#define PBE_BLE5_RAM_LASTRSSI_VAL_W 16U +#define PBE_BLE5_RAM_LASTRSSI_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_LASTRSSI_VAL_S 0U + +//****************************************************************************** +// Register: FIRSTRXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// For peripheral tasks, the timeout in µs from SYSTCMP0 event to giving up listening for the first packet. Must be at least 128 µs if non-zero. Can be up to 32000 µs based on supervision timeout, window widening. +#define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_W 16U +#define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FIRSTRXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPL +//****************************************************************************** +// Field: [15:0] val +// +// Lower part of timestamp. +#define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_W 16U +#define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_LASTTIMESTAMPL_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPH +//****************************************************************************** +// Field: [15:0] val +// +// Upper part of timestamp. +#define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_W 16U +#define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_LASTTIMESTAMPH_VAL_S 0U + +//****************************************************************************** +// Register: MDCFG +//****************************************************************************** +// Field: [1:0] force +// +// +#define PBE_BLE5_RAM_MDCFG_FORCE_W 2U +#define PBE_BLE5_RAM_MDCFG_FORCE_M 0x0003U +#define PBE_BLE5_RAM_MDCFG_FORCE_S 0U +#define PBE_BLE5_RAM_MDCFG_FORCE_MD0 0x0001U +#define PBE_BLE5_RAM_MDCFG_FORCE_MD1 0x0002U + +//****************************************************************************** +// Register: ADVCFG +//****************************************************************************** +// Field: [3:3] extended +// +// +#define PBE_BLE5_RAM_ADVCFG_EXTENDED 0x0008U +#define PBE_BLE5_RAM_ADVCFG_EXTENDED_M 0x0008U +#define PBE_BLE5_RAM_ADVCFG_EXTENDED_S 3U + +// Field: [2:2] directed +// +// +#define PBE_BLE5_RAM_ADVCFG_DIRECTED 0x0004U +#define PBE_BLE5_RAM_ADVCFG_DIRECTED_M 0x0004U +#define PBE_BLE5_RAM_ADVCFG_DIRECTED_S 2U + +// Field: [1:1] scannable +// +// +#define PBE_BLE5_RAM_ADVCFG_SCANNABLE 0x0002U +#define PBE_BLE5_RAM_ADVCFG_SCANNABLE_M 0x0002U +#define PBE_BLE5_RAM_ADVCFG_SCANNABLE_S 1U + +// Field: [0:0] connectable +// +// +#define PBE_BLE5_RAM_ADVCFG_CONNECTABLE 0x0001U +#define PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M 0x0001U +#define PBE_BLE5_RAM_ADVCFG_CONNECTABLE_S 0U + +//****************************************************************************** +// Register: TMPRSSI +//****************************************************************************** +// Field: [15:0] val +// +// RSSI +#define PBE_BLE5_RAM_TMPRSSI_VAL_W 16U +#define PBE_BLE5_RAM_TMPRSSI_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_TMPRSSI_VAL_S 0U + +//****************************************************************************** +// Register: FIRSTTIMESTAMPL +//****************************************************************************** +// Field: [15:0] val +// +// Peripheral only. +#define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_W 16U +#define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FIRSTTIMESTAMPL_VAL_S 0U + +//****************************************************************************** +// Register: FIRSTTIMESTAMPH +//****************************************************************************** +// Field: [15:0] val +// +// Peripheral only. +#define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_W 16U +#define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FIRSTTIMESTAMPH_VAL_S 0U + +//****************************************************************************** +// Register: FL1RESULT +//****************************************************************************** +// Field: [3:0] index +// +// Which entry in the address table matched +#define PBE_BLE5_RAM_FL1RESULT_INDEX_W 4U +#define PBE_BLE5_RAM_FL1RESULT_INDEX_M 0x000FU +#define PBE_BLE5_RAM_FL1RESULT_INDEX_S 0U + +//****************************************************************************** +// Register: FL1MASK +//****************************************************************************** +// Field: [15:15] match +// +// +#define PBE_BLE5_RAM_FL1MASK_MATCH 0x8000U +#define PBE_BLE5_RAM_FL1MASK_MATCH_M 0x8000U +#define PBE_BLE5_RAM_FL1MASK_MATCH_S 15U +#define PBE_BLE5_RAM_FL1MASK_MATCH_DIS 0x0000U +#define PBE_BLE5_RAM_FL1MASK_MATCH_EN 0x8000U + +// Field: [14:4] rfuign +// +// These bits works the same was as PRIVIGN and FALIGN. +#define PBE_BLE5_RAM_FL1MASK_RFUIGN_W 11U +#define PBE_BLE5_RAM_FL1MASK_RFUIGN_M 0x7FF0U +#define PBE_BLE5_RAM_FL1MASK_RFUIGN_S 4U + +// Field: [3:3] privign +// +// +#define PBE_BLE5_RAM_FL1MASK_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1MASK_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1MASK_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1MASK_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1MASK_PRIVIGN_IGN 0x0008U + +// Field: [2:2] duplicateign +// +// +#define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN 0x0004U +#define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_S 2U +#define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1MASK_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1MASK_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1MASK_TYPE_S 1U +#define PBE_BLE5_RAM_FL1MASK_TYPE_DIS 0x0000U +#define PBE_BLE5_RAM_FL1MASK_TYPE_EN 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1MASK_EN 0x0001U +#define PBE_BLE5_RAM_FL1MASK_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1MASK_EN_S 0U +#define PBE_BLE5_RAM_FL1MASK_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1MASK_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2RESULT +//****************************************************************************** +// Field: [3:0] index +// +// Which entry in the address table matched +#define PBE_BLE5_RAM_FL2RESULT_INDEX_W 4U +#define PBE_BLE5_RAM_FL2RESULT_INDEX_M 0x000FU +#define PBE_BLE5_RAM_FL2RESULT_INDEX_S 0U + +//****************************************************************************** +// Register: FL2MASK +//****************************************************************************** +// Field: [15:15] match +// +// +#define PBE_BLE5_RAM_FL2MASK_MATCH 0x8000U +#define PBE_BLE5_RAM_FL2MASK_MATCH_M 0x8000U +#define PBE_BLE5_RAM_FL2MASK_MATCH_S 15U +#define PBE_BLE5_RAM_FL2MASK_MATCH_DIS 0x0000U +#define PBE_BLE5_RAM_FL2MASK_MATCH_EN 0x8000U + +// Field: [14:4] rfuign +// +// These bits works the same was as PRIVIGN and FALIGN. +#define PBE_BLE5_RAM_FL2MASK_RFUIGN_W 11U +#define PBE_BLE5_RAM_FL2MASK_RFUIGN_M 0x7FF0U +#define PBE_BLE5_RAM_FL2MASK_RFUIGN_S 4U + +// Field: [3:3] privign +// +// +#define PBE_BLE5_RAM_FL2MASK_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2MASK_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2MASK_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2MASK_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2MASK_PRIVIGN_IGN 0x0008U + +// Field: [2:2] duplicateign +// +// +#define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN 0x0004U +#define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_S 2U +#define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2MASK_DUPLICATEIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2MASK_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2MASK_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2MASK_TYPE_S 1U +#define PBE_BLE5_RAM_FL2MASK_TYPE_DIS 0x0000U +#define PBE_BLE5_RAM_FL2MASK_TYPE_EN 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2MASK_EN 0x0001U +#define PBE_BLE5_RAM_FL2MASK_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2MASK_EN_S 0U +#define PBE_BLE5_RAM_FL2MASK_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2MASK_EN_EN 0x0001U + +//****************************************************************************** +// Register: FLSTAT +//****************************************************************************** +// Field: [1:1] fl2running +// +// Status; is FL2 running address filtering +#define PBE_BLE5_RAM_FLSTAT_FL2RUNNING 0x0002U +#define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_M 0x0002U +#define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_S 1U +#define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_IDLE 0x0000U +#define PBE_BLE5_RAM_FLSTAT_FL2RUNNING_RUNNING 0x0002U + +// Field: [0:0] fl1running +// +// Status; is FL1 running address filtering +#define PBE_BLE5_RAM_FLSTAT_FL1RUNNING 0x0001U +#define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_M 0x0001U +#define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_S 0U +#define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_IDLE 0x0000U +#define PBE_BLE5_RAM_FLSTAT_FL1RUNNING_RUNNING 0x0001U + +//****************************************************************************** +// Register: TMPATYPE +//****************************************************************************** +// Field: [0:0] val +// +// temporary address type storage +#define PBE_BLE5_RAM_TMPATYPE_VAL 0x0001U +#define PBE_BLE5_RAM_TMPATYPE_VAL_M 0x0001U +#define PBE_BLE5_RAM_TMPATYPE_VAL_S 0U + +//****************************************************************************** +// Register: PATTERN +//****************************************************************************** +// Field: [15:0] val +// +// Data to send if OPCFG.TXPATTERN is 1 +#define PBE_BLE5_RAM_PATTERN_VAL_W 16U +#define PBE_BLE5_RAM_PATTERN_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_PATTERN_VAL_S 0U + +//****************************************************************************** +// Register: RFINTERVAL +//****************************************************************************** +// Field: [15:0] val +// +// RF interval, measured from start-to-start of TX_RAW. The actual time depends on configuration of timer1. +#define PBE_BLE5_RAM_RFINTERVAL_VAL_W 16U +#define PBE_BLE5_RAM_RFINTERVAL_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_RFINTERVAL_VAL_S 0U + +//****************************************************************************** +// Register: NTXTARGET +//****************************************************************************** +// Field: [15:0] val +// +// Used in TX_RAW; Total number of packets to transfer. +#define PBE_BLE5_RAM_NTXTARGET_VAL_W 16U +#define PBE_BLE5_RAM_NTXTARGET_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_NTXTARGET_VAL_S 0U + +//****************************************************************************** +// Register: OPCFG +//****************************************************************************** +// Field: [4:4] repeat +// +// Rule for what to do after operation completes. +#define PBE_BLE5_RAM_OPCFG_REPEAT 0x0010U +#define PBE_BLE5_RAM_OPCFG_REPEAT_M 0x0010U +#define PBE_BLE5_RAM_OPCFG_REPEAT_S 4U +#define PBE_BLE5_RAM_OPCFG_REPEAT_NO 0x0000U +#define PBE_BLE5_RAM_OPCFG_REPEAT_YES 0x0010U + +// Field: [3:3] txpattern +// +// Send fixed pattern +#define PBE_BLE5_RAM_OPCFG_TXPATTERN 0x0008U +#define PBE_BLE5_RAM_OPCFG_TXPATTERN_M 0x0008U +#define PBE_BLE5_RAM_OPCFG_TXPATTERN_S 3U +#define PBE_BLE5_RAM_OPCFG_TXPATTERN_NO 0x0000U +#define PBE_BLE5_RAM_OPCFG_TXPATTERN_YES 0x0008U + +// Field: [2:1] txfcmd +// +// Rule for FCMD after TX_DONE +#define PBE_BLE5_RAM_OPCFG_TXFCMD_W 2U +#define PBE_BLE5_RAM_OPCFG_TXFCMD_M 0x0006U +#define PBE_BLE5_RAM_OPCFG_TXFCMD_S 1U +#define PBE_BLE5_RAM_OPCFG_TXFCMD_NONE 0x0000U +#define PBE_BLE5_RAM_OPCFG_TXFCMD_RETRY 0x0002U +#define PBE_BLE5_RAM_OPCFG_TXFCMD_DEALLOC 0x0004U + +// Field: [0:0] rfinterval +// +// Requires REPEAT to make sense. +#define PBE_BLE5_RAM_OPCFG_RFINTERVAL 0x0001U +#define PBE_BLE5_RAM_OPCFG_RFINTERVAL_M 0x0001U +#define PBE_BLE5_RAM_OPCFG_RFINTERVAL_S 0U +#define PBE_BLE5_RAM_OPCFG_RFINTERVAL_DIS 0x0000U +#define PBE_BLE5_RAM_OPCFG_RFINTERVAL_EN 0x0001U + +//****************************************************************************** +// Register: FL1INFO0 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO0_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO0_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO0_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO0_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO0_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO0_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO0_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO0_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO0_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO0_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO0_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO0_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO0_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO0_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO0_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO0_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO0_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO0_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO0_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO0_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO0_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO0_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL0_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL0_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM0_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM0_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH0_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH0_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO1 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO1_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO1_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO1_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO1_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO1_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO1_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO1_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO1_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO1_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO1_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO1_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO1_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO1_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO1_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO1_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO1_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO1_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO1_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO1_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO1_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO1_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO1_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL1_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL1_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM1_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM1_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH1_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH1_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO2 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO2_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO2_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO2_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO2_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO2_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO2_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO2_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO2_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO2_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO2_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO2_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO2_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO2_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO2_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO2_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO2_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO2_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO2_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO2_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO2_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO2_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO2_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL2_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL2_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM2_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM2_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH2_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH2_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO3 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO3_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO3_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO3_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO3_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO3_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO3_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO3_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO3_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO3_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO3_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO3_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO3_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO3_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO3_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO3_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO3_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO3_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO3_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO3_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO3_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO3_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO3_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL3_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL3_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM3_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM3_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH3_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH3_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO4 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO4_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO4_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO4_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO4_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO4_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO4_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO4_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO4_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO4_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO4_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO4_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO4_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO4_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO4_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO4_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO4_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO4_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO4_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO4_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO4_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO4_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO4_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL4_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL4_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM4_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM4_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH4_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH4_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO5 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO5_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO5_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO5_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO5_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO5_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO5_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO5_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO5_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO5_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO5_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO5_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO5_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO5_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO5_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO5_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO5_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO5_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO5_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO5_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO5_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO5_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO5_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL5_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL5_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM5_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM5_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH5_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH5_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO6 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO6_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO6_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO6_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO6_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO6_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO6_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO6_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO6_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO6_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO6_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO6_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO6_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO6_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO6_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO6_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO6_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO6_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO6_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO6_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO6_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO6_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO6_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL6_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL6_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM6_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM6_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH6_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH6_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO7 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO7_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO7_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO7_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO7_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO7_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO7_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO7_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO7_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO7_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO7_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO7_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO7_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO7_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO7_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO7_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO7_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO7_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO7_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO7_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO7_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO7_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO7_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL7_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL7_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM7_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM7_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH7_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH7_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO8 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO8_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO8_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO8_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO8_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO8_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO8_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO8_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO8_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO8_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO8_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO8_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO8_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO8_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO8_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO8_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO8_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO8_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO8_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO8_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO8_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO8_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO8_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL8_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL8_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM8_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM8_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH8_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH8_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO9 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO9_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO9_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO9_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO9_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO9_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO9_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO9_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO9_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO9_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO9_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO9_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO9_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO9_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO9_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO9_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO9_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO9_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO9_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO9_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO9_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO9_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO9_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL9_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL9_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM9_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM9_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH9_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH9_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO10 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO10_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO10_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO10_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO10_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO10_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO10_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO10_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO10_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO10_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO10_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO10_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO10_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO10_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO10_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO10_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO10_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO10_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO10_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO10_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO10_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO10_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO10_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL10_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL10_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM10_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM10_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH10_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH10_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO11 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO11_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO11_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO11_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO11_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO11_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO11_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO11_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO11_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO11_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO11_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO11_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO11_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO11_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO11_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO11_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO11_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO11_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO11_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO11_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO11_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO11_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO11_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL11_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL11_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM11_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM11_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH11_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH11_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO12 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO12_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO12_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO12_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO12_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO12_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO12_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO12_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO12_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO12_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO12_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO12_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO12_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO12_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO12_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO12_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO12_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO12_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO12_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO12_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO12_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO12_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO12_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL12_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL12_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM12_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM12_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH12_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH12_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO13 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO13_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO13_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO13_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO13_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO13_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO13_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO13_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO13_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO13_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO13_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO13_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO13_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO13_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO13_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO13_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO13_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO13_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO13_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO13_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO13_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO13_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO13_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL13_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL13_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM13_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM13_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH13_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH13_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO14 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO14_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO14_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO14_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO14_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO14_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO14_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO14_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO14_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO14_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO14_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO14_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO14_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO14_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO14_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO14_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO14_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO14_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO14_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO14_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO14_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO14_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO14_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL14_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL14_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM14_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM14_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH14_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH14_VAL_S 0U + +//****************************************************************************** +// Register: FL1INFO15 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL1INFO15_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL1INFO15_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL1INFO15_RESERVED_W 11U +#define PBE_BLE5_RAM_FL1INFO15_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL1INFO15_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL1INFO15_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO15_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL1INFO15_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL1INFO15_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL1INFO15_FALIGN_S 2U +#define PBE_BLE5_RAM_FL1INFO15_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL1INFO15_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL1INFO15_TYPE 0x0002U +#define PBE_BLE5_RAM_FL1INFO15_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL1INFO15_TYPE_S 1U +#define PBE_BLE5_RAM_FL1INFO15_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL1INFO15_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL1INFO15_EN 0x0001U +#define PBE_BLE5_RAM_FL1INFO15_EN_M 0x0001U +#define PBE_BLE5_RAM_FL1INFO15_EN_S 0U +#define PBE_BLE5_RAM_FL1INFO15_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL1INFO15_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL1ADRL15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL1ADRL15_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRL15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRL15_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRM15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL1ADRM15_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRM15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRM15_VAL_S 0U + +//****************************************************************************** +// Register: FL1ADRH15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL1ADRH15_VAL_W 16U +#define PBE_BLE5_RAM_FL1ADRH15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL1ADRH15_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO0 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO0_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO0_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO0_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO0_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO0_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO0_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO0_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO0_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO0_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO0_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO0_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO0_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO0_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO0_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO0_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO0_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO0_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO0_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO0_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO0_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO0_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO0_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL0_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL0_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM0_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM0_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH0 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH0_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH0_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH0_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO1 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO1_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO1_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO1_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO1_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO1_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO1_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO1_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO1_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO1_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO1_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO1_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO1_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO1_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO1_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO1_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO1_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO1_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO1_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO1_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO1_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO1_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO1_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL1_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL1_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM1_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM1_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH1 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH1_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH1_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH1_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO2 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO2_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO2_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO2_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO2_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO2_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO2_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO2_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO2_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO2_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO2_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO2_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO2_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO2_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO2_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO2_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO2_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO2_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO2_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO2_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO2_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO2_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO2_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL2_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL2_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM2_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM2_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH2 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH2_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH2_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH2_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO3 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO3_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO3_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO3_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO3_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO3_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO3_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO3_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO3_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO3_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO3_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO3_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO3_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO3_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO3_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO3_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO3_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO3_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO3_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO3_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO3_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO3_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO3_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL3_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL3_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM3_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM3_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH3 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH3_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH3_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH3_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO4 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO4_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO4_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO4_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO4_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO4_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO4_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO4_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO4_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO4_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO4_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO4_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO4_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO4_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO4_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO4_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO4_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO4_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO4_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO4_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO4_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO4_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO4_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL4_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL4_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM4_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM4_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH4 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH4_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH4_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH4_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO5 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO5_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO5_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO5_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO5_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO5_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO5_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO5_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO5_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO5_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO5_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO5_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO5_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO5_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO5_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO5_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO5_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO5_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO5_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO5_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO5_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO5_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO5_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL5_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL5_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM5_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM5_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH5 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH5_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH5_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH5_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO6 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO6_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO6_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO6_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO6_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO6_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO6_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO6_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO6_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO6_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO6_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO6_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO6_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO6_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO6_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO6_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO6_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO6_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO6_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO6_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO6_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO6_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO6_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL6_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL6_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM6_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM6_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH6 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH6_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH6_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH6_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO7 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO7_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO7_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO7_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO7_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO7_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO7_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO7_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO7_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO7_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO7_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO7_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO7_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO7_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO7_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO7_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO7_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO7_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO7_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO7_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO7_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO7_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO7_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL7_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL7_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM7_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM7_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH7 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH7_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH7_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH7_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO8 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO8_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO8_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO8_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO8_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO8_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO8_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO8_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO8_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO8_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO8_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO8_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO8_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO8_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO8_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO8_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO8_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO8_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO8_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO8_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO8_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO8_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO8_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL8_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL8_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM8_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM8_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH8 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH8_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH8_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH8_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO9 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO9_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO9_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO9_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO9_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO9_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO9_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO9_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO9_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO9_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO9_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO9_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO9_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO9_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO9_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO9_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO9_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO9_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO9_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO9_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO9_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO9_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO9_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL9_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL9_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM9_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM9_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH9 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH9_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH9_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH9_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO10 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO10_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO10_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO10_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO10_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO10_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO10_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO10_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO10_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO10_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO10_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO10_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO10_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO10_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO10_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO10_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO10_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO10_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO10_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO10_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO10_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO10_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO10_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL10_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL10_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM10_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM10_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH10 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH10_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH10_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH10_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO11 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO11_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO11_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO11_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO11_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO11_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO11_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO11_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO11_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO11_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO11_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO11_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO11_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO11_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO11_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO11_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO11_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO11_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO11_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO11_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO11_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO11_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO11_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL11_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL11_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM11_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM11_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH11 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH11_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH11_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH11_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO12 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO12_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO12_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO12_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO12_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO12_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO12_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO12_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO12_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO12_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO12_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO12_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO12_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO12_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO12_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO12_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO12_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO12_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO12_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO12_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO12_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO12_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO12_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL12_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL12_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM12_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM12_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH12 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH12_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH12_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH12_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO13 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO13_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO13_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO13_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO13_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO13_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO13_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO13_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO13_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO13_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO13_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO13_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO13_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO13_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO13_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO13_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO13_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO13_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO13_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO13_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO13_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO13_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO13_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL13_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL13_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM13_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM13_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH13 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH13_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH13_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH13_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO14 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO14_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO14_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO14_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO14_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO14_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO14_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO14_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO14_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO14_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO14_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO14_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO14_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO14_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO14_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO14_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO14_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO14_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO14_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO14_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO14_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO14_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO14_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL14_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL14_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM14_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM14_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH14 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH14_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH14_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH14_VAL_S 0U + +//****************************************************************************** +// Register: FL2INFO15 +//****************************************************************************** +// Field: [15:15] matchtmp +// +// Temporary variable used in matching, ignore from CM0 +#define PBE_BLE5_RAM_FL2INFO15_MATCHTMP 0x8000U +#define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_M 0x8000U +#define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_S 15U +#define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_NOMATCH 0x0000U +#define PBE_BLE5_RAM_FL2INFO15_MATCHTMP_MATCH 0x8000U + +// Field: [14:4] reserved +// +// Reserved for future use +#define PBE_BLE5_RAM_FL2INFO15_RESERVED_W 11U +#define PBE_BLE5_RAM_FL2INFO15_RESERVED_M 0x7FF0U +#define PBE_BLE5_RAM_FL2INFO15_RESERVED_S 4U + +// Field: [3:3] privign +// +// Ignore control for privacy +#define PBE_BLE5_RAM_FL2INFO15_PRIVIGN 0x0008U +#define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_M 0x0008U +#define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_S 3U +#define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO15_PRIVIGN_IGN 0x0008U + +// Field: [2:2] falign +// +// Ignore in accept list context +#define PBE_BLE5_RAM_FL2INFO15_FALIGN 0x0004U +#define PBE_BLE5_RAM_FL2INFO15_FALIGN_M 0x0004U +#define PBE_BLE5_RAM_FL2INFO15_FALIGN_S 2U +#define PBE_BLE5_RAM_FL2INFO15_FALIGN_NIGN 0x0000U +#define PBE_BLE5_RAM_FL2INFO15_FALIGN_IGN 0x0004U + +// Field: [1:1] type +// +// Address type +#define PBE_BLE5_RAM_FL2INFO15_TYPE 0x0002U +#define PBE_BLE5_RAM_FL2INFO15_TYPE_M 0x0002U +#define PBE_BLE5_RAM_FL2INFO15_TYPE_S 1U +#define PBE_BLE5_RAM_FL2INFO15_TYPE_PUBLIC 0x0000U +#define PBE_BLE5_RAM_FL2INFO15_TYPE_RANDOM 0x0002U + +// Field: [0:0] en +// +// Enable +#define PBE_BLE5_RAM_FL2INFO15_EN 0x0001U +#define PBE_BLE5_RAM_FL2INFO15_EN_M 0x0001U +#define PBE_BLE5_RAM_FL2INFO15_EN_S 0U +#define PBE_BLE5_RAM_FL2INFO15_EN_DIS 0x0000U +#define PBE_BLE5_RAM_FL2INFO15_EN_EN 0x0001U + +//****************************************************************************** +// Register: FL2ADRL15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_BLE5_RAM_FL2ADRL15_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRL15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRL15_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRM15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_BLE5_RAM_FL2ADRM15_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRM15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRM15_VAL_S 0U + +//****************************************************************************** +// Register: FL2ADRH15 +//****************************************************************************** +// Field: [15:0] val +// +// bits 47:32 of address +#define PBE_BLE5_RAM_FL2ADRH15_VAL_W 16U +#define PBE_BLE5_RAM_FL2ADRH15_VAL_M 0xFFFFU +#define PBE_BLE5_RAM_FL2ADRH15_VAL_S 0U + + +#endif // __PBE_BLE5_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_regdef_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_regdef_regs.h new file mode 100644 index 00000000..00045c38 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble5_regdef_regs.h @@ -0,0 +1,204 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:00 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5 +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble5/doc/pbe_ble5_regdef_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 753310d49982671f410f10b434972b7c27836bba +// +// =========================================================================== + + +#ifndef __PBE_BLE5_REGDEF_REGS_H +#define __PBE_BLE5_REGDEF_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// Packet Building Engine (PBE) interrupt generation register +#define PBE_BLE5_REGDEF_O_IRQ 0x00000010U + +// PBE API Operation Register +#define PBE_BLE5_REGDEF_O_API 0x00000030U + +//****************************************************************************** +// Register: IRQ +//****************************************************************************** +// Field: [15:15] operror +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_OPERROR 0x00008000U +#define PBE_BLE5_REGDEF_IRQ_OPERROR_M 0x00008000U +#define PBE_BLE5_REGDEF_IRQ_OPERROR_S 15U +#define PBE_BLE5_REGDEF_IRQ_OPERROR_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_OPERROR_ACTIVE 0x00008000U + +// Field: [14:14] unused14 +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_UNUSED14 0x00004000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED14_M 0x00004000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED14_S 14U +#define PBE_BLE5_REGDEF_IRQ_UNUSED14_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED14_ACTIVE 0x00004000U + +// Field: [13:13] txdone +// +// Packet transmitted. MCU shall deallocate or retry. +#define PBE_BLE5_REGDEF_IRQ_TXDONE 0x00002000U +#define PBE_BLE5_REGDEF_IRQ_TXDONE_M 0x00002000U +#define PBE_BLE5_REGDEF_IRQ_TXDONE_S 13U +#define PBE_BLE5_REGDEF_IRQ_TXDONE_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_TXDONE_ACTIVE 0x00002000U + +// Field: [12:12] txack +// +// Acknowledgement received on a transmitted packet. +#define PBE_BLE5_REGDEF_IRQ_TXACK 0x00001000U +#define PBE_BLE5_REGDEF_IRQ_TXACK_M 0x00001000U +#define PBE_BLE5_REGDEF_IRQ_TXACK_S 12U +#define PBE_BLE5_REGDEF_IRQ_TXACK_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_TXACK_ACTIVE 0x00001000U + +// Field: [11:11] txretrans +// +// Packet retransmitted with same SN. +#define PBE_BLE5_REGDEF_IRQ_TXRETRANS 0x00000800U +#define PBE_BLE5_REGDEF_IRQ_TXRETRANS_M 0x00000800U +#define PBE_BLE5_REGDEF_IRQ_TXRETRANS_S 11U +#define PBE_BLE5_REGDEF_IRQ_TXRETRANS_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_TXRETRANS_ACTIVE 0x00000800U + +// Field: [10:10] unused10 +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_UNUSED10 0x00000400U +#define PBE_BLE5_REGDEF_IRQ_UNUSED10_M 0x00000400U +#define PBE_BLE5_REGDEF_IRQ_UNUSED10_S 10U +#define PBE_BLE5_REGDEF_IRQ_UNUSED10_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED10_ACTIVE 0x00000400U + +// Field: [9:9] unused9 +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_UNUSED9 0x00000200U +#define PBE_BLE5_REGDEF_IRQ_UNUSED9_M 0x00000200U +#define PBE_BLE5_REGDEF_IRQ_UNUSED9_S 9U +#define PBE_BLE5_REGDEF_IRQ_UNUSED9_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED9_ACTIVE 0x00000200U + +// Field: [8:8] rxok +// +// Packet received with CRC OK and not to be ignored by the MCU +#define PBE_BLE5_REGDEF_IRQ_RXOK 0x00000100U +#define PBE_BLE5_REGDEF_IRQ_RXOK_M 0x00000100U +#define PBE_BLE5_REGDEF_IRQ_RXOK_S 8U +#define PBE_BLE5_REGDEF_IRQ_RXOK_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_RXOK_ACTIVE 0x00000100U + +// Field: [7:7] rxfovfl +// +// Packet received which did not fit in the RX FIFO and was not to be discarded. +#define PBE_BLE5_REGDEF_IRQ_RXFOVFL 0x00000080U +#define PBE_BLE5_REGDEF_IRQ_RXFOVFL_M 0x00000080U +#define PBE_BLE5_REGDEF_IRQ_RXFOVFL_S 7U +#define PBE_BLE5_REGDEF_IRQ_RXFOVFL_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_RXFOVFL_ACTIVE 0x00000080U + +// Field: [6:6] rxempty +// +// Empty packet received, payload is zero. +#define PBE_BLE5_REGDEF_IRQ_RXEMPTY 0x00000040U +#define PBE_BLE5_REGDEF_IRQ_RXEMPTY_M 0x00000040U +#define PBE_BLE5_REGDEF_IRQ_RXEMPTY_S 6U +#define PBE_BLE5_REGDEF_IRQ_RXEMPTY_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_RXEMPTY_ACTIVE 0x00000040U + +// Field: [5:5] rxign +// +// Packet received with correct CRC, but may be ignored by MCU +#define PBE_BLE5_REGDEF_IRQ_RXIGN 0x00000020U +#define PBE_BLE5_REGDEF_IRQ_RXIGN_M 0x00000020U +#define PBE_BLE5_REGDEF_IRQ_RXIGN_S 5U +#define PBE_BLE5_REGDEF_IRQ_RXIGN_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_RXIGN_ACTIVE 0x00000020U + +// Field: [4:4] rxnok +// +// Packet received with CRC error, no data may be trusted +#define PBE_BLE5_REGDEF_IRQ_RXNOK 0x00000010U +#define PBE_BLE5_REGDEF_IRQ_RXNOK_M 0x00000010U +#define PBE_BLE5_REGDEF_IRQ_RXNOK_S 4U +#define PBE_BLE5_REGDEF_IRQ_RXNOK_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_RXNOK_ACTIVE 0x00000010U + +// Field: [3:3] unused3 +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_UNUSED3 0x00000008U +#define PBE_BLE5_REGDEF_IRQ_UNUSED3_M 0x00000008U +#define PBE_BLE5_REGDEF_IRQ_UNUSED3_S 3U +#define PBE_BLE5_REGDEF_IRQ_UNUSED3_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED3_ACTIVE 0x00000008U + +// Field: [2:2] unused2 +// +// Software defined interrupt +#define PBE_BLE5_REGDEF_IRQ_UNUSED2 0x00000004U +#define PBE_BLE5_REGDEF_IRQ_UNUSED2_M 0x00000004U +#define PBE_BLE5_REGDEF_IRQ_UNUSED2_S 2U +#define PBE_BLE5_REGDEF_IRQ_UNUSED2_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_UNUSED2_ACTIVE 0x00000004U + +// Field: [1:1] pingrsp +// +// PBE responds to PBEOP_PING, basic test to see if the battery is connected. +#define PBE_BLE5_REGDEF_IRQ_PINGRSP 0x00000002U +#define PBE_BLE5_REGDEF_IRQ_PINGRSP_M 0x00000002U +#define PBE_BLE5_REGDEF_IRQ_PINGRSP_S 1U +#define PBE_BLE5_REGDEF_IRQ_PINGRSP_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_PINGRSP_ACTIVE 0x00000002U + +// Field: [0:0] opdone +// +// The operation commanded on PBEAPI has completed succesfully. +#define PBE_BLE5_REGDEF_IRQ_OPDONE 0x00000001U +#define PBE_BLE5_REGDEF_IRQ_OPDONE_M 0x00000001U +#define PBE_BLE5_REGDEF_IRQ_OPDONE_S 0U +#define PBE_BLE5_REGDEF_IRQ_OPDONE_OFF 0x00000000U +#define PBE_BLE5_REGDEF_IRQ_OPDONE_ACTIVE 0x00000001U + +//****************************************************************************** +// Register: API +//****************************************************************************** +// Field: [4:0] op +// +// PBE Operation +#define PBE_BLE5_REGDEF_API_OP_W 5U +#define PBE_BLE5_REGDEF_API_OP_M 0x0000001FU +#define PBE_BLE5_REGDEF_API_OP_S 0U +#define PBE_BLE5_REGDEF_API_OP_PING 0x00000000U +#define PBE_BLE5_REGDEF_API_OP_STOP 0x00000001U +#define PBE_BLE5_REGDEF_API_OP_EOPSTOP 0x00000002U +#define PBE_BLE5_REGDEF_API_OP_PERIPHERAL 0x00000003U +#define PBE_BLE5_REGDEF_API_OP_CENTRAL 0x00000004U +#define PBE_BLE5_REGDEF_API_OP_ADV 0x00000005U +#define PBE_BLE5_REGDEF_API_OP_SCAN 0x00000006U +#define PBE_BLE5_REGDEF_API_OP_INITIATOR 0x00000007U +#define PBE_BLE5_REGDEF_API_OP_RXRAW 0x00000008U +#define PBE_BLE5_REGDEF_API_OP_TXRAW 0x00000009U + + +#endif // __PBE_BLE5_REGDEF_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_ram_regs.h new file mode 100644 index 00000000..d4d007ff --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_ram_regs.h @@ -0,0 +1,696 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:01 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 8bfaeeaefba74967a4e950e027534072ffcb9647 +// +// =========================================================================== + + +#ifndef __PBE_BLE_CS_RAM_REGS_H +#define __PBE_BLE_CS_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// +#define PBE_BLE_CS_RAM_O_MODE 0x00000020U + +// +#define PBE_BLE_CS_RAM_O_ANTMSK 0x00000022U + +// +#define PBE_BLE_CS_RAM_O_ANT0 0x00000024U + +// +#define PBE_BLE_CS_RAM_O_ANT1 0x00000026U + +// +#define PBE_BLE_CS_RAM_O_ANT2 0x00000028U + +// +#define PBE_BLE_CS_RAM_O_ANT3 0x0000002AU + +// +#define PBE_BLE_CS_RAM_O_ANTN 0x0000002CU + +// +#define PBE_BLE_CS_RAM_O_TFCS 0x0000002EU + +// +#define PBE_BLE_CS_RAM_O_TFM 0x00000030U + +// +#define PBE_BLE_CS_RAM_O_TPM 0x00000032U + +// +#define PBE_BLE_CS_RAM_O_TIP1 0x00000034U + +// +#define PBE_BLE_CS_RAM_O_TIP2 0x00000036U + +// +#define PBE_BLE_CS_RAM_O_TRXTIMEOUTR013 0x00000038U + +// +#define PBE_BLE_CS_RAM_O_TRXTIMEOUTI0 0x0000003AU + +// +#define PBE_BLE_CS_RAM_O_TRXTIMEOUTI3 0x0000003CU + +// +#define PBE_BLE_CS_RAM_O_TPILOTADJ 0x0000003EU + +// +#define PBE_BLE_CS_RAM_O_TSW 0x00000040U + +// +#define PBE_BLE_CS_RAM_O_DEMMISC3 0x00000042U + +// +#define PBE_BLE_CS_RAM_O_TRXWIDENINGR0 0x00000044U + +// +#define PBE_BLE_CS_RAM_O_TSTEPREMAININGR0 0x00000046U + +// +#define PBE_BLE_CS_RAM_O_TSWADJA 0x00000048U + +// +#define PBE_BLE_CS_RAM_O_TSWADJB 0x0000004AU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTIDX 0x0000004CU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTCHIDX 0x0000004EU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTWORDSIZE 0x00000050U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOADLEN 0x00000052U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD0L 0x00000054U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD0H 0x00000056U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD1L 0x00000058U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD1H 0x0000005AU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD2L 0x0000005CU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD2H 0x0000005EU + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD3L 0x00000060U + +// +#define PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD3H 0x00000062U + +// +#define PBE_BLE_CS_RAM_O_FOFFSUM 0x00000064U + +// +#define PBE_BLE_CS_RAM_O_FOFFNUM 0x00000066U + +// +#define PBE_BLE_CS_RAM_O_FOFFLAST 0x00000068U + +// +#define PBE_BLE_CS_RAM_O_FOFFCOMP 0x0000006AU + +// +#define PBE_BLE_CS_RAM_O_RSSILAST 0x0000006CU + +// +#define PBE_BLE_CS_RAM_O_RSSISUM0 0x0000006EU + +// +#define PBE_BLE_CS_RAM_O_RSSINUM0 0x00000070U + +// +#define PBE_BLE_CS_RAM_O_NSTEPSDONE 0x00000072U + +// +#define PBE_BLE_CS_RAM_O_TSTEPACCL 0x00000074U + +// +#define PBE_BLE_CS_RAM_O_TSTEPACCH 0x00000076U + +// +#define PBE_BLE_CS_RAM_O_TSTEPACCTHRL 0x00000078U + +// +#define PBE_BLE_CS_RAM_O_TSTEPACCTHRH 0x0000007AU + +// +#define PBE_BLE_CS_RAM_O_TSTEPCOMP 0x0000007CU + +// +#define PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV1 0x0000007EU + +// +#define PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV12 0x00000080U + +//****************************************************************************** +// Register: MODE +//****************************************************************************** +// Field: [15:8] num_steps +// +// +#define PBE_BLE_CS_RAM_MODE_NUM_STEPS_W 8U +#define PBE_BLE_CS_RAM_MODE_NUM_STEPS_M 0xFF00U +#define PBE_BLE_CS_RAM_MODE_NUM_STEPS_S 8U + +// Field: [7:3] num_s2r +// +// +#define PBE_BLE_CS_RAM_MODE_NUM_S2R_W 5U +#define PBE_BLE_CS_RAM_MODE_NUM_S2R_M 0x00F8U +#define PBE_BLE_CS_RAM_MODE_NUM_S2R_S 3U + +// Field: [2:2] infinit +// +// +#define PBE_BLE_CS_RAM_MODE_INFINIT 0x0004U +#define PBE_BLE_CS_RAM_MODE_INFINIT_M 0x0004U +#define PBE_BLE_CS_RAM_MODE_INFINIT_S 2U + +// Field: [1:1] phy +// +// +#define PBE_BLE_CS_RAM_MODE_PHY 0x0002U +#define PBE_BLE_CS_RAM_MODE_PHY_M 0x0002U +#define PBE_BLE_CS_RAM_MODE_PHY_S 1U + +// Field: [0:0] role +// +// +#define PBE_BLE_CS_RAM_MODE_ROLE 0x0001U +#define PBE_BLE_CS_RAM_MODE_ROLE_M 0x0001U +#define PBE_BLE_CS_RAM_MODE_ROLE_S 0U + +//****************************************************************************** +// Register: ANTMSK +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANTMSK_VAL_W 8U +#define PBE_BLE_CS_RAM_ANTMSK_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANTMSK_VAL_S 0U + +//****************************************************************************** +// Register: ANT0 +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANT0_VAL_W 8U +#define PBE_BLE_CS_RAM_ANT0_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANT0_VAL_S 0U + +//****************************************************************************** +// Register: ANT1 +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANT1_VAL_W 8U +#define PBE_BLE_CS_RAM_ANT1_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANT1_VAL_S 0U + +//****************************************************************************** +// Register: ANT2 +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANT2_VAL_W 8U +#define PBE_BLE_CS_RAM_ANT2_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANT2_VAL_S 0U + +//****************************************************************************** +// Register: ANT3 +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANT3_VAL_W 8U +#define PBE_BLE_CS_RAM_ANT3_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANT3_VAL_S 0U + +//****************************************************************************** +// Register: ANTN +//****************************************************************************** +// Field: [7:0] val +// +// +#define PBE_BLE_CS_RAM_ANTN_VAL_W 8U +#define PBE_BLE_CS_RAM_ANTN_VAL_M 0x00FFU +#define PBE_BLE_CS_RAM_ANTN_VAL_S 0U + +//****************************************************************************** +// Register: TFCS +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TFCS_VAL_W 16U +#define PBE_BLE_CS_RAM_TFCS_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TFCS_VAL_S 0U + +//****************************************************************************** +// Register: TFM +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TFM_VAL_W 16U +#define PBE_BLE_CS_RAM_TFM_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TFM_VAL_S 0U + +//****************************************************************************** +// Register: TPM +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TPM_VAL_W 16U +#define PBE_BLE_CS_RAM_TPM_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TPM_VAL_S 0U + +//****************************************************************************** +// Register: TIP1 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TIP1_VAL_W 16U +#define PBE_BLE_CS_RAM_TIP1_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TIP1_VAL_S 0U + +//****************************************************************************** +// Register: TIP2 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TIP2_VAL_W 16U +#define PBE_BLE_CS_RAM_TIP2_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TIP2_VAL_S 0U + +//****************************************************************************** +// Register: TRXTIMEOUTR013 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_W 16U +#define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TRXTIMEOUTR013_VAL_S 0U + +//****************************************************************************** +// Register: TRXTIMEOUTI0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_W 16U +#define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TRXTIMEOUTI0_VAL_S 0U + +//****************************************************************************** +// Register: TRXTIMEOUTI3 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_W 16U +#define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TRXTIMEOUTI3_VAL_S 0U + +//****************************************************************************** +// Register: TPILOTADJ +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TPILOTADJ_VAL_W 16U +#define PBE_BLE_CS_RAM_TPILOTADJ_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TPILOTADJ_VAL_S 0U + +//****************************************************************************** +// Register: TSW +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSW_VAL_W 16U +#define PBE_BLE_CS_RAM_TSW_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSW_VAL_S 0U + +//****************************************************************************** +// Register: DEMMISC3 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_DEMMISC3_VAL_W 16U +#define PBE_BLE_CS_RAM_DEMMISC3_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_DEMMISC3_VAL_S 0U + +//****************************************************************************** +// Register: TRXWIDENINGR0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_W 16U +#define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TRXWIDENINGR0_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPREMAININGR0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPREMAININGR0_VAL_S 0U + +//****************************************************************************** +// Register: TSWADJA +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSWADJA_VAL_W 16U +#define PBE_BLE_CS_RAM_TSWADJA_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSWADJA_VAL_S 0U + +//****************************************************************************** +// Register: TSWADJB +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSWADJB_VAL_W 16U +#define PBE_BLE_CS_RAM_TSWADJB_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSWADJB_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTIDX +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTIDX_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTCHIDX +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTCHIDX_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTWORDSIZE +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTWORDSIZE_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOADLEN +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOADLEN_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD0L +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0L_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD0H +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD0H_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD1L +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1L_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD1H +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD1H_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD2L +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2L_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD2H +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD2H_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD3L +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3L_VAL_S 0U + +//****************************************************************************** +// Register: S2ROUTPAYLOAD3H +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_W 16U +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_S2ROUTPAYLOAD3H_VAL_S 0U + +//****************************************************************************** +// Register: FOFFSUM +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_FOFFSUM_VAL_W 16U +#define PBE_BLE_CS_RAM_FOFFSUM_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_FOFFSUM_VAL_S 0U + +//****************************************************************************** +// Register: FOFFNUM +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_FOFFNUM_VAL_W 16U +#define PBE_BLE_CS_RAM_FOFFNUM_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_FOFFNUM_VAL_S 0U + +//****************************************************************************** +// Register: FOFFLAST +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_FOFFLAST_VAL_W 16U +#define PBE_BLE_CS_RAM_FOFFLAST_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_FOFFLAST_VAL_S 0U + +//****************************************************************************** +// Register: FOFFCOMP +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_FOFFCOMP_VAL_W 16U +#define PBE_BLE_CS_RAM_FOFFCOMP_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_FOFFCOMP_VAL_S 0U + +//****************************************************************************** +// Register: RSSILAST +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_RSSILAST_VAL_W 16U +#define PBE_BLE_CS_RAM_RSSILAST_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_RSSILAST_VAL_S 0U + +//****************************************************************************** +// Register: RSSISUM0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_RSSISUM0_VAL_W 16U +#define PBE_BLE_CS_RAM_RSSISUM0_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_RSSISUM0_VAL_S 0U + +//****************************************************************************** +// Register: RSSINUM0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_RSSINUM0_VAL_W 16U +#define PBE_BLE_CS_RAM_RSSINUM0_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_RSSINUM0_VAL_S 0U + +//****************************************************************************** +// Register: NSTEPSDONE +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_W 16U +#define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_NSTEPSDONE_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPACCL +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPACCL_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPACCL_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPACCL_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPACCH +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPACCH_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPACCH_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPACCH_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPACCTHRL +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPACCTHRL_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPACCTHRH +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPACCTHRH_VAL_S 0U + +//****************************************************************************** +// Register: TSTEPCOMP +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_W 16U +#define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TSTEPCOMP_VAL_S 0U + +//****************************************************************************** +// Register: TPOSTPROCESSDIV1 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_W 16U +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV1_VAL_S 0U + +//****************************************************************************** +// Register: TPOSTPROCESSDIV12 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_W 16U +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_M 0xFFFFU +#define PBE_BLE_CS_RAM_TPOSTPROCESSDIV12_VAL_S 0U + + +#endif // __PBE_BLE_CS_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_regdef_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_regdef_regs.h new file mode 100644 index 00000000..b0deae93 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ble_cs_regdef_regs.h @@ -0,0 +1,48 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:02 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ble_cs/doc/pbe_ble_cs_regdef_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 622b06341c4551904e7b7c1dc6b2c1df5d995fdb +// +// =========================================================================== + + +#ifndef __PBE_BLE_CS_REGDEF_REGS_H +#define __PBE_BLE_CS_REGDEF_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// PBE API Operation Register +#define PBE_BLE_CS_REGDEF_O_API 0x00000030U + +//****************************************************************************** +// Register: API +//****************************************************************************** +// Field: [4:0] op +// +// PBE Operation +#define PBE_BLE_CS_REGDEF_API_OP_W 5U +#define PBE_BLE_CS_REGDEF_API_OP_M 0x0000001FU +#define PBE_BLE_CS_REGDEF_API_OP_S 0U +#define PBE_BLE_CS_REGDEF_API_OP_PING 0x00000000U +#define PBE_BLE_CS_REGDEF_API_OP_STOP 0x00000001U +#define PBE_BLE_CS_REGDEF_API_OP_BLE_CS 0x00000002U +#define PBE_BLE_CS_REGDEF_API_OP_PRECAL 0x00000003U + + +#endif // __PBE_BLE_CS_REGDEF_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_common_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_common_ram_regs.h new file mode 100644 index 00000000..91bd3880 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_common_ram_regs.h @@ -0,0 +1,111 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:08:58 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/common/doc/pbe_common_ram_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/common/doc/pbe_common_ram_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/common/doc/pbe_common_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: cef3659936323c87a91f6983db5e9f40a1f01b57 +// +// =========================================================================== + + +#ifndef __PBE_COMMON_RAM_REGS_H +#define __PBE_COMMON_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// +#define PBE_COMMON_RAM_O_CMDPAR0 0x00000000U + +// +#define PBE_COMMON_RAM_O_CMDPAR1 0x00000002U + +// +#define PBE_COMMON_RAM_O_MSGBOX 0x00000004U + +// Reason why PBE ended operation. +#define PBE_COMMON_RAM_O_ENDCAUSE 0x00000006U + +// +#define PBE_COMMON_RAM_O_FIFOCMDADD 0x00000008U + +//****************************************************************************** +// Register: CMDPAR0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_COMMON_RAM_CMDPAR0_VAL_W 16U +#define PBE_COMMON_RAM_CMDPAR0_VAL_M 0xFFFFU +#define PBE_COMMON_RAM_CMDPAR0_VAL_S 0U + +//****************************************************************************** +// Register: CMDPAR1 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_COMMON_RAM_CMDPAR1_VAL_W 16U +#define PBE_COMMON_RAM_CMDPAR1_VAL_M 0xFFFFU +#define PBE_COMMON_RAM_CMDPAR1_VAL_S 0U + +//****************************************************************************** +// Register: MSGBOX +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_COMMON_RAM_MSGBOX_VAL_W 16U +#define PBE_COMMON_RAM_MSGBOX_VAL_M 0xFFFFU +#define PBE_COMMON_RAM_MSGBOX_VAL_S 0U + +//****************************************************************************** +// Register: ENDCAUSE +//****************************************************************************** +// Field: [7:0] stat +// +// +#define PBE_COMMON_RAM_ENDCAUSE_STAT_W 8U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_M 0x00FFU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_S 0U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK 0x0000U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_RXTIMEOUT 0x0001U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC 0x0002U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_RXERR 0x0003U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_CONNECT 0x0004U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_MAXNAK 0x0006U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_SCANRSP 0x0006U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP 0x0007U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_RXF 0x00F9U +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_TXF 0x00FAU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_SYNTH 0x00FBU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP 0x00FCU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_PAR 0x00FDU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_BADOP 0x00FEU +#define PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_INTERNAL 0x00FFU + +//****************************************************************************** +// Register: FIFOCMDADD +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_COMMON_RAM_FIFOCMDADD_VAL_W 16U +#define PBE_COMMON_RAM_FIFOCMDADD_VAL_M 0xFFFFU +#define PBE_COMMON_RAM_FIFOCMDADD_VAL_S 0U + + +#endif // __PBE_COMMON_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_ram_regs.h new file mode 100644 index 00000000..c8e20f12 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_ram_regs.h @@ -0,0 +1,1550 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:01 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: e341d2d047097f8c7281906c9724785f4a71526a +// +// =========================================================================== + + +#ifndef __PBE_GENERIC_RAM_REGS_H +#define __PBE_GENERIC_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// +#define PBE_GENERIC_RAM_O_PHY 0x00000020U + +// +#define PBE_GENERIC_RAM_O_SYNTHCALTIMEOUT 0x00000022U + +// Packet configuration (common between TX and RX) +#define PBE_GENERIC_RAM_O_PKTCFG 0x00000024U + +// +#define PBE_GENERIC_RAM_O_NUMCRCBITS 0x00000026U + +// Configure FIFO usage +#define PBE_GENERIC_RAM_O_FIFOCFG 0x00000028U + +// +#define PBE_GENERIC_RAM_O_EXTRABYTES 0x0000002AU + +// Initialization for the whitener, if 0 the whitener is not used +#define PBE_GENERIC_RAM_O_WHITEINIT 0x0000002CU + +// CRC initialization value +#define PBE_GENERIC_RAM_O_CRCINITL 0x00000030U + +// CRC initialization value +#define PBE_GENERIC_RAM_O_CRCINITH 0x00000032U + +// Length field configuration +#define PBE_GENERIC_RAM_O_LENCFG 0x00000034U + +// +#define PBE_GENERIC_RAM_O_LENOFFSET 0x00000036U + +// +#define PBE_GENERIC_RAM_O_FIRSTRXTIMEOUT 0x00000038U + +// How long to search for sync before giving up +#define PBE_GENERIC_RAM_O_RXTIMEOUT 0x0000003AU + +// +#define PBE_GENERIC_RAM_O_RFINTERVAL 0x0000003CU + +// +#define PBE_GENERIC_RAM_O_PRETXIFS 0x0000003EU + +// +#define PBE_GENERIC_RAM_O_PRERXIFS 0x00000040U + +// combined tx/rx/fs configuration +#define PBE_GENERIC_RAM_O_OPCFG 0x00000042U + +// Maximum allowed packet length in RX +#define PBE_GENERIC_RAM_O_MAXLEN 0x00000044U + +// +#define PBE_GENERIC_RAM_O_PATTERN 0x00000046U + +// Address filtering config +#define PBE_GENERIC_RAM_O_ADDRCFG 0x00000048U + +// Address filtering config +#define PBE_GENERIC_RAM_O_ADDRSW 0x0000004AU + +// +#define PBE_GENERIC_RAM_O_TESTCFG 0x0000004CU + +// +#define PBE_GENERIC_RAM_O_TESTAPI 0x0000004EU + +// +#define PBE_GENERIC_RAM_O_TESTTIMEOUT 0x00000050U + +// +#define PBE_GENERIC_RAM_O_ADD0 0x00000054U + +// +#define PBE_GENERIC_RAM_O_ADD1 0x00000056U + +// +#define PBE_GENERIC_RAM_O_ADD2 0x00000058U + +// +#define PBE_GENERIC_RAM_O_ADD3 0x0000005AU + +// +#define PBE_GENERIC_RAM_O_ADD4 0x0000005CU + +// +#define PBE_GENERIC_RAM_O_ADD5 0x0000005EU + +// +#define PBE_GENERIC_RAM_O_ADD6 0x00000060U + +// +#define PBE_GENERIC_RAM_O_ADD7 0x00000062U + +// +#define PBE_GENERIC_RAM_O_ADD8 0x00000064U + +// +#define PBE_GENERIC_RAM_O_ADD9 0x00000066U + +// +#define PBE_GENERIC_RAM_O_ADD10 0x00000068U + +// +#define PBE_GENERIC_RAM_O_ADD11 0x0000006AU + +// +#define PBE_GENERIC_RAM_O_ADD12 0x0000006CU + +// +#define PBE_GENERIC_RAM_O_ADD13 0x0000006EU + +// +#define PBE_GENERIC_RAM_O_ADD15 0x00000070U + +// +#define PBE_GENERIC_RAM_O_NRXNOK 0x00000072U + +// +#define PBE_GENERIC_RAM_O_NRXIGNORED 0x00000074U + +// +#define PBE_GENERIC_RAM_O_NRXEMPTY 0x00000076U + +// +#define PBE_GENERIC_RAM_O_NRXFIFOFULL 0x00000078U + +// +#define PBE_GENERIC_RAM_O_NRXOK 0x0000007AU + +// +#define PBE_GENERIC_RAM_O_NTX 0x0000007CU + +// +#define PBE_GENERIC_RAM_O_NRXTIMEOUT 0x0000007EU + +// +#define PBE_GENERIC_RAM_O_LASTRSSI 0x00000080U + +// +#define PBE_GENERIC_RAM_O_LASTFREQOFF 0x00000082U + +// +#define PBE_GENERIC_RAM_O_LASTLQI 0x00000084U + +// +#define PBE_GENERIC_RAM_O_LASTTIMESTAMPL 0x00000088U + +// +#define PBE_GENERIC_RAM_O_LASTTIMESTAMPH 0x0000008AU + +// +#define PBE_GENERIC_RAM_O_PEERADRINFO 0x0000008CU + +// Peer address list for syncwordA (MDMSYNCA*) +#define PBE_GENERIC_RAM_O_PEERADR1AL 0x0000008EU + +// Peer address list for syncwordA (MDMSYNCA*) +#define PBE_GENERIC_RAM_O_PEERADR1AH 0x00000090U + +// Peer address list for syncwordA (MDMSYNCA*) +#define PBE_GENERIC_RAM_O_PEERADR0AL 0x00000092U + +// Peer address list for syncwordA (MDMSYNCA*) +#define PBE_GENERIC_RAM_O_PEERADR0AH 0x00000094U + +// Peer address list for syncwordB (MDMSYNCB*) +#define PBE_GENERIC_RAM_O_PEERADR1BL 0x00000096U + +// Peer address list for syncwordB (MDMSYNCB*) +#define PBE_GENERIC_RAM_O_PEERADR1BH 0x00000098U + +// Peer address list for syncwordB (MDMSYNCB*) +#define PBE_GENERIC_RAM_O_PEERADR0BL 0x0000009AU + +// Peer address list for syncwordB (MDMSYNCB*) +#define PBE_GENERIC_RAM_O_PEERADR0BH 0x0000009CU + +// Nordic Enhanced Shock Burst configuration shared for both PTX and PRX devices. +#define PBE_GENERIC_RAM_O_NESB 0x0000009EU + +// NESB feature. CRC value (last two bytes if more than 2 CRC bytes) of last successfully received packet with syncWord0. +#define PBE_GENERIC_RAM_O_CRCVAL0 0x000000A0U + +// Sequencing or Pkt ID status +#define PBE_GENERIC_RAM_O_SEQSTAT0 0x000000A2U + +// NESB feature. CRC value (first two bytes if more than 2 CRC bytes) of first successfully received packet with syncWord1. +#define PBE_GENERIC_RAM_O_CRCVAL1 0x000000A4U + +// Sequencing or Pkt ID status +#define PBE_GENERIC_RAM_O_SEQSTAT1 0x000000A6U + +// Status for the received packet, appended in the RX FIFO depending on FIFOCFG. +#define PBE_GENERIC_RAM_O_STATUSBYTE 0x000000A8U + +// Temporary register for storing header byte +#define PBE_GENERIC_RAM_O_TMPBYTE1 0x000000AAU + +// Temporary register for storing header byte +#define PBE_GENERIC_RAM_O_TMPBYTE2 0x000000ACU + +// Temporary register for storing header byte +#define PBE_GENERIC_RAM_O_TMPBYTE3 0x000000AEU + +// Temporary register for storing header byte +#define PBE_GENERIC_RAM_O_TMPBYTE4 0x000000B0U + +// Temporary register for storing RSSI +#define PBE_GENERIC_RAM_O_TMPRSSI 0x000000B2U + +// Temporary address register +#define PBE_GENERIC_RAM_O_TMPADR1 0x000000B4U + +// Temporary address register +#define PBE_GENERIC_RAM_O_TMPADR2 0x000000B6U + +// Temporary address register +#define PBE_GENERIC_RAM_O_TMPADR3 0x000000B8U + +// Temporary address register +#define PBE_GENERIC_RAM_O_TMPADR4 0x000000BAU + +//****************************************************************************** +// Register: PHY +//****************************************************************************** +// Field: [5:3] rfesel +// +// Used to pass on the value of the Coding Indicator to the RFE. +#define PBE_GENERIC_RAM_PHY_RFESEL_W 3U +#define PBE_GENERIC_RAM_PHY_RFESEL_M 0x0038U +#define PBE_GENERIC_RAM_PHY_RFESEL_S 3U +#define PBE_GENERIC_RAM_PHY_RFESEL_1M 0x0000U +#define PBE_GENERIC_RAM_PHY_RFESEL_2M 0x0008U +#define PBE_GENERIC_RAM_PHY_RFESEL_CODED_125K 0x0010U +#define PBE_GENERIC_RAM_PHY_RFESEL_CODED_500K 0x0018U + +// Field: [2:0] mcesel +// +// Used to pass on the value of the Coding Indicator to the MCE. +#define PBE_GENERIC_RAM_PHY_MCESEL_W 3U +#define PBE_GENERIC_RAM_PHY_MCESEL_M 0x0007U +#define PBE_GENERIC_RAM_PHY_MCESEL_S 0U +#define PBE_GENERIC_RAM_PHY_MCESEL_1M 0x0000U +#define PBE_GENERIC_RAM_PHY_MCESEL_2M 0x0001U +#define PBE_GENERIC_RAM_PHY_MCESEL_CODED_125K 0x0002U +#define PBE_GENERIC_RAM_PHY_MCESEL_CODED_500K 0x0003U + +//****************************************************************************** +// Register: SYNTHCALTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// SynthCal timeout in 0.25 us unit. 0 means infinite (no timeout) +#define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_W 16U +#define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_SYNTHCALTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: PKTCFG +//****************************************************************************** +// Field: [11:11] whiteorder +// +// For NextGen CC2500 compatibility +#define PBE_GENERIC_RAM_PKTCFG_WHITEORDER 0x0800U +#define PBE_GENERIC_RAM_PKTCFG_WHITEORDER_M 0x0800U +#define PBE_GENERIC_RAM_PKTCFG_WHITEORDER_S 11U + +// Field: [10:10] crcorder +// +// Bit ordering of the CRC +#define PBE_GENERIC_RAM_PKTCFG_CRCORDER 0x0400U +#define PBE_GENERIC_RAM_PKTCFG_CRCORDER_M 0x0400U +#define PBE_GENERIC_RAM_PKTCFG_CRCORDER_S 10U + +// Field: [9:9] bitorder +// +// Bit ordering of the payload +#define PBE_GENERIC_RAM_PKTCFG_BITORDER 0x0200U +#define PBE_GENERIC_RAM_PKTCFG_BITORDER_M 0x0200U +#define PBE_GENERIC_RAM_PKTCFG_BITORDER_S 9U + +// Field: [8:8] hdrorder +// +// Bit ordering of the header +#define PBE_GENERIC_RAM_PKTCFG_HDRORDER 0x0100U +#define PBE_GENERIC_RAM_PKTCFG_HDRORDER_M 0x0100U +#define PBE_GENERIC_RAM_PKTCFG_HDRORDER_S 8U + +// Field: [7:7] crcinchdr +// +// CRC HDR rule +#define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR 0x0080U +#define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR_M 0x0080U +#define PBE_GENERIC_RAM_PKTCFG_CRCINCHDR_S 7U + +// Field: [6:6] crcincsw +// +// CRC SW rule +#define PBE_GENERIC_RAM_PKTCFG_CRCINCSW 0x0040U +#define PBE_GENERIC_RAM_PKTCFG_CRCINCSW_M 0x0040U +#define PBE_GENERIC_RAM_PKTCFG_CRCINCSW_S 6U + +// Field: [5:0] numhdrbits +// +// Number of bits in the header 0-32 +#define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_W 6U +#define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_M 0x003FU +#define PBE_GENERIC_RAM_PKTCFG_NUMHDRBITS_S 0U + +//****************************************************************************** +// Register: NUMCRCBITS +//****************************************************************************** +// Field: [5:0] val +// +// Length of CRC checksum in bits +#define PBE_GENERIC_RAM_NUMCRCBITS_VAL_W 6U +#define PBE_GENERIC_RAM_NUMCRCBITS_VAL_M 0x003FU +#define PBE_GENERIC_RAM_NUMCRCBITS_VAL_S 0U + +//****************************************************************************** +// Register: FIFOCFG +//****************************************************************************** +// Field: [15:15] appendtimestamp +// +// +#define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP 0x8000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x8000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDTIMESTAMP_S 15U + +// Field: [14:14] appendrssi +// +// +#define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI 0x4000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI_M 0x4000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDRSSI_S 14U + +// Field: [13:13] appendfreqest +// +// +#define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST 0x2000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST_M 0x2000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDFREQEST_S 13U + +// Field: [12:12] appendlqi +// +// +#define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI 0x1000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI_M 0x1000U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDLQI_S 12U + +// Field: [11:11] appendstatus +// +// CRCOK, Ignore, Code rate +#define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS 0x0800U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS_M 0x0800U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDSTATUS_S 11U + +// Field: [10:10] appendcrc +// +// Append all received crc bits +#define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC 0x0400U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC_M 0x0400U +#define PBE_GENERIC_RAM_FIFOCFG_APPENDCRC_S 10U + +// Field: [9:9] autoflushempty +// +// +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY 0x0200U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_M 0x0200U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_S 9U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_KEEP 0x0000U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHEMPTY_FLUSH 0x0200U + +// Field: [8:8] autoflushign +// +// +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN 0x0100U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0100U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_S 8U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0100U + +// Field: [7:7] autoflushcrc +// +// +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC 0x0080U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0080U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_S 7U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U +#define PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0080U + +// Field: [6:4] lenoptpad +// +// Length of optional padding, required by the PBE during RX operations +#define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_W 3U +#define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_M 0x0070U +#define PBE_GENERIC_RAM_FIFOCFG_LENOPTPAD_S 4U + +//****************************************************************************** +// Register: EXTRABYTES +//****************************************************************************** +// Field: [15:0] val +// +// Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. It has to be equal or greater. If FIFOCFG_APPENDRSSI is high, EXTRABYTES shall increment by 2 etc. +#define PBE_GENERIC_RAM_EXTRABYTES_VAL_W 16U +#define PBE_GENERIC_RAM_EXTRABYTES_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_EXTRABYTES_VAL_S 0U + +//****************************************************************************** +// Register: WHITEINIT +//****************************************************************************** +// Field: [15:0] val +// +// Whitener initialization value +#define PBE_GENERIC_RAM_WHITEINIT_VAL_W 16U +#define PBE_GENERIC_RAM_WHITEINIT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_WHITEINIT_VAL_S 0U + +//****************************************************************************** +// Register: CRCINITL +//****************************************************************************** +// Field: [15:0] vallsb +// +// +#define PBE_GENERIC_RAM_CRCINITL_VALLSB_W 16U +#define PBE_GENERIC_RAM_CRCINITL_VALLSB_M 0xFFFFU +#define PBE_GENERIC_RAM_CRCINITL_VALLSB_S 0U + +//****************************************************************************** +// Register: CRCINITH +//****************************************************************************** +// Field: [15:0] valmsb +// +// +#define PBE_GENERIC_RAM_CRCINITH_VALMSB_W 16U +#define PBE_GENERIC_RAM_CRCINITH_VALMSB_M 0xFFFFU +#define PBE_GENERIC_RAM_CRCINITH_VALMSB_S 0U + +//****************************************************************************** +// Register: LENCFG +//****************************************************************************** +// Field: [15:10] reserved +// +// Reserved values +#define PBE_GENERIC_RAM_LENCFG_RESERVED_W 6U +#define PBE_GENERIC_RAM_LENCFG_RESERVED_M 0xFC00U +#define PBE_GENERIC_RAM_LENCFG_RESERVED_S 10U + +// Field: [9:5] numlenbits +// +// Number of bits in length field 0-16. +#define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_W 5U +#define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_M 0x03E0U +#define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_S 5U +#define PBE_GENERIC_RAM_LENCFG_NUMLENBITS_FIXED 0x0000U + +// Field: [4:0] lenpos +// +// Position of length field in header 0-31 +#define PBE_GENERIC_RAM_LENCFG_LENPOS_W 5U +#define PBE_GENERIC_RAM_LENCFG_LENPOS_M 0x001FU +#define PBE_GENERIC_RAM_LENCFG_LENPOS_S 0U + +//****************************************************************************** +// Register: LENOFFSET +//****************************************************************************** +// Field: [15:0] val +// +// Signed value to add to length field +#define PBE_GENERIC_RAM_LENOFFSET_VAL_W 16U +#define PBE_GENERIC_RAM_LENOFFSET_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LENOFFSET_VAL_S 0U + +//****************************************************************************** +// Register: FIRSTRXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// For NESB tasks, the timeout in µs from SYSTCMP0 event to giving up listening for the first packet. Must be at least 128 µs if non-zero, may be up to 32000 µs. +#define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_W 16U +#define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_FIRSTRXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: RXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// RX timeout in 0.25 us unit. 0 means infinite (no timeout) +#define PBE_GENERIC_RAM_RXTIMEOUT_VAL_W 16U +#define PBE_GENERIC_RAM_RXTIMEOUT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_RXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: RFINTERVAL +//****************************************************************************** +// Field: [15:0] val +// +// RF interval in units of 1 µs +#define PBE_GENERIC_RAM_RFINTERVAL_VAL_W 16U +#define PBE_GENERIC_RAM_RFINTERVAL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_RFINTERVAL_VAL_S 0U + +//****************************************************************************** +// Register: PRETXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used to set timer0 for when to start Transmission. +#define PBE_GENERIC_RAM_PRETXIFS_VAL_W 16U +#define PBE_GENERIC_RAM_PRETXIFS_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PRETXIFS_VAL_S 0U + +//****************************************************************************** +// Register: PRERXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used to set timer0 for when to start Reception. +#define PBE_GENERIC_RAM_PRERXIFS_VAL_W 16U +#define PBE_GENERIC_RAM_PRERXIFS_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PRERXIFS_VAL_S 0U + +//****************************************************************************** +// Register: OPCFG +//****************************************************************************** +// Field: [14:14] rxfilterop +// +// Address filtering option +#define PBE_GENERIC_RAM_OPCFG_RXFILTEROP 0x4000U +#define PBE_GENERIC_RAM_OPCFG_RXFILTEROP_M 0x4000U +#define PBE_GENERIC_RAM_OPCFG_RXFILTEROP_S 14U + +// Field: [13:13] rxincludehdr +// +// Rule for HDR inclusion in FIFO +#define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR 0x2000U +#define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_M 0x2000U +#define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_S 13U +#define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_NO 0x0000U +#define PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_YES 0x2000U + +// Field: [12:12] rxrepeatok +// +// Rule for what to do after packets with correct CRC +#define PBE_GENERIC_RAM_OPCFG_RXREPEATOK 0x1000U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_M 0x1000U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S 12U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_YES 0x0000U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATOK_NO 0x1000U + +// Field: [11:11] rxrepeatnok +// +// Rule for what to do after packets with CRC error or address mismatch. +#define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK 0x0800U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_M 0x0800U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_S 11U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_NO 0x0000U +#define PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_YES 0x0800U + +// Field: [10:10] txinfinite +// +// Infinite TX control +#define PBE_GENERIC_RAM_OPCFG_TXINFINITE 0x0400U +#define PBE_GENERIC_RAM_OPCFG_TXINFINITE_M 0x0400U +#define PBE_GENERIC_RAM_OPCFG_TXINFINITE_S 10U +#define PBE_GENERIC_RAM_OPCFG_TXINFINITE_NO 0x0000U +#define PBE_GENERIC_RAM_OPCFG_TXINFINITE_YES 0x0400U + +// Field: [9:9] txpattern +// +// Send fixed pattern +#define PBE_GENERIC_RAM_OPCFG_TXPATTERN 0x0200U +#define PBE_GENERIC_RAM_OPCFG_TXPATTERN_M 0x0200U +#define PBE_GENERIC_RAM_OPCFG_TXPATTERN_S 9U +#define PBE_GENERIC_RAM_OPCFG_TXPATTERN_NO 0x0000U +#define PBE_GENERIC_RAM_OPCFG_TXPATTERN_YES 0x0200U + +// Field: [8:7] txfcmd +// +// Rule for FCMD after TX_DONE +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_W 2U +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_M 0x0180U +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_S 7U +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_NONE 0x0000U +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_RETRY 0x0080U +#define PBE_GENERIC_RAM_OPCFG_TXFCMD_DEALLOC 0x0100U + +// Field: [6:6] start +// +// Rule for start of operation. +#define PBE_GENERIC_RAM_OPCFG_START 0x0040U +#define PBE_GENERIC_RAM_OPCFG_START_M 0x0040U +#define PBE_GENERIC_RAM_OPCFG_START_S 6U + +// Field: [5:5] fs_nocal +// +// Rule for frequency synthesizer(FS) calibration +#define PBE_GENERIC_RAM_OPCFG_FS_NOCAL 0x0020U +#define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M 0x0020U +#define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S 5U +#define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_CAL 0x0000U +#define PBE_GENERIC_RAM_OPCFG_FS_NOCAL_NOCAL 0x0020U + +// Field: [4:4] fs_keepon +// +// Rule for frequency synthesizer(FS) power down +#define PBE_GENERIC_RAM_OPCFG_FS_KEEPON 0x0010U +#define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M 0x0010U +#define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S 4U +#define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_NO 0x0000U +#define PBE_GENERIC_RAM_OPCFG_FS_KEEPON_YES 0x0010U + +// Field: [3:3] nextop +// +// Enable automatic RX/TX switching, does nothing if OPCFG_SINGLE is selected. +#define PBE_GENERIC_RAM_OPCFG_NEXTOP 0x0008U +#define PBE_GENERIC_RAM_OPCFG_NEXTOP_M 0x0008U +#define PBE_GENERIC_RAM_OPCFG_NEXTOP_S 3U +#define PBE_GENERIC_RAM_OPCFG_NEXTOP_SWITCH 0x0000U +#define PBE_GENERIC_RAM_OPCFG_NEXTOP_SAME 0x0008U + +// Field: [2:2] single +// +// Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. +#define PBE_GENERIC_RAM_OPCFG_SINGLE 0x0004U +#define PBE_GENERIC_RAM_OPCFG_SINGLE_M 0x0004U +#define PBE_GENERIC_RAM_OPCFG_SINGLE_S 2U +#define PBE_GENERIC_RAM_OPCFG_SINGLE_DIS 0x0000U +#define PBE_GENERIC_RAM_OPCFG_SINGLE_EN 0x0004U + +// Field: [1:1] ifsperiod +// +// Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. +#define PBE_GENERIC_RAM_OPCFG_IFSPERIOD 0x0002U +#define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_M 0x0002U +#define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S 1U +#define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_DIS 0x0000U +#define PBE_GENERIC_RAM_OPCFG_IFSPERIOD_EN 0x0002U + +// Field: [0:0] rfinterval +// +// Only one shall be high of SINGLE, IFSPERIOD or RFINTERVAL. +#define PBE_GENERIC_RAM_OPCFG_RFINTERVAL 0x0001U +#define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_M 0x0001U +#define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S 0U +#define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_DIS 0x0000U +#define PBE_GENERIC_RAM_OPCFG_RFINTERVAL_EN 0x0001U + +//****************************************************************************** +// Register: MAXLEN +//****************************************************************************** +// Field: [15:0] val +// +// Indicates maximum expected packet length during RX. If NUMLENBITS is 0 then MAXLEN indicates the length of the payload. The length is fixed. If it's 0, RX restarts sync search. +#define PBE_GENERIC_RAM_MAXLEN_VAL_W 16U +#define PBE_GENERIC_RAM_MAXLEN_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_MAXLEN_VAL_S 0U + +//****************************************************************************** +// Register: PATTERN +//****************************************************************************** +// Field: [15:0] val +// +// Data to send if OPCFG.TXPATTERN is 1 +#define PBE_GENERIC_RAM_PATTERN_VAL_W 16U +#define PBE_GENERIC_RAM_PATTERN_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PATTERN_VAL_S 0U + +//****************************************************************************** +// Register: ADDRCFG +//****************************************************************************** +// Field: [15:11] numaddr +// +// Number of addresses in use in the address table +#define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_W 5U +#define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_M 0xF800U +#define PBE_GENERIC_RAM_ADDRCFG_NUMADDR_S 11U + +// Field: [10:6] addrpos +// +// If ADDRTYPE=1, bit position of address in header. If ADDRTYPE=1, set to non-zero to extend address with sync word identifier. +#define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_W 5U +#define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_M 0x07C0U +#define PBE_GENERIC_RAM_ADDRCFG_ADDRPOS_S 6U + +// Field: [5:1] addrsz +// +// Address size. If ADDRTYPE=0 it is in bytes, if ADDRTYPE=1 it is in bits +#define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_W 5U +#define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_M 0x003EU +#define PBE_GENERIC_RAM_ADDRCFG_ADDRSZ_S 1U + +// Field: [0:0] addrtype +// +// Address type +#define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE 0x0001U +#define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE_M 0x0001U +#define PBE_GENERIC_RAM_ADDRCFG_ADDRTYPE_S 0U + +//****************************************************************************** +// Register: ADDRSW +//****************************************************************************** +// Field: [15:15] add15sw +// +// Control what SW add15 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD15SW 0x8000U +#define PBE_GENERIC_RAM_ADDRSW_ADD15SW_M 0x8000U +#define PBE_GENERIC_RAM_ADDRSW_ADD15SW_S 15U +#define PBE_GENERIC_RAM_ADDRSW_ADD15SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD15SW_B 0x8000U + +// Field: [14:14] add14sw +// +// Control what SW add14 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD14SW 0x4000U +#define PBE_GENERIC_RAM_ADDRSW_ADD14SW_M 0x4000U +#define PBE_GENERIC_RAM_ADDRSW_ADD14SW_S 14U +#define PBE_GENERIC_RAM_ADDRSW_ADD14SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD14SW_B 0x4000U + +// Field: [13:13] add13sw +// +// Control what SW add13 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD13SW 0x2000U +#define PBE_GENERIC_RAM_ADDRSW_ADD13SW_M 0x2000U +#define PBE_GENERIC_RAM_ADDRSW_ADD13SW_S 13U +#define PBE_GENERIC_RAM_ADDRSW_ADD13SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD13SW_B 0x2000U + +// Field: [12:12] add12sw +// +// Control what SW add12 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD12SW 0x1000U +#define PBE_GENERIC_RAM_ADDRSW_ADD12SW_M 0x1000U +#define PBE_GENERIC_RAM_ADDRSW_ADD12SW_S 12U +#define PBE_GENERIC_RAM_ADDRSW_ADD12SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD12SW_B 0x1000U + +// Field: [11:11] add11sw +// +// Control what SW add11 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD11SW 0x0800U +#define PBE_GENERIC_RAM_ADDRSW_ADD11SW_M 0x0800U +#define PBE_GENERIC_RAM_ADDRSW_ADD11SW_S 11U +#define PBE_GENERIC_RAM_ADDRSW_ADD11SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD11SW_B 0x0800U + +// Field: [10:10] add10sw +// +// Control what SW add10 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD10SW 0x0400U +#define PBE_GENERIC_RAM_ADDRSW_ADD10SW_M 0x0400U +#define PBE_GENERIC_RAM_ADDRSW_ADD10SW_S 10U +#define PBE_GENERIC_RAM_ADDRSW_ADD10SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD10SW_B 0x0400U + +// Field: [9:9] add9sw +// +// Control what SW add9 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD9SW 0x0200U +#define PBE_GENERIC_RAM_ADDRSW_ADD9SW_M 0x0200U +#define PBE_GENERIC_RAM_ADDRSW_ADD9SW_S 9U +#define PBE_GENERIC_RAM_ADDRSW_ADD9SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD9SW_B 0x0200U + +// Field: [8:8] add8sw +// +// Control what SW add8 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD8SW 0x0100U +#define PBE_GENERIC_RAM_ADDRSW_ADD8SW_M 0x0100U +#define PBE_GENERIC_RAM_ADDRSW_ADD8SW_S 8U +#define PBE_GENERIC_RAM_ADDRSW_ADD8SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD8SW_B 0x0100U + +// Field: [7:7] add7sw +// +// Control what SW add7 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD7SW 0x0080U +#define PBE_GENERIC_RAM_ADDRSW_ADD7SW_M 0x0080U +#define PBE_GENERIC_RAM_ADDRSW_ADD7SW_S 7U +#define PBE_GENERIC_RAM_ADDRSW_ADD7SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD7SW_B 0x0080U + +// Field: [6:6] add6sw +// +// Control what SW add6 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD6SW 0x0040U +#define PBE_GENERIC_RAM_ADDRSW_ADD6SW_M 0x0040U +#define PBE_GENERIC_RAM_ADDRSW_ADD6SW_S 6U +#define PBE_GENERIC_RAM_ADDRSW_ADD6SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD6SW_B 0x0040U + +// Field: [5:5] add5sw +// +// Control what SW add5 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD5SW 0x0020U +#define PBE_GENERIC_RAM_ADDRSW_ADD5SW_M 0x0020U +#define PBE_GENERIC_RAM_ADDRSW_ADD5SW_S 5U +#define PBE_GENERIC_RAM_ADDRSW_ADD5SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD5SW_B 0x0020U + +// Field: [4:4] add4sw +// +// Control what SW add4 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD4SW 0x0010U +#define PBE_GENERIC_RAM_ADDRSW_ADD4SW_M 0x0010U +#define PBE_GENERIC_RAM_ADDRSW_ADD4SW_S 4U +#define PBE_GENERIC_RAM_ADDRSW_ADD4SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD4SW_B 0x0010U + +// Field: [3:3] add3sw +// +// Control what SW add3 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD3SW 0x0008U +#define PBE_GENERIC_RAM_ADDRSW_ADD3SW_M 0x0008U +#define PBE_GENERIC_RAM_ADDRSW_ADD3SW_S 3U +#define PBE_GENERIC_RAM_ADDRSW_ADD3SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD3SW_B 0x0008U + +// Field: [2:2] add2sw +// +// Control what SW add2 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD2SW 0x0004U +#define PBE_GENERIC_RAM_ADDRSW_ADD2SW_M 0x0004U +#define PBE_GENERIC_RAM_ADDRSW_ADD2SW_S 2U +#define PBE_GENERIC_RAM_ADDRSW_ADD2SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD2SW_B 0x0004U + +// Field: [1:1] add1sw +// +// Control what SW add1 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD1SW 0x0002U +#define PBE_GENERIC_RAM_ADDRSW_ADD1SW_M 0x0002U +#define PBE_GENERIC_RAM_ADDRSW_ADD1SW_S 1U +#define PBE_GENERIC_RAM_ADDRSW_ADD1SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD1SW_B 0x0002U + +// Field: [0:0] add0sw +// +// Control what SW add0 is expected to belong to +#define PBE_GENERIC_RAM_ADDRSW_ADD0SW 0x0001U +#define PBE_GENERIC_RAM_ADDRSW_ADD0SW_M 0x0001U +#define PBE_GENERIC_RAM_ADDRSW_ADD0SW_S 0U +#define PBE_GENERIC_RAM_ADDRSW_ADD0SW_A 0x0000U +#define PBE_GENERIC_RAM_ADDRSW_ADD0SW_B 0x0001U + +//****************************************************************************** +// Register: TESTCFG +//****************************************************************************** +// Field: [9:8] endcond +// +// Condition to end the command +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_W 2U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_M 0x0300U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_S 8U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_NEVER 0x0000U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_MDMRFE 0x0100U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_TIMEOUT 0x0200U +#define PBE_GENERIC_RAM_TESTCFG_ENDCOND_TIMEOUT_DONE 0x0300U + +// Field: [7:1] reserved1 +// +// Reserved +#define PBE_GENERIC_RAM_TESTCFG_RESERVED1_W 7U +#define PBE_GENERIC_RAM_TESTCFG_RESERVED1_M 0x00FEU +#define PBE_GENERIC_RAM_TESTCFG_RESERVED1_S 1U + +// Field: [0:0] start +// +// Condition to tigger the test command +#define PBE_GENERIC_RAM_TESTCFG_START 0x0001U +#define PBE_GENERIC_RAM_TESTCFG_START_M 0x0001U +#define PBE_GENERIC_RAM_TESTCFG_START_S 0U +#define PBE_GENERIC_RAM_TESTCFG_START_SYNC 0x0000U +#define PBE_GENERIC_RAM_TESTCFG_START_ASYNC 0x0001U + +//****************************************************************************** +// Register: TESTAPI +//****************************************************************************** +// Field: [15:8] mdmapi +// +// Command to be sent to modem +#define PBE_GENERIC_RAM_TESTAPI_MDMAPI_W 8U +#define PBE_GENERIC_RAM_TESTAPI_MDMAPI_M 0xFF00U +#define PBE_GENERIC_RAM_TESTAPI_MDMAPI_S 8U + +// Field: [7:0] rfeapi +// +// Command to be sent to RFE +#define PBE_GENERIC_RAM_TESTAPI_RFEAPI_W 8U +#define PBE_GENERIC_RAM_TESTAPI_RFEAPI_M 0x00FFU +#define PBE_GENERIC_RAM_TESTAPI_RFEAPI_S 0U + +//****************************************************************************** +// Register: TESTTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// Optional timeout value for test command, unit 0.25 us +#define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_W 16U +#define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TESTTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: ADD0 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD0_VAL_W 16U +#define PBE_GENERIC_RAM_ADD0_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD0_VAL_S 0U + +//****************************************************************************** +// Register: ADD1 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD1_VAL_W 16U +#define PBE_GENERIC_RAM_ADD1_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD1_VAL_S 0U + +//****************************************************************************** +// Register: ADD2 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD2_VAL_W 16U +#define PBE_GENERIC_RAM_ADD2_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD2_VAL_S 0U + +//****************************************************************************** +// Register: ADD3 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD3_VAL_W 16U +#define PBE_GENERIC_RAM_ADD3_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD3_VAL_S 0U + +//****************************************************************************** +// Register: ADD4 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD4_VAL_W 16U +#define PBE_GENERIC_RAM_ADD4_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD4_VAL_S 0U + +//****************************************************************************** +// Register: ADD5 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD5_VAL_W 16U +#define PBE_GENERIC_RAM_ADD5_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD5_VAL_S 0U + +//****************************************************************************** +// Register: ADD6 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD6_VAL_W 16U +#define PBE_GENERIC_RAM_ADD6_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD6_VAL_S 0U + +//****************************************************************************** +// Register: ADD7 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD7_VAL_W 16U +#define PBE_GENERIC_RAM_ADD7_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD7_VAL_S 0U + +//****************************************************************************** +// Register: ADD8 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD8_VAL_W 16U +#define PBE_GENERIC_RAM_ADD8_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD8_VAL_S 0U + +//****************************************************************************** +// Register: ADD9 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD9_VAL_W 16U +#define PBE_GENERIC_RAM_ADD9_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD9_VAL_S 0U + +//****************************************************************************** +// Register: ADD10 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD10_VAL_W 16U +#define PBE_GENERIC_RAM_ADD10_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD10_VAL_S 0U + +//****************************************************************************** +// Register: ADD11 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD11_VAL_W 16U +#define PBE_GENERIC_RAM_ADD11_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD11_VAL_S 0U + +//****************************************************************************** +// Register: ADD12 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD12_VAL_W 16U +#define PBE_GENERIC_RAM_ADD12_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD12_VAL_S 0U + +//****************************************************************************** +// Register: ADD13 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD13_VAL_W 16U +#define PBE_GENERIC_RAM_ADD13_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD13_VAL_S 0U + +//****************************************************************************** +// Register: ADD15 +//****************************************************************************** +// Field: [15:0] val +// +// address bits +#define PBE_GENERIC_RAM_ADD15_VAL_W 16U +#define PBE_GENERIC_RAM_ADD15_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_ADD15_VAL_S 0U + +//****************************************************************************** +// Register: NRXNOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC error +#define PBE_GENERIC_RAM_NRXNOK_VAL_W 16U +#define PBE_GENERIC_RAM_NRXNOK_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXNOK_VAL_S 0U + +//****************************************************************************** +// Register: NRXIGNORED +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC OK, but to be ignored by the MCU +#define PBE_GENERIC_RAM_NRXIGNORED_VAL_W 16U +#define PBE_GENERIC_RAM_NRXIGNORED_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXIGNORED_VAL_S 0U + +//****************************************************************************** +// Register: NRXEMPTY +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC OK and length zero +#define PBE_GENERIC_RAM_NRXEMPTY_VAL_W 16U +#define PBE_GENERIC_RAM_NRXEMPTY_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXEMPTY_VAL_S 0U + +//****************************************************************************** +// Register: NRXFIFOFULL +//****************************************************************************** +// Field: [15:0] val +// +// Number of received packets discarded because the Rx FIFO was full +#define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_W 16U +#define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXFIFOFULL_VAL_S 0U + +//****************************************************************************** +// Register: NRXOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of non-empty packets received with CRC OK and not to be ignored by the MCU +#define PBE_GENERIC_RAM_NRXOK_VAL_W 16U +#define PBE_GENERIC_RAM_NRXOK_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXOK_VAL_S 0U + +//****************************************************************************** +// Register: NTX +//****************************************************************************** +// Field: [15:0] val +// +// Number of transmitted packets,incremented for every transmitted packet +#define PBE_GENERIC_RAM_NTX_VAL_W 16U +#define PBE_GENERIC_RAM_NTX_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NTX_VAL_S 0U + +//****************************************************************************** +// Register: NRXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// Number of RX timeout +#define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_W 16U +#define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_NRXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: LASTRSSI +//****************************************************************************** +// Field: [15:0] val +// +// RSSI of last received packet with crc OK +#define PBE_GENERIC_RAM_LASTRSSI_VAL_W 16U +#define PBE_GENERIC_RAM_LASTRSSI_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LASTRSSI_VAL_S 0U + +//****************************************************************************** +// Register: LASTFREQOFF +//****************************************************************************** +// Field: [15:0] val +// +// FREQOFF of last received packet with crc OK +#define PBE_GENERIC_RAM_LASTFREQOFF_VAL_W 16U +#define PBE_GENERIC_RAM_LASTFREQOFF_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LASTFREQOFF_VAL_S 0U + +//****************************************************************************** +// Register: LASTLQI +//****************************************************************************** +// Field: [15:0] val +// +// LQI of last received packet with crc OK +#define PBE_GENERIC_RAM_LASTLQI_VAL_W 16U +#define PBE_GENERIC_RAM_LASTLQI_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LASTLQI_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPL +//****************************************************************************** +// Field: [15:0] val +// +// Lower part of timestamp. +#define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_W 16U +#define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LASTTIMESTAMPL_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPH +//****************************************************************************** +// Field: [15:0] val +// +// Upper part of timestamp. +#define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_W 16U +#define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_LASTTIMESTAMPH_VAL_S 0U + +//****************************************************************************** +// Register: PEERADRINFO +//****************************************************************************** +// Field: [15:0] val +// +// Indicates which peer address that matched the received address. +#define PBE_GENERIC_RAM_PEERADRINFO_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADRINFO_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADRINFO_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR1AL +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_GENERIC_RAM_PEERADR1AL_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR1AL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR1AL_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR1AH +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_GENERIC_RAM_PEERADR1AH_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR1AH_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR1AH_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR0AL +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_GENERIC_RAM_PEERADR0AL_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR0AL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR0AL_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR0AH +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_GENERIC_RAM_PEERADR0AH_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR0AH_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR0AH_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR1BL +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_GENERIC_RAM_PEERADR1BL_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR1BL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR1BL_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR1BH +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_GENERIC_RAM_PEERADR1BH_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR1BH_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR1BH_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR0BL +//****************************************************************************** +// Field: [15:0] val +// +// bits 15:0 of address +#define PBE_GENERIC_RAM_PEERADR0BL_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR0BL_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR0BL_VAL_S 0U + +//****************************************************************************** +// Register: PEERADR0BH +//****************************************************************************** +// Field: [15:0] val +// +// bits 31:16 of address +#define PBE_GENERIC_RAM_PEERADR0BH_VAL_W 16U +#define PBE_GENERIC_RAM_PEERADR0BH_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_PEERADR0BH_VAL_S 0U + +//****************************************************************************** +// Register: NESB +//****************************************************************************** +// Field: [15:6] reserved +// +// reserved +#define PBE_GENERIC_RAM_NESB_RESERVED_W 10U +#define PBE_GENERIC_RAM_NESB_RESERVED_M 0xFFC0U +#define PBE_GENERIC_RAM_NESB_RESERVED_S 6U + +// Field: [5:3] peeradrlen +// +// Length of address after header (0-4 bytes) at the start of the "Payload" +#define PBE_GENERIC_RAM_NESB_PEERADRLEN_W 3U +#define PBE_GENERIC_RAM_NESB_PEERADRLEN_M 0x0038U +#define PBE_GENERIC_RAM_NESB_PEERADRLEN_S 3U + +// Field: [2:2] nesbmode +// +// The default mode is ble5 without many features, aka generic ble5. +#define PBE_GENERIC_RAM_NESB_NESBMODE 0x0004U +#define PBE_GENERIC_RAM_NESB_NESBMODE_M 0x0004U +#define PBE_GENERIC_RAM_NESB_NESBMODE_S 2U +#define PBE_GENERIC_RAM_NESB_NESBMODE_OFF 0x0000U +#define PBE_GENERIC_RAM_NESB_NESBMODE_ON 0x0004U + +//****************************************************************************** +// Register: CRCVAL0 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_GENERIC_RAM_CRCVAL0_VAL_W 16U +#define PBE_GENERIC_RAM_CRCVAL0_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_CRCVAL0_VAL_S 0U + +//****************************************************************************** +// Register: SEQSTAT0 +//****************************************************************************** +// Field: [15:5] reserved +// +// reserved +#define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_W 11U +#define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_M 0xFFE0U +#define PBE_GENERIC_RAM_SEQSTAT0_RESERVED_S 5U + +// Field: [4:3] stopauto +// +// PTX may attempt to receive an Ack packet and then execute automatic retransmission if the reception failed due to sync timeout or wrong CRC or full RX fifo. PRX may execute automatic acknowledgement transmission and then return to sync search. +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_W 2U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_M 0x0018U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_S 3U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_ALWAYS 0x0000U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_POSNOA 0x0008U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_NEGNOA 0x0010U +#define PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_NEVER 0x0018U + +// Field: [2:1] pid +// +// NESB Sequence Number or packet ID. +#define PBE_GENERIC_RAM_SEQSTAT0_PID_W 2U +#define PBE_GENERIC_RAM_SEQSTAT0_PID_M 0x0006U +#define PBE_GENERIC_RAM_SEQSTAT0_PID_S 1U + +// Field: [0:0] valid +// +// +#define PBE_GENERIC_RAM_SEQSTAT0_VALID 0x0001U +#define PBE_GENERIC_RAM_SEQSTAT0_VALID_M 0x0001U +#define PBE_GENERIC_RAM_SEQSTAT0_VALID_S 0U +#define PBE_GENERIC_RAM_SEQSTAT0_VALID_NO 0x0000U +#define PBE_GENERIC_RAM_SEQSTAT0_VALID_YES 0x0001U + +//****************************************************************************** +// Register: CRCVAL1 +//****************************************************************************** +// Field: [15:0] val +// +// +#define PBE_GENERIC_RAM_CRCVAL1_VAL_W 16U +#define PBE_GENERIC_RAM_CRCVAL1_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_CRCVAL1_VAL_S 0U + +//****************************************************************************** +// Register: SEQSTAT1 +//****************************************************************************** +// Field: [15:5] reserved +// +// reserved +#define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_W 11U +#define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_M 0xFFE0U +#define PBE_GENERIC_RAM_SEQSTAT1_RESERVED_S 5U + +// Field: [4:3] stopauto +// +// PTX may attempt to receive an Ack packet and then execute automatic retransmission if the reception failed due to sync timeout or wrong CRC or full RX fifo. PRX may execute automatic acknowledgement transmission and then return to sync search. +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_W 2U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_M 0x0018U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_S 3U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_ALWAYS 0x0000U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_POSNOA 0x0008U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_NEGNOA 0x0010U +#define PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_NEVER 0x0018U + +// Field: [2:1] pid +// +// NESB Sequence Number or packet ID. +#define PBE_GENERIC_RAM_SEQSTAT1_PID_W 2U +#define PBE_GENERIC_RAM_SEQSTAT1_PID_M 0x0006U +#define PBE_GENERIC_RAM_SEQSTAT1_PID_S 1U + +// Field: [0:0] valid +// +// +#define PBE_GENERIC_RAM_SEQSTAT1_VALID 0x0001U +#define PBE_GENERIC_RAM_SEQSTAT1_VALID_M 0x0001U +#define PBE_GENERIC_RAM_SEQSTAT1_VALID_S 0U +#define PBE_GENERIC_RAM_SEQSTAT1_VALID_NO 0x0000U +#define PBE_GENERIC_RAM_SEQSTAT1_VALID_YES 0x0001U + +//****************************************************************************** +// Register: STATUSBYTE +//****************************************************************************** +// Field: [15:5] reserved +// +// Flags +#define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_W 11U +#define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_M 0xFFE0U +#define PBE_GENERIC_RAM_STATUSBYTE_RESERVED_S 5U + +// Field: [4:4] swsel +// +// Indicates which syncword that was used. 0: SyncwordA, 1: SyncwordB. +#define PBE_GENERIC_RAM_STATUSBYTE_SWSEL 0x0010U +#define PBE_GENERIC_RAM_STATUSBYTE_SWSEL_M 0x0010U +#define PBE_GENERIC_RAM_STATUSBYTE_SWSEL_S 4U + +// Field: [3:3] ignored +// +// Ignored due to PID or address. +#define PBE_GENERIC_RAM_STATUSBYTE_IGNORED 0x0008U +#define PBE_GENERIC_RAM_STATUSBYTE_IGNORED_M 0x0008U +#define PBE_GENERIC_RAM_STATUSBYTE_IGNORED_S 3U + +// Field: [2:2] crcerror +// +// CRC check with PHA failed. +#define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR 0x0004U +#define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR_M 0x0004U +#define PBE_GENERIC_RAM_STATUSBYTE_CRCERROR_S 2U + +// Field: [1:0] phy +// +// aka Rate Indicator. +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_W 2U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_M 0x0003U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_S 0U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_1M 0x0000U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_2M 0x0001U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_CODED_125K 0x0002U +#define PBE_GENERIC_RAM_STATUSBYTE_PHY_CODED_500K 0x0003U + +//****************************************************************************** +// Register: TMPBYTE1 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPBYTE1_VAL_W 16U +#define PBE_GENERIC_RAM_TMPBYTE1_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPBYTE1_VAL_S 0U + +//****************************************************************************** +// Register: TMPBYTE2 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPBYTE2_VAL_W 16U +#define PBE_GENERIC_RAM_TMPBYTE2_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPBYTE2_VAL_S 0U + +//****************************************************************************** +// Register: TMPBYTE3 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPBYTE3_VAL_W 16U +#define PBE_GENERIC_RAM_TMPBYTE3_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPBYTE3_VAL_S 0U + +//****************************************************************************** +// Register: TMPBYTE4 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPBYTE4_VAL_W 16U +#define PBE_GENERIC_RAM_TMPBYTE4_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPBYTE4_VAL_S 0U + +//****************************************************************************** +// Register: TMPRSSI +//****************************************************************************** +// Field: [15:0] val +// +// RSSI +#define PBE_GENERIC_RAM_TMPRSSI_VAL_W 16U +#define PBE_GENERIC_RAM_TMPRSSI_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPRSSI_VAL_S 0U + +//****************************************************************************** +// Register: TMPADR1 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPADR1_VAL_W 16U +#define PBE_GENERIC_RAM_TMPADR1_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPADR1_VAL_S 0U + +//****************************************************************************** +// Register: TMPADR2 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPADR2_VAL_W 16U +#define PBE_GENERIC_RAM_TMPADR2_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPADR2_VAL_S 0U + +//****************************************************************************** +// Register: TMPADR3 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPADR3_VAL_W 16U +#define PBE_GENERIC_RAM_TMPADR3_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPADR3_VAL_S 0U + +//****************************************************************************** +// Register: TMPADR4 +//****************************************************************************** +// Field: [15:0] val +// +// Flags +#define PBE_GENERIC_RAM_TMPADR4_VAL_W 16U +#define PBE_GENERIC_RAM_TMPADR4_VAL_M 0xFFFFU +#define PBE_GENERIC_RAM_TMPADR4_VAL_S 0U + + +#endif // __PBE_GENERIC_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_regdef_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_regdef_regs.h new file mode 100644 index 00000000..bfb10c93 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_generic_regdef_regs.h @@ -0,0 +1,201 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:02 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/generic/doc/pbe_generic_regdef_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 909cc6f86073545ee6bc3a4d5aa0343a4542ddcc +// +// =========================================================================== + + +#ifndef __PBE_GENERIC_REGDEF_REGS_H +#define __PBE_GENERIC_REGDEF_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// Packet Building Engine (PBE) interrupt generation register +#define PBE_GENERIC_REGDEF_O_IRQ 0x00000010U + +// PBE API Operation Register +#define PBE_GENERIC_REGDEF_O_API 0x00000030U + +//****************************************************************************** +// Register: IRQ +//****************************************************************************** +// Field: [15:15] operror +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_OPERROR 0x00008000U +#define PBE_GENERIC_REGDEF_IRQ_OPERROR_M 0x00008000U +#define PBE_GENERIC_REGDEF_IRQ_OPERROR_S 15U +#define PBE_GENERIC_REGDEF_IRQ_OPERROR_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_OPERROR_ACTIVE 0x00008000U + +// Field: [14:14] unused14 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED14 0x00004000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED14_M 0x00004000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED14_S 14U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED14_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED14_ACTIVE 0x00004000U + +// Field: [13:13] txdone +// +// Packet transmitted. MCU shall deallocate or retry. +#define PBE_GENERIC_REGDEF_IRQ_TXDONE 0x00002000U +#define PBE_GENERIC_REGDEF_IRQ_TXDONE_M 0x00002000U +#define PBE_GENERIC_REGDEF_IRQ_TXDONE_S 13U +#define PBE_GENERIC_REGDEF_IRQ_TXDONE_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_TXDONE_ACTIVE 0x00002000U + +// Field: [12:12] unused12 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED12 0x00001000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED12_M 0x00001000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED12_S 12U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED12_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED12_ACTIVE 0x00001000U + +// Field: [11:11] unused11 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED11 0x00000800U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED11_M 0x00000800U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED11_S 11U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED11_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED11_ACTIVE 0x00000800U + +// Field: [10:10] unused10 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED10 0x00000400U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED10_M 0x00000400U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED10_S 10U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED10_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED10_ACTIVE 0x00000400U + +// Field: [9:9] unused9 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED9 0x00000200U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED9_M 0x00000200U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED9_S 9U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED9_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED9_ACTIVE 0x00000200U + +// Field: [8:8] rxok +// +// Packet received with CRC OK and not to be ignored by the MCU +#define PBE_GENERIC_REGDEF_IRQ_RXOK 0x00000100U +#define PBE_GENERIC_REGDEF_IRQ_RXOK_M 0x00000100U +#define PBE_GENERIC_REGDEF_IRQ_RXOK_S 8U +#define PBE_GENERIC_REGDEF_IRQ_RXOK_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_RXOK_ACTIVE 0x00000100U + +// Field: [7:7] rxfovfl +// +// Packet received which did not fit in the RX FIFO and was not to be discarded. +#define PBE_GENERIC_REGDEF_IRQ_RXFOVFL 0x00000080U +#define PBE_GENERIC_REGDEF_IRQ_RXFOVFL_M 0x00000080U +#define PBE_GENERIC_REGDEF_IRQ_RXFOVFL_S 7U +#define PBE_GENERIC_REGDEF_IRQ_RXFOVFL_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_RXFOVFL_ACTIVE 0x00000080U + +// Field: [6:6] unused6 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED6 0x00000040U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED6_M 0x00000040U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED6_S 6U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED6_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED6_ACTIVE 0x00000040U + +// Field: [5:5] rxign +// +// Packet received with correct CRC, but may be ignored by MCU +#define PBE_GENERIC_REGDEF_IRQ_RXIGN 0x00000020U +#define PBE_GENERIC_REGDEF_IRQ_RXIGN_M 0x00000020U +#define PBE_GENERIC_REGDEF_IRQ_RXIGN_S 5U +#define PBE_GENERIC_REGDEF_IRQ_RXIGN_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_RXIGN_ACTIVE 0x00000020U + +// Field: [4:4] rxnok +// +// Packet received with CRC error, no data may be trusted +#define PBE_GENERIC_REGDEF_IRQ_RXNOK 0x00000010U +#define PBE_GENERIC_REGDEF_IRQ_RXNOK_M 0x00000010U +#define PBE_GENERIC_REGDEF_IRQ_RXNOK_S 4U +#define PBE_GENERIC_REGDEF_IRQ_RXNOK_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_RXNOK_ACTIVE 0x00000010U + +// Field: [3:3] unused3 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED3 0x00000008U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED3_M 0x00000008U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED3_S 3U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED3_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED3_ACTIVE 0x00000008U + +// Field: [2:2] unused2 +// +// Software defined interrupt +#define PBE_GENERIC_REGDEF_IRQ_UNUSED2 0x00000004U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED2_M 0x00000004U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED2_S 2U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED2_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_UNUSED2_ACTIVE 0x00000004U + +// Field: [1:1] pingrsp +// +// PBE responds to PBEOP_PING, basic test to see if the battery is connected. +#define PBE_GENERIC_REGDEF_IRQ_PINGRSP 0x00000002U +#define PBE_GENERIC_REGDEF_IRQ_PINGRSP_M 0x00000002U +#define PBE_GENERIC_REGDEF_IRQ_PINGRSP_S 1U +#define PBE_GENERIC_REGDEF_IRQ_PINGRSP_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_PINGRSP_ACTIVE 0x00000002U + +// Field: [0:0] opdone +// +// The operation commanded on PBEAPI has completed succesfully. +#define PBE_GENERIC_REGDEF_IRQ_OPDONE 0x00000001U +#define PBE_GENERIC_REGDEF_IRQ_OPDONE_M 0x00000001U +#define PBE_GENERIC_REGDEF_IRQ_OPDONE_S 0U +#define PBE_GENERIC_REGDEF_IRQ_OPDONE_OFF 0x00000000U +#define PBE_GENERIC_REGDEF_IRQ_OPDONE_ACTIVE 0x00000001U + +//****************************************************************************** +// Register: API +//****************************************************************************** +// Field: [4:0] op +// +// PBE Operation +#define PBE_GENERIC_REGDEF_API_OP_W 5U +#define PBE_GENERIC_REGDEF_API_OP_M 0x0000001FU +#define PBE_GENERIC_REGDEF_API_OP_S 0U +#define PBE_GENERIC_REGDEF_API_OP_PING 0x00000000U +#define PBE_GENERIC_REGDEF_API_OP_STOP 0x00000001U +#define PBE_GENERIC_REGDEF_API_OP_EOPSTOP 0x00000002U +#define PBE_GENERIC_REGDEF_API_OP_TX 0x00000010U +#define PBE_GENERIC_REGDEF_API_OP_RX 0x00000011U +#define PBE_GENERIC_REGDEF_API_OP_FS 0x00000012U +#define PBE_GENERIC_REGDEF_API_OP_STOPFS 0x00000013U + + +#endif // __PBE_GENERIC_REGDEF_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_ram_regs.h new file mode 100644 index 00000000..849d2719 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_ram_regs.h @@ -0,0 +1,1404 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:08:57 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 1353f9246ed8136ef80520886e631bb482d0bdfe +// +// =========================================================================== + + +#ifndef __PBE_IEEE_RAM_REGS_H +#define __PBE_IEEE_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// Configure synth calibration timeout +#define PBE_IEEE_RAM_O_SYNTHCALTIMEOUT 0x00000020U + +// Configure FIFO what statuses to append +#define PBE_IEEE_RAM_O_FIFOCFG 0x00000022U + +// +#define PBE_IEEE_RAM_O_EXTRABYTES 0x00000024U + +// How long to search for sync before giving up +#define PBE_IEEE_RAM_O_RXTIMEOUT 0x00000026U + +// +#define PBE_IEEE_RAM_O_PRETXIFS 0x00000028U + +// +#define PBE_IEEE_RAM_O_PRERXIFS 0x0000002AU + +// Combined tx/rx/fs configuration +#define PBE_IEEE_RAM_O_OPCFG 0x0000002CU + +// +#define PBE_IEEE_RAM_O_PATTERN 0x0000002EU + +// Initialization for the whitener, if 0 the whitener is not used +#define PBE_IEEE_RAM_O_WHITEINIT 0x00000030U + +// +#define PBE_IEEE_RAM_O_PIB 0x00000032U + +// +#define PBE_IEEE_RAM_O_FFTYPE 0x00000034U + +// +#define PBE_IEEE_RAM_O_NRXNOK 0x00000036U + +// +#define PBE_IEEE_RAM_O_NRXIGNORED 0x00000038U + +// +#define PBE_IEEE_RAM_O_NRXEMPTY 0x0000003AU + +// +#define PBE_IEEE_RAM_O_NRXFIFOFULL 0x0000003CU + +// +#define PBE_IEEE_RAM_O_NRXOK 0x0000003EU + +// +#define PBE_IEEE_RAM_O_NTX 0x00000040U + +// +#define PBE_IEEE_RAM_O_NTXACK 0x00000042U + +// +#define PBE_IEEE_RAM_O_NRXTIMEOUT 0x00000044U + +// +#define PBE_IEEE_RAM_O_LASTRSSI 0x00000046U + +// +#define PBE_IEEE_RAM_O_LASTFREQOFF 0x00000048U + +// +#define PBE_IEEE_RAM_O_LASTLQI 0x0000004AU + +// +#define PBE_IEEE_RAM_O_LASTTIMESTAMPL 0x0000004CU + +// +#define PBE_IEEE_RAM_O_LASTTIMESTAMPH 0x0000004EU + +// Status of receiver and transmitter +#define PBE_IEEE_RAM_O_RXSTATUS 0x00000050U + +// General use purpose for storing values +#define PBE_IEEE_RAM_O_TMPREG1 0x00000052U + +// General use purpose for storing values +#define PBE_IEEE_RAM_O_TMPREG2 0x00000054U + +// General use purpose for storing values +#define PBE_IEEE_RAM_O_TMPREG3 0x00000056U + +// General use purpose for storing values +#define PBE_IEEE_RAM_O_TMPREG4 0x00000058U + +// Value of last sequence number found +#define PBE_IEEE_RAM_O_LSEQNR 0x0000005AU + +// Source matching index +#define PBE_IEEE_RAM_O_SRCMATCHIDX 0x0000005CU + +// +#define PBE_IEEE_RAM_O_PANID0 0x00000060U + +// +#define PBE_IEEE_RAM_O_SHORTADDR0 0x00000062U + +// +#define PBE_IEEE_RAM_O_EXTADDR00 0x00000064U + +// +#define PBE_IEEE_RAM_O_EXTADDR01 0x00000066U + +// +#define PBE_IEEE_RAM_O_EXTADDR02 0x00000068U + +// +#define PBE_IEEE_RAM_O_EXTADDR03 0x0000006AU + +// +#define PBE_IEEE_RAM_O_FFOPT0 0x0000006CU + +// +#define PBE_IEEE_RAM_O_PANID1 0x00000070U + +// +#define PBE_IEEE_RAM_O_SHORTADDR1 0x00000072U + +// +#define PBE_IEEE_RAM_O_EXTADDR10 0x00000074U + +// +#define PBE_IEEE_RAM_O_EXTADDR11 0x00000076U + +// +#define PBE_IEEE_RAM_O_EXTADDR12 0x00000078U + +// +#define PBE_IEEE_RAM_O_EXTADDR13 0x0000007AU + +// +#define PBE_IEEE_RAM_O_FFOPT1 0x0000007CU + +// +#define PBE_IEEE_RAM_O_TMPRSSI 0x0000007EU + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE00 0x00000080U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE01 0x00000082U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE02 0x00000084U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE03 0x00000086U + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING00 0x00000088U + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING01 0x0000008AU + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING02 0x0000008CU + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING03 0x0000008EU + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE10 0x00000090U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE11 0x00000092U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE12 0x00000094U + +// +#define PBE_IEEE_RAM_O_ENTRYENABLE13 0x00000096U + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING10 0x00000098U + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING11 0x0000009AU + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING12 0x0000009CU + +// +#define PBE_IEEE_RAM_O_FRAMEPENDING13 0x0000009EU + +// +#define PBE_IEEE_RAM_O_PANCFGED 0x000000A0U + +// +#define PBE_IEEE_RAM_O_TMPFCF 0x000000A2U + +// +#define PBE_IEEE_RAM_O_CFGAUTOACK 0x000000A4U + +// +#define PBE_IEEE_RAM_O_MACCMDID 0x000000A6U + +// +#define PBE_IEEE_RAM_O_ACKSTATUS 0x000000A8U + +// +#define PBE_IEEE_RAM_O_CORRCNT 0x000000AAU + +// +#define PBE_IEEE_RAM_O_PAN0_SRC_MATCH_SHORT_START 0x00000204U + +// +#define PBE_IEEE_RAM_O_PAN0_SRC_MATCH_EXT_START 0x00000284U + +// +#define PBE_IEEE_RAM_O_PAN1_SRC_MATCH_SHORT_START 0x00000304U + +// +#define PBE_IEEE_RAM_O_PAN1_SRC_MATCH_EXT_START 0x00000384U + +//****************************************************************************** +// Register: SYNTHCALTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// SynthCal timeout in 0.25us unit. 0 means infinite (no timeout) +#define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_W 16U +#define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: FIFOCFG +//****************************************************************************** +// Field: [15:15] appendtimestamp +// +// Append 16 bit TIMESTAMP +#define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP 0x8000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x8000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP_S 15U + +// Field: [14:14] appendrssi +// +// Append 8 bit RSSI +#define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI 0x4000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI_M 0x4000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI_S 14U + +// Field: [12:12] appendlqi +// +// Append 8 bit Modem LQI estimate (Frequency offset) +#define PBE_IEEE_RAM_FIFOCFG_APPENDLQI 0x1000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDLQI_M 0x1000U +#define PBE_IEEE_RAM_FIFOCFG_APPENDLQI_S 12U + +// Field: [11:11] appendstatus +// +// Append 8 bit status from STATUSBYTE +#define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS 0x0800U +#define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS_M 0x0800U +#define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS_S 11U + +// Field: [10:10] appendcrc +// +// Append all received crc bits +#define PBE_IEEE_RAM_FIFOCFG_APPENDCRC 0x0400U +#define PBE_IEEE_RAM_FIFOCFG_APPENDCRC_M 0x0400U +#define PBE_IEEE_RAM_FIFOCFG_APPENDCRC_S 10U + +// Field: [8:8] autoflushign +// +// Automatically removes packets than can be ignored according to the frame filtering in Rx queue. +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN 0x0100U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0100U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_S 8U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0100U + +// Field: [7:7] autoflushcrc +// +// Automatically removes packets with CRC error from the Rx queue. +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC 0x0080U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0080U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_S 7U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U +#define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0080U + +//****************************************************************************** +// Register: EXTRABYTES +//****************************************************************************** +// Field: [15:0] val +// +// Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. +#define PBE_IEEE_RAM_EXTRABYTES_VAL_W 16U +#define PBE_IEEE_RAM_EXTRABYTES_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTRABYTES_VAL_S 0U + +//****************************************************************************** +// Register: RXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// RX timeout in 0.25us unit. 0 means infinite (no timeout) +#define PBE_IEEE_RAM_RXTIMEOUT_VAL_W 16U +#define PBE_IEEE_RAM_RXTIMEOUT_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_RXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: PRETXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used after RX to set timer0 for when to start Transmission. +#define PBE_IEEE_RAM_PRETXIFS_VAL_W 16U +#define PBE_IEEE_RAM_PRETXIFS_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PRETXIFS_VAL_S 0U + +//****************************************************************************** +// Register: PRERXIFS +//****************************************************************************** +// Field: [15:0] val +// +// Base value used after TX to set timer0 for when to start Receiving. +#define PBE_IEEE_RAM_PRERXIFS_VAL_W 16U +#define PBE_IEEE_RAM_PRERXIFS_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PRERXIFS_VAL_S 0U + +//****************************************************************************** +// Register: OPCFG +//****************************************************************************** +// Field: [14:14] systim0beh +// +// Treatment of systim0 during operation +#define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH 0x4000U +#define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_M 0x4000U +#define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_S 14U +#define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_NORMAL 0x0000U +#define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_IGNORE 0x4000U + +// Field: [13:13] stop +// +// Rejected frame behaviour +#define PBE_IEEE_RAM_OPCFG_STOP 0x2000U +#define PBE_IEEE_RAM_OPCFG_STOP_M 0x2000U +#define PBE_IEEE_RAM_OPCFG_STOP_S 13U +#define PBE_IEEE_RAM_OPCFG_STOP_SOFTEND 0x0000U +#define PBE_IEEE_RAM_OPCFG_STOP_HARDEND 0x2000U + +// Field: [12:12] rxrepeatok +// +// Rule for what to do after packets with correct CRC +#define PBE_IEEE_RAM_OPCFG_RXREPEATOK 0x1000U +#define PBE_IEEE_RAM_OPCFG_RXREPEATOK_M 0x1000U +#define PBE_IEEE_RAM_OPCFG_RXREPEATOK_S 12U +#define PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES 0x0000U +#define PBE_IEEE_RAM_OPCFG_RXREPEATOK_NO 0x1000U + +// Field: [11:11] rxrepeatnok +// +// Rule for what to do after packets with CRC error or address mismatch. +#define PBE_IEEE_RAM_OPCFG_RXREPEATNOK 0x0800U +#define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_M 0x0800U +#define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_S 11U +#define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_NO 0x0000U +#define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES 0x0800U + +// Field: [10:10] txinfinite +// +// Infinite TX control +#define PBE_IEEE_RAM_OPCFG_TXINFINITE 0x0400U +#define PBE_IEEE_RAM_OPCFG_TXINFINITE_M 0x0400U +#define PBE_IEEE_RAM_OPCFG_TXINFINITE_S 10U +#define PBE_IEEE_RAM_OPCFG_TXINFINITE_NO 0x0000U +#define PBE_IEEE_RAM_OPCFG_TXINFINITE_YES 0x0400U + +// Field: [9:9] txpattern +// +// Send fixed pattern +#define PBE_IEEE_RAM_OPCFG_TXPATTERN 0x0200U +#define PBE_IEEE_RAM_OPCFG_TXPATTERN_M 0x0200U +#define PBE_IEEE_RAM_OPCFG_TXPATTERN_S 9U +#define PBE_IEEE_RAM_OPCFG_TXPATTERN_NO 0x0000U +#define PBE_IEEE_RAM_OPCFG_TXPATTERN_YES 0x0200U + +// Field: [8:7] txfcmd +// +// Rule for FCMD after TX_DONE +#define PBE_IEEE_RAM_OPCFG_TXFCMD_W 2U +#define PBE_IEEE_RAM_OPCFG_TXFCMD_M 0x0180U +#define PBE_IEEE_RAM_OPCFG_TXFCMD_S 7U +#define PBE_IEEE_RAM_OPCFG_TXFCMD_NONE 0x0000U +#define PBE_IEEE_RAM_OPCFG_TXFCMD_RETRY 0x0080U +#define PBE_IEEE_RAM_OPCFG_TXFCMD_DEALLOC 0x0100U + +// Field: [6:6] start +// +// Rule for start od operation +#define PBE_IEEE_RAM_OPCFG_START 0x0040U +#define PBE_IEEE_RAM_OPCFG_START_M 0x0040U +#define PBE_IEEE_RAM_OPCFG_START_S 6U +#define PBE_IEEE_RAM_OPCFG_START_SYNC 0x0000U +#define PBE_IEEE_RAM_OPCFG_START_ASYNC 0x0040U + +// Field: [3:3] nextop +// +// Enable automatic RX/TX switching, does nothing if OPCFG_SINGLE is selected. This is a feature not used currently. +#define PBE_IEEE_RAM_OPCFG_NEXTOP 0x0008U +#define PBE_IEEE_RAM_OPCFG_NEXTOP_M 0x0008U +#define PBE_IEEE_RAM_OPCFG_NEXTOP_S 3U +#define PBE_IEEE_RAM_OPCFG_NEXTOP_SWITCH 0x0000U +#define PBE_IEEE_RAM_OPCFG_NEXTOP_SAME 0x0008U + +// Field: [2:2] single +// +// Only one shall be high of SINGLE or IFSPERIOD. +#define PBE_IEEE_RAM_OPCFG_SINGLE 0x0004U +#define PBE_IEEE_RAM_OPCFG_SINGLE_M 0x0004U +#define PBE_IEEE_RAM_OPCFG_SINGLE_S 2U +#define PBE_IEEE_RAM_OPCFG_SINGLE_DIS 0x0000U +#define PBE_IEEE_RAM_OPCFG_SINGLE_EN 0x0004U + +// Field: [1:1] ifsperiod +// +// Only one shall be high of SINGLE or IFSPERIOD. +#define PBE_IEEE_RAM_OPCFG_IFSPERIOD 0x0002U +#define PBE_IEEE_RAM_OPCFG_IFSPERIOD_M 0x0002U +#define PBE_IEEE_RAM_OPCFG_IFSPERIOD_S 1U +#define PBE_IEEE_RAM_OPCFG_IFSPERIOD_DIS 0x0000U +#define PBE_IEEE_RAM_OPCFG_IFSPERIOD_EN 0x0002U + +// Field: [0:0] rfinterval +// +// Reserved bit, currently not used +#define PBE_IEEE_RAM_OPCFG_RFINTERVAL 0x0001U +#define PBE_IEEE_RAM_OPCFG_RFINTERVAL_M 0x0001U +#define PBE_IEEE_RAM_OPCFG_RFINTERVAL_S 0U +#define PBE_IEEE_RAM_OPCFG_RFINTERVAL_DIS 0x0000U +#define PBE_IEEE_RAM_OPCFG_RFINTERVAL_EN 0x0001U + +//****************************************************************************** +// Register: PATTERN +//****************************************************************************** +// Field: [15:0] val +// +// Data to send if OPCFG.TXPATTERN is 1 +#define PBE_IEEE_RAM_PATTERN_VAL_W 16U +#define PBE_IEEE_RAM_PATTERN_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PATTERN_VAL_S 0U + +//****************************************************************************** +// Register: WHITEINIT +//****************************************************************************** +// Field: [15:0] val +// +// Whitener initialization value +#define PBE_IEEE_RAM_WHITEINIT_VAL_W 16U +#define PBE_IEEE_RAM_WHITEINIT_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_WHITEINIT_VAL_S 0U + +//****************************************************************************** +// Register: PIB +//****************************************************************************** +// Field: [1:0] panmode +// +// PAN Information Base sw register +#define PBE_IEEE_RAM_PIB_PANMODE_W 2U +#define PBE_IEEE_RAM_PIB_PANMODE_M 0x0003U +#define PBE_IEEE_RAM_PIB_PANMODE_S 0U +#define PBE_IEEE_RAM_PIB_PANMODE_PROMISCUOUS 0x0000U +#define PBE_IEEE_RAM_PIB_PANMODE_SINGLE 0x0001U + +//****************************************************************************** +// Register: FFTYPE +//****************************************************************************** +// Field: [15:15] extended1 +// +// Treatment of frames with frame type 111 (Extended) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_EXTENDED1 0x8000U +#define PBE_IEEE_RAM_FFTYPE_EXTENDED1_M 0x8000U +#define PBE_IEEE_RAM_FFTYPE_EXTENDED1_S 15U + +// Field: [14:14] frag1 +// +// Treatment of frames with frame type 110 (Fragment) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_FRAG1 0x4000U +#define PBE_IEEE_RAM_FFTYPE_FRAG1_M 0x4000U +#define PBE_IEEE_RAM_FFTYPE_FRAG1_S 14U + +// Field: [13:13] multi1 +// +// Treatment of frames with frame type 101 (Multipurpose) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_MULTI1 0x2000U +#define PBE_IEEE_RAM_FFTYPE_MULTI1_M 0x2000U +#define PBE_IEEE_RAM_FFTYPE_MULTI1_S 13U + +// Field: [12:12] reserved1 +// +// Treatment of frames with frame type 100 (reserved) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_RESERVED1 0x1000U +#define PBE_IEEE_RAM_FFTYPE_RESERVED1_M 0x1000U +#define PBE_IEEE_RAM_FFTYPE_RESERVED1_S 12U + +// Field: [11:11] maccmd1 +// +// Treatment of frames with frame type 011 (MAC command) +#define PBE_IEEE_RAM_FFTYPE_MACCMD1 0x0800U +#define PBE_IEEE_RAM_FFTYPE_MACCMD1_M 0x0800U +#define PBE_IEEE_RAM_FFTYPE_MACCMD1_S 11U + +// Field: [10:10] ack1 +// +// Treatment of frames with frame type 010 (ACK) +#define PBE_IEEE_RAM_FFTYPE_ACK1 0x0400U +#define PBE_IEEE_RAM_FFTYPE_ACK1_M 0x0400U +#define PBE_IEEE_RAM_FFTYPE_ACK1_S 10U +#define PBE_IEEE_RAM_FFTYPE_ACK1_ACCEPT 0x0400U + +// Field: [9:9] data1 +// +// Treatment of frames with frame type 001 (data) +#define PBE_IEEE_RAM_FFTYPE_DATA1 0x0200U +#define PBE_IEEE_RAM_FFTYPE_DATA1_M 0x0200U +#define PBE_IEEE_RAM_FFTYPE_DATA1_S 9U + +// Field: [8:8] beacon1 +// +// Treatment of frames with frame type 000 (beacon) +#define PBE_IEEE_RAM_FFTYPE_BEACON1 0x0100U +#define PBE_IEEE_RAM_FFTYPE_BEACON1_M 0x0100U +#define PBE_IEEE_RAM_FFTYPE_BEACON1_S 8U + +// Field: [7:7] extended0 +// +// Treatment of frames with frame type 111 (Extended) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_EXTENDED0 0x0080U +#define PBE_IEEE_RAM_FFTYPE_EXTENDED0_M 0x0080U +#define PBE_IEEE_RAM_FFTYPE_EXTENDED0_S 7U + +// Field: [6:6] frag0 +// +// Treatment of frames with frame type 110 (Fragment) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_FRAG0 0x0040U +#define PBE_IEEE_RAM_FFTYPE_FRAG0_M 0x0040U +#define PBE_IEEE_RAM_FFTYPE_FRAG0_S 6U + +// Field: [5:5] multi0 +// +// Treatment of frames with frame type 101 (Multipurpose) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_MULTI0 0x0020U +#define PBE_IEEE_RAM_FFTYPE_MULTI0_M 0x0020U +#define PBE_IEEE_RAM_FFTYPE_MULTI0_S 5U + +// Field: [4:4] reserved0 +// +// Treatment of frames with frame type 100 (reserved) (NOT supported) +#define PBE_IEEE_RAM_FFTYPE_RESERVED0 0x0010U +#define PBE_IEEE_RAM_FFTYPE_RESERVED0_M 0x0010U +#define PBE_IEEE_RAM_FFTYPE_RESERVED0_S 4U + +// Field: [3:3] maccmd0 +// +// Treatment of frames with frame type 011 (MAC command) +#define PBE_IEEE_RAM_FFTYPE_MACCMD0 0x0008U +#define PBE_IEEE_RAM_FFTYPE_MACCMD0_M 0x0008U +#define PBE_IEEE_RAM_FFTYPE_MACCMD0_S 3U + +// Field: [2:2] ack0 +// +// Treatment of frames with frame type 010 (ACK) +#define PBE_IEEE_RAM_FFTYPE_ACK0 0x0004U +#define PBE_IEEE_RAM_FFTYPE_ACK0_M 0x0004U +#define PBE_IEEE_RAM_FFTYPE_ACK0_S 2U +#define PBE_IEEE_RAM_FFTYPE_ACK0_ACCEPT 0x0004U + +// Field: [1:1] data0 +// +// Treatment of frames with frame type 001 (data) +#define PBE_IEEE_RAM_FFTYPE_DATA0 0x0002U +#define PBE_IEEE_RAM_FFTYPE_DATA0_M 0x0002U +#define PBE_IEEE_RAM_FFTYPE_DATA0_S 1U + +// Field: [0:0] beacon0 +// +// Treatment of frames with frame type 000 (beacon) +#define PBE_IEEE_RAM_FFTYPE_BEACON0 0x0001U +#define PBE_IEEE_RAM_FFTYPE_BEACON0_M 0x0001U +#define PBE_IEEE_RAM_FFTYPE_BEACON0_S 0U + +//****************************************************************************** +// Register: NRXNOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC error +#define PBE_IEEE_RAM_NRXNOK_VAL_W 16U +#define PBE_IEEE_RAM_NRXNOK_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXNOK_VAL_S 0U + +//****************************************************************************** +// Register: NRXIGNORED +//****************************************************************************** +// Field: [15:0] val +// +// Number of packets received with CRC OK, but to be ignored by the MCU +#define PBE_IEEE_RAM_NRXIGNORED_VAL_W 16U +#define PBE_IEEE_RAM_NRXIGNORED_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXIGNORED_VAL_S 0U + +//****************************************************************************** +// Register: NRXEMPTY +//****************************************************************************** +// Field: [15:0] val +// +// Number of received packets discarded because the Rx FIFO was full +#define PBE_IEEE_RAM_NRXEMPTY_VAL_W 16U +#define PBE_IEEE_RAM_NRXEMPTY_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXEMPTY_VAL_S 0U + +//****************************************************************************** +// Register: NRXFIFOFULL +//****************************************************************************** +// Field: [15:0] val +// +// Number of received packets discarded because the Rx FIFO was full +#define PBE_IEEE_RAM_NRXFIFOFULL_VAL_W 16U +#define PBE_IEEE_RAM_NRXFIFOFULL_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXFIFOFULL_VAL_S 0U + +//****************************************************************************** +// Register: NRXOK +//****************************************************************************** +// Field: [15:0] val +// +// Number of non-empty packets received with CRC OK and not to be ignored by the MCU +#define PBE_IEEE_RAM_NRXOK_VAL_W 16U +#define PBE_IEEE_RAM_NRXOK_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXOK_VAL_S 0U + +//****************************************************************************** +// Register: NTX +//****************************************************************************** +// Field: [15:0] val +// +// Number of transmitted packets,incremented for every transmitted packet +#define PBE_IEEE_RAM_NTX_VAL_W 16U +#define PBE_IEEE_RAM_NTX_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NTX_VAL_S 0U + +//****************************************************************************** +// Register: NTXACK +//****************************************************************************** +// Field: [15:0] val +// +// Number of Imm-Ack transmitted packets, from auto-ack mode,incremented for every transmitted packet +#define PBE_IEEE_RAM_NTXACK_VAL_W 16U +#define PBE_IEEE_RAM_NTXACK_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NTXACK_VAL_S 0U + +//****************************************************************************** +// Register: NRXTIMEOUT +//****************************************************************************** +// Field: [15:0] val +// +// Number of RX timeout +#define PBE_IEEE_RAM_NRXTIMEOUT_VAL_W 16U +#define PBE_IEEE_RAM_NRXTIMEOUT_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_NRXTIMEOUT_VAL_S 0U + +//****************************************************************************** +// Register: LASTRSSI +//****************************************************************************** +// Field: [15:0] val +// +// RSSI of last received packet with crc OK +#define PBE_IEEE_RAM_LASTRSSI_VAL_W 16U +#define PBE_IEEE_RAM_LASTRSSI_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_LASTRSSI_VAL_S 0U + +//****************************************************************************** +// Register: LASTFREQOFF +//****************************************************************************** +// Field: [15:0] val +// +// FREQOFF of last received packet with crc OK +#define PBE_IEEE_RAM_LASTFREQOFF_VAL_W 16U +#define PBE_IEEE_RAM_LASTFREQOFF_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_LASTFREQOFF_VAL_S 0U + +//****************************************************************************** +// Register: LASTLQI +//****************************************************************************** +// Field: [15:0] val +// +// LQI of last received packet with crc OK +#define PBE_IEEE_RAM_LASTLQI_VAL_W 16U +#define PBE_IEEE_RAM_LASTLQI_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_LASTLQI_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPL +//****************************************************************************** +// Field: [15:0] val +// +// Lower part of timestamp. +#define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_W 16U +#define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_S 0U + +//****************************************************************************** +// Register: LASTTIMESTAMPH +//****************************************************************************** +// Field: [15:0] val +// +// Upper part of timestamp. +#define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_W 16U +#define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_S 0U + +//****************************************************************************** +// Register: RXSTATUS +//****************************************************************************** +// Field: [2:2] txinprogress +// +// Status of frame transmission +#define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS 0x0004U +#define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_M 0x0004U +#define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_S 2U +#define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_IDLE 0x0000U +#define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_TX 0x0004U + +// Field: [1:1] txackinprogress +// +// Status of auto ACK transmission +#define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS 0x0002U +#define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_M 0x0002U +#define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_S 1U +#define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_IDLE 0x0000U +#define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_TXACK 0x0002U + +// Field: [0:0] frameinprogress +// +// Status of frame reception +#define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS 0x0001U +#define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_M 0x0001U +#define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_S 0U +#define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_IDLE 0x0000U +#define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_FRAME 0x0001U + +//****************************************************************************** +// Register: TMPREG1 +//****************************************************************************** +// Field: [15:0] val +// +// Value can be anything is necessary to be stored temporary +#define PBE_IEEE_RAM_TMPREG1_VAL_W 16U +#define PBE_IEEE_RAM_TMPREG1_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPREG1_VAL_S 0U + +//****************************************************************************** +// Register: TMPREG2 +//****************************************************************************** +// Field: [15:0] val +// +// Value can be anything is necessary to be stored temporary +#define PBE_IEEE_RAM_TMPREG2_VAL_W 16U +#define PBE_IEEE_RAM_TMPREG2_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPREG2_VAL_S 0U + +//****************************************************************************** +// Register: TMPREG3 +//****************************************************************************** +// Field: [15:0] val +// +// Value can be anything is necessary to be stored temporary +#define PBE_IEEE_RAM_TMPREG3_VAL_W 16U +#define PBE_IEEE_RAM_TMPREG3_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPREG3_VAL_S 0U + +//****************************************************************************** +// Register: TMPREG4 +//****************************************************************************** +// Field: [15:0] val +// +// Value can be anything is necessary to be stored temporary +#define PBE_IEEE_RAM_TMPREG4_VAL_W 16U +#define PBE_IEEE_RAM_TMPREG4_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPREG4_VAL_S 0U + +//****************************************************************************** +// Register: LSEQNR +//****************************************************************************** +// Field: [7:0] val +// +// Last decoded sequence number +#define PBE_IEEE_RAM_LSEQNR_VAL_W 8U +#define PBE_IEEE_RAM_LSEQNR_VAL_M 0x00FFU +#define PBE_IEEE_RAM_LSEQNR_VAL_S 0U + +//****************************************************************************** +// Register: SRCMATCHIDX +//****************************************************************************** +// Field: [7:0] tblidx +// +// Store the index from the src table for which there was a match with the src field of the received frame +#define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_W 8U +#define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_M 0x00FFU +#define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_S 0U + +//****************************************************************************** +// Register: PANID0 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 +#define PBE_IEEE_RAM_PANID0_VAL_W 16U +#define PBE_IEEE_RAM_PANID0_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PANID0_VAL_S 0U + +//****************************************************************************** +// Register: SHORTADDR0 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 short address +#define PBE_IEEE_RAM_SHORTADDR0_VAL_W 16U +#define PBE_IEEE_RAM_SHORTADDR0_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_SHORTADDR0_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR00 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 extended address, bits 15:0 +#define PBE_IEEE_RAM_EXTADDR00_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR00_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR00_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR01 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 extended address, bits 31:16 +#define PBE_IEEE_RAM_EXTADDR01_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR01_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR01_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR02 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 extended address, bits 47:32 +#define PBE_IEEE_RAM_EXTADDR02_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR02_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR02_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR03 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID0 extended address, bits 63:48 +#define PBE_IEEE_RAM_EXTADDR03_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR03_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR03_VAL_S 0U + +//****************************************************************************** +// Register: FFOPT0 +//****************************************************************************** +// Field: [9:8] maxframe +// +// Reject frames where the frame version field in the FCF is greater than this value +#define PBE_IEEE_RAM_FFOPT0_MAXFRAME_W 2U +#define PBE_IEEE_RAM_FFOPT0_MAXFRAME_M 0x0300U +#define PBE_IEEE_RAM_FFOPT0_MAXFRAME_S 8U + +// Field: [7:7] pancoord +// +// +#define PBE_IEEE_RAM_FFOPT0_PANCOORD 0x0080U +#define PBE_IEEE_RAM_FFOPT0_PANCOORD_M 0x0080U +#define PBE_IEEE_RAM_FFOPT0_PANCOORD_S 7U +#define PBE_IEEE_RAM_FFOPT0_PANCOORD_DISABLED 0x0000U +#define PBE_IEEE_RAM_FFOPT0_PANCOORD_EN 0x0080U + +// Field: [6:6] preqonly +// +// +#define PBE_IEEE_RAM_FFOPT0_PREQONLY 0x0040U +#define PBE_IEEE_RAM_FFOPT0_PREQONLY_M 0x0040U +#define PBE_IEEE_RAM_FFOPT0_PREQONLY_S 6U +#define PBE_IEEE_RAM_FFOPT0_PREQONLY_ANY 0x0000U +#define PBE_IEEE_RAM_FFOPT0_PREQONLY_DATAREQ 0x0040U + +// Field: [5:5] defpend +// +// The value of the pending data bit in auto ACK packets that are not subject to auto-pend +#define PBE_IEEE_RAM_FFOPT0_DEFPEND 0x0020U +#define PBE_IEEE_RAM_FFOPT0_DEFPEND_M 0x0020U +#define PBE_IEEE_RAM_FFOPT0_DEFPEND_S 5U + +// Field: [4:4] autopend +// +// +#define PBE_IEEE_RAM_FFOPT0_AUTOPEND 0x0010U +#define PBE_IEEE_RAM_FFOPT0_AUTOPEND_M 0x0010U +#define PBE_IEEE_RAM_FFOPT0_AUTOPEND_S 4U +#define PBE_IEEE_RAM_FFOPT0_AUTOPEND_DISABLE 0x0000U +#define PBE_IEEE_RAM_FFOPT0_AUTOPEND_EN 0x0010U + +// Field: [2:2] autoack +// +// +#define PBE_IEEE_RAM_FFOPT0_AUTOACK 0x0004U +#define PBE_IEEE_RAM_FFOPT0_AUTOACK_M 0x0004U +#define PBE_IEEE_RAM_FFOPT0_AUTOACK_S 2U +#define PBE_IEEE_RAM_FFOPT0_AUTOACK_DISABLE 0x0000U +#define PBE_IEEE_RAM_FFOPT0_AUTOACK_EN 0x0004U + +// Field: [1:1] unused1 +// +// Unused bitfield +#define PBE_IEEE_RAM_FFOPT0_UNUSED1 0x0002U +#define PBE_IEEE_RAM_FFOPT0_UNUSED1_M 0x0002U +#define PBE_IEEE_RAM_FFOPT0_UNUSED1_S 1U + +// Field: [0:0] unused0 +// +// Unused bitfield +#define PBE_IEEE_RAM_FFOPT0_UNUSED0 0x0001U +#define PBE_IEEE_RAM_FFOPT0_UNUSED0_M 0x0001U +#define PBE_IEEE_RAM_FFOPT0_UNUSED0_S 0U + +//****************************************************************************** +// Register: PANID1 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 +#define PBE_IEEE_RAM_PANID1_VAL_W 16U +#define PBE_IEEE_RAM_PANID1_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PANID1_VAL_S 0U + +//****************************************************************************** +// Register: SHORTADDR1 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 short address +#define PBE_IEEE_RAM_SHORTADDR1_VAL_W 16U +#define PBE_IEEE_RAM_SHORTADDR1_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_SHORTADDR1_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR10 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 extended address, bits 15:0 +#define PBE_IEEE_RAM_EXTADDR10_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR10_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR10_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR11 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 extended address, bits 31:16 +#define PBE_IEEE_RAM_EXTADDR11_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR11_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR11_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR12 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 extended address, bits 47:32 +#define PBE_IEEE_RAM_EXTADDR12_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR12_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR12_VAL_S 0U + +//****************************************************************************** +// Register: EXTADDR13 +//****************************************************************************** +// Field: [15:0] val +// +// Local PAN ID1 extended address, bits 63:48 +#define PBE_IEEE_RAM_EXTADDR13_VAL_W 16U +#define PBE_IEEE_RAM_EXTADDR13_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_EXTADDR13_VAL_S 0U + +//****************************************************************************** +// Register: FFOPT1 +//****************************************************************************** +// Field: [9:8] maxframe +// +// Reject frames where the frame version field in the FCF is greater than this value +#define PBE_IEEE_RAM_FFOPT1_MAXFRAME_W 2U +#define PBE_IEEE_RAM_FFOPT1_MAXFRAME_M 0x0300U +#define PBE_IEEE_RAM_FFOPT1_MAXFRAME_S 8U + +// Field: [7:7] pancoord +// +// +#define PBE_IEEE_RAM_FFOPT1_PANCOORD 0x0080U +#define PBE_IEEE_RAM_FFOPT1_PANCOORD_M 0x0080U +#define PBE_IEEE_RAM_FFOPT1_PANCOORD_S 7U +#define PBE_IEEE_RAM_FFOPT1_PANCOORD_DISABLED 0x0000U +#define PBE_IEEE_RAM_FFOPT1_PANCOORD_EN 0x0080U + +// Field: [6:6] preqonly +// +// +#define PBE_IEEE_RAM_FFOPT1_PREQONLY 0x0040U +#define PBE_IEEE_RAM_FFOPT1_PREQONLY_M 0x0040U +#define PBE_IEEE_RAM_FFOPT1_PREQONLY_S 6U +#define PBE_IEEE_RAM_FFOPT1_PREQONLY_ANY 0x0000U +#define PBE_IEEE_RAM_FFOPT1_PREQONLY_DATAREQ 0x0040U + +// Field: [5:5] defpend +// +// The value of the pending data bit in auto ACK packets that are not subject to auto-pend +#define PBE_IEEE_RAM_FFOPT1_DEFPEND 0x0020U +#define PBE_IEEE_RAM_FFOPT1_DEFPEND_M 0x0020U +#define PBE_IEEE_RAM_FFOPT1_DEFPEND_S 5U + +// Field: [4:4] autopend +// +// +#define PBE_IEEE_RAM_FFOPT1_AUTOPEND 0x0010U +#define PBE_IEEE_RAM_FFOPT1_AUTOPEND_M 0x0010U +#define PBE_IEEE_RAM_FFOPT1_AUTOPEND_S 4U +#define PBE_IEEE_RAM_FFOPT1_AUTOPEND_DISABLE 0x0000U +#define PBE_IEEE_RAM_FFOPT1_AUTOPEND_EN 0x0010U + +// Field: [2:2] autoack +// +// +#define PBE_IEEE_RAM_FFOPT1_AUTOACK 0x0004U +#define PBE_IEEE_RAM_FFOPT1_AUTOACK_M 0x0004U +#define PBE_IEEE_RAM_FFOPT1_AUTOACK_S 2U +#define PBE_IEEE_RAM_FFOPT1_AUTOACK_DISABLE 0x0000U +#define PBE_IEEE_RAM_FFOPT1_AUTOACK_EN 0x0004U + +// Field: [1:1] unused1 +// +// Unused bitfield +#define PBE_IEEE_RAM_FFOPT1_UNUSED1 0x0002U +#define PBE_IEEE_RAM_FFOPT1_UNUSED1_M 0x0002U +#define PBE_IEEE_RAM_FFOPT1_UNUSED1_S 1U + +// Field: [0:0] unused0 +// +// Unused bitfield +#define PBE_IEEE_RAM_FFOPT1_UNUSED0 0x0001U +#define PBE_IEEE_RAM_FFOPT1_UNUSED0_M 0x0001U +#define PBE_IEEE_RAM_FFOPT1_UNUSED0_S 0U + +//****************************************************************************** +// Register: TMPRSSI +//****************************************************************************** +// Field: [15:0] val +// +// A temporary storage of the signal strength of received signal +#define PBE_IEEE_RAM_TMPRSSI_VAL_W 16U +#define PBE_IEEE_RAM_TMPRSSI_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPRSSI_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE00 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 0-15 of PAN 0 +#define PBE_IEEE_RAM_ENTRYENABLE00_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE00_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE00_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE01 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 16-31 of PAN 0 +#define PBE_IEEE_RAM_ENTRYENABLE01_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE01_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE01_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE02 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 32-47 of PAN 0 +#define PBE_IEEE_RAM_ENTRYENABLE02_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE02_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE02_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE03 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 48-63 of PAN 0 +#define PBE_IEEE_RAM_ENTRYENABLE03_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE03_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE03_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING00 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 0-15 of PAN 0 +#define PBE_IEEE_RAM_FRAMEPENDING00_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING00_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING00_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING01 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 16-31 of PAN 0 +#define PBE_IEEE_RAM_FRAMEPENDING01_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING01_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING01_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING02 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 32-47 of PAN 0 +#define PBE_IEEE_RAM_FRAMEPENDING02_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING02_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING02_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING03 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 48-63 of PAN 0 +#define PBE_IEEE_RAM_FRAMEPENDING03_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING03_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING03_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE10 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 0-15 of PAN 1 +#define PBE_IEEE_RAM_ENTRYENABLE10_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE10_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE10_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE11 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 16-31 of PAN 1 +#define PBE_IEEE_RAM_ENTRYENABLE11_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE11_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE11_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE12 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 32-47 of PAN 1 +#define PBE_IEEE_RAM_ENTRYENABLE12_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE12_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE12_VAL_S 0U + +//****************************************************************************** +// Register: ENTRYENABLE13 +//****************************************************************************** +// Field: [15:0] val +// +// Source matching entry enable bits for entry 48-63 of PAN 1 +#define PBE_IEEE_RAM_ENTRYENABLE13_VAL_W 16U +#define PBE_IEEE_RAM_ENTRYENABLE13_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_ENTRYENABLE13_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING10 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 0-15 of PAN 1 +#define PBE_IEEE_RAM_FRAMEPENDING10_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING10_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING10_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING11 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 16-31 of PAN 1 +#define PBE_IEEE_RAM_FRAMEPENDING11_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING11_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING11_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING12 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 32-47 of PAN 1 +#define PBE_IEEE_RAM_FRAMEPENDING12_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING12_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING12_VAL_S 0U + +//****************************************************************************** +// Register: FRAMEPENDING13 +//****************************************************************************** +// Field: [15:0] val +// +// Frame pending bits for source matching entry 48-63 of PAN 1 +#define PBE_IEEE_RAM_FRAMEPENDING13_VAL_W 16U +#define PBE_IEEE_RAM_FRAMEPENDING13_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_FRAMEPENDING13_VAL_S 0U + +//****************************************************************************** +// Register: PANCFGED +//****************************************************************************** +// Field: [15:0] val +// +// PANID of the PAN for which there was a match +#define PBE_IEEE_RAM_PANCFGED_VAL_W 16U +#define PBE_IEEE_RAM_PANCFGED_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PANCFGED_VAL_S 0U + +//****************************************************************************** +// Register: TMPFCF +//****************************************************************************** +// Field: [15:0] val +// +// Frame Control Field received from the frame +#define PBE_IEEE_RAM_TMPFCF_VAL_W 16U +#define PBE_IEEE_RAM_TMPFCF_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_TMPFCF_VAL_S 0U + +//****************************************************************************** +// Register: CFGAUTOACK +//****************************************************************************** +// Field: [9:9] ackmode +// +// Control the filtering process of sequence number +#define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE 0x0200U +#define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_M 0x0200U +#define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_S 9U +#define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_NOFILT 0x0000U +#define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_FILT 0x0200U + +// Field: [8:8] flagreq +// +// Control the status flag towards MCU, when timeout occured waiting for Imm-Ack frame +#define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ 0x0100U +#define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_M 0x0100U +#define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_S 8U +#define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_DIS 0x0000U +#define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_EN 0x0100U + +// Field: [7:0] expseqnm +// +// Expected sequence number to correlate with the received one +#define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_W 8U +#define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_M 0x00FFU +#define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_S 0U + +//****************************************************************************** +// Register: MACCMDID +//****************************************************************************** +// Field: [7:0] val +// +// MAC command frame command ID field received +#define PBE_IEEE_RAM_MACCMDID_VAL_W 8U +#define PBE_IEEE_RAM_MACCMDID_VAL_M 0x00FFU +#define PBE_IEEE_RAM_MACCMDID_VAL_S 0U + +//****************************************************************************** +// Register: ACKSTATUS +//****************************************************************************** +// Field: [4:4] crcok +// +// ACKDONE event is raised indicating the frame was received with CRC ok +#define PBE_IEEE_RAM_ACKSTATUS_CRCOK 0x0010U +#define PBE_IEEE_RAM_ACKSTATUS_CRCOK_M 0x0010U +#define PBE_IEEE_RAM_ACKSTATUS_CRCOK_S 4U + +// Field: [3:3] ignored +// +// ACKDONE event is raised indicating the frame was received but ignored (seq. number mismatch included) +#define PBE_IEEE_RAM_ACKSTATUS_IGNORED 0x0008U +#define PBE_IEEE_RAM_ACKSTATUS_IGNORED_M 0x0008U +#define PBE_IEEE_RAM_ACKSTATUS_IGNORED_S 3U + +// Field: [2:2] otherfrm +// +// ACKDONE event is raised indicating other frame than ACK has been received +#define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM 0x0004U +#define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM_M 0x0004U +#define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM_S 2U + +// Field: [1:1] crcerr +// +// ACKDONE event is raised indicating the frame was received with CRC error +#define PBE_IEEE_RAM_ACKSTATUS_CRCERR 0x0002U +#define PBE_IEEE_RAM_ACKSTATUS_CRCERR_M 0x0002U +#define PBE_IEEE_RAM_ACKSTATUS_CRCERR_S 1U + +// Field: [0:0] synctimeout +// +// ACKDONE event is raised indicating in the receiving window no ACK arrived +#define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT 0x0001U +#define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT_M 0x0001U +#define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT_S 0U + +//****************************************************************************** +// Register: CORRCNT +//****************************************************************************** +// Field: [7:0] val +// +// Counter of MDMPROG events to be used for CCA mode 2 +#define PBE_IEEE_RAM_CORRCNT_VAL_W 8U +#define PBE_IEEE_RAM_CORRCNT_VAL_M 0x00FFU +#define PBE_IEEE_RAM_CORRCNT_VAL_S 0U + +//****************************************************************************** +// Register: PAN0_SRC_MATCH_SHORT_START +//****************************************************************************** +// Field: [15:0] val +// +// First entry of short source match table for PAN 0 +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_W 16U +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_S 0U + +//****************************************************************************** +// Register: PAN0_SRC_MATCH_EXT_START +//****************************************************************************** +// Field: [15:0] val +// +// First entry of extended source match table for PAN 0 if present +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_W 16U +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_S 0U + +//****************************************************************************** +// Register: PAN1_SRC_MATCH_SHORT_START +//****************************************************************************** +// Field: [15:0] val +// +// First entry of short source match table for PAN 1 +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_W 16U +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_S 0U + +//****************************************************************************** +// Register: PAN1_SRC_MATCH_EXT_START +//****************************************************************************** +// Field: [15:0] val +// +// First entry of extended source match table for PAN 1 if present +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_W 16U +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_M 0xFFFFU +#define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_S 0U + + +#endif // __PBE_IEEE_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_regdef_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_regdef_regs.h new file mode 100644 index 00000000..7b17c0c6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/pbe_ieee_regdef_regs.h @@ -0,0 +1,199 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:08:58 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 3845d842252929665292454e422463ea797f6c83 +// +// =========================================================================== + + +#ifndef __PBE_IEEE_REGDEF_REGS_H +#define __PBE_IEEE_REGDEF_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// Packet Building Engine (PBE) interrupt generation register +#define PBE_IEEE_REGDEF_O_IRQ 0x00000010U + +// PBE API Operation Register +#define PBE_IEEE_REGDEF_O_API 0x00000030U + +//****************************************************************************** +// Register: IRQ +//****************************************************************************** +// Field: [15:15] operror +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_OPERROR 0x00008000U +#define PBE_IEEE_REGDEF_IRQ_OPERROR_M 0x00008000U +#define PBE_IEEE_REGDEF_IRQ_OPERROR_S 15U +#define PBE_IEEE_REGDEF_IRQ_OPERROR_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_OPERROR_ACTIVE 0x00008000U + +// Field: [14:14] unused14 +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_UNUSED14 0x00004000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED14_M 0x00004000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED14_S 14U +#define PBE_IEEE_REGDEF_IRQ_UNUSED14_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED14_ACTIVE 0x00004000U + +// Field: [13:13] txdone +// +// Packet transmitted. MCU shall deallocate or retry. +#define PBE_IEEE_REGDEF_IRQ_TXDONE 0x00002000U +#define PBE_IEEE_REGDEF_IRQ_TXDONE_M 0x00002000U +#define PBE_IEEE_REGDEF_IRQ_TXDONE_S 13U +#define PBE_IEEE_REGDEF_IRQ_TXDONE_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_TXDONE_ACTIVE 0x00002000U + +// Field: [12:12] txack +// +// ACK transmitted +#define PBE_IEEE_REGDEF_IRQ_TXACK 0x00001000U +#define PBE_IEEE_REGDEF_IRQ_TXACK_M 0x00001000U +#define PBE_IEEE_REGDEF_IRQ_TXACK_S 12U +#define PBE_IEEE_REGDEF_IRQ_TXACK_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_TXACK_ACTIVE 0x00001000U + +// Field: [11:11] unused11 +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_UNUSED11 0x00000800U +#define PBE_IEEE_REGDEF_IRQ_UNUSED11_M 0x00000800U +#define PBE_IEEE_REGDEF_IRQ_UNUSED11_S 11U +#define PBE_IEEE_REGDEF_IRQ_UNUSED11_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED11_ACTIVE 0x00000800U + +// Field: [10:10] unused10 +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_UNUSED10 0x00000400U +#define PBE_IEEE_REGDEF_IRQ_UNUSED10_M 0x00000400U +#define PBE_IEEE_REGDEF_IRQ_UNUSED10_S 10U +#define PBE_IEEE_REGDEF_IRQ_UNUSED10_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED10_ACTIVE 0x00000400U + +// Field: [9:9] unused9 +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_UNUSED9 0x00000200U +#define PBE_IEEE_REGDEF_IRQ_UNUSED9_M 0x00000200U +#define PBE_IEEE_REGDEF_IRQ_UNUSED9_S 9U +#define PBE_IEEE_REGDEF_IRQ_UNUSED9_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED9_ACTIVE 0x00000200U + +// Field: [8:8] rxok +// +// Packet received with CRC OK and not to be ignored by the MCU +#define PBE_IEEE_REGDEF_IRQ_RXOK 0x00000100U +#define PBE_IEEE_REGDEF_IRQ_RXOK_M 0x00000100U +#define PBE_IEEE_REGDEF_IRQ_RXOK_S 8U +#define PBE_IEEE_REGDEF_IRQ_RXOK_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_RXOK_ACTIVE 0x00000100U + +// Field: [7:7] rxfovfl +// +// Packet received which did not fit in the RX FIFO and was not to be discarded. +#define PBE_IEEE_REGDEF_IRQ_RXFOVFL 0x00000080U +#define PBE_IEEE_REGDEF_IRQ_RXFOVFL_M 0x00000080U +#define PBE_IEEE_REGDEF_IRQ_RXFOVFL_S 7U +#define PBE_IEEE_REGDEF_IRQ_RXFOVFL_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_RXFOVFL_ACTIVE 0x00000080U + +// Field: [6:6] ackdone +// +// ACK event that is raised on successful or not ACK receptions +#define PBE_IEEE_REGDEF_IRQ_ACKDONE 0x00000040U +#define PBE_IEEE_REGDEF_IRQ_ACKDONE_M 0x00000040U +#define PBE_IEEE_REGDEF_IRQ_ACKDONE_S 6U +#define PBE_IEEE_REGDEF_IRQ_ACKDONE_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_ACKDONE_ACTIVE 0x00000040U + +// Field: [5:5] rxign +// +// Packet received with correct CRC, but may be ignored by MCU +#define PBE_IEEE_REGDEF_IRQ_RXIGN 0x00000020U +#define PBE_IEEE_REGDEF_IRQ_RXIGN_M 0x00000020U +#define PBE_IEEE_REGDEF_IRQ_RXIGN_S 5U +#define PBE_IEEE_REGDEF_IRQ_RXIGN_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_RXIGN_ACTIVE 0x00000020U + +// Field: [4:4] rxnok +// +// Packet received with CRC error, no data may be trusted +#define PBE_IEEE_REGDEF_IRQ_RXNOK 0x00000010U +#define PBE_IEEE_REGDEF_IRQ_RXNOK_M 0x00000010U +#define PBE_IEEE_REGDEF_IRQ_RXNOK_S 4U +#define PBE_IEEE_REGDEF_IRQ_RXNOK_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_RXNOK_ACTIVE 0x00000010U + +// Field: [3:3] unused3 +// +// Software defined interrupt +#define PBE_IEEE_REGDEF_IRQ_UNUSED3 0x00000008U +#define PBE_IEEE_REGDEF_IRQ_UNUSED3_M 0x00000008U +#define PBE_IEEE_REGDEF_IRQ_UNUSED3_S 3U +#define PBE_IEEE_REGDEF_IRQ_UNUSED3_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_UNUSED3_ACTIVE 0x00000008U + +// Field: [2:2] ffok +// +// Packet received had a successful frame filtering +#define PBE_IEEE_REGDEF_IRQ_FFOK 0x00000004U +#define PBE_IEEE_REGDEF_IRQ_FFOK_M 0x00000004U +#define PBE_IEEE_REGDEF_IRQ_FFOK_S 2U +#define PBE_IEEE_REGDEF_IRQ_FFOK_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_FFOK_ACTIVE 0x00000004U + +// Field: [1:1] pingrsp +// +// PBE responds to PBEOP_PING, basic test to see if the battery is connected. +#define PBE_IEEE_REGDEF_IRQ_PINGRSP 0x00000002U +#define PBE_IEEE_REGDEF_IRQ_PINGRSP_M 0x00000002U +#define PBE_IEEE_REGDEF_IRQ_PINGRSP_S 1U +#define PBE_IEEE_REGDEF_IRQ_PINGRSP_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_PINGRSP_ACTIVE 0x00000002U + +// Field: [0:0] opdone +// +// The operation commanded on PBEAPI has completed succesfully. +#define PBE_IEEE_REGDEF_IRQ_OPDONE 0x00000001U +#define PBE_IEEE_REGDEF_IRQ_OPDONE_M 0x00000001U +#define PBE_IEEE_REGDEF_IRQ_OPDONE_S 0U +#define PBE_IEEE_REGDEF_IRQ_OPDONE_OFF 0x00000000U +#define PBE_IEEE_REGDEF_IRQ_OPDONE_ACTIVE 0x00000001U + +//****************************************************************************** +// Register: API +//****************************************************************************** +// Field: [4:0] op +// +// PBE Operation +#define PBE_IEEE_REGDEF_API_OP_W 5U +#define PBE_IEEE_REGDEF_API_OP_M 0x0000001FU +#define PBE_IEEE_REGDEF_API_OP_S 0U +#define PBE_IEEE_REGDEF_API_OP_PING 0x00000000U +#define PBE_IEEE_REGDEF_API_OP_STOP 0x00000001U +#define PBE_IEEE_REGDEF_API_OP_EOPSTOP 0x00000002U +#define PBE_IEEE_REGDEF_API_OP_TX 0x0000001CU +#define PBE_IEEE_REGDEF_API_OP_RX 0x0000001DU + + +#endif // __PBE_IEEE_REGDEF_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_coherent_pll_regdef_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_coherent_pll_regdef_regs.h new file mode 100644 index 00000000..ec2aa6ba --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_coherent_pll_regdef_regs.h @@ -0,0 +1,31 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:01 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_coherent_pll_regdef_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_cpll_ram_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_coherent_pll_regdef_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_cpll_ram_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_coherent_pll_regdef_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: e5638c3064d5d47ba3b4c8e2e4746b66c87ca536 +// +// =========================================================================== + + +#ifndef __RFE_COHERENT_PLL_REGDEF_REGS_H +#define __RFE_COHERENT_PLL_REGDEF_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** + +#endif // __RFE_COHERENT_PLL_REGDEF_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_common_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_common_ram_regs.h new file mode 100644 index 00000000..6ce31ecc --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_common_ram_regs.h @@ -0,0 +1,766 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:02 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/common/doc/rfe_common_ram_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/common/doc/rfe_common_ram_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/common/doc/rfe_common_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: d6fcb11658d75207ef1e20e66c8f03c3d5bf2cfe +// +// =========================================================================== + + +#ifndef __RFE_COMMON_RAM_REGS_H +#define __RFE_COMMON_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// RFE Synth Controls +#define RFE_COMMON_RAM_O_SYNTHCTL 0x00000804U + +// TDC Calibration 0 +#define RFE_COMMON_RAM_O_TDCCAL0 0x00000806U + +// TDC Calibration 1 +#define RFE_COMMON_RAM_O_TDCCAL1 0x00000808U + +// TDC Calibration 2 +#define RFE_COMMON_RAM_O_TDCCAL2 0x0000080AU + +// TDC Stop Time PLL Configuration +#define RFE_COMMON_RAM_O_TDCPLL 0x0000080CU + +// Derived Constant For KDCO Gain Estimation +#define RFE_COMMON_RAM_O_K1LSB 0x0000080EU + +// Derived Constant For KDCO Gain Estimation +#define RFE_COMMON_RAM_O_K1MSB 0x00000810U + +// Derived Constant Used to Calculate Pre-Lock Loop Filter Ki +#define RFE_COMMON_RAM_O_K2BL 0x00000812U + +// Derived Constant Used to Calculate Post-Lock Loop Filter Ki +#define RFE_COMMON_RAM_O_K2AL 0x00000814U + +// Derived Constant Used to Calculate Pre-Lock Loop Filter Kp +#define RFE_COMMON_RAM_O_K3BL 0x00000816U + +// Derived Constant Used to Calculate Post-Lock Loop Filter Kp +#define RFE_COMMON_RAM_O_K3AL 0x00000818U + +// Derived Constant Used to Calculate DTX Gain +#define RFE_COMMON_RAM_O_K5 0x0000081AU + +// Receive Intermediate Frequency +#define RFE_COMMON_RAM_O_RXIF 0x0000081CU + +// Transmit Intermediate Frequency +#define RFE_COMMON_RAM_O_TXIF 0x0000081EU + +// RTRIM Offset +#define RFE_COMMON_RAM_O_RTRIMOFF 0x00000820U + +// Minimum RTRIM Value +#define RFE_COMMON_RAM_O_RTRIMMIN 0x00000822U + +// Divider Initial Control +#define RFE_COMMON_RAM_O_DIVI 0x00000824U + +// Divider Final Control +#define RFE_COMMON_RAM_O_DIVF 0x00000826U + +// Divider LDO Initial Control +#define RFE_COMMON_RAM_O_DIVLDOI 0x00000828U + +// Divider LDO Final Control +#define RFE_COMMON_RAM_O_DIVLDOF 0x0000082AU + +// +#define RFE_COMMON_RAM_O_DIVLDOIOFF 0x0000082CU + +// ALO Power Up LDO Settling Time +#define RFE_COMMON_RAM_O_LDOSETTLE 0x0000082EU + +// Charge Injection Settling Time +#define RFE_COMMON_RAM_O_CHRGSETTLE 0x00000830U + +// DCOLDO Settling Time +#define RFE_COMMON_RAM_O_DCOSETTLE 0x00000832U + +// +#define RFE_COMMON_RAM_O_IFAMPRFLDOTX 0x00000834U + +// +#define RFE_COMMON_RAM_O_IFAMPRFLDODEFAULT 0x00000836U + +// Loop Filter Pre-Lock Ki +#define RFE_COMMON_RAM_O_LFKIBL 0x00000838U + +// Loop Filter Pre-Lock Kp +#define RFE_COMMON_RAM_O_LFKPBL 0x0000083AU + +// Estimated 2^24/(KDCO) +#define RFE_COMMON_RAM_O_IKT 0x0000083CU + +// Phy specific RSSI offset +#define RFE_COMMON_RAM_O_PHYRSSIOFFSET 0x0000083EU + +// Shadow register for SPARE0 +#define RFE_COMMON_RAM_O_SPARE0SHADOW 0x00000840U + +// Shadow register for SPARE1 +#define RFE_COMMON_RAM_O_SPARE1SHADOW 0x00000842U + +// AGC type information +#define RFE_COMMON_RAM_O_AGCINFO 0x00000844U + +//****************************************************************************** +// Register: SYNTHCTL +//****************************************************************************** +// Field: [7:7] chrgfilt +// +// Control dynamic control of CHRGFILT +#define RFE_COMMON_RAM_SYNTHCTL_CHRGFILT 0x0080U +#define RFE_COMMON_RAM_SYNTHCTL_CHRGFILT_M 0x0080U +#define RFE_COMMON_RAM_SYNTHCTL_CHRGFILT_S 7U + +// Field: [6:6] vrefbp +// +// Control dynamic control of VREFBYPASS +#define RFE_COMMON_RAM_SYNTHCTL_VREFBP 0x0040U +#define RFE_COMMON_RAM_SYNTHCTL_VREFBP_M 0x0040U +#define RFE_COMMON_RAM_SYNTHCTL_VREFBP_S 6U + +// Field: [5:5] txwaitmod +// +// Wait for modem or not when starting TX +#define RFE_COMMON_RAM_SYNTHCTL_TXWAITMOD 0x0020U +#define RFE_COMMON_RAM_SYNTHCTL_TXWAITMOD_M 0x0020U +#define RFE_COMMON_RAM_SYNTHCTL_TXWAITMOD_S 5U + +// Field: [4:4] phedisc +// +// Phase Error Discard Control For TX and RX +#define RFE_COMMON_RAM_SYNTHCTL_PHEDISC 0x0010U +#define RFE_COMMON_RAM_SYNTHCTL_PHEDISC_M 0x0010U +#define RFE_COMMON_RAM_SYNTHCTL_PHEDISC_S 4U +#define RFE_COMMON_RAM_SYNTHCTL_PHEDISC_DIS 0x0000U +#define RFE_COMMON_RAM_SYNTHCTL_PHEDISC_EN 0x0010U + +// Field: [3:3] rtrimtst +// +// DCO Amplitude Trimming Mode +#define RFE_COMMON_RAM_SYNTHCTL_RTRIMTST 0x0008U +#define RFE_COMMON_RAM_SYNTHCTL_RTRIMTST_M 0x0008U +#define RFE_COMMON_RAM_SYNTHCTL_RTRIMTST_S 3U +#define RFE_COMMON_RAM_SYNTHCTL_RTRIMTST_DIS 0x0000U +#define RFE_COMMON_RAM_SYNTHCTL_RTRIMTST_EN 0x0008U + +// Field: [2:2] iir +// +// Post-lock IIR Filter Control +#define RFE_COMMON_RAM_SYNTHCTL_IIR 0x0004U +#define RFE_COMMON_RAM_SYNTHCTL_IIR_M 0x0004U +#define RFE_COMMON_RAM_SYNTHCTL_IIR_S 2U +#define RFE_COMMON_RAM_SYNTHCTL_IIR_DIS 0x0000U +#define RFE_COMMON_RAM_SYNTHCTL_IIR_EN 0x0004U + +// Field: [1:1] refdthr +// +// Post-lock Reference Dithering Control +#define RFE_COMMON_RAM_SYNTHCTL_REFDTHR 0x0002U +#define RFE_COMMON_RAM_SYNTHCTL_REFDTHR_M 0x0002U +#define RFE_COMMON_RAM_SYNTHCTL_REFDTHR_S 1U +#define RFE_COMMON_RAM_SYNTHCTL_REFDTHR_DIS 0x0000U +#define RFE_COMMON_RAM_SYNTHCTL_REFDTHR_EN 0x0002U + +// Field: [0:0] fcdem +// +// TX Finecode DEM Control +#define RFE_COMMON_RAM_SYNTHCTL_FCDEM 0x0001U +#define RFE_COMMON_RAM_SYNTHCTL_FCDEM_M 0x0001U +#define RFE_COMMON_RAM_SYNTHCTL_FCDEM_S 0U +#define RFE_COMMON_RAM_SYNTHCTL_FCDEM_DIS 0x0000U +#define RFE_COMMON_RAM_SYNTHCTL_FCDEM_EN 0x0001U + +//****************************************************************************** +// Register: TDCCAL0 +//****************************************************************************** +// Field: [10:8] stop +// +// Stop configuration value. When CFG.RTRIMTST = 1, this field shall be copied into TDCPLL.STOP (RCL-L/TFW). +#define RFE_COMMON_RAM_TDCCAL0_STOP_W 3U +#define RFE_COMMON_RAM_TDCCAL0_STOP_M 0x0700U +#define RFE_COMMON_RAM_TDCCAL0_STOP_S 8U + +//****************************************************************************** +// Register: TDCCAL1 +//****************************************************************************** +// Field: [7:0] sub +// +// Offset to subtract from TDC data during TDC gain calibration. +#define RFE_COMMON_RAM_TDCCAL1_SUB_W 8U +#define RFE_COMMON_RAM_TDCCAL1_SUB_M 0x00FFU +#define RFE_COMMON_RAM_TDCCAL1_SUB_S 0U + +//****************************************************************************** +// Register: TDCCAL2 +//****************************************************************************** +// Field: [5:0] avg +// +// Averaging constant, AVG = 2^CAL0.TDCAVG * (TDCCAL0.STOP+1). +#define RFE_COMMON_RAM_TDCCAL2_AVG_W 6U +#define RFE_COMMON_RAM_TDCCAL2_AVG_M 0x003FU +#define RFE_COMMON_RAM_TDCCAL2_AVG_S 0U + +//****************************************************************************** +// Register: TDCPLL +//****************************************************************************** +// Field: [10:8] stop +// +// Stop configuration value. +#define RFE_COMMON_RAM_TDCPLL_STOP_W 3U +#define RFE_COMMON_RAM_TDCPLL_STOP_M 0x0700U +#define RFE_COMMON_RAM_TDCPLL_STOP_S 8U + +//****************************************************************************** +// Register: K1LSB +//****************************************************************************** +// Field: [15:0] val +// +// LSB value. +#define RFE_COMMON_RAM_K1LSB_VAL_W 16U +#define RFE_COMMON_RAM_K1LSB_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_K1LSB_VAL_S 0U + +//****************************************************************************** +// Register: K1MSB +//****************************************************************************** +// Field: [15:0] val +// +// MSB value. +#define RFE_COMMON_RAM_K1MSB_VAL_W 16U +#define RFE_COMMON_RAM_K1MSB_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_K1MSB_VAL_S 0U + +//****************************************************************************** +// Register: K2BL +//****************************************************************************** +// Field: [15:15] hpm +// +// High Precision Mode +#define RFE_COMMON_RAM_K2BL_HPM 0x8000U +#define RFE_COMMON_RAM_K2BL_HPM_M 0x8000U +#define RFE_COMMON_RAM_K2BL_HPM_S 15U + +// Field: [14:0] val +// +// Value +#define RFE_COMMON_RAM_K2BL_VAL_W 15U +#define RFE_COMMON_RAM_K2BL_VAL_M 0x7FFFU +#define RFE_COMMON_RAM_K2BL_VAL_S 0U + +//****************************************************************************** +// Register: K2AL +//****************************************************************************** +// Field: [15:15] hpm +// +// High Precision Mode +#define RFE_COMMON_RAM_K2AL_HPM 0x8000U +#define RFE_COMMON_RAM_K2AL_HPM_M 0x8000U +#define RFE_COMMON_RAM_K2AL_HPM_S 15U + +// Field: [14:0] val +// +// Value +#define RFE_COMMON_RAM_K2AL_VAL_W 15U +#define RFE_COMMON_RAM_K2AL_VAL_M 0x7FFFU +#define RFE_COMMON_RAM_K2AL_VAL_S 0U + +//****************************************************************************** +// Register: K3BL +//****************************************************************************** +// Field: [15:0] val +// +// Value +#define RFE_COMMON_RAM_K3BL_VAL_W 16U +#define RFE_COMMON_RAM_K3BL_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_K3BL_VAL_S 0U + +//****************************************************************************** +// Register: K3AL +//****************************************************************************** +// Field: [15:0] val +// +// Value +#define RFE_COMMON_RAM_K3AL_VAL_W 16U +#define RFE_COMMON_RAM_K3AL_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_K3AL_VAL_S 0U + +//****************************************************************************** +// Register: K5 +//****************************************************************************** +// Field: [15:0] val +// +// Value +#define RFE_COMMON_RAM_K5_VAL_W 16U +#define RFE_COMMON_RAM_K5_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_K5_VAL_S 0U + +//****************************************************************************** +// Register: RXIF +//****************************************************************************** +// Field: [11:0] foff +// +// Signed frequency offset. +#define RFE_COMMON_RAM_RXIF_FOFF_W 12U +#define RFE_COMMON_RAM_RXIF_FOFF_M 0x0FFFU +#define RFE_COMMON_RAM_RXIF_FOFF_S 0U + +//****************************************************************************** +// Register: TXIF +//****************************************************************************** +// Field: [11:0] foff +// +// Signed frequency offset. +#define RFE_COMMON_RAM_TXIF_FOFF_W 12U +#define RFE_COMMON_RAM_TXIF_FOFF_M 0x0FFFU +#define RFE_COMMON_RAM_TXIF_FOFF_S 0U + +//****************************************************************************** +// Register: RTRIMOFF +//****************************************************************************** +// Field: [3:0] val +// +// Unsigned offset to be added to possibly temperature compensated RTRIM from FCFG. +#define RFE_COMMON_RAM_RTRIMOFF_VAL_W 4U +#define RFE_COMMON_RAM_RTRIMOFF_VAL_M 0x000FU +#define RFE_COMMON_RAM_RTRIMOFF_VAL_S 0U + +//****************************************************************************** +// Register: RTRIMMIN +//****************************************************************************** +// Field: [3:0] val +// +// Possibly temperature compensated RTRIM from FCFG adjusted by RTRIMOFF.VAL must be at least this value. +#define RFE_COMMON_RAM_RTRIMMIN_VAL_W 4U +#define RFE_COMMON_RAM_RTRIMMIN_VAL_M 0x000FU +#define RFE_COMMON_RAM_RTRIMMIN_VAL_S 0U + +//****************************************************************************** +// Register: DIVI +//****************************************************************************** +// Field: [15:15] pdet +// +// Peak Detector Mode +#define RFE_COMMON_RAM_DIVI_PDET 0x8000U +#define RFE_COMMON_RAM_DIVI_PDET_M 0x8000U +#define RFE_COMMON_RAM_DIVI_PDET_S 15U + +// Field: [14:12] nmireftrim +// +// NMOS Bias Voltage Trim +#define RFE_COMMON_RAM_DIVI_NMIREFTRIM_W 3U +#define RFE_COMMON_RAM_DIVI_NMIREFTRIM_M 0x7000U +#define RFE_COMMON_RAM_DIVI_NMIREFTRIM_S 12U + +// Field: [11:9] pmireftrim +// +// PMOS Bias Voltage Trim +#define RFE_COMMON_RAM_DIVI_PMIREFTRIM_W 3U +#define RFE_COMMON_RAM_DIVI_PMIREFTRIM_M 0x0E00U +#define RFE_COMMON_RAM_DIVI_PMIREFTRIM_S 9U + +// Field: [8:8] txboost +// +// TX Buffer Boost +#define RFE_COMMON_RAM_DIVI_TXBOOST 0x0100U +#define RFE_COMMON_RAM_DIVI_TXBOOST_M 0x0100U +#define RFE_COMMON_RAM_DIVI_TXBOOST_S 8U +#define RFE_COMMON_RAM_DIVI_TXBOOST_DEFAULT 0x0000U +#define RFE_COMMON_RAM_DIVI_TXBOOST_INCREASED 0x0100U + +// Field: [7:7] s1gfrc +// +// S1G Power Switch Force +#define RFE_COMMON_RAM_DIVI_S1GFRC 0x0080U +#define RFE_COMMON_RAM_DIVI_S1GFRC_M 0x0080U +#define RFE_COMMON_RAM_DIVI_S1GFRC_S 7U +#define RFE_COMMON_RAM_DIVI_S1GFRC_DIS 0x0000U +#define RFE_COMMON_RAM_DIVI_S1GFRC_EN 0x0080U + +// Field: [6:5] bufgain +// +// Not connected or used in LRF +#define RFE_COMMON_RAM_DIVI_BUFGAIN_W 2U +#define RFE_COMMON_RAM_DIVI_BUFGAIN_M 0x0060U +#define RFE_COMMON_RAM_DIVI_BUFGAIN_S 5U + +// Field: [4:4] bias +// +// Not connected or used in LRF +#define RFE_COMMON_RAM_DIVI_BIAS 0x0010U +#define RFE_COMMON_RAM_DIVI_BIAS_M 0x0010U +#define RFE_COMMON_RAM_DIVI_BIAS_S 4U + +// Field: [3:3] out +// +// Divider Output +#define RFE_COMMON_RAM_DIVI_OUT 0x0008U +#define RFE_COMMON_RAM_DIVI_OUT_M 0x0008U +#define RFE_COMMON_RAM_DIVI_OUT_S 3U +#define RFE_COMMON_RAM_DIVI_OUT_FE_S1G 0x0000U +#define RFE_COMMON_RAM_DIVI_OUT_FE_2G4 0x0008U + +// Field: [2:0] ratio +// +// Divider Ratio +#define RFE_COMMON_RAM_DIVI_RATIO_W 3U +#define RFE_COMMON_RAM_DIVI_RATIO_M 0x0007U +#define RFE_COMMON_RAM_DIVI_RATIO_S 0U + +//****************************************************************************** +// Register: DIVF +//****************************************************************************** +// Field: [15:15] pdet +// +// Peak Detector Mode +#define RFE_COMMON_RAM_DIVF_PDET 0x8000U +#define RFE_COMMON_RAM_DIVF_PDET_M 0x8000U +#define RFE_COMMON_RAM_DIVF_PDET_S 15U + +// Field: [14:12] nmireftrim +// +// NMOS Bias Voltage Trim +#define RFE_COMMON_RAM_DIVF_NMIREFTRIM_W 3U +#define RFE_COMMON_RAM_DIVF_NMIREFTRIM_M 0x7000U +#define RFE_COMMON_RAM_DIVF_NMIREFTRIM_S 12U + +// Field: [11:9] pmireftrim +// +// PMOS Bias Voltage Trim +#define RFE_COMMON_RAM_DIVF_PMIREFTRIM_W 3U +#define RFE_COMMON_RAM_DIVF_PMIREFTRIM_M 0x0E00U +#define RFE_COMMON_RAM_DIVF_PMIREFTRIM_S 9U + +// Field: [8:8] txboost +// +// TX Buffer Boost +#define RFE_COMMON_RAM_DIVF_TXBOOST 0x0100U +#define RFE_COMMON_RAM_DIVF_TXBOOST_M 0x0100U +#define RFE_COMMON_RAM_DIVF_TXBOOST_S 8U +#define RFE_COMMON_RAM_DIVF_TXBOOST_DEFAULT 0x0000U +#define RFE_COMMON_RAM_DIVF_TXBOOST_INCREASED 0x0100U + +// Field: [7:7] s1gfrc +// +// S1G Power Switch Force +#define RFE_COMMON_RAM_DIVF_S1GFRC 0x0080U +#define RFE_COMMON_RAM_DIVF_S1GFRC_M 0x0080U +#define RFE_COMMON_RAM_DIVF_S1GFRC_S 7U +#define RFE_COMMON_RAM_DIVF_S1GFRC_DIS 0x0000U +#define RFE_COMMON_RAM_DIVF_S1GFRC_EN 0x0080U + +// Field: [6:5] bufgain +// +// Not connected or used in LRF +#define RFE_COMMON_RAM_DIVF_BUFGAIN_W 2U +#define RFE_COMMON_RAM_DIVF_BUFGAIN_M 0x0060U +#define RFE_COMMON_RAM_DIVF_BUFGAIN_S 5U + +// Field: [4:4] bias +// +// Not connected or used in LRF +#define RFE_COMMON_RAM_DIVF_BIAS 0x0010U +#define RFE_COMMON_RAM_DIVF_BIAS_M 0x0010U +#define RFE_COMMON_RAM_DIVF_BIAS_S 4U + +// Field: [3:3] out +// +// Divider Output +#define RFE_COMMON_RAM_DIVF_OUT 0x0008U +#define RFE_COMMON_RAM_DIVF_OUT_M 0x0008U +#define RFE_COMMON_RAM_DIVF_OUT_S 3U +#define RFE_COMMON_RAM_DIVF_OUT_FE_S1G 0x0000U +#define RFE_COMMON_RAM_DIVF_OUT_FE_2G4 0x0008U + +// Field: [2:0] ratio +// +// Divider Ratio +#define RFE_COMMON_RAM_DIVF_RATIO_W 3U +#define RFE_COMMON_RAM_DIVF_RATIO_M 0x0007U +#define RFE_COMMON_RAM_DIVF_RATIO_S 0U + +//****************************************************************************** +// Register: DIVLDOI +//****************************************************************************** +// Field: [15:15] itest +// +// ITEST Control +#define RFE_COMMON_RAM_DIVLDOI_ITEST 0x8000U +#define RFE_COMMON_RAM_DIVLDOI_ITEST_M 0x8000U +#define RFE_COMMON_RAM_DIVLDOI_ITEST_S 15U + +// Field: [14:8] vouttrim +// +// VOUT Trim Code +#define RFE_COMMON_RAM_DIVLDOI_VOUTTRIM_W 7U +#define RFE_COMMON_RAM_DIVLDOI_VOUTTRIM_M 0x7F00U +#define RFE_COMMON_RAM_DIVLDOI_VOUTTRIM_S 8U + +// Field: [7:7] itst +// +// ITEST Buffer Block Enable(Not Connected) +#define RFE_COMMON_RAM_DIVLDOI_ITST 0x0080U +#define RFE_COMMON_RAM_DIVLDOI_ITST_M 0x0080U +#define RFE_COMMON_RAM_DIVLDOI_ITST_S 7U + +// Field: [6:4] tmux +// +// TMUX control bits +#define RFE_COMMON_RAM_DIVLDOI_TMUX_W 3U +#define RFE_COMMON_RAM_DIVLDOI_TMUX_M 0x0070U +#define RFE_COMMON_RAM_DIVLDOI_TMUX_S 4U +#define RFE_COMMON_RAM_DIVLDOI_TMUX_OFF 0x0000U +#define RFE_COMMON_RAM_DIVLDOI_TMUX_GND 0x0010U + +// Field: [2:2] mode +// +// High BW Operation +#define RFE_COMMON_RAM_DIVLDOI_MODE 0x0004U +#define RFE_COMMON_RAM_DIVLDOI_MODE_M 0x0004U +#define RFE_COMMON_RAM_DIVLDOI_MODE_S 2U +#define RFE_COMMON_RAM_DIVLDOI_MODE_NORM 0x0000U +#define RFE_COMMON_RAM_DIVLDOI_MODE_FAST 0x0004U + +// Field: [1:1] bypass +// +// Regulator Bypass +#define RFE_COMMON_RAM_DIVLDOI_BYPASS 0x0002U +#define RFE_COMMON_RAM_DIVLDOI_BYPASS_M 0x0002U +#define RFE_COMMON_RAM_DIVLDOI_BYPASS_S 1U +#define RFE_COMMON_RAM_DIVLDOI_BYPASS_DIS 0x0000U +#define RFE_COMMON_RAM_DIVLDOI_BYPASS_EN 0x0002U + +// Field: [0:0] ctl +// +// Regulator Control +#define RFE_COMMON_RAM_DIVLDOI_CTL 0x0001U +#define RFE_COMMON_RAM_DIVLDOI_CTL_M 0x0001U +#define RFE_COMMON_RAM_DIVLDOI_CTL_S 0U +#define RFE_COMMON_RAM_DIVLDOI_CTL_DIS 0x0000U +#define RFE_COMMON_RAM_DIVLDOI_CTL_EN 0x0001U + +//****************************************************************************** +// Register: DIVLDOF +//****************************************************************************** +// Field: [15:15] itest +// +// ITEST Control +#define RFE_COMMON_RAM_DIVLDOF_ITEST 0x8000U +#define RFE_COMMON_RAM_DIVLDOF_ITEST_M 0x8000U +#define RFE_COMMON_RAM_DIVLDOF_ITEST_S 15U + +// Field: [14:8] vouttrim +// +// VOUT Trim Code +#define RFE_COMMON_RAM_DIVLDOF_VOUTTRIM_W 7U +#define RFE_COMMON_RAM_DIVLDOF_VOUTTRIM_M 0x7F00U +#define RFE_COMMON_RAM_DIVLDOF_VOUTTRIM_S 8U + +// Field: [7:7] itst +// +// ITEST Buffer Block Enable(Not Connected) +#define RFE_COMMON_RAM_DIVLDOF_ITST 0x0080U +#define RFE_COMMON_RAM_DIVLDOF_ITST_M 0x0080U +#define RFE_COMMON_RAM_DIVLDOF_ITST_S 7U + +// Field: [6:4] tmux +// +// TMUX control bits +#define RFE_COMMON_RAM_DIVLDOF_TMUX_W 3U +#define RFE_COMMON_RAM_DIVLDOF_TMUX_M 0x0070U +#define RFE_COMMON_RAM_DIVLDOF_TMUX_S 4U +#define RFE_COMMON_RAM_DIVLDOF_TMUX_OFF 0x0000U +#define RFE_COMMON_RAM_DIVLDOF_TMUX_GND 0x0010U + +// Field: [2:2] mode +// +// High BW Operation +#define RFE_COMMON_RAM_DIVLDOF_MODE 0x0004U +#define RFE_COMMON_RAM_DIVLDOF_MODE_M 0x0004U +#define RFE_COMMON_RAM_DIVLDOF_MODE_S 2U +#define RFE_COMMON_RAM_DIVLDOF_MODE_NORM 0x0000U +#define RFE_COMMON_RAM_DIVLDOF_MODE_FAST 0x0004U + +// Field: [1:1] bypass +// +// Regulator Bypass +#define RFE_COMMON_RAM_DIVLDOF_BYPASS 0x0002U +#define RFE_COMMON_RAM_DIVLDOF_BYPASS_M 0x0002U +#define RFE_COMMON_RAM_DIVLDOF_BYPASS_S 1U +#define RFE_COMMON_RAM_DIVLDOF_BYPASS_DIS 0x0000U +#define RFE_COMMON_RAM_DIVLDOF_BYPASS_EN 0x0002U + +// Field: [0:0] ctl +// +// Regulator Control +#define RFE_COMMON_RAM_DIVLDOF_CTL 0x0001U +#define RFE_COMMON_RAM_DIVLDOF_CTL_M 0x0001U +#define RFE_COMMON_RAM_DIVLDOF_CTL_S 0U +#define RFE_COMMON_RAM_DIVLDOF_CTL_DIS 0x0000U +#define RFE_COMMON_RAM_DIVLDOF_CTL_EN 0x0001U + +//****************************************************************************** +// Register: DIVLDOIOFF +//****************************************************************************** +// Field: [6:0] val +// +// Offset that RCL uses to adjust DIVLDOI.VOUTTRIM during startup. +#define RFE_COMMON_RAM_DIVLDOIOFF_VAL_W 7U +#define RFE_COMMON_RAM_DIVLDOIOFF_VAL_M 0x007FU +#define RFE_COMMON_RAM_DIVLDOIOFF_VAL_S 0U + +//****************************************************************************** +// Register: LDOSETTLE +//****************************************************************************** +// Field: [9:0] val +// +// Value. Delay = (VAL+1)/24 (us). +#define RFE_COMMON_RAM_LDOSETTLE_VAL_W 10U +#define RFE_COMMON_RAM_LDOSETTLE_VAL_M 0x03FFU +#define RFE_COMMON_RAM_LDOSETTLE_VAL_S 0U + +//****************************************************************************** +// Register: CHRGSETTLE +//****************************************************************************** +// Field: [9:0] val +// +// Value. Delay = (VAL+1)/24 (us). +#define RFE_COMMON_RAM_CHRGSETTLE_VAL_W 10U +#define RFE_COMMON_RAM_CHRGSETTLE_VAL_M 0x03FFU +#define RFE_COMMON_RAM_CHRGSETTLE_VAL_S 0U + +//****************************************************************************** +// Register: DCOSETTLE +//****************************************************************************** +// Field: [9:0] val +// +// Value. Delay = 1.5 (us) + (VAL+1)/24 (us). Minimum value shall be 5. +#define RFE_COMMON_RAM_DCOSETTLE_VAL_W 10U +#define RFE_COMMON_RAM_DCOSETTLE_VAL_M 0x03FFU +#define RFE_COMMON_RAM_DCOSETTLE_VAL_S 0U + +//****************************************************************************** +// Register: IFAMPRFLDOTX +//****************************************************************************** +// Field: [15:9] trim +// +// Value to use in TX except low output power +#define RFE_COMMON_RAM_IFAMPRFLDOTX_TRIM_W 7U +#define RFE_COMMON_RAM_IFAMPRFLDOTX_TRIM_M 0xFE00U +#define RFE_COMMON_RAM_IFAMPRFLDOTX_TRIM_S 9U + +//****************************************************************************** +// Register: IFAMPRFLDODEFAULT +//****************************************************************************** +// Field: [15:9] trim +// +// Production trim value +#define RFE_COMMON_RAM_IFAMPRFLDODEFAULT_TRIM_W 7U +#define RFE_COMMON_RAM_IFAMPRFLDODEFAULT_TRIM_M 0xFE00U +#define RFE_COMMON_RAM_IFAMPRFLDODEFAULT_TRIM_S 9U + +//****************************************************************************** +// Register: LFKIBL +//****************************************************************************** +// Field: [12:12] hpm +// +// High Precision Mode +#define RFE_COMMON_RAM_LFKIBL_HPM 0x1000U +#define RFE_COMMON_RAM_LFKIBL_HPM_M 0x1000U +#define RFE_COMMON_RAM_LFKIBL_HPM_S 12U + +// Field: [11:0] ki +// +// KI written by RFE +#define RFE_COMMON_RAM_LFKIBL_KI_W 12U +#define RFE_COMMON_RAM_LFKIBL_KI_M 0x0FFFU +#define RFE_COMMON_RAM_LFKIBL_KI_S 0U + +//****************************************************************************** +// Register: LFKPBL +//****************************************************************************** +// Field: [14:0] kp +// +// KP written by RFE +#define RFE_COMMON_RAM_LFKPBL_KP_W 15U +#define RFE_COMMON_RAM_LFKPBL_KP_M 0x7FFFU +#define RFE_COMMON_RAM_LFKPBL_KP_S 0U + +//****************************************************************************** +// Register: IKT +//****************************************************************************** +// Field: [15:0] val +// +// Value +#define RFE_COMMON_RAM_IKT_VAL_W 16U +#define RFE_COMMON_RAM_IKT_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_IKT_VAL_S 0U + +//****************************************************************************** +// Register: PHYRSSIOFFSET +//****************************************************************************** +// Field: [7:0] val +// +// Unsinged number, offset between magnitude samples and dBm +#define RFE_COMMON_RAM_PHYRSSIOFFSET_VAL_W 8U +#define RFE_COMMON_RAM_PHYRSSIOFFSET_VAL_M 0x00FFU +#define RFE_COMMON_RAM_PHYRSSIOFFSET_VAL_S 0U + +//****************************************************************************** +// Register: SPARE0SHADOW +//****************************************************************************** +// Field: [15:0] val +// +// +#define RFE_COMMON_RAM_SPARE0SHADOW_VAL_W 16U +#define RFE_COMMON_RAM_SPARE0SHADOW_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_SPARE0SHADOW_VAL_S 0U + +//****************************************************************************** +// Register: SPARE1SHADOW +//****************************************************************************** +// Field: [15:0] val +// +// +#define RFE_COMMON_RAM_SPARE1SHADOW_VAL_W 16U +#define RFE_COMMON_RAM_SPARE1SHADOW_VAL_M 0xFFFFU +#define RFE_COMMON_RAM_SPARE1SHADOW_VAL_S 0U + +//****************************************************************************** +// Register: AGCINFO +//****************************************************************************** +// Field: [0:0] mode +// +// Information about AGC behavior of this PHY +#define RFE_COMMON_RAM_AGCINFO_MODE 0x0001U +#define RFE_COMMON_RAM_AGCINFO_MODE_M 0x0001U +#define RFE_COMMON_RAM_AGCINFO_MODE_S 0U +#define RFE_COMMON_RAM_AGCINFO_MODE_FAST 0x0000U +#define RFE_COMMON_RAM_AGCINFO_MODE_GEN 0x0001U + + +#endif // __RFE_COMMON_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_cpll_ram_regs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_cpll_ram_regs.h new file mode 100644 index 00000000..b8757cb2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/rfe_cpll_ram_regs.h @@ -0,0 +1,1084 @@ +// =========================================================================== +// This file is autogenerated, please DO NOT modify! +// +// Generated on 2024-05-23 12:09:02 +// by user: developer +// on machine: swtools +// CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll +// Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_coherent_pll_regdef_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_cpll_ram_regs.txt +// C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_coherent_pll_regdef_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_cpll_ram_regs.txt +// +// Relevant file version(s): +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 68a752a8737845355f7bdb320d25a59eac685840 +// +// /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/rfe/coherent_pll/doc/rfe_cpll_ram_regs.txt +// rcs-info: (file not managed or unknown revision control system) +// git-hash: 7ff385fbe34626a3dc7d4b8e42aa321f7a658781 +// +// =========================================================================== + + +#ifndef __RFE_CPLL_RAM_REGS_H +#define __RFE_CPLL_RAM_REGS_H + +//****************************************************************************** +// REGISTER OFFSETS +//****************************************************************************** +// Settling time per channel +#define RFE_CPLL_RAM_O_FREQ_SETTLE 0x00000004U + +// Tone length per channel +#define RFE_CPLL_RAM_O_TONE_LENGTH 0x00000008U + +// RX duration per channel +#define RFE_CPLL_RAM_O_RX_LENGTH 0x0000000CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP0 0x00000E00U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP1 0x00000E02U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP2 0x00000E04U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP3 0x00000E06U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP4 0x00000E08U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP5 0x00000E0AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP6 0x00000E0CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP7 0x00000E0EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP8 0x00000E10U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP9 0x00000E12U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP10 0x00000E14U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP11 0x00000E16U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP12 0x00000E18U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP13 0x00000E1AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP14 0x00000E1CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP15 0x00000E1EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP16 0x00000E20U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP17 0x00000E22U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP18 0x00000E24U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP19 0x00000E26U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP20 0x00000E28U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP21 0x00000E2AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP22 0x00000E2CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP23 0x00000E2EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP25 0x00000E30U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP26 0x00000E32U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP27 0x00000E34U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP28 0x00000E36U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP29 0x00000E38U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP30 0x00000E3AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP31 0x00000E3CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP32 0x00000E3EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP33 0x00000E40U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP34 0x00000E42U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP35 0x00000E44U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP36 0x00000E46U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP37 0x00000E48U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP38 0x00000E4AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP39 0x00000E4CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP40 0x00000E4EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP41 0x00000E50U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP42 0x00000E52U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP43 0x00000E54U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP44 0x00000E56U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP45 0x00000E58U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP46 0x00000E5AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP47 0x00000E5CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP48 0x00000E5EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP49 0x00000E60U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP50 0x00000E62U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP51 0x00000E64U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP52 0x00000E66U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP53 0x00000E68U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP54 0x00000E6AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP55 0x00000E6CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP56 0x00000E6EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP57 0x00000E70U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP58 0x00000E72U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP59 0x00000E74U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP60 0x00000E76U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP61 0x00000E78U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP62 0x00000E7AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP63 0x00000E7CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP65 0x00000E7EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP66 0x00000E80U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP67 0x00000E82U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP68 0x00000E84U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP69 0x00000E86U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP70 0x00000E88U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP71 0x00000E8AU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP72 0x00000E8CU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP73 0x00000E8EU + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP74 0x00000E90U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP75 0x00000E92U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP76 0x00000E94U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP77 0x00000E96U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP78 0x00000E98U + +// Channel in channelmap +#define RFE_CPLL_RAM_O_CHANMAP79 0x00000E9AU + +//****************************************************************************** +// Register: FREQ_SETTLE +//****************************************************************************** +// Field: [15:0] val +// +// Unit is 16 MHz ticks +#define RFE_CPLL_RAM_FREQ_SETTLE_VAL_W 16U +#define RFE_CPLL_RAM_FREQ_SETTLE_VAL_M 0xFFFFU +#define RFE_CPLL_RAM_FREQ_SETTLE_VAL_S 0U + +//****************************************************************************** +// Register: TONE_LENGTH +//****************************************************************************** +// Field: [15:0] val +// +// Unit is 16 MHz ticks +#define RFE_CPLL_RAM_TONE_LENGTH_VAL_W 16U +#define RFE_CPLL_RAM_TONE_LENGTH_VAL_M 0xFFFFU +#define RFE_CPLL_RAM_TONE_LENGTH_VAL_S 0U + +//****************************************************************************** +// Register: RX_LENGTH +//****************************************************************************** +// Field: [15:0] val +// +// Unit is 16 MHz ticks +#define RFE_CPLL_RAM_RX_LENGTH_VAL_W 16U +#define RFE_CPLL_RAM_RX_LENGTH_VAL_M 0xFFFFU +#define RFE_CPLL_RAM_RX_LENGTH_VAL_S 0U + +//****************************************************************************** +// Register: CHANMAP0 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP0_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP0_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP0_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP1 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP1_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP1_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP1_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP2 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP2_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP2_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP2_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP3 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP3_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP3_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP3_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP4 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP4_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP4_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP4_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP5 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP5_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP5_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP5_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP6 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP6_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP6_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP6_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP7 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP7_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP7_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP7_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP8 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP8_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP8_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP8_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP9 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP9_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP9_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP9_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP10 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP10_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP10_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP10_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP11 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP11_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP11_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP11_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP12 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP12_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP12_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP12_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP13 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP13_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP13_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP13_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP14 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP14_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP14_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP14_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP15 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP15_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP15_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP15_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP16 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP16_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP16_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP16_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP17 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP17_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP17_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP17_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP18 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP18_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP18_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP18_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP19 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP19_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP19_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP19_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP20 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP20_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP20_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP20_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP21 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP21_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP21_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP21_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP22 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP22_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP22_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP22_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP23 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP23_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP23_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP23_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP25 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP25_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP25_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP25_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP26 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP26_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP26_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP26_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP27 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP27_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP27_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP27_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP28 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP28_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP28_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP28_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP29 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP29_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP29_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP29_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP30 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP30_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP30_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP30_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP31 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP31_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP31_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP31_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP32 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP32_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP32_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP32_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP33 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP33_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP33_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP33_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP34 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP34_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP34_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP34_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP35 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP35_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP35_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP35_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP36 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP36_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP36_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP36_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP37 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP37_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP37_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP37_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP38 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP38_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP38_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP38_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP39 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP39_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP39_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP39_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP40 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP40_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP40_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP40_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP41 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP41_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP41_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP41_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP42 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP42_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP42_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP42_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP43 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP43_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP43_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP43_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP44 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP44_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP44_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP44_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP45 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP45_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP45_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP45_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP46 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP46_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP46_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP46_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP47 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP47_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP47_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP47_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP48 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP48_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP48_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP48_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP49 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP49_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP49_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP49_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP50 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP50_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP50_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP50_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP51 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP51_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP51_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP51_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP52 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP52_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP52_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP52_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP53 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP53_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP53_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP53_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP54 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP54_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP54_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP54_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP55 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP55_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP55_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP55_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP56 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP56_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP56_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP56_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP57 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP57_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP57_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP57_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP58 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP58_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP58_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP58_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP59 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP59_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP59_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP59_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP60 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP60_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP60_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP60_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP61 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP61_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP61_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP61_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP62 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP62_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP62_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP62_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP63 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP63_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP63_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP63_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP65 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP65_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP65_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP65_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP66 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP66_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP66_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP66_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP67 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP67_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP67_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP67_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP68 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP68_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP68_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP68_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP69 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP69_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP69_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP69_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP70 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP70_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP70_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP70_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP71 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP71_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP71_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP71_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP72 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP72_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP72_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP72_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP73 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP73_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP73_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP73_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP74 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP74_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP74_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP74_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP75 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP75_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP75_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP75_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP76 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP76_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP76_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP76_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP77 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP77_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP77_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP77_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP78 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP78_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP78_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP78_FREQ_S 0U + +//****************************************************************************** +// Register: CHANMAP79 +//****************************************************************************** +// Field: [11:0] freq +// +// Channel frequency in MHz +#define RFE_CPLL_RAM_CHANMAP79_FREQ_W 12U +#define RFE_CPLL_RAM_CHANMAP79_FREQ_M 0x0FFFU +#define RFE_CPLL_RAM_CHANMAP79_FREQ_S 0U + + +#endif // __RFE_CPLL_RAM_REGS_H diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5.h new file mode 100644 index 00000000..7c3b0850 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:14 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ble5 --fwdesc CC2340R5 LRF firmware for mce, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/mce_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/lrf_mce_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/mce_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_MCE_BINARY_BLE5_C +#define _LRF_MCE_BINARY_BLE5_C + + +#include + +/* Length of binary image. */ +#define LRF_MCE_BINARY_BLE5_LENGTH 512 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_MCE_binary_ble5[LRF_MCE_BINARY_BLE5_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5_cc23x0r5.c new file mode 100644 index 00000000..e5debfd4 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble5_cc23x0r5.c @@ -0,0 +1,78 @@ +// This code snippet was auto-generated on Thu May 23 12:09:14 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ble5 --fwdesc CC2340R5 LRF firmware for mce, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/mce_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/lrf_mce_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble5/mce_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_mce_binary_ble5.h" + +const uint32_t LRF_MCE_binary_ble5[LRF_MCE_BINARY_BLE5_LENGTH] = { + 0x000001FF, 0x7226604C, 0x7379722A, 0x72047279, 0x67D57205, 0xB025C030, 0xFFC09000, 0xB0049020, + 0x73077306, 0x7000A004, 0x7312720E, 0x7313720F, 0x73147210, 0xA4D5A3AE, 0x15EE7000, 0x0FFF01FF, + 0x13F517FF, 0x0F000240, 0x0F0F0F0F, 0x000F0F00, 0x0F0F0F0F, 0x807A000F, 0x807E807A, 0x0FF00F30, + 0x00030000, 0x00100013, 0x00220021, 0x00310032, 0x00400043, 0x00530050, 0x00610062, 0x00720071, + 0x00510050, 0x004F004E, 0x00C300CC, 0x0033003C, 0x00010000, 0x00030002, 0x00000001, 0x6412721B, + 0xB1B26401, 0x7100B0E0, 0x721BA0E0, 0x8172B120, 0x39421020, 0x06F03122, 0x16300020, 0x14011101, + 0x606F6C01, 0x6093607A, 0x606F60ED, 0x6093607A, 0x606F6133, 0x61E5607A, 0x606F6260, 0x61E5607A, + 0x60726260, 0x60731222, 0x64121212, 0x81B16401, 0x91B20012, 0x6050B080, 0x6F136092, 0x16116E23, + 0x687B1612, 0x7A0394DB, 0x81809493, 0x44721E00, 0x9300C030, 0x9320C1F0, 0x1820C522, 0x12034091, + 0x16126E23, 0xB52C688E, 0x72796072, 0xC200B021, 0xB2A09200, 0x9210C100, 0xB130B12E, 0xB121B123, + 0x7100B0EE, 0xA0EEB12E, 0x89898977, 0x22D18181, 0x899740A9, 0xC0F389A9, 0xB02267DA, 0x7231B002, + 0x818181A0, 0x40B622F1, 0x40B62207, 0x081013F1, 0xB5209530, 0xB003B023, 0xB0F0B130, 0xB1307100, + 0x31808180, 0x93103980, 0xB1307100, 0x95379313, 0x67F8C030, 0xB1307100, 0xE0409539, 0x98849872, + 0x710067F8, 0xA0F0B130, 0xB523A520, 0x7100B0E3, 0xB123A0E3, 0x9790C030, 0x97B0C060, 0xB0E1B121, + 0xB1217100, 0x7279A0E1, 0xA00367D5, 0x7306A002, 0x73797307, 0x72267279, 0x9020C7C0, 0x656A6072, + 0x65C865C1, 0xB136B0F6, 0x67F8C050, 0x80B07100, 0x40FB2260, 0x67F8C060, 0xC07060F1, 0xB89067F8, + 0x88C588B4, 0x9874E080, 0x67F89885, 0xA0F6B136, 0x737BA790, 0x7210B790, 0x720F7314, 0x00007313, + 0xB0990000, 0xA280B261, 0x891FA282, 0x4117221F, 0xB2A0B282, 0x3D8F316F, 0xB8A791CF, 0x92C088D0, + 0xC3016785, 0x22F36795, 0x67A44524, 0xA0E095EF, 0x97B3C0B3, 0x72269127, 0xB3AE7100, 0xA4D5B087, + 0x678CC243, 0x44ED2200, 0x656A6072, 0x65C279D0, 0xC5F0A3E6, 0xB3E66938, 0xB0E565C8, 0x7100B125, + 0x225080A0, 0xA79045D6, 0xB790737B, 0x73147210, 0x7313720F, 0xB099B083, 0xA280B261, 0x8910A282, + 0x41512210, 0xB2A0B282, 0x3D803160, 0xB8A791C0, 0x92C088D0, 0x6785A0E5, 0xC261B263, 0x22F36795, + 0x67A44560, 0xB3AEA0E0, 0x7226B087, 0xC2A3A4D5, 0x2200678C, 0x60724533, 0xA214B021, 0x84D3B215, + 0x0443C1F4, 0x12021613, 0x22531204, 0x8970417D, 0x880297F0, 0x89901A82, 0x880497F0, 0x89801A84, + 0x880097F0, 0x14021A80, 0x97F089A0, 0x1A808800, 0x83A01404, 0x419522C0, 0x39101020, 0x10401402, + 0x14043910, 0x459C2253, 0x31143112, 0x2253619C, 0x3112459A, 0x619C3114, 0x31243122, 0x39823182, + 0x00423184, 0x897095F2, 0x898094E0, 0x899094F0, 0x89A09500, 0x725D9510, 0x22308270, 0xB0E545B2, + 0xB1257100, 0x61AAA0E5, 0x9200C100, 0x979079B0, 0x120A13E7, 0x26CA26AA, 0xB024B022, 0xB002B025, + 0xB005B004, 0x79C07000, 0x90409060, 0x907079E0, 0x70009050, 0xB021B07A, 0xB4D5B098, 0xA0E0A0E1, + 0xB0F5B135, 0x69D1C400, 0xC090B260, 0x700067F8, 0x88B3B890, 0x825088C4, 0x41E43980, 0x31331630, + 0x31343C03, 0x95833C04, 0xB0619594, 0xB021613C, 0x9200C200, 0xC100B2A0, 0x73129210, 0xC0007313, + 0x72799210, 0x89778180, 0x22D08989, 0x899741F7, 0x318089A9, 0x93103980, 0x953081A0, 0xC42DC2EC, + 0xC008C07E, 0xB0EEB12E, 0xB12E7100, 0x67DAA0EE, 0xB0F1B524, 0xB022B002, 0xB023B003, 0x7100B131, + 0xA524A0F1, 0xB123B520, 0xB130B0E3, 0x1074B0F0, 0x104FC0F0, 0x39146651, 0x10946A17, 0x104FC0F0, + 0x39146651, 0x84A46A1D, 0x104FC040, 0x39146651, 0x84A46A23, 0x46352204, 0x665181EF, 0x22108230, + 0x622A4230, 0xC00FC030, 0x6A316651, 0xC46D6242, 0x81EFC01E, 0x82306651, 0x423D2210, 0xC0306235, + 0x6651C00F, 0x62426A3E, 0xC030A0F1, 0xC0409790, 0xB12197B0, 0x7100B0E1, 0xA0E1B121, 0xA0037279, + 0x7226A002, 0x061F6072, 0x148F313F, 0x6FF214CF, 0x39481028, 0x14D20632, 0x71006F23, 0x931EB130, + 0x70009533, 0x93E07AC0, 0x22308270, 0xB0E5466B, 0xB1257100, 0xB021A0E5, 0xB0056262, 0xB004B025, + 0xB002B024, 0x79C0B022, 0x90609040, 0xC42DC2EC, 0x67ACC008, 0x92001200, 0x905079F0, 0x7A909070, + 0xB13493D0, 0x7100B0F4, 0xB081A0F4, 0x9420C0D0, 0xB07BB05B, 0xB07DB05D, 0x96207CA0, 0xC008B260, + 0xC2ECC21D, 0xC0308971, 0x39116696, 0x62A86A92, 0x061F101F, 0x148F313F, 0x6FF214CF, 0x39481028, + 0x31120632, 0x6F2314D2, 0x16129663, 0x96736F23, 0x7000B630, 0xC106C0F5, 0xC0C9C018, 0x7A17C20D, + 0x7AD07A2F, 0xB14693E0, 0x7100B106, 0xB146B082, 0xB134A106, 0x7100B0F4, 0xB051B134, 0xC0F0B071, + 0xA0549420, 0x7100B261, 0x7100B134, 0x6731B134, 0x4ACB1C98, 0x39208650, 0x1CD891D0, 0x161842CF, + 0x967F46C5, 0x12089667, 0x1EB8B630, 0x865042DA, 0x91D03920, 0x62D21618, 0xC0F08212, 0x71009210, + 0x81E0B134, 0x1C018971, 0x81E04727, 0x1C018981, 0xC2024727, 0xB0839212, 0xB2A0B099, 0x31608910, + 0x91C03D80, 0x88D0B8A7, 0x865092C0, 0x43122220, 0x7100B280, 0x676B7AB0, 0xB1347100, 0xB1347100, + 0x96638823, 0x96738833, 0x1C98B630, 0x86504B08, 0x91D03920, 0x81911618, 0x42FA1E01, 0x1C811621, + 0x67784EFA, 0x63257226, 0x7100A280, 0x676B7AA0, 0x1C986731, 0x86504B1C, 0x91D03920, 0x81911618, + 0x43161E01, 0x1C811631, 0x67784F16, 0xA0F47226, 0x92126072, 0xC0A07226, 0x730767F8, 0x7312B021, + 0x73147313, 0x7100627A, 0x7100B134, 0x8823B134, 0x10353983, 0x31848834, 0x10463984, 0xB1347100, + 0xB1347100, 0x31808820, 0x14043980, 0x39808820, 0x88301406, 0x39803180, 0x88301403, 0x14053980, + 0xB1347100, 0xB1347100, 0x39808820, 0x14041403, 0x31808830, 0x14053980, 0x39331406, 0x39353934, + 0x31853936, 0x31861453, 0x96631464, 0xB6309674, 0xB1347100, 0xB1347100, 0xB1347000, 0xC008B07D, + 0x710093D0, 0xB081B134, 0xC0F97100, 0x7100B134, 0x7000B134, 0x967FB263, 0x12089667, 0x1618B630, + 0x43841C98, 0x39208650, 0x637C91D0, 0x80A07000, 0x44532200, 0x1E038193, 0x70004385, 0x912797B3, + 0x80A07100, 0x44532200, 0x6401A3AE, 0x87DB7000, 0x18B087C0, 0x84B83123, 0x18031883, 0x97B31813, + 0xB121A790, 0xB0E0B790, 0x7000B0E1, 0x43AA1E08, 0xB6147100, 0x97B8B121, 0x70007100, 0xC00DC2EC, + 0xC070C008, 0xC3EB897E, 0x061F10EF, 0x148F313F, 0x6FF214CF, 0x39481028, 0x1E020632, 0xCCCA47BF, + 0x1E1263C8, 0xCC3A47C3, 0x1E2263C8, 0xC3CA47C7, 0xC33A63C8, 0x43CC2200, 0x63D110A6, 0x318A6FB7, + 0x6E7A006A, 0x391E161B, 0xB0746BB2, 0x85207000, 0x0410C021, 0x70009520, 0xB0E1B260, 0x39818491, + 0x10103141, 0x14103111, 0x97B043E7, 0xB790B121, 0xB2617100, 0xB1217279, 0x31818491, 0x10103971, + 0x14103111, 0x97B043F6, 0x7100B790, 0xB1217279, 0x7000A0E1, 0x88509860, 0x47F92200, 0x7000B840 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs.h new file mode 100644 index 00000000..029b072b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:38 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ble_cs --fwdesc CC2340R5 LRF firmware for mce, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/mce_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/lrf_mce_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/mce_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_MCE_BINARY_BLE_CS_C +#define _LRF_MCE_BINARY_BLE_CS_C + + +#include + +/* Length of binary image. */ +#define LRF_MCE_BINARY_BLE_CS_LENGTH 591 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_MCE_binary_ble_cs[LRF_MCE_BINARY_BLE_CS_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs_cc23x0r5.c new file mode 100644 index 00000000..152a454f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ble_cs_cc23x0r5.c @@ -0,0 +1,88 @@ +// This code snippet was auto-generated on Thu May 23 12:09:38 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ble_cs --fwdesc CC2340R5 LRF firmware for mce, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/mce_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/lrf_mce_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ble_cs/mce_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_mce_binary_ble_cs.h" + +const uint32_t LRF_MCE_binary_ble_cs[LRF_MCE_BINARY_BLE_CS_LENGTH] = { + 0x0000024E, 0x00016051, 0x17FF01FF, 0x100400AA, 0x03C00180, 0x000B01E0, 0x08400FF0, 0x00000000, + 0x000C0F00, 0x00000399, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x721B0000, 0x722467A1, 0x8250B1B2, 0xB0E09570, 0x721B7100, 0xB120A0E0, 0x81726669, + 0x11011632, 0x6C011421, 0x6073611D, 0x60756075, 0x60A46090, 0x60C460C4, 0x60F060E1, 0xB010606D, + 0x70006056, 0x6007B010, 0x64707000, 0x66A8611D, 0x652179A1, 0xC020652D, 0x66A49260, 0x679A7A30, + 0x97B07980, 0x6629664F, 0x7B716577, 0x45191E01, 0xA79066CA, 0x66AB1898, 0x1E1B79EB, 0x6670408F, + 0x6114B240, 0x79A166A8, 0x14017A20, 0x67776521, 0x7A318670, 0x97B01410, 0x9260C020, 0x6719664F, + 0x22E18351, 0xC64040A3, 0x611468A2, 0x79A166A8, 0x652D6521, 0x9260C010, 0x97B07880, 0x86706777, + 0x14107A31, 0xC02097B0, 0x66A89260, 0x6719664F, 0xC03066A4, 0x79909260, 0x662997B0, 0x7B716577, + 0x45191E01, 0x189866CA, 0x611466AB, 0x797066A4, 0x664F97B0, 0x65776629, 0x1E217B71, 0x66CA4119, + 0x9260C040, 0xC601679B, 0x652D6521, 0x10981889, 0x79EB66AB, 0x40E01E1B, 0x7930B521, 0x14107881, + 0xB240679A, 0x66A86111, 0x97B07A20, 0x6719664F, 0x679A7A30, 0x9260C040, 0x679ACF00, 0x6521C001, + 0x61116777, 0x797066A4, 0x664F97B0, 0x65776629, 0x1E217B71, 0x66A84119, 0x9260C010, 0x671966CA, + 0x7A30660B, 0xC040679A, 0xCF009260, 0xC001679A, 0x67776521, 0x9260C030, 0x97B07880, 0x1889652D, + 0x66AB1098, 0xC0606111, 0x61169260, 0x9260C050, 0x9000C010, 0xC050611D, 0x12229260, 0x1212611E, + 0x91B267A1, 0xC0106055, 0x78709260, 0xC9011810, 0x679A1810, 0x9260C020, 0x97B0C900, 0x66B87000, + 0xB797B79C, 0xB5207252, 0x73537231, 0xA790679B, 0xC000737B, 0x26202630, 0x00018001, 0x90019020, + 0xB0F0B130, 0xB1307100, 0x8351C070, 0x414722F1, 0x93102640, 0x71009535, 0xC0F3B130, 0x95329313, + 0xB1307100, 0x71009534, 0xB130A79C, 0x9310C030, 0x71009536, 0x1090B130, 0xC0F34164, 0x6D749313, + 0x95346D74, 0x71001617, 0x695DB130, 0xB0E2A0F0, 0xC0D0B122, 0x22F18351, 0xC0A0416C, 0xB1227100, + 0xA0E2696C, 0xB13087D9, 0xB521A0F0, 0xB790A520, 0xC0907000, 0x66F09260, 0xA394C07F, 0xB100B140, + 0x1E0079E0, 0xB1254583, 0xC00EB0E5, 0x1E007A00, 0xB09D4189, 0x818078FE, 0x418F1E10, 0xB0E1B121, + 0xB0E06196, 0xB135B136, 0xB394B79D, 0xA790B054, 0x80A07100, 0x041080E1, 0xB125A0E5, 0x41A02250, + 0x619666F0, 0x87D8B8AA, 0x926F961E, 0x220080C0, 0xA10041C5, 0xA790B140, 0x97B07A20, 0xB121B790, + 0xA054A79D, 0x8170B890, 0x45B81E90, 0x1E007A00, 0x700045B8, 0xB0F5B0F6, 0x80B07100, 0x45C02260, + 0x45C72250, 0x1E108180, 0xC0114177, 0xC02161C9, 0xC00161C9, 0xC372B2A2, 0x6E2126C2, 0x31838943, + 0x00438964, 0x6E231612, 0x7312720E, 0x7313720F, 0x45FD1E01, 0x1E007A00, 0x311041FD, 0x81721A10, + 0x45E11E92, 0xC4921A10, 0xB13326C2, 0x7100B0F3, 0xB13381E1, 0x9213C0F3, 0x81E17100, 0x6E21B133, + 0x69EA1612, 0x8172A0F3, 0x45FC1E92, 0xB0F1B131, 0x7100C040, 0x69F7B131, 0x7000A0F1, 0x7261B083, + 0xA4D5B3AE, 0xA05AB07A, 0xB021B087, 0x7312720E, 0x7313720F, 0x73147210, 0x7A007000, 0x461E1E00, + 0x80B0C011, 0x42132250, 0xC372C001, 0x6E2126C2, 0x31838943, 0x00438964, 0x6E231612, 0x62277313, + 0x26C2C492, 0x31107A00, 0x14021A10, 0x6E2181E1, 0x7261B083, 0xC0317000, 0xC1009211, 0xB0219200, + 0x89828971, 0x97F294F2, 0x94E1880E, 0x880097F1, 0x1A8E140E, 0x83A01A8E, 0x463E22C0, 0x6242312E, + 0x311010E0, 0x391E140E, 0x398E318E, 0xC00095FE, 0x26A02640, 0x90702620, 0xB4D5B098, 0xB797B79D, + 0x82707000, 0x424F2230, 0xC000B125, 0x26502640, 0x79E1B42A, 0x465B1E01, 0x2620A42A, 0x00018001, + 0x90019020, 0x93B079C0, 0x78317820, 0x90519040, 0x90719060, 0x72797000, 0x737B727C, 0xB790B121, + 0x7000B793, 0x8351C180, 0x427522F1, 0x7851C300, 0xB0F1B131, 0x93607100, 0xB13193B1, 0x7100C070, + 0x6A7DB131, 0xB122A0F1, 0xC7F0B0E2, 0x7100C004, 0xB8A4B122, 0x318188D1, 0x14143D81, 0xA0E26A85, + 0x1404C080, 0x12203D44, 0x31151045, 0x6A921454, 0x1414C081, 0x7A113D44, 0xC3611814, 0x6E1426C1, + 0xC0C091C4, 0x79C09360, 0x700093B0, 0x93807900, 0x7000B060, 0xB0607238, 0xC3917000, 0x6E1826C1, + 0x88D21611, 0x16116E12, 0x6E1288E2, 0x88F21611, 0x70006E12, 0x89A48992, 0x22027845, 0x391542BE, + 0x22F47846, 0x391646C2, 0x31197A09, 0x42C91E09, 0xC2971A19, 0x700026C7, 0x26C1C3D1, 0x313088B0, + 0x6E103D30, 0x88C01611, 0x3D303130, 0x00006E10, 0x1E0079E0, 0x84A046EF, 0x46EF2280, 0x7BD31610, + 0x1E107BE5, 0x1E2042E9, 0x78C246EF, 0x78D41423, 0x3D131445, 0xC0C63D15, 0x6E6326C6, 0x6E651616, + 0x700094A0, 0x8171C600, 0x46F51E51, 0x78913110, 0xB06193E1, 0xB8906AF8, 0x313088B0, 0x95803D30, + 0x313088C0, 0x95903D30, 0x93E078A0, 0x7000B061, 0x78D378C2, 0x228084A0, 0x7A524313, 0x89607A63, + 0x1C10C2D1, 0x7A724313, 0x95827A83, 0x78B09593, 0xB06193E0, 0x67067000, 0x791A6763, 0x817179FB, + 0x47221E51, 0x4324221B, 0x7267161A, 0x26CCC3FC, 0x7100B0E1, 0xC080B121, 0x97BD9260, 0x1A1A6736, + 0x71004726, 0xA0E1737B, 0x723FB121, 0x7000A893, 0x120F120E, 0xB3F0B067, 0xB0EBB12B, 0x71001040, + 0x6B3DB12B, 0xB8937220, 0x88CF88BE, 0x3D3E313E, 0x3D3F313F, 0x475B1E23, 0x18701040, 0x7100B12B, + 0x6B4DB12B, 0x88B5B893, 0x313588C6, 0x31363D35, 0x145E3D36, 0x3D1E146F, 0xA3F03D1F, 0xA0EBB067, + 0x161C6ECE, 0x161C6ECF, 0x794D7000, 0x141D79B1, 0x8492967D, 0x10210632, 0x26123122, 0x849493F2, + 0x84973984, 0x39873187, 0x84933947, 0x06333923, 0x679B7000, 0x79B17940, 0x79121410, 0x1E121003, + 0x638A4780, 0x47841E22, 0x638A3110, 0x47891E32, 0x14303110, 0x3120638A, 0x817179F4, 0x22211A21, + 0x22144392, 0x63944396, 0x43962204, 0xC0031430, 0xB5219673, 0x7000679A, 0xB0E197B0, 0x737B7100, + 0xA0E1B121, 0x720E7000, 0x720F7312, 0x72107313, 0xA3AE7314, 0x7379A4D5, 0x72047279, 0x72527205, + 0xB025C030, 0xFFC09000, 0xB0049020, 0x73077306, 0x7000A004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6051A010, 0x10810003, 0x01FF0008, 0x640A17FF, 0x6072A010, 0x8191721C, 0x40171E31, + 0x40131E21, 0x64346426, 0x641A7000, 0x64436434, 0x641A7000, 0x70006443, 0x26C1C1D1, 0x26C2C312, + 0x6D13C030, 0x6E236D13, 0x16121611, 0x7000681F, 0x26C2C112, 0xB12FC0B0, 0x7228B0EF, 0xB12F7100, + 0x6E218291, 0x682B1612, 0x7000A0EF, 0x26C2C1D2, 0xC1301A12, 0xB0EFB12F, 0x16127228, 0xB12F7100, + 0x6E218291, 0xA0EF683A, 0xC0037000, 0x26C2C312, 0xB0EFC1F0, 0x6D216D21, 0x71006E23, 0x9281B12F, + 0x68481612, 0xC372A0EF, 0x1A1326C2, 0x70006E23, 0xA0106459, 0x7238606F, 0x723EB060, 0x72597258, + 0x2640C000, 0x26202650, 0x00018001, 0x90019020, 0x93907820, 0x93B07830, 0x78617850, 0x90519040, + 0x90719060, 0xC00A818B, 0xB0EDB12D, 0xB12D7100, 0x7841A0ED, 0xB06793F1, 0xB12BB3F0, 0xC820B0EB, + 0xB12B7100, 0xA0EB687E, 0x88B0B893, 0xA3F088C1, 0x3130B067, 0x31313D30, 0xB12F3D31, 0x9280B0EF, + 0xB12F7100, 0x71009281, 0xA0EFB12F, 0x161A7224, 0x40721E1A, 0x1E0B1A1B, 0x70004471 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common.h new file mode 100644 index 00000000..ac5a7aa5 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:08:43 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname common --fwdesc CC2340R5 LRF firmware for mce, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/mce_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/lrf_mce_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/mce_common_ram.bin +// Binary source last modified: 23-May-2024 12:08 + + +#ifndef _LRF_MCE_BINARY_COMMON_C +#define _LRF_MCE_BINARY_COMMON_C + + +#include + +/* Length of binary image. */ +#define LRF_MCE_BINARY_COMMON_LENGTH 2 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_MCE_binary_common[LRF_MCE_BINARY_COMMON_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common_cc23x0r5.c new file mode 100644 index 00000000..9d54f330 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_common_cc23x0r5.c @@ -0,0 +1,15 @@ +// This code snippet was auto-generated on Thu May 23 12:08:43 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname common --fwdesc CC2340R5 LRF firmware for mce, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/mce_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/lrf_mce_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/common/mce_common_ram.bin +// Binary source last modified: 23-May-2024 12:08 + + +#include "lrf_mce_binary_common.h" + +const uint32_t LRF_MCE_binary_common[LRF_MCE_BINARY_COMMON_LENGTH] = { + 0x00000000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk.h new file mode 100644 index 00000000..aaa69964 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:18 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname genfsk --fwdesc CC2340R5 LRF firmware for mce, mode genfsk /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/mce_genfsk_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/lrf_mce_binary_genfsk.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/mce_genfsk_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_MCE_BINARY_GENFSK_C +#define _LRF_MCE_BINARY_GENFSK_C + + +#include + +/* Length of binary image. */ +#define LRF_MCE_BINARY_GENFSK_LENGTH 495 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_MCE_binary_genfsk[LRF_MCE_BINARY_GENFSK_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk_cc23x0r5.c new file mode 100644 index 00000000..561111b6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_genfsk_cc23x0r5.c @@ -0,0 +1,76 @@ +// This code snippet was auto-generated on Thu May 23 12:09:18 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname genfsk --fwdesc CC2340R5 LRF firmware for mce, mode genfsk /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/mce_genfsk_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/lrf_mce_binary_genfsk.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/genfsk/mce_genfsk_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_mce_binary_genfsk.h" + +const uint32_t LRF_MCE_binary_genfsk[LRF_MCE_BINARY_GENFSK_LENGTH] = { + 0x000001EE, 0x7226604F, 0x7379722A, 0x72047279, 0x67687205, 0xB025C030, 0xFFC09000, 0xB0049020, + 0x73077306, 0x7000A004, 0x7312720E, 0x7313720F, 0x73147210, 0xA4D5A3AE, 0x03FF7000, 0x300517F7, + 0x8080FF00, 0x17D020EE, 0x17E017C0, 0x32211300, 0x71625043, 0x31221003, 0x72615340, 0x00100001, + 0x10000100, 0x00200002, 0x20000200, 0x00400004, 0x40000400, 0x00800008, 0x80000800, 0x00030001, + 0x00180020, 0x000A0020, 0x00110029, 0x00180029, 0x00030032, 0x00110032, 0x000A003B, 0x0000003B, + 0x721B0000, 0x64016412, 0xB0E0B1B2, 0xA0E07100, 0x721BB120, 0x10208172, 0x31323942, 0x002006F0, + 0x11011630, 0x6C011401, 0x60826082, 0x63306146, 0x60826082, 0x60826082, 0x60826082, 0x62C860E3, + 0x60826082, 0x60826082, 0x60826082, 0x60826082, 0x60826082, 0x60826082, 0x64121212, 0x81B16401, + 0x91B20012, 0x6053B080, 0x7279607A, 0x818181A0, 0x89848972, 0x408C22D1, 0x89A48992, 0x409222F1, + 0x40922202, 0x081013F1, 0x84D09530, 0x0401C1F1, 0xC0F31611, 0xC200C0F5, 0x40B21C01, 0x1C10C100, + 0x4CAA40A8, 0x18031013, 0x1A131830, 0x39121A10, 0x60B268A5, 0x60B213F3, 0x101513F3, 0x1850C100, + 0x1A101A15, 0x68B03914, 0x7100B0EE, 0xA0EEB12E, 0xB52067B5, 0xB023B003, 0xB022B002, 0xB0F07231, + 0x7100B130, 0x8180B130, 0x39803180, 0x71009310, 0x8180B130, 0x44C522E0, 0x1C0313F0, 0x931340D1, + 0x71009532, 0x9315B130, 0x70009534, 0xC030A0F1, 0xC0209790, 0xB12197B0, 0x7100B0E1, 0xA0E1B121, + 0xA0037279, 0xA002722A, 0x72797000, 0x73137312, 0x67D5C030, 0xC200B021, 0xB2A09200, 0x9210C000, + 0xC247C2C6, 0xC009C008, 0xC00BC00A, 0xC00DC00C, 0xC10E7A1F, 0x652A6483, 0x10ACC009, 0x10F010BD, + 0x1E003980, 0x82304110, 0x41062210, 0x610981E0, 0x061010F0, 0x6517391F, 0x65406530, 0x1CE91619, + 0x60FA4501, 0x65406530, 0x1CE91619, 0x64D44510, 0x1081607A, 0x6F121471, 0x411D2200, 0x10233982, + 0x311A0613, 0x1023003A, 0x06133913, 0x003B311B, 0x39481028, 0x700006F8, 0x651781E0, 0x1CE91619, + 0x7000452A, 0x14921062, 0x10C16F23, 0x41380431, 0x6139C010, 0x3110C000, 0x043110D1, 0x1610413F, + 0x7000613F, 0x7100C011, 0x93119530, 0x7000B130, 0x73137312, 0x67D5C040, 0xC200B021, 0xB2A09200, + 0x9210C100, 0x71006483, 0xB0F0B130, 0xB523A520, 0xB0E3B123, 0xA0E37100, 0x607A64D4, 0x9211C201, + 0xB025B005, 0xB024B004, 0xB022B002, 0x838384C2, 0x84609382, 0x0420C3F2, 0xC1F484D3, 0xC1F20443, + 0x31621832, 0x31511021, 0x00200012, 0x10309460, 0x39301610, 0x417B2210, 0x31501220, 0x12021003, + 0x22731204, 0x8970418A, 0x880297F0, 0x89901A82, 0x880497F0, 0x618C1A84, 0x41972263, 0x97F08980, + 0x1A808800, 0x89A01402, 0x880097F0, 0x14041A80, 0x898061A5, 0x3181CFF1, 0x97F00410, 0x1A428802, + 0xCFF189A0, 0x04103181, 0x880497F0, 0x31521A44, 0x39633154, 0x16130633, 0x38343832, 0x39823182, + 0x00423184, 0x897095F2, 0x898094E0, 0x899094F0, 0x89A09500, 0x725D9510, 0x93E08680, 0x904079B0, + 0x79C09060, 0x90709050, 0xA0E5B125, 0xC00BC00C, 0x93E08680, 0x720E7279, 0x7210720F, 0xB0F1B131, + 0xB0817100, 0xA05CA0F1, 0xB021B07C, 0xB098B07A, 0xA528A051, 0xC180A527, 0x398184A1, 0x16113961, + 0x69DF3010, 0x8690B260, 0x668693E0, 0xB125B0E5, 0xB1217279, 0xA794B794, 0x97907A00, 0xC070C068, + 0xC0EE97B0, 0x7100C01F, 0x80A0B790, 0x47A42250, 0xA103A100, 0x80C9A0E5, 0x460C2209, 0x460C2239, + 0xB100A790, 0xB0E5B103, 0x22F184B1, 0xB08441F1, 0x80C0B143, 0x46062230, 0x61F1B096, 0x7100A0E2, + 0x97B0C020, 0x7100B121, 0x97BEB082, 0x88F1B8A1, 0x3D813181, 0x220985F0, 0x3D80461D, 0x3180621F, + 0x83A23D80, 0x422322C2, 0x18013910, 0x220995D1, 0xB8AA422C, 0x88F188D0, 0x6230A1B2, 0x88D0B8AB, + 0xB1B288F1, 0x1C811801, 0x14184E3B, 0x623C4A39, 0x423C1C01, 0xB5274E3B, 0xB528623C, 0xB121B071, + 0xB0517100, 0xB12197BF, 0xB05C7100, 0xB05BB07C, 0x13F0B07B, 0xA0E197B0, 0x22C084A0, 0xC0004672, + 0x81719370, 0x42532281, 0xB0F5C1D0, 0xB0F6B135, 0xB7E0B136, 0xB7947100, 0x9791C281, 0x80B09370, + 0x46652250, 0x67D5C050, 0x6A63C800, 0x821061C6, 0x9211C0F1, 0x84D281E3, 0x0421C1F1, 0x1821C102, + 0x92114A71, 0x921081E3, 0x22E084B0, 0x82504278, 0x41C62220, 0xB2A0B261, 0xB099B083, 0x31608910, + 0x91C03D80, 0x88D0B8A7, 0xA0F592C0, 0x7000A0F6, 0xB121B126, 0xB143B140, 0xB122B125, 0x720F720E, + 0xB1007210, 0xB0E1B103, 0x22F084B0, 0xCAA042AB, 0xCAA13180, 0x84B30001, 0x39833183, 0x31803980, + 0xF0710030, 0x84B30410, 0x06F33983, 0x1834C1F4, 0x00403134, 0x0010C031, 0x84A2B096, 0x42AF22D2, + 0x7000B0E2, 0x81B0B8A7, 0x392488D4, 0x00043184, 0xC06091B4, 0x722667D5, 0x72797379, 0xA0056768, + 0xA002B025, 0xA004B022, 0x7204B024, 0x72057306, 0x607A7307, 0x67D5C070, 0x22308270, 0xB0E546D2, + 0xB1257100, 0x62C8A0E5, 0x9200C100, 0x655CB3AE, 0xC000A05C, 0xB05D9200, 0xA0E1B07D, 0xB0F4B134, + 0x9790C070, 0x97B0C070, 0x7100B134, 0x7100B134, 0xB134A0F4, 0xC1071206, 0xC00D7A38, 0x31131063, + 0x676D1483, 0x1C671616, 0xC02F46EC, 0x7A397A28, 0xB05D120E, 0x1206B07D, 0x679C1060, 0x31131013, + 0x677A1493, 0x31131063, 0x676D1483, 0x1C671616, 0x0A1E46FA, 0x430D1E1E, 0x7A397A28, 0x7A38630F, + 0x162F7A29, 0x1E008190, 0x393042F9, 0x1CF01620, 0x4EF94318, 0x26D0C000, 0x90507204, 0x10601206, + 0x1013679C, 0x14933113, 0x1616677A, 0x471D1C67, 0x72046794, 0x73067205, 0xA0047307, 0xC7C0A002, + 0x607A9020, 0x22308270, 0xB0E54738, 0xB1257100, 0x6330A0E5, 0x9200C100, 0xC080B3AE, 0x655C67D5, + 0x93E08690, 0x220080A0, 0x81944453, 0x43401E04, 0xB0E697B4, 0x87C1B126, 0x161187B0, 0x87B11810, + 0x1AF01AF1, 0x87B14F57, 0x4F591690, 0x4F5C1E00, 0x97B16365, 0x16717100, 0xB12697B1, 0xA260A261, + 0xB0877100, 0x1401C0A0, 0xB12697B1, 0xB1267100, 0x62B0A0E6, 0xC0218520, 0x95200410, 0xB1217000, + 0x7100B0E1, 0xA0E1B121, 0x88328821, 0x6E316E31, 0x6E321613, 0x70006E32, 0x6D316D31, 0x31841014, + 0x39813984, 0x6D321613, 0x10256D32, 0x39823185, 0x14543182, 0x14219664, 0xB6309671, 0x4B921EFD, + 0x39208650, 0x91D00610, 0x7000161D, 0xB630C0F0, 0x86510A11, 0x91D10611, 0x70006B95, 0x06311001, + 0x39203121, 0x12F10010, 0x70001801, 0xB890B125, 0x88C488B3, 0x39808250, 0x43B41E00, 0x31331630, + 0x31343C03, 0x95833C04, 0xB0619594, 0xB26061E6, 0x8491B0E1, 0x31413981, 0x31111010, 0x1E001410, + 0x97B043C3, 0xB790B121, 0xB2617100, 0xB1217279, 0x31818491, 0x10103971, 0x14103111, 0x43D31E00, + 0xB79097B0, 0x72797100, 0xA0E1B121, 0x98607000, 0x22008850, 0xB84047D6, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee.h new file mode 100644 index 00000000..dcd8ed8a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:06 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ieee --fwdesc CC2340R5 LRF firmware for mce, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/mce_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/lrf_mce_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/mce_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_MCE_BINARY_IEEE_C +#define _LRF_MCE_BINARY_IEEE_C + + +#include + +/* Length of binary image. */ +#define LRF_MCE_BINARY_IEEE_LENGTH 219 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_MCE_binary_ieee[LRF_MCE_BINARY_IEEE_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee_cc23x0r5.c new file mode 100644 index 00000000..cccc3b6c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_mce_binary_ieee_cc23x0r5.c @@ -0,0 +1,42 @@ +// This code snippet was auto-generated on Thu May 23 12:09:06 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu mce --fwname ieee --fwdesc CC2340R5 LRF firmware for mce, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/mce_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/lrf_mce_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/mce/ieee/mce_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_mce_binary_ieee.h" + +const uint32_t LRF_MCE_binary_ieee[LRF_MCE_BINARY_IEEE_LENGTH] = { + 0x000000DA, 0x7226603F, 0x7379722A, 0x72047279, 0x65857205, 0xB025C030, 0xFFC09000, 0xB0049020, + 0x73077306, 0x7000A004, 0x7312720E, 0x7313720F, 0x73147210, 0xA4D5A3AE, 0xF7037000, 0x70399B3A, + 0x039BB3AF, 0x39B33AF7, 0x9B3AAF70, 0xB3AFF703, 0x3AF77039, 0xAF70039B, 0x08FCB9B3, 0x8FC664C5, + 0xFC644C50, 0xC64CC508, 0x64C5508F, 0x4C5008FC, 0xC5088FC6, 0x508FFC64, 0x03F8C64C, 0x01F40FEF, + 0x721B7F7F, 0x64016412, 0xB0E0B1B2, 0xA0E07100, 0xB120721B, 0x10208172, 0x06703952, 0x16300020, + 0x14011101, 0x60616C01, 0x606B6061, 0x60D560A5, 0x60616061, 0x60616061, 0x606B6061, 0x60D560A5, + 0x60616061, 0x60646061, 0x60651222, 0x64121212, 0x001281B1, 0xB08091B2, 0x72796043, 0xB001B021, + 0x9200C0F0, 0xC002C010, 0x658A91D2, 0xC0706872, 0x658A9200, 0x91D08970, 0xB205658A, 0xC130B2A0, + 0xB1239210, 0xB0EEB12E, 0xB12E7100, 0x658EA0EE, 0xB002B022, 0xB023B523, 0xB0E3B003, 0xB1237100, + 0x1000A0E3, 0x9790C030, 0x97B0C020, 0x7100B0E1, 0xA0E1B121, 0xA0037279, 0x6585A002, 0x73077306, + 0x72797379, 0x722A7226, 0x9020C7C0, 0xB0216064, 0xA214B001, 0xC250B215, 0x79B092D0, 0x79C09500, + 0x89709510, 0xC1B206F0, 0x14023110, 0x94E06F20, 0x6F201612, 0x827094F0, 0x44C12230, 0x7100B0E5, + 0xA0E5B125, 0x727960B9, 0x9200C030, 0xB004B002, 0x8170B005, 0x40CC2280, 0x60CD7BC0, 0x90607BB0, + 0x7BD09040, 0x90509070, 0x68D3C400, 0xB260B067, 0x31808480, 0x31818481, 0x00103981, 0x89759470, + 0x120E06F5, 0x12061207, 0x946012F0, 0x9460C190, 0xB149B021, 0xA10CB109, 0x1203B098, 0x71001204, + 0xA0E17279, 0xA109B149, 0xB10CB14C, 0x7100A464, 0x00000000, 0x6523B14C, 0x41161E76, 0x39408970, + 0x1C0F06F0, 0x84A044D5, 0x4CD51C90, 0x12021205, 0xB0831276, 0xB261B099, 0x85C0B2A0, 0x3D803180, + 0xC03091C0, 0xC0C065AE, 0x7BE09460, 0x611D9470, 0x91DF1647, 0x1E008190, 0x1C70411D, 0x71004922, + 0x220080A0, 0x60F84446, 0x12096064, 0xC06C120A, 0xB8A9120D, 0x318888E8, 0x1C893D88, 0x1C8A4930, + 0x613D4D36, 0x12001089, 0x100A1880, 0x613D10DB, 0x1200108A, 0x10091880, 0x168B10DB, 0x161D613D, + 0x41421E8D, 0x6127909C, 0x1E8210BF, 0x1495414A, 0x1E821612, 0x92C5454A, 0x494D1E8B, 0xC0701A8B, + 0x163018B0, 0x14011101, 0x909C6C01, 0x909C909C, 0x909C909C, 0x909C909C, 0xB091909C, 0xB8A91000, + 0x318388E3, 0xB0923D83, 0x1000B092, 0x88E4B8A9, 0x3D843184, 0x496F1E8F, 0x49741CA3, 0x49761CA4, + 0x1C937000, 0x1C944D74, 0x70004D76, 0x61781A1E, 0x6178161E, 0x1CE0C040, 0x10E0497F, 0x49821640, + 0xC00E7000, 0x7000B094, 0xB093C00E, 0x85207000, 0x0410C021, 0x70009520, 0x22018231, 0x7000418A, + 0xB0E1B260, 0x39818491, 0x10103141, 0x14103111, 0x419C1E00, 0xB12197B0, 0x7100B790, 0x7279B261, + 0x8491B121, 0x39713181, 0x31111010, 0x1E001410, 0x97B041AC, 0x7100B790, 0xB1217279, 0x7000A0E1, + 0x88509860, 0x45AF2200, 0x7000B840 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5.h new file mode 100644 index 00000000..66d10faa --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:11 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ble5 --fwdesc CC2340R5 LRF firmware for pbe, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/pbe_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/lrf_pbe_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/pbe_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_PBE_BINARY_BLE5_C +#define _LRF_PBE_BINARY_BLE5_C + + +#include + +/* Length of binary image. */ +#define LRF_PBE_BINARY_BLE5_LENGTH 930 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_PBE_binary_ble5[LRF_PBE_BINARY_BLE5_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c new file mode 100644 index 00000000..9dfa3d86 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble5_cc23x0r5.c @@ -0,0 +1,131 @@ +// This code snippet was auto-generated on Thu May 23 12:10:11 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ble5 --fwdesc CC2340R5 LRF firmware for pbe, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/pbe_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/lrf_pbe_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble5/pbe_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_pbe_binary_ble5.h" + +const uint32_t LRF_PBE_binary_ble5[LRF_PBE_BINARY_BLE5_LENGTH] = { + 0x000003A1, 0x7000601F, 0x636D0000, 0x6376634D, 0x6365637A, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x61120000, 0x60FD623F, 0x00000000, 0x00000000, 0x10070707, + 0x72820000, 0xB82267D3, 0x7100B070, 0xB0907282, 0x1EA080C0, 0x1E304F7A, 0xC09C482B, 0xB079671D, + 0x645A8957, 0xB097C041, 0xC01C9191, 0xA370671D, 0x1E1081C0, 0xB07A4769, 0x80C0120B, 0x11011630, + 0x6C011401, 0x604B6078, 0x607D604B, 0x62CA60AC, 0x61D0611F, 0x619C618D, 0x63861202, 0x16106D10, + 0x70006E10, 0x221184B1, 0x84794050, 0x84D19569, 0x44551E01, 0x70008599, 0xB3709397, 0x7000B091, + 0x22308D50, 0x87CE47C1, 0x180E8780, 0x486A1A10, 0x4F7E1E40, 0x68688781, 0x87858784, 0x70001A3E, + 0x79C2C071, 0xC0F16073, 0x949179D2, 0x95719481, 0x700094A2, 0x98227280, 0x9030B041, 0x8C3A604A, + 0x26BBC38B, 0xC01C609D, 0x81C0671D, 0x43692230, 0xB097C041, 0x89679191, 0xC01C645A, 0xA370671D, + 0x1E1081C0, 0x70004769, 0x123E67B9, 0x1E0E67BB, 0x2A4D4099, 0x67C5645E, 0x2A3B64B4, 0xA370894A, + 0x44A1223B, 0x1203A07A, 0x67C36687, 0x1C508A80, 0x66AB4B51, 0x665367BD, 0x609264CE, 0x645AC197, + 0x6092C30B, 0x644CCB91, 0x60C6B04B, 0x10018A00, 0x08103910, 0x40B02210, 0xCB812A5D, 0x40C22204, + 0x40C22214, 0x265D644C, 0x40C6227D, 0x644CCC11, 0x9A0D2A7D, 0x2A3D64EE, 0x22BB9A0D, 0x700044D4, + 0x4757221B, 0x22BB66BA, 0x700040D4, 0x22A08050, 0x222B40DA, 0x2A5B40DA, 0x311010B0, 0x225000B0, + 0x89B0404A, 0x06701002, 0x393240E7, 0x08020672, 0x70004363, 0x1C06CBD0, 0x66BA44ED, 0x70006367, + 0xC08CA0F0, 0xC07C671D, 0xC050671D, 0x89379190, 0x18178961, 0xCBF1645A, 0x6481644C, 0x64FF7000, + 0x22AB63C9, 0x8A904506, 0x410D2240, 0x700067B5, 0x8A9067B3, 0x450C2220, 0x2A8B2E6B, 0x8AB87000, + 0xCB261267, 0x610567D1, 0x1292C0F3, 0xB0236792, 0xA370B022, 0x120AB07A, 0x41D822AB, 0x475722DB, + 0xC0F36124, 0x8C3A26AB, 0xA3706124, 0x67AF72A4, 0x67C36687, 0x66AB6172, 0x22308A90, 0x22DB4133, + 0x229B4533, 0x2A7B4133, 0x67CB2A9B, 0x64E86653, 0x4512220B, 0x22008A20, 0x22EB4151, 0xD8004151, + 0x67A9943B, 0x4512227B, 0x4512226B, 0x22DB66BA, 0x8050444A, 0x474D22A0, 0x474D222B, 0x1A108A10, + 0x9A104958, 0x8A306112, 0x444A2220, 0x22408A40, 0x6112444A, 0x67B99A10, 0x67981267, 0x0404C400, + 0x8AA03114, 0x00043160, 0x9D141634, 0x10E5C0CE, 0xCAC1C050, 0x97D26D12, 0x69681611, 0x64EE67C1, + 0x894A26DB, 0x6123C0F3, 0x422422DB, 0x22208A30, 0x1E434584, 0xC2504755, 0x4B551C50, 0x4B551E65, + 0x39788D18, 0xCAF61267, 0x612967D1, 0x418A22AB, 0x47551E73, 0x63C7646E, 0x47551E83, 0xA3706188, + 0xC0F3B07A, 0x6687120A, 0x66AB67C3, 0x66531207, 0x66BA64E8, 0x22408D50, 0x604A458D, 0x120A26AB, + 0x22008D50, 0x8D3741B6, 0xB09293A7, 0x61B6B378, 0xB07AB072, 0x22A08050, 0x222B474D, 0x7100474D, + 0x220F805F, 0x222F4738, 0xB092436D, 0xA07AA072, 0x645AC197, 0x645E67B9, 0x64EE67C1, 0x1267161A, + 0x22208D50, 0x125745C5, 0x45C52210, 0x679861C6, 0x1E008D40, 0x1C0A41CB, 0x8D50404A, 0x45A62240, + 0x604AA378, 0x8A70C0F3, 0x41D71E00, 0xB072B092, 0x120AB378, 0x668767B1, 0x622467C3, 0x67CB66AB, + 0x64E86653, 0x4512220B, 0x943BD810, 0x227B67A9, 0x226B4512, 0x66BA4512, 0x404A1E83, 0x45F41E73, + 0x22208A30, 0x22DB404A, 0x604A41F4, 0x104667B9, 0xB092645E, 0xA378A072, 0x22408A90, 0x86F14204, + 0x679E1661, 0x22662A74, 0x26744204, 0x1E008A70, 0x86F14211, 0xC14086E3, 0x96E11401, 0x39228A62, + 0x96E397D2, 0x67C196E3, 0x8A3064EE, 0x456E2220, 0x67B9604A, 0x645E1046, 0x169186F1, 0x2A74679E, + 0x42212266, 0x67C12674, 0x635F64EE, 0x8A302AEB, 0x422A2210, 0x423D1E73, 0x22008A30, 0x8A804236, + 0x49121C50, 0x42411E13, 0x42491E03, 0x463722AB, 0x1E236112, 0x1E63424A, 0x1E734249, 0x646E4512, + 0x647163C7, 0x1EC56250, 0x64FF4512, 0x12778AA8, 0x67D1CAC6, 0x26EB6250, 0x1C50C250, 0x1E654912, + 0x64FF4912, 0x452922AB, 0x224861DC, 0x89A04257, 0x22589770, 0x8140425B, 0x22689770, 0x8130425F, + 0x22789770, 0x8C804263, 0x22889770, 0x8640426D, 0x39809770, 0x86509770, 0x39809770, 0x86A19770, + 0x42740631, 0x18101230, 0x6A729771, 0x106167CF, 0x6792644C, 0x1E676798, 0xB04D467C, 0x9C208C80, + 0xCB621061, 0xC0001821, 0x90402410, 0xB09D9A0D, 0x2A9B7000, 0x2A7B2A8B, 0x67B72A6B, 0x42911E0A, + 0x645A10A7, 0xC0BCB071, 0x671DB098, 0xA071A370, 0xB09CA07A, 0x671DC0CC, 0x10946450, 0x31841045, + 0x39853984, 0x162E105E, 0x646E7000, 0xB09C1A1E, 0x671DC0CC, 0x97796450, 0x1E1E63BF, 0x4BBF42A3, + 0x4BBF1A2E, 0x42B622FF, 0xC0CCB09C, 0xB09F671D, 0x97B96450, 0x62AB805F, 0x671DC08C, 0x9190C010, + 0x671DC07C, 0x1E0081C0, 0xC05042BE, 0x72259190, 0xC1976481, 0x7000645A, 0xA07AC0F3, 0x645AC197, + 0x645E67B9, 0x64EE67C1, 0x1E008C70, 0x22FB404A, 0x894A444A, 0x67B167AF, 0x6687A370, 0x62EA67C3, + 0x2A9B66AB, 0x665367CB, 0x67B56309, 0x22108A90, 0x2E6B46E9, 0x63032A8B, 0x1E53C220, 0xC0C042F6, + 0x42F61E33, 0x8AB86355, 0xCB261267, 0x630367D1, 0x47551C50, 0x22208C70, 0x1E5346F1, 0x67B342E3, + 0x22008A90, 0x2E6B4703, 0x8AA82A8B, 0xCAC61277, 0x2A9B67D1, 0x64E862DE, 0x4757220B, 0xD82066BA, + 0x67A9943B, 0x444A227B, 0x431A1E53, 0x444A1E33, 0x444A226B, 0x62CE26FB, 0x435B226B, 0x8071604A, + 0x907124C1, 0x805F7100, 0x4738220F, 0x473022AB, 0x4330222F, 0x8A6AB092, 0x1E4A1A1A, 0x8A7A4F2E, + 0x63209A6A, 0x907128C1, 0x436D20CF, 0x24C11201, 0x70009091, 0x80C2262B, 0x43761E12, 0x477A1E22, + 0x22A1B090, 0x6320474D, 0x67981257, 0x6346A370, 0x4749223B, 0xC0126351, 0x67A9C830, 0xC0726386, + 0x67A9C840, 0xC0226386, 0x67A9C850, 0x12926386, 0xC0326792, 0x67A9C860, 0x26FB6386, 0x22208A30, + 0xC0424617, 0x67A9C870, 0xC0626386, 0xCFA26386, 0xCF926382, 0xCFB26382, 0x67A9C880, 0x229F6382, + 0x221F4776, 0x22AF4742, 0x222B474D, 0x637E474D, 0xC890CFC2, 0x638267A9, 0xC8A0CFE2, 0x638267A9, + 0xC8B0CFF2, 0x638267A9, 0xB821678A, 0x6022B04F, 0xB820678A, 0x6022B040, 0x9190C050, 0x81C067D5, + 0x438D2230, 0x70009832, 0x6E028840, 0x1C01C681, 0x70004792, 0x6E078840, 0x1C01C681, 0x70004798, + 0x96E186E3, 0xCAF1C020, 0x97D26D12, 0x6BA21611, 0x96E396E3, 0x94207000, 0x22008410, 0xB40047AA, + 0xB0107000, 0xB0106008, 0xB0106009, 0xB010600A, 0xB010600B, 0xB010600C, 0xB010600D, 0xB010600E, + 0xB010600F, 0xB0106010, 0xB0106011, 0xB0106012, 0xB0106013, 0xB0106014, 0xB0106018, 0xB0106019, + 0xB0106002, 0xB010601B, 0xC010601A, 0xB0239190, 0xC00BB022, 0xA378A370, 0x7217720F, 0x72087207, + 0x1E008120, 0x81C043DE, 0x43E11E00, 0x730A7309, 0x00007000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00006027, 0x00007000, 0x00000000, 0x00000000, 0x63076303, 0x6318630B, 0x6120612E, + 0x61666141, 0x60546090, 0x6036623C, 0x0000625A, 0x00000000, 0x62CE629D, 0x6325621C, 0x04568000, + 0x04580457, 0x04960459, 0x04980497, 0x07070499, 0xC8C01007, 0x62F966F1, 0x84D19569, 0x442B1E01, + 0x94698599, 0x8D297000, 0x64E9C0FC, 0x6031642A, 0x403A220D, 0x603B2A24, 0x222D2624, 0x2A344440, + 0x60422A1D, 0x261D2634, 0x22A08050, 0x222B444F, 0x8C60444F, 0x404C2200, 0x60502644, 0x444F2210, + 0x2A446050, 0x2244264B, 0x2A4B4454, 0x64E9C03C, 0x64E9C01C, 0xB0F0A370, 0xB097B098, 0x22308D50, + 0x31854431, 0x10490054, 0x6074642A, 0x063186F1, 0x1230406B, 0x87811810, 0x62F76869, 0x1A1E650E, + 0xB09F8789, 0x64E9C0FC, 0x6085642A, 0x406C1E1E, 0x1A2E4885, 0x805F4885, 0x408222CF, 0xC0FCB09F, + 0xB09C64E9, 0x470122DF, 0x642A87C9, 0x650E6074, 0x85588547, 0x642A1079, 0x10793987, 0x1089642A, + 0x6064642A, 0x7A50650E, 0xB09C94A0, 0x8998C020, 0x409F2238, 0x64E9C0CC, 0xB09C64DF, 0x68989779, + 0xC0CC60A4, 0x64DF64E9, 0x689FB09C, 0x80E08927, 0x40A92200, 0x89618917, 0x93971817, 0xB091B370, + 0xCBE61282, 0x22CB8A0D, 0x26CB44B8, 0x9CAA864A, 0x9CB18651, 0x1E218901, 0x80E048C0, 0x22001231, + 0x122144C0, 0x1E008520, 0x853044C7, 0x44C71E00, 0x262160D6, 0xC8D099A1, 0x125766F1, 0x2208CBA6, + 0x129240D0, 0x44D4220B, 0x62F7260B, 0x62F7261B, 0x2A0B99A1, 0x44DE22BB, 0x9C418641, 0x9C518651, + 0x84B162F7, 0x40DF2211, 0x95698479, 0x1E0184D1, 0x859944E4, 0x80717000, 0x907124C1, 0x805F7100, + 0x4504220F, 0x44FC22AB, 0x40FC222F, 0x8A6AB092, 0x1E4A1A1A, 0x8A7A4CFA, 0x60EC9A6A, 0x907128C1, + 0x42F920CF, 0x24C11201, 0x70009091, 0x80C2262B, 0x42FD1E12, 0x46FF1E22, 0x22A1B090, 0x60EC46FB, + 0x7A52C071, 0xC0F16113, 0x94917A62, 0x95719481, 0x700094A2, 0x952189E1, 0x953189F1, 0x950189C1, + 0x70007251, 0xC0216518, 0x31408900, 0xB0970001, 0xB0989191, 0x9111B093, 0xC0516511, 0x62F792C1, + 0x9C80C7F0, 0x8900C031, 0x00013140, 0x1C018190, 0xB0974139, 0xB0989191, 0x9111B09B, 0x651192C1, + 0x65187225, 0x8A0D62F7, 0x22918691, 0x224D454E, 0x10D04152, 0x08D03910, 0x45522210, 0x614FC114, + 0x12051214, 0x264D120E, 0x222462F7, 0x262D4157, 0x2A2D7000, 0x89A07000, 0x99A02630, 0x2218CBB6, + 0x12924160, 0x2A0D62F7, 0x41652234, 0x7000260D, 0x265B1257, 0x4590220B, 0x10406553, 0x08D03930, + 0x41592200, 0x45771E05, 0x2228CBC6, 0x12924177, 0x223D6561, 0x1040458D, 0x08D03910, 0x221089B1, + 0x06714191, 0xCB6199B1, 0xB04C6594, 0x458D224D, 0x6594CB51, 0x225DCB71, 0x6594418C, 0x22441267, + 0x2A5B4590, 0x168162F7, 0x62F799B1, 0x16106D10, 0x70006E10, 0x262BB090, 0x1E2180C1, 0x62FD419E, + 0x80517100, 0x419822C1, 0x221184B1, 0x847D41A2, 0x84D1956D, 0x45A71E01, 0xB09C859D, 0x1A2E97BD, + 0xC8E07000, 0x72D066F1, 0x6D1212F0, 0x6E1226F2, 0x69B31641, 0x7000CFF0, 0xB07C9D14, 0x9AFD659E, + 0x7000660D, 0x9B0D659E, 0x7000660D, 0x9B1D659E, 0xA07C660D, 0xC8F07000, 0x8CD166F1, 0x220179C6, + 0x260641D0, 0x41D32264, 0x79DA2616, 0x6DA212F0, 0x1C260412, 0x164A41E6, 0x73CC69D5, 0x22FD266B, + 0x22ED45E4, 0x226441E4, 0x268B41E4, 0x7000C006, 0x180AC0FA, 0xC0069CCA, 0xC9007000, 0x8CF166F1, + 0x220179C6, 0x260641F2, 0x41F52264, 0x7A1A2616, 0x6DA212F0, 0x1C260412, 0x164A4208, 0x73CE69F7, + 0x22FD266B, 0x22ED4606, 0x22644206, 0x268B4206, 0x7000C006, 0x180AC0FA, 0xC0069CEA, 0xC0F07000, + 0x1CD66D26, 0x164A4615, 0x6A0E1642, 0x6DA6621B, 0x6EA62AF6, 0x1642164A, 0x70006A0E, 0x1A6E661F, + 0x122062F7, 0x16166D62, 0xC0CCB09C, 0x64DF64E9, 0x97B9B09C, 0x422B1C29, 0x6A20247B, 0x08483078, + 0x42312078, 0x207B247B, 0x22F9423B, 0x22E9463B, 0x2074423B, 0x1627423B, 0x7000247B, 0x1E031230, + 0x22544643, 0x161E4243, 0x04431A10, 0x163210E2, 0x92523132, 0x161110E1, 0x89D21401, 0x97B11421, + 0x1A109770, 0x6A509770, 0x97759774, 0xB0431A2E, 0x81D0B09C, 0x62F79C80, 0x4B3A1E15, 0xC3F166C8, + 0x04171097, 0x39611091, 0x31861016, 0x1E118A30, 0x4A6B4270, 0x42751E21, 0x22DB633A, 0x2230466F, + 0x627A433A, 0x433A2240, 0x467A22AB, 0x22506277, 0x2220433A, 0x26EB427A, 0x42C11E07, 0x5F3A1C7E, + 0x009666C8, 0x9A461A17, 0x22066511, 0x1A67429F, 0x5F3A9A57, 0x468B22DB, 0x22AB6340, 0x8A904695, + 0x46972240, 0x12678AB8, 0x661FCB26, 0x8D18629C, 0x10486298, 0x12673978, 0x661FCAF6, 0x8A461A6E, + 0x22168A57, 0x1A6742AB, 0x5F3A9A57, 0x12778AA8, 0x661FCAC6, 0x8A461A6E, 0x22268A57, 0x1A1742AF, + 0x22365F3A, 0x1A2742B3, 0x22465F3A, 0x1A3742B8, 0x264B5F3A, 0x42BC2256, 0x5F3A1B27, 0x42C32266, + 0x5F3A1A17, 0xC91062C3, 0xD92066F1, 0x66F19437, 0x633E9A46, 0x64E9C0CC, 0x977964DF, 0x70001A1E, + 0x1207265B, 0x46EE220B, 0x396110B1, 0x46EC22DB, 0x1E5106F1, 0x1E5346E1, 0x898046E1, 0x42E12200, + 0x2A8B2A6B, 0x897062EE, 0x04100230, 0x1E5042EE, 0x1EA042EF, 0x1EF042EF, 0x615942EF, 0x45590631, + 0xB9A462F7, 0x942062F7, 0x22008410, 0xB40046F2, 0xA0107000, 0xA0106001, 0xA0106003, 0xA0106004, + 0xA0106005, 0xA0106006, 0x79D16007, 0x9CC065AF, 0x7A1162F7, 0x9CE065AF, 0xBD0062F7, 0x79E279DA, + 0x79DA65BA, 0x65C079F2, 0x7A0279DA, 0x65C965C4, 0x62F7AD00, 0x7A1ABD01, 0x65BA7A22, 0x7A327A1A, + 0x7A1A65C0, 0x65C47A42, 0xAD0165EB, 0x1E8262F7, 0x8690472D, 0x432E2220, 0x1292CBD6, 0x62F72A5B, + 0x22342A0D, 0x260D4332, 0x2204CC01, 0x22144339, 0x65944339, 0x62F7267D, 0x66F1C930, 0x6015A010, + 0x6016A010, 0x6017A010 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs.h new file mode 100644 index 00000000..efa80aa3 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:23 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ble_cs --fwdesc CC2340R5 LRF firmware for pbe, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/pbe_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/lrf_pbe_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/pbe_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_PBE_BINARY_BLE_CS_C +#define _LRF_PBE_BINARY_BLE_CS_C + + +#include + +/* Length of binary image. */ +#define LRF_PBE_BINARY_BLE_CS_LENGTH 378 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_PBE_binary_ble_cs[LRF_PBE_BINARY_BLE_CS_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs_cc23x0r5.c new file mode 100644 index 00000000..b282a050 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ble_cs_cc23x0r5.c @@ -0,0 +1,62 @@ +// This code snippet was auto-generated on Thu May 23 12:09:23 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ble_cs --fwdesc CC2340R5 LRF firmware for pbe, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/pbe_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/lrf_pbe_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ble_cs/pbe_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_pbe_binary_ble_cs.h" + +const uint32_t LRF_PBE_binary_ble_cs[LRF_PBE_BINARY_BLE_CS_LENGTH] = { + 0x00000179, 0x00006080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03030B00, + 0x078005A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x9190C010, + 0xB022B023, 0xA370C00B, 0x720FA378, 0x72077217, 0x81207208, 0x40771E00, 0x1E0081C0, 0x7309407A, + 0x7000730A, 0x646C7282, 0xB070B822, 0x72827100, 0xB090A070, 0x1E4280C2, 0x1E224EDC, 0xB0794891, + 0xA0797100, 0x1632B099, 0x14211101, 0x61BB6C01, 0x61DD62D3, 0xB45061BC, 0x938078C0, 0x937078D0, + 0x00DD8971, 0x8BF040A3, 0x93911801, 0xB091733A, 0xB370B092, 0x7902B378, 0xC04191B2, 0x8900B097, + 0x40B12210, 0x91912641, 0x31800610, 0xD0013110, 0x91A10001, 0xC9627000, 0xB094C0B0, 0x7100B074, + 0x6D21B094, 0x161290D1, 0xA07468BD, 0xC1027000, 0x87C126C2, 0x70006E21, 0x26C2C102, 0xB074B094, + 0x6D216D21, 0xB0947100, 0x161290D1, 0x87C1C120, 0x71006E21, 0xB09490D1, 0x68D51612, 0x87C1C110, + 0x16126E21, 0xA07468DD, 0xC6A27000, 0x7B0126C2, 0x16126E21, 0x6E21C001, 0xB0947000, 0xC1F0B074, + 0x7100720D, 0x80E1B094, 0x68EE97B1, 0xC562C003, 0xC15026C2, 0x6D216D21, 0x6E2397B1, 0x68F81612, + 0x7000A074, 0x9B6181E1, 0x1E017911, 0x89014512, 0x45122201, 0x9B438133, 0x22F48B34, 0x16144512, + 0x8B229B34, 0x9B221432, 0x79117000, 0x41371E01, 0x22018901, 0xB0964537, 0x8B21B076, 0x8B329151, + 0x39123112, 0x8B329172, 0x453722F2, 0x41351E02, 0xB0967100, 0x9B538163, 0xB0967100, 0x81638184, + 0x9BC39BD4, 0x22F1C015, 0x1A254534, 0x72B39BE5, 0xA07672B2, 0x89157000, 0x0BFB105B, 0x04528922, + 0x04B18451, 0x94520012, 0x10617000, 0x147106F1, 0x6D126D12, 0x84510452, 0x001204B1, 0x39469452, + 0x8A437000, 0x7B318A54, 0x7B411413, 0xB0911414, 0x9393B071, 0xB0917100, 0x89998A0A, 0x89B814A9, + 0x1408CF00, 0x8915C927, 0x7B161A19, 0x1A108960, 0xC00A9399, 0x66AA6543, 0x81217100, 0x418B1E21, + 0x6968B091, 0x710066AA, 0x66AAB091, 0x89607B16, 0x14481A10, 0x93981498, 0x6543C00A, 0x710066A8, + 0x9399B091, 0x66A8697B, 0x1E317911, 0x79214588, 0x418B2211, 0xB0917100, 0x653966A8, 0xA071A370, + 0x8BA37000, 0x5D9514F3, 0x16148BB4, 0x9BA39BB4, 0x22038903, 0x8BB345BA, 0x1C348BD4, 0x45BA49A9, + 0x8BC48BA3, 0x41A522F4, 0x41BA22F3, 0x22F361A7, 0x1C3445A9, 0x8BC54DBA, 0x0BF58BD6, 0x16150BF6, + 0x16165DB0, 0x8BB48BA3, 0x14531464, 0x16145DB6, 0x9BB49BA3, 0x143F8BE3, 0x62D37000, 0x398B890B, + 0x1E0B78FF, 0x87C242D3, 0x10B087C0, 0x00023180, 0x721AC070, 0x919091B2, 0x924BC0A1, 0x87C29111, + 0xB09487C0, 0xC030B074, 0xB0947100, 0x97B180E1, 0x91B2720D, 0x1A1B69D2, 0x45CD1E0B, 0xB45162D3, + 0x398E890E, 0xC01CC00D, 0x1E0EA451, 0x64C542D3, 0x1E0D6499, 0x1E0E41EC, 0x61F441FC, 0x9251C011, + 0x9111C011, 0x64CA64B9, 0x62028C02, 0x9251C021, 0x9111C011, 0x64EB64CA, 0x6202C002, 0x9251C031, + 0x9111C011, 0xC00264EB, 0x22B18691, 0x222146D7, 0x7B2F46DA, 0x658F142F, 0x93AF1A1F, 0x92017AE1, + 0x92117AF1, 0x92217AC1, 0x92317AD1, 0x42D300EE, 0xB07164E3, 0xA0717100, 0xA450B091, 0x1E1181C1, + 0xC0514222, 0x627B9191, 0x1E1080C0, 0x805042D5, 0x46D52290, 0x46D522A0, 0xC6417900, 0x427A1C10, + 0x06128902, 0x3122042C, 0x79111622, 0x42371E01, 0x1421C00C, 0x8902C063, 0x423D2212, 0x91A12643, + 0x924C9193, 0x65139111, 0x66916539, 0x7911B098, 0x424C1E01, 0x424B1E11, 0x627A654F, 0x467A1E1C, + 0x8A20A370, 0x46551FF0, 0xB092A378, 0x00DD625B, 0x8C014259, 0x93A01810, 0xB073B378, 0xB079B070, + 0xB072B07A, 0x72077100, 0xB092B090, 0xB0938050, 0x46742230, 0xA3787211, 0x00DD8A21, 0x8C00426F, + 0x10F01801, 0x1A401810, 0x627A93A0, 0xA378C00C, 0x8C018A30, 0x93A01410, 0xA370B378, 0x7100B072, + 0xB092A072, 0x8121B370, 0x42871E11, 0x42881E21, 0x650062DE, 0x9B9D161D, 0x45E51A1E, 0x22218901, + 0x161E41E7, 0x793161E5, 0x42A71010, 0x31109A90, 0x26C2C242, 0x6D24CAA3, 0x6E346D24, 0x16131612, + 0x79006A99, 0x89029A70, 0x46A42212, 0x9A813171, 0x70009A6D, 0x62ABC002, 0x8901C012, 0x1C210611, + 0x1E0A46D2, 0x161A46B5, 0x26C3C563, 0xA07162D2, 0x7217B076, 0xB0967100, 0x6E318161, 0x72171613, + 0xB0967100, 0x6E318161, 0x72171613, 0xB0967100, 0x6E318161, 0x72171613, 0xB0967100, 0x6E318161, + 0xB0961613, 0xB071A076, 0x12027000, 0xCFC262E6, 0xA45062E0, 0x62E0CFA2, 0x62E0CF92, 0x62E0CFE2, + 0x62E0CFF2, 0x9190C050, 0xB8229832, 0x62EBB04F, 0x9190C050, 0xB8219832, 0x7309B040, 0x720F7207, + 0x721A7237, 0x6083721B }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common.h new file mode 100644 index 00000000..ffbeb6cd --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:00 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname common --fwdesc CC2340R5 LRF firmware for pbe, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/pbe_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/lrf_pbe_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/pbe_common_ram.bin +// Binary source last modified: 23-May-2024 12:08 + + +#ifndef _LRF_PBE_BINARY_COMMON_C +#define _LRF_PBE_BINARY_COMMON_C + + +#include + +/* Length of binary image. */ +#define LRF_PBE_BINARY_COMMON_LENGTH 2 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_PBE_binary_common[LRF_PBE_BINARY_COMMON_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common_cc23x0r5.c new file mode 100644 index 00000000..1f6e2c4d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_common_cc23x0r5.c @@ -0,0 +1,15 @@ +// This code snippet was auto-generated on Thu May 23 12:09:00 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname common --fwdesc CC2340R5 LRF firmware for pbe, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/pbe_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/lrf_pbe_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/common/pbe_common_ram.bin +// Binary source last modified: 23-May-2024 12:08 + + +#include "lrf_pbe_binary_common.h" + +const uint32_t LRF_PBE_binary_common[LRF_PBE_BINARY_COMMON_LENGTH] = { + 0x00000000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic.h new file mode 100644 index 00000000..5682c015 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:41 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname generic --fwdesc CC2340R5 LRF firmware for pbe, mode generic /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/pbe_generic_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/lrf_pbe_binary_generic.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/pbe_generic_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_PBE_BINARY_GENERIC_C +#define _LRF_PBE_BINARY_GENERIC_C + + +#include + +/* Length of binary image. */ +#define LRF_PBE_BINARY_GENERIC_LENGTH 738 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_PBE_binary_generic[LRF_PBE_BINARY_GENERIC_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic_cc23x0r5.c new file mode 100644 index 00000000..3575d4a2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_generic_cc23x0r5.c @@ -0,0 +1,107 @@ +// This code snippet was auto-generated on Thu May 23 12:09:41 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname generic --fwdesc CC2340R5 LRF firmware for pbe, mode generic /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/pbe_generic_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/lrf_pbe_binary_generic.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/generic/pbe_generic_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_pbe_binary_generic.h" + +const uint32_t LRF_PBE_binary_generic[LRF_PBE_BINARY_GENERIC_LENGTH] = { + 0x000002E1, 0x70006012, 0x00000000, 0x635C6347, 0x6378638C, 0x63906388, 0x603D6380, 0x000060DE, + 0x07070019, 0x00000000, 0x67BD7282, 0xB070B822, 0x72827100, 0x8A1D80C7, 0x22208CF0, 0x26EB401E, + 0xC150B090, 0x4F8C1C07, 0x78F2C071, 0x94819491, 0x94A29571, 0x318080C0, 0x1E003980, 0x1E10432B, + 0x1E20403F, 0xC101403F, 0x4B8C1810, 0x11011630, 0x6C011401, 0x611263B9, 0x6050604C, 0x120262FF, + 0x63996398, 0x93908910, 0xC041B370, 0xC01C9191, 0xA3706738, 0x1E0081C0, 0x70004388, 0xB0796731, + 0x603D6440, 0x6453B079, 0xC051603D, 0xC07C9191, 0x6738B097, 0x1E0081C0, 0x22004055, 0x70004390, + 0x72517250, 0x8921C034, 0x406722B1, 0x95B4C074, 0x92C4C014, 0x446B2271, 0x89617000, 0x89819501, + 0x89919521, 0x89219531, 0x44752261, 0x85B57000, 0x95B1C0F1, 0x92C1C011, 0x4482228B, 0x95A18201, + 0x821164DA, 0x608795A1, 0x95A18221, 0x823164DA, 0x64DA95A1, 0x892195B5, 0x448E22B1, 0x92C1C031, + 0x89227000, 0x22822A92, 0x2692409A, 0x8922609A, 0x22A22A92, 0x2692409A, 0x221184B1, 0x8479409A, + 0x44A922B2, 0x64DA9569, 0x44A62292, 0x70008599, 0x398985D9, 0x95897000, 0x85D964DA, 0x85913989, + 0x700095A1, 0x2A928922, 0x40B52282, 0x84952692, 0x1A111081, 0x95719491, 0x221184B1, 0x847940BA, + 0x64DA9569, 0x44C42292, 0x60C98599, 0x398985D9, 0x1881C081, 0x94953819, 0x70009575, 0x22918921, + 0x956944D4, 0x859964DA, 0x70009469, 0x64DA9589, 0x398985D9, 0x70009469, 0x1E0184D1, 0x700044DA, + 0xC08CA0F0, 0xC07C6738, 0xB0226738, 0x16108BE0, 0x12679BE0, 0x44EE228D, 0x227D1257, 0x60EF44EE, + 0x805067AB, 0x477822A0, 0x4778224B, 0x22FBC3D6, 0x22CD40F9, 0xD002443D, 0x223D8A01, 0xFBB24277, + 0x627789F1, 0x2A6B2ACB, 0x67A51292, 0x221080E0, 0xB0234504, 0xC010B022, 0xA3709190, 0x8120B07A, + 0x410D1E00, 0x611E89DE, 0x89CE267B, 0x22EB263B, 0x26FB4118, 0xB07A6731, 0x225DB079, 0x6440451E, + 0x1E0E669F, 0x939E4125, 0xB091B370, 0xC03CB071, 0x6738B098, 0xB091A370, 0xA07AA071, 0x81D02ABB, + 0x1C10C7F1, 0x9D90413A, 0xAD442A8B, 0x222080E0, 0x268B4139, 0x645EBD44, 0xC3F18920, 0xC0780410, + 0xC0030408, 0x496B1A10, 0x10033930, 0xCD5E1613, 0x22828922, 0xB09C4557, 0x6738C0CC, 0x45521E00, + 0x41521E08, 0x615364B0, 0x6EE9648F, 0x6949161E, 0x140E6169, 0x41621E08, 0xC0CCB09C, 0x64B06738, + 0x1A1E6EE9, 0x49691A10, 0xC0CCB09C, 0x648F6738, 0x1A1E6EE9, 0xB82B6962, 0x8922C1F8, 0x456F2272, + 0x89A0646B, 0x39571007, 0x1E070487, 0x26BB4578, 0x619C8A2E, 0x10060480, 0x10020636, 0xCD5E3932, + 0x6DE4142E, 0x10711205, 0x1E911461, 0x161E4987, 0x105E6DE5, 0x004E318E, 0x2A2B2A0B, 0x127C2A1B, + 0x004B04C4, 0x41931E06, 0x12E0386E, 0x10711202, 0x459A1C01, 0x1A112402, 0x042E6996, 0x140E89B0, + 0x8A204900, 0x49001CE0, 0x893010E1, 0x39301A10, 0x14011610, 0x31311431, 0x10E99251, 0x14098950, + 0x39408940, 0x14090670, 0x22AB1619, 0x143941B6, 0x977097B9, 0xCD5169B7, 0x1E001030, 0x22AB41C4, + 0x1A1041C4, 0x97726D12, 0x69C01611, 0xC7F181D0, 0x41C91C10, 0x8CF49D90, 0x38241232, 0x12070674, + 0x9DB79DA7, 0x9DD79DC7, 0x66B7CDA7, 0x12572A5B, 0x462122CB, 0x12318CF0, 0x06703810, 0x41F91E00, + 0x8DB48DA5, 0x00543184, 0x8DDE8DC5, 0x00E5318E, 0xCCB11210, 0x45EB228B, 0x6D1ECC71, 0x45F31CE4, + 0x6D1E1611, 0x45F41CE5, 0x161161F8, 0x69EB1611, 0x66F81201, 0x8A1D9C61, 0x421C22FB, 0x8D618D5C, + 0x001C3181, 0x126110B4, 0x228B0414, 0xCD2ECD33, 0xCD134609, 0x6D30CD0E, 0x42152200, 0x1C040410, + 0x6DE04615, 0x46151CC0, 0x2ACB66F8, 0x6D30621C, 0x2A102A20, 0x00402600, 0x6EEC6E30, 0x81401267, + 0x81309C20, 0x22B89C10, 0x8D404225, 0x22C89770, 0x81404229, 0x22D89770, 0x8130422D, 0x22E89770, + 0x8D904231, 0x22F89770, 0x8640423B, 0x39809770, 0x86509770, 0x39809770, 0x86A19770, 0x42420631, + 0x18101230, 0x6A409771, 0x464A1E82, 0x22208690, 0xCBC6424A, 0x265B1292, 0x16106D60, 0x67A56E60, + 0x106167AB, 0x1821CB52, 0x2410C000, 0xB09D9040, 0x4784225B, 0x6738C08C, 0x9190C010, 0x22A08050, + 0x224B4778, 0xD0064778, 0x4265229B, 0x22CB603D, 0x22BD426B, 0x22FB403D, 0x226B4500, 0x22FB4271, + 0x22CD4671, 0xFBB2443D, 0x223D89F1, 0xD0024277, 0x2A3B8A01, 0x443D222D, 0x429E221D, 0xB3709391, + 0xCD33228B, 0xCD134682, 0x39306D30, 0x1E100630, 0x1E304291, 0x1E204294, 0x1062428D, 0x220B6294, + 0x10624694, 0x220B6294, 0x10624294, 0x1C02C3D0, 0xC01C403D, 0xA3706738, 0x1C02FBB0, 0x610043BB, + 0x72256C02, 0xC7F0B093, 0xC0319D90, 0x06708900, 0x00013140, 0xC0319111, 0x39308900, 0x00013140, + 0x1E0081C0, 0x919142AE, 0x22DD2AAB, 0x26AB42B6, 0x89227000, 0x4AC61A1E, 0xC0CCB09C, 0x649A6738, + 0x1E049779, 0x1A1442C4, 0x16176E79, 0x62B8B09C, 0xC7F181D0, 0x42CB1C10, 0x89309D90, 0x42E43930, + 0x1A108948, 0xC0CCCD53, 0x64956738, 0x22A8B09C, 0x977942D8, 0x16136E39, 0x12826AD1, 0x64DACBD6, + 0x85318520, 0x46EE1E00, 0x46EE1E01, 0x8D90B828, 0x72D49C00, 0x8641266B, 0x86519C41, 0x70009C51, + 0xB829BD42, 0x67B1C800, 0x2278CB96, 0x129242F6, 0x700026CB, 0xBD4326CB, 0x2288CBA6, 0x129242FE, + 0x8A607000, 0x47042200, 0x6738C09C, 0x10018A70, 0x31813980, 0x91103981, 0xB0989191, 0x8A60B097, + 0x22103980, 0x8A814323, 0xB0919391, 0xA370B071, 0xC01CB370, 0x8A606738, 0x43292280, 0x22008120, + 0x81C0432A, 0x432A2200, 0x22006329, 0xC08C4323, 0xC07C6738, 0x603D6738, 0x72806390, 0x12209822, + 0x9030B041, 0x226D603D, 0xB07A4737, 0x6738C09C, 0x7000A07A, 0x24C18071, 0x71009071, 0x28C1805F, + 0x220F9071, 0x20CF4750, 0x12014347, 0x909124C1, 0x229F7000, 0x221F475C, 0x22AF4762, 0x224B4778, + 0x63904778, 0x80C2264B, 0x435C1E12, 0x478C1E22, 0x22A1B090, 0x24C14778, 0x633B9071, 0xA079B099, + 0xA070B090, 0x6394CFC2, 0x8BF0B82A, 0x9BF01610, 0x221080E0, 0xB0234766, 0x9191C011, 0x67AB1257, + 0xB091A370, 0x223BA071, 0x637C4774, 0xC810C012, 0x639867B1, 0xC820C072, 0x639867B1, 0xC830C022, + 0x639867B1, 0xC840CFA2, 0x639467B1, 0xC850CF92, 0x639467B1, 0xC860CFB2, 0x639467B1, 0xC870CFE2, + 0x639467B1, 0xC880CFF2, 0x639467B1, 0xB821679C, 0x6015B04F, 0xB820679C, 0x6015B040, 0x43A2227B, + 0x47A2224D, 0x9190C050, 0x983267BF, 0x88407000, 0xC6816E02, 0x47A51C01, 0x88407000, 0xC6816E07, + 0x47AB1C01, 0x94207000, 0x22008410, 0xB40047B2, 0xB0107000, 0xB0106002, 0xB0106003, 0xC010600D, + 0xB0239190, 0xC00BB022, 0xA378A370, 0x7217720F, 0x72087207, 0x1E008120, 0x81C043C8, 0x43CB1E00, + 0x730A7309, 0x00007000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00006012, 0x60B26012, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x60BC0000, + 0x07070019, 0x00000000, 0x6593C890, 0x84D16199, 0x44151E01, 0x89217000, 0x442922B1, 0x44232291, + 0x64159569, 0x94698599, 0x95897000, 0x85D96415, 0x94693989, 0x95697000, 0x641595C9, 0x398985D9, + 0x70009469, 0x22B18921, 0x22814429, 0x601E4423, 0x10828575, 0x95721A12, 0x22818921, 0x95694441, + 0x85996415, 0x95896048, 0x85D96415, 0xC0813989, 0x38191881, 0x84859575, 0x94699482, 0x220184B1, + 0x9485404C, 0x72507000, 0xC0547251, 0x22B18921, 0xC074405A, 0xC01495B4, 0x227192C4, 0x7000445E, + 0x95018961, 0x95218981, 0x95318991, 0x22618921, 0x70004468, 0xC0F185B5, 0xC01195B1, 0x824192C1, + 0x447722D1, 0x95A18201, 0x82116415, 0x641595A1, 0x8221607D, 0x641595A1, 0x95A18231, 0x95B56415, + 0x22B18921, 0xC0514483, 0x700092C1, 0x93908910, 0xC041B370, 0xC01C9191, 0xA3706497, 0x1E0081C0, + 0x700041A3, 0x4496226D, 0xC09CB07A, 0xA07A6497, 0x80717000, 0x907124C1, 0x805F7100, 0x907128C1, + 0x44A6220F, 0x419B20CF, 0x24C11201, 0x70009091, 0x80C2264B, 0x419D1E12, 0x459F1E22, 0x22A1B090, + 0x24C145A1, 0x609A9071, 0x120A267B, 0x40B722EB, 0x6490269B, 0x225DB079, 0x648444BC, 0x22FBA24D, + 0x228B40C2, 0xB24D40C2, 0x8900C021, 0x31400670, 0x91110001, 0x8900C021, 0x31403930, 0x91910001, + 0x939078E0, 0x22FBB370, 0x60E740D4, 0x26DB26CB, 0x44E7229D, 0x22AD2ADB, 0x2ACB44E7, 0x878087CE, + 0x1E00180E, 0x1A1040E6, 0x4DA51E50, 0x68E48781, 0x64511A1E, 0x6497C03C, 0x6497C01C, 0xB0F0A370, + 0xB098B097, 0x22FBB82B, 0x10B34116, 0x2A030673, 0x12328CF9, 0x06793829, 0x120E1090, 0x00393139, + 0x8921C038, 0x45062281, 0x12096430, 0x610B6436, 0x12091093, 0x10396436, 0x1A106430, 0xCDA34912, + 0x16136D39, 0x690E6419, 0xC0FCB09F, 0x61546497, 0x456322DB, 0xC3F18920, 0x414F0410, 0x0408C078, + 0x39301A10, 0xCD571003, 0x1A1E8789, 0x16176E79, 0x10306922, 0x22818921, 0xCD57453B, 0x16176D79, + 0x6497C0FC, 0x45A722DF, 0x45381E00, 0x41381E08, 0x614F6436, 0x692C6430, 0x1A17614F, 0x41471E08, + 0x1A176D79, 0x6497C0FC, 0x45A722DF, 0x1A106436, 0x6D79494F, 0xC0FC1A17, 0x22DF6497, 0x643045A7, + 0x8D576947, 0x2207260B, 0x2A0B4554, 0x22728922, 0x645E4558, 0x455C22CB, 0x496D1A1E, 0x6497C0FC, + 0x45A722DF, 0x64198789, 0x8A396158, 0x6497C0FC, 0x8A396419, 0xC0FC3989, 0x64196497, 0x89216163, + 0x457922A1, 0x85588547, 0x39879D57, 0x9D789D67, 0x9D883988, 0x85276181, 0x9D878538, 0x9D773987, + 0x39889D68, 0x89309D58, 0x1E003930, 0xCD52418B, 0x6D291A10, 0x16126419, 0x86F16987, 0x41920631, + 0x18101230, 0x69908781, 0x942061AB, 0x22008410, 0xB4004594, 0xA0107000, 0xA0106001, 0xA0106004, + 0xA0106005, 0xA0106006, 0xA0106007, 0xA0106008, 0xA0106009, 0xA010600A, 0xA010600B, 0xC010600C, + 0xB0239190, 0xC00BB022, 0xA378A370, 0x7217720F, 0x72087207, 0x1E008120, 0x81C041B8, 0x41BB1E00, + 0x730A7309, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee.h new file mode 100644 index 00000000..ab3c2c79 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:59 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ieee --fwdesc CC2340R5 LRF firmware for pbe, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/pbe_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/lrf_pbe_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/pbe_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_PBE_BINARY_IEEE_C +#define _LRF_PBE_BINARY_IEEE_C + + +#include + +/* Length of binary image. */ +#define LRF_PBE_BINARY_IEEE_LENGTH 914 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_PBE_binary_ieee[LRF_PBE_BINARY_IEEE_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c new file mode 100644 index 00000000..fdf7bc0a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_pbe_binary_ieee_cc23x0r5.c @@ -0,0 +1,129 @@ +// This code snippet was auto-generated on Thu May 23 12:09:59 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu pbe --fwname ieee --fwdesc CC2340R5 LRF firmware for pbe, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/pbe_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/lrf_pbe_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee/pbe_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_pbe_binary_ieee.h" + +const uint32_t LRF_PBE_binary_ieee[LRF_PBE_BINARY_IEEE_LENGTH] = { + 0x00000391, 0x07076018, 0xFFFF001B, 0x9190C010, 0xB022B023, 0xA370C00B, 0x720FA378, 0x72077217, + 0x81207208, 0x400F1E00, 0x1E0081C0, 0x73094012, 0x7000730A, 0x64047282, 0xB070B822, 0x72827100, + 0xB09080C7, 0x1C07C1E0, 0xC0714F20, 0x94917812, 0x95719481, 0x80C094A2, 0x39803180, 0x403E1E00, + 0x403D1E10, 0x403D1E20, 0x1810C1C1, 0x16304B20, 0x14011101, 0x60576C01, 0x1202606C, 0x632D632C, + 0xB031B041, 0x8900603B, 0xB3709390, 0x9191C041, 0x66B8C01C, 0x81C0A370, 0x431C1E00, 0x84B17000, + 0x404D2211, 0x95698479, 0x1E0184D1, 0x85994452, 0x63467000, 0x673A1292, 0x221080E0, 0xB023445A, + 0xC010B022, 0xA3709190, 0x8120B07A, 0x40631E00, 0x8D20120E, 0x406B2280, 0x6070893E, 0x66B1896D, + 0xB079B07A, 0x26FA6574, 0x93A0C3F0, 0xB072B092, 0xB378B0A8, 0x40811E0E, 0xA378A072, 0x939E2AFA, + 0xB091B370, 0x120BB071, 0xB098C03C, 0xA37066B8, 0xA071B091, 0x2AFAA07A, 0xB092B0A8, 0xA378A072, + 0x93907830, 0xB091B370, 0xBA80B071, 0x120A1204, 0x67566771, 0x72506584, 0x72537252, 0xC7F2109E, + 0x10E1042E, 0x10101611, 0x92513131, 0x89413170, 0x89011410, 0xCAC11810, 0x93901810, 0x1E0E1A2E, + 0x67505C58, 0x1E008990, 0x1E1E4121, 0x1E2E4921, 0x261B4CB9, 0x658F6121, 0x1A2E674D, 0x10B06753, + 0x40C32210, 0x412122DD, 0x22446058, 0x654E44C7, 0x8AA09AD9, 0x1E200670, 0x677A44CE, 0x61166774, + 0x40D82264, 0x44D62294, 0x44D62234, 0x610526C4, 0x60D9261B, 0x10B0659E, 0x40DF2210, 0x412122DD, + 0x22F46058, 0x108040E9, 0x06303980, 0x58E71E20, 0x222A261B, 0x220A4121, 0x675C40F5, 0x40F52274, + 0x8B018D00, 0x44F51C01, 0x60F58B15, 0x65F28B95, 0x221010B0, 0x22DD40FC, 0x60584121, 0x44FF220A, + 0x10B0674A, 0x41052210, 0x412122DD, 0x66336058, 0x06708AA0, 0x450D1E00, 0x223A677A, 0x22644516, + 0x674A4115, 0x4115221B, 0x412122DD, 0x663C6058, 0x221110B1, 0xC8004120, 0x22BA6740, 0xB0464121, + 0x6121BD43, 0x22CBB042, 0x1E0E413A, 0x8B60413A, 0x413A2220, 0x413A2260, 0xB09CC000, 0x66B8C0CC, + 0x9779644D, 0x9D39B09C, 0x22041A1E, 0x22EA4139, 0x26EA4539, 0x692B6777, 0x2A5B6557, 0x220B1257, + 0x22BA4144, 0xB0464143, 0x614DBD41, 0x414822BA, 0xBD44B046, 0x81401267, 0x81309A50, 0x62539A40, + 0x49601A1E, 0xC0CCB09C, 0x644D66B8, 0xB09C9779, 0x1A1E7000, 0xB09C4960, 0x66B8C0CC, 0x9779644D, + 0x6157B09C, 0xC0108918, 0x416C22A8, 0x66B8C0CC, 0x644DC002, 0x9779B09C, 0x61726964, 0x66B8C0CC, + 0x644DC002, 0x696CB09C, 0x7000675F, 0x13F072A8, 0xC7F09AE0, 0x64419BF0, 0xB0937225, 0x9111C031, + 0x72519191, 0xC0317250, 0x700092C1, 0xB09CCA9A, 0x66B8C0CC, 0x6EA9644D, 0x9439D810, 0x161A6740, + 0xC0107000, 0xC0CCB09C, 0x644D66B8, 0x161A6EA9, 0x8ABA6990, 0x8AA0318A, 0x9D1A000A, 0x7000120A, + 0x45A922F4, 0x45A32294, 0x226426C4, 0x223445F1, 0x2AC441A8, 0x104161D0, 0x78203971, 0x22340401, + 0x262145B0, 0x11021631, 0x6C011421, 0x61D061CD, 0x61CB61CF, 0x61F461D0, 0x61CB6202, 0x61CF6231, + 0x61CB61CF, 0x61D06241, 0x61CB61D0, 0x61CF6231, 0x61CB61D0, 0x61D0624A, 0x261B6202, 0x262A7000, + 0x26C47000, 0x1096654E, 0x3189654E, 0x78310096, 0x41EE1C61, 0x1C608B00, 0x899041E6, 0x41EC1E10, + 0x1C608B80, 0x8BE845EC, 0x45E52284, 0x61EA8B95, 0x22848B68, 0x8B1545EA, 0x70009D06, 0x7000261B, + 0x9D06260A, 0x70007000, 0x42022274, 0x1096654E, 0x3189654E, 0x78310096, 0x42291C61, 0x46001C65, + 0x70006765, 0x7000261B, 0xCA928D05, 0x654E1230, 0x654E1096, 0x00963189, 0x16126E26, 0x78316A05, + 0xC030CA92, 0x1C616D26, 0x16124617, 0x67596A10, 0xCA926229, 0x8B00CB21, 0x461D1C05, 0xCBA1621E, + 0x6D151230, 0x1C656D26, 0x16114600, 0x6A1F1612, 0x67656759, 0x220A7000, 0x6765462C, 0x8B00261A, + 0x67659D00, 0x26C46201, 0x22C47000, 0x654E4368, 0x654E1096, 0x00963189, 0x70006762, 0x423F2294, + 0x22A4268A, 0x654E424A, 0x654E1096, 0x00963189, 0x9AE013E0, 0x7000676E, 0x425222B4, 0x22CB268A, + 0x12704252, 0x6A50654E, 0x22B87000, 0x10B04257, 0x22C89770, 0x8140425B, 0x22E89770, 0x8BF0425F, + 0x22F89770, 0x86404269, 0x39809770, 0x86509770, 0x39809770, 0x86A19770, 0x42700631, 0x18101230, + 0x6A6E9771, 0x46781E82, 0x22208690, 0xC9E64278, 0x265B1292, 0x6D101061, 0x6E101610, 0x1061673A, + 0x1821C972, 0x2410C000, 0xB09D9040, 0x4718225B, 0x66B8C08C, 0x226B676B, 0xA3704694, 0xA071B091, + 0x22A08050, 0x224B4710, 0x62A04710, 0x9190C050, 0xAA80BA81, 0x66B8C01C, 0x223081C0, 0xB097431C, + 0x6348A370, 0x89608951, 0x443B2220, 0x22808D20, 0x890042B0, 0xC6F01801, 0x93911801, 0xC01CB370, + 0xA37066B8, 0x226D6058, 0xB07A46B7, 0x66B8C09C, 0x7000A07A, 0x24C18071, 0x22FA9071, 0x120742BF, + 0x71009D57, 0x28C1805F, 0x220F9071, 0x20CF46EF, 0x896046CE, 0x42D222E0, 0x42D4229F, 0x62F8B099, + 0x24C11201, 0x70009091, 0x46FB229F, 0x4703221F, 0x471022AF, 0x4710224B, 0x42EE22FA, 0x8071B092, + 0x907124C1, 0x80638D52, 0x42E82283, 0x16123317, 0x62E9B0A8, 0x22873117, 0x1A1242EC, 0x62BF9D52, + 0x264B6324, 0x1E1280C2, 0x1E2242FB, 0xB0904720, 0x471022A1, 0x907124C1, 0xB09962BF, 0xB090A079, + 0xCFC2A070, 0x6740C820, 0x263B6328, 0xB82A6771, 0x16108A20, 0xA3709A20, 0xA071B091, 0x6740C830, + 0x6071120E, 0xC840C072, 0x632C6740, 0xC850CFA2, 0x63286740, 0xC860CF92, 0x63286740, 0xC870CFB2, + 0x63286740, 0xC880CFE2, 0x63286740, 0xC890CFF2, 0x63286740, 0xB8216730, 0x601BB04F, 0xB8206730, + 0x601BB040, 0x9190C050, 0x81C06406, 0x43332230, 0x983272A8, 0x70007207, 0x6E028840, 0x1C01C681, + 0x7000473A, 0x84109420, 0x47412200, 0x7000B400, 0x62EDB010, 0x62EEB010, 0x62EFB010, 0xB0107000, + 0x700062F2, 0x62F5B010, 0xB0107000, 0x700062F8, 0x62FBB010, 0xB0107000, 0x700062FE, 0x6301B010, + 0xB0107000, 0x70006304, 0x6307B010, 0xB0107000, 0x7000630A, 0x630DB010, 0xB0107000, 0x70006310, + 0x6313B010, 0xB0107000, 0x70006316, 0x6319B010, 0xB0107000, 0x7000631C, 0x631FB010, 0x62D27000, + 0x63246310, 0x66B16314, 0x62E4B010, 0xB0106441, 0x66B862E7, 0x62EAB010, 0x000062A0, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x05026004, 0x00190582, 0x66D4C8A0, 0xBA8262DA, 0x229D896D, 0x269B400F, 0x400F22AD, + 0x66E2268B, 0x66E5B079, 0x64957830, 0xC03C72D4, 0xC01C66E8, 0xA37066E8, 0xB097B0F0, 0xB82BB098, + 0x443A229B, 0x4481226B, 0x1A1E8789, 0x66E8C0FC, 0x46E022DF, 0x725064B5, 0x72537252, 0x4431228B, + 0x48461A1E, 0x89816033, 0xC0FC9501, 0x22DF66E8, 0x878946E0, 0x602C64B5, 0x95018981, 0xC0FC8979, + 0x64B566E8, 0x39898979, 0x66E8C0FC, 0x603C64B5, 0x85588547, 0x39879A97, 0x9AB89AA7, 0x9AC83988, + 0xC010CA92, 0x64B56D29, 0x68501612, 0x063186F1, 0x1230405B, 0x87811810, 0xA0F06859, 0x66E8C08C, + 0x66E8C07C, 0x81C0B022, 0x42DE2200, 0x22008120, 0xB04D42DE, 0x406F226B, 0x16108A10, 0xB04C9A10, + 0x8A00607B, 0x9A001610, 0x89601267, 0x447A2280, 0x22701257, 0x607B447A, 0x805064BC, 0x46DC22A0, + 0x46DC224B, 0xC0FC62EB, 0x125966E8, 0xC0FC9469, 0xC02966E8, 0x408B22BB, 0x64B52649, 0x66E8C0FC, + 0x64B51209, 0x66E8C0FC, 0x64B58AD9, 0xC0216046, 0x91919111, 0xB3709390, 0x72507251, 0x92C1C051, + 0x44B4226B, 0x269B268B, 0x22908960, 0x2A9B44B4, 0x44B422A0, 0x87CE2A8B, 0x180E8780, 0x40B31E00, + 0x1E501A10, 0x87814EDE, 0x1A1E68B1, 0x95697000, 0x1E0184D1, 0x859944B6, 0x70009469, 0x6E078840, + 0x1C01C681, 0x700044BC, 0x66D4C8B0, 0x8AB18AA0, 0x22301204, 0x260440CA, 0x40CD2240, 0x22502614, + 0x262440D0, 0x40D32260, 0x31412634, 0x64E9C000, 0xC0000004, 0x22018AB1, 0x264440DC, 0x40DF2211, + 0x64E92654, 0x00043130, 0x89A76587, 0x654B8B68, 0x64FC659B, 0x39617000, 0x16310631, 0x14211102, + 0x60F36C01, 0x60F860F5, 0x266060FA, 0x264A7000, 0x7000261B, 0x70002670, 0x70002680, 0xC02010E1, + 0x45012244, 0x22641610, 0x16204504, 0x41072274, 0x22841620, 0x1680410A, 0x450F2294, 0x450F2234, + 0x22A41620, 0x16204112, 0x411522B4, 0x1C011680, 0x261B5918, 0x8B687000, 0x654489A7, 0x5D201C10, + 0x61258B00, 0x65448BE8, 0x5D271C10, 0x9D008B80, 0x26AA6130, 0x7000261B, 0x1C106544, 0x269A5930, + 0x6141261B, 0x8B0089A7, 0x1C018D01, 0x61374536, 0x654B3987, 0x1E020472, 0x26AA453E, 0x6141261B, + 0x66D4C8C0, 0xC8D06143, 0x700066D4, 0x39801080, 0x8AB10630, 0x06313941, 0x12027000, 0x06708AA0, + 0x11011630, 0x6C001410, 0x6162615A, 0x617A616E, 0x617F617F, 0x617F617F, 0x417F2207, 0x22642602, + 0x2294417F, 0x6180457F, 0x417F2217, 0x22942612, 0x22644169, 0x2264457F, 0x22784180, 0x6180417F, + 0x45742227, 0x22808D20, 0x617F4574, 0x22642622, 0x2294417F, 0x6180417F, 0x417F2237, 0x26CB2632, + 0x261B6165, 0x418622BA, 0x45862222, 0xBD42B046, 0x8AB17000, 0x06313941, 0x11021631, 0x6C011421, + 0x61946192, 0x61986196, 0x700026D4, 0x700026E4, 0x700026F4, 0x261B269A, 0x22027000, 0xC8E041A0, + 0x61B166D4, 0x41A52212, 0x66D4C8F0, 0x222261B1, 0xC90041AA, 0x61B166D4, 0x41AF2232, 0x66D4C910, + 0xC92061B1, 0x700066D4, 0x892010E1, 0x16211401, 0xC00097B1, 0x97799770, 0xCAA17000, 0x6D12C010, + 0x16119772, 0x700069BD, 0xC7F181D0, 0x41C71C10, 0x70009BF0, 0x9AA08D10, 0x9AB03980, 0x12827000, + 0x8520C9F6, 0x1E008531, 0x1E0145E1, 0xB82845E1, 0x10B12A0B, 0x45EA2211, 0x9A308BF0, 0x9A618641, + 0x9A718651, 0xB8297000, 0x66D4C930, 0x2278C9B6, 0x129241E8, 0x7000260B, 0x2288C9C6, 0x129241EE, + 0x9D067000, 0x8B001205, 0x1C608B68, 0x899241F9, 0x45FB1E12, 0x8B156200, 0x8B806200, 0x46001C60, + 0x8B958BE8, 0x22781082, 0x8AA2420C, 0x22020672, 0x2264420C, 0x1C60420C, 0x261B421A, 0x06728AA2, + 0x46171E02, 0x1A12C002, 0x42271C20, 0x421A1C60, 0x1E05261B, 0x6225461A, 0x42282264, 0x8D008B01, + 0x46221C10, 0x62237813, 0x9AC37823, 0x267A6228, 0x263A7000, 0x220B7000, 0x89904661, 0x42611E00, + 0x4661221B, 0x42612224, 0x4236222B, 0x62378BE2, 0x22228B62, 0x8D104261, 0x22000670, 0x22204261, + 0x22F44661, 0x22844661, 0x62464244, 0x4661220A, 0x4661221A, 0x2ABB266B, 0x1E418D31, 0x26DA464E, + 0x425A2242, 0x46562262, 0x425E228A, 0x425A2262, 0x426122DA, 0x425E228A, 0x425D2252, 0x626126BB, + 0x426122CA, 0x700026BB, 0xC40CCC02, 0x8D078AC3, 0xC000C001, 0x16236271, 0x1CC11611, 0xC0F04283, + 0x46710410, 0x6D251612, 0x42692005, 0x1C756D35, 0x16134669, 0x16136D35, 0x466A1C65, 0x16429AE1, + 0x20036D23, 0x26CA4282, 0x13F17000, 0x268A9AE1, 0x223B7000, 0x8D204292, 0x429B2280, 0xBD40B046, + 0x2A8026BA, 0x629B9D20, 0x22808D20, 0x26BA429B, 0x1E018991, 0x2A80469B, 0x70009D20, 0x429F1E0E, + 0x8D20261B, 0x42AE2280, 0x42AA2290, 0x0410CFF1, 0x1C108AD1, 0x261B42AA, 0x2A808D20, 0x26BA9D20, + 0xC0017000, 0x22521092, 0x164146B4, 0x06323932, 0x46B91E02, 0x1E1262C2, 0x161146BD, 0x1E2262C2, + 0x165146C1, 0x169162C2, 0x1C1E1611, 0x10105EC6, 0x8B607000, 0x22F43980, 0x1E2042CE, 0x261B5AD3, + 0x42D322E4, 0x5AD31E10, 0x7000261B, 0x84109420, 0x46D52200, 0x7000B400, 0x637DA010, 0x637EA010, + 0x637FA010, 0x6380A010, 0x6381A010, 0xA0107000, 0x70006384, 0x6387A010, 0xA0107000, 0x6007638A, + 0x652A6011, 0x634CA010, 0xA01064C2, 0x65B2634F, 0x6352A010, 0xA01065BB, 0x65C26355, 0x6358A010, + 0xA01065C8, 0x6519635B, 0x635EA010, 0xA01065CD, 0x65EF6361, 0x6364A010, 0xA010661C, 0x661A6367, + 0x636AA010, 0xA0106629, 0x6662636D, 0x6370A010, 0xA0106687, 0x669C6373, 0x6376A010, 0xA01066AF, + 0x66C76379, 0x637CA010 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5.h new file mode 100644 index 00000000..71fc829b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:01 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble5 --fwdesc CC2340R5 LRF firmware for rfe, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/rfe_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/lrf_rfe_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/rfe_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_BLE5_C +#define _LRF_RFE_BINARY_BLE5_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_BLE5_LENGTH 864 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ble5[LRF_RFE_BINARY_BLE5_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c new file mode 100644 index 00000000..a1aca87f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:01 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble5 --fwdesc CC2340R5 LRF firmware for rfe, mode ble5 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/rfe_ble5_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/lrf_rfe_binary_ble5.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5/rfe_ble5_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ble5.h" + +const uint32_t LRF_RFE_binary_ble5[LRF_RFE_BINARY_BLE5_LENGTH] = { + 0x0000035F, 0x00006011, 0x0E700E00, 0x0FF00EF0, 0x0FF30FF1, 0x0FFF0FF7, 0x0BFF0DFF, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB1526648, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0xEFF03942, + 0x980297F1, 0x16316663, 0x14101100, 0x602D6C00, 0x6032602D, 0x60436038, 0x602D6049, 0x6255602D, + 0x62556465, 0x6255644D, 0x6450644D, 0x62556453, 0x62556456, 0x4C401E22, 0x64656456, 0x62556459, + 0x62556553, 0x65536456, 0x645C603C, 0x8040645F, 0x44492200, 0x644B6255, 0x64626251, 0xB0107000, + 0x70006023, 0x6026B010, 0xB0107000, 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, + 0xB0107000, 0x70006035, 0x6038B010, 0x72167000, 0xC7F0B183, 0x65349870, 0x8190A064, 0x44722200, + 0x22008040, 0x606A4524, 0xB084B064, 0xB0608229, 0x22418131, 0x826244FC, 0x102F06F2, 0x142F311F, + 0xC0108266, 0x6F0D1420, 0x398A826A, 0x827006FA, 0x39803180, 0x180BC00B, 0x10BC921B, 0x889318AC, + 0x149B1439, 0x06F08260, 0x31101001, 0x82211410, 0x140C1410, 0x39408280, 0x100206F0, 0x3001C011, + 0x1801C010, 0x31821802, 0x26C10021, 0xCFE09251, 0x82806663, 0x06F03980, 0xC0111002, 0xC0103001, + 0x18021801, 0x00213182, 0x924126C1, 0x39478287, 0xB0033987, 0xB023B002, 0xA062B022, 0x8041A063, + 0x45242201, 0x40BD2231, 0x97408860, 0x1CB58755, 0xB2004CE1, 0xB06EB08E, 0x22017100, 0x80414524, + 0x44D422E1, 0x22108190, 0x606544FA, 0xA2008755, 0x8864A06E, 0x87549744, 0x1C751845, 0x81904CE1, + 0x40C72210, 0x984D60FA, 0x22008180, 0x22C644F1, 0x826140F1, 0x39513981, 0x81603181, 0x39803180, + 0x91610001, 0x989FB180, 0x14F98229, 0x22008190, 0x22104065, 0x613844FA, 0x6663CFD0, 0xA06EA200, + 0xB083A063, 0x06F08280, 0xC0111002, 0xC0103001, 0x18021801, 0x00213182, 0x925126C1, 0xB003B023, + 0xB063B083, 0xB064B084, 0x80417100, 0x45242201, 0xB084B083, 0x22108190, 0x22404065, 0x88614512, + 0x87519741, 0x98711891, 0x6112B1E1, 0xA180A183, 0xA003A200, 0xC7F0A063, 0x70009870, 0x6534A180, + 0x88958229, 0xD4001459, 0x60C76932, 0x39428262, 0x623F06F2, 0x80418290, 0x45242201, 0x97448864, + 0x18958755, 0x81919875, 0x44FA2211, 0x80416939, 0x45242201, 0x97448864, 0x1CC58755, 0x1895492C, + 0x81909875, 0x41452210, 0x721860FA, 0x82627216, 0x06F23942, 0xB183663F, 0x8190A064, 0x45622200, + 0x22008040, 0x615A4634, 0xA040A183, 0x8260827D, 0x0410C0F1, 0x826A1009, 0x041A394A, 0x39808260, + 0x100E0410, 0x10BC10AB, 0x663F10C2, 0x6663CFC0, 0xB003B023, 0xB06365F9, 0xB064B060, 0xB023B084, + 0x65E265D9, 0x80417100, 0x46342201, 0x22108190, 0xB084458E, 0x41802231, 0x65FFB083, 0x618065B2, + 0x887FB084, 0x3D8F318F, 0x97FFDFB0, 0x71006663, 0x22018041, 0xB0844634, 0x22108190, 0xB08341A7, + 0x22C18261, 0x65FF45A2, 0x22D18261, 0x65B24595, 0x88716195, 0x31818882, 0x31823D81, 0xEFA03D82, + 0x980297F1, 0x61536663, 0x97408860, 0x18D38753, 0x0BF34DBF, 0x1CE31613, 0x974349D8, 0x143B8763, + 0x1CE361C4, 0x974349D8, 0x183B8763, 0x4DD41CAB, 0x49D61C9B, 0x41D81CBC, 0x826010B2, 0x41D122D0, + 0x22108190, 0x663F45D8, 0x61D865D9, 0x61C810AB, 0x61C8109B, 0x82807000, 0x0410C0F1, 0x7100B083, + 0x10BC69DC, 0x7000B180, 0x97428862, 0x88918752, 0x82211812, 0x82911812, 0x3D813181, 0x49F01C12, + 0xB1E2B182, 0x1421C7F1, 0xC8124DF4, 0x98829872, 0xB181B1E1, 0x12087000, 0xC7F0C006, 0x98809870, + 0x88917000, 0x97408860, 0x18108750, 0x18108221, 0x81811406, 0x31828292, 0x1C203D82, 0xB1824A13, + 0x46172221, 0xCF90B1E2, 0x22216663, 0xA1824217, 0x8281B1E2, 0xC0F03941, 0x1E010401, 0x16184225, + 0x3010C010, 0x46331C08, 0x3C101060, 0xC7F11006, 0x4E291461, 0x9876C816, 0x31818881, 0x1C163D81, + 0x98864A30, 0xC006B1E1, 0x70001208, 0x8891A183, 0x31828872, 0xEF803D82, 0x980297F1, 0xA0036663, + 0xC0107000, 0x6F031420, 0x10209843, 0x14023112, 0x70009892, 0x73097308, 0x72077206, 0x721C7218, + 0x9870C7F0, 0x66487000, 0xB1E0B150, 0x6648625D, 0xB1E0B150, 0x1E508120, 0xB0804414, 0xB153644B, + 0x66486014, 0xB1E0B151, 0x97E06014, 0x220087D0, 0xB7C04668, 0x00007000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6011A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x604FA010, 0xA01064F4, 0x64E06052, 0x6055A010, 0xA010646C, + 0x646E6058, 0x605BA010, 0xA0106509, 0x6537605E, 0x6061A010, 0xA010664C, 0x78E86064, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666E, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668AA350, 0x700066A6, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x70006669, 0xA39FA2F1, 0xC2F0668A, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A6, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x80407100, 0x42BA2270, 0x8712B087, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0x7100728F, + 0x22708040, 0xB08742BA, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x80407100, 0x42BA2270, 0x96ADB087, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62B561D2, 0x62B561DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x80407100, 0x42BA2270, 0x86F0B087, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665C7892, 0x78B294A4, 0x94B4665E, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665E78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665C, 0x422722F6, 0xC1C526C4, 0x78C26665, 0xC1D5665E, 0xC1E56665, + 0x66651014, 0x944CA067, 0x782D7100, 0x4639223D, 0x4639227D, 0xA079A3F6, 0x8050A663, 0x42BA2290, + 0x7000B2A0, 0xA2A06164, 0x86D2B661, 0x1EB206F2, 0x70004643, 0x7000A661, 0x61FF79E1, 0xA2A0A660, + 0x223D782D, 0xB821465B, 0x7283B820, 0xA68FA680, 0xA3F6A39F, 0xA3C0A3E0, 0x7000A3D0, 0x39123112, + 0x98F298E1, 0x6A61C060, 0x89348923, 0x26C57000, 0x6E5426A5, 0xC0067000, 0x220D782D, 0x2606426E, + 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x221D782D, 0xB6654279, 0xB664627A, 0x427D222D, 0x2206B683, + 0xB6874280, 0x26C5C1C5, 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA683A685, 0x8660A687, + 0x0410C701, 0x42A51E00, 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x2A508660, 0x96602A40, 0x26C5C1C5, + 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA682B681, 0xB6827251, 0xA687A682, 0xB09CB07C, + 0x22C18051, 0xA07C42AE, 0xA681A05C, 0x80407000, 0x46BA2200, 0x62B57100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll.h new file mode 100644 index 00000000..afad58a8 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble5_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ble5, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/rfe_ble5_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/lrf_rfe_binary_ble5_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/rfe_ble5_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_BLE5_NOPLL_C +#define _LRF_RFE_BINARY_BLE5_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_BLE5_NOPLL_LENGTH 861 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ble5_nopll[LRF_RFE_BINARY_BLE5_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll_cc23x0r5.c new file mode 100644 index 00000000..a2ac58bd --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble5_nopll_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble5_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ble5, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/rfe_ble5_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/lrf_rfe_binary_ble5_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble5_nopll/rfe_ble5_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ble5_nopll.h" + +const uint32_t LRF_RFE_binary_ble5_nopll[LRF_RFE_BINARY_BLE5_NOPLL_LENGTH] = { + 0x0000035C, 0x00006011, 0x0E700E00, 0x0FF00EF0, 0x0FF30FF1, 0x0FFF0FF7, 0x0BFF0DFF, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB1526648, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0xEFF03942, + 0x980297F1, 0x16316663, 0x14101100, 0x602D6C00, 0x6032602D, 0x60436038, 0x602D6049, 0x6255602D, + 0x62556465, 0x6255644D, 0x6450644D, 0x62556453, 0x62556456, 0x4C401E22, 0x64656456, 0x62556459, + 0x62556553, 0x65536456, 0x645C603C, 0x8040645F, 0x44492200, 0x644B6255, 0x64626251, 0xB0107000, + 0x70006023, 0x6026B010, 0xB0107000, 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, + 0xB0107000, 0x70006035, 0x6038B010, 0x72167000, 0xC7F0B183, 0x65349870, 0x8190A064, 0x44722200, + 0x22008040, 0x606A4524, 0xB084B064, 0xB0608229, 0x22418131, 0x826244FC, 0x102F06F2, 0x142F311F, + 0xC0108266, 0x6F0D1420, 0x398A826A, 0x827006FA, 0x39803180, 0x180BC00B, 0x10BC921B, 0x889318AC, + 0x149B1439, 0x06F08260, 0x31101001, 0x82211410, 0x140C1410, 0x39408280, 0x100206F0, 0x3001C011, + 0x1801C010, 0x31821802, 0x26C10021, 0xCFE09251, 0x82806663, 0x06F03980, 0xC0111002, 0xC0103001, + 0x18021801, 0x00213182, 0x924126C1, 0x39478287, 0xB0033987, 0xB023B002, 0xA062B022, 0x8041A063, + 0x45242201, 0x40BD2231, 0x97408860, 0x1CB58755, 0xB2004CE1, 0xB06EB08E, 0x22017100, 0x80414524, + 0x44D422E1, 0x22108190, 0x606544FA, 0xA2008755, 0x8864A06E, 0x87549744, 0x1C751845, 0x81904CE1, + 0x40C72210, 0x984D60FA, 0x22008180, 0x22C644F1, 0x826140F1, 0x39513981, 0x81603181, 0x39803180, + 0x91610001, 0x989FB180, 0x14F98229, 0x22008190, 0x22104065, 0x613844FA, 0x6663CFD0, 0xA06EA200, + 0xB083A063, 0x06F08280, 0xC0111002, 0xC0103001, 0x18021801, 0x00213182, 0x925126C1, 0xB003B023, + 0xB063B083, 0xB064B084, 0x80417100, 0x45242201, 0xB084B083, 0x22108190, 0x22404065, 0x88614512, + 0x87519741, 0x98711891, 0x6112B1E1, 0xA180A183, 0xA003A200, 0xC7F0A063, 0x70009870, 0x6534A180, + 0x88958229, 0xD4001459, 0x60C76932, 0x39428262, 0x623F06F2, 0x80418290, 0x45242201, 0x97448864, + 0x18958755, 0x81919875, 0x44FA2211, 0x80416939, 0x45242201, 0x97448864, 0x1CC58755, 0x1895492C, + 0x81909875, 0x41452210, 0x721860FA, 0x82627216, 0x06F23942, 0xB183663F, 0x8190A064, 0x45622200, + 0x22008040, 0x615A4634, 0xA040A183, 0x8260827D, 0x0410C0F1, 0x826A1009, 0x041A394A, 0x39808260, + 0x100E0410, 0x10BC10AB, 0x663F10C2, 0x6663CFC0, 0xB003B023, 0xB06365F9, 0xB064B060, 0xB023B084, + 0x65E265D9, 0x80417100, 0x46342201, 0x22108190, 0xB084458E, 0x41802231, 0x65FFB083, 0x618065B2, + 0x887FB084, 0x3D8F318F, 0x97FFDFB0, 0x71006663, 0x22018041, 0xB0844634, 0x22108190, 0xB08341A7, + 0x22C18261, 0x65FF45A2, 0x22D18261, 0x65B24595, 0x88716195, 0x31818882, 0x31823D81, 0xEFA03D82, + 0x980297F1, 0x61536663, 0x97408860, 0x18D38753, 0x0BF34DBF, 0x1CE31613, 0x974349D8, 0x143B8763, + 0x1CE361C4, 0x974349D8, 0x183B8763, 0x4DD41CAB, 0x49D61C9B, 0x41D81CBC, 0x826010B2, 0x41D122D0, + 0x22108190, 0x663F45D8, 0x61D865D9, 0x61C810AB, 0x61C8109B, 0x82807000, 0x0410C0F1, 0x7100B083, + 0x10BC69DC, 0x7000B180, 0x97428862, 0x88918752, 0x82211812, 0x82911812, 0x3D813181, 0x49F01C12, + 0xB1E2B182, 0x1421C7F1, 0xC8124DF4, 0x98829872, 0xB181B1E1, 0x12087000, 0xC7F0C006, 0x98809870, + 0x88917000, 0x97408860, 0x18108750, 0x18108221, 0x81811406, 0x31828292, 0x1C203D82, 0xB1824A13, + 0x46172221, 0xCF90B1E2, 0x22216663, 0xA1824217, 0x8281B1E2, 0xC0F03941, 0x1E010401, 0x16184225, + 0x3010C010, 0x46331C08, 0x3C101060, 0xC7F11006, 0x4E291461, 0x9876C816, 0x31818881, 0x1C163D81, + 0x98864A30, 0xC006B1E1, 0x70001208, 0x8891A183, 0x31828872, 0xEF803D82, 0x980297F1, 0xA0036663, + 0xC0107000, 0x6F031420, 0x10209843, 0x14023112, 0x70009892, 0x73097308, 0x72077206, 0x721C7218, + 0x9870C7F0, 0x66487000, 0xB1E0B150, 0x6648625D, 0xB1E0B150, 0x1E508120, 0xB0804414, 0xB153644B, + 0x66486014, 0xB1E0B151, 0x97E06014, 0x220087D0, 0xB7C04668, 0x00007000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6011A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x604FA010, 0xA01064F4, 0x64E06052, 0x6055A010, 0xA010646C, + 0x646E6058, 0x605BA010, 0xA0106509, 0x6537605E, 0x6061A010, 0xA010664D, 0x78E86064, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666F, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668BA350, 0x700066A7, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x7000666A, 0xA39FA2F1, 0xC2F0668B, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A7, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x6965C170, 0x22008040, 0x871246B4, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0xC170728F, + 0x8040698E, 0x46B42200, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x69AFC170, 0x22008040, 0x96AD46B4, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62AF61D2, 0x62AF61DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x69F3C2F0, 0x22008040, 0x86F046B4, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665D7892, 0x78B294A4, 0x94B4665F, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665F78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665D, 0x422722F6, 0xC1C526C4, 0x78C26666, 0xC1D5665F, 0xC1E56666, + 0x66661014, 0x944CA067, 0x6A33D370, 0x223D782D, 0x227D463A, 0xA3F6463A, 0xA663A079, 0x22008040, + 0xB2A046B4, 0x61647000, 0xB661A2A0, 0x06F286D2, 0x46441EB2, 0xA6617000, 0x79E17000, 0xA66061FF, + 0x782DA2A0, 0x465C223D, 0xB820B821, 0xA6807283, 0xA39FA68F, 0xA3E0A3F6, 0xA3D0A3C0, 0x31127000, + 0x98E13912, 0xC06098F2, 0x89236A62, 0x70008934, 0x26A526C5, 0x70006E54, 0x782DC006, 0x426F220D, + 0x84A42606, 0x79C084B3, 0x94A079D1, 0x782D94B1, 0x427A221D, 0x627BB665, 0x222DB664, 0xB683427E, + 0x42812206, 0xC1C5B687, 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xA6857000, 0xA687A683, + 0xC7018660, 0x1E000410, 0x84A442A6, 0x79C084B3, 0x94A079D1, 0x866094B1, 0x2A402A50, 0xC1C59660, + 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xB6817000, 0x7251A682, 0xA682B682, 0xA681A687, + 0x80407000, 0x46B42200, 0x62AF7100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs.h new file mode 100644 index 00000000..3324a35d --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble_cs --fwdesc CC2340R5 LRF firmware for rfe, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/rfe_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/lrf_rfe_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/rfe_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_BLE_CS_C +#define _LRF_RFE_BINARY_BLE_CS_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_BLE_CS_LENGTH 869 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ble_cs[LRF_RFE_BINARY_BLE_CS_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_cc23x0r5.c new file mode 100644 index 00000000..8b0b104e --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_cc23x0r5.c @@ -0,0 +1,123 @@ +// This code snippet was auto-generated on Thu May 23 12:10:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble_cs --fwdesc CC2340R5 LRF firmware for rfe, mode ble_cs /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/rfe_ble_cs_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/lrf_rfe_binary_ble_cs.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs/rfe_ble_cs_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ble_cs.h" + +const uint32_t LRF_RFE_binary_ble_cs[LRF_RFE_BINARY_BLE_CS_LENGTH] = { + 0x00000364, 0x00006042, 0x0E700E00, 0x0FF00EF0, 0x0FF30FF1, 0x0FFF0FF7, 0x0BFF0DFF, 0x07FF09FF, + 0x03FF05FF, 0x096201FF, 0x00000000, 0x00008A0A, 0xCCCD0000, 0x3333006C, 0x383C001B, 0x00000000, + 0x00000000, 0x05020201, 0x1F150D08, 0x624E3C2C, 0xAD9D8A76, 0xCCC9C2B9, 0x3B2C0000, 0x8975614E, + 0xC0B7AB9B, 0x0000CAC7, 0x604D3B2B, 0xA9998774, 0xC8C5BEB5, 0x1308151F, 0x00001307, 0x00000000, + 0x0A8C0380, 0x00F07FFF, 0x66DD7215, 0xB060B152, 0x00007100, 0x81217215, 0xA060B080, 0x101206F1, + 0x11011632, 0x6C011421, 0x62366236, 0x62366236, 0x627D6265, 0x605A6094, 0x26C1C021, 0x6D1226A1, + 0x26326D12, 0x814B6E12, 0x6696398B, 0x66996647, 0x66907251, 0x6696606C, 0x66996647, 0x8262C00A, + 0x60713942, 0x66B38262, 0x7C117277, 0xB0819791, 0xB770B061, 0x72777100, 0xA061B081, 0xB0887216, + 0x7100B068, 0xA068B088, 0x1E1A161A, 0x1A1B4070, 0x408A1E0B, 0x6069669F, 0x26C1C021, 0x6D1226A1, + 0x2A326D12, 0x66936E12, 0x627F669F, 0x813166AD, 0x1EB106F1, 0x1A51449A, 0x101A1A21, 0x449F2221, + 0x101066D6, 0xA26E0630, 0x44A51E00, 0x1E01B26E, 0x067140AC, 0x4CAC1A41, 0x60AE65AD, 0x65A9C002, + 0x222A658E, 0x669040B5, 0xB18366A2, 0x668760B6, 0x7100B064, 0x22408040, 0xB08440B6, 0x8190A064, + 0x16411101, 0x6C011401, 0x60D260C2, 0x60D760DE, 0x60E760E4, 0x60EB60E9, 0x612E60ED, 0x60B660B6, + 0x60B660B6, 0x60B660B6, 0x79307962, 0x66271402, 0x222A6122, 0x795244DD, 0x14027930, 0x61226627, + 0x6690668D, 0xB18366A2, 0x60B66624, 0x66876693, 0x66936122, 0x668D6124, 0xA0036124, 0x7B906122, + 0xB0039250, 0xB083B023, 0x7C03B063, 0xC005C004, 0x8290C006, 0x1A101007, 0x88617100, 0x92527BA2, + 0x49011C13, 0x1C141013, 0x10144D04, 0x5D071415, 0xB0831616, 0xA00368FA, 0x98D6B083, 0x98E798C5, + 0xB066728F, 0x91A37100, 0x7100B086, 0xB08691A4, 0x6917C040, 0x71008905, 0xB08691A5, 0x7100657B, + 0xB08691A1, 0x60B6A066, 0x60B67218, 0x95107960, 0x8170A26D, 0x452C2200, 0xB26DB26C, 0x627F7218, + 0x7B80C003, 0xB0039250, 0x7BE0B023, 0xB7739770, 0x65646539, 0xB06460EB, 0x7100B063, 0x22408040, + 0x22304560, 0xB0834139, 0x7BF18860, 0x49521C10, 0x22E28262, 0x22D24152, 0x22C24152, 0xA26C4152, + 0xB18366B3, 0x6139C003, 0x41551E33, 0x7BD01613, 0xC3B27BC1, 0x6E2126C2, 0x6E201612, 0x88601612, + 0x61396E20, 0xB083A773, 0x7000A063, 0xC60187A0, 0x87B11810, 0x496E1810, 0x49761E23, 0x61717BD5, + 0x49761E33, 0x7BC17BB5, 0x39151415, 0x6177657B, 0x9871C801, 0xB7749881, 0x97457000, 0x88908751, + 0x82201801, 0xC7F01801, 0x14021012, 0xC8014D86, 0x85117000, 0xC1317000, 0x6D1226C1, 0x70006D12, + 0x10A27941, 0x1E020672, 0x38214195, 0x22013821, 0x79544199, 0x7964619A, 0x14047930, 0x41A02211, + 0x61A17953, 0x14037963, 0x26C1C0E1, 0x6E1326A1, 0x6E141611, 0xC1317000, 0x6E1226C1, 0x81B27000, + 0xB08681D3, 0x45B41E03, 0x7000C002, 0x10211204, 0x41BB22F1, 0x16110BF1, 0x3113C014, 0x31131431, + 0x3D8198C1, 0x98D13D71, 0x728F98E3, 0x69C5C100, 0x10238902, 0x41CC2204, 0x16120BF2, 0x1E0391A2, + 0xC00141DE, 0x265198C1, 0x98E398D1, 0xC100728F, 0x890369D6, 0x22458915, 0x225545DE, 0x61E045DE, + 0x13F513F3, 0x91C565A9, 0x700091A3, 0x79A17990, 0xC3F28403, 0x1E330423, 0x797041ED, 0x98C07981, + 0x85F198D1, 0x98E1728F, 0x69F3C140, 0x0BF18901, 0xC1521611, 0x6E2126C2, 0x81407000, 0x31101001, + 0x14103121, 0x141079B1, 0x91603920, 0xC5217000, 0x1612C1D2, 0x661EC0B0, 0x81407000, 0x1801C1D1, + 0xC3714E1D, 0x4A181801, 0x1612C2A2, 0xC050C581, 0x621D661E, 0x1612C312, 0xC050C581, 0x7000661E, + 0x6E136F23, 0x16121611, 0x70006A1E, 0xB023B003, 0x86817000, 0xA682B681, 0xB6829512, 0x7000A681, + 0x7100B064, 0x22408040, 0xA064422E, 0x7000B084, 0x6687627F, 0x6687627F, 0x668D668A, 0x66906240, + 0x6693627F, 0xC0528120, 0x1E509152, 0x669F467F, 0x7915627F, 0xC7F18140, 0x14050410, 0x10509635, + 0x96203910, 0xC3F08401, 0x10500401, 0x42591E31, 0x467C1EC1, 0x725E3120, 0x840295F0, 0xC3F33982, + 0x1C310423, 0x31104262, 0x96107260, 0x66967000, 0x66996647, 0x65E466BD, 0x660565FB, 0xC050660B, + 0x26A026C0, 0x6D016D01, 0x728C98D1, 0x8040669C, 0x467D2200, 0x220082A0, 0x627F427C, 0x669F6283, + 0x66DD627F, 0xB1E0B150, 0x66DD6045, 0xB1E0B151, 0xB0106045, 0x70006023, 0x6026B010, 0xB0107000, + 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, 0x6038B010, + 0xB0107000, 0x7000603B, 0x22C28262, 0x394242A6, 0x814262B3, 0x627F66B3, 0x7100B060, 0xC7F0627F, + 0x98809870, 0x92507B80, 0x06F27000, 0x1420C010, 0x98436F03, 0x31121020, 0x98921402, 0x81317000, + 0x46D52291, 0x22F382B3, 0x2AF342C5, 0xC1A162CF, 0x26A126C1, 0x6D126D12, 0x82D0DFF1, 0x00200410, + 0x82E092D0, 0x0410C1F1, 0x92E00030, 0x7000B2D8, 0xB83FB2F0, 0xB834B83E, 0xB2F1B835, 0x73087000, + 0x72067309, 0x72187207, 0xC7F0721C, 0x70009870, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6042A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64890000, 0x6289A010, 0xA01064FD, 0x64E9628C, 0x628FA010, 0xA010646F, + 0x64716292, 0x6295A010, 0xA0106512, 0x65406298, 0x629BA010, 0xA0106649, 0x6655629E, 0x62A1A010, + 0x951878E8, 0x40451E08, 0xB682B681, 0xA327A682, 0x7000B2D8, 0xB811B2C0, 0xB360B2D0, 0xC470B350, + 0xB83F684E, 0xB83EB83D, 0xB833B839, 0xA822B832, 0xB318B319, 0x6859C660, 0xB325B326, 0x782DB327, + 0x4061224D, 0xB343B685, 0x6863C0F0, 0xC130A343, 0xA8236866, 0x7820B824, 0x446D2260, 0x6677B39F, + 0x643E7000, 0xA8246048, 0xA39FB823, 0xA319B822, 0xA327A318, 0xA326A325, 0xA83FA839, 0xA83EA83D, + 0xA832A833, 0xA811A2C0, 0xA2D8A2D0, 0xA350A360, 0x66AF6693, 0x78F17000, 0xB6819511, 0xA681B682, + 0x228182D1, 0x82B344A0, 0x409622F3, 0x60982AF3, 0x64F779A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, + 0x689FC470, 0xB810B2F0, 0x22507820, 0x64A844A6, 0x700064BD, 0xB064B060, 0x80407100, 0x44B72240, + 0x40A82200, 0x8121B080, 0x40B61E11, 0x44A81E51, 0xA0647000, 0x8190B084, 0x40A82200, 0x81217000, + 0x40E81E11, 0x40E81E51, 0xB83EB83F, 0xB835B834, 0x221082F0, 0xB2F144CC, 0x68CBC2F0, 0x22607820, + 0xB39F44D0, 0x22507820, 0xB06044E1, 0x7100B064, 0xB084A064, 0x22108190, 0x812144E1, 0x40E81E11, + 0x40E81E51, 0x782D60D4, 0x40E5224D, 0xC170B685, 0x667268E6, 0xA2F17000, 0x6693A39F, 0x68EDC2F0, + 0xA810A2F0, 0xA83FA2D8, 0xA834A83E, 0x66AFA835, 0xDFF179B2, 0x041082D0, 0x92D00020, 0x81217000, + 0x410D1E11, 0x410D1E51, 0xB064B060, 0x80407100, 0x410E2240, 0xB084A064, 0x22018191, 0x70004502, + 0x41022200, 0x60FDB080, 0x96B086A0, 0x31803980, 0x3141C081, 0x26010001, 0xC80096A1, 0x04018661, + 0xA2A09661, 0x22F08680, 0x70004124, 0x8681C400, 0x96810401, 0x93C07940, 0x93B07920, 0xB3E0B3F6, + 0xB3D0B3C0, 0x69317970, 0x69337980, 0xA821A820, 0xB830B68F, 0x69397990, 0x93B07930, 0x26007950, + 0x700093C0, 0x844A813E, 0xCF0910AC, 0x089E049E, 0x944A00EA, 0x454D227A, 0x260086B0, 0xB83C96A0, + 0xB680B838, 0xC8008661, 0x78300401, 0x26010001, 0xB0679661, 0xB079B087, 0xB060B099, 0x7850728C, + 0xC02098D0, 0xA6A06960, 0x41F3225E, 0x3180C400, 0xB6A396B0, 0x8130C0FF, 0x416D2280, 0x71007000, + 0x22708040, 0xB08742C3, 0x87208712, 0x100A3940, 0x040F8720, 0x1A8D10AD, 0x00FD314D, 0x02BD314D, + 0xC00D96AD, 0x96BD318D, 0xA447A660, 0xB660A446, 0xC3C01025, 0x10AD1405, 0x314D168D, 0x314D00FD, + 0xC7F802BD, 0x10233188, 0x18037840, 0x728F98E3, 0x80407100, 0x42C32270, 0x8713B087, 0x96B896AD, + 0xB660A660, 0xC3C01036, 0xC0091406, 0x18681028, 0x260949A8, 0x18581038, 0x261949AC, 0x10ADC3C8, + 0x00FD314D, 0x023D314D, 0x94608900, 0x7850728C, 0x710098D0, 0x22708040, 0xB08742C3, 0x871496AD, + 0x14871047, 0xA445A660, 0x1048B662, 0x49C71858, 0x10482619, 0x49CB1868, 0x10382609, 0x49CF1878, + 0x16392629, 0x14901100, 0x61DB6C00, 0x61DD61DB, 0x61DB61E1, 0x61E462BE, 0xB66062BE, 0x103961F4, + 0x39191449, 0x104961E7, 0x61E71669, 0x1A691039, 0x784061E7, 0x98E91809, 0x1000728F, 0xB6601000, + 0x69EFC0C0, 0x94608900, 0xB66261F4, 0x224E79E1, 0x78704208, 0x788098C0, 0x710098D0, 0x22708040, + 0xB08742C3, 0x98E086F0, 0x98F08700, 0x1E0088B0, 0x89014604, 0x78927296, 0x94A46665, 0x666778B2, + 0x872094B4, 0x96A03140, 0x26F0C410, 0x04028682, 0x96822642, 0x8662C810, 0x78600402, 0x26320002, + 0x78D29662, 0x22F46667, 0x31144629, 0x422722F3, 0x94742604, 0x7347622A, 0x666578A2, 0x22F678A6, + 0x26C44230, 0x666EC1C5, 0x666778C2, 0x666EC1D5, 0x1014C1E5, 0xA067666E, 0x7100944C, 0x223D782D, + 0x227D4642, 0xA3F64642, 0xA663A079, 0x22908050, 0xB2A042C3, 0x616D7000, 0xB661A2A0, 0x06F286D2, + 0x464C1EB2, 0xA6617000, 0x79E17000, 0xA6606208, 0x782DA2A0, 0x4664223D, 0xB820B821, 0xA6807283, + 0xA39FA68F, 0xA3E0A3F6, 0xA3D0A3C0, 0x31127000, 0x98E13912, 0xC06098F2, 0x89236A6A, 0x70008934, + 0x26A526C5, 0x70006E54, 0x782DC006, 0x4277220D, 0x84A42606, 0x79C084B3, 0x94A079D1, 0x782D94B1, + 0x4282221D, 0x6283B665, 0x222DB664, 0xB6834286, 0x42892206, 0xC1C5B687, 0x26A526C5, 0x10346E54, + 0x26C5C1D5, 0x6E5426A5, 0xA6857000, 0xA687A683, 0xC7018660, 0x1E000410, 0x84A442AE, 0x79C084B3, + 0x94A079D1, 0x866094B1, 0x2A402A50, 0xC1C59660, 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, + 0xB6817000, 0x7251A682, 0xA682B682, 0xB07CA687, 0x8051B09C, 0x42B722C1, 0xA05CA07C, 0x7000A681, + 0x22008040, 0x710046C3, 0xA6A062BE, 0xA6A3A6A1, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll.h new file mode 100644 index 00000000..79a64a39 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble_cs_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ble_cs, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/rfe_ble_cs_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/lrf_rfe_binary_ble_cs_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/rfe_ble_cs_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_BLE_CS_NOPLL_C +#define _LRF_RFE_BINARY_BLE_CS_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_BLE_CS_NOPLL_LENGTH 866 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ble_cs_nopll[LRF_RFE_BINARY_BLE_CS_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c new file mode 100644 index 00000000..f1c96b97 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ble_cs_nopll_cc23x0r5.c @@ -0,0 +1,123 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ble_cs_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ble_cs, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/rfe_ble_cs_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/lrf_rfe_binary_ble_cs_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ble_cs_nopll/rfe_ble_cs_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ble_cs_nopll.h" + +const uint32_t LRF_RFE_binary_ble_cs_nopll[LRF_RFE_BINARY_BLE_CS_NOPLL_LENGTH] = { + 0x00000361, 0x00006042, 0x0E700E00, 0x0FF00EF0, 0x0FF30FF1, 0x0FFF0FF7, 0x0BFF0DFF, 0x07FF09FF, + 0x03FF05FF, 0x096201FF, 0x00000000, 0x00008A0A, 0xCCCD0000, 0x3333006C, 0x383C001B, 0x00000000, + 0x00000000, 0x05020201, 0x1F150D08, 0x624E3C2C, 0xAD9D8A76, 0xCCC9C2B9, 0x3B2C0000, 0x8975614E, + 0xC0B7AB9B, 0x0000CAC7, 0x604D3B2B, 0xA9998774, 0xC8C5BEB5, 0x1308151F, 0x00001307, 0x00000000, + 0x0A8C0380, 0x00F07FFF, 0x66DD7215, 0xB060B152, 0x00007100, 0x81217215, 0xA060B080, 0x101206F1, + 0x11011632, 0x6C011421, 0x62366236, 0x62366236, 0x627D6265, 0x605A6094, 0x26C1C021, 0x6D1226A1, + 0x26326D12, 0x814B6E12, 0x6696398B, 0x66996647, 0x66907251, 0x6696606C, 0x66996647, 0x8262C00A, + 0x60713942, 0x66B38262, 0x7C117277, 0xB0819791, 0xB770B061, 0x72777100, 0xA061B081, 0xB0887216, + 0x7100B068, 0xA068B088, 0x1E1A161A, 0x1A1B4070, 0x408A1E0B, 0x6069669F, 0x26C1C021, 0x6D1226A1, + 0x2A326D12, 0x66936E12, 0x627F669F, 0x813166AD, 0x1EB106F1, 0x1A51449A, 0x101A1A21, 0x449F2221, + 0x101066D6, 0xA26E0630, 0x44A51E00, 0x1E01B26E, 0x067140AC, 0x4CAC1A41, 0x60AE65AD, 0x65A9C002, + 0x222A658E, 0x669040B5, 0xB18366A2, 0x668760B6, 0x7100B064, 0x22408040, 0xB08440B6, 0x8190A064, + 0x16411101, 0x6C011401, 0x60D260C2, 0x60D760DE, 0x60E760E4, 0x60EB60E9, 0x612E60ED, 0x60B660B6, + 0x60B660B6, 0x60B660B6, 0x79307962, 0x66271402, 0x222A6122, 0x795244DD, 0x14027930, 0x61226627, + 0x6690668D, 0xB18366A2, 0x60B66624, 0x66876693, 0x66936122, 0x668D6124, 0xA0036124, 0x7B906122, + 0xB0039250, 0xB083B023, 0x7C03B063, 0xC005C004, 0x8290C006, 0x1A101007, 0x88617100, 0x92527BA2, + 0x49011C13, 0x1C141013, 0x10144D04, 0x5D071415, 0xB0831616, 0xA00368FA, 0x98D6B083, 0x98E798C5, + 0xB066728F, 0x91A37100, 0x7100B086, 0xB08691A4, 0x6917C040, 0x71008905, 0xB08691A5, 0x7100657B, + 0xB08691A1, 0x60B6A066, 0x60B67218, 0x95107960, 0x8170A26D, 0x452C2200, 0xB26DB26C, 0x627F7218, + 0x7B80C003, 0xB0039250, 0x7BE0B023, 0xB7739770, 0x65646539, 0xB06460EB, 0x7100B063, 0x22408040, + 0x22304560, 0xB0834139, 0x7BF18860, 0x49521C10, 0x22E28262, 0x22D24152, 0x22C24152, 0xA26C4152, + 0xB18366B3, 0x6139C003, 0x41551E33, 0x7BD01613, 0xC3B27BC1, 0x6E2126C2, 0x6E201612, 0x88601612, + 0x61396E20, 0xB083A773, 0x7000A063, 0xC60187A0, 0x87B11810, 0x496E1810, 0x49761E23, 0x61717BD5, + 0x49761E33, 0x7BC17BB5, 0x39151415, 0x6177657B, 0x9871C801, 0xB7749881, 0x97457000, 0x88908751, + 0x82201801, 0xC7F01801, 0x14021012, 0xC8014D86, 0x85117000, 0xC1317000, 0x6D1226C1, 0x70006D12, + 0x10A27941, 0x1E020672, 0x38214195, 0x22013821, 0x79544199, 0x7964619A, 0x14047930, 0x41A02211, + 0x61A17953, 0x14037963, 0x26C1C0E1, 0x6E1326A1, 0x6E141611, 0xC1317000, 0x6E1226C1, 0x81B27000, + 0xB08681D3, 0x45B41E03, 0x7000C002, 0x10211204, 0x41BB22F1, 0x16110BF1, 0x3113C014, 0x31131431, + 0x3D8198C1, 0x98D13D71, 0x728F98E3, 0x69C5C100, 0x10238902, 0x41CC2204, 0x16120BF2, 0x1E0391A2, + 0xC00141DE, 0x265198C1, 0x98E398D1, 0xC100728F, 0x890369D6, 0x22458915, 0x225545DE, 0x61E045DE, + 0x13F513F3, 0x91C565A9, 0x700091A3, 0x79A17990, 0xC3F28403, 0x1E330423, 0x797041ED, 0x98C07981, + 0x85F198D1, 0x98E1728F, 0x69F3C140, 0x0BF18901, 0xC1521611, 0x6E2126C2, 0x81407000, 0x31101001, + 0x14103121, 0x141079B1, 0x91603920, 0xC5217000, 0x1612C1D2, 0x661EC0B0, 0x81407000, 0x1801C1D1, + 0xC3714E1D, 0x4A181801, 0x1612C2A2, 0xC050C581, 0x621D661E, 0x1612C312, 0xC050C581, 0x7000661E, + 0x6E136F23, 0x16121611, 0x70006A1E, 0xB023B003, 0x86817000, 0xA682B681, 0xB6829512, 0x7000A681, + 0x7100B064, 0x22408040, 0xA064422E, 0x7000B084, 0x6687627F, 0x6687627F, 0x668D668A, 0x66906240, + 0x6693627F, 0xC0528120, 0x1E509152, 0x669F467F, 0x7915627F, 0xC7F18140, 0x14050410, 0x10509635, + 0x96203910, 0xC3F08401, 0x10500401, 0x42591E31, 0x467C1EC1, 0x725E3120, 0x840295F0, 0xC3F33982, + 0x1C310423, 0x31104262, 0x96107260, 0x66967000, 0x66996647, 0x65E466BD, 0x660565FB, 0xC050660B, + 0x26A026C0, 0x6D016D01, 0x728C98D1, 0x8040669C, 0x467D2200, 0x220082A0, 0x627F427C, 0x669F6283, + 0x66DD627F, 0xB1E0B150, 0x66DD6045, 0xB1E0B151, 0xB0106045, 0x70006023, 0x6026B010, 0xB0107000, + 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, 0x6038B010, + 0xB0107000, 0x7000603B, 0x22C28262, 0x394242A6, 0x814262B3, 0x627F66B3, 0x7100B060, 0xC7F0627F, + 0x98809870, 0x92507B80, 0x06F27000, 0x1420C010, 0x98436F03, 0x31121020, 0x98921402, 0x81317000, + 0x46D52291, 0x22F382B3, 0x2AF342C5, 0xC1A162CF, 0x26A126C1, 0x6D126D12, 0x82D0DFF1, 0x00200410, + 0x82E092D0, 0x0410C1F1, 0x92E00030, 0x7000B2D8, 0xB83FB2F0, 0xB834B83E, 0xB2F1B835, 0x73087000, + 0x72067309, 0x72187207, 0xC7F0721C, 0x70009870, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6042A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64890000, 0x6289A010, 0xA01064FD, 0x64E9628C, 0x628FA010, 0xA010646F, + 0x64716292, 0x6295A010, 0xA0106512, 0x65406298, 0x629BA010, 0xA010664A, 0x6656629E, 0x62A1A010, + 0x951878E8, 0x40451E08, 0xB682B681, 0xA327A682, 0x7000B2D8, 0xB811B2C0, 0xB360B2D0, 0xC470B350, + 0xB83F684E, 0xB83EB83D, 0xB833B839, 0xA822B832, 0xB318B319, 0x6859C660, 0xB325B326, 0x782DB327, + 0x4061224D, 0xB343B685, 0x6863C0F0, 0xC130A343, 0xA8236866, 0x7820B824, 0x446D2260, 0x6678B39F, + 0x643E7000, 0xA8246048, 0xA39FB823, 0xA319B822, 0xA327A318, 0xA326A325, 0xA83FA839, 0xA83EA83D, + 0xA832A833, 0xA811A2C0, 0xA2D8A2D0, 0xA350A360, 0x66B06694, 0x78F17000, 0xB6819511, 0xA681B682, + 0x228182D1, 0x82B344A0, 0x409622F3, 0x60982AF3, 0x64F779A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, + 0x689FC470, 0xB810B2F0, 0x22507820, 0x64A844A6, 0x700064BD, 0xB064B060, 0x80407100, 0x44B72240, + 0x40A82200, 0x8121B080, 0x40B61E11, 0x44A81E51, 0xA0647000, 0x8190B084, 0x40A82200, 0x81217000, + 0x40E81E11, 0x40E81E51, 0xB83EB83F, 0xB835B834, 0x221082F0, 0xB2F144CC, 0x68CBC2F0, 0x22607820, + 0xB39F44D0, 0x22507820, 0xB06044E1, 0x7100B064, 0xB084A064, 0x22108190, 0x812144E1, 0x40E81E11, + 0x40E81E51, 0x782D60D4, 0x40E5224D, 0xC170B685, 0x667368E6, 0xA2F17000, 0x6694A39F, 0x68EDC2F0, + 0xA810A2F0, 0xA83FA2D8, 0xA834A83E, 0x66B0A835, 0xDFF179B2, 0x041082D0, 0x92D00020, 0x81217000, + 0x410D1E11, 0x410D1E51, 0xB064B060, 0x80407100, 0x410E2240, 0xB084A064, 0x22018191, 0x70004502, + 0x41022200, 0x60FDB080, 0x96B086A0, 0x31803980, 0x3141C081, 0x26010001, 0xC80096A1, 0x04018661, + 0xA2A09661, 0x22F08680, 0x70004124, 0x8681C400, 0x96810401, 0x93C07940, 0x93B07920, 0xB3E0B3F6, + 0xB3D0B3C0, 0x69317970, 0x69337980, 0xA821A820, 0xB830B68F, 0x69397990, 0x93B07930, 0x26007950, + 0x700093C0, 0x844A813E, 0xCF0910AC, 0x089E049E, 0x944A00EA, 0x454D227A, 0x260086B0, 0xB83C96A0, + 0xB680B838, 0xC8008661, 0x78300401, 0x26010001, 0xB0679661, 0xB079B087, 0xB060B099, 0x7850728C, + 0xC02098D0, 0xA6A06960, 0x41F3225E, 0x3180C400, 0xB6A396B0, 0x8130C0FF, 0x416D2280, 0xC1707000, + 0x8040696E, 0x46BD2200, 0x87208712, 0x100A3940, 0x040F8720, 0x1A8D10AD, 0x00FD314D, 0x02BD314D, + 0xC00D96AD, 0x96BD318D, 0xA447A660, 0xB660A446, 0xC3C01025, 0x10AD1405, 0x314D168D, 0x314D00FD, + 0xC7F802BD, 0x10233188, 0x18037840, 0x728F98E3, 0x6997C170, 0x22008040, 0x871346BD, 0x96B896AD, + 0xB660A660, 0xC3C01036, 0xC0091406, 0x18681028, 0x260949A8, 0x18581038, 0x261949AC, 0x10ADC3C8, + 0x00FD314D, 0x023D314D, 0x94608900, 0x7850728C, 0xC17098D0, 0x804069B8, 0x46BD2200, 0x871496AD, + 0x14871047, 0xA445A660, 0x1048B662, 0x49C71858, 0x10482619, 0x49CB1868, 0x10382609, 0x49CF1878, + 0x16392629, 0x14901100, 0x61DB6C00, 0x61DD61DB, 0x61DB61E1, 0x61E462B8, 0xB66062B8, 0x103961F4, + 0x39191449, 0x104961E7, 0x61E71669, 0x1A691039, 0x784061E7, 0x98E91809, 0x1000728F, 0xB6601000, + 0x69EFC0C0, 0x94608900, 0xB66261F4, 0x224E79E1, 0x78704208, 0x788098C0, 0xC2F098D0, 0x804069FC, + 0x46BD2200, 0x98E086F0, 0x98F08700, 0x1E0088B0, 0x89014604, 0x78927296, 0x94A46666, 0x666878B2, + 0x872094B4, 0x96A03140, 0x26F0C410, 0x04028682, 0x96822642, 0x8662C810, 0x78600402, 0x26320002, + 0x78D29662, 0x22F46668, 0x31144629, 0x422722F3, 0x94742604, 0x7347622A, 0x666678A2, 0x22F678A6, + 0x26C44230, 0x666FC1C5, 0x666878C2, 0x666FC1D5, 0x1014C1E5, 0xA067666F, 0xD370944C, 0x782D6A3C, + 0x4643223D, 0x4643227D, 0xA079A3F6, 0x8040A663, 0x46BD2200, 0x7000B2A0, 0xA2A0616D, 0x86D2B661, + 0x1EB206F2, 0x7000464D, 0x7000A661, 0x620879E1, 0xA2A0A660, 0x223D782D, 0xB8214665, 0x7283B820, + 0xA68FA680, 0xA3F6A39F, 0xA3C0A3E0, 0x7000A3D0, 0x39123112, 0x98F298E1, 0x6A6BC060, 0x89348923, + 0x26C57000, 0x6E5426A5, 0xC0067000, 0x220D782D, 0x26064278, 0x84B384A4, 0x79D179C0, 0x94B194A0, + 0x221D782D, 0xB6654283, 0xB6646284, 0x4287222D, 0x2206B683, 0xB687428A, 0x26C5C1C5, 0x6E5426A5, + 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA683A685, 0x8660A687, 0x0410C701, 0x42AF1E00, 0x84B384A4, + 0x79D179C0, 0x94B194A0, 0x2A508660, 0x96602A40, 0x26C5C1C5, 0x6E5426A5, 0xC1D51034, 0x26A526C5, + 0x70006E54, 0xA682B681, 0xB6827251, 0xA687A682, 0x7000A681, 0x22008040, 0x710046BD, 0xA6A062B8, + 0xA6A3A6A1, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll.h new file mode 100644 index 00000000..16f7ddb9 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:56 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname coherent_pll --fwdesc CC2340R5 LRF firmware for rfe, mode coherent_pll /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/rfe_coherent_pll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/lrf_rfe_binary_coherent_pll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/rfe_coherent_pll_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_RFE_BINARY_COHERENT_PLL_C +#define _LRF_RFE_BINARY_COHERENT_PLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_COHERENT_PLL_LENGTH 863 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_coherent_pll[LRF_RFE_BINARY_COHERENT_PLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_cc23x0r5.c new file mode 100644 index 00000000..fe6e943c --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:09:56 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname coherent_pll --fwdesc CC2340R5 LRF firmware for rfe, mode coherent_pll /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/rfe_coherent_pll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/lrf_rfe_binary_coherent_pll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll/rfe_coherent_pll_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_rfe_binary_coherent_pll.h" + +const uint32_t LRF_RFE_binary_coherent_pll[LRF_RFE_BINARY_COHERENT_PLL_LENGTH] = { + 0x0000035E, 0x00006012, 0x0000003C, 0x00000064, 0x00000064, 0x17501700, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64EA7215, 0xB060B152, 0x72157100, 0xB0808121, 0x1012A060, 0x394206F1, + 0x97F1EFF0, 0x65059802, 0x11001631, 0x6C001410, 0x60306030, 0x60306033, 0x6047603B, 0x60306030, + 0x6037604D, 0x64D260F7, 0x64D260F7, 0x64D864D5, 0x647160F7, 0x648064D2, 0xCFE06035, 0x64E16505, + 0x6505CFD0, 0x804064E4, 0x44472200, 0x6505CFC0, 0x644960F7, 0xCFB060F3, 0x64E76505, 0xCFA07000, + 0x725E6505, 0x120B7260, 0x788064E1, 0x6D0514B0, 0x96356D05, 0x95F01050, 0x39109610, 0x64E49620, + 0x10B07891, 0x14013110, 0x6E108720, 0x84601611, 0x72666E10, 0x161BA2A0, 0x31808140, 0x1C0B3980, + 0x64E74453, 0xCF9060F7, 0x64E16505, 0x7260725E, 0x6DB0788B, 0x96306DB0, 0x961095F0, 0x96203910, + 0x700064E4, 0x6505CF80, 0x12081206, 0x96407820, 0x00000000, 0x0000A664, 0x00000000, 0xB6660000, + 0xB09DB07D, 0xB09D7100, 0xB09D7100, 0x81471208, 0x31871079, 0x39893987, 0x409E1E09, 0x40A71C89, + 0x120B1206, 0x161664A8, 0x1C67161B, 0x161844A0, 0x7000609A, 0x14BC788C, 0x6DCD6DCD, 0x789C0000, + 0x311010B0, 0x6DCE140C, 0x314E6DCE, 0x6DCF161C, 0x961D6DCF, 0x946F96AE, 0xA6857100, 0x7840B09D, + 0x84A09640, 0x84B13960, 0x94A03931, 0x95FD94B1, 0xB6857100, 0x7820B09D, 0x84A09640, 0x84B13160, + 0x94A03131, 0x700094B1, 0x6020B010, 0xB0107000, 0x70006023, 0x6026B010, 0xB0107000, 0x70006029, + 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, 0x73097308, 0x72077206, + 0x721C7218, 0x9870C7F0, 0x64EA7000, 0xB1E0B150, 0x64EA60FF, 0xB1E0B150, 0x1E508120, 0xB0804415, + 0xB1536449, 0x64EA6015, 0xB1E0B151, 0x97E06015, 0x220087D0, 0xB7C04506, 0x00007000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6012A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xA0106483, 0x64F160D4, 0x60D7A010, 0xA01064DD, 0x646960DA, 0x60DDA010, 0xA010646B, + 0x650660E0, 0x60E3A010, 0xA0106534, 0x664960E6, 0x60E9A010, 0x951878E8, 0x403F1E08, 0xB682B681, + 0xA327A682, 0x7000B2D8, 0xB811B2C0, 0xB360B2D0, 0xC470B350, 0xB83F6848, 0xB83EB83D, 0xB833B839, + 0xA822B832, 0xB318B319, 0x6853C660, 0xB325B326, 0x782DB327, 0x405B224D, 0xB343B685, 0x685DC0F0, + 0xC130A343, 0xA8236860, 0x7820B824, 0x44672260, 0x666BB39F, 0x64387000, 0xA8246042, 0xA39FB823, + 0xA319B822, 0xA327A318, 0xA326A325, 0xA83FA839, 0xA83EA83D, 0xA832A833, 0xA811A2C0, 0xA2D8A2D0, + 0xA350A360, 0x66A36687, 0x78F17000, 0xB6819511, 0xA681B682, 0x22F382B3, 0x2AF3408D, 0x79A2608F, + 0x82E064EB, 0x0410C1F1, 0x92E00030, 0xC470B2D8, 0xB2F06896, 0x7820B810, 0x449D2250, 0x64B4649F, + 0xB0607000, 0x7100B064, 0x22408040, 0x220044AE, 0xB080409F, 0x1E118121, 0x1E5140AD, 0x7000449F, + 0xB084A064, 0x22008190, 0x7000409F, 0x1E118121, 0x1E5140DC, 0xB83F40DC, 0xB834B83E, 0xB2F1B835, + 0x68BFC2F0, 0x22607820, 0xB39F44C4, 0x22507820, 0xB06044D5, 0x7100B064, 0xB084A064, 0x22108190, + 0x812144D5, 0x40DC1E11, 0x40DC1E51, 0x782D60C8, 0x40D9224D, 0xC170B685, 0x666668DA, 0xA2F17000, + 0x6687A39F, 0x68E1C2F0, 0xA810A2F0, 0xA83FA2D8, 0xA834A83E, 0x66A3A835, 0xDFF179B2, 0x041082D0, + 0x92D00020, 0x81217000, 0x41011E11, 0x41011E51, 0xB064B060, 0x80407100, 0x41022240, 0xB084A064, + 0x22018191, 0x700044F6, 0x40F62200, 0x60F1B080, 0x96B086A0, 0x31803980, 0x3141C081, 0x26010001, + 0xC80096A1, 0x04018661, 0xA2A09661, 0x22F08680, 0x70004118, 0x8681C400, 0x96810401, 0x93C07940, + 0x93B07920, 0xB3E0B3F6, 0xB3D0B3C0, 0x69257970, 0x69277980, 0xA821A820, 0xB830B68F, 0x692D7990, + 0x93B07930, 0x26007950, 0x700093C0, 0x844A813E, 0xCF0910AC, 0x089E049E, 0x944A00EA, 0x4541227A, + 0x260086B0, 0xB83C96A0, 0xB680B838, 0xC8008661, 0x78300401, 0x26010001, 0xB0679661, 0xB079B087, + 0xB060B099, 0x7850728C, 0xC02098D0, 0xA6A06954, 0x41E7225E, 0x3180C400, 0xB6A396B0, 0x8130C0FF, + 0x41612280, 0x71007000, 0x22708040, 0xB08742B7, 0x87208712, 0x100A3940, 0x040F8720, 0x1A8D10AD, + 0x00FD314D, 0x02BD314D, 0xC00D96AD, 0x96BD318D, 0xA447A660, 0xB660A446, 0xC3C01025, 0x10AD1405, + 0x314D168D, 0x314D00FD, 0xC7F802BD, 0x10233188, 0x18037840, 0x728F98E3, 0x80407100, 0x42B72270, + 0x8713B087, 0x96B896AD, 0xB660A660, 0xC3C01036, 0xC0091406, 0x18681028, 0x2609499C, 0x18581038, + 0x261949A0, 0x10ADC3C8, 0x00FD314D, 0x023D314D, 0x94608900, 0x7850728C, 0x710098D0, 0x22708040, + 0xB08742B7, 0x871496AD, 0x14871047, 0xA445A660, 0x1048B662, 0x49BB1858, 0x10482619, 0x49BF1868, + 0x10382609, 0x49C31878, 0x16392629, 0x14901100, 0x61CF6C00, 0x61D161CF, 0x61CF61D5, 0x61D862B2, + 0xB66062B2, 0x103961E8, 0x39191449, 0x104961DB, 0x61DB1669, 0x1A691039, 0x784061DB, 0x98E91809, + 0x1000728F, 0xB6601000, 0x69E3C0C0, 0x94608900, 0xB66261E8, 0x224E79E1, 0x787041FC, 0x788098C0, + 0x710098D0, 0x22708040, 0xB08742B7, 0x98E086F0, 0x98F08700, 0x1E0088B0, 0x890145F8, 0x78927296, + 0x94A46659, 0x665B78B2, 0x872094B4, 0x96A03140, 0x26F0C410, 0x04028682, 0x96822642, 0x8662C810, + 0x78600402, 0x26320002, 0x78D29662, 0x22F4665B, 0x3114461D, 0x421B22F3, 0x94742604, 0x7347621E, + 0x665978A2, 0x22F678A6, 0x26C44224, 0x6662C1C5, 0x665B78C2, 0x6662C1D5, 0x1014C1E5, 0xA0676662, + 0x7100944C, 0x223D782D, 0x227D4636, 0xA3F64636, 0xA663A079, 0x22908050, 0xB2A042B7, 0x61617000, + 0xB661A2A0, 0x06F286D2, 0x46401EB2, 0xA6617000, 0x79E17000, 0xA66061FC, 0x782DA2A0, 0x4658223D, + 0xB820B821, 0xA6807283, 0xA39FA68F, 0xA3E0A3F6, 0xA3D0A3C0, 0x31127000, 0x98E13912, 0xC06098F2, + 0x89236A5E, 0x70008934, 0x26A526C5, 0x70006E54, 0x782DC006, 0x426B220D, 0x84A42606, 0x79C084B3, + 0x94A079D1, 0x782D94B1, 0x4276221D, 0x6277B665, 0x222DB664, 0xB683427A, 0x427D2206, 0xC1C5B687, + 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xA6857000, 0xA687A683, 0xC7018660, 0x1E000410, + 0x84A442A2, 0x79C084B3, 0x94A079D1, 0x866094B1, 0x2A402A50, 0xC1C59660, 0x26A526C5, 0x10346E54, + 0x26C5C1D5, 0x6E5426A5, 0xB6817000, 0x7251A682, 0xA682B682, 0xB07CA687, 0x8051B09C, 0x42AB22C1, + 0xA05CA07C, 0x7000A681, 0x22008040, 0x710046B7, 0xA6A062B2, 0xA6A3A6A1, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll.h new file mode 100644 index 00000000..94e9bcb3 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:03 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname coherent_pll_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode coherent_pll, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/rfe_coherent_pll_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/lrf_rfe_binary_coherent_pll_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/rfe_coherent_pll_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_COHERENT_PLL_NOPLL_C +#define _LRF_RFE_BINARY_COHERENT_PLL_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_COHERENT_PLL_NOPLL_LENGTH 860 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_coherent_pll_nopll[LRF_RFE_BINARY_COHERENT_PLL_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll_cc23x0r5.c new file mode 100644 index 00000000..2f43ad20 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_coherent_pll_nopll_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:03 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname coherent_pll_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode coherent_pll, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/rfe_coherent_pll_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/lrf_rfe_binary_coherent_pll_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/coherent_pll_nopll/rfe_coherent_pll_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_coherent_pll_nopll.h" + +const uint32_t LRF_RFE_binary_coherent_pll_nopll[LRF_RFE_BINARY_COHERENT_PLL_NOPLL_LENGTH] = { + 0x0000035B, 0x00006012, 0x0000003C, 0x00000064, 0x00000064, 0x17501700, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64EA7215, 0xB060B152, 0x72157100, 0xB0808121, 0x1012A060, 0x394206F1, + 0x97F1EFF0, 0x65059802, 0x11001631, 0x6C001410, 0x60306030, 0x60306033, 0x6047603B, 0x60306030, + 0x6037604D, 0x64D260F7, 0x64D260F7, 0x64D864D5, 0x647160F7, 0x648064D2, 0xCFE06035, 0x64E16505, + 0x6505CFD0, 0x804064E4, 0x44472200, 0x6505CFC0, 0x644960F7, 0xCFB060F3, 0x64E76505, 0xCFA07000, + 0x725E6505, 0x120B7260, 0x788064E1, 0x6D0514B0, 0x96356D05, 0x95F01050, 0x39109610, 0x64E49620, + 0x10B07891, 0x14013110, 0x6E108720, 0x84601611, 0x72666E10, 0x161BA2A0, 0x31808140, 0x1C0B3980, + 0x64E74453, 0xCF9060F7, 0x64E16505, 0x7260725E, 0x6DB0788B, 0x96306DB0, 0x961095F0, 0x96203910, + 0x700064E4, 0x6505CF80, 0x12081206, 0x96407820, 0x00000000, 0x0000A664, 0x00000000, 0xB6660000, + 0xB09DB07D, 0xB09D7100, 0xB09D7100, 0x81471208, 0x31871079, 0x39893987, 0x409E1E09, 0x40A71C89, + 0x120B1206, 0x161664A8, 0x1C67161B, 0x161844A0, 0x7000609A, 0x14BC788C, 0x6DCD6DCD, 0x789C0000, + 0x311010B0, 0x6DCE140C, 0x314E6DCE, 0x6DCF161C, 0x961D6DCF, 0x946F96AE, 0xA6857100, 0x7840B09D, + 0x84A09640, 0x84B13960, 0x94A03931, 0x95FD94B1, 0xB6857100, 0x7820B09D, 0x84A09640, 0x84B13160, + 0x94A03131, 0x700094B1, 0x6020B010, 0xB0107000, 0x70006023, 0x6026B010, 0xB0107000, 0x70006029, + 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, 0x73097308, 0x72077206, + 0x721C7218, 0x9870C7F0, 0x64EA7000, 0xB1E0B150, 0x64EA60FF, 0xB1E0B150, 0x1E508120, 0xB0804415, + 0xB1536449, 0x64EA6015, 0xB1E0B151, 0x97E06015, 0x220087D0, 0xB7C04506, 0x00007000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6012A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xA0106483, 0x64F160D4, 0x60D7A010, 0xA01064DD, 0x646960DA, 0x60DDA010, 0xA010646B, + 0x650660E0, 0x60E3A010, 0xA0106534, 0x664A60E6, 0x60E9A010, 0x951878E8, 0x403F1E08, 0xB682B681, + 0xA327A682, 0x7000B2D8, 0xB811B2C0, 0xB360B2D0, 0xC470B350, 0xB83F6848, 0xB83EB83D, 0xB833B839, + 0xA822B832, 0xB318B319, 0x6853C660, 0xB325B326, 0x782DB327, 0x405B224D, 0xB343B685, 0x685DC0F0, + 0xC130A343, 0xA8236860, 0x7820B824, 0x44672260, 0x666CB39F, 0x64387000, 0xA8246042, 0xA39FB823, + 0xA319B822, 0xA327A318, 0xA326A325, 0xA83FA839, 0xA83EA83D, 0xA832A833, 0xA811A2C0, 0xA2D8A2D0, + 0xA350A360, 0x66A46688, 0x78F17000, 0xB6819511, 0xA681B682, 0x22F382B3, 0x2AF3408D, 0x79A2608F, + 0x82E064EB, 0x0410C1F1, 0x92E00030, 0xC470B2D8, 0xB2F06896, 0x7820B810, 0x449D2250, 0x64B4649F, + 0xB0607000, 0x7100B064, 0x22408040, 0x220044AE, 0xB080409F, 0x1E118121, 0x1E5140AD, 0x7000449F, + 0xB084A064, 0x22008190, 0x7000409F, 0x1E118121, 0x1E5140DC, 0xB83F40DC, 0xB834B83E, 0xB2F1B835, + 0x68BFC2F0, 0x22607820, 0xB39F44C4, 0x22507820, 0xB06044D5, 0x7100B064, 0xB084A064, 0x22108190, + 0x812144D5, 0x40DC1E11, 0x40DC1E51, 0x782D60C8, 0x40D9224D, 0xC170B685, 0x666768DA, 0xA2F17000, + 0x6688A39F, 0x68E1C2F0, 0xA810A2F0, 0xA83FA2D8, 0xA834A83E, 0x66A4A835, 0xDFF179B2, 0x041082D0, + 0x92D00020, 0x81217000, 0x41011E11, 0x41011E51, 0xB064B060, 0x80407100, 0x41022240, 0xB084A064, + 0x22018191, 0x700044F6, 0x40F62200, 0x60F1B080, 0x96B086A0, 0x31803980, 0x3141C081, 0x26010001, + 0xC80096A1, 0x04018661, 0xA2A09661, 0x22F08680, 0x70004118, 0x8681C400, 0x96810401, 0x93C07940, + 0x93B07920, 0xB3E0B3F6, 0xB3D0B3C0, 0x69257970, 0x69277980, 0xA821A820, 0xB830B68F, 0x692D7990, + 0x93B07930, 0x26007950, 0x700093C0, 0x844A813E, 0xCF0910AC, 0x089E049E, 0x944A00EA, 0x4541227A, + 0x260086B0, 0xB83C96A0, 0xB680B838, 0xC8008661, 0x78300401, 0x26010001, 0xB0679661, 0xB079B087, + 0xB060B099, 0x7850728C, 0xC02098D0, 0xA6A06954, 0x41E7225E, 0x3180C400, 0xB6A396B0, 0x8130C0FF, + 0x41612280, 0xC1707000, 0x80406962, 0x46B12200, 0x87208712, 0x100A3940, 0x040F8720, 0x1A8D10AD, + 0x00FD314D, 0x02BD314D, 0xC00D96AD, 0x96BD318D, 0xA447A660, 0xB660A446, 0xC3C01025, 0x10AD1405, + 0x314D168D, 0x314D00FD, 0xC7F802BD, 0x10233188, 0x18037840, 0x728F98E3, 0x698BC170, 0x22008040, + 0x871346B1, 0x96B896AD, 0xB660A660, 0xC3C01036, 0xC0091406, 0x18681028, 0x2609499C, 0x18581038, + 0x261949A0, 0x10ADC3C8, 0x00FD314D, 0x023D314D, 0x94608900, 0x7850728C, 0xC17098D0, 0x804069AC, + 0x46B12200, 0x871496AD, 0x14871047, 0xA445A660, 0x1048B662, 0x49BB1858, 0x10482619, 0x49BF1868, + 0x10382609, 0x49C31878, 0x16392629, 0x14901100, 0x61CF6C00, 0x61D161CF, 0x61CF61D5, 0x61D862AC, + 0xB66062AC, 0x103961E8, 0x39191449, 0x104961DB, 0x61DB1669, 0x1A691039, 0x784061DB, 0x98E91809, + 0x1000728F, 0xB6601000, 0x69E3C0C0, 0x94608900, 0xB66261E8, 0x224E79E1, 0x787041FC, 0x788098C0, + 0xC2F098D0, 0x804069F0, 0x46B12200, 0x98E086F0, 0x98F08700, 0x1E0088B0, 0x890145F8, 0x78927296, + 0x94A4665A, 0x665C78B2, 0x872094B4, 0x96A03140, 0x26F0C410, 0x04028682, 0x96822642, 0x8662C810, + 0x78600402, 0x26320002, 0x78D29662, 0x22F4665C, 0x3114461D, 0x421B22F3, 0x94742604, 0x7347621E, + 0x665A78A2, 0x22F678A6, 0x26C44224, 0x6663C1C5, 0x665C78C2, 0x6663C1D5, 0x1014C1E5, 0xA0676663, + 0xD370944C, 0x782D6A30, 0x4637223D, 0x4637227D, 0xA079A3F6, 0x8040A663, 0x46B12200, 0x7000B2A0, + 0xA2A06161, 0x86D2B661, 0x1EB206F2, 0x70004641, 0x7000A661, 0x61FC79E1, 0xA2A0A660, 0x223D782D, + 0xB8214659, 0x7283B820, 0xA68FA680, 0xA3F6A39F, 0xA3C0A3E0, 0x7000A3D0, 0x39123112, 0x98F298E1, + 0x6A5FC060, 0x89348923, 0x26C57000, 0x6E5426A5, 0xC0067000, 0x220D782D, 0x2606426C, 0x84B384A4, + 0x79D179C0, 0x94B194A0, 0x221D782D, 0xB6654277, 0xB6646278, 0x427B222D, 0x2206B683, 0xB687427E, + 0x26C5C1C5, 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA683A685, 0x8660A687, 0x0410C701, + 0x42A31E00, 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x2A508660, 0x96602A40, 0x26C5C1C5, 0x6E5426A5, + 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA682B681, 0xB6827251, 0xA687A682, 0x7000A681, 0x22008040, + 0x710046B1, 0xA6A062AC, 0xA6A3A6A1, 0x00007000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common.h new file mode 100644 index 00000000..fc2e0aa6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname common --fwdesc CC2340R5 LRF firmware for rfe, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/rfe_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/lrf_rfe_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/rfe_common_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_RFE_BINARY_COMMON_C +#define _LRF_RFE_BINARY_COMMON_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_COMMON_LENGTH 2 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_common[LRF_RFE_BINARY_COMMON_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_cc23x0r5.c new file mode 100644 index 00000000..8a996070 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_cc23x0r5.c @@ -0,0 +1,15 @@ +// This code snippet was auto-generated on Thu May 23 12:09:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname common --fwdesc CC2340R5 LRF firmware for rfe, mode common /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/rfe_common_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/lrf_rfe_binary_common.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common/rfe_common_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_rfe_binary_common.h" + +const uint32_t LRF_RFE_binary_common[LRF_RFE_BINARY_COMMON_LENGTH] = { + 0x00000000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll.h new file mode 100644 index 00000000..7b7e9d3f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:09:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname common_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode common, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/rfe_common_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/lrf_rfe_binary_common_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/rfe_common_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#ifndef _LRF_RFE_BINARY_COMMON_NOPLL_C +#define _LRF_RFE_BINARY_COMMON_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_COMMON_NOPLL_LENGTH 2 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_common_nopll[LRF_RFE_BINARY_COMMON_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll_cc23x0r5.c new file mode 100644 index 00000000..04856c88 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_common_nopll_cc23x0r5.c @@ -0,0 +1,15 @@ +// This code snippet was auto-generated on Thu May 23 12:09:04 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname common_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode common, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/rfe_common_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/lrf_rfe_binary_common_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/common_nopll/rfe_common_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:09 + + +#include "lrf_rfe_binary_common_nopll.h" + +const uint32_t LRF_RFE_binary_common_nopll[LRF_RFE_BINARY_COMMON_NOPLL_LENGTH] = { + 0x00000000 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk.h new file mode 100644 index 00000000..6a0bc1a0 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:03 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname genfsk --fwdesc CC2340R5 LRF firmware for rfe, mode genfsk /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/rfe_genfsk_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/lrf_rfe_binary_genfsk.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/rfe_genfsk_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_GENFSK_C +#define _LRF_RFE_BINARY_GENFSK_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_GENFSK_LENGTH 864 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_genfsk[LRF_RFE_BINARY_GENFSK_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_cc23x0r5.c new file mode 100644 index 00000000..f1a97f36 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:03 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname genfsk --fwdesc CC2340R5 LRF firmware for rfe, mode genfsk /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/rfe_genfsk_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/lrf_rfe_binary_genfsk.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk/rfe_genfsk_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_genfsk.h" + +const uint32_t LRF_RFE_binary_genfsk[LRF_RFE_BINARY_GENFSK_LENGTH] = { + 0x0000035F, 0x00006011, 0x08000080, 0x08300810, 0x08F00870, 0x09F109F0, 0x09F709F3, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB1526578, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0x31323982, + 0x16321412, 0x14211101, 0x602B6C01, 0x602E602B, 0x60376033, 0x602B6043, 0x6185602B, 0x61856461, + 0x644C6449, 0x6185644F, 0x64526185, 0x64556461, 0xCFF06185, 0x64586593, 0x6593CFE0, 0x22008040, + 0x645B4443, 0x6593CFD0, 0x64456185, 0xCFC06181, 0x645E6593, 0xB0107000, 0x70006023, 0x6026B010, + 0xB0107000, 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, + 0x6038B010, 0xA15C7000, 0x72167218, 0x827DA040, 0x398D318D, 0xC0F18260, 0x10090410, 0x394A826A, + 0x8260041A, 0x04103980, 0x10AB100E, 0x10C210BC, 0x7279656F, 0x6593CFB0, 0xC7F0B183, 0xA0649870, + 0x22008040, 0x81904564, 0x44852200, 0xB023607D, 0x651AB003, 0xB060B063, 0xB084B064, 0x64FDB023, + 0x22E08260, 0x65054492, 0x80417100, 0x45642201, 0x8190B084, 0x44A32210, 0x40922231, 0x6520B083, + 0x22E08260, 0x64C84492, 0xB0846092, 0x318F887F, 0xDFA03D8F, 0x659397FF, 0x81217100, 0x41641A11, + 0x8190B084, 0x40BD2210, 0x8261B083, 0x44B822C1, 0x65526520, 0x22D18261, 0x64C844AA, 0x887160AA, + 0x31818882, 0x31823D81, 0xEF903D82, 0x980297F1, 0x60616593, 0x97408860, 0x87978753, 0x18D3A790, + 0x0BF34CD7, 0x1CE31613, 0x974348FC, 0x143B8763, 0x1CBA60E8, 0x1E2344E3, 0x1CE348E3, 0xB7904CE3, + 0x40E32207, 0x1A1BA790, 0x1CE360EE, 0x974348FC, 0x183B8763, 0x4CF81CAB, 0x48FA1C9B, 0x40FC1CBC, + 0x826010B2, 0x40F522D0, 0x22108190, 0x656F44FC, 0x60FC64FD, 0x60EC10AB, 0x60EC109B, 0x82807000, + 0xB08306F0, 0x68FF7100, 0xB18010BC, 0x88627000, 0x87529742, 0x18128891, 0x18128221, 0x31818291, + 0x1C123D81, 0xB1624912, 0x1421C7F1, 0xC8124D16, 0x98829872, 0x7000B161, 0xC0061208, 0x9870C7F0, + 0x70009880, 0x88608891, 0x87509740, 0x82211810, 0x14061810, 0x82928161, 0x3D823182, 0x49331C20, + 0x45362221, 0xCF80B162, 0x22216593, 0xA1624136, 0x39418281, 0x0401C0F0, 0x41441E01, 0xC0101618, + 0x1C083010, 0x10604551, 0x10063C10, 0x1461C7F1, 0xC8164D48, 0x88819876, 0x3D813181, 0x494F1C16, + 0xC0069886, 0x70001208, 0x31818871, 0x82903D81, 0x18013980, 0x49631CF1, 0x81501401, 0x456322C0, + 0xEF70B15C, 0x980F97F1, 0x70006593, 0xC7F0A183, 0xA0039870, 0x81427000, 0x6185656F, 0x7100B060, + 0xC0106185, 0x6F031420, 0x10209843, 0x14023112, 0x70009892, 0x73097308, 0x72077206, 0x721C7218, + 0x9870C7F0, 0x65787000, 0xB1E0B150, 0x6578618D, 0xB1E0B150, 0x1E508120, 0xB0804414, 0xB1536445, + 0x65786014, 0xB1E0B151, 0x97E06014, 0x220087D0, 0xB7C04598, 0x00007000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6011A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x604BA010, 0xA01064F4, 0x64E0604E, 0x6051A010, 0xA010646C, + 0x646E6054, 0x6057A010, 0xA0106509, 0x6537605A, 0x605DA010, 0xA010664C, 0x78E86060, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666E, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668AA350, 0x700066A6, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x70006669, 0xA39FA2F1, 0xC2F0668A, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A6, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x80407100, 0x42BA2270, 0x8712B087, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0x7100728F, + 0x22708040, 0xB08742BA, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x80407100, 0x42BA2270, 0x96ADB087, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62B561D2, 0x62B561DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x80407100, 0x42BA2270, 0x86F0B087, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665C7892, 0x78B294A4, 0x94B4665E, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665E78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665C, 0x422722F6, 0xC1C526C4, 0x78C26665, 0xC1D5665E, 0xC1E56665, + 0x66651014, 0x944CA067, 0x782D7100, 0x4639223D, 0x4639227D, 0xA079A3F6, 0x8050A663, 0x42BA2290, + 0x7000B2A0, 0xA2A06164, 0x86D2B661, 0x1EB206F2, 0x70004643, 0x7000A661, 0x61FF79E1, 0xA2A0A660, + 0x223D782D, 0xB821465B, 0x7283B820, 0xA68FA680, 0xA3F6A39F, 0xA3C0A3E0, 0x7000A3D0, 0x39123112, + 0x98F298E1, 0x6A61C060, 0x89348923, 0x26C57000, 0x6E5426A5, 0xC0067000, 0x220D782D, 0x2606426E, + 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x221D782D, 0xB6654279, 0xB664627A, 0x427D222D, 0x2206B683, + 0xB6874280, 0x26C5C1C5, 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA683A685, 0x8660A687, + 0x0410C701, 0x42A51E00, 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x2A508660, 0x96602A40, 0x26C5C1C5, + 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA682B681, 0xB6827251, 0xA687A682, 0xB09CB07C, + 0x22C18051, 0xA07C42AE, 0xA681A05C, 0x80407000, 0x46BA2200, 0x62B57100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll.h new file mode 100644 index 00000000..662cecb2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname genfsk_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode genfsk, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/rfe_genfsk_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/lrf_rfe_binary_genfsk_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/rfe_genfsk_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_GENFSK_NOPLL_C +#define _LRF_RFE_BINARY_GENFSK_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_GENFSK_NOPLL_LENGTH 861 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_genfsk_nopll[LRF_RFE_BINARY_GENFSK_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll_cc23x0r5.c new file mode 100644 index 00000000..846ee2aa --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_genfsk_nopll_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:02 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname genfsk_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode genfsk, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/rfe_genfsk_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/lrf_rfe_binary_genfsk_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/genfsk_nopll/rfe_genfsk_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_genfsk_nopll.h" + +const uint32_t LRF_RFE_binary_genfsk_nopll[LRF_RFE_BINARY_GENFSK_NOPLL_LENGTH] = { + 0x0000035C, 0x00006011, 0x08000080, 0x08300810, 0x08F00870, 0x09F109F0, 0x09F709F3, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB1526578, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0x31323982, + 0x16321412, 0x14211101, 0x602B6C01, 0x602E602B, 0x60376033, 0x602B6043, 0x6185602B, 0x61856461, + 0x644C6449, 0x6185644F, 0x64526185, 0x64556461, 0xCFF06185, 0x64586593, 0x6593CFE0, 0x22008040, + 0x645B4443, 0x6593CFD0, 0x64456185, 0xCFC06181, 0x645E6593, 0xB0107000, 0x70006023, 0x6026B010, + 0xB0107000, 0x70006029, 0x602CB010, 0xB0107000, 0x7000602F, 0x6032B010, 0xB0107000, 0x70006035, + 0x6038B010, 0xA15C7000, 0x72167218, 0x827DA040, 0x398D318D, 0xC0F18260, 0x10090410, 0x394A826A, + 0x8260041A, 0x04103980, 0x10AB100E, 0x10C210BC, 0x7279656F, 0x6593CFB0, 0xC7F0B183, 0xA0649870, + 0x22008040, 0x81904564, 0x44852200, 0xB023607D, 0x651AB003, 0xB060B063, 0xB084B064, 0x64FDB023, + 0x22E08260, 0x65054492, 0x80417100, 0x45642201, 0x8190B084, 0x44A32210, 0x40922231, 0x6520B083, + 0x22E08260, 0x64C84492, 0xB0846092, 0x318F887F, 0xDFA03D8F, 0x659397FF, 0x81217100, 0x41641A11, + 0x8190B084, 0x40BD2210, 0x8261B083, 0x44B822C1, 0x65526520, 0x22D18261, 0x64C844AA, 0x887160AA, + 0x31818882, 0x31823D81, 0xEF903D82, 0x980297F1, 0x60616593, 0x97408860, 0x87978753, 0x18D3A790, + 0x0BF34CD7, 0x1CE31613, 0x974348FC, 0x143B8763, 0x1CBA60E8, 0x1E2344E3, 0x1CE348E3, 0xB7904CE3, + 0x40E32207, 0x1A1BA790, 0x1CE360EE, 0x974348FC, 0x183B8763, 0x4CF81CAB, 0x48FA1C9B, 0x40FC1CBC, + 0x826010B2, 0x40F522D0, 0x22108190, 0x656F44FC, 0x60FC64FD, 0x60EC10AB, 0x60EC109B, 0x82807000, + 0xB08306F0, 0x68FF7100, 0xB18010BC, 0x88627000, 0x87529742, 0x18128891, 0x18128221, 0x31818291, + 0x1C123D81, 0xB1624912, 0x1421C7F1, 0xC8124D16, 0x98829872, 0x7000B161, 0xC0061208, 0x9870C7F0, + 0x70009880, 0x88608891, 0x87509740, 0x82211810, 0x14061810, 0x82928161, 0x3D823182, 0x49331C20, + 0x45362221, 0xCF80B162, 0x22216593, 0xA1624136, 0x39418281, 0x0401C0F0, 0x41441E01, 0xC0101618, + 0x1C083010, 0x10604551, 0x10063C10, 0x1461C7F1, 0xC8164D48, 0x88819876, 0x3D813181, 0x494F1C16, + 0xC0069886, 0x70001208, 0x31818871, 0x82903D81, 0x18013980, 0x49631CF1, 0x81501401, 0x456322C0, + 0xEF70B15C, 0x980F97F1, 0x70006593, 0xC7F0A183, 0xA0039870, 0x81427000, 0x6185656F, 0x7100B060, + 0xC0106185, 0x6F031420, 0x10209843, 0x14023112, 0x70009892, 0x73097308, 0x72077206, 0x721C7218, + 0x9870C7F0, 0x65787000, 0xB1E0B150, 0x6578618D, 0xB1E0B150, 0x1E508120, 0xB0804414, 0xB1536445, + 0x65786014, 0xB1E0B151, 0x97E06014, 0x220087D0, 0xB7C04598, 0x00007000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6011A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x604BA010, 0xA01064F4, 0x64E0604E, 0x6051A010, 0xA010646C, + 0x646E6054, 0x6057A010, 0xA0106509, 0x6537605A, 0x605DA010, 0xA010664D, 0x78E86060, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666F, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668BA350, 0x700066A7, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x7000666A, 0xA39FA2F1, 0xC2F0668B, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A7, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x6965C170, 0x22008040, 0x871246B4, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0xC170728F, + 0x8040698E, 0x46B42200, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x69AFC170, 0x22008040, 0x96AD46B4, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62AF61D2, 0x62AF61DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x69F3C2F0, 0x22008040, 0x86F046B4, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665D7892, 0x78B294A4, 0x94B4665F, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665F78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665D, 0x422722F6, 0xC1C526C4, 0x78C26666, 0xC1D5665F, 0xC1E56666, + 0x66661014, 0x944CA067, 0x6A33D370, 0x223D782D, 0x227D463A, 0xA3F6463A, 0xA663A079, 0x22008040, + 0xB2A046B4, 0x61647000, 0xB661A2A0, 0x06F286D2, 0x46441EB2, 0xA6617000, 0x79E17000, 0xA66061FF, + 0x782DA2A0, 0x465C223D, 0xB820B821, 0xA6807283, 0xA39FA68F, 0xA3E0A3F6, 0xA3D0A3C0, 0x31127000, + 0x98E13912, 0xC06098F2, 0x89236A62, 0x70008934, 0x26A526C5, 0x70006E54, 0x782DC006, 0x426F220D, + 0x84A42606, 0x79C084B3, 0x94A079D1, 0x782D94B1, 0x427A221D, 0x627BB665, 0x222DB664, 0xB683427E, + 0x42812206, 0xC1C5B687, 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xA6857000, 0xA687A683, + 0xC7018660, 0x1E000410, 0x84A442A6, 0x79C084B3, 0x94A079D1, 0x866094B1, 0x2A402A50, 0xC1C59660, + 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xB6817000, 0x7251A682, 0xA682B682, 0xA681A687, + 0x80407000, 0x46B42200, 0x62AF7100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee.h new file mode 100644 index 00000000..1d7e450f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:08 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ieee --fwdesc CC2340R5 LRF firmware for rfe, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/rfe_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/lrf_rfe_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/rfe_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_IEEE_C +#define _LRF_RFE_BINARY_IEEE_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_IEEE_LENGTH 864 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ieee[LRF_RFE_BINARY_IEEE_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c new file mode 100644 index 00000000..bd97ea2b --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:08 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ieee --fwdesc CC2340R5 LRF firmware for rfe, mode ieee /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/rfe_ieee_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/lrf_rfe_binary_ieee.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee/rfe_ieee_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ieee.h" + +const uint32_t LRF_RFE_binary_ieee[LRF_RFE_BINARY_IEEE_LENGTH] = { + 0x0000035F, 0x1FF76021, 0x00001FFF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08000080, 0x08300810, 0x08F00870, 0x09F109F0, 0x09F709F3, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB152652F, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0xEFF03942, + 0x980297F1, 0x3132654A, 0x16321412, 0x14211101, 0x603F6C01, 0x604A603F, 0x6052604E, 0x603F605E, + 0x613C603F, 0x613C6464, 0x613C646A, 0x613C646D, 0x613C6470, 0x613C647C, 0x64676464, 0x613C646A, + 0x647C646D, 0x613C6470, 0x654ACFE0, 0xCFD06473, 0x6476654A, 0x22008040, 0xCFC0445E, 0x613C654A, + 0x61386460, 0x654ACFB0, 0x70006479, 0x6023B010, 0xB0107000, 0x70006026, 0x6029B010, 0xB0107000, + 0x7000602C, 0x602FB010, 0xB0107000, 0x70006032, 0x6035B010, 0xB0107000, 0x70006038, 0xC7F0B183, + 0x826E9870, 0x06F910E9, 0x10EA394E, 0x10AC06FA, 0x06FE394E, 0x652610C2, 0x10CB827D, 0xA06464DF, + 0x22008190, 0x80404495, 0x45132200, 0xA183607C, 0x654ACFA0, 0xB063B023, 0xB060B083, 0xB084B064, + 0x7100B003, 0x8193B083, 0x407C2203, 0x80417100, 0x45132201, 0x40AC2241, 0x60A1B084, 0x8860B083, + 0x875F9740, 0x875F916F, 0x22138193, 0x81304511, 0x45112240, 0x18D310F3, 0x0BF34CC3, 0x1CE31613, + 0x97434911, 0x143B8763, 0x1CE360C8, 0x97434911, 0x183B8763, 0x4CDB1CAB, 0x48DD1C9B, 0x41111CBC, + 0xB1801CBC, 0x10BCA180, 0x652610B2, 0x64EE64EE, 0xB0837100, 0xB0837100, 0x10AB60A1, 0x109B60CC, + 0x781760CC, 0x18707820, 0x6E71C001, 0x68E31617, 0x12087817, 0xC7F0C006, 0x70009870, 0x10001000, + 0x889110F0, 0x6D711810, 0x18166D71, 0x6E701406, 0x78211617, 0x44FB1C17, 0x16187817, 0x450E1E88, + 0x39301060, 0x18108221, 0x22018191, 0x9870410E, 0x31818881, 0x1C103D81, 0x9880490C, 0x1278B1E1, + 0x10007000, 0x64EE1000, 0xA18360A1, 0x88728891, 0x3D823182, 0x97F1EF90, 0x654A9802, 0x9870C7F0, + 0x7000A003, 0x65268142, 0xB060613C, 0x613C7100, 0x1420C110, 0x98436F03, 0x31121020, 0x98921402, + 0x73087000, 0x72067309, 0x72187207, 0xC7F0721C, 0x70009870, 0xB150652F, 0x6144B1E0, 0xB150652F, + 0x8120B1E0, 0x44241E50, 0x6460B080, 0x6024B153, 0xB151652F, 0x6024B1E0, 0x87D097E0, 0x454F2200, + 0x7000B7C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6021A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x6066A010, 0xA01064F4, 0x64E06069, 0x606CA010, 0xA010646C, + 0x646E606F, 0x6072A010, 0xA0106509, 0x65376075, 0x6078A010, 0xA010664C, 0x78E8607B, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666E, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668AA350, 0x700066A6, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x70006669, 0xA39FA2F1, 0xC2F0668A, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A6, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x80407100, 0x42BA2270, 0x8712B087, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0x7100728F, + 0x22708040, 0xB08742BA, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x80407100, 0x42BA2270, 0x96ADB087, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62B561D2, 0x62B561DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x80407100, 0x42BA2270, 0x86F0B087, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665C7892, 0x78B294A4, 0x94B4665E, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665E78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665C, 0x422722F6, 0xC1C526C4, 0x78C26665, 0xC1D5665E, 0xC1E56665, + 0x66651014, 0x944CA067, 0x782D7100, 0x4639223D, 0x4639227D, 0xA079A3F6, 0x8050A663, 0x42BA2290, + 0x7000B2A0, 0xA2A06164, 0x86D2B661, 0x1EB206F2, 0x70004643, 0x7000A661, 0x61FF79E1, 0xA2A0A660, + 0x223D782D, 0xB821465B, 0x7283B820, 0xA68FA680, 0xA3F6A39F, 0xA3C0A3E0, 0x7000A3D0, 0x39123112, + 0x98F298E1, 0x6A61C060, 0x89348923, 0x26C57000, 0x6E5426A5, 0xC0067000, 0x220D782D, 0x2606426E, + 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x221D782D, 0xB6654279, 0xB664627A, 0x427D222D, 0x2206B683, + 0xB6874280, 0x26C5C1C5, 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA683A685, 0x8660A687, + 0x0410C701, 0x42A51E00, 0x84B384A4, 0x79D179C0, 0x94B194A0, 0x2A508660, 0x96602A40, 0x26C5C1C5, + 0x6E5426A5, 0xC1D51034, 0x26A526C5, 0x70006E54, 0xA682B681, 0xB6827251, 0xA687A682, 0xB09CB07C, + 0x22C18051, 0xA07C42AE, 0xA681A05C, 0x80407000, 0x46BA2200, 0x62B57100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll.h new file mode 100644 index 00000000..143d59b6 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll.h @@ -0,0 +1,21 @@ +// This code snippet was auto-generated on Thu May 23 12:10:07 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ieee_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ieee, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/rfe_ieee_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/lrf_rfe_binary_ieee_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/rfe_ieee_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#ifndef _LRF_RFE_BINARY_IEEE_NOPLL_C +#define _LRF_RFE_BINARY_IEEE_NOPLL_C + + +#include + +/* Length of binary image. */ +#define LRF_RFE_BINARY_IEEE_NOPLL_LENGTH 861 + +/* Declaration of raw binary. */ +extern const uint32_t LRF_RFE_binary_ieee_nopll[LRF_RFE_BINARY_IEEE_NOPLL_LENGTH]; + +#endif diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll_cc23x0r5.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll_cc23x0r5.c new file mode 100644 index 00000000..c24a899f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/rf_patches/lrf_rfe_binary_ieee_nopll_cc23x0r5.c @@ -0,0 +1,122 @@ +// This code snippet was auto-generated on Thu May 23 12:10:07 2024 using command: +// perl /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/bin2csource_v2.pl --cpu rfe --fwname ieee_nopll --fwdesc CC2340R5 LRF firmware for rfe, mode ieee, NOPLL=1 /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/rfe_ieee_nopll_ram.bin /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/lrf_rfe_binary_ieee_nopll.c + + +// Binary source file: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/rfe/ieee_nopll/rfe_ieee_nopll_ram.bin +// Binary source last modified: 23-May-2024 12:10 + + +#include "lrf_rfe_binary_ieee_nopll.h" + +const uint32_t LRF_RFE_binary_ieee_nopll[LRF_RFE_BINARY_IEEE_NOPLL_LENGTH] = { + 0x0000035C, 0x1FF76021, 0x00001FFF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08000080, 0x08300810, 0x08F00870, 0x09F109F0, 0x09F709F3, 0x07FF09FF, + 0x03FF05FF, 0x721501FF, 0xB152652F, 0x7100B060, 0x81217215, 0xA060B080, 0x06F11012, 0xEFF03942, + 0x980297F1, 0x3132654A, 0x16321412, 0x14211101, 0x603F6C01, 0x604A603F, 0x6052604E, 0x603F605E, + 0x613C603F, 0x613C6464, 0x613C646A, 0x613C646D, 0x613C6470, 0x613C647C, 0x64676464, 0x613C646A, + 0x647C646D, 0x613C6470, 0x654ACFE0, 0xCFD06473, 0x6476654A, 0x22008040, 0xCFC0445E, 0x613C654A, + 0x61386460, 0x654ACFB0, 0x70006479, 0x6023B010, 0xB0107000, 0x70006026, 0x6029B010, 0xB0107000, + 0x7000602C, 0x602FB010, 0xB0107000, 0x70006032, 0x6035B010, 0xB0107000, 0x70006038, 0xC7F0B183, + 0x826E9870, 0x06F910E9, 0x10EA394E, 0x10AC06FA, 0x06FE394E, 0x652610C2, 0x10CB827D, 0xA06464DF, + 0x22008190, 0x80404495, 0x45132200, 0xA183607C, 0x654ACFA0, 0xB063B023, 0xB060B083, 0xB084B064, + 0x7100B003, 0x8193B083, 0x407C2203, 0x80417100, 0x45132201, 0x40AC2241, 0x60A1B084, 0x8860B083, + 0x875F9740, 0x875F916F, 0x22138193, 0x81304511, 0x45112240, 0x18D310F3, 0x0BF34CC3, 0x1CE31613, + 0x97434911, 0x143B8763, 0x1CE360C8, 0x97434911, 0x183B8763, 0x4CDB1CAB, 0x48DD1C9B, 0x41111CBC, + 0xB1801CBC, 0x10BCA180, 0x652610B2, 0x64EE64EE, 0xB0837100, 0xB0837100, 0x10AB60A1, 0x109B60CC, + 0x781760CC, 0x18707820, 0x6E71C001, 0x68E31617, 0x12087817, 0xC7F0C006, 0x70009870, 0x10001000, + 0x889110F0, 0x6D711810, 0x18166D71, 0x6E701406, 0x78211617, 0x44FB1C17, 0x16187817, 0x450E1E88, + 0x39301060, 0x18108221, 0x22018191, 0x9870410E, 0x31818881, 0x1C103D81, 0x9880490C, 0x1278B1E1, + 0x10007000, 0x64EE1000, 0xA18360A1, 0x88728891, 0x3D823182, 0x97F1EF90, 0x654A9802, 0x9870C7F0, + 0x7000A003, 0x65268142, 0xB060613C, 0x613C7100, 0x1420C110, 0x98436F03, 0x31121020, 0x98921402, + 0x73087000, 0x72067309, 0x72187207, 0xC7F0721C, 0x70009870, 0xB150652F, 0x6144B1E0, 0xB150652F, + 0x8120B1E0, 0x44241E50, 0x6460B080, 0x6024B153, 0xB151652F, 0x6024B1E0, 0x87D097E0, 0x454F2200, + 0x7000B7C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6021A010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x64860000, 0x6066A010, 0xA01064F4, 0x64E06069, 0x606CA010, 0xA010646C, + 0x646E606F, 0x6072A010, 0xA0106509, 0x65376075, 0x6078A010, 0xA010664D, 0x78E8607B, 0x1E089518, + 0xB6814042, 0xA682B682, 0xB2D8A327, 0xB2C07000, 0xB2D0B811, 0xB350B360, 0x684BC470, 0xB83DB83F, + 0xB839B83E, 0xB832B833, 0xB319A822, 0xC660B318, 0xB3266856, 0xB327B325, 0x224D782D, 0xB685405E, + 0xC0F0B343, 0xA3436860, 0x6863C130, 0xB824A823, 0x22607820, 0xB39F446A, 0x7000666F, 0x6045643B, + 0xB823A824, 0xB822A39F, 0xA318A319, 0xA325A327, 0xA839A326, 0xA83DA83F, 0xA833A83E, 0xA2C0A832, + 0xA2D0A811, 0xA360A2D8, 0x668BA350, 0x700066A7, 0x951178F1, 0xB682B681, 0x82B3A681, 0x409022F3, + 0x60922AF3, 0x64EE79A2, 0xC1F182E0, 0x00300410, 0xB2D892E0, 0x6899C470, 0xB810B2F0, 0x22507820, + 0x64A244A0, 0x700064B7, 0xB064B060, 0x80407100, 0x44B12240, 0x40A22200, 0x8121B080, 0x40B01E11, + 0x44A21E51, 0xA0647000, 0x8190B084, 0x40A22200, 0x81217000, 0x40DF1E11, 0x40DF1E51, 0xB83EB83F, + 0xB835B834, 0xC2F0B2F1, 0x782068C2, 0x44C72260, 0x7820B39F, 0x44D82250, 0xB064B060, 0xA0647100, + 0x8190B084, 0x44D82210, 0x1E118121, 0x1E5140DF, 0x60CB40DF, 0x224D782D, 0xB68540DC, 0x68DDC170, + 0x7000666A, 0xA39FA2F1, 0xC2F0668B, 0xA2F068E4, 0xA2D8A810, 0xA83EA83F, 0xA835A834, 0x79B266A7, + 0x82D0DFF1, 0x00200410, 0x700092D0, 0x1E118121, 0x1E514104, 0xB0604104, 0x7100B064, 0x22408040, + 0xA0644105, 0x8191B084, 0x44F92201, 0x22007000, 0xB08040F9, 0x86A060F4, 0x398096B0, 0xC0813180, + 0x00013141, 0x96A12601, 0x8661C800, 0x96610401, 0x8680A2A0, 0x411B22F0, 0xC4007000, 0x04018681, + 0x79409681, 0x792093C0, 0xB3F693B0, 0xB3C0B3E0, 0x7970B3D0, 0x79806928, 0xA820692A, 0xB68FA821, + 0x7990B830, 0x79306930, 0x795093B0, 0x93C02600, 0x813E7000, 0x10AC844A, 0x049ECF09, 0x00EA089E, + 0x227A944A, 0x86B04544, 0x96A02600, 0xB838B83C, 0x8661B680, 0x0401C800, 0x00017830, 0x96612601, + 0xB087B067, 0xB099B079, 0x728CB060, 0x98D07850, 0x6957C020, 0x225EA6A0, 0xC40041EA, 0x96B03180, + 0xC0FFB6A3, 0x22808130, 0x70004164, 0x6965C170, 0x22008040, 0x871246B4, 0x39408720, 0x8720100A, + 0x10AD040F, 0x314D1A8D, 0x314D00FD, 0x96AD02BD, 0x318DC00D, 0xA66096BD, 0xA446A447, 0x1025B660, + 0x1405C3C0, 0x168D10AD, 0x00FD314D, 0x02BD314D, 0x3188C7F8, 0x78401023, 0x98E31803, 0xC170728F, + 0x8040698E, 0x46B42200, 0x96AD8713, 0xA66096B8, 0x1036B660, 0x1406C3C0, 0x1028C009, 0x499F1868, + 0x10382609, 0x49A31858, 0xC3C82619, 0x314D10AD, 0x314D00FD, 0x8900023D, 0x728C9460, 0x98D07850, + 0x69AFC170, 0x22008040, 0x96AD46B4, 0x10478714, 0xA6601487, 0xB662A445, 0x18581048, 0x261949BE, + 0x18681048, 0x260949C2, 0x18781038, 0x262949C6, 0x11001639, 0x6C001490, 0x61D261D2, 0x61D861D4, + 0x62AF61D2, 0x62AF61DB, 0x61EBB660, 0x14491039, 0x61DE3919, 0x16691049, 0x103961DE, 0x61DE1A69, + 0x18097840, 0x728F98E9, 0x10001000, 0xC0C0B660, 0x890069E6, 0x61EB9460, 0x79E1B662, 0x41FF224E, + 0x98C07870, 0x98D07880, 0x69F3C2F0, 0x22008040, 0x86F046B4, 0x870098E0, 0x88B098F0, 0x45FB1E00, + 0x72968901, 0x665D7892, 0x78B294A4, 0x94B4665F, 0x31408720, 0xC41096A0, 0x868226F0, 0x26420402, + 0xC8109682, 0x04028662, 0x00027860, 0x96622632, 0x665F78D2, 0x462022F4, 0x22F33114, 0x2604421E, + 0x62219474, 0x78A27347, 0x78A6665D, 0x422722F6, 0xC1C526C4, 0x78C26666, 0xC1D5665F, 0xC1E56666, + 0x66661014, 0x944CA067, 0x6A33D370, 0x223D782D, 0x227D463A, 0xA3F6463A, 0xA663A079, 0x22008040, + 0xB2A046B4, 0x61647000, 0xB661A2A0, 0x06F286D2, 0x46441EB2, 0xA6617000, 0x79E17000, 0xA66061FF, + 0x782DA2A0, 0x465C223D, 0xB820B821, 0xA6807283, 0xA39FA68F, 0xA3E0A3F6, 0xA3D0A3C0, 0x31127000, + 0x98E13912, 0xC06098F2, 0x89236A62, 0x70008934, 0x26A526C5, 0x70006E54, 0x782DC006, 0x426F220D, + 0x84A42606, 0x79C084B3, 0x94A079D1, 0x782D94B1, 0x427A221D, 0x627BB665, 0x222DB664, 0xB683427E, + 0x42812206, 0xC1C5B687, 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xA6857000, 0xA687A683, + 0xC7018660, 0x1E000410, 0x84A442A6, 0x79C084B3, 0x94A079D1, 0x866094B1, 0x2A402A50, 0xC1C59660, + 0x26A526C5, 0x10346E54, 0x26C5C1D5, 0x6E5426A5, 0xB6817000, 0x7251A682, 0xA682B682, 0xA681A687, + 0x80407000, 0x46B42200, 0x62AF7100, 0xA6A1A6A0, 0x7000A6A3 }; + + + diff --git a/simplelink_lpf3/source/ti/drivers/rcl/LRF.c b/simplelink_lpf3/source/ti/drivers/rcl/LRF.c new file mode 100644 index 00000000..e246c6ed --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/LRF.c @@ -0,0 +1,784 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== LRF.c ======== + */ + +#include +#include + +#include +#include +#include +#include + +// #define LRF_DEBUG_TRACE + +LRF_SetupResult LRF_loadImage(const LRF_TOPsmImage *image, uint32_t destinationAddress) +{ + LRF_SetupResult result; + + if (image == NULL) + { + /* OK, don't load image */ + result = SetupResult_Ok; + } + else + { + const uint32_t *topsmSourcePointer = image->image; + uint32_t *ram = (uint32_t *) destinationAddress; + uint32_t length = image->imageLen; + + if (length > (TOPSM_RAM_SZ / sizeof(uint32_t))) + { + /* Image too long */ + result = SetupResult_ErrorImageLen; + } + else + { + uint32_t i = 0; + /* Check if the image is 128-bit aligned, and if not, read out 32-bit word(s) */ + while ((((uintptr_t) topsmSourcePointer) & 0x0F) != 0) + { + *ram++ = *topsmSourcePointer++; + i++; + } + /* Load most of the image using aligned 128-bit reads */ +#ifdef DeviceFamily_CC27XX + /* We don't need to use HWREG_READ_LRF every time, as the loop only writes to RAM without registers inbetween, but we should protect the first write */ + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + while (i < length - 3) + { +#ifdef NO_INLINE_ASM + struct quadword { + uint32_t word[4]; + }; + *((struct quadword *) ram) = *((const struct quadword *) topsmSourcePointer); + topsmSourcePointer += 4; + ram += 4; +#else + __asm( + "LDMIA %0!, {r4, r5, r6, r7} \n" + "STMIA %1!, {r4, r5, r6, r7} \n" + : "+r" (topsmSourcePointer), + "+r" (ram) : + : "r4", "r5", "r6", "r7" + ); +#endif + i += 4; + } + + /* If one or more 32-bit word is left, read it here */ + while (i < length) + { + *ram++ = *topsmSourcePointer++; + i++; + } + result = SetupResult_Ok; + } + } + return result; +} + +void LRF_initSettingsState(LRF_ApplySettingsState *state, + LRF_ApplySettingsBase includeBase, + uint16_t phyFeatures) +{ + LRF_resetSettingsState(state); + state->includeBase = includeBase; + state->phyFeatures = phyFeatures; +} + +LRF_SetupResult LRF_applySettings(LRF_ConfigWord *config, + LRF_ApplySettingsState *state, + int32_t bufferAvailWords) +{ +#ifdef BUFFER_SPLIT_SUPPORT + uint32_t totalLength = state->totalLength; +#else + (void)bufferAvailWords; +#endif + uint32_t segmentLength; + uint32_t regionLength; + LRF_RegionOperation operation = LRF_RegionOperation_Invalid; + uintptr_t address = 0; + + /* If settings is NULL, ignore the entry */ + if (config == NULL) + { + return SetupResult_Ok; + } + + /* Use 32-bit pointer to read entries to ensure compailer doesn't insert + 16-bit reads toward (possible) flash */ + uint32_t *curEntry = &config->value32; + + /* Initialize state if starting fresh */ +#ifdef BUFFER_SPLIT_SUPPORT + if (totalLength == 0) + { + if (bufferAvailWords < 2) + { + return SetupResult_ErrorElemLen; + } + LRF_ConfigWord curWord; + curWord.value32 = *curEntry; + totalLength = curWord.segment.length; /* Total length is at least segment */ + + segmentLength = 0; /* Expect region header next */ + regionLength = 0; /* Read segment next */ + if (curWord.segment.compoundSegment != 0) + { + if (totalLength > MAX_REG_CONFIG_LEN || totalLength == 0) + { + /* Too long or non-existent entry */ + return SetupResult_ErrorConfigLen; + + } + +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "New compound configration, length is %d", totalLength); +#endif + + /* Get subsegment length from next word */ + curEntry++; + bufferAvailWords--; /* Decrement available words */ + } + else + { + totalLength += 1; /* Simulate a compound header */ +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "New configration, length is %d", totalLength); +#endif + } + + address = 0; + operation = LRF_RegionOperation_Invalid; + + } + else + { + segmentLength = state->segmentLength; + regionLength = state->regionLength; + operation = state->operation; + address = state->address; + + totalLength -= segmentLength; + /* Check if we have words left to skip from last round */ + if (operation == LRF_RegionOperation_Skip) + { + bufferAvailWords -= regionLength; + curEntry += regionLength; + if (bufferAvailWords < 0) + { + /* Still more words to skip */ + segmentLength = -bufferAvailWords; /* Number of words left of segment */ + /* Add unprocessed part of segment back */ + totalLength += segmentLength; + state->regionLength = -bufferAvailWords; /* Signal number of words to skip */ + state->segmentLength = segmentLength; + state->totalLength = totalLength; + return SetupResult_Ok_Partial; + } + else + { + /* Start new segment */ + segmentLength = 0; + operation = LRF_RegionOperation_Invalid; + } + } +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "Resuming, totalLength:%d, segmentLength:%d address:0x%04X", totalLength, segmentLength, address & 0xffff); +#endif + } +#endif + + /* While entire segment not parsed, go on. Can abort in the middle if error or + * out of data */ +#ifdef BUFFER_SPLIT_SUPPORT + while (totalLength + segmentLength > 0) +#endif + { +#ifdef BUFFER_SPLIT_SUPPORT + if (segmentLength == 0) +#endif + { + /* If segment length is 0, process new segment */ + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; + uint16_t featureMask = curWord.segment.featureMask; + if ((curWord.segment.invertedFeatureMask == 0 && + ((featureMask != 0 && (featureMask & state->phyFeatures) == 0) || + (featureMask == 0 && !state->includeBase))) || + (curWord.segment.invertedFeatureMask != 0 && (featureMask != (featureMask & ~state->phyFeatures)))) + { + /* We skip it */ +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "Skipping segment length %1d because invertedFeatureMask = %1d, phyFeatures is 0x%04X and segment's featureMask is 0x%04X", curWord.segment.length, curWord.segment.invertedFeatureMask, state->phyFeatures, featureMask); +#endif +#ifdef BUFFER_SPLIT_SUPPORT + uint32_t skipSegmentLength = curWord.segment.length; + bufferAvailWords -= skipSegmentLength + 1; + totalLength -= skipSegmentLength + 1; + + if (bufferAvailWords < 0) + { + segmentLength = -bufferAvailWords; /* Signal number of words to skip */ + regionLength = segmentLength; + operation = LRF_RegionOperation_Skip; /* Skip when resuming */ + bufferAvailWords = 0; + } + else + { + curEntry += skipSegmentLength; + segmentLength = 0; + } +#else + segmentLength = 0; + return SetupResult_Ok; +#endif + } + else + { + segmentLength = curWord.segment.length; +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "New segment, segmentLength:%d", segmentLength); +#endif + +#ifdef BUFFER_SPLIT_SUPPORT + if (segmentLength == 0 || segmentLength >= totalLength) + { + return SetupResult_ErrorConfigLen; + } + bufferAvailWords--; + totalLength -= segmentLength + 1; +#else + if (segmentLength == 0 || segmentLength >= MAX_REG_CONFIG_LEN) + { + return SetupResult_ErrorConfigLen; + } +#endif + regionLength = 0; /* Read segment next */ + } + } + while (segmentLength > 0) + { +#ifdef BUFFER_SPLIT_SUPPORT + if (bufferAvailWords == 0) + { + /* Add unprocessed part of segment back */ + totalLength += segmentLength; + state->totalLength = totalLength; + state->segmentLength = segmentLength; + state->regionLength = regionLength; + state->operation = operation; + state->address = address; + + return SetupResult_Ok_Partial; + } +#endif + /* If regionLength is 0 we are expecting a region header */ + if (regionLength == 0) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; + regionLength = curWord.region.lengthMinus1 + 1; + operation = (LRF_RegionOperation) curWord.region.type; + uint32_t regionStart = curWord.region.startAddress; + + /* Accounting. Parsed a region header, so consume+increment word and + * parsed count */ + segmentLength--; +#ifdef BUFFER_SPLIT_SUPPORT + bufferAvailWords--; +#endif + /* Find correct region base address */ + if (operation >= SW_Region_Clear && operation != HW_Write_16bit_masked) + { + if (operation >= Par_Region_Clear) + { + address = ((uintptr_t) &swParamList) + regionStart; + uint32_t regionActualLength = (operation == Par_Reference_32bit) ? 1 : regionLength; + if ((regionStart + (regionActualLength * sizeof(uint32_t))) > swParamListSz) + { + return SetupResult_ErrorParRange; + } + } + else + { + address = PBE_RAM_BASE_ADDR + regionStart; + } + } + else + { + address = LRF_BASE_ADDR + regionStart; + } +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "New region, regionLength:%d address:0x%04X, operation:%d", regionLength, address & 0xffff, operation); +#endif + } + + /* Shuffle the data as requested */ + uint32_t numWords; + switch (operation) + { + case HW_Region_Clear: + case Par_Region_Clear: + { + if ((address & 0x03) != 0) + { + return SetupResult_ErrorElemAddrAlign; + } + volatile uint32_t *clear32 = (uint32_t *) address; + for (uint32_t i = 0; i < regionLength; i++) + { +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(clear32++) = 0; +#else + *clear32++ = 0; +#endif //DeviceFamily_CC27XX + } + regionLength = 0; + numWords = 0; + } + break; + + case SW_Region_Clear: + { + if ((address & 0x01) != 0) + { + return SetupResult_ErrorElemAddrAlign; + } + volatile uint16_t *clear16 = (uint16_t *) address; + for (uint32_t i = 0; i < regionLength; i++) + { +#ifdef DeviceFamily_CC27XX + HWREGH_WRITE_LRF(clear16++) = 0; +#else + *clear16++ = 0; +#endif //DeviceFamily_CC27XX + } + regionLength = 0; + numWords = 0; + } + break; + + case HW_Write_16bit: + case SW_Write_16bit: + /* Two output words per input words. If number of input + word is odd, last half-word is taken separately */ + if ((address & 0x01) != 0) + { + return SetupResult_ErrorElemAddrAlign; + } + numWords = regionLength / 2; + break; + + case HW_Write_16bit_masked: + if ((address & 0x01) != 0) + { + return SetupResult_ErrorElemAddrAlign; + } + numWords = regionLength; + break; + + case Par_Reference_32bit: + case HW_Write_32bit: + case SW_Write_32bit: + case Par_Write_32bit: + case HW_Write_16bit_sparse: + case SW_Write_16bit_sparse: + if ((address & 0x03) != 0) + { + return SetupResult_ErrorElemAddrAlign; + } + numWords = regionLength; + break; + + default: + return SetupResult_ErrorElemType; + } + if (numWords > segmentLength) + { + return SetupResult_ErrorElemLen; + } +#ifdef BUFFER_SPLIT_SUPPORT + if ((int32_t)numWords > bufferAvailWords) + { + numWords = bufferAvailWords; + } +#endif + if (numWords > 0) + { + /* Write as much as we can */ + switch (operation) + { + case HW_Write_16bit: + { + volatile uint32_t *dst32 = (volatile uint32_t *) address; + for (uint32_t i = 0; i < numWords; i++) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCore, Log_INFO1, "HW_Write_16bit: %04X = %08X, ", dst32&0xFFFF, curWord.value32); +#endif + +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(dst32++) = curWord.value16[0]; + HWREG_WRITE_LRF(dst32++) = curWord.value16[1]; +#else + *dst32++ = curWord.value16[0]; + *dst32++ = curWord.value16[1]; +#endif //DeviceFamily_CC27XX + } + regionLength -= 2 * numWords; + address = (uintptr_t) dst32; + } + break; + + case HW_Write_16bit_masked: + { + volatile uint32_t *dst32 = (volatile uint32_t *) address; + for (uint32_t i = 0; i < numWords; i++) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO1, "HW_Write_16bit_Masked: %04X: mask %04X value %04X, ", + dst32&0xFFFF, curWord.masked.mask16, curWord.masked.value16); +#endif + /* On full setup, do not apply mask, as the register is assumed to start at 0 */ + if (state->includeBase) + { +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(dst32++) = curWord.masked.value16; +#else + *dst32++ = curWord.masked.value16; +#endif //DeviceFamily_CC27XX + } + else + { + /* The type is intended for 16-bit registers with 32-bit aperture */ + /* If used on a true 32-bit register, the 16 most significant bits will not be changed */ +#ifdef DeviceFamily_CC27XX + uint32_t oldValue = HWREG_READ_LRF(dst32); + HWREG_WRITE_LRF(dst32++) = (oldValue & ~curWord.masked.mask16) | curWord.masked.value16; +#else + uint32_t oldValue = *dst32; + *dst32++ = (oldValue & ~curWord.masked.mask16) | curWord.masked.value16; +#endif //DeviceFamily_CC27XX + } + } + regionLength -= numWords; + address = (uintptr_t) dst32; + } + break; + + case SW_Write_16bit: + { + volatile uint16_t *dst16 = (volatile uint16_t *) address; + for (uint32_t i = 0; i < numWords; i++) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCore, Log_INFO1, "SW_Write_16bit: %04X = %08X, ", dst16&0xFFFF, curWord.value32); +#endif + +#ifdef DeviceFamily_CC27XX + HWREGH_WRITE_LRF(dst16++) = curWord.value16[0]; + HWREGH_WRITE_LRF(dst16++) = curWord.value16[1]; +#else + *dst16++ = curWord.value16[0]; + *dst16++ = curWord.value16[1]; +#endif //DeviceFamily_CC27XX + } + regionLength -= 2 * numWords; + address = (uintptr_t) dst16; + } + break; + + case HW_Write_32bit: + case SW_Write_32bit: + case Par_Write_32bit: + { + volatile uint32_t *dst32 = (volatile uint32_t *) address; + for (uint32_t i = 0; i < numWords; i++) + { +#ifdef LRF_DEBUG_TRACE + switch(operation) + { + case HW_Write_32bit: + Log_printf(RclCore, Log_INFO1, "HW_Write_32bit: %04X = %08X", dst32&0xffff, *curEntry); + break; + case SW_Write_32bit: + Log_printf(RclCore, Log_INFO1, "SW_Write_32bit: %04X = %08X", dst32&0xffff, *curEntry); + break; + case Par_Write_32bit: + Log_printf(RclCore, Log_INFO1, "Par_Write_32bit: %04X = %08X", dst32&0xffff, *curEntry); + break; + default: + break; + } +#endif +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(dst32++) = *curEntry++; +#else + *dst32++ = *curEntry++; +#endif //DeviceFamily_CC27XX + } + regionLength -= numWords; + address = (uintptr_t) dst32; + } + break; + + case Par_Reference_32bit: + { +#ifdef BUFFER_SPLIT_SUPPORT + /* Embedded constants must be contiguous */ + if ((int32_t)regionLength > bufferAvailWords) + { + return SetupResult_ErrorParRange; + } +#endif + volatile uint32_t **dst32 = (volatile uint32_t **) address; + *dst32 = curEntry; + regionLength -= numWords; + curEntry += numWords; +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCore, Log_INFO1, "Par_Reference_32bit: %04X = %08X", address, *dst32); +#endif + } + break; + + case HW_Write_16bit_sparse: + for (uint32_t i = 0; i < numWords; i++) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; + uint32_t curAddress = curWord.sparse.address; + if ((curAddress & 3) == 0) + { + /* Word aligned access to hardware */ + uint32_t *dst32 = (uint32_t *)(address + curAddress); +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(dst32) = curWord.sparse.value16; +#else + *dst32 = curWord.sparse.value16; +#endif //DeviceFamily_CC27XX + } + else if ((curAddress & 1) == 0) + { + /* Halfword aligned */ + uint16_t *dst16 = (uint16_t *)(address + curAddress); +#ifdef DeviceFamily_CC27XX + HWREGH_WRITE_LRF(dst16) = curWord.sparse.value16; +#else + *dst16 = curWord.sparse.value16; +#endif //DeviceFamily_CC27XX + } + else + { + return SetupResult_ErrorElemAddrAlign; + } +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "HW_Write_16bit_sparse: 0x%04X = 0x%04X", curAddress, curWord.sparse.value16); +#endif + } + regionLength -= numWords; + break; + + case SW_Write_16bit_sparse: + for (uint32_t i = 0; i < numWords; i++) + { + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; + if ((curWord.sparse.address & 1) == 0) + { + /* Word aligned 16 bit access */ + uint16_t *dst16 = (uint16_t *)(address + curWord.sparse.address); +#ifdef DeviceFamily_CC27XX + HWREGH_WRITE_LRF(dst16) = curWord.sparse.value16; +#else + *dst16 = curWord.sparse.value16; +#endif + } + else + { + return SetupResult_ErrorElemAddrAlign; + } +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "SW_Write_16bit_sparse: 0x%04X = 0x%04X", curWord.sparse.address, curWord.sparse.value16); +#endif + } + regionLength -= numWords; + break; + + default: + break; + } +#ifdef BUFFER_SPLIT_SUPPORT + bufferAvailWords -= numWords; +#endif + segmentLength -= numWords; + } + /* Write straggler for 16-bit */ + if (regionLength == 1 && +#ifdef BUFFER_SPLIT_SUPPORT + bufferAvailWords > 0 && +#endif + (operation == HW_Write_16bit || operation == SW_Write_16bit)) + { + if (segmentLength < 1) + { + return SetupResult_ErrorElemLen; + } + if (operation == SW_Write_16bit) + { + volatile uint16_t *dst16 = (volatile uint16_t *) address; + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; +#ifdef DeviceFamily_CC27XX + HWREGH_WRITE_LRF(dst16) = curWord.value16[0]; +#else + *dst16 = curWord.value16[0]; +#endif //DeviceFamily_CC27XX +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "SW_Write_16bit: 0x%04X = 0x%04X, ", dst16&0xFFFF, curWord.value16[0]); +#endif + } + else + { + volatile uint32_t *dst32 = (volatile uint32_t *) address; + LRF_ConfigWord curWord; + curWord.value32 = *curEntry++; +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(dst32) = curWord.value16[0]; +#else + *dst32 = curWord.value16[0]; +#endif //DeviceFamily_CC27XX +#ifdef LRF_DEBUG_TRACE + Log_printf(RclCoreShort, Log_INFO, "HW_Write_16bit: 0x%04X = 0x%04X, ", dst32&0xFFFF, curWord.value16[0]); +#endif + } + regionLength -= 1; +#ifdef BUFFER_SPLIT_SUPPORT + bufferAvailWords--; +#endif + segmentLength--; + } + } + /* Done with this segment and its header */ +#ifdef BUFFER_SPLIT_SUPPORT + if (bufferAvailWords == 0 && totalLength > 0) + { + state->totalLength = totalLength; + state->segmentLength = 0; + state->regionLength = 0; + state->operation = operation; + + return SetupResult_Ok_Partial; + } +#endif + } + +#ifdef BUFFER_SPLIT_SUPPORT + RCL_Debug_assert(totalLength == 0); + + state->totalLength = 0; +#endif + + return SetupResult_Ok; +} + +LRF_TxPowerTable_Entry LRF_TxPowerTable_findValue(const LRF_TxPowerTable *table, LRF_TxPowerTable_Index powerLevel) +{ + if (powerLevel.rawValue == LRF_TxPower_Use_Raw.rawValue) + { + /* Handle special input argument - return raw tx power setting if supported, + invalid value otherwise. */ + return LRF_getRawTxPower(); + } + else if (table != NULL && table->numEntries > 0 && powerLevel.rawValue <= LRF_TxPower_Use_Max.rawValue) + { + if (powerLevel.rawValue == LRF_TxPower_Use_Min.rawValue) + { + /* Handle special input argument - return lowest possible tx power. */ + Log_printf(RclCore, Log_INFO, "Tx table search: lowest possible"); + return table->powerTable[0]; + } + else if (powerLevel.rawValue == LRF_TxPower_Use_Max.rawValue) + { + /* Handle special input argument - return highest possible tx power. */ + Log_printf(RclCore, Log_INFO, "Tx table search: highest possible"); + return table->powerTable[table->numEntries - 1]; + } + else if (table->powerTable[0].power.rawValue > powerLevel.rawValue) + { + /* If the first entry is already larger, then the requested + power level is invalid. */ + Log_printf(RclCore, Log_INFO, "Tx table search: %d too low", powerLevel.rawValue); + return LRF_TxPowerEntry_INVALID_VALUE; + } + else + { + for (size_t i = 1; i < table->numEntries; i++) + { + /* Search for the first entry higher than target power level. */ + if (table->powerTable[i].power.rawValue > powerLevel.rawValue) + { + /* Return last entry that was not larger than target power level. */ + return table->powerTable[i - 1]; + } + } + if (table->powerTable[table->numEntries - 1].power.rawValue == powerLevel.rawValue) + { + /* Return highest value if it matches the requested power level. */ + return table->powerTable[table->numEntries - 1]; + } + else + { + /* If no entries are larger than target power level, then the requested + power level is invalid. */ + Log_printf(RclCore, Log_INFO, "Tx table search: %d too high", powerLevel.rawValue); + return LRF_TxPowerEntry_INVALID_VALUE; + } + } + } + else + { + /* Return invalid value. This covers LRF_TxPower_Use_None. */ + return LRF_TxPowerEntry_INVALID_VALUE; + } +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/LRF.h b/simplelink_lpf3/source/ti/drivers/rcl/LRF.h new file mode 100644 index 00000000..1808f7de --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/LRF.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __lrf_h__ +#define __lrf_h__ + +#include +#include +#include +#include + +#if defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R2) || defined(DeviceFamily_CC27XX) || defined(DeviceFamily_CC23X0R22) || defined(DeviceFamily_CC2340R53) +# include +# include DeviceFamily_constructPath(inc/hw_types.h) +# include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +# include +#endif + +#ifdef DeviceFamily_CC1308 +# define BUFFER_SPLIT_SUPPORT +# include "LRFCC1308.h" +#endif + +/** + * Special value given as a TX power to indicate that the lowest available + * TX power is requested + */ +#define LRF_TxPower_Use_Min ((LRF_TxPowerTable_Index){.rawValue = -128}) +/** + * Special value given as a TX power to indicate that the highest available + * TX power is requested + */ +#define LRF_TxPower_Use_Max ((LRF_TxPowerTable_Index){.rawValue = 125}) +/** + * Special value given as a TX power to indicate that a given raw TX power + * register setting should be used. + */ +#define LRF_TxPower_Use_Raw ((LRF_TxPowerTable_Index){.rawValue = 126}) +/** + * Special value given as a TX power to indicate that a TX power should not + * be programmed; instead, use the register value written through settings or + * register write. + */ +#define LRF_TxPower_None ((LRF_TxPowerTable_Index){.rawValue = 127}) + +/** + * Buffer available limit when no limit exists + * + */ +#define LRF_SETTINGS_BUFFER_UNLIMITED 0x3FFF + +/** + * RSSI value indicating an invalid RSSI + * + */ +#define LRF_RSSI_INVALID (127) + + +typedef enum LRF_RadioState_e { + RadioState_Down = 0, + RadioState_ImagesLoaded, /* TOPsm images loaded, persists */ + RadioState_Configured, /* REGBANK values loaded, no persist */ +} LRF_RadioState; + +/** + * @brief Setup operation result + */ +typedef enum LRF_SetupResult_e { + SetupResult_Ok, /*!< Setup was successful */ + SetupResult_Ok_Partial, /*!< Setup was successful so far, need rest of buffer */ + SetupResult_ErrorImageLen, /*!< An image was too long */ + SetupResult_ErrorConfigLen, /*!< A register configuration table was too long */ + SetupResult_ErrorElemLen, /*!< A register configuration element exceeded the table length */ + SetupResult_ErrorElemType, /*!< A register configuration element had invalid type */ + SetupResult_ErrorElemAddrAlign, /*!< A register configuration element had unsupported address alignment */ + SetupResult_ErrorParRange, /*!< A register parameter element was outside the allowed range */ + SetupResult_ErrorSwConfig, /*!< The swConfig field was NULL */ +} LRF_SetupResult; + +struct LRF_TOPsmImage_s { + uint32_t imageLen; + uint32_t image[]; +}; + +typedef union { + struct { + uint32_t lengthMinus1 : 12; + uint32_t type : 4; + uint32_t startAddress : 16; + } region; + uint32_t value32; + uint16_t value16[2]; + struct { + uint16_t value16; + uint16_t address; + } sparse; + struct { + uint16_t value16; + uint16_t mask16; + } masked; + struct { + uint32_t length : 14; + uint32_t invertedFeatureMask : 1; + uint32_t compoundSegment : 1; + uint32_t featureMask : 16; + } segment; +} LRF_ConfigWord; + +struct LRF_RegConfigList_s { + uint32_t numEntries; + LRF_ConfigWord *entries[]; +}; + +typedef enum { + HW_Region_Clear = 0, + HW_Write_16bit = 1, + HW_Write_32bit = 2, + HW_Write_16bit_sparse = 3, + SW_Region_Clear = 4, + SW_Write_16bit = 5, + SW_Write_32bit = 6, + SW_Write_16bit_sparse = 7, + Par_Region_Clear = 8, + Par_Reference_32bit = 9, + Par_Write_32bit = 10, + HW_Write_16bit_masked = 11, + LRF_RegionOperation_Skip = 254, + LRF_RegionOperation_Invalid = 255, +} LRF_RegionOperation; + +typedef enum { + LRF_ApplySettings_NoBase = 0, + LRF_ApplySettings_IncludeBase = 1, +} LRF_ApplySettingsBase; + +typedef struct { + /* Settings */ + uint16_t phyFeatures; + LRF_ApplySettingsBase includeBase; + +#ifdef BUFFER_SPLIT_SUPPORT + /* State variables */ + bool started; + int32_t totalLength; + uint32_t segmentLength; + + /* State variables for region */ + uintptr_t address; + LRF_RegionOperation operation; + uint32_t regionLength; + uint32_t regionStart; +#endif +} LRF_ApplySettingsState; + +#define LRF_PhyFeatures_Default 0 + +/* The definition below ensures an invalid value runtime and a warning compiletime */ +#define __ERROR_Address_is_in_an_invalid_range_for_LRF_setup 0x00040000 + +#define _ADDRESS_REGION_BIT(_address) \ + ((((((uintptr_t)(_address)) >= (LRF_BASE_ADDR)) && \ + ((uintptr_t)(_address)) < ((LRF_BASE_ADDR) + 0x10000)) ? 0 : \ + ((((uintptr_t)(_address)) >= (PBE_RAM_BASE_ADDR)) && \ + (((uintptr_t)(_address)) < ((PBE_RAM_BASE_ADDR) + 0x10000)) ? \ + 1 : \ + (((((uintptr_t)(_address)) >= 0) && \ + (((uintptr_t)(_address)) < 0x10000)) ? \ + 2 : \ + (__ERROR_Address_is_in_an_invalid_range_for_LRF_setup)))) << 14) + +#define LRF_SETTINGS_CLEAR(_startAddress, _numWords) \ + ((((_numWords) - 1) & 0x0FFF) | \ + _ADDRESS_REGION_BIT(_startAddress) | \ + ((((uintptr_t)(_startAddress)) & 0xFFFF) << 16)) + +#define LRF_SETTINGS_16BIT_BLOCK(_startAddress, _numWords) \ + ((((_numWords) - 1) & 0x0FFF) | \ + _ADDRESS_REGION_BIT(_startAddress) | (1 << 12) | \ + ((((uintptr_t)(_startAddress)) & 0xFFFF) << 16)) + +#define LRF_SETTINGS_16BIT_DUAL_ENTRY(_value0, _value1) \ + (((_value0) & 0xFFFF) | (((_value1) & 0xFFFF) << 16)) + +#define LRF_SETTINGS_32BIT_BLOCK(_startAddress, _numWords) \ + ((((_numWords) - 1) & 0x0FFF) | \ + _ADDRESS_REGION_BIT(_startAddress) | (2 << 12) | \ + ((((uintptr_t)(_startAddress)) & 0xFFFF) << 16)) + +#define LRF_SETTINGS_16BIT_SPARSE_BLOCK(_startAddress, _numWords) \ + ((((_numWords) - 1) & 0x0FFF) | \ + _ADDRESS_REGION_BIT(_startAddress) | (3 << 12)) \ + +#define LRF_SETTINGS_16BIT_SPARSE_ENTRY(_address, _value) \ + (((((uintptr_t)(_address)) & 0xFFFF) << 16) | ((_value) & 0xFFFF)) + +#define LRF_SETTINGS_16BIT_MASKED_BLOCK(_startAddress, _numWords) \ + ((((_numWords) - 1) & 0x0FFF) | (11 << 12) | \ + ((((uintptr_t)(_startAddress)) & 0xFFFF) << 16)) + +#define LRF_SETTINGS_16BIT_MASKED_ENTRY(_mask, _value) \ + ((((_mask) & 0xFFFF) << 16) | ((_value) & 0xFFFF)) + +LRF_SetupResult LRF_setupRadio(const LRF_Config *lrfConfig, uint16_t phyFeatures, LRF_RadioState lrfState); + +LRF_SetupResult LRF_loadImage(const LRF_TOPsmImage *image, uint32_t destinationAddress); + +static inline void LRF_resetSettingsState(LRF_ApplySettingsState *state) +{ +#ifdef BUFFER_SPLIT_SUPPORT + state->totalLength = 0; +#else + (void)state; +#endif +} + +void LRF_initSettingsState(LRF_ApplySettingsState *state, + LRF_ApplySettingsBase includeBase, + uint16_t phyFeatures); +LRF_SetupResult LRF_applySettings(LRF_ConfigWord *config, + LRF_ApplySettingsState *state, + int32_t bufferAvailWords); + +void LRF_enable(void); +void LRF_disable(void); +void LRF_powerDown(void); +void LRF_sendHardStop(void); +void LRF_sendGracefulStop(void); +void LRF_hardStop(void); + +void LRF_waitForTopsmReady(void); +uint32_t LRF_prepareRxFifo(void); +uint32_t LRF_prepareTxFifo(void); +uint32_t LRF_peekRxFifo(int32_t offset); +uint32_t LRF_peekTxFifo(int32_t offset); +uint8_t *LRF_getTxFifoWrAddr(int32_t offset); +void LRF_skipTxFifoWords(uint32_t wordLength); +void LRF_discardRxFifoWords(uint32_t wordLength); +void LRF_readRxFifoWords(uint32_t *data32, uint32_t wordLength); +void LRF_writeTxFifoWords(const uint32_t *data32, uint32_t wordLength); +void LRF_setRxFifoEffSz(uint32_t maxSz); +void LRF_programFrequency(uint32_t frequency, bool tx); +uint32_t LRF_enableSynthRefsys(void); +void LRF_disableSynthRefsys(void); +void LRF_setClockEnable(uint16_t mask, uint8_t entryNumber); +void LRF_clearClockEnable(uint16_t mask, uint8_t entryNumber); +int8_t LRF_readRssi(void); +void LRF_setRawTxPower(uint32_t value, uint32_t temperatureCoefficient); +LRF_TxPowerTable_Entry LRF_getRawTxPower(void); +bool LRF_imagesNeedUpdate(const LRF_Config *lrfConfig); + +/** + * @brief Search for settings corresponding to the highest tx power lower than + * specified value in the tx power table + * + * @param table pointer to the tx power table to be searched + * @param powerLevel maximum allowed power level + * + * @return Settings corresponding to a power level equal to or lower than requested + * or LRF_TxPowerTable_INVALID_VALUE if no valid setting was found. + * + */ +LRF_TxPowerTable_Entry LRF_TxPowerTable_findValue(const LRF_TxPowerTable *table, LRF_TxPowerTable_Index powerLevel); + +void LRF_rclEnableRadioClocks(void); +void LRF_rclDisableRadioClocks(void); + +static inline void LRF_enableHwInterrupt(uint32_t mask) +{ + hal_enable_command_radio_interrupt(mask); +} + +static inline void LRF_disableHwInterrupt(uint32_t mask) +{ + hal_disable_command_radio_interrupt(mask); +} + +static inline void LRF_clearHwInterrupt(uint32_t mask) +{ + hal_clear_command_radio_interrupt(mask); +} + +extern uint32_t swParamList[]; +extern const size_t swParamListSz; + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.c b/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.c new file mode 100644 index 00000000..88162757 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.c @@ -0,0 +1,1538 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== LRFCC23X0.c ======== + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe32.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/rfe_common_ram_regs.h) + + +static uint32_t LRF_findPllMBase(uint32_t frequency); +static uint32_t countLeadingZeros(uint16_t value); +static uint32_t LRF_findCalM(uint32_t frequency, uint32_t prediv); +static uint32_t LRF_findFoff(int32_t frequencyOffset, uint32_t invSynthFreq); +static void LRF_programShape(const LRF_TxShape *txShape, uint32_t deviation, uint32_t invSynthFreq); +static uint32_t LRF_findLog2Bde1(uint32_t demmisc3); +static uint32_t LRF_programPQ(uint32_t pllMBase); +static void LRF_programCMixN(int32_t rxIntFrequency, uint32_t invSynthFreq); +static void LRF_applyTrim(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig); +static void LRF_updateTrim(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig); +static void LRF_setTrimCommon(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig); +static void LRF_setTemperatureTrim(const LRF_TrimDef *trimDef); +static void LRF_temperatureCompensateTrim(const LRF_TrimDef *trimDef); +static uint32_t LRF_findExtTrim1TrimAdjustment(uint32_t temperatureDiff, uint32_t tempThreshFactor, uint32_t maxAdjustment); +static int32_t LRF_findExtTrim0TrimAdjustment(int32_t temperature, int32_t tempCompFactor, int32_t offset); +static uint32_t LRF_scaleFreqWithHFXTOffset(uint32_t frequency); +static void LRF_writeFifoPtr(uint32_t value, uintptr_t regAddr); +static void LRF_writeFifoPtrs(uint32_t value, uintptr_t regAddr0, uintptr_t regAddr1); + +uint32_t swParamList[sizeof(LRF_SwParam)/sizeof(uint32_t)]; +const size_t swParamListSz = sizeof(LRF_SwParam); + +static struct { + const LRF_TOPsmImage *pbeLoaded; + const LRF_TOPsmImage *mceLoaded; + const LRF_TOPsmImage *rfeLoaded; + uint16_t phyFeatures; + LRF_TxPowerTable_Entry currentTxPower; + LRF_TxPowerTable_Entry rawTxPower; +} lrfPhyState = {0}; + +/* Required time from enabling refsys to synth programming */ +#define LRF_REFSYS_ENABLE_TIME RCL_SCHEDULER_SYSTIM_US(30) + +/* Status to tell if the RX FIFO is already in a deallocated state (SRP and RP being the same) */ +static bool rxFifoDeallocated = true; + +LRF_SetupResult LRF_setupRadio(const LRF_Config *lrfConfig, uint16_t phyFeatures, LRF_RadioState lrfState) +{ + enum { + trimNoUpdate, + trimPartialUpdate, + trimFullUpdate + } trimUpdate = trimNoUpdate; + LRF_SetupResult result = SetupResult_Ok; + + if (lrfPhyState.pbeLoaded != lrfConfig->pbeImage || lrfState < RadioState_ImagesLoaded) + { + result = LRF_loadImage(lrfConfig->pbeImage, LRFD_PBERAM_BASE); + lrfPhyState.pbeLoaded = lrfConfig->pbeImage; + } + if ((result == SetupResult_Ok) && + (lrfPhyState.mceLoaded != lrfConfig->mceImage || lrfState < RadioState_ImagesLoaded)) + { + result = LRF_loadImage(lrfConfig->mceImage, LRFD_MCERAM_BASE); + lrfPhyState.mceLoaded = lrfConfig->mceImage; + } + if ((result == SetupResult_Ok) && + (lrfPhyState.rfeLoaded != lrfConfig->rfeImage || lrfState < RadioState_ImagesLoaded)) + { + result = LRF_loadImage(lrfConfig->rfeImage, LRFD_RFERAM_BASE); + lrfPhyState.rfeLoaded = lrfConfig->rfeImage; + } + + if ((result == SetupResult_Ok) && (lrfConfig->regConfigList != NULL)) + { + LRF_ApplySettingsBase includeBase; + + if (lrfState < RadioState_Configured) + { + includeBase = LRF_ApplySettings_IncludeBase; + Log_printf(RclCore, Log_VERBOSE, "Performing full setup"); + trimUpdate = trimFullUpdate; + } + else + { + includeBase = LRF_ApplySettings_NoBase; + if (phyFeatures != lrfPhyState.phyFeatures) + { + Log_printf(RclCore, Log_VERBOSE, "Changing PHY features"); + trimUpdate = trimPartialUpdate; + } + } + if (includeBase == LRF_ApplySettings_IncludeBase || phyFeatures != lrfPhyState.phyFeatures) + { + LRF_ApplySettingsState settingsState; + /* Initialize setup state */ + lrfPhyState.phyFeatures = phyFeatures; + LRF_initSettingsState(&settingsState, includeBase, phyFeatures); + for (uint32_t i = 0; i < lrfConfig->regConfigList->numEntries; i++) + { + LRF_ConfigWord *config = lrfConfig->regConfigList->entries[i]; + + result = LRF_applySettings(config, &settingsState, LRF_SETTINGS_BUFFER_UNLIMITED); + + if (result != SetupResult_Ok) + { + break; + } + } + } + /* Invalidate RSSI value to cover the case in which no RX has run before. */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_RSSI) = LRF_RSSI_INVALID; + /* Set PBE to writing FIFO commands to FCMD */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD) = ((LRFDPBE_BASE + LRFDPBE_O_FCMD) & 0x0FFF) >> 2; + } + + if (result == SetupResult_Ok) + { + LRF_SwParam *swParam = (LRF_SwParam *) swParamList; + + if (swParam->swConfig == NULL) + { + result = SetupResult_ErrorSwConfig; + } + else + { + if (trimUpdate == trimFullUpdate) + { + LRF_applyTrim(swParam->trimDef, swParam->swConfig); + } + else if (trimUpdate == trimPartialUpdate) + { + LRF_updateTrim(swParam->trimDef, swParam->swConfig); + } + else + { + LRF_setTemperatureTrim(swParam->trimDef); + } + } + } + return result; +} + +bool LRF_imagesNeedUpdate(const LRF_Config *lrfConfig) +{ + return ((lrfPhyState.pbeLoaded != lrfConfig->pbeImage && lrfConfig->pbeImage != NULL) || + (lrfPhyState.mceLoaded != lrfConfig->mceImage && lrfConfig->mceImage != NULL) || + (lrfPhyState.rfeLoaded != lrfConfig->rfeImage && lrfConfig->rfeImage != NULL)); +} + +static void LRF_applyTrim(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig) +{ + + if (trimDef != NULL) + { +#ifdef DeviceFamily_CC27XX + if (trimDef->revision >= LRF_TRIM_VERSION_CORRECT_AMOUNT_OF_PA_TRIMS_CC27XX) + { + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_PATRIM01) = trimDef->trim0.pa2trim01; + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_PATRIM23) = trimDef->trim4.pa2trim23; + } + else + { + /* Workaround: Write trim0.pa2trim01 to all trim fields for revisions where all trim fields are not available in apptrims */ + uint16_t paTrim = trimDef->trim0.pa2trim01; + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_PATRIM01) = (paTrim << RFE_COMMON_RAM_PATRIM01_VAL1_S) | (paTrim << RFE_COMMON_RAM_PATRIM01_VAL0_S); + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_PATRIM23) = (paTrim << RFE_COMMON_RAM_PATRIM23_VAL3_S) | (paTrim << RFE_COMMON_RAM_PATRIM23_VAL2_S); + } +#else + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PA0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_PA0) | trimDef->trim0.pa0; +#endif + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_ATSTREFH) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_ATSTREFH) | trimDef->trim0.atstRefH; + + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_LNA) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_LNA) | trimDef->trim1.lna; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) | trimDef->trim1.ifampRfLdo; + +#ifdef DeviceFamily_CC27XX + /* DCOLDO0 Workaround: DCOLDO0:FIRSTTRIM is hardcoded to 8U and DCOLDO0:SECONDTRIM is increased by 10 for CC27XX state B devices (see: RCL-616) + * ASSUMPTION: AppTrims revision on CC27XX state C devices is not smaller than 7 + */ + if (trimDef->revision >= LRF_TRIM_VERSION_STATE_C_TRIM_WORKAROUND_CC27XX) + { + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) | trimDef->trim2.dcoLdo0; + } + else + { + uint32_t trimDcoldo0Val = trimDef->trim2.dcoLdo0; + uint32_t secondTrimVal = (trimDcoldo0Val & LRFDRFE_DCOLDO0_SECONDTRIM_M) >> LRFDRFE_DCOLDO0_SECONDTRIM_S; + + /* Invert bit 3 and 5 to decode the SECONDTRIM value */ + uint32_t secondTrimValDecoded = secondTrimVal ^ LRF_TRIM_DCOLDO0_SECONDTRIM_CODED_BITS_MASK_STATE_B_DCOLDO_WORKAROUND_CC27XX; + uint32_t newSecondTrimVal = secondTrimValDecoded + LRF_TRIM_DCOLDO0_SECONDTRIM_INC_STATE_B_DCOLDO_WORKAROUND_CC27XX; + + /* DCOLDO0[13:8]SECONDTRIM is saturated at 63U */ + if (newSecondTrimVal > LRF_TRIM_DCOLDO0_SECONDTRIM_MAX_STATE_B_DCOLDO_WORKAROUND_CC27XX) + { + newSecondTrimVal = LRF_TRIM_DCOLDO0_SECONDTRIM_MAX_STATE_B_DCOLDO_WORKAROUND_CC27XX; + } + + /* Invert bit 3 and 5 to encode the SECONDTRIM value */ + uint32_t newSecondTrimValCoded = newSecondTrimVal ^ LRF_TRIM_DCOLDO0_SECONDTRIM_CODED_BITS_MASK_STATE_B_DCOLDO_WORKAROUND_CC27XX; + + /* Hardcode the FIRSTTRIM to 8U */ + trimDcoldo0Val = (trimDcoldo0Val & ~LRFDRFE_DCOLDO0_FIRSTTRIM_M) | (LRF_TRIM_DCOLDO0_FIRSTTRIM_VALUE_STATE_B_DCOLDO_WORKAROUND_CC27XX << LRFDRFE_DCOLDO0_FIRSTTRIM_S); + + trimDcoldo0Val = (trimDcoldo0Val & ~LRFDRFE_DCOLDO0_SECONDTRIM_M) | (newSecondTrimValCoded << LRFDRFE_DCOLDO0_SECONDTRIM_S); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) | trimDcoldo0Val; + } +#else + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DCOLDO0) | trimDef->trim2.dcoLdo0; +#endif + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCALDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCALDO) | trimDef->trim2.ifadcAldo; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCDLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCDLDO) | trimDef->trim2.ifadcDldo; + + /* DEMIQMC0 has no fields not to be trimmed */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMIQMC0) = trimDef->trim4.demIQMC0; + + /* Write trim to shadow registers */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_IFAMPRFLDODEFAULT) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) & LRFDRFE_IFAMPRFLDO_TRIM_M; + + LRF_setTrimCommon(trimDef, swConfig); + LRF_temperatureCompensateTrim(trimDef); + } +} + +static void LRF_updateTrim(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig) +{ + if (trimDef != NULL) + { + /* Remove trim fields from registers with BW variations */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCQUANT) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCQUANT) & (~(LRFDRFE_IFADCQUANT_QUANTTHR_M)); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) & (~(LRFDRFE_IFADC0_AAFCAP_M | LRFDRFE_IFADC0_INT2ADJ_M | LRFDRFE_IFADC0_DITHEREN_M | LRFDRFE_IFADC0_DITHERTRIM_M)); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC1) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC1) & (~(LRFDRFE_IFADC1_TRIM_M | LRFDRFE_IFADC1_NRZ_M)); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCLF) = 0; /* All fields are trimmed so everything needs to be cleared */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) & (~LRFDRFE_IFAMPRFLDO_AAFCAP_M); + + LRF_setTrimCommon(trimDef, swConfig); + LRF_setTemperatureTrim(trimDef); + } +} + +static void LRF_setTrimCommon(const LRF_TrimDef *trimDef, const LRF_SwConfig *swConfig) +{ + uint8_t bwIndex = 0; + uint8_t bwIndexDither = 0; + uint8_t revision = trimDef->revision; + if (revision >= LRF_TRIM_MIN_VERSION_FULL_FEATURES) + { + bwIndex = swConfig->bwIndex; + bwIndexDither = swConfig->bwIndexDither; + } + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCQUANT) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCQUANT) | trimDef->trimVariant[bwIndex].ifadcQuant; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) | trimDef->trimVariant[bwIndex].ifadc0; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC1) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC1) | trimDef->trimVariant[bwIndex].ifadc1; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCLF) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADCLF) | trimDef->trimVariant[bwIndex].ifadclf; + + if (revision >= LRF_TRIM_MIN_VERSION_FULL_FEATURES) + { + /* Set AAFCAP according to BW */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFAMPRFLDO) | trimDef->trim4.ifamprfldo[bwIndex]; + + if (bwIndexDither != bwIndex) + { + /* Use different setting of dither settings compared to the rest of the IFADC0 register. */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) = (HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_IFADC0) & ~(LRFDRFE_IFADC0_DITHEREN_M | LRFDRFE_IFADC0_DITHERTRIM_M)) | + (trimDef->trimVariant[bwIndexDither].ifadc0 & (LRFDRFE_IFADC0_DITHEREN_M | LRFDRFE_IFADC0_DITHERTRIM_M)); + } + } +} + +static void LRF_setTemperatureTrim(const LRF_TrimDef *trimDef) +{ + if (trimDef != NULL) + { + /* Remove trim fields from registers with temperature compensation */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOF) = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOF) & (~RFE_COMMON_RAM_DIVLDOF_VOUTTRIM_M); + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOI) = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOI) & (~RFE_COMMON_RAM_DIVLDOI_VOUTTRIM_M); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_TDCLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_TDCLDO) & (~LRFDRFE_TDCLDO_VOUTTRIM_M); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DCO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DCO) & (~LRFDRFE_DCO_TAILRESTRIM_M); + + LRF_temperatureCompensateTrim(trimDef); + } +} + +/* Number of shifts in temperature compensation for fields in lrfdrfeExtTrim1 */ +#define LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP 4U +/* Adjustment per step of DIVLDO at lowest temperature */ +#define LRF_DIVLDO_LOW_TEMP_ADJ_FACTOR 10U +/* Adjustment per step of DIVLDO at highest temperature */ +#define LRF_DIVLDO_HIGH_TEMP_ADJ_FACTOR 10U +/* Adjustment per step of TDCLDO at lowest temperature */ +#define LRF_TDCLDO_LOW_TEMP_ADJ_FACTOR 10U +/* Adjustment per step of TDCLDO at highest temperature */ +#define LRF_TDCLDO_HIGH_TEMP_ADJ_FACTOR 10U +/* Adjustment per step of RTRIM at lowest temperature */ +#define LRF_RTRIM_LOW_TEMP_ADJ_FACTOR 1U +/* Adjustment per step of RTRIM at highest temperature */ +#define LRF_RTRIM_HIGH_TEMP_ADJ_FACTOR 1U +/* Maximum allowed value (saturation value) for RTRIM, except if RTRIM value in FCFG is above this level */ +#define LRF_DEFAULT_RTRIM_MAX 12U + +/* Number of shifts in temperature compensation for fields in lrfdrfeExtTrim0 */ +#define LRF_EXTTRIM0_TEMPERATURE_SCALE_EXP 7 + +/* Lowest temperature supported */ +#define LRF_TEMPERATURE_MIN (-40) +/* Highest temperature supported */ +#define LRF_TEMPERATURE_MAX 125 +/* Nominal temperature for offset definitions */ +#define LRF_TEMPERATURE_NOM 25 + +/* Bit masks and positions in SPARE0 and SPARE1 */ +/* RFE_SPARE0: Fast AGC only */ +#define RFE_SPARE0_LOW_GAIN_BM 0x000F +#define RFE_SPARE0_LOW_GAIN 0 +#define RFE_SPARE0_HIGH_GAIN_BM 0x00F0 +#define RFE_SPARE0_HIGH_GAIN 4 +/* RFE_SPARE1: Fast AGC: Threshold. Standard AGC: Magnitude */ +/* These fields have the same position in the register */ +#define RFE_SPARE1_AGC_VALUE_BM 0x000FF +#define RFE_SPARE1_AGC_VALUE 0 + +static void LRF_temperatureCompensateTrim(const LRF_TrimDef *trimDef) +{ + uint32_t divLdoTempOffset = 0; + uint32_t tdcLdoTempOffset = 0; + uint32_t rtrimTempOffset = 0; + int32_t rssiTempOffset = 0; + int32_t agcValOffset = 0; + int32_t agcHighGainOffset = 0; + int32_t agcLowGainOffset = 0; + + if (trimDef->revision >= LRF_TRIM_MIN_VERSION_FULL_FEATURES) + { + int32_t temperature = hal_get_temperature(); + + LRF_Trim_tempLdoRtrim tempLdoRtrim = trimDef->trim3.fields.lrfdrfeExtTrim1.tempLdoRtrim; + + int32_t tempThreshLow = LRF_TEMPERATURE_MIN + tempLdoRtrim.tThrl * (1 << LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP); + int32_t tempThreshHigh = LRF_TEMPERATURE_MAX - tempLdoRtrim.tThrh * (1 << LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP); + + /* Adjust values for extreme temperatures */ + if (temperature < tempThreshLow) + { + uint32_t temperatureDiff = tempThreshLow - temperature; + divLdoTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrl, + LRF_DIVLDO_LOW_TEMP_ADJ_FACTOR * tempLdoRtrim.divLdoMinOffset); + tdcLdoTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrl, + LRF_TDCLDO_LOW_TEMP_ADJ_FACTOR * tempLdoRtrim.tdcLdoMinOffset); + rtrimTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrl, + LRF_RTRIM_LOW_TEMP_ADJ_FACTOR * tempLdoRtrim.rtrimMinOffset); + } + else if (temperature > tempThreshHigh) + { + uint32_t temperatureDiff = temperature - tempThreshHigh; + divLdoTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrh, + LRF_DIVLDO_HIGH_TEMP_ADJ_FACTOR * tempLdoRtrim.divLdoMaxOffset); + tdcLdoTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrh, + LRF_TDCLDO_HIGH_TEMP_ADJ_FACTOR * tempLdoRtrim.tdcLdoMaxOffset); + rtrimTempOffset = LRF_findExtTrim1TrimAdjustment(temperatureDiff, tempLdoRtrim.tThrh, + LRF_RTRIM_HIGH_TEMP_ADJ_FACTOR * tempLdoRtrim.rtrimMaxOffset); + } + + rssiTempOffset = LRF_findExtTrim0TrimAdjustment(temperature, trimDef->trim3.fields.lrfdrfeExtTrim0.rssiTcomp, 0); + + if (((HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_AGCINFO) & RFE_COMMON_RAM_AGCINFO_MODE_M) >> RFE_COMMON_RAM_AGCINFO_MODE_S) == (RFE_COMMON_RAM_AGCINFO_MODE_FAST >> RFE_COMMON_RAM_AGCINFO_MODE_S)) + { + /* Fast AGC */ + agcValOffset =LRF_findExtTrim0TrimAdjustment(temperature, trimDef->trim3.fields.lrfdrfeExtTrim0.agcThrTcomp, + trimDef->trim3.fields.lrfdrfeExtTrim0.agcThrOffset); + agcHighGainOffset = trimDef->trim3.fields.lrfdrfeExtTrim0.highGainOffset; + agcLowGainOffset = trimDef->trim3.fields.lrfdrfeExtTrim0.lowGainOffset; + } + else + { + /* Standard AGC */ + agcValOffset = LRF_findExtTrim0TrimAdjustment(temperature, trimDef->trim3.fields.lrfdrfeExtTrim0.magnTcomp, + trimDef->trim3.fields.lrfdrfeExtTrim0.magnOffset); + } + } + + uint32_t divLdoVoutTrim = trimDef->trim1.fields.divLdo.voutTrim; + + /* Most significant bit is inverted */ + divLdoVoutTrim ^= 0x40; + + divLdoVoutTrim += divLdoTempOffset; + + /* Saturate at maximum value */ + if (divLdoVoutTrim > (LRFDRFE_DIVLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S)) + { + divLdoVoutTrim = (LRFDRFE_DIVLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S); + } + /* Write back with most signigicant bit inverted back */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOF) = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOF) | ((divLdoVoutTrim ^ 0x40) << RFE_COMMON_RAM_DIVLDOF_VOUTTRIM_S); + + /* Add offset to initial value */ + divLdoVoutTrim += HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOIOFF); + + /* Saturate at maximum value */ + if (divLdoVoutTrim > (LRFDRFE_DIVLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S)) + { + divLdoVoutTrim = (LRFDRFE_DIVLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S); + } + /* Write back with most signigicant bit inverted back */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOI) = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_DIVLDOI) | ((divLdoVoutTrim ^ 0x40) << RFE_COMMON_RAM_DIVLDOI_VOUTTRIM_S); + + uint32_t tdcLdoVoutTrim = trimDef->trim1.fields.tdcLdo.voutTrim; + + if (tdcLdoTempOffset > 0) + { + /* Most significant bit is inverted */ + tdcLdoVoutTrim ^= 0x40; + + tdcLdoVoutTrim += tdcLdoTempOffset; + + /* Saturate at maximum value */ + if (tdcLdoVoutTrim > (LRFDRFE_TDCLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S)) + { + tdcLdoVoutTrim = (LRFDRFE_TDCLDO_VOUTTRIM_ONES >> LRFDRFE_DIVLDO_VOUTTRIM_S); + } + + /* Invert back */ + tdcLdoVoutTrim ^= 0x40; + } + /* Write back */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_TDCLDO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_TDCLDO) | (tdcLdoVoutTrim << LRFDRFE_TDCLDO_VOUTTRIM_S); + +#ifdef DeviceFamily_CC27XX + /* RTRIM Workaround: hardcode the RTRIM to 10U rather than read it from FCFG for CC27XX state B devices (see: RCL-591) + * ASSUMPTION: AppTrims revision on CC27XX state C devices is not smaller than 7 + */ + uint32_t rtrim; + if (trimDef->revision >= LRF_TRIM_VERSION_STATE_C_TRIM_WORKAROUND_CC27XX) + { + rtrim = trimDef->trim2.fields.dco.tailresTrim; + } + else + { + rtrim = LRF_TRIM_RTRIM_VALUE_STATE_B_RTRIM_WORKAROUND_CC27XX; + } +#else + uint32_t rtrim = trimDef->trim2.fields.dco.tailresTrim; +#endif + /* Temperature compensation and PHY offset can only be applied if the value is not above the saturation level */ + /* If RTRIM from FCFG is above this, always use that level */ + if (rtrim < LRF_DEFAULT_RTRIM_MAX) + { + /* Add offset from temperature compensation */ + rtrim += rtrimTempOffset; + + /* Add offset from PHY */ + rtrim += HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_RTRIMOFF); + + /* Saturate */ + if (rtrim > LRF_DEFAULT_RTRIM_MAX) + { + rtrim = LRF_DEFAULT_RTRIM_MAX; + } + } + + /* Ensure it is not smaller than minimum from PHY */ + uint32_t minRtrim = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_RTRIMMIN); + if (rtrim < minRtrim) + { + rtrim = minRtrim; + } + + /* Write into register */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DCO) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DCO) | (rtrim << LRFDRFE_DCO_TAILRESTRIM_S); + + /* Get RSSI offset from FCFG */ + int32_t rssiOffset = trimDef->trim4.rssiOffset; + +#if defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R22) || defined(DeviceFamily_CC2340R53) + /* RCL-335: Some devices (State D) have an error in the programmed RSSI offset */ + if (trimDef->revision == LRF_TRIM_VERSION_RSSIOFFSET_ISSUE_CC23X0R5) + { + if (rssiOffset <= LRF_TRIM_LIMIT_RSSIOFFSET_ISSUE_CC23X0R5) + { + rssiOffset += LRF_TRIM_CORRECTION_RSSIOFFSET_ISSUE_CC23X0R5; + } + } +#endif + + /* Apply temperature compensation */ + rssiOffset += rssiTempOffset; + + /* Apply PHY specific offset */ + rssiOffset += HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_PHYRSSIOFFSET); + + /* Store in HW register */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_RSSIOFFSET) = rssiOffset; + + if (((HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_AGCINFO) & RFE_COMMON_RAM_AGCINFO_MODE_M) >> RFE_COMMON_RAM_AGCINFO_MODE_S) == (RFE_COMMON_RAM_AGCINFO_MODE_FAST >> RFE_COMMON_RAM_AGCINFO_MODE_S)) + { + uint32_t spare0Val = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_SPARE0SHADOW); + if (agcHighGainOffset != 0 || agcLowGainOffset != 0) + { + int32_t lowGain = (spare0Val & RFE_SPARE0_LOW_GAIN_BM) >> RFE_SPARE0_LOW_GAIN; + int32_t highGain = (spare0Val & RFE_SPARE0_HIGH_GAIN_BM) >> RFE_SPARE0_HIGH_GAIN; + if (agcLowGainOffset != 0) + { + lowGain += agcLowGainOffset; + if (lowGain < 0) + { + lowGain = 0; + } + if (lowGain > (RFE_SPARE0_LOW_GAIN_BM >> RFE_SPARE0_LOW_GAIN)) + { + lowGain = (RFE_SPARE0_LOW_GAIN_BM >> RFE_SPARE0_LOW_GAIN); + } + } + if (agcHighGainOffset != 0) + { + highGain += agcHighGainOffset; + if (highGain < 0) + { + highGain = 0; + } + if (highGain > (RFE_SPARE0_HIGH_GAIN_BM >> RFE_SPARE0_HIGH_GAIN)) + { + highGain = (RFE_SPARE0_HIGH_GAIN_BM >> RFE_SPARE0_HIGH_GAIN); + } + } + spare0Val = (spare0Val & ~(RFE_SPARE0_LOW_GAIN_BM | RFE_SPARE0_HIGH_GAIN_BM)) | + (lowGain << RFE_SPARE0_LOW_GAIN) | (highGain << RFE_SPARE0_HIGH_GAIN); + } + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE0) = spare0Val; + } + + uint32_t spare1Val = HWREGH_READ_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_SPARE1SHADOW); + if (agcValOffset != 0) + { + int32_t agcVal = (spare1Val & RFE_SPARE1_AGC_VALUE_BM) >> RFE_SPARE1_AGC_VALUE; + agcVal += agcValOffset; + if (agcVal < 0) + { + agcVal = 0; + } + if (agcVal > (RFE_SPARE1_AGC_VALUE_BM >> RFE_SPARE1_AGC_VALUE)) + { + agcVal = (RFE_SPARE1_AGC_VALUE_BM >> RFE_SPARE1_AGC_VALUE); + } + spare1Val = (spare1Val & ~RFE_SPARE1_AGC_VALUE_BM) | (agcVal << RFE_SPARE1_AGC_VALUE); + } + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE1) = spare1Val; +} + +/* Represent 1/3 with the approximation LRF_ONE_THIRD_MANTISSA * 2^(-LRF_ONE_THIRD_NEG_EXP) */ +#define LRF_ONE_THIRD_MANTISSA 21845U /* (round(1/3 * 2^16)) */ +#define LRF_ONE_THIRD_NEG_EXP 16 +/* Calculate temperature compensation for the fields in lrfdrfeExtTrim1 */ +/* temperatureDiff: absolute difference from calculated temperature threshold */ +/* tempThreshFactor: Temperature Threshold field as defined in the trim spec: + The temperature threshold is given by (125 - tempThreshFactor * 2^k) for high temperatures and + (-40C + tempThreshFactor * 2^k) for low temperatures, where k = LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP. */ +/* maxAdjustment: The adjustment to apply at the extreme temperature */ +/* Return: Adjustment to add to value */ +static uint32_t LRF_findExtTrim1TrimAdjustment(uint32_t temperatureDiff, uint32_t tempThreshFactor, uint32_t maxAdjustment) +{ + uint32_t adjustment; + /* Calculate adjustment = round((temperatureDiff * maxAdjustment) / (tempThreshFactor * 2^LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP)) */ + switch (tempThreshFactor) + { + case 0: + default: + /* tempThreshFactor = 0: + No temperatures will be in the range for adjustment */ + adjustment = 0; + break; + case 1: + /* tempThreshFactor = 1: + adjustment = round((temperatureDiff * maxAdjustment) / (1 * 2^LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP)) */ + adjustment = ((temperatureDiff * maxAdjustment) + (1 << (LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP - 1))) >> LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP; + break; + case 2: + /* tempThreshFactor = 2: + adjustment = round((temperatureDiff * maxAdjustment) / (2 * 2^LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP)) */ + adjustment = ((temperatureDiff * maxAdjustment) + (1 << LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP)) >> (LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP + 1); + break; + case 3: + /* tempThreshFactor = 3: + adjustment = round((temperatureDiff * maxAdjustment) / (3 * 2^LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP)) + Use approximation with multiplication to avoid performing division */ + adjustment = ((temperatureDiff * maxAdjustment * LRF_ONE_THIRD_MANTISSA) + (1 << (LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP + LRF_ONE_THIRD_NEG_EXP - 1))) + >> (LRF_EXTTRIM1_TEMPERATURE_SCALE_EXP + LRF_ONE_THIRD_NEG_EXP); + break; + } + return adjustment; +} + +/* Calculate temperature compensation for the fields in lrfdrfeExtTrim0 */ +/* temperature: temperature (degrees C) */ +/* tempCompFactor: Temperature compensation coefficient used to find offset from the formula ((temperature - 25) * tempCompFactor) / 128 */ +/* offset: Absolute offset to apply independent of temperature */ +/* Return: Adjustment to add to value */ +static int32_t LRF_findExtTrim0TrimAdjustment(int32_t temperature, int32_t tempCompFactor, int32_t offset) +{ + return (((temperature - LRF_TEMPERATURE_NOM) * tempCompFactor) >> LRF_EXTTRIM0_TEMPERATURE_SCALE_EXP) + offset; +} + +void LRF_enable(void) +{ + /* Set MSGBOX register to 0 */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_MSGBOX) = 0; + + /* Initialize and enable PBE TOPsm and FIFO */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_INIT) = ((1 << LRFDPBE_INIT_MDMF_S) | + (1 << LRFDPBE_INIT_TOPSM_S)); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_ENABLE) = ((1 << LRFDPBE_ENABLE_MDMF_S) | + (1 << LRFDPBE_ENABLE_TOPSM_S)); + + /* Initialize and enable MCE TOPsm and FIFO */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_INIT) = ((1 << LRFDMDM_INIT_TXRXFIFO_S) | + (1 << LRFDMDM_INIT_TOPSM_S)); + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_ENABLE) = ((1 << LRFDMDM_ENABLE_TXRXFIFO_S)| + (1 << LRFDMDM_ENABLE_TOPSM_S)); + + /* Initialize and enable RFE TOPsm */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_INIT) = (1 << LRFDRFE_INIT_TOPSM_S); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_ENABLE) = (1 << LRFDRFE_ENABLE_TOPSM_S); +} + +void LRF_disable(void) +{ + /* Request PBE powerdown */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_PDREQ) = LRFDPBE_PDREQ_TOPSMPDREQ_M; + /* Disable all PBE modules */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_ENABLE) = 0; + /* Stop powerdown request */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_PDREQ) = 0; + + /* Request MCE powerdown */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_PDREQ) = LRFDMDM_PDREQ_TOPSMPDREQ_M; + /* Disable all MDM modules */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_ENABLE) = 0; + /* Stop powerdown request */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_PDREQ) = 0; + + /* Request RFE powerdown */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PDREQ) = LRFDRFE_PDREQ_TOPSMPDREQ_M; + /* Disable all RFE modules */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_ENABLE) = 0; + /* Stop powerdown request */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PDREQ) = 0; +} + +void LRF_waitForTopsmReady(void) +{ + /* Make sure PBE is finished booting */ + /* This poll should be quick as long as the TOPsms have been reset and enabled */ + while (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_MSGBOX) == 0) + { + } +} + +uint32_t LRF_prepareRxFifo(void) +{ + uint32_t fifoSize; + /* Reset RXFIFO. NOTE: Only allowed while PBE is not running, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_RXFIFO_RESET >> LRFDPBE_FCMD_DATA_S); + /* Set up RXFIFO without auto commit or deallocate */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) & (~(LRFDPBE_FCFG0_RXADEAL_M | LRFDPBE_FCFG0_RXACOM_M)); + /* Read writable bytes, which is the FIFO size */ + fifoSize = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFWRITABLE); + /* Write SRP to 0. This sets no available space for writing; to be updated + by calling LRF_setRxFifoEffSz(). + This write can be done without protection since PBE is not allowed to be + running here, ref RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFSRP) = 0; + rxFifoDeallocated = false; + + return fifoSize; +} + +uint32_t LRF_prepareTxFifo(void) +{ + /* Reset RXFIFO. NOTE: Only allowed while PBE is not running, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RESET >> LRFDPBE_FCMD_DATA_S); + /* Set up TXFIFO with auto commit, without auto deallocate */ + uint32_t fcfg0 = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0); + fcfg0 &= ~LRFDPBE_FCFG0_TXADEAL_M; + fcfg0 |= LRFDPBE_FCFG0_TXACOM_M; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) = fcfg0; + /* Return writable bytes, which is the FIFO size */ + return HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWRITABLE); +} + +uint32_t LRF_peekRxFifo(int32_t offset) +{ + int32_t index = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRP) + offset; + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG4) & LRFDPBE_FCFG4_RXSIZE_M) >> LRFDPBE_FCFG4_RXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + + return HWREG_READ_LRF(LRFD_BUFRAM_BASE + (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG3) << 2) + index); +} + +uint32_t LRF_peekTxFifo(int32_t offset) +{ + int32_t index = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFRP) + offset; + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG2) & LRFDPBE_FCFG2_TXSIZE_M) >> LRFDPBE_FCFG2_TXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + return HWREG_READ_LRF(LRFD_BUFRAM_BASE + (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG1) << 2) + index); +} + +uint8_t *LRF_getTxFifoWrAddr(int32_t offset) +{ + int32_t index = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWP) + offset; + return (uint8_t *) (TXF_UNWRAPPED_BASE_ADDR + (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG1) << 2) + index); +} + +/* Use the workaround of RCL-367 to write the FIFO pointer register with + * address regAddr to the given value. This allows PBE to protect against + * writing FCMD at the same time */ +static void LRF_writeFifoPtr(uint32_t value, uintptr_t regAddr) +{ + /* Run in protected region to avoid unnecessary delays */ + uintptr_t key = HwiP_disable(); + /* Direct PBE to write FIFO commands to FSTAT register to make them ignored */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD) = ((LRFDPBE_BASE + LRFDPBE_O_FSTAT) & 0x0FFF) >> 2; + /* Wait a little so that PBE has time to finish any pending command writes */ + /* Do the wait by dummy reads of FIFOCMDADD */ + (void) HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD); + (void) HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD); + /* Write to specified register */ + HWREG_WRITE_LRF(regAddr) = value; + /* Set PBE back to writing FIFO commands to FCMD */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD) = ((LRFDPBE_BASE + LRFDPBE_O_FCMD) & 0x0FFF) >> 2; + + HwiP_restore(key); +} + +/* Use the workaround of RCL-367 to write both FIFO pointer registers with + * addresses regAddr0 and regAddr1 to the given value. This allows PBE to + * protect against writing FCMD at the same time */ +static void LRF_writeFifoPtrs(uint32_t value, uintptr_t regAddr0, uintptr_t regAddr1) +{ + /* Run in protected region to avoid unnecessary delays */ + uintptr_t key = HwiP_disable(); + /* Direct PBE to write FIFO commands to FSTAT register to make them ignored */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD) = ((LRFDPBE_BASE + LRFDPBE_O_FSTAT) & 0x0FFF) >> 2; + /* Wait a little so that PBE has time to finish any pending command writes */ + /* Do the wait by dummy reads of FIFOCMDADD */ + (void) HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD); + (void) HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD); + /* Write to specified registers */ + HWREG_WRITE_LRF(regAddr0) = value; + HWREG_WRITE_LRF(regAddr1) = value; + /* Set PBE back to writing FIFO commands to FCMD */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_FIFOCMDADD) = ((LRFDPBE_BASE + LRFDPBE_O_FCMD) & 0x0FFF) >> 2; + + + HwiP_restore(key); +} + +void LRF_skipTxFifoWords(uint32_t wordLength) +{ + int32_t index = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFRP) + (wordLength * 4); + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG2) & LRFDPBE_FCFG2_TXSIZE_M) >> LRFDPBE_FCFG2_TXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + LRF_writeFifoPtr(index, (LRFDPBE_BASE + LRFDPBE_O_TXFRP)); +} + +void LRF_discardRxFifoWords(uint32_t wordLength) +{ + int32_t index = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRP) + (wordLength * 4); + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG4) & LRFDPBE_FCFG4_RXSIZE_M) >> LRFDPBE_FCFG4_RXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + /* Write updated pointer to rp and srp */ + LRF_writeFifoPtrs(index, (LRFDPBE_BASE + LRFDPBE_O_RXFRP), (LRFDPBE_BASE + LRFDPBE_O_RXFSRP)); + /* RX FIFO is now deallocated */ + rxFifoDeallocated = true; +} + +void LRF_readRxFifoWords(uint32_t *data32, uint32_t wordLength) +{ + /* Due to RCL-367, the packet is read from memory, and the read pointer is updated afterwards */ + /* Pointer to unwrapped FIFO RAM representation */ + uint32_t fifoStart = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG3) & LRFDPBE_FCFG3_RXSTRT_M) >> LRFDPBE_FCFG3_RXSTRT_S) << 2; + uint32_t readPointer = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRP) & ~0x0003; + volatile uint32_t *fifoReadPtr = (volatile uint32_t *) (RXF_UNWRAPPED_BASE_ADDR + fifoStart + readPointer); + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + for (uint32_t i = 0; i < wordLength; i++) { + *data32++ = *fifoReadPtr++; + } + /* Update read pointer */ + int32_t index = readPointer + (wordLength * 4); + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG4) & LRFDPBE_FCFG4_RXSIZE_M) >> LRFDPBE_FCFG4_RXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + LRF_writeFifoPtr(index, (LRFDPBE_BASE + LRFDPBE_O_RXFRP)); + /* RP was moved, so RX FIFO is not deallocated */ + rxFifoDeallocated = false; +} + +void LRF_writeTxFifoWords(const uint32_t *data32, uint32_t wordLength) +{ + /* Due to RCL-367, the packet is written to memory, and the write pointer is updated afterwards */ + /* Pointer to unwrapped FIFO RAM representation */ + uint32_t fifoStart = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG1) & LRFDPBE_FCFG1_TXSTRT_M) >> LRFDPBE_FCFG1_TXSTRT_S) << 2; + uint32_t writePointer = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWP) & ~0x0003; + volatile uint32_t *fifoWritePtr = (volatile uint32_t *) (TXF_UNWRAPPED_BASE_ADDR + fifoStart + writePointer); + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + for (uint32_t i = 0; i < wordLength; i++) { + *fifoWritePtr++ = *data32++; + } + /* Update write pointer */ + int32_t index = writePointer + (wordLength * 4); + int32_t fifosz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG2) & LRFDPBE_FCFG2_TXSIZE_M) >> LRFDPBE_FCFG2_TXSIZE_S) << 2; + if (index >= fifosz) + { + index -= fifosz; + } + LRF_writeFifoPtr(index, (LRFDPBE_BASE + LRFDPBE_O_TXFWP)); +} + +void LRF_setRxFifoEffSz(uint32_t maxSz) +{ + uint32_t fifoSz = ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG4) & LRFDPBE_FCFG4_RXSIZE_M) >> LRFDPBE_FCFG4_RXSIZE_S) << 2; + if (maxSz >= fifoSz) + { + /* Deallocate RX FIFO to get no additional FIFO restriction */ + /* Due to RCL-367, the operation is done with a FIFO pointer register write */ + if (!rxFifoDeallocated) + { + /* We should not do this write if the FIFO was already deallocated, as it would move the SRP one full round */ + LRF_writeFifoPtr(HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRP), (LRFDPBE_BASE + LRFDPBE_O_RXFSRP)); + rxFifoDeallocated = true; + } + } + else { + uint32_t newSrp; + /* A limit of 0 can't be achieved through manipulating SRP. For all practical purposes, a limit of 1 has the same effect. */ + if (maxSz == 0) + { + maxSz = 1; + } + + newSrp = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRP) + maxSz; + if (newSrp >= fifoSz) + { + newSrp -= fifoSz; + } + /* The new SRP value will always be a write forward in the FIFO */ + /* Do not write if the value is the same as before, as this will be + interpreted by the FIFO HW as going a full round forward */ + + if (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFSRP) != newSrp) + { + LRF_writeFifoPtr(newSrp, (LRFDPBE_BASE + LRFDPBE_O_RXFSRP)); + /* SRP is now different from RP, so RX FIFO is not deallocated */ + rxFifoDeallocated = false; + } + } +} + +/* (FXTALINVL + (FXTALINVH << 16)) = round(2^67/48e6) */ +#define FXTALINVL 0x00001E52U +#define FXTALINVH 0x02CBD3F0U +/* (fXtalInv.word[0] + (fXtalInv.word[1] << 16)) = round(2^67/fXtal), where fXtal is clock frequency in Hz */ +/* Only 16 bits are used of word[0] */ +LRF_DoubleWord fXtalInv = +{ + .word = {FXTALINVL, FXTALINVH}, +}; +/* Calculate PLLM base, that is PLLM assuming an FREF corresponding to the crystal frequency */ +/* This can be used to find true PLLM by multiplying with prediv */ +static uint32_t LRF_findPllMBase(uint32_t frequency) +{ + /* 2^51 / fxtal */ + uint32_t frefInv = fXtalInv.word[1]; + + uint32_t pllMBase; + /* Find pllMBase = frequency / fxtal, encoded as <12.18u> */ + /* First, find pllMBase = frequency / fxtal * 2^(51-32) */ + pllMBase = (frefInv >> 16) * (frequency >> 16); + uint32_t tmpPllMBase; + tmpPllMBase = ((frefInv >> 16) * (frequency & 0xFFFFU)) >> 1; + tmpPllMBase += ((frefInv & 0xFFFFU) * (frequency >> 16)) >> 1; + tmpPllMBase += (1U << 14); + tmpPllMBase >>= 15; + pllMBase += tmpPllMBase; + + /* Divide by 2 with rounding to get pllMBase = frequency / fxtal * 2^18 */ + pllMBase += 1; + pllMBase >>= 1; + + return pllMBase; +} + +static uint32_t countLeadingZeros(uint16_t value) +{ + int numZeros = 0; + if (value >= 0x0100) { + value >>= 8; + } + else { + numZeros += 8; + } + if (value >= 0x10) { + value >>= 4; + } + else { + numZeros += 4; + } + if (value >= 0x04) { + value >>= 2; + } + else { + numZeros += 2; + } + if (value >= 0x02) { + /* No need to shift down value since this is the last step */ + } + else { + numZeros += 1; + } + return numZeros; +} + +static uint32_t LRF_findCalM(uint32_t frequency, uint32_t prediv) +{ + /* Find 2^47 / fref = 2^47 * prediv / fxtal */ + uint32_t frefInv = (fXtalInv.word[1] >> 4) * prediv; + /* Round to 2^31 * prediv / fxtal */ + frefInv += 1 << 15; + frefInv >>= 16; + + uint32_t calM; + /* Find calM = frequency / fref (no fractional bits) */ + /* First, find calM = frequency / fref * 2^(31-15)) */ + calM = frefInv * ((frequency + (1 << 14)) >> 15); + + /* Divide by 2^16 with rounding to get calM = frequency / fref */ + calM += 1 << 15; + calM >>= 16; + + return calM; +} + +/* invSynthFreq = 2^47 / synthFrequency */ +static uint32_t LRF_findFoff(int32_t frequencyOffset, uint32_t invSynthFreq) +{ + uint32_t absFrequencyOffset; + int32_t fOffRes; + if (frequencyOffset == 0) + { + return 0; + } + else { + if (frequencyOffset < 0) + { + absFrequencyOffset = -frequencyOffset; + } + else + { + absFrequencyOffset = frequencyOffset; + } + /* Calculate 2^41 * abs(frequencyOffset) / synthFrequency */ + absFrequencyOffset = (absFrequencyOffset + (1U << 5)) >> 6; + absFrequencyOffset *= invSynthFreq; + /* Round to 2^21 * abs(frequencyOffset) / synthFrequency */ + absFrequencyOffset = (absFrequencyOffset + (1U << 19)) >> 20; + /* Re-intruduce sign */ + if (frequencyOffset < 0) + { + fOffRes = -absFrequencyOffset; + } + else + { + fOffRes = absFrequencyOffset; + } + + return (((uint32_t)fOffRes) & LRFDRFE_MOD1_FOFF_M); + } +} + +#define NUM_TX_FILTER_TAPS 24 +/* deviation in Hz */ +/* invSynthFreq = 2^51 / synthFrequency */ +static void LRF_programShape(const LRF_TxShape *txShape, uint32_t deviation, uint32_t invSynthFreq) +{ + /* If txShape is NULL, do not program shape, but instead leave the values programmed as part of setup */ + if (txShape != NULL) + { + union { + uint8_t b[NUM_TX_FILTER_TAPS]; + uint32_t w[NUM_TX_FILTER_TAPS/4]; + } filterCoeff; + /* Find deviation * 2^29/fs * 2^10 */ + uint32_t deviationFactor1 = ((deviation >> 12) * invSynthFreq) + + (((deviation & 0x0FFFU) * invSynthFreq) >> 12); + /* Find deviation * 2^29/fs * scale / 2^16 */ + uint32_t scale = txShape->scale; + uint32_t deviationFactor2 = ((((deviationFactor1 >> 15) * scale) >> 1) + + (((deviationFactor1 & 0x7FFF) * scale) >> 16) + (1 << 4)) >> 5; + /* Find shapeGain and scaling */ + int32_t shapeGain = 8 - countLeadingZeros(deviationFactor2 >> 11); + if (shapeGain < 0) + { + shapeGain = 0; + } + uint32_t startCoeff = NUM_TX_FILTER_TAPS - txShape->numCoeff; + for (uint32_t i = 0; i < startCoeff; i++) + { + filterCoeff.b[i] = 0; + } + for (uint32_t i = 0; i < NUM_TX_FILTER_TAPS - startCoeff; i++) + { + filterCoeff.b[i + startCoeff] = + ((deviationFactor2 * txShape->coeff[i]) + (1 << (18 + shapeGain))) >> (19 + shapeGain); + } + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + for (int i = 0; i < NUM_TX_FILTER_TAPS / 4; i++) + { + *((unsigned long*) (LRFDRFE32_BASE + LRFDRFE32_O_DTX1_DTX0) + i) = filterCoeff.w[i]; + } + if (shapeGain > 3) + { + /* TODO: Scale by adjusting the symbol mapping */ + shapeGain = 3; + } + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MOD0) = (HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_MOD0) & ~LRFDRFE_MOD0_SHPGAIN_M) | (shapeGain << LRFDRFE_MOD0_SHPGAIN_S); + } +} + +static uint32_t LRF_findLog2Bde1(uint32_t demmisc3) +{ + uint32_t log2Bde1; + if ((demmisc3 & LRFDMDM_DEMMISC3_BDE1FILTMODE_M) != 0) + { + log2Bde1 = 0; + } + else + { + log2Bde1 = (demmisc3 & LRFDMDM_DEMMISC3_BDE1NUMSTAGES_M) >> LRFDMDM_DEMMISC3_BDE1NUMSTAGES_S; + } + return log2Bde1; +} + +/* Calculate P as rateWord * bde1 * bde2 * pdifDecim * 9 * 2^4 + Calculate Q as pllMBase * pre + Normalize Q to 28 bits and do the same normalization to P */ +/* Multiplication factor from P formula */ +#define P_FACTOR 9 +/* Shift from P formula */ +#define P_SHIFT 4 +/* Right shift of PLL M to allow 32-bit calculation */ +#define Q_MAGN_SHIFT 6 +/* Number of bits in P and Q */ +#define FRAC_NUM_BITS 28 +/* Number of extra bits in an uint32_t compared to the P and Q HW registers */ +#define FRAC_EXTRA_BITS (32 - FRAC_NUM_BITS) +static uint32_t LRF_programPQ(uint32_t pllMBase) +{ + bool roundingError = false; + uint32_t rateWord = (HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_BAUD) << 5); + rateWord |= ((HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_BAUDPRE) & LRFDMDM_BAUDPRE_EXTRATEWORD_M) >> LRFDMDM_BAUDPRE_EXTRATEWORD_S); + uint32_t pre = (HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_BAUDPRE) & LRFDMDM_BAUDPRE_PRESCALER_M); + uint32_t demmisc3 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC3); + uint32_t log2Bde1 = LRF_findLog2Bde1(demmisc3); + + uint32_t bde2 = (demmisc3 & LRFDMDM_DEMMISC3_BDE2DECRATIO_M) >> LRFDMDM_DEMMISC3_BDE2DECRATIO_S; + uint32_t log2PdifDecim = (demmisc3 & LRFDMDM_DEMMISC3_PDIFDECIM_M) >> LRFDMDM_DEMMISC3_PDIFDECIM_S; + int32_t leftShiftP; + + leftShiftP = log2Bde1 + log2PdifDecim + P_SHIFT; + + uint32_t demFracP = rateWord * bde2; + if (demFracP > (uint32_t)((1ULL << 32) / P_FACTOR)) + { + if ((demFracP & 1) != 0) + { + roundingError = true; + } + demFracP >>= 1; + leftShiftP -= 1; + } + demFracP *= P_FACTOR; + + /* Preliminary calculation to find scaling factor - round PLLM upwards to ensure no overflow + in final calculation */ + uint32_t demFracQ = ((pllMBase + ((1 << Q_MAGN_SHIFT) - 1)) >> Q_MAGN_SHIFT) * pre; + uint32_t num0Q = countLeadingZeros(demFracQ >> 16); + + int32_t pllMShift = Q_MAGN_SHIFT + FRAC_EXTRA_BITS - num0Q; + uint32_t pllMBaseRounded; + if (pllMShift <= 0) + { + pllMBaseRounded = pllMBase; + demFracQ = pllMBase * pre; + int32_t leftShiftQ = -pllMShift; + leftShiftP += leftShiftQ; + /* leftShiftQ is sure to be positive since pllMShift <= 0 */ + demFracQ <<= leftShiftQ; + } + else + { + /* Scale PLLM to allow Q to fit */ + pllMBaseRounded = (pllMBase + (1U << (pllMShift - 1))) >> pllMShift; + demFracQ = pllMBaseRounded * pre; + /* Multiply PLLM back (rounding is now applied) */ + pllMBaseRounded <<= pllMShift; + leftShiftP -= pllMShift; + } + + if (leftShiftP >= 0) + { + demFracP <<= leftShiftP; + } + else + { + /* Check if right shift of P introduces rounding error */ + if ((demFracP & ((1 << -leftShiftP) - 1)) != 0) + { + roundingError = true; + } + demFracP >>= -leftShiftP; + } + + if (demFracP >= demFracQ) + { + Log_printf(RclCore, Log_ERROR, "Error: resampler fraction greater than 1; demodulator will not work"); + } + if (roundingError) + { + Log_printf(RclCore, Log_WARNING, "Rounding error in fractional resampler"); + } + if (pllMBaseRounded != pllMBase) + { + Log_printf(RclCore, Log_INFO, "PLLM base rounded from %08X to %08X to fit in fractional resampler", pllMBase, pllMBaseRounded); + } + +#ifdef DeviceFamily_CC27XX + /* Check if shadow register for downsampler coefficient P is in use */ + if ((HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_BAUDCOMP) & LRFDMDM_BAUDCOMP_FRAC_SHADOW) != 0) + { + /* Write downsampler coefficient P to shadow registers for new Rx operations to restore */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMCOHR3) = demFracP & 0x0000FFFFU; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMCOHR4) = demFracP >> 16; + } +#endif /* DeviceFamily_CC27XX */ + + HWREG_WRITE_LRF(LRFDMDM32_BASE + LRFDMDM32_O_DEMFRAC1_DEMFRAC0) = demFracP; + HWREG_WRITE_LRF(LRFDMDM32_BASE + LRFDMDM32_O_DEMFRAC3_DEMFRAC2) = demFracQ; + + return pllMBaseRounded; +} + +/* invSynthFreq = 2^47 / synthFrequency */ +static void LRF_programCMixN(int32_t rxIntFrequency, uint32_t invSynthFreq) +{ + /* Calculate n = f_if/f_pll*24*12*bde1*1024 + = f_if/f_pll * 2^(15 + log2Bde1) * 9 */ + uint32_t absRxIntFrequency; + if (rxIntFrequency < 0) + { + absRxIntFrequency = -rxIntFrequency; + } + else + { + absRxIntFrequency = rxIntFrequency; + } + + absRxIntFrequency = (absRxIntFrequency + (1 << 5)) >> 6; + /* Find 2^41 * abs(rxIntFrequency) / synthFrequency */ + uint32_t cMixN = absRxIntFrequency * invSynthFreq; + /* Find 2^37 * abs(rxIntFrequency) / synthFrequency * 9 */ + cMixN = ((cMixN + (1 << 3)) >> 4) * 9; + + /* Find 2^(15 + log2Bde1) * abs(rxIntFrequency) / synthFrequency * 9 */ + uint32_t rightShift = (37 - 15) - LRF_findLog2Bde1(HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC3)); + cMixN = (cMixN + (1 << (rightShift - 1))) >> rightShift; + + int32_t signedCMixN; + /* Use inverse sign */ + if (rxIntFrequency > 0) + { + signedCMixN = -cMixN; + } + else + { + signedCMixN = cMixN; + } +#ifdef DeviceFamily_CC27XX + /* Workaround (RCL-489): Invert RX frequency programmed to account for swapped I and Q signals in CC27xx PG1.0 + * TODO: May be swapped back for later PGs + */ + signedCMixN = -signedCMixN; +#endif + + cMixN = (uint32_t)(signedCMixN & LRFDMDM_DEMMISC0_CMIXN_M); + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC0) = cMixN; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_SPARE3) = cMixN; +} + +void LRF_programFrequency(uint32_t frequency, bool tx) +{ + uint32_t synthFrequency; + LRF_SwParam *swParam = (LRF_SwParam *) swParamList; + const LRF_SwConfig *swConfig = swParam->swConfig; + + /* Find frequency corrected for IF. Normally, the result will be the same for tx and rx, and + that is a prerequisite for switching without recalibration. */ + if (tx) + { + synthFrequency = frequency - swConfig->txFrequencyOffset; + } + else + { + synthFrequency = frequency - swConfig->rxFrequencyOffset + - swConfig->rxIntFrequency; + } + + /* Compensate desired frequency for temperature-dependent offset in HFXT, if any */ + uint32_t synthFrequencyCompensated = LRF_scaleFreqWithHFXTOffset(synthFrequency); + + /* Frequency divided by 2^16, rounded */ + uint32_t frequencyDiv2_16 = (synthFrequency + (1 << 15)) >> 16; + + /* Start calculating 2^47/frequency (approximated as 2^31/(synthFrequency/2^16)) */ + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_DIVIDEND) = 1U << 31; + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_DIVISOR) = frequencyDiv2_16; + + /* Write approximate freuency to RFE */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_K5) = frequencyDiv2_16; + + /* Find setting for coarse and mid calibration */ + uint32_t precalSetting = HWREG_READ_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PRE3_PRE2); + uint32_t coarsePrecal = (precalSetting & LRFDRFE32_PRE3_PRE2_CRSCALDIV_M) >> LRFDRFE32_PRE3_PRE2_CRSCALDIV_S; + uint32_t midPrecal = (precalSetting & + (LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_M | LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_M)) + >> LRFDRFE_PRE2_MIDCALDIVLSB_S; + + uint32_t calMCoarse = LRF_findCalM(synthFrequency, coarsePrecal); + uint32_t calMMid; + if (coarsePrecal == midPrecal) + { + calMMid = calMCoarse; + } + else + { + calMMid = LRF_findCalM(synthFrequency, midPrecal); + } + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_CALMMID_CALMCRS) = (calMCoarse << LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_S) | + (calMMid << LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_S); + + precalSetting = HWREG_READ_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PRE1_PRE0); + + uint32_t precal0 = (precalSetting & LRFDRFE32_PRE1_PRE0_PLLDIV0_M) >> LRFDRFE32_PRE1_PRE0_PLLDIV0_S; + uint32_t precal1 = (precalSetting & LRFDRFE32_PRE1_PRE0_PLLDIV1_M) >> LRFDRFE32_PRE1_PRE0_PLLDIV1_S; + + uint32_t pllMBase = LRF_findPllMBase(synthFrequency); + pllMBase = LRF_programPQ(pllMBase); + + uint32_t pllMBaseCompensated; + if (synthFrequencyCompensated == synthFrequency) + { + pllMBaseCompensated = pllMBase; + } + else + { + pllMBaseCompensated = LRF_findPllMBase(synthFrequencyCompensated); + } + + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PLLM0) = ((pllMBaseCompensated * precal0) << LRFDRFE32_PLLM0_VAL_S); + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PLLM1) = ((pllMBaseCompensated * precal1) << LRFDRFE32_PLLM1_VAL_S); + + /* Read out division result to find invSynthFreq */ + while ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DIVSTA) & LRFDRFE_DIVSTA_STAT_M) != 0) + { + } + uint32_t invSynthFreq = HWREG_READ_LRF(LRFDRFE32_BASE + LRFDRFE32_O_QUOTIENT); + + /* Calculate intermediate frequencies */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_RXIF) = LRF_findFoff(swConfig->rxFrequencyOffset, invSynthFreq); + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_TXIF) = LRF_findFoff(swConfig->txFrequencyOffset, invSynthFreq); + + /* Calculate CMIXN */ + LRF_programCMixN(swConfig->rxIntFrequency, invSynthFreq); + + LRF_programShape(swConfig->txShape, swConfig->modFrequencyDeviation, + invSynthFreq << 4); +} + +uint32_t LRF_enableSynthRefsys(void) +{ + uint32_t earliestStartTime; + + /* Enable REFSYS if not already done. If it is enabled now, we need to make sure that start + time is late enough */ + uint32_t atstref = HWREG_READ_LRF(LRFDRFE32_BASE + LRFDRFE32_O_ATSTREF); + if ((atstref & LRFDRFE32_ATSTREF_BIAS_M) == 0) + { + /* Bias not already enabled - enable it now */ + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_ATSTREF) = atstref | LRFDRFE32_ATSTREF_BIAS_M; + /* Set earliest start time of synth to some later time */ + earliestStartTime = LRF_REFSYS_ENABLE_TIME; + } + else + { + /* No restriction on start time */ + earliestStartTime = 0; + } + /* Add current time */ + earliestStartTime += RCL_Scheduler_getCurrentTime(); + + return earliestStartTime; +} + +void LRF_disableSynthRefsys(void) +{ + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_ATSTREF) = HWREG_READ_LRF(LRFDRFE32_BASE + LRFDRFE32_O_ATSTREF) & (~LRFDRFE32_ATSTREF_BIAS_M); +} + +void LRF_rclEnableRadioClocks(void) +{ + LRF_setRclClockEnable(LRFDDBELL_CLKCTL_BUFRAM_M | + LRFDDBELL_CLKCTL_DSBRAM_M | + LRFDDBELL_CLKCTL_RFERAM_M | + LRFDDBELL_CLKCTL_MCERAM_M | + LRFDDBELL_CLKCTL_PBERAM_M | + LRFDDBELL_CLKCTL_RFE_M | + LRFDDBELL_CLKCTL_MDM_M | + LRFDDBELL_CLKCTL_PBE_M); +} + +void LRF_rclDisableRadioClocks(void) +{ + LRF_clearRclClockEnable(LRFDDBELL_CLKCTL_BUFRAM_M | + LRFDDBELL_CLKCTL_DSBRAM_M | + LRFDDBELL_CLKCTL_RFERAM_M | + LRFDDBELL_CLKCTL_MCERAM_M | + LRFDDBELL_CLKCTL_PBERAM_M | + LRFDDBELL_CLKCTL_RFE_M | + LRFDDBELL_CLKCTL_MDM_M | + LRFDDBELL_CLKCTL_PBE_M); +} + +int8_t LRF_readRssi(void) +{ + return (int8_t)(HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_RSSI) & LRFDRFE_RSSI_VAL_M); +} + +void LRF_setRawTxPower(uint32_t value, uint32_t temperatureCoefficient) +{ + lrfPhyState.rawTxPower.value.rawValue = value; + lrfPhyState.rawTxPower.tempCoeff = temperatureCoefficient; + lrfPhyState.rawTxPower.power = LRF_TxPower_Use_Raw; +} + +LRF_TxPowerTable_Entry LRF_getRawTxPower(void) +{ + if (lrfPhyState.rawTxPower.power.rawValue == LRF_TxPower_Use_Raw.rawValue) + { + /* Raw TX power has been set */ + return lrfPhyState.rawTxPower; + } + else + { + /* Error: Raw TX power was never set */ + return LRF_TxPowerEntry_INVALID_VALUE; + } +} + +/* Avoid IB = 0 as it effectively turns the PA off */ +#define RFE_PA0_IB_MIN_USED 1 + +void LRF_programTemperatureCompensatedTxPower(void) +{ + LRF_TxPowerTable_Entry txPowerEntry = lrfPhyState.currentTxPower; + uint8_t tempCoeff = txPowerEntry.tempCoeff; + if (tempCoeff != 0) + { + int32_t ib = txPowerEntry.value.ib; + int32_t temperature = hal_get_temperature(); + /* Linear adjustment of IB field as a function of temperature, scaled + * by the coefficient for the given setting */ + ib += ((temperature - LRF_TXPOWER_REFERENCE_TEMPERATURE) * (int32_t) tempCoeff) + / LRF_TXPOWER_TEMPERATURE_SCALING; + /* Saturate IB */ + if (ib < (int32_t) RFE_PA0_IB_MIN_USED) + { + ib = RFE_PA0_IB_MIN_USED; + } +#ifdef DeviceFamily_CC27XX + /* TODO: See RCL-444. Use LRFDRFE_PA1_IB_MAX for CC27XX. */ + if (ib > (int32_t) (LRFDRFE_PA1_IB_MAX >> LRFDRFE_PA1_IB_S)) + { + ib = LRFDRFE_PA1_IB_MAX >> LRFDRFE_PA1_IB_S; + } +#else + if (ib > (int32_t) (LRFDRFE_PA0_IB_MAX >> LRFDRFE_PA0_IB_S)) + { + ib = LRFDRFE_PA0_IB_MAX >> LRFDRFE_PA0_IB_S; + } +#endif + txPowerEntry.value.ib = ib; + } + /* Program into RFE shadow register for PA power */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE5) = txPowerEntry.value.rawValue; +} + +LRF_TxPowerResult LRF_programTxPower(LRF_TxPowerTable_Index powerLevel) +{ + if (powerLevel.rawValue != LRF_TxPower_None.rawValue) + { + LRF_SwParam *swParam = (LRF_SwParam *) swParamList; + LRF_TxPowerTable_Entry txPowerEntry = LRF_TxPowerTable_findValue(swParam->txPowerTable, powerLevel); + if (txPowerEntry.value.rawValue != LRF_TxPowerTable_INVALID_VALUE.rawValue) + { + lrfPhyState.currentTxPower = txPowerEntry; + LRF_programTemperatureCompensatedTxPower(); + } + else + { + return TxPowerResult_Error; + } + } + return TxPowerResult_Ok; +} + +static uint32_t LRF_scaleFreqWithHFXTOffset(uint32_t frequency) +{ + /* Get HFXT ratio from HFTRACKCTL register. This will have been + * updated by the power driver if compensation is enabled and the temperature has drifted beyond the threshold. + */ + uint32_t ratio = hal_get_hfxt_ratio(); + + /* If temperature compensation is disabled, or temperature has not drifted, + * the ratio will have its reset-value of 0x400000. In this case, do not perform scaling of input frequency + * to save computational cost. + * Rationale: + * ratio = 24 MHz / (2 * HFXT_freq) * 2^24 ==> HFXT_freq = 24 MHz / ratio * 2^23 + * (ref: CKMD.HFTRACKCTL.RATIO register description) + * Nominal HFXT frequency is 48 MHz + * + * frequency_out = frequency_in * HFXT_nominal_freq / HFXT_freq + * = frequency_in * 48 MHz / (24 MHz / ratio * 2^23) + * frequency_out = frequency_in * ratio * 2^-22 + * + * The method below is a computationally cost-effective way to calculate the scaled result. + * Instead of performing 64-bit multiplication and shifting, the multiplier and multiplicand are divided into + * half-words which are multiplied, added, and shifted appropriately. + */ + if (ratio != hal_get_hfxt_ratio_default()) + { + uint32_t ah = frequency >> 16; /* Multiplier high half-word */ + uint32_t al = frequency & 0xFFFF; /* Multiplier low half-word */ + + uint32_t bh = ratio >> 16; /* Multiplicand high half-word */ + uint32_t bl = ratio & 0xFFFF; /* Multiplicand low half-word */ + + /* Perform standard long multiplication where each "digit" is a half-word + * https://en.wikipedia.org/wiki/Multiplication_algorithm + * The rounding error will be maximum 1 Hz in this calculation. + * frequency * ratio >> 22 = [ah al] * [bh bl] >> 22 + * [ah al] * [bh bl] >> 22 = ([bl * al] + (([bl * ah] + [bh * al]) << 16) + ([bh * ah]) << 32) >> 22 + * = (([bl * ah] + [bh * al]) >> 6) + ([bh * ah]) << 10) + */ + frequency = ((bl*ah + bh*al + ((bl*al) >> 16)) >> 6) + ((bh*ah) << 10); + } + + return frequency; +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.h b/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.h new file mode 100644 index 00000000..22f2e508 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/LRFCC23X0.h @@ -0,0 +1,637 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_LRFCC2340_h__include +#define ti_drivers_LRFCC2340_h__include + +#include +#include +#include +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/pbe_generic_regdef_regs.h) + +#include + +/** @brief Type for tx power configuration. + * + * Register value to be written to registers, prior to temperature compensation + */ +#ifdef DeviceFamily_CC27XX +/* TODO: See RCL-556 */ +#define LRFDPBE32_BASE 0x40081400 // LRFDPBE32 +#define LRFDMDM32_BASE 0x40082400 // LRFDMDM32 +#define LRFDRFE32_BASE 0x40083400 // LRFDRFE32 +typedef union +{ + struct { + uint16_t ibBoost: 2; + uint16_t ib: 6; + uint16_t gain: 3; + uint16_t mode: 2; + uint16_t reserved: 2; + uint16_t noIfampRfLdoBypass: 1; + }; + uint16_t rawValue; +} LRF_TxPowerTable_Value; +#else +typedef union +{ + struct { + uint16_t reserved: 5; + uint16_t ib: 6; + uint16_t gain: 3; + uint16_t mode: 1; + uint16_t noIfampRfLdoBypass: 1; + }; + uint16_t rawValue; +} LRF_TxPowerTable_Value; +#endif +#define LRF_TxPowerTable_INVALID_VALUE ((LRF_TxPowerTable_Value){.rawValue = 0xFFFF}) /*!< Value indicating that no valid tx power could be found in the table. */ + +typedef uint8_t LRF_TxPowerTable_TempCoeff; + +typedef enum LRF_TxPowerResult_e { + TxPowerResult_Ok, /*!< TX power value was OK */ + TxPowerResult_Error, /*!< TX power value had an error */ +} LRF_TxPowerResult; + + +#define LRF_EventNone ((LRF_Events){ .value = (0U << 0U)}) /*!< No events */ +#define LRF_EventOpDone ((LRF_Events){ .value = (1U << 0U)}) /*!< The PBE operation has finished */ +#define LRF_EventPingRsp ((LRF_Events){ .value = (1U << 1U)}) /*!< When receiving a CMD_PING, PBE responds with a PINGRSP. */ +#define LRF_EventRxCtrl ((LRF_Events){ .value = (1U << 2U)}) /*!< Frame filtering passed, or LL control packet received correctly */ +#define LRF_EventRxCtrlAck ((LRF_Events){ .value = (1U << 3U)}) /*!< LL control packet received with CRC OK, not to be ignored, then acknowledgement sent */ +#define LRF_EventRxNok ((LRF_Events){ .value = (1U << 4U)}) /*!< Packet received with CRC error */ +#define LRF_EventRxIgnored ((LRF_Events){ .value = (1U << 5U)}) /*!< Packet received, but may be ignored by MCU */ +#define LRF_EventRxEmpty ((LRF_Events){ .value = (1U << 6U)}) /*!< Empty packet received, or Rx ACK treatment finished */ +#define LRF_EventRxBufFull ((LRF_Events){ .value = (1U << 7U)}) /*!< Packet received which did not fit in the RX FIFO and was not to be discarded.  */ +#define LRF_EventRxOk ((LRF_Events){ .value = (1U << 8U)}) /*!< Packet received with CRC OK and not to be ignored by the MCU */ +#define LRF_EventTxCtrl ((LRF_Events){ .value = (1U << 9U)}) /*!< Transmitted LL control packet */ +#define LRF_EventTxCtrlAckAck ((LRF_Events){ .value = (1U << 10U)}) /*!< Acknowledgement received on a transmitted LL control packet, and acknowledgement transmitted for that packet */ +#define LRF_EventTxRetrans ((LRF_Events){ .value = (1U << 11U)}) /*!< Packet retransmitted with same SN */ +#define LRF_EventTxAck ((LRF_Events){ .value = (1U << 12U)}) /*!< Acknowledgement transmitted, or acknowledgement received on a transmitted packet. */ +#define LRF_EventTxDone ((LRF_Events){ .value = (1U << 13U)}) /*!< Packet transmitted */ +#define LRF_EventTxCtrlAck ((LRF_Events){ .value = (1U << 14U)}) /*!< Acknowledgement received on a transmitted LL control packet */ +#define LRF_EventOpError ((LRF_Events){ .value = (1U << 15U)}) /*!< Something went awfully wrong, the reason is indicated in RAM-based register BLE_ENDCAUSE. */ +#define LRF_EventRxfifo ((LRF_Events){ .value = (1U << 16U)}) /*!< Event from fifo, triggered when crossing threshold. Normal use for rxfifo is to generate IRQ when crossing threshold upwards (filling fifo). But downwards is also possible to configure, could be use case for using both fifos for TX or both for RX */ +#define LRF_EventTxfifo ((LRF_Events){ .value = (1U << 17U)}) /*!< Event from fifo, triggered when crossing threshold. Normal use for txfifo is to generate IRQ when crossing threshold downwards (emptying fifo). But upwards is also possible to configure, could be use case for using both fifos for TX or both for RX */ +#define LRF_EventLossOfLock ((LRF_Events){ .value = (1U << 18U)}) /*!< LOSS_OF_LOCK event */ +#define LRF_EventLock ((LRF_Events){ .value = (1U << 19U)}) /*!< LOCK event */ +#define LRF_EventRfesoft0 ((LRF_Events){ .value = (1U << 20U)}) /*!< RFESOFT0 event */ +#define LRF_EventRfesoft1 ((LRF_Events){ .value = (1U << 21U)}) /*!< RFESOFT1 event */ +#define LRF_EventRfedone ((LRF_Events){ .value = (1U << 22U)}) /*!< RFEDONE event */ +#define LRF_EventMdmsoft0 ((LRF_Events){ .value = (1U << 23U)}) /*!< MDMSOFT event */ +#define LRF_EventMdmsoft1 ((LRF_Events){ .value = (1U << 24U)}) /*!< MDMSOFT1 event */ +#define LRF_EventMdmsoft2 ((LRF_Events){ .value = (1U << 25U)}) /*!< MDMSOFT event */ +#define LRF_EventMdmout ((LRF_Events){ .value = (1U << 26U)}) /*!< MDMOUT event */ +#define LRF_EventMdmin ((LRF_Events){ .value = (1U << 27U)}) /*!< MDMIN event */ +#define LRF_EventMdmdone ((LRF_Events){ .value = (1U << 28U)}) /*!< MDMDONE event */ +#define LRF_EventSystim0 ((LRF_Events){ .value = (1U << 29U)}) /*!< SYSTIM0 event */ +#define LRF_EventSystim1 ((LRF_Events){ .value = (1U << 30U)}) /*!< SYSTIM1 event */ +#define LRF_EventSystim2 ((LRF_Events){ .value = (1U << 31U)}) /*!< SYSTIM2 event */ + + +union LRF_Events_u { + struct { + uint32_t opDone : 1; /*!< The PBE operation has finished */ + uint32_t pingRsp : 1; /*!< When receiving a CMD_PING, PBE responds with a PINGRSP. */ + uint32_t rxCtrl : 1; /*!< LL control packet received correctly */ + uint32_t rxCtrlAck : 1; /*!< LL control packet received with CRC OK, not to be ignored, then acknowledgement sent */ + uint32_t rxNok : 1; /*!< Packet received with CRC error */ + + uint32_t rxIgnored : 1; /*!< Packet received, but may be ignored by MCU */ + uint32_t rxEmpty : 1; /*!< Empty packet received */ + uint32_t rxBufFull : 1; /*!< Packet received which did not fit in the RX FIFO and was not to be discarded.  */ + uint32_t rxOk : 1; /*!< Packet received with CRC OK and not to be ignored by the MCU */ + uint32_t txCtrl : 1; /*!< Transmitted LL control packet */ + uint32_t txCtrlAckAck : 1; /*!< Acknowledgement received on a transmitted LL control packet, and acknowledgement transmitted for that packet */ + uint32_t txRetrans : 1; /*!< Packet retransmitted with same SN */ + uint32_t txAck : 1; /*!< Acknowledgement received on a transmitted packet. */ + uint32_t txDone : 1; /*!< Packet transmitted */ + uint32_t txCtrlAck : 1; /*!< Acknowledgement received on a transmitted LL control packet */ + uint32_t opError : 1; /*!< Something went awfully wrong, the reason is indicated in RAM-based register BLE_ENDCAUSE. */ + uint32_t rxfifo : 1; /*!< Event from fifo, triggered when crossing threshold. Normal use for rxfifo is to generate IRQ when crossing threshold upwards (filling fifo). But downwards is also possible to configure, could be use case for using both fifos for TX or both for RX */ + uint32_t txfifo : 1; /*!< Event from fifo, triggered when crossing threshold. Normal use for txfifo is to generate IRQ when crossing threshold downwards (emptying fifo). But upwards is also possible to configure, could be use case for using both fifos for TX or both for RX */ + uint32_t lossOfLock : 1; /*!< LOSS_OF_LOCK event */ + uint32_t lock : 1; /*!< LOCK event */ + uint32_t rfesoft0 : 1; /*!< RFESOFT0 event */ + uint32_t rfesoft1 : 1; /*!< RFESOFT1 event */ + uint32_t rfedone : 1; /*!< RFEDONE event */ + uint32_t mdmsoft0 : 1; /*!< MDMSOFT event */ + uint32_t mdmsoft1 : 1; /*!< MDMSOFT1 event */ + uint32_t mdmsoft2 : 1; /*!< MDMSOFT event */ + uint32_t mdmout : 1; /*!< MDMOUT event */ + uint32_t mdmin : 1; /*!< MDMIN event */ + uint32_t mdmdone : 1; /*!< MDMDONE event */ + uint32_t systim0 : 1; /*!< SYSTIM0 event */ + uint32_t systim1 : 1; /*!< SYSTIM1 event */ + uint32_t systim2 : 1; /*!< SYSTIM2 event */ + }; + uint32_t value; +}; + +typedef struct LRF_RegConfig_s { + uint32_t configLen; + uint32_t regConfig[]; +} LRF_RegConfig; + +/** + * @brief Index of the tx power table. + */ +typedef union +{ + struct { + uint8_t fraction : 1; /*!< If set to 1, raises the requested power level by 0.5 dB */ + int8_t dBm : 7; /*!< Unit of level used to indicate that a power level is expressed in decibels (dB) with reference to one milliwatt (mW). */ + }; + int8_t rawValue; /*!< rawValue is twice the dBm number, allowing 0.5 dB steps */ +} LRF_TxPowerTable_Index; + +/** + * @brief Single entry of the tx power table. Maps power in dBm to specific + * register settings. + */ +typedef struct { + LRF_TxPowerTable_Index power; /*!< Power level */ + LRF_TxPowerTable_TempCoeff tempCoeff; /*!< Temperature coefficient */ + LRF_TxPowerTable_Value value; /*!< Settings to be compensated and written into register */ +} LRF_TxPowerTable_Entry; + +/** Value indicating that no valid tx power could be found in the table. */ +#define LRF_TxPowerEntry_INVALID_VALUE \ +((LRF_TxPowerTable_Entry) {\ + .power = LRF_TxPower_None,\ + .tempCoeff = 0,\ + .value = LRF_TxPowerTable_INVALID_VALUE,\ +}) + +/** + * @brief Tx power table, containing all characterized dBm to register settings mappings + * + * The table must be sorted from lowest to highest power level + */ +typedef struct { + uint32_t numEntries; + LRF_TxPowerTable_Entry powerTable[]; +} LRF_TxPowerTable; + +typedef struct LRF_TxShape_s { + struct { + uint32_t scale :17; + uint32_t numCoeff :15; + }; + uint8_t coeff[]; +} LRF_TxShape; + +#define LRF_TRIM_NUM_VARIANTS 2 +#define LRF_TRIM_NORMAL_BW 0 +#define LRF_TRIM_HIGH_BW 1 /* Revision >= 4 only */ + +#define LRF_TRIM_MIN_VERSION_FULL_FEATURES 4 /* Only AppTrims revision 4 and above has all features */ + +/* RCL-335: Some CC23X0R5 devices (State D) have an error in the programmed RSSI offset */ +#define LRF_TRIM_VERSION_RSSIOFFSET_ISSUE_CC23X0R5 4 /* AppTrims revision with issue in rssiOffset field */ +#define LRF_TRIM_LIMIT_RSSIOFFSET_ISSUE_CC23X0R5 (-4) /* If rssiOffset is less or equal to this, apply correction */ +#define LRF_TRIM_CORRECTION_RSSIOFFSET_ISSUE_CC23X0R5 5 /* Correction to apply to devices with wrong RSSI offset */ + +#define LRF_TRIM_VERSION_STATE_C_TRIM_WORKAROUND_CC27XX 7U /* AppTrims revision of CC27XX devices in state C and beyond */ +/* RCL-591: RTRIM is hardcoded to 10 for CC27XX state B devices */ +#define LRF_TRIM_RTRIM_VALUE_STATE_B_RTRIM_WORKAROUND_CC27XX 10U /* RTRIM value used on CC27XX state B devices */ +/* RCL-616: DCOLDO0:FIRSTTRIM is hardcoded to 8 and DCOLDO0:SECONDTRIM is increased by 10 for CC27XX state B devices */ +#define LRF_TRIM_DCOLDO0_FIRSTTRIM_VALUE_STATE_B_DCOLDO_WORKAROUND_CC27XX 8U /* DCOLDO0:FIRSTTRIM value used on CC27XX state B devices */ +#define LRF_TRIM_DCOLDO0_SECONDTRIM_INC_STATE_B_DCOLDO_WORKAROUND_CC27XX 10U /* DCOLDO0:SECONDTRIM needs to be increased by 10 on CC27XX state B devices */ +#define LRF_TRIM_DCOLDO0_SECONDTRIM_CODED_BITS_MASK_STATE_B_DCOLDO_WORKAROUND_CC27XX ((1U << 3U) | (1U << 5U)) /* Bits mask for bit 3 and 5 of DCOLDO0:SECONDTRIM */ +#define LRF_TRIM_DCOLDO0_SECONDTRIM_MAX_STATE_B_DCOLDO_WORKAROUND_CC27XX 63U /* DCOLDO0:SECONDTRIM maximum value allowed within the range of 6-bit representation */ + +/* CC27XX devices with revision numbers below 5 only have one PA trim value (instead of four) in CFG and need a workaround */ +#define LRF_TRIM_VERSION_CORRECT_AMOUNT_OF_PA_TRIMS_CC27XX 5 + +/* Definitions for trim */ +typedef struct { + uint32_t word[2]; +} LRF_DoubleWord; + +typedef union { + struct { + // Trim value for LRFDRFE:PA0.TRIM + union { + struct { // length: 2B + uint16_t trim : 5; + uint16_t zero : 11; + } pa0; +#ifdef DeviceFamily_CC27XX + // Trim values for PA (mode0, mode1) + struct { // length: 2B + uint16_t trim0 : 5; + uint16_t zero0 : 3; + uint16_t trim1 : 5; + uint16_t zero1 : 3; + } pa2trim01; +#endif + }; + // Trim value for LRFDRFE:ATSTREFH.IREFTRIM + struct { // length: 2B + uint16_t zero0 : 10; + uint16_t irefTrim : 5; + uint16_t zero1 : 1; + } atstRefH; + } fields; + struct { +#ifdef DeviceFamily_CC27XX + uint16_t pa2trim01; +#else + uint16_t pa0; +#endif + uint16_t atstRefH; + }; + uint32_t data; +} LRF_Trim0; + +typedef union { + struct { + // Trim value for LRFDRFE:LNA.TRIM + struct { // length: 2B + uint16_t zero0 : 4; + uint16_t trim : 4; + uint16_t zero1 : 8; + } lna; + // Trim value for LRFDRFE:IFAMPRFLDO.TRIM + struct { // length: 2B + uint16_t zero : 9; + uint16_t trim : 7; + } ifampRfLdo; + // Trim value for LRFDRFE:DIVLDO.VOUTTRIM + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t voutTrim : 7; + uint16_t zero1 : 1; + } divLdo; + // Trim value for LRFDRFE:TDCLDO.VOUTTRIM + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t voutTrim : 7; + uint16_t zero1 : 1; + } tdcLdo; + } fields; + struct { + uint16_t lna; + uint16_t ifampRfLdo; + uint16_t divLdo; + uint16_t tdcLdo; + }; + LRF_DoubleWord data; +} LRF_Trim1; + +typedef union { + struct { + // Trim values for LRFDRFE:DCOLDO0 + struct { // length: 2B + uint16_t zero0 : 4; + uint16_t firstTrim : 4; + uint16_t secondTrim : 6; + uint16_t zero1 : 2; + } dcoLdo0; + // Trim value for LRFDRFE:IFADCALDO.TRIMOUT + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t trimout : 6; + uint16_t zero1 : 2; + } ifadcAldo; + // Trim value for LRFDRFE:IFADCDLDO.TRIMOUT + struct { // length: 2B + uint16_t zero0 : 8; + uint16_t trimout : 6; + uint16_t zero1 : 2; + } ifadcDldo; + // Trim value for LRFDRFE:DCO.TAILRESTRIM + struct { // length: 2B + uint16_t zero0 : 3; + uint16_t tailresTrim : 4; + uint16_t zero1 : 9; + } dco; + } fields; + struct { + uint16_t dcoLdo0; + uint16_t ifadcAldo; + uint16_t ifadcDldo; + uint16_t dco; + }; + LRF_DoubleWord data; +} LRF_Trim2; + +typedef union { + struct { + // Trim value for LRFDRFE:IFADCQUANT.QUANTTHR + struct { // length: 2B + uint16_t quantThr : 3; + uint16_t zero : 13; + } ifadcQuant; + // Trim values for LRFDRFE:IFADC0 + struct { // length: 2B + uint16_t zero0 : 2; + uint16_t aafcap : 2; + uint16_t int2Adj : 4; + uint16_t zero1 : 2; + uint16_t ditheren : 2; /* Revision >= 4 only */ + uint16_t dithertrim : 3; + uint16_t zero2 : 1; + } ifadc0; + // Trim value for LRFDRFE:IFADC1.TRIM + struct { // length: 2B + uint16_t zero0 : 9; + uint16_t trim : 6; + uint16_t nrz : 1; + } ifadc1; + // Trim values for LRFDRFE:IFADCLF + struct { // length: 2B + uint16_t int3 : 4; + uint16_t ff1 : 4; + uint16_t ff2 : 4; + uint16_t ff3 : 4; + } ifadclf; + } fields; + struct { + uint16_t ifadcQuant; + uint16_t ifadc0; + uint16_t ifadc1; + uint16_t ifadclf; + }; + LRF_DoubleWord data; +} LRF_Trim_Variant; + +typedef struct +{ + uint16_t rtrimMinOffset : 2; + uint16_t rtrimMaxOffset : 2; + uint16_t divLdoMinOffset: 2; + uint16_t divLdoMaxOffset: 2; + uint16_t tdcLdoMinOffset: 2; + uint16_t tdcLdoMaxOffset: 2; + uint16_t tThrl : 2; + uint16_t tThrh : 2; +} LRF_Trim_tempLdoRtrim; + +typedef struct { + int32_t rssiTcomp : 4; + int32_t magnTcomp : 4; + int32_t magnOffset : 4; + int32_t rfu : 4; + int32_t agcThrTcomp : 4; + int32_t agcThrOffset : 4; + int32_t lowGainOffset : 4; + int32_t highGainOffset : 4; +} LRF_Trim_tempRssiAgc; + +typedef union { + struct { + struct { // length: 4B + LRF_Trim_tempLdoRtrim tempLdoRtrim; + uint8_t hfxtPdError; + uint8_t res; + } lrfdrfeExtTrim1; /* Revision >= 4 only */ + // Trim values for synth divider 0 + LRF_Trim_tempRssiAgc lrfdrfeExtTrim0; + } fields; + struct { + uint32_t lrfdrfeExtTrim1; + uint32_t lrfdrfeExtTrim0; + }; + uint32_t data; +} LRF_Trim3; + +typedef union { + struct { + struct { // length: 2B + // RSSI measured for front end 0 in production test. + // Value is read by RF Core FW during RF Core initialization + uint16_t offset : 8; + uint16_t trimCompleteN : 1; + uint16_t zero : 7; + } fend0Rssi; + // Trim values for synth divider 0 + struct { // length: 2B + // Trim value for IQ mismatch compensation. + // Value is read by RF Core FW during RF Core initialization + uint16_t iqmc : 16; + } syntDiv0; +#ifdef DeviceFamily_CC27XX + // Trim values for PA (mode2, mode3) + struct { // length: 2B + uint16_t trim2 : 5; + uint16_t zero0 : 3; + uint16_t trim3 : 5; + uint16_t zero1 : 3; + } pa2trim23; +#else + uint16_t res1; +#endif + struct { + uint8_t zero : 4; + uint8_t aafcap : 4; + } ifamprfldo[LRF_TRIM_NUM_VARIANTS]; /* Revision >= 4 only */ + } fields; + struct { + int8_t rssiOffset; + uint8_t trimCompleteN; + uint16_t demIQMC0; +#ifdef DeviceFamily_CC27XX + uint16_t pa2trim23; +#else + uint16_t res1; +#endif + uint8_t ifamprfldo[LRF_TRIM_NUM_VARIANTS]; + }; + uint32_t data; +} LRF_Trim4; + +/* This definition is used instead of the definition from hw_fcfg.h to accommodate implementation + and cut parameters not relevant to LRF */ +typedef struct { + uint8_t revision; /* Revision of appTrims */ + uint8_t nToolsClientOffset; + uint8_t reserved[2]; + LRF_Trim0 trim0; + LRF_Trim1 trim1; + LRF_Trim2 trim2; + LRF_Trim_Variant trimVariant[LRF_TRIM_NUM_VARIANTS]; + LRF_Trim3 trim3; + LRF_Trim4 trim4; +} LRF_TrimDef; + +/** + * @brief Software defined PHY parameters + */ +typedef struct LRF_SwConfig_s { + int32_t rxIntFrequency; /*!< Receiver intermediate frequency [Hz] */ + int32_t rxFrequencyOffset; /*!< Receiver frequency offset [Hz] */ + int32_t txFrequencyOffset; /*!< Transmitter frequency offset [Hz] */ + uint32_t modFrequencyDeviation; /*!< Transmitter frequency deviation [Hz] */ + const LRF_TxShape *txShape; /*!< Transmitter shape definition */ + uint8_t bwIndex; /*!< Index to use for bandwitdh dependent settings (0: normal 1: high) */ + uint8_t bwIndexDither; /*!< Index to use for bandwitdh dependent ADC dithering settings (0: low 1: normal/high) */ +} LRF_SwConfig; + +/** + * @brief Software defined PHY parameter list + */ +typedef struct LRF_SwParam_s { + const LRF_SwConfig *swConfig; /*!< Software defined parameters. */ + const LRF_TxPowerTable *txPowerTable; /*!< TX power table */ + const LRF_TrimDef *trimDef; /*!< Trim definitions. NULL: Do not apply trim. */ +} LRF_SwParam; + +/** + * @brief Radio configuration structure + */ +typedef struct LRF_Config_s { + const LRF_TOPsmImage *pbeImage; /*!< Image for the PBE */ + const LRF_TOPsmImage *mceImage; /*!< Image for the MCE */ + const LRF_TOPsmImage *rfeImage; /*!< Image for the RFE */ + const LRF_RegConfigList *regConfigList; /*!< List of pointers to register definitions */ +} LRF_Config; + +#define LRF_BASE_ADDR 0x40080000U +#define PBE_RAM_BASE_ADDR 0x40090000U +#define BUF_RAM_BASE_ADDR 0x40092000U +#define RXF_UNWRAPPED_BASE_ADDR 0x40093000U +#define TXF_UNWRAPPED_BASE_ADDR 0x40093800U +#define MCE_RAM_BASE_ADDR 0x40094000U +#define RFE_RAM_BASE_ADDR 0x40096000U +#define S2R_RAM_BASE_ADDR 0x40098000U +#define TOPSM_RAM_SZ 0x00001000U /* 4 KB */ +#define MAX_REG_CONFIG_LEN 1024U /* 1024 entries, using 4 KB */ + +#define LRF_TXPOWER_REFERENCE_TEMPERATURE 25 /*!< Reference temperature for TX power, degrees C */ +#define LRF_TXPOWER_TEMPERATURE_SCALING 0x100 /*!< Scaling factor for TX power temperature coefficients */ + +extern const LRF_TxShape LRF_shapeBaseGfsk05; +extern const LRF_TxShape LRF_shapeBaseGfsk067; +extern const LRF_TxShape LRF_shapeBaseGfsk20; + +static inline void LRF_sendHardStop(void) +{ + /* Send stop to PBE */ + /* This API is the same across PBE banks */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOP; +} + +static inline void LRF_sendGracefulStop(void) +{ + /* Send stop to PBE */ + /* This API is the same across PBE banks */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_EOPSTOP; +} + +static inline void LRF_hardStop(void) +{ + /* LRF does not need to do anything special after hard stop is sent */ +} + +static inline uint32_t LRF_getTxFifoWritable(void) +{ + return HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWRITABLE); +} + +/** + * @brief Programs current TX power setting in radio with temperature compensation + */ +void LRF_programTemperatureCompensatedTxPower(void); + +/** + * @brief Finds settings corresponding to the highest tx power lower than + * the specified value in the tx power table and programs it in the radio + * + * @param powerLevel maximum allowed power level in dBm, or special value + * (%LRF_TxPower_Use_Min, %LRF_TxPower_Use_Max, %LRF_TxPower_Use_Raw, or %LRF_TxPower_None) + * + * @return TxPowerResult_Ok on success; TxPowerResult_Error if no valid settings were found + * + */ +LRF_TxPowerResult LRF_programTxPower(LRF_TxPowerTable_Index powerLevel); + +/** + * @brief Request specific clock enable bits for use by the RCL + * + * @param mask Bit mask of clock enable bits to be set; bit positions as in LRFDDBELL_CLKCTL + * + */ +static inline void LRF_setRclClockEnable(uint16_t mask) +{ + hal_set_rcl_clock_enable(mask); +} + +/** + * @brief Remove request of specific clock enable bits for use by the RCL + * + * @param mask Bit mask of clock enable bits to be cleared; bit positions as in LRFDDBELL_CLKCTL + * + */ +static inline void LRF_clearRclClockEnable(uint16_t mask) +{ + hal_clear_rcl_clock_enable(mask); +} + +/* Temporarily added definitions until https://jira.itg.ti.com/browse/TIDRIVERS-6489 is implemented */ +#ifndef NO_DRIVERS +#include + +#ifdef DeviceFamily_CC27XX +#define LRF_POWER_PERIPH_VALUE(x) (PowerCC27XX_PERIPH_GROUP_LRFD | (x)) +#else +#define LRF_POWER_PERIPH_VALUE(x) (PowerCC23X0_PERIPH_GROUP_LRFD | (x)) +#endif + +#ifdef PowerLPF3_PERIPH_LRFD_BUFRAM +#error "Remove local definition in LRFCC23X0.h and rely on Power driver's definition" +#else +#define PowerLPF3_PERIPH_LRFD_BUFRAM LRF_POWER_PERIPH_VALUE(LRFDDBELL_CLKCTL_BUFRAM_S) +#endif + +#ifdef PowerLPF3_PERIPH_LRFD_MDM +#error "Remove local definition in LRFCC23X0.h and rely on Power driver's definition" +#else +#define PowerLPF3_PERIPH_LRFD_MDM LRF_POWER_PERIPH_VALUE(LRFDDBELL_CLKCTL_MDM_S) +#endif + +#ifdef PowerLPF3_PERIPH_LRFD_TRC +#error "Remove local definition in LRFCC23X0.h and rely on Power driver's definition" +#else +#define PowerLPF3_PERIPH_LRFD_TRC LRF_POWER_PERIPH_VALUE(LRFDDBELL_CLKCTL_TRC_S) +#endif +/* End of temporarily added definitions */ + +#endif + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL.c new file mode 100644 index 00000000..f5332449 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL.c @@ -0,0 +1,912 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL.c ======== + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + + +/* Globals */ +static bool isInitialized = 0; +RCL rclState; + +static void rclCommandHwi(void); +static void rclDispatchHwi(void); +static void rclSchedulerHwi(void); +static void rclPowerNotify(RCL_PowerEvent eventType); +static RCL_CommandStatus rclStop(RCL_Command_Handle c, RCL_StopType stopType, RCL_SchedulerStopReason stopReason); + +/* Hooks */ + +/** + * @brief Hook function to determine what stop type the ongoing command should get + * + * @param[in] currentCmd Currently running command + * @param[in] newCmd New command to potentially take its place + * + * @return ::RCL_StopType How the ongoing command will be terminated if not already terminated when needed + */ +RCL_StopType policyHook(RCL_Command *currentCmd, RCL_Command *newCmd); + +/** + * @brief Hook function to allow dynamic PHY change + * + * @param[in] rclState RCL state + * @param[in] client Current RCL client + * @param[in] cmd Currently running command + * + */ +void phyHook(RCL *rclState, RCL_Handle client, RCL_Command *cmd); + +/** + * @brief Hook function to schedule new command + * + * @param[in] rclSchedulerState Scheduler state + * @param[in] client Current RCL client + * @param[in] cmd Command to be scheduled + * + */ +void scheduleHook(RCL_SchedulerState *rclSchedulerState, RCL_Handle client, RCL_Command *cmd); + +/* command - highest pri hwi */ +static void rclCommandHwi(void) +{ + RCL_Command *cmd = rclSchedulerState.currCmd; + /* We expect no call with NULL pointer, but if debug is off, handle the error by returning safely. */ + RCL_Debug_assert(NULL != cmd); + + /* If command is already finished, return without doing anything */ + if (NULL == cmd || cmd->status >= RCL_CommandStatus_Finished) + { + return; + } + + RCL_Client *client = cmd->runtime.client; + + /*** 1. Get events */ + /* 1a. Posted RCL events */ + RCL_Events rclEventsIn = rclSchedulerState.postedRclEvents; + RCL_Events rclEventsOut = RCL_EventNone; + rclSchedulerState.postedRclEvents = RCL_EventNone; + + /* 1b. Hardware LRF events */ + LRF_Events lrfEvents = {.value = hal_get_command_ifg_reg()}; + + /* 1c. Timer events mapped to RCL events */ + HalTimerEvent timerEvt = hal_check_clear_timer_compare(); + switch (timerEvt) + { + case HAL_TIMER_EVT_SETUP: + rclEventsIn.setup = 1; + break; + case HAL_TIMER_EVT_START: + rclEventsIn.timerStart = 1; + break; + case HAL_TIMER_EVT_HARD_STOP: + rclEventsIn.hardStop = 1; + break; + case HAL_TIMER_EVT_PACKET_TIMEOUT: + rclEventsIn.packetTimeout = 1; + break; + case HAL_TIMER_EVT_GRACEFUL_STOP: + rclEventsIn.gracefulStop = 1; + break; + default: + break; + } + + Log_printf(RclCore, Log_DEBUG, "Command input events RCL: 0x%08X; LRF: 0x%08X", rclEventsIn.value, lrfEvents.value); + + /*** 2. Handle stop or setup event (either from timer or posted SW event) */ + /* Hardstop immediately, graceful is up to the handler */ + if (rclEventsIn.gracefulStop || rclEventsIn.hardStop || rclEventsIn.descheduleStop) + { + /* If not started yet, just cancel timer and increment status to + * finished; bypasses handler later */ + if (cmd->status == RCL_CommandStatus_Scheduled) + { + hal_cancel_start_time(); + if (rclEventsIn.hardStop) + { + rclSchedulerState.descheduleReason = rclSchedulerState.hardStopInfo.stopReason; + } + else if (rclEventsIn.gracefulStop) + { + rclSchedulerState.descheduleReason = rclSchedulerState.gracefulStopInfo.stopReason; + } + else + { + /* The event is descheduleStop - source already set */ + } + cmd->status = RCL_Scheduler_findStopStatus(RCL_StopType_DescheduleOnly); + /* This codepath skips the handler call below which is normally responsible for setting + * this (see comment above). These eventsOut are stored into deferredEvents and eventually + * trigger a callback to the client telling them about the requested stop on this command. + */ + rclEventsOut.lastCmdDone = 1; + } + else /* Command started, handle hardStop here */ + { + if (rclEventsIn.hardStop) + { + LRF_hardStop(); + } + } + } + else if (rclEventsIn.setup) + { + /* Load TOPsm images, settings, etc */ + LRF_RadioState lrfState = rclState.lrfState; + if (rclState.lrfConfig != client->lrfConfig) + { + /* Different config than last time: Ensure settings are reloaded */ + rclState.lrfConfig = client->lrfConfig; + if (lrfState > RadioState_ImagesLoaded) + { + lrfState = RadioState_ImagesLoaded; + } + } + LRF_SetupResult result = LRF_setupRadio(rclState.lrfConfig, cmd->phyFeatures, lrfState); + if (result != SetupResult_Ok) + { + Log_printf(RclCoreShort, Log_ERROR, "Setup failed with code %1d", result); + cmd->status = RCL_CommandStatus_Error_Setup; + rclEventsOut.lastCmdDone = 1; + rclState.lrfState = RadioState_Down; + } + else + { + rclState.lrfState = RadioState_Configured; + } + + /* Set power constraints since the radio has been set up */ + if (rclState.powerState == RCL_standbyAllow) + { + hal_power_set_constraint(); + rclState.powerState = RCL_standbyDisallow; + } + } + + /*** 3. Invoke handler FSM with new events */ + if (cmd->status >= RCL_CommandStatus_Scheduled && cmd->status < RCL_CommandStatus_Finished) + { + rclEventsOut = cmd->runtime.handler(cmd, lrfEvents, rclEventsIn); + } + Log_printf(RclCore, Log_DEBUG, "RCL out: 0x%08X", rclEventsOut.value); + + /*** 4. If the command was caused to start now, configure end timeouts */ + if (rclEventsOut.cmdStarted) + { + RCL_StopType immediateStop = RCL_Scheduler_setStopTimes(); + if (immediateStop != RCL_StopType_None) + { + rclStop(rclSchedulerState.currCmd, immediateStop, RCL_SchedulerStopReason_Timeout); + } + } + /*** 5. If the command raises an event indicating the need for partial radio setup, do it */ + if (rclEventsOut.partialSetup) + { + /* Rerun the radio setup */ + LRF_RadioState lrfState = rclState.lrfState; + + LRF_SetupResult result = LRF_setupRadio(rclState.lrfConfig, rclSchedulerState.requestedPhyFeatures, lrfState); + if (result != SetupResult_Ok) + { + Log_printf(RclCoreShort, Log_ERROR, "Setup failed with code %1d", result); + cmd->status = RCL_CommandStatus_Error_Setup; + rclEventsOut.lastCmdDone = 1; + rclState.lrfState = RadioState_Down; + } + else + { + rclState.lrfState = RadioState_Configured; + } + /* Invoke command handler again to resume the ongoing operation */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventHandlerCmdUpdate); + } + + /*** 6. If stop did not happen, queued event might be delayed */ + if (rclEventsIn.gracefulStop && cmd->status < RCL_CommandStatus_Finished) + { + rclEventsOut.stopDelayed = 1; + } + if (rclEventsIn.descheduleStop && cmd->status < RCL_CommandStatus_Finished) + { + rclEventsOut.stopRejected = 1; + } + + /* We pass the stop things to dispatch even if not subscribed to current, + * since they affect the next queued command + */ + RCL_Events rclEventMask = cmd->runtime.rclCallbackMask; + rclEventMask.stopDelayed = 1; + rclEventMask.stopRejected = 1; + + /*** 7. Filter events, pass stop-rejected to setup, to alert nextCmd */ + client->deferredRclEvents.value |= rclEventMask.value & rclEventsOut.value; + + /*** 8. If finished or have events, invoke setup */ + if (cmd->status >= RCL_CommandStatus_Finished || client->deferredRclEvents.value) + { + if (cmd->status >= RCL_CommandStatus_Finished) + { + hal_cancel_graceful_stop_time(); + hal_cancel_hard_stop_time(); + hal_disable_all_command_radio_interrupts(); + + /* It's now safe to go into standby */ + if (rclState.powerState != RCL_standbyAllow) + { + hal_power_release_constraint(); + rclState.powerState = RCL_standbyAllow; + } + } + hal_trigger_dispatch_fsm(); + } +} + +static void rclDispatchHwi(void) +{ + /* Keep track for callback */ + RCL_Command *currCmd = rclSchedulerState.currCmd; + if (NULL == currCmd) + { + /* An extra pending IRQ may happen if the command HWI comes in and + finishes the command during this ISR. If so, the extra IRQ can be ignored. */ + return; + } + RCL_Client *currClient = currCmd->runtime.client; + RCL_Debug_assert(currClient != NULL); + + /* Get hardware LRF events that should produce callback */ + LRF_Events lrfEvents = { .value = hal_get_dispatch_ifg_reg() }; + + /* If command completed, take out of circulation for possible reuse and + * trigger scheduler in any case to tear down / start next. + */ + if (currCmd->status >= RCL_CommandStatus_Finished) + { + /* It's done or failed */ + Log_printf(RclCore, Log_DEBUG, "Finished; Clearing currCmd, calling scheduleHwi"); + RCL_Command *doneCmd = rclSchedulerState.currCmd; + rclSchedulerState.currCmd = NULL; + + if (doneCmd->runtime.client->pendCmd == doneCmd) + { + Log_printf(RclCore, Log_INFO, "Unpending client: 0x%08X", doneCmd->runtime.client); + doneCmd->runtime.client->pendCmd = NULL; + SemaphoreP_post(&doneCmd->runtime.client->pendSem); + } + + /* See if more waiting, schedule-fsm runs after this hwi */ + hal_trigger_scheduler_fsm(); + /* Now rclSchedulerState.currCmd is free in case client needs to queue something new before scheduler */ + /* Disable the radio HW interrupts for dispatch */ + hal_disable_all_dispatch_radio_interrupts(); + } + + /* Atomically retrieve what is supposed to get done since higher priority + * interrupt sets these + */ + uintptr_t key = HwiP_disable(); + RCL_Events rclEvents = { .value = currClient->deferredRclEvents.value & currCmd->runtime.rclCallbackMask.value }; + RCL_Events stopEvents = { .value = currClient->deferredRclEvents.value & ((RCL_Events){.stopDelayed = 1, .stopRejected = 1}).value }; + RCL_Callback callback = currCmd->runtime.callback; + + currClient->deferredRclEvents = RCL_EventNone; + HwiP_restore(key); + + /* Check if failed stop is a problem for the next command */ + if (stopEvents.value) { + RCL_Command *nextCmd = rclState.nextCmd; + if (nextCmd && !nextCmd->allowDelay && rclSchedulerState.nextWantsStop) + { + Log_printf(RclCore, Log_DEBUG, "Command deplanned due to rejected start: 0x%08X", nextCmd); + + /* Next command does not allow delay, and stop did not take immediate effect */ + rclState.nextCmd = NULL; + rclSchedulerState.nextWantsStop = false; + /* In a world where there can be a queue of commands, get a new next command, lower pri executes after this hwi */ + hal_trigger_scheduler_fsm(); + + /* Synthesize rejected start */ + nextCmd->status = RCL_CommandStatus_RejectedStart; + RCL_Events rejectedEvents = RCL_EventNone; + rejectedEvents.lastCmdDone = 1; + rejectedEvents.startRejected = 1; + + /* Notify owner that command was rejected, if they care */ + RCL_Callback callback = nextCmd->runtime.callback; + if (callback && rejectedEvents.value & nextCmd->runtime.rclCallbackMask.value) + { + callback(nextCmd, LRF_EventNone, rejectedEvents); + } + } + } + + /* Notify owner about events */ + Log_printf(RclCore, Log_INFO, "Client callback: LRF: 0x%08X, RCL: 0x%08X", lrfEvents.value, rclEvents.value); + if ((lrfEvents.value || rclEvents.value) && callback) + { + callback(currCmd, lrfEvents, rclEvents); + } +} + +/* + * ======== policyHook ======== + */ +__attribute__((weak)) RCL_StopType policyHook(RCL_Command *currentCmd, RCL_Command *newCmd) +{ + (void) currentCmd; + + switch(newCmd->conflictPolicy) + { + case RCL_ConflictPolicy_AlwaysInterrupt: + return RCL_StopType_Hard; + case RCL_ConflictPolicy_Polite: + return RCL_StopType_Graceful; + case RCL_ConflictPolicy_NeverInterrupt: + return RCL_StopType_DescheduleOnly; + default: + return RCL_StopType_None; + } +} + +/* + * ======== phyHook ======== + */ +__attribute__((weak)) void phyHook(RCL *rclState, RCL_Handle client, RCL_Command *cmd) +{ + (void)rclState; + (void)client; + (void)cmd; +} + +/* + * ======== scheduleHook ======== + */ +__attribute__((weak)) void scheduleHook(RCL_SchedulerState *rclSchedulerState, RCL_Handle client, RCL_Command *cmd) +{ + (void) client; + + RCL_StopType stopType = policyHook(rclSchedulerState->currCmd, cmd); + + if (rclSchedulerState->currCmd && stopType > RCL_StopType_None) + { + uint32_t now = RCL_Scheduler_getCurrentTime(); + uint32_t then = cmd->timing.absStartTime - RCL_SCHEDULER_MARGIN_LOAD*2; + bool urgent = !RCL_Scheduler_isLater(now, then); + + rclSchedulerState->nextWantsStop = true; + if (cmd->scheduling == RCL_Schedule_Now || urgent) + { + Log_printf(RclCore, Log_VERBOSE, "Stopping old command immediately, urgent=%d", urgent); + rclStop(rclSchedulerState->currCmd, stopType, RCL_SchedulerStopReason_Scheduling); + } + else + { + Log_printf(RclCore, Log_VERBOSE, "Setting running command stop-time to 0x%08X", then); + RCL_SchedulerStopInfo *stopInfo; + switch (stopType) + { + case RCL_StopType_Hard: + stopInfo = &rclSchedulerState->hardStopInfo; + break; + case RCL_StopType_Graceful: + stopInfo = &rclSchedulerState->gracefulStopInfo; + break; + default: + stopInfo = NULL; + break; + } + if (stopInfo != NULL) + { + /* Set selected scheduler stop */ + /* Check if this changes active stop times */ + RCL_StopType immediateStop = RCL_Scheduler_setSchedStopTime(stopInfo, then); + /* Stop now if new stop time is in the past */ + if (immediateStop != RCL_StopType_None) + { + rclStop(rclSchedulerState->currCmd, immediateStop, RCL_SchedulerStopReason_Scheduling); + } + } + } + } +} + +/* scheduler - lowest pri hwi */ +static void rclSchedulerHwi(void) +{ + /* Find next command */ + /* TODO: See RCL-344 */ + RCL_Command *nextCmd = rclState.nextCmd; + Log_printf(RclCore, Log_VERBOSE, "SchedulerHwi nextCmd: 0x%08X", nextCmd); + + /* If nothing is pending, pack up */ + if (NULL == nextCmd) + { + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStop); + return; + } + + int32_t deltaTime = (nextCmd->scheduling == RCL_Schedule_Now) + ? (int32_t)RCL_SCHEDULER_TRIG_NOW_DELAY + : RCL_Scheduler_delta(RCL_Scheduler_getCurrentTime(), nextCmd->timing.absStartTime); + /* Event must be in future */ + if (false == nextCmd->allowDelay && deltaTime < (int32_t)RCL_SCHEDULER_TRIG_NOW_DELAY) + { + nextCmd->status = RCL_CommandStatus_Error_StartTooLate; + return; + } + + /* ScheduleHook might immediately terminate running command and cmdHwi might update currCmd to NULL */ + scheduleHook(&rclSchedulerState, nextCmd->runtime.client, nextCmd); + + /* Determine if can progress nextCmd to currCmd and invoke cmdHwi */ + if (rclSchedulerState.currCmd) + { + /* If there is a current command, we will be triggered again after it is + * finished. + */ + Log_printf(RclCore, Log_VERBOSE, "Could not promote; command 0x%08X running, status 0x%02X", + rclSchedulerState.currCmd, + rclSchedulerState.currCmd->status); + /* A finished command should not be the current command */ + RCL_Debug_assert(rclSchedulerState.currCmd->status < RCL_CommandStatus_Finished); + return; + } + + /* Adopt new command */ + rclState.nextCmd = NULL; + memset((void *)&rclSchedulerState, 0, sizeof(rclSchedulerState)); + rclSchedulerState.currCmd = nextCmd; + /* Set up callback interrupts */ + hal_init_dispatch_radio_interrupts(nextCmd->runtime.lrfCallbackMask.value); + + /* Next command may need different PHY applied; prepare this */ + phyHook(&rclState, nextCmd->runtime.client, rclSchedulerState.currCmd); + + if (deltaTime <= (int32_t)RCL_SCHEDULER_SLEEP_CUTOFF) + { + Log_printf(RclCore, Log_DEBUG, "Calling setup immediately, %d µs until event", deltaTime >> 2); + + /* Command handler does last mile config and trigger */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventSetup); + } + else + { + /* TODO: See RCL-275 */ + uint32_t margin = RCL_SCHEDULER_MARGIN_ARM + RCL_SCHEDULER_WAKEUP_MARGIN; + if (rclState.lrfState < RadioState_Configured || + nextCmd->runtime.client->lrfConfig != rclState.lrfConfig) + { + margin += RCL_SCHEDULER_MARGIN_CONFIGURE; + } + if (rclState.lrfState < RadioState_ImagesLoaded || + LRF_imagesNeedUpdate(nextCmd->runtime.client->lrfConfig)) + { + margin += RCL_SCHEDULER_MARGIN_LOAD; + } + + /* Use LRF:systim0 (SYSTIM:CH2) as wakeup source */ + hal_setup_setup_time(rclSchedulerState.currCmd->timing.absStartTime - margin); + + /* SetupFSM triggers command handler due to timer */ + Log_printf(RclCore, Log_DEBUG, "Wakeup scheduled at 0x%08X (.25µs) with margin subtracted from deltaTime: %d µs", rclSchedulerState.currCmd->timing.absStartTime, deltaTime >> 2); + } +} + +/* Power event routine */ +static void rclPowerNotify(RCL_PowerEvent eventType) +{ + if (eventType == RCL_POWER_STANDBY_AWAKE) + { + /* + * Executed every time the device exits the standby sleep state. + */ + /* Reinitialize the tracer */ + RCL_Tracer_wakeup(); + + /* The rest is only done if at least one client is open */ + if (rclState.numClients > 0) + { + RCL_GPIO_enable(); + + /* Mark radio as not configured */ + if (rclState.lrfState > RadioState_ImagesLoaded) + { + rclState.lrfState = RadioState_ImagesLoaded; + } + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStart); + /* Check if there is an active command at the time of wakeup */ + /* If so, enable start timer interrupt */ + if (rclSchedulerState.currCmd != NULL) + { + /* Restore the DBELL interrupt masks */ + hal_enable_setup_time_irq(); + /* Set up callback interrupts */ + hal_init_dispatch_radio_interrupts(rclSchedulerState.currCmd->runtime.lrfCallbackMask.value); + } + } + } + else if (eventType == RCL_POWER_STANDBY_ENTER) + { + RCL_Tracer_standby(); + /* The rest is only done if at least one client is open */ + if (rclState.numClients > 0) + { + RCL_GPIO_disable(); + } + } + else + { + /* No action */ + } +} + +/* + * ======== RCL_init ======== + */ +void RCL_init(void) +{ + if (!isInitialized) + { + /* Initialize state */ + rclState = (RCL){ + .numClients = 0, + .powerNotifyEnableCount = 0, + .lrfState = RadioState_Down, + .lrfConfig = NULL, + }; + hal_init_fsm(rclDispatchHwi, rclSchedulerHwi, rclCommandHwi); + /* Ensure temperature compensation of TX output power and RF Trims */ + hal_temperature_init(); + isInitialized = true; + /* Initialize the RF Tracer */ + RCL_Tracer_enable(); + } +} + +/* + * ======== RCL_openPowerNotifications ======== + */ +void RCL_openPowerNotifications(void) +{ + if (rclState.powerNotifyEnableCount == 0) + { + hal_power_open(&rclPowerNotify); + } + rclState.powerNotifyEnableCount++; + /* Check for overflow */ + RCL_Debug_assert(rclState.powerNotifyEnableCount > 0); +} + +/* + * ======== RCL_closePowerNotifications ======== + */ +void RCL_closePowerNotifications(void) +{ + /* Check for underflow */ + RCL_Debug_assert(rclState.powerNotifyEnableCount > 0); + rclState.powerNotifyEnableCount--; + if (rclState.powerNotifyEnableCount == 0) + { + hal_power_close(); + } +} + +/* + * ======== RCL_open ======== + */ +RCL_Handle RCL_open(RCL_Client *c, const LRF_Config *lrfConfig) +{ + *c = (RCL_Client){ 0 }; + + SemaphoreP_Params sp; + SemaphoreP_Params_init(&sp); + sp.mode = SemaphoreP_Mode_BINARY; + SemaphoreP_construct(&c->pendSem, 0, &sp); + + if (rclState.numClients == 0) + { + /* Do the operations below if no client was open prior to this one */ + RCL_openPowerNotifications(); + + /* Temporary solution: Enable all needed clocks here */ + LRF_rclEnableRadioClocks(); + + /* Initialize the RCL GPIOs */ + RCL_GPIO_enable(); + + /* Temporary solution: Enable the high performance clock buffer. + * This could be done together with synth REFSYS at the start and end of the command */ + hal_enable_clk_buffer(); + } + + Log_printf(RclCore, Log_DEBUG,"Git SHA: %08x%08x", (uint32_t) (RCL_VERSION_SHA >> 32), RCL_VERSION_SHA); + Log_printf(RclCore, Log_DEBUG,"RCL Version: %08x, Channel number: %x", RCL_VERSION, RCL_VERSION_CHANNEL_NUMBER); + + rclState.numClients += 1; + c->lrfConfig = lrfConfig; + + return c; +} + +/* + * ======== RCL_close ======== + */ +void RCL_close(RCL_Handle h) +{ + rclState.numClients -= 1; + + if (h->lrfConfig == rclState.lrfConfig) + { + /* Closing a client using the current LRF config */ + /* Invalidate config, in case it gets changed before reused in a new client */ + rclState.lrfConfig = NULL; + } + + if (rclState.numClients == 0) + { + /* Disable RCL GPIO pins*/ + RCL_GPIO_disable(); + + /* Temporary solution: Disable clocks here */ + LRF_rclDisableRadioClocks(); + + RCL_closePowerNotifications(); + } + + return; +} + +/* + * ======== submitHook ======== + */ +__attribute__((weak)) bool submitHook(RCL *rclState, RCL_Handle h, RCL_Command *c) +{ + (void) h; + /* Reject if already pending, can't be bothered with list */ + if (rclState->nextCmd != NULL) + { + c->status = RCL_CommandStatus_Error_CommandQueueFull; + return false; + } + + /* Schedule command */ + rclState->nextCmd = c; + c->status = RCL_CommandStatus_Scheduled; + + return true; +} + +/* + * ======== RCL_Command_submit ======== + */ +RCL_CommandStatus RCL_Command_submit(RCL_Handle h, RCL_Command_Handle c) +{ + RCL_Command *cmd = (RCL_Command *)c; + + /* Can't submit again if already submitted */ + if (cmd->status != RCL_CommandStatus_Idle && cmd->status < RCL_CommandStatus_Finished) + { + return RCL_CommandStatus_Error_AlreadySubmitted; + } + + /* Extra check in case user modified status field */ + if (cmd == rclSchedulerState.currCmd || cmd == rclState.nextCmd) + { + return RCL_CommandStatus_Error_AlreadySubmitted; + } + + /* Point back to originator */ + cmd->runtime.client = h; + + /* Try to submit */ + if (!submitHook(&rclState, h, cmd)) + { + return RCL_CommandStatus_Error; + } + + /* Trigger scheduling FSM */ + hal_trigger_scheduler_fsm(); + + return cmd->status; +} + +/* + * ======== RCL_Command_pend ======== + */ +RCL_CommandStatus RCL_Command_pend(RCL_Command_Handle c) +{ + RCL_Command *cmd = (RCL_Command *)c; + RCL_Handle h = cmd->runtime.client; + + RCL_Debug_assert(cmd != NULL); + RCL_Debug_assert(h != NULL); + + /* Indicate interest */ + h->pendCmd = cmd; + + /* Check if already completed. */ + if (cmd->status > RCL_CommandStatus_Active) + { + h->pendCmd = NULL; + return cmd->status; + } + + /* Wait */ + SemaphoreP_pend(&h->pendSem, SemaphoreP_WAIT_FOREVER); + + return cmd->status; +} + +/* + * ======== RCL_Command_stop ======== + */ +RCL_CommandStatus RCL_Command_stop(RCL_Command_Handle c, RCL_StopType stopType) +{ + return rclStop(c, stopType, RCL_SchedulerStopReason_Api); +} + +/* + * ======== rclStop ======== + */ +static RCL_CommandStatus rclStop(RCL_Command_Handle c, RCL_StopType stopType, RCL_SchedulerStopReason stopReason) +{ + RCL_Command *cmd = (RCL_Command *)c; + + /* Check if command is already finished or no stop is done*/ + uintptr_t key = HwiP_disable(); + if (cmd->status < RCL_CommandStatus_Queued || cmd->status >= RCL_CommandStatus_Finished || stopType == RCL_StopType_None) + { + HwiP_restore(key); + Log_printf(RclCoreShort, Log_DEBUG, "Stop called with type: %d, resulting status: 0x%02X", stopType, cmd->status); + return cmd->status; + } + + if (cmd->status == RCL_CommandStatus_Queued) + { + rclState.nextCmd = NULL; + cmd->status = RCL_Scheduler_findStopStatus(RCL_StopType_DescheduleOnly); + /* Cancel scheduler stop of current command */ + RCL_StopType stopType; + /* In the unlikely case that the cmd stop time was very shortly after the canceled sched stop time, + the event could be missed and needs to be handled */ + stopType = RCL_Scheduler_cancelSchedStopTime(&rclSchedulerState.hardStopInfo); + if (stopType == RCL_StopType_Hard && rclSchedulerState.currCmd != NULL) + { + /* Stop currently running command (not the one being canceled) immediately, + * as command stop time must have been passed */ + if (rclSchedulerState.hardStopInfo.apiStopEnabled == 0) + { + LRF_sendHardStop(); + rclSchedulerState.hardStopInfo.apiStopEnabled = 1; + } + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventHardStop); + } + else + { + stopType = RCL_Scheduler_cancelSchedStopTime(&rclSchedulerState.gracefulStopInfo); + if (stopType == RCL_StopType_Graceful && rclSchedulerState.currCmd != NULL) + { + /* Stop currently running command (not the one being canceled) gracefully now, + * as command stop time must have been passed */ + /* Do not send graceful stop if any stop is already sent */ + if (rclSchedulerState.gracefulStopInfo.apiStopEnabled == 0 && + rclSchedulerState.hardStopInfo.apiStopEnabled == 0) + { + LRF_sendGracefulStop(); + rclSchedulerState.gracefulStopInfo.apiStopEnabled = 1; + } + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventGracefulStop); + } + } + } + else + { + RCL_Events rclEvent = RCL_EventNone; + switch (stopType) + { + case RCL_StopType_DescheduleOnly: + rclSchedulerState.descheduleReason = stopReason; + rclEvent.descheduleStop = 1; + break; + case RCL_StopType_Graceful: + rclEvent.gracefulStop = 1; + rclSchedulerState.gracefulStopInfo.stopReason = stopReason; + /* Do not send graceful stop if any stop is already sent */ + if (rclSchedulerState.gracefulStopInfo.apiStopEnabled == 0 && + rclSchedulerState.hardStopInfo.apiStopEnabled == 0) + { + LRF_sendGracefulStop(); + rclSchedulerState.gracefulStopInfo.apiStopEnabled = 1; + } + break; + case RCL_StopType_Hard: + /* Do not send hard stop if already sent (but send if graceful stop is sent) */ + rclEvent.hardStop = 1; + rclSchedulerState.hardStopInfo.stopReason = stopReason; + if (rclSchedulerState.hardStopInfo.apiStopEnabled == 0) + { + LRF_sendHardStop(); + rclSchedulerState.hardStopInfo.apiStopEnabled = 1; + } + break; + case RCL_StopType_None: + default: + RCL_Debug_assert(1 == 0); + break; + } + RCL_Scheduler_postEvent(cmd, rclEvent); + } + HwiP_restore(key); + + Log_printf(RclCoreShort, Log_DEBUG, "Stop called with type: %d, resulting status: 0x%02X", stopType, cmd->status); + return cmd->status; +} + +/* + * ======== RCL_readRssi ======== + */ +int8_t RCL_readRssi(void) +{ + int8_t rssiVal; + + if (rclState.lrfState < RadioState_Configured) + { + rssiVal = LRF_RSSI_INVALID; + } + else + { + rssiVal = LRF_readRssi(); + } + return rssiVal; +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL.h new file mode 100644 index 00000000..38ebbcc3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_h__include +#define ti_drivers_RCL_h__include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/** + * @brief RCL power state + * + * Tracks when the RCL core has requested standby to be disallowed to the power driver. + */ +typedef enum { + RCL_standbyAllow = 0, + RCL_standbyDisallow, +} RCL_PowerState; + +/** + * @brief Global shared driver state + */ +typedef struct RCL_s { + uint8_t numClients; + uint8_t powerNotifyEnableCount; + LRF_RadioState lrfState; + RCL_PowerState powerState; + const LRF_Config *lrfConfig; + RCL_Command *nextCmd; + RCL_Command *doneCmd; +} RCL; + +/** + * @brief Initializes the RCL driver state + * + * Resets global state and initialize hardware. + * + * @note Must be called before using any other RCL API + */ +void RCL_init(void); + +/** + * @brief Initializes an RCL client instance + * + * @param[in] c - Client object struct to be initialized + * @param[in] lrfConfig - Radio configuration to be used by client + * + * @return Instance %RCL_Handle handle or NULL + */ +RCL_Handle RCL_open(RCL_Client *c, const LRF_Config *lrfConfig); + +/** + * @brief Closes client instance and deallocates open resources + * + * @param[in] h - Client handle + */ +void RCL_close(RCL_Handle h); + +/** + * @brief Request RCL power notifications + */ +void RCL_openPowerNotifications(void); + +/** + * @brief Remove RCL power notification request + */ +void RCL_closePowerNotifications(void); + +/** + * @brief Submit RCL command object to be scheduled for execution + * + * This API returns immediately with either %RCL_CommandStatus_Error or the asynchronous + * current state of the command. + * + * @param[in] h - Client handle + * @param[in] c - Command handle + * + * @return %RCL_CommandStatus result of the submission + */ +RCL_CommandStatus RCL_Command_submit(RCL_Handle h, RCL_Command_Handle c); + +/** + * @brief Wait for a submitted command to complete. + * + * Uses %SemaphoreP_pend to block in the callers context. + * + * @pre This function must be called from a task context, with interrupts enabled. + * + * @param[in] c - Client handle + */ +RCL_CommandStatus RCL_Command_pend(RCL_Command_Handle c); + +/** + * @brief Stop a command + * + * Sends the message to try to stop a command. When the function returns, the command may still be + * running. Depending on the stop type, the command may stop after some time. %RCL_Command_pend + * may be used to wait for the command to finish. + * + * @param c [in] - Command handle + * @param stopType [in] - Stop type; telling which situations the command will stop + * + * @return Status of the command; if the command is not finished, a wait is needed. + */ +RCL_CommandStatus RCL_Command_stop(RCL_Command_Handle c, RCL_StopType stopType); + +/** + * @brief Get the last valid RSSI value. + * + * This API returns the last valid RSSI value or a specific error status if the last obtained RSSI + * value is no longer valid. + * + * @return Returns RSSI value, or LRF_RSSI_INVALID if the last obtained RSSI value is no longer valid + * or if the radio is unavailable (e.g. in the middle of a Tx operation). + */ +int8_t RCL_readRssi(void); + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.c new file mode 100644 index 00000000..08f72475 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL_Buffer.c ======== + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +#include + +static bool RxEntry_isAtEnd(RCL_MultiBuffer *multiBuffer, uint16_t curIndex); +static void List_consumeAndStore(List_List *list, List_List *consumedBuffers); + +/* + * ======== RCL_TxBuffer_put ======== + */ +void RCL_TxBuffer_put(List_List *list, RCL_Buffer_TxBuffer *elem) +{ + + List_put(list, (List_Elem *)elem); + /* Notify running command */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventTxBufferUpdate); +} + +/* + * ======== RCL_TxBuffer_init ======== + */ +uint8_t *RCL_TxBuffer_init(RCL_Buffer_TxBuffer *buffer, uint32_t numPad, uint32_t hdrLen, + uint32_t dataLen) +{ + if (buffer == NULL) + { + return NULL; + } + else + { + buffer->state = RCL_BufferStatePending; + buffer->length = sizeof(buffer->numPad) + numPad + hdrLen + dataLen; + buffer->numPad = numPad; + /* Start writing at pad0, then continue into data field */ + uint8_t *data = &buffer->pad0; + while (numPad > 0) + { + --numPad; + *data++ = numPad; + } + return data; + } +} + +/* + * ======== RCL_MultiBuffer_clear ======== + */ +void RCL_MultiBuffer_clear(RCL_MultiBuffer *buffer) +{ + buffer->state = RCL_BufferStatePending; + buffer->headIndex = 0; + buffer->tailIndex = 0; +} + +/* + * ======== RCL_MultiBuffer_init ======== + */ +void RCL_MultiBuffer_init(RCL_MultiBuffer *buffer, size_t size) +{ + size -= offsetof(RCL_MultiBuffer, data); + RCL_Debug_assert(size > 0 && size <= 0xFFFF); + buffer->length = size; + RCL_MultiBuffer_clear(buffer); + +} + +/* + * ======== RCL_MultiBuffer_put ======== + */ +void RCL_MultiBuffer_put(List_List *list, RCL_MultiBuffer *elem) +{ + List_put(list, (List_Elem *)elem); + /* Notify running command */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventRxBufferUpdate); +} + +/* + * ======== RCL_MultiBuffer_RxEntry_get ======== + */ +RCL_Buffer_DataEntry *RCL_MultiBuffer_RxEntry_get(List_List *list, List_List *consumedBuffers) +{ + RCL_Buffer_DataEntry *rxEntry = NULL; + RCL_MultiBuffer *multiBuffer = (RCL_MultiBuffer *)list->head; + if (multiBuffer != NULL) + { + int32_t headIndex = multiBuffer->headIndex; + int32_t tailIndex = multiBuffer->tailIndex; + + RCL_Debug_assert(headIndex <= tailIndex); + + if (headIndex >= tailIndex) + { + if (multiBuffer->state == RCL_BufferStateFinished) + { + List_consumeAndStore(list, consumedBuffers); + multiBuffer = (RCL_MultiBuffer *) List_head(list); + headIndex = 0; + tailIndex = multiBuffer->tailIndex; + RCL_Debug_assert(multiBuffer->headIndex == 0); + + } + } + + if (headIndex < tailIndex) + { + rxEntry = (RCL_Buffer_DataEntry *) &multiBuffer->data[headIndex]; + headIndex += RCL_Buffer_DataEntry_paddedLen(rxEntry->length); + RCL_Debug_assert(headIndex <= tailIndex); + multiBuffer->headIndex = headIndex; + if (headIndex >= tailIndex) + { + if (multiBuffer->state == RCL_BufferStateFinished) + { + List_consumeAndStore(list, consumedBuffers); + } + } + } + } + return rxEntry; +} + +/* + * ======== RCL_MultiBuffer_RxEntry_isEmpty ======== + */ +bool RCL_MultiBuffer_RxEntry_isEmpty(List_List *list) +{ + RCL_MultiBuffer *multiBuffer = (RCL_MultiBuffer *)list->head; + + if (multiBuffer != NULL) + { + return RxEntry_isAtEnd(multiBuffer, multiBuffer->headIndex); + } + else { + return true; + } +} + +/* + * ======== RCL_MultiBuffer_ListInfo_init ======== + */ +void RCL_MultiBuffer_ListInfo_init(RCL_MultiBuffer_ListInfo *listInfo, List_List *list) +{ + RCL_Debug_assert(listInfo != NULL); + RCL_Debug_assert(list != NULL); + + listInfo->multiBuffers = list; + listInfo->nextBuffer = (RCL_MultiBuffer *) List_head(list); + if (listInfo->nextBuffer != NULL) + { + listInfo->nextIndex = listInfo->nextBuffer->headIndex; + } + else + { + listInfo->nextIndex = 0; + } +} + +/* + * ======== RCL_MultiBuffer_RxEntry_next ======== + */ +RCL_Buffer_DataEntry *RCL_MultiBuffer_RxEntry_next(RCL_MultiBuffer_ListInfo *listInfo) +{ + RCL_Buffer_DataEntry *rxEntry = NULL; + + RCL_Debug_assert(listInfo != NULL); + RCL_MultiBuffer *nextBuffer = listInfo->nextBuffer; + + if (nextBuffer == NULL) + { + RCL_Debug_assert(listInfo->multiBuffers != NULL); + nextBuffer = RCL_MultiBuffer_head(listInfo->multiBuffers); + } + + if (nextBuffer != NULL) + { + int32_t nextIndex = listInfo->nextIndex; + int32_t tailIndex = nextBuffer->tailIndex; + if (nextIndex >= tailIndex) + { + if (nextBuffer->state == RCL_BufferStateFinished) + { + nextBuffer = (RCL_MultiBuffer *) List_next((List_Elem *) nextBuffer); + nextIndex = 0; + tailIndex = nextBuffer->tailIndex; + } + } + + if (nextIndex < tailIndex) + { + rxEntry = (RCL_Buffer_DataEntry *) &nextBuffer->data[nextIndex]; + nextIndex += RCL_Buffer_DataEntry_paddedLen(rxEntry->length); + RCL_Debug_assert(nextIndex <= tailIndex); + if (nextIndex >= tailIndex) + { + if (nextBuffer->state == RCL_BufferStateFinished) + { + nextBuffer = (RCL_MultiBuffer *) List_next((List_Elem *) nextBuffer); + nextIndex = 0; + } + } + } + listInfo->nextBuffer = nextBuffer; + listInfo->nextIndex = nextIndex; + } + return rxEntry; +} + +/* + * ======== RCL_MultiBuffer_RxEntry_isLast ======== + */ +bool RCL_MultiBuffer_RxEntry_isLast(RCL_MultiBuffer_ListInfo *listInfo) +{ + RCL_Debug_assert(listInfo != NULL); + + RCL_MultiBuffer *nextBuffer = listInfo->nextBuffer; + + if (nextBuffer != NULL) + { + return RxEntry_isAtEnd(nextBuffer, listInfo->nextIndex); + } + else { + RCL_Debug_assert(listInfo->multiBuffers != NULL); + return RxEntry_isAtEnd((RCL_MultiBuffer *)List_head(listInfo->multiBuffers), 0); + } +} + +/* + * ======== RCL_MultiBuffer_RxEntry_consume ======== + */ +void RCL_MultiBuffer_RxEntry_consume(RCL_MultiBuffer_ListInfo *listInfo, List_List *consumedBuffers) +{ + RCL_Debug_assert(listInfo != NULL); + + List_List *multiBuffers = listInfo->multiBuffers; + RCL_Debug_assert(multiBuffers != NULL); + + RCL_MultiBuffer *nextBuffer = listInfo->nextBuffer; + RCL_MultiBuffer *head = RCL_MultiBuffer_head(multiBuffers); + if (head != NULL) + { + while (head != nextBuffer) + { + RCL_Debug_assert(head != NULL); + List_consumeAndStore(multiBuffers, consumedBuffers); + head = (RCL_MultiBuffer *) List_next((List_Elem *) head); + } + } +} + +/* + * ======== RCL_MultiBuffer_findFirstWritableBuffer ======== + */ +RCL_MultiBuffer *RCL_MultiBuffer_findFirstWritableBuffer(RCL_MultiBuffer *head) +{ + RCL_MultiBuffer *curBuffer = head; + while (curBuffer != NULL && curBuffer->state == RCL_BufferStateFinished) + { + curBuffer = (RCL_MultiBuffer *) List_next((List_Elem *)curBuffer); + } + return curBuffer; +} + +/* + * ======== RCL_MultiBuffer_getBuffer ======== + */ +RCL_MultiBuffer *RCL_MultiBuffer_getBuffer(RCL_MultiBuffer *curBuffer, + uint32_t minLength) +{ + /* Try to find a buffer with enough space */ + if (curBuffer != NULL) + { + /* Check if first buffer in queue needs initialization */ + if (curBuffer->state != RCL_BufferStateInUse) + { + /* Initialize buffer for use */ + curBuffer->state = RCL_BufferStateInUse; + /* Initialize indeces */ + curBuffer->headIndex = 0; + curBuffer->tailIndex = 0; + } + if (minLength + curBuffer->tailIndex > curBuffer->length) + { + /* Not room in this buffer. Need to go to next buffer - unless buffer is empty */ + if (curBuffer->tailIndex == 0) + { + /* New buffer already - give up, as buffer is too small */ + curBuffer = NULL; + } + else + { + curBuffer->state = RCL_BufferStateFinished; + curBuffer = (RCL_MultiBuffer *) List_next((List_Elem *)curBuffer); + /* Check that buffer is available */ + if (curBuffer != NULL) { + /* Make sure that length is enough */ + if (minLength > curBuffer->length) + { + /* Buffer too short */ + curBuffer = NULL; + } + else + { + /* Initialize buffer for use */ + curBuffer->state = RCL_BufferStateInUse; + /* Initialize indeces */ + curBuffer->headIndex = 0; + curBuffer->tailIndex = 0; + } + } + } + } + } + + return curBuffer; +} + +/* + * ======== RCL_MultiBuffer_findAvailableRxSpace ======== + */ +uint32_t RCL_MultiBuffer_findAvailableRxSpace(const RCL_MultiBuffer *curBuffer) +{ + uint32_t space = 0; + + if (curBuffer != NULL) + { + /* Find available space in current buffer */ + if (curBuffer->state == RCL_BufferStateInUse) + { + const RCL_MultiBuffer *nextBuffer; + nextBuffer = (RCL_MultiBuffer *) List_next((List_Elem *)curBuffer); + /* Check if there is another buffer available */ + if (nextBuffer == NULL) + { + /* No - use remaining space in this buffer */ + space = curBuffer->length - curBuffer->tailIndex; + } + else + { + /* Yes - use space in next buffer */ + space = nextBuffer->length; + } + } + else + { + space = curBuffer->length; + } + } + return space; +} + +/* + * ======== RxEntry_isAtEnd ======== + */ +static bool RxEntry_isAtEnd(RCL_MultiBuffer *multiBuffer, uint16_t curIndex) +{ + bool isAtEnd = true; + + if (multiBuffer != NULL) + { + if (curIndex < multiBuffer->tailIndex) + { + isAtEnd = false; + } + else + { + if (multiBuffer->state == RCL_BufferStateFinished) + { + /* Look in next MultiBuffer to see if there is data there */ + multiBuffer = (RCL_MultiBuffer *) List_next((List_Elem *)multiBuffer); + if (multiBuffer != NULL && multiBuffer->tailIndex > 0) + { + isAtEnd = false; + } + } + } + } + + return isAtEnd; +} + +/* + * ======== List_consumeAndStore ======== + */ +static void List_consumeAndStore(List_List *list, List_List *consumedBuffers) +{ + List_Elem *consumedBuffer = List_get(list); + + if (consumedBuffers != NULL) + { + List_put(consumedBuffers, consumedBuffer); + } +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.h new file mode 100644 index 00000000..efede96e --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Buffer.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Buffers_h__include +#define ti_drivers_RCL_Buffers_h__include + +#include +#include + + +/** + * @brief Buffer state + */ +typedef enum { + RCL_BufferStatePending = 0U, /*!< Buffer is not yet accessed by RCL */ + RCL_BufferStateInUse = 1U, /*!< Buffer has been accessed by RCL, and may be accessed again */ + RCL_BufferStateFinished = 2U /*!< RCL is finished with the buffer. It may be reused or freed. */ +} RCL_BufferState; + +typedef struct RCL_Buffer_TxBuffer_s RCL_Buffer_TxBuffer; +typedef struct RCL_Buffer_DataEntry_s RCL_Buffer_DataEntry; +typedef struct RCL_MultiBuffer_s RCL_MultiBuffer; +typedef struct RCL_MultiBuffer_ListInfo_s RCL_MultiBuffer_ListInfo; + +/** + * @brief Definition of an RCL Tx Buffer + * + * Instances of %RCL_Buffer_TxBuffer shall be allocated by the protocol stacks. + */ +struct RCL_Buffer_TxBuffer_s { + List_Elem __elem__; + RCL_BufferState state; /*!< Buffer state */ + uint16_t length __attribute__ ((aligned (4))); /*!< Number of bytes in buffer after the length field */ + uint8_t numPad; /*!< Number of pad bytes before start of the packet */ + uint8_t pad0; /*!< First pad byte, or first byte of the packet if numPad == 0 */ + uint8_t data[]; /*!< Remaining pad bytes and packet */ +}; + +/** + * @brief Definition of an RCL Rx Buffer Entry + * + * Instances of %RCL_Buffer_DataEntry are written by LRF into %RCL_MultiBuffer + * instances allocated by the protocol stacks, or used for a single TX packet + */ +struct RCL_Buffer_DataEntry_s { + uint16_t length __attribute__ ((aligned (4))); /*!< Number of bytes in buffer after the length field */ + uint8_t numPad; /*!< Number of pad bytes before start of the packet */ + uint8_t pad0; /*!< First pad byte, or first byte of the packet if numPad == 0 */ + uint8_t data[]; /*!< Remaining pad bytes and packet */ +}; + +/** + * @brief Definition of an RCL Rx MultiBuffer + * + * Instances of %RCL_MultiBuffer are allocated by the protocol stacks, and + * provided to RCL + */ +struct RCL_MultiBuffer_s { + List_Elem __elem__; + RCL_BufferState state; /*!< Buffer state */ + uint16_t length; /*!< Number of bytes in the data field */ + uint16_t headIndex; /*!< Number of bytes consumed */ + uint16_t tailIndex; /*!< Number of bytes written */ + uint8_t data[]; /*!< Data buffer consisting of %RCL_Buffer_DataEntry elements */ +}; + +/** + * @brief Information about an RCL_MultiBuffer list being traversed + * + * An instance of %RCL_MultiBuffer_ListInfo is used to hold information + * of an RX queue which is read without consuming directly. + */ +struct RCL_MultiBuffer_ListInfo_s { + List_List *multiBuffers; /*!< Pointer to list of MultiBuffers */ + RCL_MultiBuffer *nextBuffer; /*!< Pointer to next MultiBuffer to traverse */ + uint16_t nextIndex; /*!< Index of nextBuffer->data for next entry */ +}; + +/** + * @brief Number of 32-bit words needed to hold a given number of bytes (rounded up) + */ +#define RCL_Buffer_bytesToWords(byteLen) (((byteLen) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/** + * @brief Total length of a data entry in bytes based on length field of the entry + */ +/* Include the data entry's length field and padding to uint32_t boundary */ +#define RCL_Buffer_DataEntry_paddedLen(len) (RCL_Buffer_bytesToWords((len) + sizeof(uint16_t)) * sizeof(uint32_t)) + +/** @defgroup bufferApiFunctions Buffer APIs + * These functions are useful as part of the API to RCL + * @{ + */ + +/** + * @brief Total length of a data entry in bytes, including entry length field and padding + * + * @param numPad Number of padding bytes in front of the packet + * + * @param hdrLen Number of header bytes to hold + * + * @param dataLen Number of payload bytes to hold + * + */ +#define RCL_Buffer_entryLen(numPad, hdrLen, dataLen) (RCL_Buffer_DataEntry_paddedLen(sizeof(uint8_t) + (numPad) + (hdrLen) + (dataLen))) + +/** + * @brief Total length of a TX buffer in bytes, including all fields and padding + * + * @param numPad Number of padding bytes in front of the packet + * + * @param hdrLen Number of header bytes to hold + * + * @param dataLen Number of payload bytes to hold + * + */ +#define RCL_TxBuffer_len(numPad, hdrLen, dataLen) (offsetof(RCL_Buffer_TxBuffer, length) + RCL_Buffer_entryLen(numPad, hdrLen, dataLen)) + +/** + * @brief Total length of a TX buffer in 32-bit words, including all fields and padding + * + * @param numPad Number of padding bytes in front of the packet + * + * @param hdrLen Number of header bytes to hold + * + * @param dataLen Number of payload bytes to hold + * + */ +#define RCL_TxBuffer_len_u32(numPad, hdrLen, dataLen) (RCL_Buffer_bytesToWords(RCL_TxBuffer_len(numPad, hdrLen, dataLen))) + +/** + * @brief Total length of a multi buffer in bytes, including all fields + * + * @param dataLen Number of bytes available to store data entries + * + */ +#define RCL_MultiBuffer_len(dataLen) (offsetof(RCL_MultiBuffer, data) + (dataLen)) + +/** + * @brief Total length of a multi buffer in 32-bit words, including all fields + * + * @param dataLen Number of bytes available to store data entries + * + */ +#define RCL_MultiBuffer_len_u32(dataLen) (RCL_Buffer_bytesToWords(RCL_MultiBuffer_len(dataLen))) + +/** + * @brief Function to atomically get the first elem in a Tx Buffer list + * + * @param list A pointer to a linked list of Tx Buffers + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +static inline RCL_Buffer_TxBuffer *RCL_TxBuffer_get(List_List *list) +{ + return (RCL_Buffer_TxBuffer *)List_get(list); +} + +/** + * @brief Function to return the head of a TxBuffer list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list of Tx Buffers + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline RCL_Buffer_TxBuffer *RCL_TxBuffer_head(List_List *list) +{ + return (RCL_Buffer_TxBuffer *) (list->head); +} + +/** + * @brief Function to return the next elem in a linked list of Tx Buffers + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the TxBuffer list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline RCL_Buffer_TxBuffer *RCL_TxBuffer_next(RCL_Buffer_TxBuffer *elem) +{ + return (RCL_Buffer_TxBuffer *)(((List_Elem *)elem)->next); +} + +/** + * @brief Function to initialize a TX buffer entry for use by RCL + * + * Initialize a new TX buffer entry with the correct length and padding + * + * @param buffer Tx buffer to initialize + * + * @param numPad Number of padding bytes in front of the packet + * + * @param hdrLen Number of header bytes to hold + * + * @param dataLen Number of payload bytes to hold + * + * @return Pointer to address where first header byte should be stored (followed by payload) +*/ +extern uint8_t *RCL_TxBuffer_init(RCL_Buffer_TxBuffer *buffer, uint32_t numPad, uint32_t hdrLen, + uint32_t dataLen); + +/** + * @brief Function to atomically put an elem onto the end of a Tx Buffer list + * + * Add an entry to the TX buffer list and notify the running command if there is any + * + * @param list A pointer to the Tx buffer list + * + * @param elem Element to place onto the end of the linked list + */ +extern void RCL_TxBuffer_put(List_List *list, RCL_Buffer_TxBuffer *elem); + +/** + * @brief Function to return the head of a MultiBuffer list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list of Multi Buffers + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline RCL_MultiBuffer *RCL_MultiBuffer_head(List_List *list) +{ + return (RCL_MultiBuffer *) (list->head); +} + +/** + * @brief Function to return the next elem in a linked list of MultiBuffers + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the MultiBuffer list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline RCL_MultiBuffer *RCL_MultiBuffer_next(RCL_MultiBuffer *elem) +{ + return (RCL_MultiBuffer *)(((List_Elem *)elem)->next); +} + +/** + * @brief Function to get the first elem in a MultiBuffer list + * + * Returns the first whole MultiBuffer from a list. Note that this + * will be done even if the buffer wasn't finished and that the + * buffer may contain several entries. + * + * @param list A pointer to a linked list of Tx Buffers + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +static inline RCL_MultiBuffer *RCL_MultiBuffer_get(List_List *list) +{ + return (RCL_MultiBuffer *)List_get(list); +} + +/** + * @brief Function to clear a multi buffer entry for re-use by RCL + * + * Clear a new multi buffer entry so that it can be re-used by RCL for + * storing received packets + * + * @param buffer Multi buffer to clear + */ +extern void RCL_MultiBuffer_clear(RCL_MultiBuffer *buffer); + +/** + * @brief Function to initialize a multi buffer entry for use by RCL + * + * Initialize a new multi buffer entry so that it can be provided to + * RCL for storing received packets + * + * @param buffer Multi buffer to initialize + * + * @param size Size of the buffer in bytes including all fields + */ +extern void RCL_MultiBuffer_init(RCL_MultiBuffer *buffer, size_t size); + +/** + * @brief Function to get the first entry in a MultiBuffer list + * + * This function gets the first entry in a MultiBuffer list and + * consumes it. If one or two whole %RCL_MultiBuffer are consumed as + * a result of this, they are added to the consumedBuffers list. + * + * @param list A pointer to a linked list of MultiBuffers + * + * @param consumedBuffers A pointer to a linked list which will hold + * the buffers that were consumed and can now + * be re-used. The list is not initialized, + * so that it is possible to get consumed + * entries appended. If this is not desired, + * the list should be cleared first. If NULL, + * consumed buffers are not reported + * + * @return Pointer the first entry in the linked list or NULL if empty + */ +extern RCL_Buffer_DataEntry *RCL_MultiBuffer_RxEntry_get(List_List *list, List_List *consumedBuffers); + +/** + * @brief Function to check if the MultiBuffer List is out of entries + * + * This function returns true if there are no more entries to read + * from a list of MultiBuffers + * + * @param list Pointer to list of multi buffers + * + * @return true if there are no more entries to read now; false if + * there are more entries to read + */ +extern bool RCL_MultiBuffer_RxEntry_isEmpty(List_List *list); + +/** + * @brief Function to initialize information for traversing a multi buffer list + * + * This function prepares a struct for holding information about entries being + * read from a list of multi buffers. It will set up the struct to start by + * traversing the head of the list. + * + * @param listInfo Pointer to list information which will be set up to start + * traversing the head of the list + * + * @param list Pointer to list of multi buffers + * + */ +extern void RCL_MultiBuffer_ListInfo_init(RCL_MultiBuffer_ListInfo *listInfo, List_List *list); + +/** + * @brief Function to return the next entry in a list of multi buffers + * + * This function does not remove the entry, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list of + * multi buffers. + * + * @param listInfo Struct with information of the next entry to + * access. Set up using + * %RCL_MultiBuffer_ListInfo_init before starting. + * + * @return Pointer to the entry in the linked list of MultiBuffers or NULL if + * at the end + */ +extern RCL_Buffer_DataEntry *RCL_MultiBuffer_RxEntry_next(RCL_MultiBuffer_ListInfo *listInfo); + +/** + * @brief Function to check a traversed entry was the last one + * + * This function returns true if the latest entry returned by + * %RCL_MultiBuffer_RxEntry_next was the last one + * + * @param listInfo Struct with information of the next entry to + * access + * + * @return true if there are no more entries to read now; false if + * there are more entries to read + */ +extern bool RCL_MultiBuffer_RxEntry_isLast(RCL_MultiBuffer_ListInfo *listInfo); + +/** + * @brief Function to atomically put an elem onto the end of a multi buffer list + * + * Add an entry to the multi buffer list and notify the running command if there is any + * + * @param list A pointer to the multi buffer list + * + * @param elem Multi buffer to place onto the end of the linked list + */ +extern void RCL_MultiBuffer_put(List_List *list, RCL_MultiBuffer *elem); +/** @} + */ + +/** @defgroup bufferHandlerFunctions Buffer Handler Functions + * These functions are meant mostly to be used by handlers and RCL itself + * @{ + */ +/** + * @brief Find the first writable buffer in a list of MultiBuffers + * + * @note This function is intended as internal to RCL and its handlers + * + * @param head [in] - The head of the list + * + * @return Pointer to first non-finished MultiBuffer after head; NULL if none + */ +RCL_MultiBuffer *RCL_MultiBuffer_findFirstWritableBuffer(RCL_MultiBuffer *head); + +/** + * @brief Returns a buffer with at least `minLength` bytes remaining capacity. + * + * Checks current buffer and next buffer against minLength, returns current if enough + * space, otherwise moves to next buffer. + * + * If no such buffer is available, NULL is returned. + * + * @note This function is intended as internal to RCL and its handlers + * + * @note The caller is responsible for issuing the necessary event if the decision is + * made to use the returned buffer and it is != curBuffer, or if the result of a + * NULL return is to stop using curBuffer. + * + * @param curBuffer [in] - Buffer to search from + * @param minLength [in] - Minimum amount of bytes needed in buffer + * + * @return Suitable %RCL_MultiBuffer or NULL + */ +RCL_MultiBuffer *RCL_MultiBuffer_getBuffer(RCL_MultiBuffer *curBuffer, + uint32_t minLength); + +/** + * @brief Find the minumum number of bytes that can be stored in available MultiBuffers + * + * Finds the number of bytes that can be guaranteed to be possible to store in available + * MultiBuffers, regardless of packet sizes. This is the size of a free MultiBuffer if that + * is available, or the remaining space in a MultiBuffer. + * + * @note This function is intended as internal to RCL and its handlers + * + * @param curBuffer [in] - Pointer to the first writable %RCL_MultiBuffer + * + * @return Number of available bytes + */ +uint32_t RCL_MultiBuffer_findAvailableRxSpace(const RCL_MultiBuffer *curBuffer); + +/** + * @brief Find the first byte to write in an %RCL_MultiBuffer + * + * @note This function is intended as internal to RCL and its handlers + * + * @param curBuffer [in] - Pointer to %RCL_MultiBuffer + * + * @return Pointer to first writable byte in curBuffer + */ +static inline uint8_t *RCL_MultiBuffer_getNextWritableByte(RCL_MultiBuffer *curBuffer) +{ + return & curBuffer->data[curBuffer->tailIndex]; +} + +/** + * @brief Update number of bytes written to %RCL_MultiBuffer + * + * @note This function is intended as internal to RCL and its handlers + * + * @note The caller is responsible for ensuring that the buffer can fit the bytes + * to be committed for issuing the necessary event if the decision is + * + * @param curBuffer [in] - Pointer to %RCL_MultiBuffer + * @param numBytes [in] - Number of bytes that have been written + */ +static inline void RCL_MultiBuffer_commitBytes(RCL_MultiBuffer *curBuffer, uint32_t numBytes) +{ + curBuffer->tailIndex += numBytes; +} +/** @} + */ + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Client.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Client.h new file mode 100644 index 00000000..357069f8 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Client.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Client_h__include +#define ti_drivers_RCL_Client_h__include + +#include +#include +#include + +#include + +/** + * @brief RCL Client object + * + * The application must not access any member variables of this structure! + */ +struct RCL_Client_s { + RCL_Command *pendCmd; + SemaphoreP_Struct pendSem; + RCL_Events deferredRclEvents; /* Deferred from cmd -> cmd */ + const LRF_Config *lrfConfig; +}; + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Command.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Command.h new file mode 100644 index 00000000..9d3cfd54 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Command.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Command_h__include +#define ti_drivers_RCL_Command_h__include + +#include +#include + +#include +#include +#include + +/** + * @brief Command handler function type + */ +typedef RCL_Events (*RCL_CommandHandler)(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEvents); + +/** + * @brief Callback function type + */ +typedef void (*RCL_Callback)(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEvents); + +/** + * @brief Command runtime structure + * + * Holds information on running the command + */ +struct RCL_CommandRuntime_s { + RCL_CommandHandler handler; /*!< Command handler to use for this command */ + RCL_Client *client; /*!< Client */ + LRF_Events lrfCallbackMask; /*!< Callbacks enabled for events directly from LRF */ + RCL_Events rclCallbackMask; /*!< Callbacks enabled for events generated in RCL */ + RCL_Callback callback; /*!< Callback function */ +}; + +/** + * @brief Command timing structure + * + * Holds information on the timing of the command + */ +struct RCL_CommandTiming_s { + uint32_t absStartTime; /*!< Unless timing is Schedule_Now: Start time of the command on SYSTIM (0.25 us steps) */ + uint32_t relMinTime; /*!< For scheduler: Minimum time command must be allowed to run (0.25 us steps). Not supported in this version. */ + int32_t relGracefulStopTime; /*!< Time to initiate graceful stop of command. If negative: Relative to hardStopTime, otherwise relative to startTime (0.25 us steps). 0: Not used */ + uint32_t relHardStopTime; /*!< Time to stop the command as soon as possible; relative to start time (0.25 us steps). 0: Not used. */ +}; + +/** + * @brief Command status + * + * Gives information on the command, and if finished, how it finished. + */ +typedef enum RCL_CommandStatus_e { + RCL_CommandStatus_Idle = 0, /*!< Command is not yet run. This state is mandatory when submitting. */ + RCL_CommandStatus_Queued, /*!< Command is queued, but pending end of previous command */ + RCL_CommandStatus_Scheduled, /*!< Command is scheduled, pending start time. */ + RCL_CommandStatus_Active, /*!< Command is currently running. */ + RCL_CommandStatus_Suspended, /*!< Command is suspended and will resume once the othe running commands have finished */ + RCL_CommandStatus_Deferred, /*!< Command is deferred. */ + RCL_CommandStatus_Finished = 0x10, /*!< Command has finished normally */ + RCL_CommandStatus_ChannelIdle, /*!< Channel assessment has finished with channel idle */ + RCL_CommandStatus_ChannelBusy, /*!< Channel assessment has finished with channel busy */ + RCL_CommandStatus_RxTimeout, /*!< Command timed out waiting for sync */ + RCL_CommandStatus_NoSync, /*!< Command timed out waiting for a returned packet from peer device */ + RCL_CommandStatus_RxErr, /*!< Command ended due to errors with the received packet (e.g, CRC errors) */ + RCL_CommandStatus_RejectedStart, /*!< Command was rejected start due to scheduling parameters */ + RCL_CommandStatus_UnexpectedMdrRx, /*!< Command ended because an MDR packet was received when we have MDR disabled */ + RCL_CommandStatus_DescheduledApi = 0x31, /*!< Command was descheduled before starting running in the radio because stop API was called */ + RCL_CommandStatus_DescheduledScheduling, /*!< Command was descheduled before starting running in the radio due to scheduling of another command */ + RCL_CommandStatus_GracefulStopTimeout = 0x34, /*!< Command ended because graceful stop time was reached */ + RCL_CommandStatus_GracefulStopApi, /*!< Command ended because stop API was called with RCL_StopType_Graceful argument */ + RCL_CommandStatus_GracefulStopScheduling, /*!< Command ended due to scheduling where interrupting command had RCL_ConflictPolicy_Polite */ + RCL_CommandStatus_HardStopTimeout = 0x38, /*!< Command ended because hard stop time was reached */ + RCL_CommandStatus_HardStopApi, /*!< Command ended because stop API was called with RCL_StopType_Hard argument */ + RCL_CommandStatus_HardStopScheduling, /*!< Command ended due to scheduling where interrupting command had RCL_ConflictPolicy_AlwaysInterrupt */ + RCL_CommandStatus_Connect = 0x40, /*!< Command has finished and a connection may be established (BLE5 advertiser and initiator) */ + RCL_CommandStatus_MaxNak, /*!< Command ended because more subsequent NAKs than supported were received (BLE5) */ + RCL_CommandStatus_MaxAuxWaitTimeExceeded, /*!< Command ended because the wait time for a new packet following an AuxPtr was exceeded (BLE5 scanner and initiator) */ + RCL_CommandStatus_Error = 0x80, /*!< Command ended with unknown error */ + RCL_CommandStatus_Error_Setup, /*!< Command ended because of an error in the setup */ + RCL_CommandStatus_Error_Param, /*!< Command ended because of an error with a parameter */ + RCL_CommandStatus_Error_MissingTxBuffer, /*!< Command ended because no TX buffer was available when required */ + RCL_CommandStatus_Error_TxBufferCorruption, /*!< Command ended because of errors in TX buffer structure */ + RCL_CommandStatus_Error_RxBufferCorruption, /*!< Command ended because of errors in RX buffer structure */ + RCL_CommandStatus_Error_StartTooLate, /*!< Command ended because start time was in the past */ + RCL_CommandStatus_Error_TxFifo, /*!< Command ended because of underflow of TX FIFO */ + RCL_CommandStatus_Error_RxFifo, /*!< Command ended because of unsupported overflow of RX FIFO (no buffer to store packets) */ + RCL_CommandStatus_Error_Synth, /*!< Command ended because of synth programming error */ + RCL_CommandStatus_Error_UnknownOp, /*!< Command ended because radio did not recognize command; probably wrong image for given command */ + RCL_CommandStatus_Error_AlreadySubmitted, /*!< Command is already submitted and planned or running and can't be submitted again without calling stop first */ + RCL_CommandStatus_Error_CommandQueueFull /*!< Command was not submitted because there is no space in the pending commands queue */ +} RCL_CommandStatus; + +/** + * Helper macros to compare command status + */ +#define RCL_CommandStatus_isAnyStop(x) (((x) >= RCL_CommandStatus_DescheduledApi) && ((x) <= RCL_CommandStatus_HardStopScheduling)) +#define RCL_CommandStatus_isAnyDescheduled(x) (((x) >= RCL_CommandStatus_DescheduledApi) && ((x) <= RCL_CommandStatus_DescheduledScheduling)) +#define RCL_CommandStatus_isAnyGracefulStop(x) (((x) >= RCL_CommandStatus_GracefulStopTimeout) && ((x) <= RCL_CommandStatus_GracefulStopScheduling)) +#define RCL_CommandStatus_isAnyHardStop(x) (((x) >= RCL_CommandStatus_HardStopTimeout) && ((x) <= RCL_CommandStatus_HardStopScheduling)) +#define RCL_CommandStatus_isAnyTimeoutStop(x) (((x) == RCL_CommandStatus_GracefulStopTimeout) || ((x) == RCL_CommandStatus_HardStopTimeout)) +#define RCL_CommandStatus_isAnyApiStop(x) (((x) == RCL_CommandStatus_DescheduledApi) || ((x) == RCL_CommandStatus_GracefulStopApi) || ((x) == RCL_CommandStatus_HardStopApi)) +#define RCL_CommandStatus_isAnySchedulingStop(x) (((x) == RCL_CommandStatus_DescheduledScheduling) || ((x) == RCL_CommandStatus_GracefulStopScheduling) || ((x) == RCL_CommandStatus_HardStopScheduling)) + +/** + * @brief Stop types + * + * Type of stop to perform + */ +typedef enum { + RCL_StopType_None = 0, /*!< No stop requested */ + RCL_StopType_DescheduleOnly, /*!< Stop a command that is queued or pending start, but do not stop it from running */ + RCL_StopType_Graceful, /*!< Stop the command gracefully, that is finish a packet or transaction in progress before ending */ + RCL_StopType_Hard, /*!< Stop the command as soon as possible */ +} RCL_StopType; + +/** + * @brief Schedule type + * + * The type of scheduling used for a command + */ +typedef enum { + RCL_Schedule_Now = 0, /*!< Schedule the command to start as soon as possible */ + RCL_Schedule_AbsTime = 1, /*!< Schedule command to start at a given time; give error if delays occur */ +} RCL_ScheduleType; + +/** + * @brief Conflict resolution policy + * + * How will this command interact with an already running and overlapping command + */ +typedef enum { + RCL_ConflictPolicy_AlwaysInterrupt = 0, /*!< Always stop a running command if necessary to run this command */ + RCL_ConflictPolicy_Polite = 1, /*!< Stop a running command unless it is communicating, i.e. transmitting or is actively receiving */ + RCL_ConflictPolicy_NeverInterrupt = 2, /*!< Never stop an ongoing command */ +} RCL_ConflictPolicy; + +/** + * @brief General command + * + * Fields common for all commands + */ +struct RCL_Command_s { + uint16_t cmdId; /*!< Command ID */ + uint16_t phyFeatures; /*!< PHY feature selector; use 0 if only one PHY */ + RCL_ScheduleType scheduling : 8; /*!< Scheduling type */ + RCL_CommandStatus status : 8; /*!< Status of command */ + RCL_ConflictPolicy conflictPolicy : 8; /*!< Conflict resolution policy */ + bool allowDelay; /*!< Start may be delayed */ + RCL_CommandRuntime runtime; /*!< Runtime information */ + RCL_CommandTiming timing; /*!< Timing information */ +}; + +#define RCL_Command_Default(_id, _handler) \ +{ \ + .cmdId = _id, \ + .phyFeatures = 0, \ + .scheduling = RCL_Schedule_Now, \ + .status = RCL_CommandStatus_Idle, \ + .conflictPolicy = RCL_ConflictPolicy_AlwaysInterrupt, \ + .allowDelay = false, \ + .runtime = { \ + .handler = _handler, \ + }, \ + .timing = { \ + .absStartTime = 0, \ + .relGracefulStopTime = 0, \ + .relHardStopTime = 0, \ + }, \ +} +#define RCL_Command_DefaultRuntime(_id, _handler) (RCL_Command) RCL_Command_Default(_id, _handler) + +/** + * @brief Type for TX power + * + * The wanted TX power to program; the RCL will select the highest available power smaller than or + * equal to the requested setting. + * + * Special settings: + * %LRF_TxPower_Use_Min: Use minimum available TX power + * %LRF_TxPower_Use_Max: Use maximum available TX power + * %LRF_TxPower_Use_Raw: Use a raw TX power register setting given with %RCL_Command_setRawTxPower() + * %LRF_TxPower_None: Do not write TX power + */ +typedef LRF_TxPowerTable_Index RCL_Command_TxPower; + +/** + * @brief Set raw TX power + * + * Set the TX power to be written directly into the TX power register applicable to the chip. + * The setting only applies to commands where the TX power is set to %LRF_TxPower_Use_Raw + */ +static inline void RCL_Command_setRawTxPower(uint32_t registerSetting, uint32_t temperatureCoefficient) +{ + LRF_setRawTxPower(registerSetting, temperatureCoefficient); +} + +#endif /* ti_drivers_RCL_Command_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.c new file mode 100644 index 00000000..078a3477 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL_Debug.c ======== + */ + +#include +#include + + +/* + * ======== RCL_Assert_proxy ======== + */ +__attribute__((weak)) void RCL_Debug_assertProxy(const char *expr, const char *file, int line) +{ + (void) expr; + (void) file; + (void) line; + DebugP_assert(false); +} + diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.h new file mode 100644 index 00000000..1ead1144 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Debug.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Debug_h__include +#define ti_drivers_RCL_Debug_h__include + + + +#define assert_str(s) #s +#define RCL_Debug_assert(expr) (expr ? (void)0 : RCL_Debug_assertProxy(assert_str(expr), __FILE__, __LINE__)) + + +extern void __attribute__((weak)) RCL_Debug_assertProxy(const char *expr, const char *file, int line); + + +#endif /* ti_drivers_RCL_Debug_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Event.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Event.h new file mode 100644 index 00000000..8606aae9 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Event.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __rcl_events_h__ +#define __rcl_events_h__ + +#include + +#define RCL_EventNone ((RCL_Events){ .value = (0 << 0)}) /*!< No events */ +#define RCL_EventCmdStarted ((RCL_Events){ .value = (1 << 0)}) /*!< Command handler has accepted and started executing */ +#define RCL_EventLastCmdDone ((RCL_Events){ .value = (1 << 1)}) /*!< The RCL is finished with the command */ +#define RCL_EventRxEntryAvail ((RCL_Events){ .value = (1 << 2)}) /*!< An RX entry has been made available */ +#define RCL_EventRxBufferFinished ((RCL_Events){ .value = (1 << 3)}) /*!< An RX multi-buffer is finished */ +#define RCL_EventTxBufferFinished ((RCL_Events){ .value = (1 << 4)}) /*!< A TX buffer is finished */ +#define RCL_EventSoftwareTriggered ((RCL_Events){ .value = (1 << 5)}) /*!< Handler is triggered from software */ +#define RCL_EventTimerStart ((RCL_Events){ .value = (1 << 6)}) /*!< Timer-based start signalled */ +#define RCL_EventDescheduleStop ((RCL_Events){ .value = (1 << 7)}) /*!< Deschedule-type stop signalled */ +#define RCL_EventGracefulStop ((RCL_Events){ .value = (1 << 8)}) /*!< Timer-based graceful-stop signalled */ +#define RCL_EventHardStop ((RCL_Events){ .value = (1 << 9)}) /*!< Timer-based hard-stop signalled */ +#define RCL_EventStopDelayed ((RCL_Events){ .value = (1 << 10)}) /*!< Command was not stopped */ +#define RCL_EventStopRejected ((RCL_Events){ .value = (1 << 11)}) /*!< Command was not stopped */ +#define RCL_EventStartDelayed ((RCL_Events){ .value = (1 << 12)}) /*!< Command start is delayed, may still happen within allowDelay */ +#define RCL_EventStartRejected ((RCL_Events){ .value = (1 << 13)}) /*!< Command start is not possible within scheduling parameters */ +#define RCL_EventSetup ((RCL_Events){ .value = (1 << 14)}) /*!< Setup has been performed */ +#define RCL_EventPartialSetup ((RCL_Events){ .value = (1 << 15)}) /*!< Partial setup has been performed or is required by the running command */ +#define RCL_EventRxBufferUpdate ((RCL_Events){ .value = (1 << 16)}) /*!< RX buffer has been updated */ +#define RCL_EventTxBufferUpdate ((RCL_Events){ .value = (1 << 17)}) /*!< TX buffer has been updated */ +#define RCL_EventHandlerCmdUpdate ((RCL_Events){ .value = (1 << 18)}) /*!< A property of a running command has been updated, to be detailed by handler */ +#define RCL_EventCmdStepDone ((RCL_Events){ .value = (1 << 19)}) /*!< A step of the command has been done; details are command specific */ +#define RCL_EventStopTimesUpdated ((RCL_Events){ .value = (1 << 20)}) /*!< A change was made to the stop times */ +#define RCL_EventPacketTimeout ((RCL_Events){ .value = (1 << 21)}) /*!< A manually set packet-specific timeout has expired */ + +union RCL_Events_u { + struct { + uint32_t cmdStarted : 1; /*!< Command handler has accepted and started executing */ + uint32_t lastCmdDone : 1; /*!< The RCL is finished with the command */ + uint32_t rxEntryAvail : 1; /*!< An RX entry has been made available */ + uint32_t rxBufferFinished : 1; /*!< An RX multi-buffer is finished */ + uint32_t txBufferFinished : 1; /*!< A TX buffer is finished */ + uint32_t swTriggered : 1; /*!< Handler is triggered from software */ + uint32_t timerStart : 1; /*!< Timer-based start signalled */ + uint32_t descheduleStop : 1; /*!< Deschedule-type stop signalled */ + uint32_t gracefulStop : 1; /*!< Timer/api-based graceful-stop signalled */ + uint32_t hardStop : 1; /*!< Timer/api-based hard-stop signalled */ + uint32_t stopDelayed : 1; /*!< Command was not stopped */ + uint32_t stopRejected : 1; /*!< Command was not stopped */ + uint32_t startDelayed : 1; /*!< Command start is delayed, may still happen within allowDelay */ + uint32_t startRejected : 1; /*!< Command start is not possible within scheduling parameters */ + uint32_t setup : 1; /*!< Setup has been performed */ + uint32_t partialSetup : 1; /*!< Partial setup has been performed or is required by the running command */ + uint32_t rxBufferUpdate : 1; /*!< RX buffer has been updated */ + uint32_t txBufferUpdate : 1; /*!< TX buffer has been updated */ + uint32_t handlerCmdUpdate : 1; /*!< A property of a running command has been updated, to be detailed by handler */ + uint32_t cmdStepDone : 1; /*!< A step of the command has been done; details are command specific */ + uint32_t stopTimesUpdated : 1; /*!< A change was made to the stop times */ + uint32_t packetTimeout : 1; /*!< A manually set packet-specific timeout has expired */ + }; + uint32_t value; +}; + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.c new file mode 100644 index 00000000..d469505a --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL_Profiling.c ======== + */ + +#include + +/* + * ======== RCL_Profiling_eventHook ======== + */ +void __attribute__((weak)) RCL_Profiling_eventHook(RCL_ProfilingEvent event) +{ + /* Internal TI use: Sets start and stop events for power profiling */ + (void) event; +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.h new file mode 100644 index 00000000..c999a66b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Profiling.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Profiling_h__include +#define ti_drivers_RCL_Profiling_h__include + +typedef enum RCL_ProfilingEvent_e { + RCL_ProfilingEvent_PreprocStart = 1, /*!< Radio operation preprocessing has started */ + RCL_ProfilingEvent_PreprocStop, /*!< Radio operation preprocessing has finalized */ + RCL_ProfilingEvent_PostprocStart, /*!< Radio operation postprocessing has started */ + RCL_ProfilingEvent_PostprocStop, /*!< Radio operation postprocessing has finalized */ +} RCL_ProfilingEvent; + +extern void __attribute__((weak)) RCL_Profiling_eventHook(RCL_ProfilingEvent event); + + +#endif /* ti_drivers_RCL_Profiling_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.c new file mode 100644 index 00000000..0c389509 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.c @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL_Scheduler.c ======== + */ + +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include + +#include + +RCL_SchedulerState rclSchedulerState; + + +typedef enum +{ + SchedulerNoStart = 0, + SchedulerStartNow = 1, + SchedulerStartAbsTimeAllowDelay = 2, + SchedulerStartAbsTimeNoDelay = 3, +} SchedulerStartType; + +static RCL_CommandStatus rclSchedulerProcessCmdStartStopTime(const RCL_CommandTiming *timing, uint32_t startTime, SchedulerStartType startType); +static void rclSchedulerFindEarliestStopTime(RCL_SchedulerStopInfo *stopInfo); +static RCL_StopType rclSchedulerSetNewStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t newStopTime, bool sched); +static RCL_StopType rclSchedulerCancelStopTime(RCL_SchedulerStopInfo *stopInfo, bool sched); + +/* + * ======== RCL_Scheduler_findStopStatus ======== + */ +RCL_CommandStatus RCL_Scheduler_findStopStatus(RCL_StopType stopType) +{ + RCL_CommandStatus status; + switch (stopType) + { + case RCL_StopType_DescheduleOnly: + switch (rclSchedulerState.descheduleReason) + { + case RCL_SchedulerStopReason_Scheduling: + status = RCL_CommandStatus_DescheduledScheduling; + break; + case RCL_SchedulerStopReason_Api: + status = RCL_CommandStatus_DescheduledApi; + break; + default: + /* Other values should not occur */ + status = RCL_CommandStatus_Error; + break; + } + break; + case RCL_StopType_Graceful: + switch (rclSchedulerState.gracefulStopInfo.stopReason) + { + case RCL_SchedulerStopReason_Timeout: + status = RCL_CommandStatus_GracefulStopTimeout; + break; + case RCL_SchedulerStopReason_Scheduling: + status = RCL_CommandStatus_GracefulStopScheduling; + break; + case RCL_SchedulerStopReason_Api: + status = RCL_CommandStatus_GracefulStopApi; + break; + default: + /* Other values should not occur */ + status = RCL_CommandStatus_Error; + break; + } + break; + case RCL_StopType_Hard: + switch (rclSchedulerState.hardStopInfo.stopReason) + { + case RCL_SchedulerStopReason_Timeout: + status = RCL_CommandStatus_HardStopTimeout; + break; + case RCL_SchedulerStopReason_Scheduling: + status = RCL_CommandStatus_HardStopScheduling; + break; + case RCL_SchedulerStopReason_Api: + status = RCL_CommandStatus_HardStopApi; + break; + default: + /* Other values should not occur */ + status = RCL_CommandStatus_Error; + break; + } + break; + default: + /* Other stop types not allowed */ + status = RCL_CommandStatus_Error; + } + /* Error status should not be produced if function is used correctly */ + RCL_Debug_assert(status < RCL_CommandStatus_Error); + + return status; +} + +/* + * ======== RCL_Scheduler_setStartStopTime ======== + */ +RCL_CommandStatus RCL_Scheduler_setStartStopTime(const RCL_Command *cmd) +{ + uint32_t startTime; + SchedulerStartType startType; + + RCL_Debug_assert(cmd != NULL); + + if (cmd->scheduling == RCL_Schedule_AbsTime) + { + startType = cmd->allowDelay ? SchedulerStartAbsTimeAllowDelay : SchedulerStartAbsTimeNoDelay; + startTime = cmd->timing.absStartTime; + } + else + { + /* For schedule now, we don't need to check allowDelay here, as delays at this stage will be small */ + startType = SchedulerStartNow; + startTime = 0; + } + + return rclSchedulerProcessCmdStartStopTime(&cmd->timing, startTime, startType); +} + +/* + * ======== RCL_Scheduler_setStartStopTimeEarliestStart ======== + */ +RCL_CommandStatus RCL_Scheduler_setStartStopTimeEarliestStart(const RCL_Command *cmd, uint32_t earliestStartTime) +{ + uint32_t startTime; + SchedulerStartType startType; + + RCL_Debug_assert(cmd != NULL); + + if (cmd->scheduling == RCL_Schedule_AbsTime) + { + startType = cmd->allowDelay ? SchedulerStartAbsTimeAllowDelay : SchedulerStartAbsTimeNoDelay; + startTime = cmd->timing.absStartTime; + if (!RCL_Scheduler_isLater(earliestStartTime, startTime)) + { + /* Start time is earlier than indicated - delay start if allowed */ + if (startType == SchedulerStartAbsTimeNoDelay) + { + /* Delay not allowed */ + return RCL_CommandStatus_Error_StartTooLate; + } + else + { + startTime = earliestStartTime; + } + } + } + else + { + /* For schedule now, we don't need to check allowDelay here, as delays at this stage will be small */ + startType = SchedulerStartAbsTimeAllowDelay; + startTime = earliestStartTime; + } + + return rclSchedulerProcessCmdStartStopTime(&cmd->timing, startTime, startType); +} + +/* + * ======== RCL_Scheduler_setCustomStartStopTime ======== + */ +RCL_CommandStatus RCL_Scheduler_setCustomStartStopTime(const RCL_CommandTiming *timing, RCL_ScheduleType scheduling, bool allowDelay) +{ + uint32_t startTime; + SchedulerStartType startType; + + RCL_Debug_assert(timing != NULL); + + if (scheduling == RCL_Schedule_AbsTime) + { + startType = allowDelay ? SchedulerStartAbsTimeAllowDelay : SchedulerStartAbsTimeNoDelay; + startTime = timing->absStartTime; + } + else + { + /* For schedule now, we don't need to check allowDelay here, as delays at this stage will be small */ + startType = SchedulerStartNow; + startTime = 0; + } + + return rclSchedulerProcessCmdStartStopTime(timing, startTime, startType); +} + +/* + * ======== RCL_Scheduler_setCustomStartStopTimeEarliestStart ======== + */ +RCL_CommandStatus RCL_Scheduler_setCustomStartStopTimeEarliestStart(const RCL_CommandTiming *timing, RCL_ScheduleType scheduling, bool allowDelay, uint32_t earliestStartTime) +{ + uint32_t startTime; + SchedulerStartType startType; + + RCL_Debug_assert(timing != NULL); + + if (scheduling == RCL_Schedule_AbsTime) + { + startType = allowDelay ? SchedulerStartAbsTimeAllowDelay : SchedulerStartAbsTimeNoDelay; + startTime = timing->absStartTime; + if (!RCL_Scheduler_isLater(earliestStartTime, startTime)) + { + /* Start time is earlier than indicated - delay start if allowed */ + if (startType == SchedulerStartAbsTimeNoDelay) + { + /* Delay not allowed */ + return RCL_CommandStatus_Error_StartTooLate; + } + else + { + startTime = earliestStartTime; + } + } + } + else + { + /* For schedule now, we don't need to check allowDelay here, as delays at this stage will be small */ + startType = SchedulerStartAbsTimeAllowDelay; + startTime = earliestStartTime; + } + + return rclSchedulerProcessCmdStartStopTime(timing, startTime, startType); +} + +/* + * ======== RCL_Scheduler_setCmdStopTimeNoStartTrigger ======== + */ +RCL_CommandStatus RCL_Scheduler_setCmdStopTimeNoStartTrigger(const RCL_Command *cmd) +{ + RCL_Debug_assert(cmd != NULL); + + return rclSchedulerProcessCmdStartStopTime(&cmd->timing, 0, SchedulerNoStart); +} + +/* + * ======== RCL_Scheduler_setNewStartNow ======== + */ +RCL_CommandStatus RCL_Scheduler_setNewStartNow(void) +{ + return rclSchedulerProcessCmdStartStopTime(NULL, 0, SchedulerStartNow); +} + +/* + * ======== RCL_Scheduler_setNewStartAbsTime ======== + */ +RCL_CommandStatus RCL_Scheduler_setNewStartAbsTime(uint32_t startTime, bool allowDelay) +{ + return rclSchedulerProcessCmdStartStopTime(NULL, startTime, + allowDelay ? SchedulerStartAbsTimeAllowDelay : SchedulerStartAbsTimeNoDelay); +} + +/* + * ======== RCL_Scheduler_setNewStartRelTime ======== + */ +RCL_CommandStatus RCL_Scheduler_setNewStartRelTime(uint32_t relStartTime) +{ + uint32_t startTime = rclSchedulerState.actualStartTime + relStartTime; + + return rclSchedulerProcessCmdStartStopTime(NULL, startTime, SchedulerStartAbsTimeAllowDelay); +} + +/* + * ======== rclSchedulerProcessCmdStartStopTime ======== + */ +static RCL_CommandStatus rclSchedulerProcessCmdStartStopTime(const RCL_CommandTiming *timing, uint32_t startTime, SchedulerStartType startType) +{ + uintptr_t key; + uint32_t currentTime; + uint32_t actualStartTime = startTime; + + key = HwiP_disable(); + + if (startType == SchedulerNoStart) + { + actualStartTime = hal_get_current_time(); + } + else if (startType == SchedulerStartNow) + { + /* Find start time to trig now; add a delay to allow trigger to be in the future */ + actualStartTime = hal_get_current_time() + RCL_SCHEDULER_TRIG_NOW_DELAY; + } + else + { + /* Check if there is enough time for start */ + currentTime = hal_get_current_time(); + if (!RCL_Scheduler_isLater(currentTime + RCL_SCHEDULER_TRIG_NOW_DELAY, startTime)) + { + if (startType == SchedulerStartAbsTimeAllowDelay) + { + actualStartTime = currentTime + RCL_SCHEDULER_TRIG_NOW_DELAY; + } + else { + /* Error - start is too late */ + HwiP_restore(key); + return RCL_CommandStatus_Error_StartTooLate; + } + } + } + + rclSchedulerState.actualStartTime = actualStartTime; + if (startType != SchedulerNoStart) + { + hal_setup_start_time(actualStartTime); + /* Due to protected area and added delay, the programmed start time is not expected to be in the future. */ + RCL_Debug_assert(RCL_Scheduler_isLater(RCL_Scheduler_getCurrentTime(), actualStartTime)); + } + + /* Set up stop times from command if not already done */ + if (timing != NULL && (rclSchedulerState.stopTimeState < RCL_SchedulerStopTimeState_Found)) + { + uint32_t relHardStopTime = timing->relHardStopTime; + int32_t relGracefulStopTime = timing->relGracefulStopTime; + if (relHardStopTime != 0) + { + rclSchedulerState.hardStopInfo.cmdStopTime = startTime + relHardStopTime; + rclSchedulerState.hardStopInfo.cmdStopEnabled = true; + } + + if (relGracefulStopTime < 0 && relHardStopTime != 0) + { + /* Graceful stop time relative to hard stop time */ + relGracefulStopTime += relHardStopTime; + if (relGracefulStopTime <= 0) + { + /* Stop immediately */ + relGracefulStopTime = 1; + } + } + if (relGracefulStopTime > 0) + { + rclSchedulerState.gracefulStopInfo.cmdStopTime = actualStartTime + relGracefulStopTime; + rclSchedulerState.gracefulStopInfo.cmdStopEnabled = true; + } + + /* Find earliest stop times */ + rclSchedulerFindEarliestStopTime(&rclSchedulerState.hardStopInfo); + rclSchedulerFindEarliestStopTime(&rclSchedulerState.gracefulStopInfo); + + rclSchedulerState.stopTimeState = RCL_SchedulerStopTimeState_Found; + } + + /* Check if stop has been requested; at this time, radio may not have started */ + if (rclSchedulerState.hardStopInfo.apiStopEnabled) + { + /* Hard stop before modem start */ + HwiP_restore(key); + return RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + } + else if (rclSchedulerState.hardStopInfo.stopReason != RCL_SchedulerStopReason_None) + { + uint32_t stopTime = (rclSchedulerState.hardStopInfo.stopReason == RCL_SchedulerStopReason_Timeout) ? + rclSchedulerState.hardStopInfo.cmdStopTime : rclSchedulerState.hardStopInfo.schedStopTime; + + if (!RCL_Scheduler_isLater(actualStartTime, stopTime)) + { + /* Hard stop before modem start */ + HwiP_restore(key); + return RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + } + } + + if (rclSchedulerState.gracefulStopInfo.apiStopEnabled) + { + /* Graceful stop before modem start */ + HwiP_restore(key); + return RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + else if (rclSchedulerState.gracefulStopInfo.stopReason != RCL_SchedulerStopReason_None) + { + uint32_t stopTime = (rclSchedulerState.gracefulStopInfo.stopReason == RCL_SchedulerStopReason_Timeout) ? + rclSchedulerState.gracefulStopInfo.cmdStopTime : rclSchedulerState.gracefulStopInfo.schedStopTime; + + if (!RCL_Scheduler_isLater(actualStartTime, stopTime)) + { + /* Graceful stop before modem start */ + HwiP_restore(key); + return RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + } + + HwiP_restore(key); + + Log_printf(RclCore, Log_DEBUG, "Using PBE start time 0x%08X (current time 0x%08X)", actualStartTime, RCL_Scheduler_getCurrentTime()); + + return RCL_CommandStatus_Active; +} + +/* + * ======== RCL_Scheduler_setStopTimes ======== + */ +RCL_StopType RCL_Scheduler_setStopTimes(void) +{ + RCL_StopType stopType = RCL_StopType_None; + + /* If stop times have not been found, do not program stop. Note that this + should only be done for very fast commands that are over as soon as + they start */ + if (rclSchedulerState.stopTimeState >= RCL_SchedulerStopTimeState_Found) + { + uintptr_t key = HwiP_disable(); + + if (rclSchedulerState.hardStopInfo.stopReason != RCL_SchedulerStopReason_None) + { + uint32_t stopTime = (rclSchedulerState.hardStopInfo.stopReason == RCL_SchedulerStopReason_Timeout) ? + rclSchedulerState.hardStopInfo.cmdStopTime : rclSchedulerState.hardStopInfo.schedStopTime; + + hal_setup_hard_stop_time(stopTime); + + if (!RCL_Scheduler_isLater(RCL_Scheduler_getCurrentTime(), stopTime)) + { + /* Hard stop already occurred */ + hal_cancel_hard_stop_time(); + stopType = RCL_StopType_Hard; + } + } + + if (rclSchedulerState.gracefulStopInfo.stopReason != RCL_SchedulerStopReason_None) + { + uint32_t stopTime = (rclSchedulerState.gracefulStopInfo.stopReason == RCL_SchedulerStopReason_Timeout) ? + rclSchedulerState.gracefulStopInfo.cmdStopTime : rclSchedulerState.gracefulStopInfo.schedStopTime; + + hal_setup_graceful_stop_time(stopTime); + + if (!RCL_Scheduler_isLater(RCL_Scheduler_getCurrentTime(), stopTime)) + { + /* Graceful stop already occurred */ + hal_cancel_graceful_stop_time(); + stopType = RCL_StopType_Graceful; + } + } + + rclSchedulerState.stopTimeState = RCL_SchedulerStopTimeState_Programmed; + + HwiP_restore(key); + } + return stopType; +} + +/* + * ======== RCL_Scheduler_isLater ======== + */ +bool RCL_Scheduler_isLater(uint32_t refTime, uint32_t chkTime) +{ + uint32_t timediff = refTime - chkTime; + if (timediff >= 0x20000000) + { + /* chkTime is later than refTime */ + return true; + } + else + { + /* chkTime is earlier than or same time as refTime */ + return false; + } +} + +/* + * ======== RCL_Scheduler_delta ======== + */ +int32_t RCL_Scheduler_delta(uint32_t refTime, uint32_t chkTime) +{ + uint32_t timediff = refTime - chkTime; + if (timediff >= 0x20000000) + { + /* chkTime is later than refTime. Get difference as a positive number */ + timediff = chkTime - refTime; + if (timediff >= 0x80000000) + { + /* Large difference - saturate */ + return (int32_t) 0x7FFFFFFF; + } + else + { + /* Difference is a positive value also as signed */ + return (int32_t) timediff; + } + } + else + { + /* chkTime is earlier than or same time as refTime. Return negative result or 0 */ + return (int32_t)(-timediff); + } +} + +/* + * ======== RCL_Scheduler_setSchedStopTime ======== + */ +RCL_StopType RCL_Scheduler_setSchedStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t schedStopTime) +{ + return rclSchedulerSetNewStopTime(stopInfo, schedStopTime, true); +} + +/* + * ======== RCL_Scheduler_setCmdStopTime ======== + */ +RCL_StopType RCL_Scheduler_setCmdStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t cmdStopTime) +{ + return rclSchedulerSetNewStopTime(stopInfo, cmdStopTime, false); +} + +/* + * ======== RCL_Scheduler_cancelSchedStopTime ======== + */ +RCL_StopType RCL_Scheduler_cancelSchedStopTime(RCL_SchedulerStopInfo *stopInfo) +{ + return rclSchedulerCancelStopTime(stopInfo, true); +} + +/* + * ======== RCL_Scheduler_cancelCmdStopTime ======== + */ +RCL_StopType RCL_Scheduler_cancelCmdStopTime(RCL_SchedulerStopInfo *stopInfo) +{ + return rclSchedulerCancelStopTime(stopInfo, false); +} + +static RCL_StopType rclSchedulerSetNewStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t newStopTime, bool sched) +{ + RCL_StopType immediateStop = RCL_StopType_None; + + /* Store current state of the stop info */ + RCL_SchedulerStopReason oldStopReason = stopInfo->stopReason; + uint32_t oldStopTime; + switch (stopInfo->stopReason) + { + case RCL_SchedulerStopReason_Timeout: + oldStopTime = stopInfo->cmdStopTime; + break; + + case RCL_SchedulerStopReason_Scheduling: + oldStopTime = stopInfo->schedStopTime; + break; + default: + oldStopTime = 0; + } + + /* Set new stop time and enable it */ + if (sched) + { + stopInfo->schedStopTime = newStopTime; + stopInfo->schedStopEnabled = 1; + } + else + { + stopInfo->cmdStopTime = newStopTime; + stopInfo->cmdStopEnabled = 1; + } + + /* Find updated earliest stop time */ + rclSchedulerFindEarliestStopTime(stopInfo); + + uint32_t stopTime; + /* One of the stop times will be set, since we just set it */ + stopTime = (stopInfo->stopReason == RCL_SchedulerStopReason_Timeout) ? + stopInfo->cmdStopTime : stopInfo->schedStopTime; + + /* Check if stop time has changed */ + if (oldStopReason != RCL_SchedulerStopReason_None || stopTime != oldStopTime) + { + /* Check if stop has been activated */ + if (rclSchedulerState.stopTimeState == RCL_SchedulerStopTimeState_Programmed) + { + /* Modify stop time and see if immediate stop is needed */ + immediateStop = RCL_Scheduler_setStopTimes(); + /* Notify handler that stop time has been changed */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventStopTimesUpdated); + } + } + + return immediateStop; +} + +static RCL_StopType rclSchedulerCancelStopTime(RCL_SchedulerStopInfo *stopInfo, bool sched) +{ + RCL_StopType immediateStop = RCL_StopType_None; + + /* Store current state of the stop info */ + RCL_SchedulerStopReason oldStopReason = stopInfo->stopReason; + uint32_t oldStopTime; + switch (stopInfo->stopReason) + { + case RCL_SchedulerStopReason_Timeout: + oldStopTime = stopInfo->cmdStopTime; + break; + + case RCL_SchedulerStopReason_Scheduling: + oldStopTime = stopInfo->schedStopTime; + break; + default: + oldStopTime = 0; + } + + /* Disable applicable stop time */ + if (sched) + { + stopInfo->schedStopEnabled = 0; + } + else + { + stopInfo->cmdStopEnabled = 0; + } + + /* Find updated earliest stop time */ + rclSchedulerFindEarliestStopTime(stopInfo); + + if (stopInfo->stopReason == RCL_SchedulerStopReason_None) + { + if (oldStopReason != RCL_SchedulerStopReason_None && rclSchedulerState.stopTimeState == RCL_SchedulerStopTimeState_Programmed) + { + /* Cancel stop time */ + if (stopInfo == &rclSchedulerState.hardStopInfo) + { + hal_cancel_hard_stop_time(); + } + else + { + hal_cancel_graceful_stop_time(); + } + } + } + else + { + uint32_t stopTime = (stopInfo->stopReason == RCL_SchedulerStopReason_Timeout) ? + stopInfo->cmdStopTime : stopInfo->schedStopTime; + + /* Check if stop time has changed */ + if (stopTime != oldStopTime) + { + /* Check if stop has been activated */ + if (rclSchedulerState.stopTimeState == RCL_SchedulerStopTimeState_Programmed) + { + /* Modify stop time and see if immediate stop is needed */ + immediateStop = RCL_Scheduler_setStopTimes(); + /* Notify handler that stop time has been changed */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventStopTimesUpdated); + } + } + } + + return immediateStop; +} + +/* + * ======== rclSchedulerFindEarliestStopTime ======== + */ +static void rclSchedulerFindEarliestStopTime(RCL_SchedulerStopInfo *stopInfo) +{ + /* Find which stop time comes first */ + if (stopInfo->cmdStopEnabled) + { + if (stopInfo->schedStopEnabled) + { + uint32_t currentTime = RCL_Scheduler_getCurrentTime(); + if (RCL_Scheduler_isLater(currentTime, stopInfo->cmdStopTime)) + { + if (RCL_Scheduler_isLater(currentTime, stopInfo->schedStopTime)) + { + /* Find difference from current time for each stop time */ + uint32_t timeDiffSched = stopInfo->schedStopTime - currentTime; + uint32_t timeDiffCmd = stopInfo->cmdStopTime - currentTime; + if (timeDiffSched < timeDiffCmd) + { + /* Scheduler stop time is first */ + stopInfo->stopReason = RCL_SchedulerStopReason_Scheduling; + } + else + { + /* Command stop time is first */ + stopInfo->stopReason = RCL_SchedulerStopReason_Timeout; + } + } + else + { + /* Scheduler stop time is already in the past */ + stopInfo->stopReason = RCL_SchedulerStopReason_Scheduling; + } + } + else + { + /* Command stop time is already in the past */ + stopInfo->stopReason = RCL_SchedulerStopReason_Timeout; + } + } + else + { + /* Command stop time is the only one */ + stopInfo->stopReason = RCL_SchedulerStopReason_Timeout; + } + } + else if (stopInfo->schedStopEnabled) + { + /* Scheduler stop time is the only one */ + stopInfo->stopReason = RCL_SchedulerStopReason_Scheduling; + } + else + { + stopInfo->stopReason = RCL_SchedulerStopReason_None; + } +} + +/* + * ======== RCL_Scheduler_postEvent ======== + */ +bool RCL_Scheduler_postEvent(RCL_Command_Handle c, RCL_Events e) +{ + RCL_Command *cmd = (RCL_Command *)c; + bool result = false; + if (cmd != NULL) + { + uintptr_t key = HwiP_disable(); + if (cmd->status > RCL_CommandStatus_Queued && cmd->status < RCL_CommandStatus_Finished) + { + rclSchedulerState.postedRclEvents.value |= e.value | RCL_EventSoftwareTriggered.value; + hal_trigger_command_fsm(); + result = true; + } + HwiP_restore(key); + } + return result; +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.h new file mode 100644 index 00000000..9ef6be5c --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Scheduler.h @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Scheduler_h__include +#define ti_drivers_RCL_Scheduler_h__include + +#include +#include + +#include +#include + +/** + * Number of ticks in the given number of microseconds + */ +#define RCL_SCHEDULER_SYSTIM_US(x) (((uint32_t) (x)) * 4U) +/** + * Number of ticks in the given number of milliseconds + */ +#define RCL_SCHEDULER_SYSTIM_MS(x) (((uint32_t) (x)) * 4U * 1000U) + + +/* Timing constants */ +#define ABS_START_TIME_OFFSET RCL_SCHEDULER_SYSTIM_US(100U) /*!< Delay from scheduled start to start trigger to LRF */ +#define IMM_START_TIME_OFFSET RCL_SCHEDULER_SYSTIM_US(90U) /*!< Delay from immediate start to start trigger to LRF */ +#define RCL_SCHEDULER_MARGIN_ARM RCL_SCHEDULER_SYSTIM_US(40U) /*!< Time to prepare FIFO + PBE */ +#define RCL_SCHEDULER_MARGIN_CONFIGURE RCL_SCHEDULER_SYSTIM_US(76U) /*!< Time to reload REGBANKs */ +#define RCL_SCHEDULER_MARGIN_LOAD RCL_SCHEDULER_SYSTIM_US(460U) /*!< Time to load TOPsm images */ +#define RCL_SCHEDULER_SLEEP_CUTOFF RCL_SCHEDULER_SYSTIM_MS(10U) /*!< Time margin when not to arm LRF immediately */ +#define RCL_SCHEDULER_TRIG_NOW_DELAY RCL_SCHEDULER_SYSTIM_US(50U) /*!< Delay to add to current time to allow start to be in the future */ +#if defined(DeviceFamily_CC23X0R5) || defined(DeviceFamily_CC23X0R2) || defined(DeviceFamily_CC23X0R22) || defined(DeviceFamily_CC2340R53) +#define RCL_SCHEDULER_WAKEUP_MARGIN RCL_SCHEDULER_SYSTIM_US(390U) /*!< Wakeup margin to allow for varying command and setup time */ +#else +#define RCL_SCHEDULER_WAKEUP_MARGIN RCL_SCHEDULER_SYSTIM_US(1000U)/*!< Wakeup margin to allow for varying command and setup time */ +#endif + +typedef enum { + RCL_SchedulerStopReason_None = 0, /*!< No stop active */ + RCL_SchedulerStopReason_Timeout = 1, /*!< Command stop time is active */ + RCL_SchedulerStopReason_Scheduling = 2, /*!< Scheduler stop is active */ + RCL_SchedulerStopReason_Api = 3, /*!< API stop has been sent and will take precedence */ +} RCL_SchedulerStopReason; + +typedef enum { + RCL_SchedulerStopTimeState_Init = 0, /*!< Stop times not calculated or programmed */ + RCL_SchedulerStopTimeState_Found = 1, /*!< Stop times calculated, but not programmed */ + RCL_SchedulerStopTimeState_Programmed = 2, /*!< Stop times calculated and programmed to timer */ +} RCL_SchedulerStopTimeState; + +typedef struct RCL_SchedulerStopInfo_s { + uint32_t cmdStopEnabled : 1; + uint32_t schedStopEnabled : 1; + uint32_t apiStopEnabled : 1; + RCL_SchedulerStopReason stopReason : 2; + uint32_t cmdStopTime; + uint32_t schedStopTime; +} RCL_SchedulerStopInfo; + +typedef struct RCL_SchedulerState_s { + RCL_Command *currCmd; + uint32_t nextWantsStop : 1; + RCL_SchedulerStopTimeState stopTimeState : 2; + RCL_SchedulerStopReason descheduleReason : 2; + RCL_Events postedRclEvents; /* Events to be handled by the command handler */ + uint32_t actualStartTime; + RCL_SchedulerStopInfo hardStopInfo; + RCL_SchedulerStopInfo gracefulStopInfo; + uint16_t requestedPhyFeatures; +} RCL_SchedulerState; + +extern RCL_SchedulerState rclSchedulerState; + +/** @defgroup timingHandlerFunctions Timing Handler Functions + * These functions are meant mostly to be used by handlers and RCL itself + * @{ + */ + +/** + * @brief Get relevant status when a command was stopped + * + * Returns the status to be set for a command that was stopped with the given stop source, + * depending on what caused the stop + * + * @note This function is intended as internal to RCL and its handlers + * + * @param stopType Stop type observed + * + * @return Command status that should be produced + */ +RCL_CommandStatus RCL_Scheduler_findStopStatus(RCL_StopType stopType); + +/** + * @brief Set start and stop time for LRF based on command + * + * Sets start and stop times for LRF based on scheduled times + * + * @note This function is intended as internal to RCL and its handlers + * + * @param cmd Pointer to running command + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setStartStopTime(const RCL_Command *cmd); + +/** + * @brief Set start and stop time for LRF based on command with earliest start time + * + * Sets start and stop times for LRF based on scheduled times, but delay start if needed due to hardware startup time + * + * @note This function is intended as internal to RCL and its handlers + * + * @param cmd Pointer to running command + * + * @param earliestStartTime Start at earliest at this time, or fail if delay not allowed + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setStartStopTimeEarliestStart(const RCL_Command *cmd, uint32_t earliestStartTime); + +/** + * @brief Set start and stop time for LRF + * + * Sets start and stop times for LRF based on provided times + * + * @note This function is intended as internal to RCL and its handlers + * + * @param timing Start and stop times to set + * + * @param scheduling Scheduling type + * + * @param allowDelay True if start may be delayed; false if late start is an error + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setCustomStartStopTime(const RCL_CommandTiming *timing, RCL_ScheduleType scheduling, bool allowDelay); + +/** + * @brief Set start and stop time for LRF with earliest start time + * + * Sets start and stop times for LRF based on provided times, but delay start if needed due to hardware startup time + * + * @note This function is intended as internal to RCL and its handlers + * + * @param timing Start and stop times to set + * + * @param scheduling Scheduling type + * + * @param allowDelay True if start may be delayed; false if late start is an error + * + * @param earliestStartTime Start at earliest at this time, or fail if delay not allowed + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setCustomStartStopTimeEarliestStart(const RCL_CommandTiming *timing, RCL_ScheduleType scheduling, bool allowDelay, uint32_t earliestStartTime); + +/** + * @brief Set stop time for LRF based on command when it does not need a start trigger + * + * Sets stop times for LRF based on scheduled times, but do not program any start trigger + * + * @note This function is intended as internal to RCL and its handlers + * + * @param cmd Pointer to running command + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setCmdStopTimeNoStartTrigger(const RCL_Command *cmd); + +/** + * @brief Set new start time for LRF to now, after a previous start + * + * @note This function is intended as internal to RCL and its handlers + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setNewStartNow(void); + +/** + * @brief Set new start time for LRF to given absolute time, after a previous start + * + * @note This function is intended as internal to RCL and its handlers + * + * @param startTime Absloute start time + * + * @param allowDelay True if start may be delayed; false if late start is an error + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setNewStartAbsTime(uint32_t startTime, bool allowDelay); + +/** + * @brief Set new start time for LRF to given time relative to previous LRF start + * + * @note This function is intended as internal to RCL and its handlers + * + * @param relStartTime Start time relative to previous actual start time of LRF + * + * @return Command status that should be produced if the command should end or RCL_CmdStatus_Active to go on + */ +RCL_CommandStatus RCL_Scheduler_setNewStartRelTime(uint32_t relStartTime); + +/** + * @brief Function to apply relevant stop times + * + * Sets stop times for LRF based on scheduled times + * + * @note This function is intended as internal to RCL and its handlers + * + * @return Stop type if stop needs to be applied immediately + */ +RCL_StopType RCL_Scheduler_setStopTimes(void); + +/** @} + */ + +/** @defgroup timingApiFunctions Timing API Functions + * These functions are useful as part of the API to RCL + * @{ + */ + +/** + * @brief Find if a time instant occurs after another, allowing wrap-around + * + * Checks if a time is before or after another. In the processing, a time is assumed to be before + * the reference if it is less than 1/8 of the full timer range (134 seconds) before it; otherwise + * it is assumed to be in the future. This means that the time presumed to be the latest should + * always be the second parameter (%chkTime) + * + * @param refTime Reference time + * + * @param chkTime Time to be checked + * + * @return true if %chkTime comes after %refTime. false if %chkTime comes before %refTime or if they are equal. + */ +bool RCL_Scheduler_isLater(uint32_t refTime, uint32_t chkTime); + +/** + * @brief Find the time difference between two times, allowing wrap-around + * + * Finds the signed difference between two times, saturated at the maximum signed 32-bit integer + * value. In the processing, a time is assumed to be before the reference if it is less than 1/8 + * of the full timer range (134 seconds) before it; otherwise + * it is assumed to be in the future. + * + * @param refTime Reference time + * + * @param chkTime Time to be checked + * + * @return Time difference (%chkTime-%refTime) corrected for wrap-around. + * Saturated at 0x7FFFFFFF (8 min 57 sec). + */ +int32_t RCL_Scheduler_delta(uint32_t refTime, uint32_t chkTime); + +/** + * @brief Get current time + * + * @return Current SYSTIM time (0.25 us steps) usable for radio command timing + */ +static inline uint32_t RCL_Scheduler_getCurrentTime(void) +{ + return hal_get_current_time(); +} + +/** + * @brief Set scheduler stop time + * + * Sets scheduler stop time for the given stop type, finds which of the + * active stop times comes first, sets selection bits accordingly and + * reprograms the stop time if it was already programmed. + * + * @param stopInfo Pointer to stop info for the relevant stop type + * + * @param schedStopTime New scheduler stop time to apply + * + * @return Stop type if stop needs to be applied immediately + */ +RCL_StopType RCL_Scheduler_setSchedStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t schedStopTime); + +/** + * @brief Set command stop time + * + * Sets command stop time for the given stop type, finds which of the + * active stop times comes first, sets selection bits accordingly and + * reprograms the stop time if it was already programmed. + * + * @param stopInfo Pointer to stop info for the relevant stop type + * + * @param cmdStopTime New command stop time to apply + * + * @return Stop type if stop needs to be applied immediately + */ +RCL_StopType RCL_Scheduler_setCmdStopTime(RCL_SchedulerStopInfo *stopInfo, uint32_t cmdStopTime); + +/** + * @brief Cancel scheduler stop time + * + * Cancels scheduler stop time for the given stop type, finds if there + * is still an active stop time, cancels or reprograms the stop time + * if it was already programmed. + * + * @param stopInfo Pointer to stop info for the relevant stop type + * + * @return Stop type if stop needs to be applied immediately + */ +RCL_StopType RCL_Scheduler_cancelSchedStopTime(RCL_SchedulerStopInfo *stopInfo); + +/** + * @brief Cancel command stop time + * + * Cancels command stop time for the given stop type, finds if there + * is still an active stop time, cancels or reprograms the stop time + * if it was already programmed. + * + * @param stopInfo Pointer to stop info for the relevant stop type + * + * @return Stop type if stop needs to be applied immediately + */ +RCL_StopType RCL_Scheduler_cancelCmdStopTime(RCL_SchedulerStopInfo *stopInfo); + +/** + * @brief Post event to command handler + * + * @param[in] c Command to post event to + * @param[in] e Event(s) to post + * @return true If command was active and event was posted + * @return false If command was not active + */ +bool RCL_Scheduler_postEvent(RCL_Command_Handle c, RCL_Events e); + +/** @} + */ + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.c b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.c new file mode 100644 index 00000000..0b36a496 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RCL_Tracer.c ======== + */ + + +/* + * ======== RCL_Tracer_enable ======== + */ +void __attribute__((weak)) RCL_Tracer_enable(void) +{ + /* Internal TI use: Enables RF Tracer */ +} + +/* + * ======== RCL_Tracer_disable ======== + */ +void __attribute__((weak)) RCL_Tracer_disable(void) +{ + /* Internal TI use: Disables RF Tracer */ +} + +/* + * ======== RCL_Tracer_wakeup ======== + */ +void __attribute__((weak)) RCL_Tracer_wakeup(void) +{ + /* Internal TI use: Re-enables RF Tracer after wakeup from standby*/ +} + +/* + * ======== RCL_Tracer_standby ======== + */ +void __attribute__((weak)) RCL_Tracer_standby(void) +{ + /* Internal TI use: Prepares RF Tracer for standby */ +} + +/* + * ======== RCL_GPIO_enable ======== + */ +void __attribute__((weak)) RCL_GPIO_enable(void) +{ + /* Internal TI use: Enables RCL GPIOs */ +} + +/* + * ======== RCL_GPIO_disable ======== + */ +void __attribute__((weak)) RCL_GPIO_disable(void) +{ + /* Internal TI use: Disables RCL GPIOs */ +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.h new file mode 100644 index 00000000..d24829aa --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Tracer.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Tracer_h__include +#define ti_drivers_RCL_Tracer_h__include + + +extern void RCL_Tracer_enable(void); +extern void RCL_Tracer_disable(void); +extern void RCL_Tracer_wakeup(void); +extern void RCL_Tracer_standby(void); +extern void RCL_GPIO_enable(void); +extern void RCL_GPIO_disable(void); + + +#endif /* ti_drivers_RCL_Tracer_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Types.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Types.h new file mode 100644 index 00000000..5e283473 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Types.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_Types_h__include +#define ti_drivers_RCL_Types_h__include + +typedef void * RCL_Command_Handle; +typedef struct RCL_Command_s RCL_Command; + +typedef struct RCL_CommandRuntime_s RCL_CommandRuntime; +typedef struct RCL_CommandTiming_s RCL_CommandTiming; + +typedef struct RCL_Client_s RCL_Client; +typedef struct RCL_Client_s *RCL_Handle; + +typedef union RCL_Events_u RCL_Events; +typedef union LRF_Events_u LRF_Events; + +typedef struct LRF_TOPsmImage_s LRF_TOPsmImage; +typedef struct LRF_RegConfigList_s LRF_RegConfigList; +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/RCL_Version.h b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Version.h new file mode 100644 index 00000000..4cb5b6c5 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/RCL_Version.h @@ -0,0 +1,15 @@ + +#ifndef __source_ti_drivers_rcl_rcl_version__ +#define __source_ti_drivers_rcl_rcl_version__ + +#define RCL_VERSION_MAJOR 0x08 +#define RCL_VERSION_MINOR 0x20 +#define RCL_VERSION_PATCH 0x00 +#define RCL_VERSION_BUILD 0x02 +#define RCL_VERSION_CHANNEL "eng" + +#define RCL_VERSION_SHA 0x9e10067d6ba68e85 +#define RCL_VERSION 0x08200002 +#define RCL_VERSION_CHANNEL_NUMBER 0x3 + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/commands/adc_noise.h b/simplelink_lpf3/source/ti/drivers/rcl/commands/adc_noise.h new file mode 100644 index 00000000..49ef7dba --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/commands/adc_noise.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_commands_adc_noise_h__include +#define ti_drivers_RCL_commands_adc_noise_h__include + +#include +#include + +typedef struct RCL_CMD_ADC_NOISE_GET RCL_CmdAdcNoiseGet; + +/* Command IDs */ +#define RCL_CMDID_ADC_NOISE_GET 0x0001 + +/* Max number of samples that can be collected in one session */ +#define RCL_ADC_NOISE_MAX_NUM_WORDS (1024) + +/** + * @brief ADC noise command + * + * Command to collect ADC samples from radio. + * + * This command is used to collect ADC samples from the radio. The samples represent noise (random data), + * and is intended only to be used as input for entropy generation. + * + * If the output buffer is set to NULL, the samples must be read out by the caller before submitting a new RCL command. + * The location of the samples can always be read from the output-pointer, which will be updated by the RCL-handler + * in the case where a NULL-pointer is passed. + * + * # Data format # + * + * The data format of the output is described below + * + * | Word | word[31] | word[30..26] | word[25..21] | word[20..16] | word[15] | word[14..10] | word[9..5] | word[4..0] | + * | --- | --- | --- | --- | --- | --- | --- | --- | --- | + * | 0 | ‘0’ | IAC2 | IAC1 | IAC0 | ‘0’ | QAC2 | QAC1 | QAC0 | + * | 1 | ‘0’ | IAC5 | IAC4 | IAC3 | ‘0’ | QAC5 | QAC4 | QAC3 | + * | ... | | | | | | | | | + * | i | ‘0’ | IAC(3i+2) | IAC(3i+1) | IAC(3i) | ‘0’ | QAC(3i+2) | QAC(3i+1) | QAC(3i) | + * + * + */ +struct RCL_CMD_ADC_NOISE_GET +{ + RCL_Command common; + uint32_t numWords; /*!< Number of ADC sample words to collect. Range [1..1024] */ + uint32_t *output; /*!< Buffer for storing ADC samples. NULL: Do not copy samples, but leave them in the LRF RAM. + * This pointer will be updated by the RCL-handler to point to the location in RAM where + * the data is stored. + */ +}; + +#define RCL_CmdAdcNoiseGet_Default() \ + (RCL_CmdAdcNoiseGet) \ + { \ + .common = RCL_Command_Default(RCL_CMDID_ADC_NOISE_GET, \ + RCL_Handler_ADC_Noise_getNoise), \ + .numWords = RCL_ADC_NOISE_MAX_NUM_WORDS, \ + .output = NULL, \ + } + +#endif // ti_drivers_RCL_commands_adc_noise_h__include diff --git a/simplelink_lpf3/source/ti/drivers/rcl/commands/ble5.h b/simplelink_lpf3/source/ti/drivers/rcl/commands/ble5.h new file mode 100644 index 00000000..027259ea --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/commands/ble5.h @@ -0,0 +1,808 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_commands_ble5_h__include +#define ti_drivers_RCL_commands_ble5_h__include + +typedef struct RCL_FL_ENTRY_t RCL_FL_Entry; +typedef struct RCL_FILTER_LIST_t RCL_FilterList; + +typedef struct RCL_ADDR_TYPE_t RCL_AddrType; +typedef struct RCL_CONN_PARAMS_t RCL_ConnParams; + +typedef struct RCL_CMD_BLE5_ADV_t RCL_CmdBle5Advertiser; +typedef struct RCL_CMD_BLE5_AUX_ADV_t RCL_CmdBle5AuxAdvertiser; +typedef struct RCL_CMD_BLE5_PER_ADV_t RCL_CmdBle5PeriodicAdvertiser; +typedef struct RCL_CMD_BLE5_INITIATOR_t RCL_CmdBle5Initiator; +typedef struct RCL_CMD_BLE5_SCANNER_t RCL_CmdBle5Scanner; +typedef struct RCL_CMD_BLE5_PER_SCANNER_t RCL_CmdBle5PeriodicScanner; +typedef struct RCL_CMD_BLE5_CONNECTION_t RCL_CmdBle5Connection; +typedef struct RCL_CMD_BLE5_DTM_TX RCL_CmdBle5DtmTx; +typedef struct RCL_CMD_BLE5_GENERIC_RX_t RCL_CmdBle5GenericRx; +typedef struct RCL_CMD_BLE5_GENERIC_TX_t RCL_CmdBle5GenericTx; +typedef struct RCL_CMD_BLE5_TX_TEST_t RCL_CmdBle5TxTest; + +typedef struct RCL_CTX_ADVERTISER_t RCL_CtxAdvertiser; +typedef struct RCL_CTX_PER_ADVERTISER_t RCL_CtxPeriodicAdvertiser; +typedef struct RCL_CTX_SCAN_INIT_t RCL_CtxScanInit; +typedef struct RCL_CTX_PER_SCANNER_t RCL_CtxPeriodicScanner; +typedef struct RCL_CTX_CONNECTION_t RCL_CtxConnection; +typedef struct RCL_CTX_GENERIC_RX_t RCL_CtxGenericRx; +typedef struct RCL_CTX_GENERIC_TX_t RCL_CtxGenericTx; + +typedef struct RCL_STATS_ADV_SCAN_INIT_t RCL_StatsAdvScanInit; +typedef struct RCL_STATS_CONNECTION_t RCL_StatsConnection; +typedef struct RCL_STATS_GENERIC_RX_t RCL_StatsGenericRx; + +/** + * @brief Type for BLE channels + * + * 0-39: BLE channel number, indicates standard BLE whitening + * 64-103: Physical channel number; 64 is 2402 MHz, 65 is 2404 MHz, etc. Whitening disabled + * 128-255: Custom frequency programmed with %RCL_BLE5_setDefaultRfFrequency(); custom whitening. + * See %BLE_CUSTOM_FREQ_BM. + */ +typedef uint8_t RCL_Ble5Channel; + +/** + * @brief PHY returned in status of received packets + * + */ +typedef enum { + RCL_Ble5_RxPhy1Mbps = 0, + RCL_Ble5_RxPhy2Mbps = 1, + RCL_Ble5_RxPhyCodedS8 = 2, + RCL_Ble5_RxPhyCodedS2 = 3, +} RCL_Ble5_RxPhy; + +/** + * @brief Appended packet status field from RX buffer + * + */ +typedef union { + struct { + RCL_Ble5_RxPhy phy :2; /*!< Received PHY */ + uint8_t crcError :1; /*!< True if packet had CRC error */ + uint8_t ignored :1; /*!< True if packet was ignored */ + uint8_t ignoredRpa :1; /*!< True if packet should have been ignored due to unknown RPA, but was kept due to rpaMode */ + uint8_t ignoredSyncInfo :1; /*!< True if packet should have been ignored due to unknown RPA, but was kept due to periodicSyncEstablishment */ + uint8_t reserved :2; + }; + uint8_t value; +} RCL_Ble5_RxPktStatus; + +/* Invalid packet status */ +#define RCL_BLE5_RX_PKT_STATUS_INVALID 0xFF + +/* Do includes after typedefs, as the types are needed in ti/drivers/rcl/handlers/ble5.h */ +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/pbe_ble5_ram_regs.h) + +/* Command IDs for BLE commands */ +#define RCL_CMDID_BLE5_ADVERTISER 0x1001U +#define RCL_CMDID_BLE5_INITIATOR 0x1002U +#define RCL_CMDID_BLE5_SCANNER 0x1003U +#define RCL_CMDID_BLE5_CONNECTION 0x1004U +#define RCL_CMDID_BLE5_DTM_TX 0x1005U +#define RCL_CMDID_BLE5_GENERIC_RX 0x1006U +#define RCL_CMDID_BLE5_GENERIC_TX 0x1007U +#define RCL_CMDID_BLE5_TX_TEST 0x1008U +#define RCL_CMDID_BLE5_AUX_ADV 0x1009U +#define RCL_CMDID_BLE5_PERIODIC_ADV 0x100AU +#define RCL_CMDID_BLE5_PERIODIC_SCAN 0x100BU + +/** + * @brief Bit mask indicating the use of a custom frequency + * + * If a channel or chanMap parameter has this bit set, the RF frequency used must be programmed + * with %RCL_BLE5_setDefaultRfFrequency(), and the whitening is initialzed by bits 0-6 of channel + * or chanMap + */ +#define BLE_CUSTOM_FREQ_BM 0x80U + +/** + * @brief Filter list entry + * + * Accept or reject filter entry + */ +struct RCL_FL_ENTRY_t { + union + { + struct + { + uint16_t enabled : 1; /*!< 1 if the entry is used; 0 otherwise */ + uint16_t addType : 1; /*!< Address type of this entry */ + uint16_t duplicateIgn : 1; /*!< 1 to ignore the entry due to duplicate address filtering (scanners only) */ + uint16_t privIgn : 1; /*!< 1 to ignore the entry due to privacy (initiators only) */ + uint16_t reserved : 12;/*!< Reserved, set to 0 */ + } ctl; + uint16_t ctlWord; + }; + uint16_t address[3]; /*!< Address of entry */ +}; + +/** + * @brief Filter list object + * + * Accept or reject filter list + */ +struct RCL_FILTER_LIST_t { + uint32_t numEntries; + RCL_FL_Entry entries[16]; +}; + +/** + * @brief Address type + * + * Address type for own address and peer address + */ +struct RCL_ADDR_TYPE_t { + uint8_t peer :1; /*!< Address type for peer device (0: public. 1: random) */ + uint8_t own :1; /*!< Address type for this device (0: public. 1: random) */ + uint8_t reserved: 6; /*!< Reserved, set to 0 */ +}; + +/** + * @brief Connection parameters + * + * Connection parameters for AUX_CONNECT_REQ based on received AuxPhy + */ +struct RCL_CONN_PARAMS_t { + struct + { + uint16_t interval; + uint16_t latency; + uint16_t timeout; + } ble2M; + struct + { + uint16_t interval; + uint16_t latency; + uint16_t timeout; + } bleCoded; +}; + +/** + * @brief Advertiser command + * + * Command to run BLE advertiser. The advertisement type is found from the packet type transmitted. + */ +struct RCL_CMD_BLE5_ADV_t { + RCL_Command common; + uint8_t chanMap; /*!< Channel map. Bit positions 0-2 correspond to channels 37-39; a 1 means channel enabled */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint8_t order; /*!< Order to run channels. 0: Run in increasing order. 1-5: Other order. Others: Reserved */ + uint8_t highDuty; /*!< High duty-cycle advertising (directed advertising only) 0: Disabled. 1 Enabled */ + uint32_t connectPktTime; /*!< Time of received CONNECT_IND or AUX_CONNECT_REQ packet is returned if connection is formed */ + RCL_CtxAdvertiser *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdBle5Advertiser_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_ADVERTISER, \ + RCL_Handler_BLE5_adv), \ + .chanMap = 0x7, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .order = 0, \ + .highDuty = 0, \ + .connectPktTime = 0, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdBle5Advertiser_DefaultRuntime() (RCL_CmdBle5Advertiser) RCL_CmdBle5Advertiser_Default() + +/** + * @brief Secondary Channel Advertiser command + * + * Command to run BLE advertiser on a secondary channel. The advertisement type is found from the packet type transmitted. + */ +struct RCL_CMD_BLE5_AUX_ADV_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint32_t connectPktTime; /*!< Time of received CONNECT_IND packet is returned if connection is formed - Not supported in this release. */ + RCL_CtxAdvertiser *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdBle5AuxAdvertiser_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_AUX_ADV, \ + RCL_Handler_BLE5_aux_adv), \ + .channel = 0, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdBle5AuxAdvertiser_DefaultRuntime() (RCL_CmdBle5AuxAdvertiser) RCL_CmdBle5AuxAdvertiser_Default() + +/** + * @brief Advertiser context + * + * Context for advertiser command + */ +struct RCL_CTX_ADVERTISER_t { + RCL_FilterList *filterListConn; /*!< Filter list for initiator packets */ + RCL_FilterList *filterListScan; /*!< Filter list for scanner packets */ + List_List txBuffers; /*!< Linked list of packets to transmit: Advertisement followed by scan response */ + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + uint16_t advA[3]; /*!< Advertiser address of type %addrType.own */ + uint16_t peerA[3]; /*!< Directed advertising: Peer device address of type %addrType.peer */ + RCL_AddrType addrType; /*!< Address types */ + uint8_t filterPolicy: 2; /*!< Filter policy */ + uint8_t privIgnMode: 1; /*!< Privacy ignore mode. 0: Use filter list only when filter policy says. 1: Use filter list to ignore packets with privIgn bit set for all filter policies */ + uint8_t rpaModePeer: 1; /*!< RPA mode for peer address. 0: Treat RPA normally. 1: Report packets where advertiser address is an unknown RPA */ + uint8_t acceptAllRpaConnectInd: 1; /*!< CONNECT_IND RPA treatment. 0: Treat RPA in InitA normally. 1: Accept all RPA in InitA of CONNECT_IND. */ +}; + +#define RCL_CtxAdvertiser_Default() \ +{ \ + .filterListConn = NULL, \ + .filterListScan = NULL, \ + .txBuffers = { 0 }, \ + .rxBuffers = { 0 }, \ + .advA = { 0 }, \ + .peerA = { 0 }, \ + .addrType = { 0 }, \ + .filterPolicy = 0, \ + .privIgnMode = 0, \ + .rpaModePeer = 0, \ + .acceptAllRpaConnectInd = 0 \ +} +#define RCL_CtxAdvertiser_DefaultRuntime() (RCL_CtxAdvertiser) RCL_CtxAdvertiser_Default() + +/** + * @brief Periodic advertiser command + * + * Command to run BLE periodic advertiser. + */ +struct RCL_CMD_BLE5_PER_ADV_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + RCL_CtxPeriodicAdvertiser *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdBle5PeriodicAdvertiser_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_PERIODIC_ADV, \ + RCL_Handler_BLE5_periodicAdv), \ + .channel = 0, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdBle5PeriodicAdvertiser_DefaultRuntime() (RCL_CmdBle5PeriodicAdvertiser) RCL_CmdBle5PeriodicAdvertiser_Default() + +/** + * @brief Periodic Advertiser context + * + * Context for periodic advertiser command + */ +struct RCL_CTX_PER_ADVERTISER_t { + List_List txBuffers; /*!< Linked list of packets to transmit. Only AUX_SYNC_IND and AUX_CHAIN_IND */ + uint32_t accessAddress; /*!< Access address */ + uint32_t crcInit; /*!< CRC initialization value (24 bits) */ +}; + +#define RCL_CtxPeriodicAdvertiser_Default() \ +{ \ + .txBuffers = { 0 }, \ + .accessAddress = 0, \ + .crcInit = 0, \ +} +#define RCL_CtxPeriodicAdvertiser_DefaultRuntime() (RCL_CtxPeriodicAdvertiser) RCL_CtxPeriodicAdvertiser_Default() + +/** + * @brief Initiator command + * + * Command to run BLE initiator. + */ +struct RCL_CMD_BLE5_INITIATOR_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t maxAuxPtrWaitTime; /*!< Maximum time to wait for AuxPtr before ending command (1 us units). 0: No limit */ + bool dynamicWinOffset; /*!< Window offset processing. 0: Fixed. 1: Dynamic */ + bool acceptLegacy : 1; /*!< Accept legacy advertising. 0: Do not accept. 1: Accept */ + bool acceptExtended : 1; /*!< Accept extended advertising. 0: Do not accept. 1: Accept */ + uint32_t connectTime; /*!< For dynamic window offset, wanted connect time is given as input. In all cases, actual connect time is returned. */ + RCL_CtxScanInit *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdInitiator_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_INITIATOR, \ + RCL_Handler_BLE5_scan_init), \ + .channel = 37, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .maxAuxPtrWaitTime = 30000, \ + .dynamicWinOffset = 0, \ + .acceptLegacy = 1, \ + .acceptExtended = 0, \ + .connectTime = 0, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdInitiator_DefaultRuntime() (RCL_CmdBle5Initiator) RCL_CmdInitiator_Default() + +/** + * @brief Scanner command + * + * Command to run BLE scanner + */ +struct RCL_CMD_BLE5_SCANNER_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t maxAuxPtrWaitTime; /*!< Maximum time to wait for AuxPtr before ending command (1 us units). 0: No limit */ + bool activeScan; /*!< Scan type. 0: Passive. 1: Active */ + bool acceptLegacy : 1; /*!< Accept legacy advertising. 0: Do not accept. 1: Accept */ + bool acceptExtended : 1; /*!< Accept extended advertising. 0: Do not accept. 1: Accept */ + RCL_CtxScanInit *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdScanner_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_SCANNER, \ + RCL_Handler_BLE5_scan_init), \ + .channel = 37, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .maxAuxPtrWaitTime = 20000, \ + .activeScan = 0, \ + .acceptLegacy = 1, \ + .acceptExtended = 0, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdScanner_DefaultRuntime() (RCL_CmdBle5Scanner) RCL_CmdScanner_Default() + +/** + * @brief Scanner and initiator context + * + * Context for scanner or initiator command + */ +struct RCL_CTX_SCAN_INIT_t { + RCL_FilterList *filterList; /*!< Filter list */ + List_List txBuffers; /*!< Linked list of packets to transmit: Only CONNECT_IND and AUX_CONNECT_REQ */ + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + uint16_t ownA[3]; /*!< Own device address of type %addrType.own */ + uint16_t peerA[3]; /*!< Initiator: Peer device address of type %addrType.peer */ + RCL_AddrType addrType; /*!< Address types */ + uint8_t filterPolicy : 1; /*!< Filter policy */ + uint8_t scanExtFilterPolicy: 1; /*!< Extended filter policy for scanners */ + uint8_t rpaModeOwn: 1; /*!< RPA mode for own address. 0: Treat RPA normally. 1: Report packets where target address is an unknown RPA */ + uint8_t rpaModePeer: 1; /*!< RPA mode for peer address. 0: Treat RPA normally. 1: Report packets where advertiser address is an unknown RPA */ + uint8_t acceptAllRpaConnectRsp: 1; /*!< AUX_CONNECT_RSP RPA treatment. 0: Treat RPA in TargetA normally. 1: Accept all RPA in TargetA of AUX_CONNECT_RSP - Not supported in this release */ + uint8_t periodicSyncEstablishment: 1; /*!< Synchronization to periodic advertisement. 0: Disabled. 1: Report all packets with SyncInfo present */ + uint16_t initialBackoff; /*!< Initial backoff value */ + uint8_t backoffUpper; /*!< Backoff parameter */ + struct + { + uint8_t backOffLastFail : 1; + uint8_t backOffLastSucceed : 1; + uint8_t reserved : 6; + } backoffStatus; /*!< Backoff parameter */ + uint16_t localClockAccuracy; /*!< Maximum relative local clock error (in ppm) scaled by 2^26 */ + RCL_ConnParams *connParams; /*!< Pointer to connection parameters structure (LE 2M and LE Coded only). LE 1M parameters are provided in the default CONNECT_IND/AUX_CONNECT_REQ */ +}; + +#define RCL_CtxScanInit_Default() \ +{ \ + .filterList = NULL, \ + .txBuffers = { 0 }, \ + .rxBuffers = { 0 }, \ + .ownA = { 0 }, \ + .peerA = { 0 }, \ + .addrType = { 0 }, \ + .filterPolicy = 0, \ + .scanExtFilterPolicy = 0, \ + .rpaModeOwn = 0, \ + .rpaModePeer = 0, \ + .acceptAllRpaConnectRsp = 0, \ + .periodicSyncEstablishment = 0, \ + .initialBackoff = 1, \ + .backoffUpper = 0, \ + .backoffStatus = { 0 }, \ + .localClockAccuracy = 3355, \ + .connParams = NULL, \ +} +#define RCL_CtxScanInit_DefaultRuntime() (RCL_CtxScanInit) RCL_CtxScanInit_Default() + +/** + * @brief Periodic Scanner command + * + * Command to run BLE periodic scanner + */ +struct RCL_CMD_BLE5_PER_SCANNER_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t maxAuxPtrWaitTime; /*!< Maximum time to wait for AuxPtr before ending command (1 us units). 0: No limit */ + RCL_CtxPeriodicScanner *ctx; /*!< Pointer to context structure */ + RCL_StatsAdvScanInit *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdPeriodicScanner_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_PERIODIC_SCAN, \ + RCL_Handler_BLE5_periodicScan), \ + .channel = 37, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .maxAuxPtrWaitTime = 20000, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdPeriodicScanner_DefaultRuntime() (RCL_CmdBle5PeriodicScanner) RCL_CmdPeriodicScanner_Default() + +/** + * @brief Periodic scanner context + * + * Context for periodic scanner command + */ +struct RCL_CTX_PER_SCANNER_t { + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + uint16_t localClockAccuracy; /*!< Maximum relative local clock error (in ppm) scaled by 2^26 */ + uint32_t accessAddress; /*!< Access address */ + uint32_t crcInit; /*!< CRC initialization value (24 bits) */ +}; + +#define RCL_CtxPeriodicScanner_Default() \ +{ \ + .rxBuffers = { 0 }, \ + .localClockAccuracy = 3355, \ + .accessAddress = 0, \ + .crcInit = 0, \ +} +#define RCL_CtxPeriodicScanner_DefaultRuntime() (RCL_CtxPeriodicScanner) RCL_CtxPeriodicScanner_Default() + +/** + * @brief Statistics structure for advertiser, scanner and initiator + * + * Statistics for advertiser, scanner or initiator command + */ +struct RCL_STATS_ADV_SCAN_INIT_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t timestampValid; /*!< Returns 1 if %lastTimestamp is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet */ + uint32_t lastTimestamp; /*!< Timestamp of last successfully received packet */ + uint16_t nRxNok; /*!< Number of packets received with CRC error */ + uint16_t nRxIgnored; /*!< Number of packets to be ignored received */ + uint16_t nRxOk; /*!< Number of correctly received, accepted packets */ + uint8_t nRxFifoFull; /*!< Number of packets received which could not be stored */ + uint8_t nTx; /*!< Number of packets transmitted */ +}; + +#define RCL_StatsAdvScanInit_Default() \ +{ \ + .config = { 0 }, \ + .timestampValid = 0, \ + .lastRssi = LRF_RSSI_INVALID, \ +} +#define RCL_StatsAdvScanInit_DefaultRuntime() (RCL_StatsAdvScanInit) RCL_StatsAdvScanInit_Default() + +/** + * @brief Connection command + * + * Command to run connection event as central or peripheral + */ +struct RCL_CMD_BLE5_CONNECTION_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t relRxTimeoutTime; /*!< Peripheral only: Time before timing out the first packet of the event (0.25 us units). 0: No timeout. */ + RCL_CtxConnection *ctx; /*!< Pointer to context structure */ + RCL_StatsConnection *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdBle5Connection_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_CONNECTION, \ + RCL_Handler_BLE5_conn), \ + .channel = 0, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdBle5Connection_DefaultRuntime() (RCL_CmdBle5Connection) RCL_CmdBle5Connection_Default() + +/** + * @brief Connection context + * + * Context for a connection + */ +struct RCL_CTX_CONNECTION_t { + List_List txBuffers; /*!< Linked list of packets to transmit. RCL will pop packets that have been ACKed */ + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + bool isPeripheral; /*!< 0: Run as central. 1: Run as peripheral */ + uint16_t seqStat; /*!< Sequencer status. Use default initialization for a new connection and keep unchanged between connection events on the same connection. */ + uint32_t accessAddress; /*!< Access address */ + uint32_t crcInit; /*!< CRC initialization value (24 bits) */ +}; + +#define _INIT_SEQSTAT (PBE_BLE5_RAM_SEQSTAT_LASTRXSN_M | \ + PBE_BLE5_RAM_SEQSTAT_LASTTXSN_M | \ + PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_M ) + +#define RCL_CtxConnection_Default() \ +{ \ + .txBuffers = { 0 }, \ + .rxBuffers = { 0 }, \ + .isPeripheral = 0, \ + .seqStat = _INIT_SEQSTAT, \ + .accessAddress = 0, \ + .crcInit = 0, \ +} +#define RCL_CtxConnection_DefaultRuntime() (RCL_CtxConnection) RCL_CtxConnection_Default() + +/** + * @brief Statistics structure for connection + * + * Statistics for connection command + */ +struct RCL_STATS_CONNECTION_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t anchorValid; /*!< Returns 1 if %anchorPoint is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet */ + uint32_t anchorPoint; /*!< Peripheral only: Timestamp of first received packet */ + uint8_t nTxDone; /*!< Number of TX buffers finished because ACK is received */ + uint8_t nTxAck; /*!< Number of ACKs received on transmitted packets */ + uint8_t nTxCtlAck; /*!< Number of ACKs received on transmitted control packets */ + uint8_t nTxCtl; /*!< Number of control packets transmitted */ + uint8_t nTxRetrans; /*!< Number of packets retransmitted */ + uint8_t nRxNok; /*!< Number of packets received with CRC error */ + uint8_t nRxIgnored; /*!< Number of packets to be ignored received */ + uint8_t nRxEmpty; /*!< Number of empty packets received */ + uint8_t nRxFifoFull; /*!< Number of packets received which could not be stored */ + uint8_t nRxOk; /*!< Number of correctly received, accepted packets */ + uint8_t nTx; /*!< Number of packets transmitted */ + uint8_t nRxCtl; /*!< Number of control packets received */ + uint8_t nRxCtlAck; /*!< Number of ACKs transmitted on received control packets */ +}; + +#define RCL_StatsConnection_Default() \ +{ \ + .config = { 0 }, \ + .anchorValid = 0, \ + .lastRssi = LRF_RSSI_INVALID, \ +} +#define RCL_StatsConnection_DefaultRuntime() (RCL_StatsConnection) RCL_StatsConnection_Default() + +/** + * @brief DTM TX command + * + * Command to send BLE direct test mode packets + */ +struct RCL_CMD_BLE5_DTM_TX { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint8_t pduHeader; /*!< PDU header to transmit; payload is given according to BLE DTM spec */ + uint8_t pduLength; /*!< PDU length */ + uint8_t cteInfo; /*!< CTE info; decides length of CTE. Ignored if bit #5 of %pduHeader is 0. Not supported in this version. */ + uint16_t periodUs; /*!< Time between start of each packet in 1 us units */ + uint16_t numPackets; /*!< Number of packets to transmit. 0: Transmit indefinitely until command times out or is stopped. */ +}; + +#define RCL_CmdBle5DtmTx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_DTM_TX, \ + RCL_Handler_BLE5_dtmTx), \ + .channel = 64, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .pduHeader = 0x00, \ + .pduLength = 37, \ + .cteInfo = 0x14, \ + .periodUs = 625, \ + .numPackets = 0, \ +} +#define RCL_CmdBle5DtmTx_DefaultRuntime() (RCL_CmdBle5DtmTx) RCL_CmdBle5DtmTx_Default() + +/** + * @brief Generic RX command + * + * Command to receive generic BLE packets + */ +struct RCL_CMD_BLE5_GENERIC_RX_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_CtxGenericRx *ctx; /*!< Pointer to context structure */ + RCL_StatsGenericRx *stats; /*!< Pointer to statistics structure */ +}; + +#define RCL_CmdBle5GenericRx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_GENERIC_RX, \ + RCL_Handler_BLE5_genericRx), \ + .channel = 64, \ + .ctx = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdBle5GenericRx_DefaultRuntime() (RCL_CmdBle5GenericRx) RCL_CmdBle5GenericRx_Default() + +/** + * @brief Generic RX context + * + * Context for generic RX command + */ +struct RCL_CTX_GENERIC_RX_t { + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + uint32_t accessAddress; /*!< Access address */ + uint32_t crcInit; /*!< CRC initialization value (24 bits) */ + uint8_t maxPktLen; /*!< Maximum payload length of received packets */ + struct { + uint8_t repeated: 1; /*!< 0: End after receiving one packet. 1: Go back to sync search after receiving. */ + uint8_t disableSync: 1; /*!< 0: Listen for sync 1: Do not listen for sync */ + uint8_t discardRxPackets: 1; /*!< 0: Store received packets in rxBuffers. 1: Do not store packets, useful for link tests where CRC result is enough */ + uint8_t reserved: 4; /*!< Reserved, set to 0 */ + } config; +}; + +#define RCL_CtxGenericRx_Default() \ +{ \ + .rxBuffers = { 0 }, \ + .accessAddress = 0x71764129U, \ + .crcInit = 0x555555, \ + .config = { \ + .repeated = 1, \ + .disableSync = 0, \ + .discardRxPackets = 1, \ + .reserved = 0, \ + }, \ +} +#define RCL_CtxGenericRx_DefaultRuntime() (RCL_CtxGenericRx) RCL_CtxGenericRx_Default() + +/** + * @brief Statistics structure for generic RX + * + * Statistics for generic RX command + */ +struct RCL_STATS_GENERIC_RX_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t timestampValid; /*!< Returns 1 if %lastTimestamp is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet */ + uint32_t lastTimestamp; /*!< Timestamp of last successfully received packet */ + uint16_t nRxNok; /*!< Number of packets received with CRC error */ + uint16_t nRxOk; /*!< Number of correctly received, accepted packets */ + uint8_t nRxFifoFull; /*!< Number of packets received which could not be stored */ +}; + +#define RCL_StatsGenericRx_Default() \ +{ \ + .config = { 0 }, \ + .timestampValid = 0, \ + .lastRssi = LRF_RSSI_INVALID, \ +} +#define RCL_StatsGenericRx_DefaultRuntime() (RCL_StatsGenericRx) RCL_StatsGenericRx_Default() + +/** + * @brief Generic TX command + * + * Command to transmit a generic BLE packet with no restriction on packet contents + */ +struct RCL_CMD_BLE5_GENERIC_TX_t { + RCL_Command common; + RCL_Ble5Channel channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + RCL_CtxGenericTx *ctx; /*!< Pointer to context structure */ +}; + +#define RCL_CmdBle5GenericTx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_GENERIC_TX, \ + RCL_Handler_BLE5_genericTx), \ + .channel = 64, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .ctx = NULL, \ +} +#define RCL_CmdBle5GenericTx_DefaultRuntime() (RCL_CmdBle5GenericTx) RCL_CmdBle5GenericTx_Default() + +/** + * @brief Generic TX context + * + * Context for generic TX command + */ +struct RCL_CTX_GENERIC_TX_t { + List_List txBuffers; /*!< Linked list of packets to transmit. First packet will be transmitted and consumed. */ + uint32_t accessAddress; /*!< Access address */ + uint32_t crcInit; /*!< CRC initialization value (24 bits) */ +}; + +#define RCL_CtxGenericTx_Default() \ +{ \ + .txBuffers = { 0 }, \ + .accessAddress = 0x71764129U, \ + .crcInit = 0x555555, \ +} +#define RCL_CtxGenericTx_DefaultRuntime() (RCL_CtxGenericTx) RCL_CtxGenericTx_Default() + +/** + * @brief BLE5 transmitter test command + * + * Command to transmit continuously, either a modulated signal or continuous wave + */ +struct RCL_CMD_BLE5_TX_TEST_t { + RCL_Command common; + uint8_t channel; /*!< Channel index */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t txWord; /*!< Repeated word to transmit */ + struct { + uint8_t whitenMode: 2; /*!< 0. No or default whitening. 1: PRBS-9. 2: PRBS-15. 3: PRBS-32 */ + uint8_t sendCw: 1; /*!< 0: Send modulated signal. 1: Send CW */ + uint8_t reserved: 5; /*!< Reserved, set to 0 */ + } config; +}; + +#define RCL_CmdBle5TxTest_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE5_TX_TEST, \ + RCL_Handler_Ble5_txTest), \ + .channel = 64, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .txWord = 0, \ + .config = { \ + .whitenMode = 2, \ + .sendCw = 0, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdBle5TxTest_DefaultRuntime() (RCL_CmdBle5TxTest) RCL_CmdBle5TxTest_Default() + +#define RCL_CMD_BLE5_WH_MODE_DEFAULT 0 /*!< config.whitenMode: Default (or no) whitening */ +#define RCL_CMD_BLE5_WH_MODE_PRBS9 1 /*!< config.whitenMode: PRBS-9 */ +#define RCL_CMD_BLE5_WH_MODE_PRBS15 2 /*!< config.whitenMode: PRBS-15 */ +#define RCL_CMD_BLE5_WH_MODE_PRBS32 3 /*!< config.whitenMode: PRBS-32 */ + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/commands/ble_cs.h b/simplelink_lpf3/source/ti/drivers/rcl/commands/ble_cs.h new file mode 100644 index 00000000..62b8059e --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/commands/ble_cs.h @@ -0,0 +1,687 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_commands_ble_cs_h__include +#define ti_drivers_RCL_commands_ble_cs_h__include + +#include +#include +#include + +#include + +/* Forward declaration of types */ +typedef struct RCL_CMD_BLE_CS_t RCL_CmdBleCs; +typedef struct RCL_CMD_BLE_CS_STEP_INTERNAL_t RCL_CmdBleCs_Step_Internal; +typedef struct RCL_CMD_BLE_CS_STEP_RESULT_INTERNAL_t RCL_CmdBleCs_StepResult_Internal; +typedef struct RCL_CMD_BLE_CS_STEP_t RCL_CmdBleCs_Step; +typedef struct RCL_CMD_BLE_CS_SUBEVENT_RESULTS_t RCL_CmdBleCs_SubeventResults; +typedef struct RCL_CMD_BLE_CS_SUBEVENT_RESULTS_CONTINUE_t RCL_CmdBleCs_SubeventResultsContinue; +typedef struct RCL_CMD_BLE_CS_S2R_t RCL_CmdBleCs_S2r; +typedef struct RCL_CMD_BLE_CS_STATS_t RCL_CmdBleCs_Stats; +typedef struct RCL_CMD_BLE_CS_IQ_SAMPLE_t RCL_CmdBleCs_IQSample; +typedef struct RCL_CMD_BLE_CS_PRECAL_t RCL_CmdBleCs_Precal; +typedef struct RCL_CMD_BLE_CS_PRECAL_TABLE_t RCL_CmdBleCs_PrecalTable; +typedef struct RCL_CMD_BLE_CS_PRECAL_ENTRY_t RCL_CmdBleCs_PrecalEntry; + +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_TONE_t RCL_CmdBleCs_Tone; +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_I0_t RCL_CmdBleCs_ResultI0; +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_R0_t RCL_CmdBleCs_ResultR0; +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_IR1_t RCL_CmdBleCs_ResultIR1; +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_IR2_t RCL_CmdBleCs_ResultIR2; +typedef struct RCL_CMD_BLE_CS_STEP_RESULTS_IR3_t RCL_CmdBleCs_ResultIR3; + +typedef enum RCL_CMD_BLE_CS_Phy_e RCL_CmdBleCs_Phy; +typedef enum RCL_CMD_BLE_CS_Role_e RCL_CmdBleCs_Role; +typedef enum RCL_CMD_BLE_CS_StepMode_e RCL_CmdBleCs_StepMode; +typedef enum RCL_CMD_BLE_CS_PacketResult_e RCL_CmdBleCs_PacketResult; +typedef enum RCL_CMD_BLE_CS_Tfcs_e RCL_CmdBleCs_Tfcs; +typedef enum RCL_CMD_BLE_CS_Tpm_e RCL_CmdBleCs_Tpm; +typedef enum RCL_CMD_BLE_CS_Tip_e RCL_CmdBleCs_Tip; +typedef enum RCL_CMD_BLE_CS_Tsw_e RCL_CmdBleCs_Tsw; +typedef enum RCL_CMD_BLE_CS_AntennaConfig_e RCL_CmdBleCs_AntennaConfig; +typedef enum RCL_CMD_BLE_CS_Payload_e RCL_CmdBleCs_Payload; +typedef enum RCL_CMD_BLE_CS_RxGain_e RCL_CmdBleCs_RxGain; +typedef enum RCL_CMD_BLE_CS_ToneQuality_e RCL_CmdBleCs_ToneQuality; +typedef enum RCL_CMD_BLE_CS_ToneExtensionSlot_e RCL_CmdBleCs_ToneExtensionSlot; + +/* Command IDs for generic commands */ +#define RCL_CMDID_BLE_CS 0x1101U +#define RCL_CMDID_BLE_CS_PRECAL 0x1102U + +/* Helper macros to convert between time units */ +#define RCL_BLE_CS_US_TO_MCE_TIMER(x) ((x)*48) +#define RCL_BLE_CS_US_TO_PBE_TIMER(x) ((x)*4) +#define RCL_BLE_CS_MCE_TIMER_TO_US(x) ((x)/48) +#define RCL_BLE_CS_PBE_TIMER_TO_US(x) ((x)/4) +#define RCL_BLE_CS_MCE_TIMER_TO_PBE_TIMER(x) ((x)/12) + +/* Helper macros for constants */ +#define RCL_BLE_CS_MAX_NUM_ANT 4 +#define RCL_BLE_CS_MAX_NUM_ANT_PATH 5 +#define RCL_BLE_CS_MAX_PAYLOAD_SIZE 4 +#define RCL_BLE_CS_NUM_CORR 3 +#define RCL_BLE_CS_NUM_STIM 2 +#define RCL_BLE_CS_MAX_S2R_LEN 1024 +#define RCL_BLE_CS_NUM_RX_GAIN_LEVEL 2 +#define RCL_BLE_CS_NUM_PRECAL_CHANNELS 4 + +/** + * @brief BLE Channel Sounding IQ Sample + * + * Container to store complex vectors + */ +struct RCL_CMD_BLE_CS_IQ_SAMPLE_t { + int16_t i; /*!< Sample I-branch */ + int16_t q; /*!< Sample Q-branch */ +}; + +/** + * @brief BLE Channel Sounding + * + * Command to execute a BLE Channel Sounding event + */ +struct RCL_CMD_BLE_CS_t { + RCL_Command common; + struct { + uint16_t role:1; /*!< Role of the device @ref RCL_CmdBleCs_Role */ + uint16_t phy:1; /*!< Phy used for packet exchange @ref RCL_CmdBleCs_Phy */ + uint16_t repeatSteps:1; /*!< Enable continuous repetition of step list */ + uint16_t chFilterEnable:1; /*!< Enable filtering of restricted channels at (2402, 2403, 2425, 2426, 2427, 2479, 2480 MHz) */ + uint16_t reserved:4; + uint16_t nSteps:8; /*!< Total number of steps within the BLE CS Sub-Event */ + } mode; + + struct { + uint8_t select; /*!< Antenna pattern selection by index @ref RCL_CmdBleCs_AntennaConfig */ + uint8_t gpoMask; /*!< Mask of GPOs on the LRF controlling the antennas */ + uint8_t gpoVal[RCL_BLE_CS_MAX_NUM_ANT]; /*!< GPOCTRL word for antenna path 0..3 */ + } antennaConfig; + + struct { + uint16_t tFcs; /*!< Config of time of Frequency Change period @ref RCL_CmdBleCs_Tfcs */ + uint16_t tFm; /*!< Config of time of Frequency Measurement period */ + uint16_t tPm; /*!< Config of time of Phase Measurement Duration @ref RCL_CmdBleCs_Tpm */ + uint16_t tIp1; /*!< Config of time of Interlude Period 1 @ref RCL_CmdBleCs_Tip */ + uint16_t tIp2; /*!< Config of time of Interlude Period 2 @ref RCL_CmdBleCs_Tip */ + uint16_t tRxWideningR0; /*!< Config of additional time of RX timeout of mode-0 steps on reflector. */ + uint16_t tSw; /*!< Config of time of Antenna Switching duration @ref RCL_CmdBleCs_Tsw */ + uint16_t tSwAdjustA; /*!< Time adjustment of first set of antenna switching within a step (Pkt-Tn / ...) */ + uint16_t tSwAdjustB; /*!< Time adjustment of second set of antenna switching within a step (... / Tn-Pkt) */ + } timing; + + struct { + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint8_t rxGain; /*!< 0: Automatic Gain Control enabled, 1...15: Index value of manual RX gain @ref RCL_CmdBleCs_RxGain */ + int16_t foffOverride; /*!< Frequency offset compensation override value in [4xFOFF = 4x (FRF/2^21)] units. */ + uint16_t foffOverrideEnable:1; /*!< Disables automatic frequency offset estimation and enforces the use of the provided override value */ + uint16_t reserved:15; + } frontend; + + RCL_CmdBleCs_PrecalTable *precalTable; /*!< Pointer to a table contains DC values from precalibration */ + RCL_CmdBleCs_StepResult_Internal *results; /*!< Pointer to result list */ + RCL_CmdBleCs_Stats *stats; /*!< Pointer to statistics structure */ + List_List stepBuffers; /*!< Linked list of steps to be executed */ + List_List stepBuffersDone; /*!< Linked list of steps have been executed */ + List_List resultBuffers; /*!< Linked list of empty result buffers */ + List_List resultBuffersDone; /*!< Linked list of result buffers containing data */ + List_List s2rBuffers; /*!< Linked list of empty s2r containers */ + List_List s2rBuffersDone; /*!< Linked list of s2r containers with data */ +}; + +/* Default configuration of command */ +#define RCL_CmdBleCs_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE_CS, \ + RCL_Handler_BLE_CS), \ +} +#define RCL_CmdBleCs_DefaultRuntime() (RCL_CmdBleCs) RCL_CmdBleCs_Default() + +/** + * @brief BLE Channel Sounding Step + * + * Descriptor to configure a single step within the BLE Channel Sounding Event + */ +struct RCL_CMD_BLE_CS_STEP_INTERNAL_t { + uint16_t channelIdx; /*!< Integer index of channel information (0: 2402MHz) */ + uint16_t mode; /*!< Step mode @ref RCL_CmdBleCs_StepMode */ + uint16_t toneExtension; /*!< Configuration of tone extension */ + uint16_t payloadLen; /*!< Length of payload in units of 32bit words @ref RCL_CmdBleCs_Payload */ + uint16_t foffErr; /*!< Internal! Used for frequency offset compensation */ + uint16_t tAdjustA; /*!< Internal! Used for timegrid adjustment */ + uint16_t tAdjustB; /*!< Internal! Used for timegrid adjustment */ + uint16_t reserved0; + RCL_CmdBleCs_IQSample dcComp[RCL_BLE_CS_NUM_RX_GAIN_LEVEL]; /*!< Internal! Used for DC compensation with precalibrated values */ + uint32_t payloadTx[RCL_BLE_CS_MAX_PAYLOAD_SIZE]; /*!< Payload to transmit containing random bit sequence (TX) */ + uint32_t payloadRx[RCL_BLE_CS_MAX_PAYLOAD_SIZE]; /*!< Expected payload to receive containing random bit sequence (RX) */ + uint32_t aaTx; /*!< Access Address to be transmitted */ + uint32_t aaRx; /*!< Access Address to be received */ + uint16_t antennaPermIdx; /*!< Index of entry to be used from the antenna permutation table @ref RCL_CmdBleCs_AntennaConfig */ + uint16_t antennaSequence; /*!< Internal! Decoded antenna control sequence based on permutation table */ + uint16_t tStep; /*!< Internal! The total duration of step dynamically calculated */ + uint16_t tAntennaA; /*!< Internal! Antenna timing adjustment */ + uint16_t tAntennaB; /*!< Internal! Antenna timing adjustment */ + uint16_t reserved1; +}; + +/** + * @brief BLE Channel Sounding QQ data + * + * Container to store RSSI data for postprocess of the quality of tone + */ +typedef struct { + int16_t magnMin; /*!< Minimum of signal magnitude during TPM */ + int16_t magnMax; /*!< Maximum of signal magnitude during TPM */ + int16_t magnAvg; /*!< Average of signal magnitude during TPM */ + int16_t magnAvgdB; /*!< Average of signal magnitude during TPM in dB */ +} MagnData; + +/** + * @brief BLE Channel Sounding Step Result + * + * Container to store the results of a single step within the BLE Channel Sounding Event + */ +struct RCL_CMD_BLE_CS_STEP_RESULT_INTERNAL_t { + uint16_t channelIdx; /*!< Integer index of channel information (0: 2402MHz) */ + uint16_t mode; /*!< Step mode @ref RCL_CmdBleCs_StepMode */ + uint16_t toneExtension; /*!< Configuration of tone extension */ + uint16_t payloadLen; /*!< Length of payload in units of 32bit words @ref RCL_CmdBleCs_Payload */ + uint16_t reserved; + int16_t foffMeasured; /*!< Frequency offset between devices (only set on Initiator Mode 0) */ + uint16_t pktResult; /*!< Result of packet reception @ref RCL_CmdBleCs_PacketResult */ + uint8_t gain; /*!< LNA gain used (Low/High)*/ + int8_t pktRssi; /*!< Receiver Signal Strength Indicator [dBm] captured during packet reception */ + uint16_t rtt; /*!< RTT timestamp */ + uint16_t corr[RCL_BLE_CS_NUM_CORR]; /*!< Correlator before-peak-after values for fractional time estimation */ + RCL_CmdBleCs_IQSample dc; /*!< DC offset measured on packet */ + RCL_CmdBleCs_IQSample pct[RCL_BLE_CS_MAX_NUM_ANT_PATH]; /*!< Phase Correction Terms per antenna path (incl. extension) */ + uint32_t payload[RCL_BLE_CS_MAX_PAYLOAD_SIZE]; /*!< Payload containing random bit sequence (RX) */ + MagnData magn[RCL_BLE_CS_MAX_NUM_ANT_PATH]; /*!< Received magnitude data of tone per antenna path for quality estimation (incl. extension) */ + + /* Echoed by PBE */ + uint16_t antennaPermIdx; /*!< Index of entry to be used from the antenna permutation table @ref RCL_CmdBleCs_AntennaConfig */ + uint16_t antennaPkt; /*!< Antenna used for packet exchange. No selection supported. */ +}; + +/** + * @brief BLE Channel Sounding S2R Sample type definition + * + * One S2R sample can be interpreted multiple ways, depending of the signal source + */ +typedef union { + uint32_t word; /*!< Sample format for copying data */ + uint8_t byte[4]; /*!< Sample format of the Decoding Stage */ + RCL_CmdBleCs_IQSample iq; /*!< Sample format of the Front End Stage */ +} S2RSample; + +/** + * @brief BLE Channel Sounding S2R IQ Data + * + * Container to store raw S2R samples of a BLE Channel Sounding Step + */ +struct RCL_CMD_BLE_CS_S2R_t { + uint8_t idx; /*!< The index of entry in the step list which the data belongs to */ + uint8_t phy; /*!< Phy the samples captured on */ + uint8_t channel; /*!< Frequency channel */ + uint8_t payloadLen; /*!< Payload length in bits */ + uint32_t payload0; /*!< Payload bits [00:31] */ + uint32_t payload1; /*!< Payload bits [32:63] */ + uint32_t payload2; /*!< Payload bits [64:95] */ + uint32_t payload3; /*!< Payload bits [96:127] */ + uint16_t iqLength; /*!< Number of valid iq samples in data[] */ + uint16_t reserved; + S2RSample data[]; /*!< Raw samples captured */ +}; + +/** + * @brief BLE Channel Sounding Statistics + * + * Container to store the statistical outputs of the BLE Channel Sounding Event + */ +struct RCL_CMD_BLE_CS_STATS_t { + uint16_t nStepsWritten; /*!< Number of steps sent to the PBE through the FIFO */ + uint16_t nResultsRead; /*!< Number of results read from the PBE through the FIFO */ + uint16_t nStepsDone; /*!< Number of steps have been executed by the PBE */ + uint16_t nRxOk; /*!< Number of steps where pktResult == OK, filled by the CM0 */ + uint16_t nRxNok; /*!< Number of steps where pktResult != OK, filled by the CM0 */ + uint8_t nS2RDone; /*!< Number of Samples-To-Ram containers filled by the CM0 */ + int8_t lastRssi; /*!< Last valid RSSI received by the PBE */ + int16_t lastFoff; /*!< Last valid frequency offset received by the PBE */ + int16_t foffComp; /*!< Frequency offset compensation value */ + uint8_t numAntennaPath; /*!< Number of true antenna paths (1...4) */ + uint8_t reserved0; + uint16_t reserved1; +}; + +/** + * @brief Enumerator of phy types + * + * Describes the phy packets shall be transmitted + */ +enum RCL_CMD_BLE_CS_Phy_e { + RCL_CmdBleCs_Phy_1M, + RCL_CmdBleCs_Phy_2M, + RCL_CmdBleCs_Phy_Length +}; + +/** + * @brief Enumerator of role types + * + * Describes the role of the device during a BLE channel sounding event + */ +enum RCL_CMD_BLE_CS_Role_e { + RCL_CmdBleCs_Role_Initiator, + RCL_CmdBleCs_Role_Reflector, + RCL_CmdBleCs_Role_Length +}; + +/** + * @brief Enumerator of step types + * + * Describes the available modes of a BLE CS step + */ +enum RCL_CMD_BLE_CS_StepMode_e { + RCL_CmdBleCs_StepMode_0, /*!< (M) Pkt-Pkt-Tn */ + RCL_CmdBleCs_StepMode_1, /*!< (M) Pkt-Pkt */ + RCL_CmdBleCs_StepMode_2, /*!< (M) Tn-Tn */ + RCL_CmdBleCs_StepMode_3, /*!< (O) Pkt-Tn-Tn-Pkt */ + RCL_CmdBleCs_StepMode_Length +}; + +/** + * @brief Enumerator of packet status options + * + * Describes the available packet status words + */ +enum RCL_CMD_BLE_CS_PacketResult_e { + RCL_CmdBleCs_PacketResult_Error = -1, /*!< NA for mode-2 steps, otherwise command execution error. */ + RCL_CmdBleCs_PacketResult_Ok = 0, /*!< The packet reception was succesfull */ + RCL_CmdBleCs_PacketResult_BitError = 1, /*!< The packet was received with one or more bit errors */ + RCL_CmdBleCs_PacketResult_Lost = 2, /*!< The packet reception was terminated by timeout */ + RCL_CmdBleCs_PacketResult_Length +}; + +/** + * @brief Enumerator of tFcs duration options + * + * Describes the available durations for frequency change + */ +enum RCL_CMD_BLE_CS_Tfcs_e { + RCL_CmdBleCs_Tfcs_80us, /*!< (C.1) */ + RCL_CmdBleCs_Tfcs_100us, + RCL_CmdBleCs_Tfcs_120us, + RCL_CmdBleCs_Tfcs_150us, /*!< (M) */ + RCL_CmdBleCs_Tfcs_Length, +}; + +/** + * @brief Enumerator of tPm duration options + * + * Describes the available durations for phase measurement + */ +enum RCL_CMD_BLE_CS_Tpm_e { + RCL_CmdBleCs_Tpm_10us, + RCL_CmdBleCs_Tpm_20us, + RCL_CmdBleCs_Tpm_40us, /*!< (M) */ + RCL_CmdBleCs_Tpm_Length, +}; + +/** + * @brief Enumerator of tIp duration + * + * Describes the available durations for interlude period + */ +enum RCL_CMD_BLE_CS_Tip_e { + RCL_CmdBleCs_Tip_40us, /*!< (C.1) */ + RCL_CmdBleCs_Tip_50us, + RCL_CmdBleCs_Tip_60us, + RCL_CmdBleCs_Tip_80us, /*!< (C.1) */ + RCL_CmdBleCs_Tip_145us, /*!< (M) */ + RCL_CmdBleCs_Tip_Length, +}; + +/** + * @brief Enumerator of antenna switch duration + * + * Describes the available durations for antenna switching transient + */ +enum RCL_CMD_BLE_CS_Tsw_e { + RCL_CmdBleCs_Tsw_0us, /*!< (M) for 1x1 */ + RCL_CmdBleCs_Tsw_1us, + RCL_CmdBleCs_Tsw_2us, + RCL_CmdBleCs_Tsw_4us, + RCL_CmdBleCs_Tsw_10us, /*!< (M) */ + RCL_CmdBleCs_Tsw_Length +}; + +/** + * @brief Enumerator of antenna configuration + * + * Describes the available values for configuration of + * antenna control for PCT measurement. + */ +enum RCL_CMD_BLE_CS_AntennaConfig_e { + RCL_CmdBleCs_AntennaConfig_1x1, /*!< (M) */ + RCL_CmdBleCs_AntennaConfig_2x1, + RCL_CmdBleCs_AntennaConfig_3x1, + RCL_CmdBleCs_AntennaConfig_4x1, + RCL_CmdBleCs_AntennaConfig_1x2, + RCL_CmdBleCs_AntennaConfig_1x3, + RCL_CmdBleCs_AntennaConfig_1x4, + RCL_CmdBleCs_AntennaConfig_2x2, + RCL_CmdBleCs_AntennaConfig_Length, +}; + +/** + * @brief Enumerator of payload length + * + * Describes the available payload lengths + */ +enum RCL_CMD_BLE_CS_Payload_e { + RCL_CmdBleCs_Payload_None, + RCL_CmdBleCs_Payload_32bit, + RCL_CmdBleCs_Payload_64bit, + RCL_CmdBleCs_Payload_96bit, + RCL_CmdBleCs_Payload_128bit, + RCL_CmdBleCs_Payload_Length +}; + +/** + * @brief Enumerator of RX gain + * + * Describes the available RX gain settings + */ +enum RCL_CMD_BLE_CS_RxGain_e { + RCL_CmdBleCs_RxGain_Auto = 0, + RCL_CmdBleCs_RxGain_MaxMinus21dB = 8, + RCL_CmdBleCs_RxGain_MaxMinus18dB = 9, + RCL_CmdBleCs_RxGain_MaxMinus15dB = 10, + RCL_CmdBleCs_RxGain_MaxMinus12dB = 11, + RCL_CmdBleCs_RxGain_MaxMinus9dB = 12, + RCL_CmdBleCs_RxGain_MaxMinus6dB = 13, + RCL_CmdBleCs_RxGain_MaxMinus3dB = 14, + RCL_CmdBleCs_RxGain_Max = 15, +}; + +/** + * @brief Enumerator of tone quality + * + * Describes the classification of tone quality + */ +enum RCL_CMD_BLE_CS_ToneQuality_e { + RCL_CmdBleCs_ToneQuality_Good, + RCL_CmdBleCs_ToneQuality_Medium, + RCL_CmdBleCs_ToneQuality_Low, + RCL_CmdBleCs_ToneQuality_Unavailable, + RCL_CmdBleCs_ToneQuality_Length +}; + +/** + * @brief Enumerator of tone extension slot + * + * Describes the classification of tone extension slot + */ +enum RCL_CMD_BLE_CS_ToneExtensionSlot_e { + RCL_CmdBleCs_ToneExtensionSlot_Disabled, + RCL_CmdBleCs_ToneExtensionSlot_Enabled_NoToneExpected, + RCL_CmdBleCs_ToneExtensionSlot_Enabled_ToneExpected, + RCL_CmdBleCs_ToneExtensionSlot_Length +}; + +/***************************************************** + DC precalibration +*****************************************************/ + +/** + * @brief Callback function for DC precalibration feature + * + * Describes the method that can select the right compensation value from the available precalibration table. + */ +typedef void (*RCL_CmdBleCs_PrecalCallback)(RCL_CmdBleCs_PrecalTable *table, uint8_t channel, uint32_t *hdc, uint32_t *ldc); + +/** + * @brief DC precalibration entry + * + * Data structure to store a single DC precalibration entry. + */ +struct RCL_CMD_BLE_CS_PRECAL_ENTRY_t { + uint8_t channel; + uint8_t valid; + RCL_CmdBleCs_IQSample hdc; + RCL_CmdBleCs_IQSample ldc; +}; + +/** + * @brief DC precalibration table + * + * Data structure to store and use the DC precalibration table. + */ +struct RCL_CMD_BLE_CS_PRECAL_TABLE_t { + RCL_CmdBleCs_PrecalCallback callback; + uint32_t timestamp; + uint16_t rxGain; + int8_t temperature; + uint8_t numEntries : 7; + uint8_t valid : 1; + RCL_CmdBleCs_PrecalEntry entries[]; +}; + +/* Default callback implemented in the driver */ +void RCL_Handler_BLE_CS_PrecalDefaultCallback(RCL_CmdBleCs_PrecalTable *table, uint8_t channel, uint32_t *hdc, uint32_t *ldc); + +/* Default configuration of DC precalibration */ +#define RCL_CmdBleCs_PrecalTable_Default() \ +{ \ + .callback = RCL_Handler_BLE_CS_PrecalDefaultCallback, \ + .timestamp = 0, \ + .rxGain = 0x00F7, \ + .temperature = 0, \ + .numEntries = 4, \ + .valid = 0, \ + .entries = {{.channel = 10}, \ + {.channel = 30}, \ + {.channel = 50}, \ + {.channel = 70}}, \ +} + +/** + * @brief DC precalibration command + * + * Command to run precalibration for a list of channels. + */ +struct RCL_CMD_BLE_CS_PRECAL_t { + RCL_Command common; + RCL_CmdBleCs_PrecalTable *table; +}; + +/* Default configuration of DC precalibration command */ +#define RCL_CmdBleCs_Precal_Default(pTable) \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_BLE_CS_PRECAL, \ + RCL_Handler_BLE_CS_Precal), \ + .table = pTable \ +} +#define RCL_CmdBleCs_Precal_DefaultRuntime(pTable) (RCL_CmdBleCs_Precal) RCL_CmdBleCs_Precal_Default(pTable) + +/***************************************************** + HCI interface +*****************************************************/ +/** + * @brief Container format for a single step in the subevent + * + * Compressed format used within a multibuffer + */ +struct RCL_CMD_BLE_CS_STEP_t { + uint32_t channelIdx : 7; /*!< Integer index of channel information (0: 2402MHz) */ + uint32_t mode : 2; /*!< Step mode @ref RCL_CmdBleCs_StepMode */ + uint32_t antennaPermIdx : 5; /*!< Index of entry to be used from the antenna permutation table @ref RCL_CmdBleCs_AntennaConfig */ + uint32_t toneExtension : 2; /*!< Enable tone extension, [0]=first tone (transmitted by initiator), [1]=second tone (transmitted by reflector) */ + uint32_t payloadLen : 3; /*!< Length of payload in units of 32bit words @ref RCL_CmdBleCs_Payload */ + uint32_t reserved : 13; + uint32_t aaTx; /*!< Access Address to be transmitted */ + uint32_t aaRx; /*!< Access Address to be received */ + uint32_t payloadTx[RCL_BLE_CS_MAX_PAYLOAD_SIZE]; /*!< Payload to transmit containing random bit sequence (TX) */ + uint32_t payloadRx[RCL_BLE_CS_MAX_PAYLOAD_SIZE]; /*!< Expected payload to receive containing random bit sequence (RX) */ +}; + +/** + * @brief Container format for a batch of step results in the subevent (first segment) + * + * The data[] field contains the results in mode specific format (size varies with step-mode) + */ +struct RCL_CMD_BLE_CS_SUBEVENT_RESULTS_t { + uint8_t subeventCode; + uint16_t connectionHandle; + uint8_t configID; + uint16_t startAclConnectionEvent; + uint16_t procedureCounter; + int16_t frequencyCompensation; + uint8_t referencePowerLevel; + uint8_t procedureDoneStatus; + uint8_t subeventDoneStatus; + uint8_t abortReason; + uint8_t numAntennaPath; + uint8_t numStepsReported; + uint8_t data[]; +} __attribute__ ((packed)); + +/** + * @brief Container format for a batch of step results in the subevent (second+ segment) + * + * The data[] field contains the results in mode specific format (size varies with step-mode) + */ +struct RCL_CMD_BLE_CS_SUBEVENT_RESULTS_CONTINUE_t { + uint8_t subeventCode; + uint16_t connectionHandle; + uint8_t configID; + uint8_t procedureDoneStatus; + uint8_t subeventDoneStatus; + uint8_t abortReason; + uint8_t numAntennaPath; + uint8_t numStepsReported; + uint8_t data[]; +} __attribute__ ((packed)); + +/** + * @brief Container format for tones + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_TONE_t { + uint32_t i : 12; + uint32_t q : 12; + uint32_t quality : 8; +}; + +/** + * @brief Container format for mode-0 step results + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_I0_t { + /* Common */ + uint8_t mode; + uint8_t channel; + uint8_t dataLength; + /* Packet */ + uint8_t packetAAQuality; + int8_t packetRssi; + uint8_t packetAntenna; + /* Frequency */ + int16_t measuredFreqOffset; +}; + +/** + * @brief Container format for mode-0 step results + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_R0_t { + /* Common */ + uint8_t mode; + uint8_t channel; + uint8_t dataLength; + /* Packet */ + uint8_t packetAAQuality; + int8_t packetRssi; + uint8_t packetAntenna; +}; + +/** + * @brief Container format for mode-1 step results + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_IR1_t { + /* Common */ + uint8_t mode; + uint8_t channel; + uint8_t dataLength; + /* Packet */ + uint8_t packetAAQuality; + uint8_t nadm; + int8_t packetRssi; + uint8_t packetAntenna; + int16_t packetToF; +}; + +/** + * @brief Container format for mode-2 step results + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_IR2_t { + /* Common */ + uint8_t mode; + uint8_t channel; + uint8_t dataLength; + /* Tones */ + uint8_t antennaPermutationIndex; + RCL_CmdBleCs_Tone tones[]; +}; + +/** + * @brief Container format for mode-3 step results + * + */ +struct RCL_CMD_BLE_CS_STEP_RESULTS_IR3_t { + /* Common */ + uint8_t mode; + uint8_t channel; + uint8_t dataLength; + /* Packet */ + uint8_t packetAAQuality; + uint8_t nadm; + int8_t packetRssi; + uint8_t packetAntenna; + int16_t packetToF; + /* Tones */ + uint8_t antennaPermutationIndex; + RCL_CmdBleCs_Tone tones[]; +}; + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/commands/generic.h b/simplelink_lpf3/source/ti/drivers/rcl/commands/generic.h new file mode 100644 index 00000000..36ad55d4 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/commands/generic.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_commands_generic_h__include +#define ti_drivers_RCL_commands_generic_h__include + +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/pbe_generic_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_generic_regdef_regs.h) + +typedef struct RCL_CMD_GENERIC_FS_t RCL_CmdGenericFs; +typedef struct RCL_CMD_GENERIC_FS_OFF_t RCL_CmdGenericFsOff; +typedef struct RCL_CMD_GENERIC_TX_t RCL_CmdGenericTx; +typedef struct RCL_CMD_GENERIC_TX_REPEAT_t RCL_CmdGenericTxRepeat; +typedef struct RCL_CMD_GENERIC_TX_TEST_t RCL_CmdGenericTxTest; +typedef struct RCL_CMD_GENERIC_RX_t RCL_CmdGenericRx; +typedef struct RCL_CMD_GENERIC_PBE_OPERATION_t RCL_CmdGenericPbeOperation; +typedef struct RCL_STATS_GENERIC_t RCL_StatsGeneric; +typedef struct RCL_CMD_NESB_PTX_t RCL_CmdNesbPtx; +typedef struct RCL_CMD_NESB_PRX_t RCL_CmdNesbPrx; +typedef struct RCL_STATS_NESB_t RCL_StatsNesb; +typedef struct RCL_CONFIG_ADDRESS_t RCL_ConfigAddress; + +/* Command IDs for generic commands */ +#define RCL_CMDID_GENERIC_FS 0x0001U +#define RCL_CMDID_GENERIC_FS_OFF 0x0002U +#define RCL_CMDID_GENERIC_TX 0x0003U +#define RCL_CMDID_GENERIC_TX_REPEAT 0x0004U +#define RCL_CMDID_GENERIC_TX_TEST 0x0005U +#define RCL_CMDID_GENERIC_RX 0x0006U +#define RCL_CMDID_GENERIC_PBE_OPERATION 0x0007U +#define RCL_CMDID_NESB_PTX 0x0008U +#define RCL_CMDID_NESB_PRX 0x0009U + + +/** + * @brief RF frequency programming type object + * + * Type to specify how frequency programming is done for FS command + */ +typedef enum RCL_FsType_e { + RCL_FsType_Rx, /*!< Program synth as for RX operation */ + RCL_FsType_Tx, /*!< Program synth as for TX operation */ +} RCL_FsType; + +/** + * @brief Frequency programming command + * + * Command to program a synth frequency without directly starting RX or TX + */ +struct RCL_CMD_GENERIC_FS_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program */ + RCL_FsType fsType; /*!< Rules for synth setup */ +}; + +#define RCL_CmdGenericFs_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_FS, \ + RCL_Handler_Generic_Fs), \ + .rfFrequency = 2440000000U, \ + .fsType = RCL_FsType_Rx, \ +} +#define RCL_CmdGenericFs_DefaultRuntime() (RCL_CmdGenericFs) RCL_CmdGenericFs_Default() + +/** + * @brief Stop frequency synthesizer command + * + * Command to stop the frequency synthesizer if it is running after a command + */ +struct RCL_CMD_GENERIC_FS_OFF_t { + RCL_Command common; +}; + +#define RCL_CmdGenericFsOff_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_FS_OFF, \ + RCL_Handler_Generic_FsOff), \ +} +#define RCL_CmdGenericFsOff_DefaultRuntime() (RCL_CmdGenericFsOff) RCL_CmdGenericFsOff_Default() + + +/** + * @brief Generic transmit command + * + * Command to transmit a packet + */ +struct RCL_CMD_GENERIC_TX_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency */ + List_List txBuffers; /*!< Linked list of packets to transmit. RCL will pop the first packet when transmitted. */ + uint32_t syncWord; /*!< Sync word to transmit */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + struct { + uint8_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint8_t reserved: 7; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdGenericTx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_TX, \ + RCL_Handler_Generic_Tx), \ + .rfFrequency = 2440000000U, \ + .txBuffers = { 0 }, \ + .syncWord = 0x930B51DE, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .config = { \ + .fsOff = 1, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdGenericTx_DefaultRuntime() (RCL_CmdGenericTx) RCL_CmdGenericTx_Default() + +/** + * @brief Generic repeated packet transmit command + * + * Command to transmit a packet repeatedly + */ +struct RCL_CMD_GENERIC_TX_REPEAT_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency */ + RCL_Buffer_DataEntry *txEntry; /*!< Packet to transmit */ + uint32_t syncWord; /*!< Sync word to transmit */ + uint32_t timePeriod; /*!< Time period (0.25 us units) of repeated transmissions. 0: Back-to-back */ + uint16_t numPackets; /*!< Number of times to send the packet: 0: Unlimited */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + struct { + uint8_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint8_t fsRecal: 1; /*!< 0: Keep synth running between each packet. 1. Turn off synth after each packet and recalibrate for the next. Requires %rfFrequency != 0 */ + uint8_t reserved: 6; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdGenericTxRepeat_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_TX_REPEAT, \ + RCL_Handler_Generic_TxRepeat),\ + .rfFrequency = 2440000000U, \ + .txEntry = NULL, \ + .syncWord = 0x930B51DE, \ + .timePeriod = 0, \ + .numPackets = 0, \ + .config = { \ + .fsOff = 1, \ + .fsRecal = 0, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdGenericTxRepeat_DefaultRuntime() (RCL_CmdGenericTxRepeat) RCL_CmdGenericTxRepeat_Default() + +/** + * @brief Generic transmitter test command + * + * Command to transmit continuously, either a modulated signal or continuous wave + */ +struct RCL_CMD_GENERIC_TX_TEST_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + struct { + uint32_t txWord: 16; /*!< Repeated word to transmit */ + uint32_t whitenMode: 2;/*!< 0. No whitening. 1: Default whitening. 2: PRBS-15. 3: PRBS-32 */ + uint32_t sendCw: 1; /*!< 0: Send modulated signal. 1: Send CW */ + uint32_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint32_t reserved: 12; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdGenericTxTest_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_TX_TEST, \ + RCL_Handler_Generic_TxTest), \ + .rfFrequency = 2440000000U, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .config = { \ + .txWord = 0, \ + .whitenMode = 2, \ + .sendCw = 0, \ + .fsOff = 1, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdGenericTxTest_DefaultRuntime() (RCL_CmdGenericTxTest) RCL_CmdGenericTxTest_Default() + +#define RCL_CMD_GENERIC_WH_MODE_NONE 0 /*!< config.whitenMode: No whitening */ +#define RCL_CMD_GENERIC_WH_MODE_DEFAULT 1 /*!< config.whitenMode: Default whitening */ +#define RCL_CMD_GENERIC_WH_MODE_PRBS15 2 /*!< config.whitenMode: PRBS-15 */ +#define RCL_CMD_GENERIC_WH_MODE_PRBS32 3 /*!< config.whitenMode: PRBS-32 */ + +/** + * @brief Generic receive command + * + * Command to receive a packet + */ +struct RCL_CMD_GENERIC_RX_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency */ + List_List rxBuffers; /*!< Linked list of buffers where packets are stored */ + RCL_StatsGeneric *stats; /*!< Pointer to statistics structure. NULL: Do not store statistics */ + uint32_t syncWordA; /*!< Sync word to listen for */ + uint32_t syncWordB; /*!< Alternate Sync word to listen for */ + uint16_t maxPktLen; /*!< Maximum packet length, or packet length for fixed length */ + struct { + uint8_t repeated: 1; /*!< 0: End after receiving one packet. 1: Go back to sync search after receiving. */ + uint8_t disableSyncA: 1; /*!< 0: Listen for syncWordA. 1: Do not listen for syncWordA */ + uint8_t disableSyncB: 1; /*!< 0: Listen for syncWordB. 1: Do not listen for syncWordB */ + uint8_t discardRxPackets: 1; /*!< 0: Store received packets in rxBuffers. 1: Do not store packets, useful for link tests where checksum result is enough */ + uint8_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint8_t reserved: 3; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdGenericRx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_RX, \ + RCL_Handler_Generic_Rx), \ + .rfFrequency = 2440000000U, \ + .rxBuffers = {0}, \ + .stats = NULL, \ + .syncWordA = 0x930B51DE, \ + .syncWordB = 0x12345678, \ + .maxPktLen = 255, \ + .config = { \ + .repeated = 1, \ + .disableSyncA = 0, \ + .disableSyncB = 1, \ + .discardRxPackets = 0, \ + .fsOff = 1, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdGenericRx_DefaultRuntime() (RCL_CmdGenericRx) RCL_CmdGenericRx_Default() + +struct RCL_STATS_GENERIC_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t timestampValid; /*!< Returns 1 if %lastTimestamp is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet. */ + uint32_t lastTimestamp; /*!< Timestamp of last successfully received packet */ + uint32_t nRxNok; /*!< Number of packets received with CRC error */ + uint32_t nRxOk; /*!< Number of correctly received packets */ +}; + +#define RCL_StatsGeneric_Default() \ +{ \ + .config = { 0 }, \ + .timestampValid = 0, \ + .lastRssi = LRF_RSSI_INVALID, \ +} +#define RCL_StatsGeneric_DefaultRuntime() (RCL_StatsGeneric) RCL_StatsGeneric_Default() + +/** + * @brief Send PBE operation + * + * Send an opcode to the PBE and wait for it to report done + */ +struct RCL_CMD_GENERIC_PBE_OPERATION_t { + RCL_Command common; + uint16_t pbeOperation; /*!< Operation code to send to the PBE */ +}; + +#define RCL_CmdGenericPbeOperation_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_GENERIC_PBE_OPERATION, \ + RCL_Handler_Generic_PbeOperation),\ + .pbeOperation = PBE_GENERIC_REGDEF_API_OP_PING, \ +} +#define RCL_CmdGenericPbeOperation_DefaultRuntime() (RCL_CmdGenericPbeOperation) RCL_CmdGenericPbeOperation_Default() + +/** + * @brief NESB transmit command + * + * Command to transmit a packet + */ +struct RCL_CMD_NESB_PTX_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency. */ + List_List txBuffers; /*!< Linked list of packets to transmit. RCL will pop the first packet when transmitted. */ + List_List rxBuffers; /*!< Linked list of buffers for storing received packets. In this case, the ACK. */ + RCL_StatsNesb *stats; /*!< Pointer to statistics structure. NULL: Do not store statistics */ + uint32_t syncWord; /*!< Sync word to transmit */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint8_t seqNo; /*!< Sequence number to use for next packet */ + uint8_t maxRetrans; /*!< Maximum number of retransmissions */ + uint32_t retransDelay; /*!< Number of Systim ticks (250 [ns] resolution) from start of transmission of a packet to retransmission. + If an unattainable retransmission delay is set, the retransmission will start as soon as possible. */ + struct { + uint8_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint8_t autoRetransmitMode: 2; /*!< 0: Do not listen for ACK. + 1: Listen for ACK if transmitted NO_ACK = 0 and retransmit if missing. + 2: Listen for ACK if transmitted NO_ACK = 1 and retransmit if missing. + 3: Always listen for ACK and retransmit if missing. */ + uint8_t hdrConf: 1; /*!< 0: Insert NO_ACK field from TX buffer. + 1: Insert SEQ and NO_ACK field from TX buffer. */ + uint8_t reserved: 4; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdNesbPtx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_NESB_PTX, \ + RCL_Handler_Nesb_Ptx), \ + .rfFrequency = 2440000000U, \ + .txBuffers = { 0 }, \ + .rxBuffers = { 0 }, \ + .stats = NULL, \ + .syncWord = 0x930B51DE, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .seqNo = 0, \ + .maxRetrans = 5, \ + .retransDelay = 100000, \ + .config = { \ + .fsOff = 1, \ + .autoRetransmitMode = 3, \ + .hdrConf = 1, \ + .reserved = 0, \ + } \ +} +#define RCL_CmdNesbPtx_DefaultRuntime() (RCL_CmdNesbPtx) RCL_CmdNesbPtx_Default() + +struct RCL_CONFIG_ADDRESS_t { + uint32_t address; /*!< Address after header */ + uint16_t crcVal; /*!< CRC value (last two bytes if more than 2 CRC bytes) of last successfully received + packet. */ + uint8_t maxPktLen; /*!< Packet length for fixed length, maximum packet length for variable + length */ + uint8_t autoAckMode: 2; /*!< 0: Disable auto-acknowledgement. + 1: Enable auto-acknowledgement if received NO_ACK = 0. + 2: Enable auto-acknowledgement if received NO_ACK = 1. + 3: Enable auto-acknowledgement regardless of received NO_ACK. */ + uint8_t varLen: 1; /*!< 0: Use fixed length given by maxPktLenA in receiver when receiving packets + 1: Use variable length in receiver when receiving packets */ + uint8_t seqValid: 1; /*!< 0: The status is not valid. Any packet is viewed as new. + 1: The status is valid. Only packets with sequence number and CRC different from + the previous one are accepted. */ + uint8_t seq: 2; /*!< Sequence number of last successfully received packet */ + uint8_t reserved: 2; /*!< Reserved, set to 0 */ +}; + +#define RCL_ConfigAddress_Default(_addr) \ +{ \ + .address = _addr, \ + .crcVal = 0, \ + .maxPktLen = 255, \ + .autoAckMode = 3, \ + .varLen = 1, \ + .seqValid = 0, \ + .seq = 1, \ + .reserved = 0, \ +} +#define RCL_ConfigAddress_DefaultRuntime(_addr) (RCL_ConfigAddress) RCL_ConfigAddress_Default(_addr) + + +/** + * @brief NESB receive command + * + * Command to receive a packet + */ +struct RCL_CMD_NESB_PRX_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program. 0: Do not program frequency */ + List_List rxBuffers; /*!< Linked list of buffers where packets are stored */ + RCL_StatsNesb *stats; /*!< Pointer to statistics structure. NULL: Do not store statistics */ + uint32_t syncWordA; /*!< Sync word to listen for */ + uint32_t syncWordB; /*!< Alternate Sync word to listen for */ + RCL_Command_TxPower txPower; /*!< Transmit power for ACKs */ + uint8_t addrLen; /*!< Length of address after header (0-4 bytes) */ + struct { + uint8_t disableSyncA: 1; /*!< 0: Listen for syncWordA. 1: Do not listen for syncWordA */ + uint8_t disableSyncB: 1; /*!< 0: Listen for syncWordB. 1: Do not listen for syncWordB */ + uint8_t discardRxPackets: 1; /*!< 0: Store received packets in rxBuffers. + 1: Do not store packets, useful for link tests where checksum result is enough */ + uint8_t fsOff: 1; /*!< 0: Keep PLL enabled after command. 1: Turn off FS after command. */ + uint8_t repeatOk: 1; /*!< 0: End operation after receiving a packet correctly. + 1: Go back to sync search after receiving a packet correctly */ + uint8_t repeatNok: 1; /*!< 0: End operation after receiving a packet with CRC error or address mismatch. + 1: Go back to sync search after receiving a packet with CRC error or address + mismatch */ + uint8_t reserved: 2; /*!< Reserved, set to 0 */ + } config; + union { + RCL_ConfigAddress syncWord[2]; + struct { + RCL_ConfigAddress syncWordACfg; + RCL_ConfigAddress syncWordBCfg; + }; + }; +}; +#define RCL_CmdNesbPrx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_NESB_PRX, \ + RCL_Handler_Nesb_Prx), \ + .rfFrequency = 2440000000U, \ + .rxBuffers = {0}, \ + .stats = NULL, \ + .syncWordA = 0x930B51DE, \ + .syncWordB = 0x570451AE, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .addrLen = 4, \ + .config = { \ + .disableSyncA = 0, \ + .disableSyncB = 1, \ + .discardRxPackets = 0, \ + .fsOff = 1, \ + .repeatOk = 1, \ + .repeatNok = 0, \ + .reserved = 0, \ + }, \ + .syncWord[0] = RCL_ConfigAddress_Default(0xEFFEABBA), \ + .syncWord[1] = RCL_ConfigAddress_Default(0xEFFEABBC) \ +} +#define RCL_CmdNesbPrx_DefaultRuntime() (RCL_CmdNesbPrx) RCL_CmdNesbPrx_Default() + +struct RCL_STATS_NESB_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t timestampValid; /*!< Returns 1 if %lastTimestamp is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet. */ + uint32_t lastTimestamp; /*!< Timestamp of last successfully received packet */ + uint32_t nTx; /*!< Number of packets or acknowledgements transmitted */ + uint32_t nRxNok; /*!< Number of packets that have been received with CRC error */ + uint32_t nRxOk; /*!< Number of packets that have been received with CRC OK and not ignored */ + uint32_t nRxIgnored; /*!< Number of packets ignored as retransmissions */ + uint32_t nRxAddrMismatch; /*!< Number of packets ignored due to address mismatch */ + uint32_t nRxBufFull; /*!< Number of packets that have been received and discarded due to lack of buffer space */ +}; + +#define RCL_StatsNesb_Default() \ +{ \ + .config = { 0 }, \ + .timestampValid = 0, \ + .lastRssi = -128, \ +} +#define RCL_StatsNesb_DefaultRuntime() (RCL_StatsNesb) RCL_StatsNesb_Default() + + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/commands/ieee.h b/simplelink_lpf3/source/ti/drivers/rcl/commands/ieee.h new file mode 100644 index 00000000..279190c7 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/commands/ieee.h @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_commands_ieee_h__include +#define ti_drivers_RCL_commands_ieee_h__include + +#include +#include + +#include + +typedef struct RCL_CMD_IEEE_RX_TX_t RCL_CmdIeeeRxTx; +typedef struct RCL_CMD_IEEE_TX_TEST_t RCL_CmdIeeeTxTest; +typedef struct RCL_STATS_IEEE_t RCL_StatsIeee; +typedef struct RCL_CmdIeee_RxAction_t RCL_CmdIeee_RxAction; +typedef struct RCL_CmdIeee_TxAction_t RCL_CmdIeee_TxAction; + +/* Command IDs for generic commands */ +#define RCL_CMDID_IEEE_RX_TX 0x2001U +#define RCL_CMDID_IEEE_TX_TEST 0x2002U + +/** Macro for finding RF frequency from channel */ +#define RCL_CMD_IEEE_CHANNEL_FREQUENCY(channel) ((((channel) - 11UL) * 5000000UL) + 2405000000UL) + +/** + * @brief Appended packet status field from RX buffer + * + */ +typedef union { + struct { + uint8_t crcError :1; /*!< True if packet had CRC error */ + uint8_t ignored :1; /*!< True if packet was ignored */ + uint8_t reserved :6; + }; + uint8_t value; +} RCL_CmdIeee_RxPktStatus; + + /** + * @brief IEEE 802.15.4 Receive and transmit command + * + * Command to receive or transmit a packet + */ +struct RCL_CMD_IEEE_RX_TX_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + RCL_CmdIeee_RxAction *rxAction; /*!< Configuration of receive part of command. NULL: Transmit only */ + RCL_CmdIeee_TxAction *txAction; /*!< Configuration of transmit part of command. NULL: No transmission configured */ + RCL_StatsIeee *stats; /*!< Statistics */ + +}; +#define RCL_CmdIeeeRxTx_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_IEEE_RX_TX, \ + RCL_Handler_Ieee_RxTx), \ + .rfFrequency = 2440000000U, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .rxAction = NULL, \ + .txAction = NULL, \ + .stats = NULL, \ +} +#define RCL_CmdIeeeRxTx_DefaultRuntime() (RCL_CmdIeeeRxTx) RCL_CmdIeeeRxTx_Default() + +typedef enum +{ + RCL_CmdIeee_AutoAck_Off, /*!< No auto-ACK */ + RCL_CmdIeee_AutoAck_ImmAckNoAutoPend, /*!< Send automatic Imm-Ack with frame pending from setting */ + RCL_CmdIeee_AutoAck_ImmAckAutoPendAll, /*!< Send automatic Imm-Ack with frame pending from source matching table */ + RCL_CmdIeee_AutoAck_ImmAckAutoPendDataReq, /*!< Send automatic Imm-Ack with frame pending from source matching table for data requests */ + RCL_CmdIeee_AutoAck_ProvidedFrame, /*!< Send ACK frame provided externally (not supported in this version) */ +} RCL_CmdIeee_AutoAckMode; + +typedef union +{ + struct { + uint16_t panId; /*!< Pan ID of the entry */ + uint16_t shortAddr; /*!< Short address of the entry */ + }; + uint32_t combined; +} RCL_CmdIeee_PanIdAddr; + +/** Maximum number of entries in %RCL_CmdIeee_SourceMatchingTableShort (assuming no extended entry) */ +#define RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_MAX_LEN 64 + +/** Maximum number of entries in %RCL_CmdIeee_SourceMatchingTableShort if an extended table is present*/ +#define RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_WITH_EXT_MAX_LEN 32 + +#define RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_NUM_WORDS \ +(((RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_MAX_LEN) + ((8 * sizeof(uint16_t)) - 1)) / (8 * sizeof(uint16_t))) + +typedef struct +{ + uint32_t numEntries; /*!< Number of entries in the list */ + uint16_t entryEnable[RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_NUM_WORDS]; /*!< Bits indicating which entires are enabled for matching (1 means enabled) */ + uint16_t framePending[RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_NUM_WORDS]; /*!< Frame pending bits for the entries */ + RCL_CmdIeee_PanIdAddr shortEntry[]; /*!< PAN ID and short address for the entry */ +} RCL_CmdIeee_SourceMatchingTableShort; + +/** Maximum number of entries in %RCL_CmdIeee_SourceMatchingTableExt */ +#define RCL_CMD_IEEE_SOURCE_MATCH_TABLE_EXT_MAX_LEN 16 + +#define RCL_CMD_IEEE_SOURCE_MATCH_TABLE_EXT_NUM_WORDS \ +(((RCL_CMD_IEEE_SOURCE_MATCH_TABLE_EXT_MAX_LEN) + ((8 * sizeof(uint16_t)) - 1)) / (8 * sizeof(uint16_t))) + +typedef struct +{ + uint32_t numEntries; /*!< Number of entries in the list */ + uint16_t entryEnable[RCL_CMD_IEEE_SOURCE_MATCH_TABLE_EXT_NUM_WORDS]; /*!< Bits indicating which entires are enabled for matching (1 means enabled) */ + uint16_t framePending[RCL_CMD_IEEE_SOURCE_MATCH_TABLE_EXT_NUM_WORDS]; /*!< Frame pending bits for the entries */ + uint64_t extEntry[]; /*!< Extended address for the entry */ +} RCL_CmdIeee_SourceMatchingTableExt; + +typedef struct RCL_CmdIeee_PanConfig_t +{ + uint64_t localExtAddr; /*!< Extended address of device */ + uint16_t localPanId; /*!< PAN ID of device */ + uint16_t localShortAddr; /*!< Short address of device */ + RCL_CmdIeee_AutoAckMode autoAckMode : 3; /*!< Auto-ACK mode */ + uint8_t defaultPend : 1; /*!< Default value of frame pending bit */ + uint8_t panCoord : 1; /*!< 0: Device is not pan coordinator. 1: Device is PAN coordinator */ + uint8_t maxFrameVersion : 2; /*!< Maximum frame version to accept */ + RCL_CmdIeee_SourceMatchingTableShort *sourceMatchingTableShort; /*!< Source matching table for short addresses */ + RCL_CmdIeee_SourceMatchingTableExt *sourceMatchingTableExt; /*!< Source matching table for extended addresses (not supported in this version)*/ +} RCL_CmdIeee_PanConfig; + +#define RCL_CmdIeee_PanConfig_Default() \ +{ \ + .localExtAddr = 0, \ + .localPanId = 0, \ + .localShortAddr = 0, \ + .autoAckMode = RCL_CmdIeee_AutoAck_Off, \ + .defaultPend = 0, \ + .panCoord = 0, \ + .maxFrameVersion = 1, \ + .sourceMatchingTableShort = NULL, \ + .sourceMatchingTableExt = NULL, \ +} +#define RCL_CmdIeee_PanConfig_DefaultRuntime() (RCL_CmdIeee_PanConfig) RCL_CmdIeee_PanConfig_Default() + +/* Do include after typedefs, as the types are needed in ti/drivers/rcl/handlers/ieee.h */ +#include + +/** Maximum number of simultaneously supported PANs */ +#define RCL_CMD_IEEE_MAX_NUM_PAN 1 /* Maximum number of PANs; will be updated to 2 when dual PAN support is added */ + +struct RCL_CmdIeee_RxAction_t +{ + List_List rxBuffers; /*!< Linked list of buffers for storing received packets */ + uint8_t numPan; /*!< Number of PANs to support. 0: Frame filtering disabled (promiscuous mode). 1: Single PAN. 2: Dual PAN (not supported in this version). */ + bool frameFiltStop; /*!< 0: Receive frame to the end on frame filtering mismatch. 1: Go back to sync search on frame filtering mismatch. Not supported in this version. */ + bool disableSync; /*!< 0: Receive packets normally. 1: Do not sync to received SFD (not supported in this version). */ + bool alwaysStoreAck; /*!< 0: Store ACKs received after transmission only. 1: Store all received ACKs. */ + RCL_CmdIeee_PanConfig panConfig[RCL_CMD_IEEE_MAX_NUM_PAN]; /*!< PAN configuration for the supplied PANs */ +}; + +#define RCL_CmdIeee_RxAction_Default() \ +{ \ + .rxBuffers = { 0 }, \ + .numPan = 0, \ + .frameFiltStop = false, \ + .disableSync = false, \ + .alwaysStoreAck = false, \ + .panConfig = {RCL_CmdIeee_PanConfig_Default()} \ +} +#define RCL_CmdIeee_RxAction_DefaultRuntime() (RCL_CmdIeee_RxAction) RCL_CmdIeee_RxAction_Default() + +typedef enum +{ + RCL_CmdIeee_NoCca = 0, /*!< No CCA; transmit unconditionally */ + RCL_CmdIeee_CcaMode1Energy = 1, /*!< Report busy channel on energy above threshold */ + RCL_CmdIeee_CcaMode2Signal = 2, /*!< Report busy channel on DSSS signal observed */ + RCL_CmdIeee_CcaMode3EnergyOrSignal = 3, /*!< Report busy channel on energy above threshold OR DSSS signal observed */ + RCL_CmdIeee_CcaMode4Aloha = 4, /*!< Always report idle channel when not receiving a packet */ + RCL_CmdIeee_CcaMode3EnergyAndSignal = 7, /*!< Report busy channel on energy above threshold AND DSSS signal observed */ +} RCL_CmdIeee_CcaMode; + +struct RCL_CmdIeee_TxAction_t +{ + RCL_CommandStatus txStatus; /*!< Returned status of TX operation */ + int8_t rssiLimit; /*!< RSSI limit (dBm) for energy based CCA */ + RCL_ScheduleType ccaScheduling : 1; /*!< Schedule type for the CCA part */ + uint16_t allowDelay : 1; /*!< 0: Give error if CCA time is in the past. 1: Start immediately if CCA time is in the past */ + RCL_CmdIeee_CcaMode ccaMode : 3; /*!< CCA mode */ + uint16_t ccaCorrThresh : 3; /*!< Correlation threshold for signal based CCA (0-7; correlation tops in 128 us window) */ + uint16_t ccaContentionWindow : 2; /*!< Initial contention window value for CCA */ + uint16_t expectImmAck : 1; /*!< 0: Immediate ACK not expected. 1: Immediate ACK expected */ + uint16_t expectEnhAck : 1; /*!< 0: Enhanced ACK not expected. 1: Enhanced ACK expected. Not supported in this version. */ + uint16_t allowTxDelay : 1; /*!< 0: Give error if TX time is in the past. 1: Send TX packet immediately if TX time is in the past */ + uint16_t endCmdWhenDone : 1; /*!< 0: Keep command and RX action alive after TX action is done. 1: End command after TX action is done */ + uint32_t absCcaStartTime; /*!< Absolute start time of the CCA part */ + uint16_t relativeTxStartTime; /*!< Start time of TX packet relative to the CCA start time */ + uint16_t ackTimeout; /*!< Timeout for getting sync on ACK relative to end of transmitted packet */ + RCL_Buffer_DataEntry *txEntry; /*!< Entry holding frame to be transmitted */ + uint32_t txTimeStamp; /*!< Returned time stamp of transmitted packet. Not supported in this version. */ +}; +#define RCL_CmdIeee_TxAction_Default() \ +{ \ + .txStatus = RCL_CommandStatus_Idle, \ + .rssiLimit = -70, \ + .ccaScheduling = RCL_Schedule_Now, \ + .allowDelay = 1, \ + .ccaMode = RCL_CmdIeee_NoCca, \ + .ccaCorrThresh = 3, \ + .ccaContentionWindow = 1, \ + .expectImmAck = 0, \ + .expectEnhAck = 0, \ + .allowTxDelay = 1, \ + .endCmdWhenDone = 0, \ + .absCcaStartTime = 0, \ + .relativeTxStartTime = 0, \ + .ackTimeout = RCL_SCHEDULER_SYSTIM_US(300), \ + .txEntry = NULL, \ + .txTimeStamp = 0, \ +} +#define RCL_CmdIeee_TxAction_DefaultRuntime() (RCL_CmdIeee_TxAction) RCL_CmdIeee_TxAction_Default() + + +/** + * @brief IEEE 802.15.4 transmitter test command + * + * Command to transmit continuously, either a modulated signal or continuous wave + */ +struct RCL_CMD_IEEE_TX_TEST_t { + RCL_Command common; + uint32_t rfFrequency; /*!< RF frequency in Hz to program */ + RCL_Command_TxPower txPower; /*!< Transmit power */ + uint16_t txWord; /*!< Repeated word to transmit */ + struct { + uint8_t whitenMode: 2; /*!< 0. No whitening. 1: PRBS-9. 2: PRBS-15. 3: PRBS-32 */ + uint8_t sendCw: 1; /*!< 0: Send modulated signal. 1: Send CW */ + uint8_t reserved: 5; /*!< Reserved, set to 0 */ + } config; +}; +#define RCL_CmdIeeeTxTest_Default() \ +{ \ + .common = RCL_Command_Default(RCL_CMDID_IEEE_TX_TEST, \ + RCL_Handler_Ieee_TxTest), \ + .rfFrequency = 2440000000U, \ + .txPower = {.dBm = 0, .fraction = 0}, \ + .txWord = 0, \ + .config = { \ + .whitenMode = 2, \ + .sendCw = 0, \ + .reserved = 0, \ + }, \ +} +#define RCL_CmdIeeeTxTest_DefaultRuntime() (RCL_CmdIeeeTxTest) RCL_CmdIeeeTxTest_Default() + +#define RCL_CMD_IEEE_WH_MODE_OFF 0 /*!< config.whitenMode: No whitening */ +#define RCL_CMD_IEEE_WH_MODE_PRBS9 1 /*!< config.whitenMode: PRBS-9 */ +#define RCL_CMD_IEEE_WH_MODE_PRBS15 2 /*!< config.whitenMode: PRBS-15 */ +#define RCL_CMD_IEEE_WH_MODE_PRBS32 3 /*!< config.whitenMode: PRBS-32 */ + +struct RCL_STATS_IEEE_t { + struct + { + uint8_t accumulate : 1; /*!< 0: Reset counters to 0 at start of command. 1: Add to incoming value of counters. */ + uint8_t activeUpdate : 1; /*!< 0: Update only at end of command. 1: Update after receiving or transmitting packets. */ + uint8_t reserved : 6; /*!< Reserved, set to 0 */ + } config; /*!< Configuration provided to RCL */ + uint8_t timestampValid; /*!< Returns 1 if %lastTimestamp is updated; 0 otherwise */ + int8_t lastRssi; /*!< RSSI of last received packet */ + int8_t maxRssi; /*!< Highest RSSI observed during the operation (only updated after packets and at the end of operation). Not supported in this version. */ + uint32_t lastTimestamp; /*!< Timestamp of last successfully received packet */ + uint16_t nRxNok; /*!< Number of packets received with CRC error */ + uint16_t nRxFifoFull; /*!< Number of packets received that did not fit in RX FIFO */ + uint16_t nRxOk; /*!< Number of correctly received packets */ + uint16_t nRxIgnored; /*!< Number of ignored packets received */ + uint16_t nTxAck; /*!< Number of auto-ACKs transmitted */ + uint16_t nTx; /*!< Number of frames transmitted */ +}; + +#define RCL_StatsIeee_Default() \ +{ \ + .config = { 0 }, \ + .timestampValid = 0, \ + .lastRssi = LRF_RSSI_INVALID, \ + .maxRssi = LRF_RSSI_INVALID, \ +} +#define RCL_StatsIeee_DefaultRuntime() (RCL_StatsIeee) RCL_StatsIeee_Default() + + + +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c b/simplelink_lpf3/source/ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c new file mode 100644 index 00000000..1db28411 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/hal/cc23x0/hal_cc23x0.c @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== hal_cc23x0rx.c ======== + */ + +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_systim.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_evtsvt.h) +#include DeviceFamily_constructPath(inc/hw_clkctl.h) +#include DeviceFamily_constructPath(inc/hw_ckmd.h) + +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) + +#include DeviceFamily_constructPath(driverlib/lrfd.h) + +#include + +#include + +#ifndef SOCFPGA +/* FPGA doesn't support Standby */ +static int hal_power_post_notify_fxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +Power_NotifyObj powerAwakeStandbyObj; +Power_NotifyObj powerEnterStandbyObj; + +static void (*rclPowerNotify)(RCL_PowerEvent) = NULL; +#endif +static void hal_cancel_lrfd_systim0(void); + +#define RCL_DEFAULT_HFTRACKCTL_RATIO CKMD_HFTRACKCTL_RATIO_REF48M + +static HwiP_Struct schedHwi; +void (*halSchedFsmCb)(void) = NULL; + +static void RF_schedHwi(uintptr_t a) +{ + (void) a; + if (halSchedFsmCb != NULL) + { + halSchedFsmCb(); + } +} + +static HwiP_Struct dispatchHwi; +void (*halDispatchFsmCb)(void) = NULL; +static void RF_dispatchHwi(uintptr_t a) +{ + (void) a; + if (halDispatchFsmCb != NULL) + { + halDispatchFsmCb(); + } +} + +static HwiP_Struct commandHwi; +void (*halCommandFsmCb)(void) = NULL; +static void RF_commandHwi(uintptr_t a) +{ + (void) a; + if (halCommandFsmCb != NULL) + { + halCommandFsmCb(); + } +} + +uint32_t hal_get_command_ifg_reg(void) +{ + uint32_t dbellIrq; + /* Using masked interrupt */ + dbellIrq = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_MIS0); + /* Remove SYSTIM 0 and 1 interrupts, as they should be handled by hal_check_clear_timer_compare() */ + dbellIrq &= ~(LRFDDBELL_MIS0_SYSTIM0_M | LRFDDBELL_MIS0_SYSTIM1_M); + /* Clear interrupts (unmasked only) */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = dbellIrq; + + return dbellIrq; +} + +uint32_t hal_get_dispatch_ifg_reg(void) +{ + uint32_t dbellIrq; + /* Using masked interrupt */ + dbellIrq = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_MIS1); + /* Clear interrupts (unmasked only) */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR1) = dbellIrq; + + return dbellIrq; +} + +/* + * Initialize RCL interrupt handlers + */ +void hal_init_fsm(void (*dispatchFsmCb)(void), void (*schedFsmCb)(void), + void (*commandFsmCb)(void)) +{ + HwiP_Params hp; + HwiP_Params_init(&hp); +#ifdef DeviceFamily_CC27XX + hp.priority = INT_PRI_LEVEL4; +#else + hp.priority = INT_PRI_LEVEL2; +#endif + HwiP_construct(&schedHwi, INT_CPUIRQ4, RF_schedHwi, &hp); +#ifdef DeviceFamily_CC27XX + hp.priority = INT_PRI_LEVEL2; +#else + hp.priority = INT_PRI_LEVEL1; +#endif + HwiP_construct(&dispatchHwi, INT_LRFD_IRQ1, RF_dispatchHwi, &hp); +#ifdef DeviceFamily_CC27XX + hp.priority = INT_PRI_LEVEL1; +#else + hp.priority = INT_PRI_LEVEL0; +#endif + HwiP_construct(&commandHwi, INT_LRFD_IRQ0, RF_commandHwi, &hp); + + halDispatchFsmCb = dispatchFsmCb; + halSchedFsmCb = schedFsmCb; + halCommandFsmCb = commandFsmCb; + /* TODO: See RCL-345 */ + + HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ4SEL) = 0xE; /* LRFDIRQ2 */ +} + + +void hal_trigger_command_fsm(void) +{ + /* Software trig command FSM */ + HwiP_post(INT_LRFD_IRQ0); +} + +void hal_trigger_dispatch_fsm(void) +{ + /* Software trig dispatch IRQ */ + HwiP_post(INT_LRFD_IRQ1); +} + +void hal_trigger_scheduler_fsm(void) +{ + /* Software schedule IRQ */ + HwiP_post(INT_CPUIRQ4); +} + +uint32_t hal_get_current_time(void) +{ + return HWREG(SYSTIM_BASE + SYSTIM_O_TIME250N); +} + +enum { + SYSTIM_CH2_SETUP = 1, /* Early start, to kick off setup */ + SYSTIM_CH2_START = 2, /* Start event to radio */ + SYSTIM_CH2_STOP = 3, /* Hard stop time */ +} channel2usage = SYSTIM_CH2_SETUP; + +void hal_enable_setup_time_irq(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | LRFDDBELL_IMASK0_SYSTIM0_M; +} + +void hal_setup_setup_time(uint32_t time) +{ + channel2usage = SYSTIM_CH2_SETUP; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM0_M; + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CC) = time; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | LRFDDBELL_IMASK0_SYSTIM0_M; +#ifndef SOCFPGA + /* The power driver uses SYSTIM_0_IMASK to restore the timeouts (including CH2). + Therefore, we need to set this register in case the system goes into standby. */ + HWREG(SYSTIM_BASE + SYSTIM_O_IMSET) = SYSTIM_IMSET_EV2_SET; +#endif +} + +void hal_setup_start_time(uint32_t time) +{ + channel2usage = SYSTIM_CH2_START; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM0_M; + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CC) = time; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | LRFDDBELL_IMASK0_SYSTIM0_M; +} + +void hal_setup_hard_stop_time(uint32_t time) +{ + channel2usage = SYSTIM_CH2_STOP; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM0_M; + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CC) = time; + /* Interrupt is not always needed, as event will be handled by PBE */ +} + +void hal_enable_hard_stop_time_irq(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | LRFDDBELL_IMASK0_SYSTIM0_M; +} + +void hal_disable_hard_stop_time_irq(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & ~LRFDDBELL_IMASK0_SYSTIM0_M; +} + +void hal_setup_graceful_stop_time(uint32_t time) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM1_M; + HWREG(SYSTIM_BASE + SYSTIM_O_CH3CC) = time; + /* Interrupt is not always needed, as event will be handled by PBE */ +} + +void hal_enable_graceful_stop_time_irq(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | LRFDDBELL_IMASK0_SYSTIM1_M; +} + +static void hal_cancel_lrfd_systim0(void) +{ + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CC) = 0; + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CFG) = SYSTIM_CH2CFG_MODE_CAPT; + HWREG(SYSTIM_BASE + SYSTIM_O_CH2CFG) = SYSTIM_CH2CFG_MODE_DIS; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & (~LRFDDBELL_IMASK0_SYSTIM0_M); +#ifndef SOCFPGA + /* The power driver uses SYSTIM_0_IMASK to restore the timeouts (including CH2). + Therefore, we need to clear the CH2 IMASK field in addition. */ + HWREG(SYSTIM_BASE + SYSTIM_O_IMCLR) = SYSTIM_IMCLR_EV2_CLR; +#endif +} + +void hal_cancel_setup_time(void) +{ + hal_cancel_lrfd_systim0(); +} + +void hal_cancel_start_time(void) +{ + hal_cancel_lrfd_systim0(); +} + +void hal_cancel_hard_stop_time(void) +{ + hal_cancel_lrfd_systim0(); +} + +void hal_cancel_graceful_stop_time(void) +{ + HWREG(SYSTIM_BASE + SYSTIM_O_CH3CC) = 0; + HWREG(SYSTIM_BASE + SYSTIM_O_CH3CFG) = SYSTIM_CH3CFG_MODE_CAPT; + HWREG(SYSTIM_BASE + SYSTIM_O_CH3CFG) = SYSTIM_CH3CFG_MODE_DIS; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & ~LRFDDBELL_IMASK0_SYSTIM1_M; +} + +void hal_enable_clk_buffer(void) +{ +#ifndef SOCFPGA + /* FPGA doesn't support standby */ + HWREG( CKMD_BASE + CKMD_O_HFXTCTL ) |= CKMD_HFXTCTL_HPBUFEN; +#endif +} + +void hal_setup_sync_found_cap(void) +{ + /* SRAT sync found repeat capture config */ + /* Route event_ibus(21) (mdm) to DBELL input (capt_sources[0]) */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_SYSTIMEVTMUX0) = (21 << LRFDMDM_SYSTIMEVTMUX0_SEL0_S); + /* Route through DBELL */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_SYSTIMOEV) = (LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM0); + /* SYSTIM channel 4 uses srat_ievent(0) as repeated capture trigger */ + HWREG(SYSTIM_BASE + SYSTIM_O_CH4CFG) |= SYSTIM_CH4CFG_INP_RISE | SYSTIM_CH4CFG_MODE_CAPT | SYSTIM_CH4CFG_REARM_EN; +} + +HalTimerEvent hal_check_clear_timer_compare(void) +{ + HalTimerEvent event = HAL_TIMER_EVT_NONE; + + uint32_t mis0 = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_MIS0); + + /* Start or hard-stop takes priority, meaning hard-stop takes priority over graceful. */ + if (mis0 & LRFDDBELL_MIS0_SYSTIM0_M) + { + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & (~LRFDDBELL_IMASK0_SYSTIM0_M); + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM0_M; +#ifndef SOCFPGA + /* The power driver uses SYSTIM_0_IMASK to restore the timeouts (including CH2). + Therefore, we need to clear the CH2 IMASK field in addition. */ + HWREG(SYSTIM_BASE + SYSTIM_O_IMCLR) = SYSTIM_IMCLR_EV2_CLR; +#endif + switch (channel2usage) + { + case SYSTIM_CH2_SETUP: + event = HAL_TIMER_EVT_SETUP; + break; + case SYSTIM_CH2_START: + event = HAL_TIMER_EVT_START; + break; + case SYSTIM_CH2_STOP: + event = HAL_TIMER_EVT_HARD_STOP; + break; + default: + break; + } + } + else if (mis0 & LRFDDBELL_MIS0_SYSTIM1_M) + { + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & (~LRFDDBELL_IMASK0_SYSTIM1_M); + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = LRFDDBELL_ICLR0_SYSTIM1_M; + event = HAL_TIMER_EVT_GRACEFUL_STOP; + } + return event; +} + +void hal_init_dispatch_radio_interrupts(uint32_t mask) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR1) = ~0; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK1) = mask; +} + +void hal_enable_command_radio_interrupt(uint32_t mask) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = + HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) | mask; +} + +void hal_clear_command_radio_interrupt(uint32_t mask) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = mask; +} + +void hal_disable_command_radio_interrupt(uint32_t mask) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = + HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) & ~mask; +} + +void hal_disable_all_command_radio_interrupts(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = 0; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = ~0; +} + +void hal_disable_all_dispatch_radio_interrupts(void) +{ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK1) = 0; + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR1) = ~0; +} + +void hal_set_rcl_clock_enable(uint16_t mask) +{ + uintptr_t key = HwiP_disable(); + LRFDSetClockDependency(mask, LRFD_CLK_DEP_RCL); + HwiP_restore(key); +} + +void hal_clear_rcl_clock_enable(uint16_t mask) +{ + uintptr_t key = HwiP_disable(); + LRFDReleaseClockDependency(mask, LRFD_CLK_DEP_RCL); + HwiP_restore(key); +} + +#ifndef SOCFPGA +static int hal_power_post_notify_fxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + (void) eventArg; + (void) clientArg; + + if (rclPowerNotify != NULL) + { + if (eventType == PowerLPF3_AWAKE_STANDBY) + { + rclPowerNotify(RCL_POWER_STANDBY_AWAKE); + } + else if (eventType == PowerLPF3_ENTERING_STANDBY) + { + rclPowerNotify(RCL_POWER_STANDBY_ENTER); + } + } + return (Power_NOTIFYDONE); +} +#endif + +void hal_power_set_constraint(void) +{ +#ifndef SOCFPGA + /* FPGA doesn't support standby */ + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + Log_printf(RclCore, Log_INFO, "Power constraints set"); +#endif +} + +void hal_power_release_constraint(void) +{ +#ifndef SOCFPGA + /* FPGA doesn't support standby */ + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + Log_printf(RclCore, Log_INFO, "Power constraints released"); +#endif +} + +void hal_power_open(void (*f)(RCL_PowerEvent)) +{ +#ifndef SOCFPGA + rclPowerNotify = f; + + /* Register power notification functions */ + Power_registerNotify(&powerEnterStandbyObj, PowerLPF3_ENTERING_STANDBY, hal_power_post_notify_fxn, (uintptr_t)NULL); + Power_registerNotify(&powerAwakeStandbyObj, PowerLPF3_AWAKE_STANDBY, hal_power_post_notify_fxn, (uintptr_t)NULL); +#endif +} + +void hal_power_close(void) +{ +#ifndef SOCFPGA + /* Unregister power notification objects */ + Power_unregisterNotify(&powerEnterStandbyObj); + Power_unregisterNotify(&powerAwakeStandbyObj); +#endif +} + +void hal_temperature_init(void) +{ + Temperature_init(); +} + +/* Make function weak to allow tests to override reported temperature */ +__attribute__((weak)) int16_t hal_get_temperature(void) +{ + return Temperature_getTemperature(); +} + +uint32_t hal_get_hfxt_ratio(void) +{ + return (HWREG(CKMD_BASE + CKMD_O_HFTRACKCTL) & CKMD_HFTRACKCTL_RATIO_M) >> CKMD_HFTRACKCTL_RATIO_S; +} + +uint32_t hal_get_hfxt_ratio_default(void) +{ +#ifdef DeviceFamily_CC27XX + return 0x00200000U; +#else + return RCL_DEFAULT_HFTRACKCTL_RATIO; +#endif +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/hal/hal.h b/simplelink_lpf3/source/ti/drivers/rcl/hal/hal.h new file mode 100644 index 00000000..f8c4b082 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/hal/hal.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __rcl_hal_h__ +#define __rcl_hal_h__ + +#include + +void hal_init_fsm(void (*setupFsmCb)(void), void (*schedFsmCb)(void), + void (*commandFsmCb)(void)); +void hal_trigger_command_fsm(void); +void hal_trigger_dispatch_fsm(void); +void hal_trigger_scheduler_fsm(void); +uint32_t hal_get_command_ifg_reg(void); +uint32_t hal_get_dispatch_ifg_reg(void); +uint32_t hal_get_current_time(void); +void hal_enable_setup_time_irq(void); +void hal_setup_setup_time(uint32_t setupTime); +void hal_setup_start_time(uint32_t startTime); +void hal_setup_packet_timeout(uint32_t stopTime); +void hal_setup_hard_stop_time(uint32_t stopTime); +void hal_enable_hard_stop_time_irq(void); +void hal_disable_hard_stop_time_irq(void); +void hal_setup_graceful_stop_time(uint32_t stopTime); +void hal_enable_graceful_stop_time_irq(void); +void hal_cancel_setup_time(void); +void hal_cancel_start_time(void); +void hal_cancel_packet_timeout(void); +void hal_cancel_hard_stop_time(void); +void hal_cancel_graceful_stop_time(void); +void hal_init_dispatch_radio_interrupts(uint32_t mask); +void hal_enable_command_radio_interrupt(uint32_t mask); +void hal_disable_command_radio_interrupt(uint32_t mask); +void hal_clear_command_radio_interrupt(uint32_t mask); +void hal_disable_all_command_radio_interrupts(void); +void hal_disable_all_dispatch_radio_interrupts(void); +void hal_temperature_init(void); +int16_t hal_get_temperature(void); +uint32_t hal_get_hfxt_ratio(void); +uint32_t hal_get_hfxt_ratio_default(void); + +typedef enum { + HAL_TIMER_EVT_NONE = 0, + HAL_TIMER_EVT_SETUP = 1, + HAL_TIMER_EVT_START = 2, + HAL_TIMER_EVT_GRACEFUL_STOP = 3, + HAL_TIMER_EVT_HARD_STOP = 4, + HAL_TIMER_EVT_PACKET_TIMEOUT = 5, +} HalTimerEvent; + +typedef enum { + RCL_POWER_STANDBY_AWAKE = 0, + RCL_POWER_XTAL_AVAILABLE = 1, + RCL_POWER_STANDBY_ENTER = 2, +} RCL_PowerEvent; + +HalTimerEvent hal_check_clear_timer_compare(void); +void hal_setup_cmd_start_cap(void); +void hal_arm_cmd_start_cap(void); +uint32_t hal_get_cmd_start_cap(void); +void hal_setup_sync_found_cap(void); +void hal_arm_sync_found_cap(void); +uint32_t hal_get_sync_found_cap(void); +void hal_setup_cmd_done_cap(void); +void hal_arm_cmd_done_cap(void); +uint32_t hal_get_cmd_done_cap(void); +void hal_set_rcl_clock_enable(uint16_t mask); +void hal_clear_rcl_clock_enable(uint16_t mask); +void hal_enable_clk_buffer(void); +void hal_power_set_constraint(void); +void hal_power_release_constraint(void); +void hal_power_open(void (*f)(RCL_PowerEvent)); +void hal_power_close(void); +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.c b/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.c new file mode 100644 index 00000000..b1e885f3 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.c @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== adc_noise.c ======== + */ + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe32.h) +#include DeviceFamily_constructPath(inc/rfe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/hw_lrfds2r.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) + +/* Storage location of S2R samples */ +#define ADC_NOISE_SAMPLE_MEM (PBE_RAM_BASE_ADDR) +#define ADC_NOISE_SAMPLE_PTR ((uint32_t *)ADC_NOISE_SAMPLE_MEM) +/* Start-address of PBE RAM in S2R address-space */ +#ifdef DeviceFamily_CC23X0R2 +#define ADC_NOISE_SAMPLE_MEM_S2R_START 1024 +#else +#define ADC_NOISE_SAMPLE_MEM_S2R_START 2048 +#endif + +struct +{ + uint8_t synthRefsys:1; + uint8_t powerUp:1; + uint8_t s2rConversion:1; +} adcNoiseHandlerState; + +static void RCL_Handler_Adc_Noise_configureS2R(uint32_t numWords); +static void RCL_Handler_Adc_Noise_powerUp(void); +static void RCL_Handler_Adc_Noise_powerDown(void); + +/* + * ======== RCL_Handler_ADC_Noise_getNoise ======== + */ +RCL_Events RCL_Handler_ADC_Noise_getNoise(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdAdcNoiseGet *adcCmd = (RCL_CmdAdcNoiseGet *)cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_CommandStatus startTimeStatus; + + /* Verify that length is greater than 0, and does not exceed maximum. + * A length of 0 is not handled by the S2R module, so abort here. + */ + if ((adcCmd->numWords == 0) || (adcCmd->numWords > RCL_ADC_NOISE_MAX_NUM_WORDS)) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + return rclEvents; + } + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + /* Schedule new command start-time to wait for refsys */ + startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + LRF_disableSynthRefsys(); + } + else + { + /* Initialise handler state */ + adcNoiseHandlerState.powerUp = 0; + adcNoiseHandlerState.s2rConversion = 0; + + /* Indicate that command has been accepted and is active */ + cmd->status = RCL_CommandStatus_Active; + /* Update handler state */ + adcNoiseHandlerState.synthRefsys = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + if (adcNoiseHandlerState.synthRefsys != 0) + { + /* Power up hardware */ + RCL_Handler_Adc_Noise_powerUp(); + + /* Configure S2R */ + RCL_Handler_Adc_Noise_configureS2R(adcCmd->numWords); + + Log_printf(RclCore, Log_VERBOSE, "RFE powered up. Configured S2R for %d words, buffer: 0x%x", adcCmd->numWords, adcCmd->output); + + adcNoiseHandlerState.synthRefsys = 0; + adcNoiseHandlerState.powerUp = 1; + rclEvents.cmdStarted = 1; + } + + if (adcNoiseHandlerState.s2rConversion != 0) + { + /* Make sure S2R is complete */ + while (HWREG_READ_LRF(LRFDS2R_BASE + LRFDS2R_O_STAT) & LRFDS2R_STAT_RUNNING_M); + + /* Power down hardware */ + RCL_Handler_Adc_Noise_powerDown(); + + if (adcCmd->output == NULL) + { + /* Update output pointer if it was NULL */ + adcCmd->output = ADC_NOISE_SAMPLE_PTR; + } + else + { + /* Copy data from ADC_NOISE_SAMPLE_MEM to output buffer */ + memcpy(adcCmd->output, ADC_NOISE_SAMPLE_PTR, adcCmd->numWords * sizeof(uint32_t)); + /* Clear data from LRF RAM */ + memset(ADC_NOISE_SAMPLE_PTR, 0, adcCmd->numWords * sizeof(uint32_t)); + } + + /* Command is complete */ + adcNoiseHandlerState.s2rConversion = 0; + cmd->status = RCL_CommandStatus_Finished; + rclEvents.lastCmdDone = 1; + } + } + + if (lrfEvents.rfedone != 0) + { + /* Hardware is powered up - proceed to start collecting samples */ + if (adcNoiseHandlerState.powerUp != 0) + { + RCL_CommandStatus startTimeStatus; + + /* Clear messagebox */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX) = 0; + /* Start RX */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEAPI) = 3; + /* Wait until RX is up and running */ + while ((HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_RFECMDIN) & 0x08) == 0); + + /* Disable LNA and mixer clocks to reduce impact of any signal received on the antenna */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_LNA) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_LNA) & (~LRFDRFE_LNA_EN_M); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_DIVCTL) = HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_DIVCTL) & (~(LRFDRFE_DIVCTL_RXPH90DIV_M | LRFDRFE_DIVCTL_RXPH0DIV_M)); + + /* Initialize and enable ADC digital interface */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_INIT) = (LRFDMDM_INIT_ADCDIG_RESET); + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_ENABLE) = (LRFDMDM_ENABLE_ADCDIG_EN); + + /* Trigger one shot capture */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_TRIG) = LRFDS2R_TRIG_TRIG_ARM; + + /* Wait for S2R to complete by setting new handler start time. + * ADC sampling frequency is ~11.5 MSamples/s, or 3 words / 260 ns. + * We wait for (words / 3) * 250 ns, as there is no need to sleep for too long. + * The handler will poll for the last few us before reading out the samples + */ + startTimeStatus = RCL_Scheduler_setNewStartAbsTime(RCL_Scheduler_getCurrentTime() + adcCmd->numWords / 3, true); + + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + RCL_Handler_Adc_Noise_powerDown(); + } + else + { + adcNoiseHandlerState.s2rConversion = 1; + } + + adcNoiseHandlerState.powerUp = 0; + } + } + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_Adc_Noise_configureS2R ======== + */ +static void RCL_Handler_Adc_Noise_configureS2R(uint32_t numWords) +{ + /* Enable S2R module */ + LRF_setRclClockEnable(LRFDDBELL_CLKCTL_S2R_M); + + /* Configure S2R */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_ADCDIGCONF) = (1 << LRFDMDM_ADCDIGCONF_QBRANCHEN_S) | (1 << LRFDMDM_ADCDIGCONF_IBRANCHEN_S); + + /* Setup Sample capture, use PBE RAM for storing samples */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_CFG) = ((LRFDS2R_CFG_TRIGMODE_ONESHOT) | + (LRFDS2R_CFG_SEL_ADCDIG) | + (LRFDS2R_CFG_CTL_EN)); + + /* Set start-address of where to store samples */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_START) = ADC_NOISE_SAMPLE_MEM_S2R_START; + /* Set stop-address */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_STOP) = ADC_NOISE_SAMPLE_MEM_S2R_START + numWords - 1; +} + +/* + * ======== RCL_Handler_Adc_Noise_powerUp ======== + */ +static void RCL_Handler_Adc_Noise_powerUp(void) +{ + /* Write precomputed frequency words, based on frequency: 2440000000 */ + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_K5) = 0x9160; + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_CALMMID_CALMCRS) = 0x098604C4; + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PLLM0) = 0x130E0000; + HWREG_WRITE_LRF(LRFDRFE32_BASE + LRFDRFE32_O_PLLM1) = 0x163B0000; + HWREGH_WRITE_LRF(LRFD_RFERAM_BASE + RFE_COMMON_RAM_O_RXIF) = 0; + + /* Initialize and enable RFE TOPsm */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_INIT) = (1 << LRFDRFE_INIT_TOPSM_S); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_ENABLE) = (1 << LRFDRFE_ENABLE_TOPSM_S); + + /* Wait for boot done */ + while(HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX) != 4); + + /* Clear message box */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX) = 0; + /* Calibrate PLL */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEAPI) = 4; + + /* Enable RFEDONE interrupt */ + LRF_enableHwInterrupt(LRFDDBELL_IMASK0_RFEDONE_M); +} + +/* + * ======== RCL_Handler_Adc_Noise_powerDown ======== + */ +static void RCL_Handler_Adc_Noise_powerDown(void) +{ + /* Disable RFEDONE interrupt */ + LRF_disableHwInterrupt(LRFDDBELL_IMASK0_RFEDONE_M); + + /* Clear message box */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX) = 0; + /* Stop Radio */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEAPI) = 1; + + /* Wait until radio stops */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEMSGBOX) == 0); + + /* Clear message box */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX) = 0; + /* Stop PLL */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEAPI) = 5; + + /* Wait until radio stops */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RFEMSGBOX) == 0); + + /* Disable S2R module */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_CFG) = 0; + /* Initialize/Reset (needed for safe shut down of ADCDIG) */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_INIT) = 0xFFFF; + /* Stop modem */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_ENABLE) = 0; + + /* Request RFE powerdown */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PDREQ) = LRFDRFE_PDREQ_TOPSMPDREQ_M; + /* Disable all RFE modules */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_ENABLE) = 0; + /* Stop powerdown request */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PDREQ) = 0; + + /* Disable S2R module */ + LRF_clearRclClockEnable(LRFDDBELL_CLKCTL_S2R_M); + + /* Disable refsys */ + LRF_disableSynthRefsys(); +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.h b/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.h new file mode 100644 index 00000000..fcbc4564 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/adc_noise.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_handlers_adc_noise_h__include +#define ti_drivers_RCL_handlers_adc_noise_h__include + +#include +#include +#include + +RCL_Events RCL_Handler_ADC_Noise_getNoise(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); + +#endif // ti_drivers_RCL_handlers_adc_noise_h__include diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.c b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.c new file mode 100644 index 00000000..d1b2dcb7 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.c @@ -0,0 +1,6341 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ble5.c ======== + */ + +#include +#include + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include DeviceFamily_constructPath(inc/pbe_ble5_ram_regs.h) +#include DeviceFamily_constructPath(inc/hw_lrfdtxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/pbe_ble5_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_ble5_regdef_regs.h) + +#define RCL_HANDLER_BLE5_RESTORE_NONE 0x0000 +#define RCL_HANDLER_BLE5_RESTORE_MODCTRL 0x0001 +#define RCL_HANDLER_BLE5_RESTORE_WHITEN_POLY 0x0002 + +typedef struct +{ + RCL_Buffer_TxBuffer *lastEnteredTxBuffer; + uint8_t *lastTxHdr; + bool isConnBuffer; + uint16_t numBytes; + uint16_t numBuffers; +} RCL_TxBufferInfo; + +typedef struct +{ + uint8_t pktLen; + uint8_t chIndex: 6; + uint8_t ca: 1; + uint8_t offsetUnits: 1; + uint16_t auxOffset: 13; + uint16_t auxPhy: 3; + uint8_t ptrIndex; + uint8_t *auxOffsetLowFifoPtr; + uint8_t *auxOffsetHighFifoPtr; + uint8_t *auxChCaOffsetUnitsFifoPtr; + uint8_t numPrimaryChPackets; + bool auxPtrPresent; +} RCL_AuxPtrInfo; + +struct +{ + struct { + uint32_t defaultRfFrequency; + bool accessAddressModification; + RCL_CommandStatus endStatus; + bool activeUpdate; + RCL_Ble5Channel channel; + uint16_t rxFifoSz; + uint16_t txFifoSz; + uint16_t phyFeatures; + uint16_t fifoCfg; + int8_t filterListUpdateIndex; + RCL_MultiBuffer *curBuffer; + uint32_t timestampAdjust; + RCL_FilterList *updatableFilterList; + RCL_AuxPtrInfo auxPtrInfo; + RCL_TxBufferInfo txBufferInfo; + } common; + union { + struct { + uint8_t chanMap; + bool runRx; + bool gracefulStopObserved; + bool isExtAdv; + bool switchPhy; + bool auxScanReqReceived; + uint8_t auxScanRspLen; + uint8_t auxAdvIndLen; + } adv; + struct { + bool runRx; + bool gracefulStopObserved; + bool sendAuxAdv; + bool auxScanReqReceived; + uint8_t auxScanRspLen; + uint8_t auxAdvIndLen; + } auxAdv; + struct { + bool gracefulStopObserved; + } perAdv; + struct { + bool initiator; + bool dynamicWinOffset; + bool switchPhy; + bool followAuxPtr; + bool isExtAdv; + uint8_t advPktLen; + uint16_t *winOffsetFifoPtr; + uint16_t *winOffsetBufferPtr; + uint16_t transmitWindowOffset; + uint16_t *intervalFifoPtr; + uint16_t connectInterval; + uint16_t filterListInvertMask; + } scanInit; + struct { + bool followAuxPtr; + } perScan; + struct { + bool isPeripheral; + } conn; + struct { + uint16_t demc1be0; + uint16_t demc1be1; + uint16_t demc1be2; +#ifdef DeviceFamily_CC27XX + uint16_t demc1be12; +#endif + bool restoreThresh; + } genericRx; + struct { + uint16_t storedPbeTimPre; + } dtmTx; + struct { + uint8_t restoreSelector; + uint32_t storedWhitenPoly; + } txTest; + + }; +} ble5HandlerState; + +uint32_t RCL_Handler_BLE5_getRandomNumber(void); +static void RCL_Handler_BLE5_updateRxCurBufferAndFifo(List_List *rxBuffers); +static uint16_t RCL_Handler_BLE5_findWhitenInit(RCL_Ble5Channel channel); +static uint32_t RCL_Handler_BLE5_findRfFreq(RCL_Ble5Channel channel); +static RCL_Ble5Channel RCL_Handler_BLE5_findAdvChannel(uint32_t advMap, uint32_t order); +static RCL_CommandStatus RCL_Handler_BLE5_setPhy(uint16_t phyFeatures); +static RCL_CommandStatus RCL_Handler_BLE5_findPbeErrorEndStatus(uint16_t pbeEndStatus); +static uint32_t RCL_Handler_BLE5_updateTxBuffers(List_List *txBuffers, + uint32_t maxBuffers, + RCL_TxBufferInfo *txBufferInfo, + bool retransPossible); +static void RCL_Handler_BLE5_commitPacket(RCL_MultiBuffer *curBuffer, uint32_t numBytes); +static uint32_t RCL_Handler_BLE5_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate); +static bool RCL_Handler_BLE5_initAdvScanInitStats(RCL_StatsAdvScanInit *stats, uint32_t startTime); +static void RCL_Handler_BLE5_updateAdvScanInitStats(RCL_StatsAdvScanInit *stats, uint32_t startTime); +static bool RCL_Handler_BLE5_initConnStats(RCL_StatsConnection *stats, uint32_t startTime); +static void RCL_Handler_BLE5_updateConnStats(RCL_StatsConnection *stats, uint32_t startTime); +static bool RCL_Handler_BLE5_initGenericRxStats(RCL_StatsGenericRx *stats, uint32_t startTime); +static void RCL_Handler_BLE5_updateGenericRxStats(RCL_StatsGenericRx *stats, uint32_t startTime); +static void RCL_Handler_BLE5_InitializeFilterList(RCL_FilterList *filterList, uint32_t *pbeFilterList, uint32_t invertMask); +static void RCL_Handler_BLE5_updateFilterListEntry(RCL_FilterList *filterList, uint32_t *pbeFilterList, uint32_t invertMask, uint32_t index); +static uint32_t RCL_Handler_BLE5_prepareConnectTime(uint32_t *connectTime, uint32_t referenceTime, uint32_t interval); +static uint32_t RCL_Handler_BLE5_findConnectTime(uint32_t initialConnectTime, uint32_t referenceTime, uint32_t interval); +static uint32_t RCL_Handler_BLE5_findPacketDuration(uint32_t length, uint16_t phyFeatures); +static uint16_t RCL_Handler_BLE5_findRxSyncOverhead(uint16_t phyFeatures); +static uint32_t RCL_Handler_BLE5_findNumExtraBytes(uint32_t fifoCfg); +static void RCL_Handler_BLE5_getAuxPtrFromTxBuffer(RCL_Buffer_TxBuffer *curBuffer, RCL_AuxPtrInfo *auxPtrInfo, uint8_t offset); +static bool RCL_Handler_BLE5_updateAuxPtr(RCL_AuxPtrInfo *auxPtr, uint32_t packetDuration, uint8_t chanMap, bool switchPhy); +static void RCL_Handler_BLE5_readAuxPtrFromRxBuffer(uint32_t *data32, RCL_AuxPtrInfo *auxPtrInfo); +static void RCL_Handler_BLE5_updateBackoffParams(RCL_CtxScanInit * ctx, uint16_t endCause); +static uint8_t RCL_Handler_BLE5_checkExtHdrField(uint8_t extHdrFlags, uint8_t fieldMask); + + + +/* First BLE data channel number */ +#define BLE_DATA_CHAN_MIN 0U +/* Last BLE data channel number */ +#define BLE_DATA_CHAN_MAX 36U +/* Frequency of first BLE data channel */ +#define BLE_DATA_CHAN_BASE 2404000000U +/* BLE channel spacing */ +#define BLE_CHAN_SPACE 2000000U +/* Lower advertising channel */ +#define BLE_ADV_CHAN_LO 37U +/* Middle advertising channel */ +#define BLE_ADV_CHAN_MID 38U +/* Upper advertising channel */ +#define BLE_ADV_CHAN_HI 39U +/* First BLE PHY channel number */ +#define BLE_PHY_CHAN_MIN 64U +/* Last BLE PHY channel number */ +#define BLE_PHY_CHAN_MAX 103U +/* Frequency of lower advertising channel */ +#define BLE_ADV_CHAN_LO_FREQ 2402000000U +/* Frequency of middle advertising channel */ +#define BLE_ADV_CHAN_MID_FREQ 2426000000U +/* Frequency of upper advertising channel */ +#define BLE_ADV_CHAN_HI_FREQ 2480000000U +/* Interval between advertising packets when using high duty cycle advertising */ +#define HIGH_DUTY_CYCLE_INTERVAL RCL_SCHEDULER_SYSTIM_US(1250) +/* Transmit delay between primary channel extended advertising packets */ +#define EXT_ADV_INTERVAL_US 330U +/* Transmit delay associated with phy switching */ +#define EXT_ADV_PHY_SWITCHING_DELAY_US 120U +/* See RCL-513.To be characterized */ +#define RX_START_OVERHEAD 240U +#define RX_SYNC_OVERHEAD_1MBPS 164U +#define RX_SYNC_OVERHEAD_2MBPS 120U +#define RX_SYNC_OVERHEAD_CODED 1600U +/* Express systim units in terms of offset units */ +#define BLE_convertSystimUnitsToOffsetUnits(x, offsetUnit) \ +((((uint32_t)(x) >> 2) + offsetUnit - 1) / ((uint32_t)(offsetUnit))) +/* Time from start of preamble to SYSTIM capture at sync found */ +#define TIMESTAMP_ADJUST_1MBPS 267U +/* Time from start of preamble to SYSTIM capture at sync found */ +#define TIMESTAMP_ADJUST_2MBPS 148U +/* Time from start of preamble to SYSTIM capture at sync found */ +#define TIMESTAMP_ADJUST_CODED 1673U +/* Access address for advertising */ +#define ADV_ACCESS_ADDRESS 0x8E89BED6U +/* Access address for DTM packets */ +#define DTM_ACCESS_ADDRESS (~ADV_ACCESS_ADDRESS) +/* CRC initialization for advertising */ +#define ADV_CRC_INIT (0x555555U << 8) +/* Maximum exponent of backoff algorithm */ +#define BACKOFF_UPPER_MAX 8U +/* Timing of packets: */ +/* Duration of a 1 Mbps packet with length = 0 */ +#define BLE_1MBPS_PACKET_BASE_TIME RCL_SCHEDULER_SYSTIM_US(80) +/* Duration of an additional byte for 1 Mbps */ +#define BLE_1MBPS_TIME_PER_BYTE RCL_SCHEDULER_SYSTIM_US(8) +/* Duration of a 2 Mbps packet with length = 0 */ +#define BLE_2MBPS_PACKET_BASE_TIME RCL_SCHEDULER_SYSTIM_US(44) +/* Duration of an additional byte for 2 Mbps */ +#define BLE_2MBPS_TIME_PER_BYTE RCL_SCHEDULER_SYSTIM_US(4) +/* Duration of a 125 kbps packet with length = 0 */ +#define BLE_CODED_S8_PACKET_BASE_TIME RCL_SCHEDULER_SYSTIM_US(720) +/* Duration of an additional byte for 125 kbps */ +#define BLE_CODED_S8_TIME_PER_BYTE RCL_SCHEDULER_SYSTIM_US(64) +/* Duration of a 500 kbps packet with length = 0 */ +#define BLE_CODED_S2_PACKET_BASE_TIME RCL_SCHEDULER_SYSTIM_US(462) +/* Duration of an additional byte for 500 kbps */ +#define BLE_CODED_S2_TIME_PER_BYTE RCL_SCHEDULER_SYSTIM_US(16) +/* Interframe space */ +#define BLE_T_IFS RCL_SCHEDULER_SYSTIM_US(150) +/* Header length in bytes */ +#define BLE_HEADER_LENGTH 2 +/* Number of padding bytes */ +#define BLE_NUM_PAD 3 +/* CRC length in bytes */ +#define BLE_CRC_LENGTH 3 +/* Maximum length of a BLE packet */ +#define BLE_MAX_PKT_LEN 255 +/* Maximum length of a legacy advertising packet */ +#define BLE_ADV_LEGACY_MAX_PKT_LEN 37 +/* Maximum length of an extended advertising packet */ +#define BLE_ADV_EXTENDED_MAX_PKT_LEN 255 +/* Length of an AUX_SCAN_REQ */ +#define BLE_ADV_AUX_SCAN_REQ_PKT_LEN 12 +/* Clock Accuracy scale factor */ +#define BLE_CLK_ACCURACY_SCALE_FACTOR 26 +/* 50 PPM clock accuracy scaled by 2^26 */ +#define BLE_SCALED_CLK_ACCURACY_50PPM 3355 +/* 500 PPM clock accuracy scaled by 2^26 */ +#define BLE_SCALED_CLK_ACCURACY_500PPM 33550 + +/* Bit controlling advertiser filter policy for scanning */ +#define BLE_ADV_FILTER_POLICY_SCAN 1 +/* Bit controlling advertiser filter policy for connection */ +#define BLE_ADV_FILTER_POLICY_CONN 2 + +/* Number of filter list entries in PBE */ +#define PBE_NUM_FILTER_ENTRIES 16U + +/* PHY feature definitions - must match the setup */ +#define BLE_PHY_FEATURE_PHY_1MBPS 0 +#define BLE_PHY_FEATURE_PHY_2MBPS 1 +#define BLE_PHY_FEATURE_PHY_CODED 2 +#define BLE_PHY_FEATURE_PHY_MASK 0x0003 +#define BLE_PHY_FEATURE_CODING_S8 0 +#define BLE_PHY_FEATURE_CODING_S2 4 +#define BLE_PHY_FEATURE_CODING_MASK 0x0004 + +/* DTM packet header definition */ +#define BLE_DTM_PAYLOAD_TYPE_PRBS9 0x00 +#define BLE_DTM_PAYLOAD_TYPE_11110000 0x01 +#define BLE_DTM_PAYLOAD_TYPE_10101010 0x02 +#define BLE_DTM_PAYLOAD_TYPE_PRBS15 0x03 +#define BLE_DTM_PAYLOAD_TYPE_11111111 0x04 +#define BLE_DTM_PAYLOAD_TYPE_00000000 0x05 +#define BLE_DTM_PAYLOAD_TYPE_00001111 0x06 +#define BLE_DTM_PAYLOAD_TYPE_01010101 0x07 + +/** Polynomial to use for PRBS9 data */ +#define RCL_HANDLER_BLE5_PRBS9_POLY 0x08800000 +#define RCL_HANDLER_BLE5_PRBS9_INIT 0x0000001F +/** Polynomial to use for PRBS15 data */ +#define RCL_HANDLER_BLE5_PRBS15_POLY 0x00060000 +#define RCL_HANDLER_BLE5_PRBS15_INIT 0x00003FFF +/** Polynomial to use for PRBS32 data */ +#define RCL_HANDLER_BLE5_PRBS32_POLY 0x00400007 +#define RCL_HANDLER_BLE5_PRBS32_INIT 0x00005555 +#define RCL_HANDLER_BLE5_PRBS_SYNC 0xAB05FA1C + +/* Transmit window timing constants */ +/* Payload length of a CONNECT_IND or AUX_CONNECT_REQ in bytes */ +#define BLE_CONNECT_MSG_LEN 34U +/* Payload length of an AUX_CONNECT_RSP in bytes */ +#define BLE_AUX_CONNECT_RSP_MSG_LEN 14U +/* Position of WinSize in a CONNECT_IND or AUX_CONNECT_REQ */ +#define BLE_WIN_SIZE_POS 19U +/* Position of WinOffset in a CONNECT_IND or AUX_CONNECT_REQ */ +#define BLE_WIN_OFFSET_POS 20U +/* Position of Interval in a CONNECT_IND or AUX_CONNECT_REQ */ +#define BLE_INTERVAL_POS 22U +/* Position of Latency in a CONNECT_IND or AUX_CONNECT_REQ */ +#define BLE_LATENCY_POS 24U +/* Position of Timeout in a CONNECT_IND or AUX_CONNECT_REQ */ +#define BLE_TIMEOUT_POS 26U +/* Transmit window delay for legacy advertising */ +#define BLE_TRANSMIT_WINDOW_DELAY_LEGACY RCL_SCHEDULER_SYSTIM_US(1250) +/* Transmit window delay for extended advertising */ +#define BLE_TRANSMIT_WINDOW_DELAY_EXT_UNCODED RCL_SCHEDULER_SYSTIM_US(2500) +#define BLE_TRANSMIT_WINDOW_DELAY_EXT_CODED RCL_SCHEDULER_SYSTIM_US(3750) +/* Connection interval unit */ +#define BLE_CONNECT_INT_UNIT RCL_SCHEDULER_SYSTIM_US(1250) +/* Number of sub-intervals per connection interval unit used in connection setup */ +#define RCL_BLE5_CONNECT_INT_SUB_DIV 4 +/* Duration of a sub-interval */ +#define RCL_BLE5_CONNECT_SUB_INT (BLE_CONNECT_INT_UNIT / RCL_BLE5_CONNECT_INT_SUB_DIV) + +/* LRFD runs on a 48 MHz clock */ +#define LRF_CLOCK_TICKS_PER_US 48 + +/* Offset units for Extended advertising */ +#define BLE_AUX_OFFSET_300_US 300U +#define BLE_AUX_OFFSET_30_US 30U + +/* Bitmask for the advertiser's device address flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_ADVA_BM 0x01 +/* Bitmask for the target's device address flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_TARGETA_BM 0x02 +/* Bitmask for the CTEInfo flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_CTEINFO_BM 0x04 +/* Bitmask for the ADI flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_ADI_BM 0x08 +/* Bitmask for the AuxPtr flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_AUXPTR_BM 0x10 +/* Bitmask for the SyncInfo flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_SYNCINFO_BM 0x20 +/* Bitmask for the Tx Power flag in the Extended Header Flags byte */ +#define BLE_EXTENDED_HEADER_TXPOWER_BM 0x40 + +/* Length in bytes of the advertiser's device address */ +#define BLE_EXTENDED_HEADER_ADVA_LEN 6 +/* Length in bytes of the target's device address */ +#define BLE_EXTENDED_HEADER_TARGETA_LEN 6 +/* Length in bytes of the CTEInfo field */ +#define BLE_EXTENDED_HEADER_CTEINFO_LEN 1 +/* Length in bytes of the CTEInfo field */ +#define BLE_EXTENDED_HEADER_ADI_LEN 2 +/* Length in bytes of the AuxPtr field */ +#define BLE_EXTENDED_HEADER_AUXPTR_LEN 3 +/* Length in bytes of the SyncInfo field */ +#define BLE_EXTENDED_HEADER_SYNCINFO_LEN 18 +/* Length in bytes of the Tx Power field */ +#define BLE_EXTENDED_HEADER_TXPOWER_LEN 1 + +/* Bitmask for accessing PDU Type */ +#define BLE_PDU_TYPE_BM 0x0F + +/* Bitmask for accessing advertising mode */ +#define BLE_ADV_MODE_BM 0xC0 + +/* Advertising physical channel PDU header's PDU Type */ +#define BLE_PDU_ADV_IND 0x00 +#define BLE_PDU_ADV_DIRECT_IND 0x01 +#define BLE_PDU_ADV_NONCONN_IND 0x02 +#define BLE_PDU_ADV_SCAN_IND 0x06 +#define BLE_PDU_ADV_EXTENDED 0x07 +#define BLE_PDU_AUX_CONNECT_RSP 0x08 + +/* Available advertising modes in the common extended advertising payload format */ +#define BLE_ADV_MODE_NONCONN_NONSCAN 0x00 +#define BLE_ADV_MODE_CONN_NONSCAN 0x01 +#define BLE_ADV_MODE_NONCONN_SCAN 0x02 + + +/** + * @brief Pointer to a given byte in the data part of a TX buffer + * + * @param buffer Pointer to TX buffer + * + * @param pos Position + * + */ +#define txBuffer_dataByte(buffer, pos) ((buffer->data) + ((buffer->numPad) - 1 + pos)) + +/* + * ======== RCL_Handler_BLE5_adv ======== + */ +RCL_Events RCL_Handler_BLE5_adv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + uint32_t rfFreq; + RCL_CmdBle5Advertiser *advCmd = (RCL_CmdBle5Advertiser *) cmd; + bool runAdv = false; + bool runExtAdv = false; + bool advDone = false; + RCL_Ble5Channel curChannel; + RCL_Events rclEvents = {.value = 0}; + uint32_t earliestStartTime = 0; + + if (rclEventsIn.setup != 0) + { + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + ble5HandlerState.adv.chanMap = advCmd->chanMap; + + /* Keep track of the number of primary channel packets to be sent based on the channel map */ + ble5HandlerState.common.auxPtrInfo.numPrimaryChPackets = (advCmd->chanMap & 1) + ((advCmd->chanMap >> 1) & 1) + ((advCmd->chanMap >> 2) & 1); + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = ADV_CRC_INIT; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + if (LRF_programTxPower(advCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&advCmd->ctx->rxBuffers); + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* Enter address */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRL) = advCmd->ctx->advA[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRM) = advCmd->ctx->advA[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRH) = advCmd->ctx->advA[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRTYPE) = advCmd->ctx->addrType.own; + + /* Find which type of advertising */ + RCL_Buffer_TxBuffer *txBuffer = RCL_TxBuffer_head(&advCmd->ctx->txBuffers); + uint16_t advCfg = 0; + + if (txBuffer != NULL) + { + uint8_t header = txBuffer->data[txBuffer->numPad - 1]; + + /* Check advertising type */ + switch (header & BLE_PDU_TYPE_BM) + { + case BLE_PDU_ADV_IND: + advCfg = PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M | PBE_BLE5_RAM_ADVCFG_SCANNABLE_M; + ble5HandlerState.adv.runRx = true; + ble5HandlerState.adv.isExtAdv = false; + ble5HandlerState.adv.auxScanReqReceived = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + + case BLE_PDU_ADV_DIRECT_IND: + advCfg = PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M | PBE_BLE5_RAM_ADVCFG_DIRECTED_M; + /* Enter address */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRL) = advCmd->ctx->peerA[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRM) = advCmd->ctx->peerA[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRH) = advCmd->ctx->peerA[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRTYPE) = advCmd->ctx->addrType.peer; + ble5HandlerState.adv.runRx = true; + ble5HandlerState.adv.isExtAdv = false; + ble5HandlerState.adv.auxScanReqReceived = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + + case BLE_PDU_ADV_NONCONN_IND: + advCfg = 0; + ble5HandlerState.adv.runRx = false; + ble5HandlerState.adv.isExtAdv = false; + ble5HandlerState.adv.auxScanReqReceived = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + + case BLE_PDU_ADV_SCAN_IND: + advCfg = PBE_BLE5_RAM_ADVCFG_SCANNABLE_M; + ble5HandlerState.adv.runRx = true; + ble5HandlerState.adv.isExtAdv = false; + ble5HandlerState.adv.auxScanReqReceived = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + + case BLE_PDU_ADV_EXTENDED: + advCfg = 0; + ble5HandlerState.adv.runRx = false; + ble5HandlerState.adv.isExtAdv = true; + ble5HandlerState.adv.auxScanReqReceived = false; + /* Extract AuxPtr information if available */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(txBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Check if a PHY switch is needed before the move to secondary channel advertising */ + if ((cmd->phyFeatures & 0x03) != ble5HandlerState.common.auxPtrInfo.auxPhy) + { + ble5HandlerState.adv.switchPhy = true; + } + else + { + ble5HandlerState.adv.switchPhy = false; + } + } + else + { + ble5HandlerState.adv.switchPhy = false; + } + break; + + default: + advCfg = 0; + ble5HandlerState.adv.runRx = false; + ble5HandlerState.adv.isExtAdv = false; + ble5HandlerState.adv.auxScanReqReceived = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + } + } + /* Enter payload. + * For legacy advertising, maximum two Tx buffers can be entered (to account for possible SCAN_RSP PDUs). + * For extended advertising, enter only one Tx buffer (corresponding to the ADV_EXT_IND PDU). + */ + uint32_t nBuffer; + if (ble5HandlerState.adv.isExtAdv) + { + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { 0 }; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&advCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + } + else + { + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&advCmd->ctx->txBuffers, 2, + NULL, false); + } + if (nBuffer == 0) + { + status = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + /* Scannable types also need a SCAN_RSP */ + if (((advCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) && (nBuffer < 2)) + { + status = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = advCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = (advCmd->ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_ADV_S) & + PBE_BLE5_RAM_FILTPOLICY_ADV_M; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = (advCmd->ctx->rpaModePeer << PBE_BLE5_RAM_RPAMODE_PEERADR_S); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPACONNECT) = advCmd->ctx->acceptAllRpaConnectInd << PBE_BLE5_RAM_RPACONNECT_ENDADV_S; + + if ((advCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) + { + RCL_FilterList *filterList = advCmd->ctx->filterListScan; + uint32_t invertMask = 0; + if ((advCmd->ctx->filterPolicy & BLE_ADV_FILTER_POLICY_SCAN) != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M | + PBE_BLE5_RAM_FL1MASK_EN_M; + } + else + { + if (advCmd->ctx->privIgnMode != 0) + { + /* Set filter list masks for RPA filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider pribvIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M; + invertMask = PBE_BLE5_RAM_FL1MASK_PRIVIGN_M; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + filterList = NULL; + } + } + RCL_Handler_BLE5_InitializeFilterList(filterList, (uint32_t *) (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1INFO0), invertMask); + } + else + { + /* Filter list not applicable */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + } + if ((advCfg & PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M) != 0) + { + RCL_FilterList *filterList = advCmd->ctx->filterListConn; + uint32_t invertMask = 0; + if ((advCmd->ctx->filterPolicy & BLE_ADV_FILTER_POLICY_CONN) != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = PBE_BLE5_RAM_FL2MASK_MATCH_M | + PBE_BLE5_RAM_FL2MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL2MASK_TYPE_M | + PBE_BLE5_RAM_FL2MASK_EN_M; + } + else + { + if (advCmd->ctx->privIgnMode != 0) + { + /* Set filter list masks for RPA filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = PBE_BLE5_RAM_FL2MASK_MATCH_M | + PBE_BLE5_RAM_FL2MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL2MASK_TYPE_M; + invertMask = PBE_BLE5_RAM_FL2MASK_PRIVIGN_M; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + filterList = NULL; + } + } + RCL_Handler_BLE5_InitializeFilterList(filterList, (uint32_t *) (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2INFO0), invertMask); + } + else + { + /* Filter list not applicable */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + } + /* Run advertiser next */ + runAdv = true; + } + + /* Once packets are copied to the TX FIFO, consume them from the Tx Buffer list and notify the caller (only for extended) */ + if (ble5HandlerState.adv.isExtAdv) + { + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&advCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + rclEvents.txBufferFinished = 1; + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + if(rclEventsIn.handlerCmdUpdate != 0) + { + /* PHY change concluded successfully. Proceed with the advertising event */ + runExtAdv = true; + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&advCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + if (ble5HandlerState.adv.isExtAdv) + { + ble5HandlerState.adv.auxScanReqReceived = true; + } + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateAdvScanInitStats(advCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.adv.gracefulStopObserved = true; + } + + if (lrfEvents.opDone != 0 && rclEventsIn.handlerCmdUpdate == 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_CONNECT) + { + /* 32-bit access to also read LASTTIMESTAMPH */ + advCmd->connectPktTime = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) - ble5HandlerState.common.timestampAdjust; + ble5HandlerState.common.endStatus = RCL_CommandStatus_Connect; + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + runAdv = false; + runExtAdv = false; + advDone = true; + } + else if (rclEventsIn.hardStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + runAdv = false; + runExtAdv = false; + advDone = true; + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP || + ble5HandlerState.adv.gracefulStopObserved || + rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + runAdv = false; + runExtAdv = false; + advDone = true; + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC && ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* If no AUX_SCAN_REQ is received, no point in sending any subsequent AUX_CHAIN_IND PDUs */ + runAdv = false; + runExtAdv = false; + advDone = true; + } + else + { + if (ble5HandlerState.adv.chanMap != 0) + { + /* Retry TX FIFO. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RETRY >> LRFDPBE_FCMD_DATA_S); + + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateAdvScanInitStats(advCmd->stats, rclSchedulerState.actualStartTime); + } + + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + runAdv = true; + runExtAdv = false; + advDone = false; + } + else + { + /* Once done with primary channel advertising, check AuxPtr and proceed with extended advertising if needed. */ + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + if (ble5HandlerState.common.auxPtrInfo.offsetUnits == 1 && ble5HandlerState.common.auxPtrInfo.auxOffset == 0) + { + /* Reset TX FIFO to handle auxPtr updates. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RESET >> LRFDPBE_FCMD_DATA_S); + + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + + if (ble5HandlerState.adv.switchPhy) + { + /* Update phyFeatures while keeping the code rate selection intact */ + rclSchedulerState.requestedPhyFeatures = ble5HandlerState.common.auxPtrInfo.auxPhy | (cmd->phyFeatures & 0x04); + + /* Raise a partialSetup event so that the PHY switching can be applied by the RCL */ + rclEvents.partialSetup = 1; + } + else + { + runExtAdv = true; + } + runAdv = false; + advDone = false; + } + else + { + advDone = true; + } + } + else + { + advDone = true; + } + } + } + if (advDone) + { + cmd->status = ble5HandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + runAdv = false; + runExtAdv = false; + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + runAdv = false; + runExtAdv = false; + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&advCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + + if (runAdv) + { + curChannel = RCL_Handler_BLE5_findAdvChannel(ble5HandlerState.adv.chanMap, advCmd->order); + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + rfFreq = RCL_Handler_BLE5_findRfFreq(curChannel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + RCL_CommandStatus startTimeStatus; + + if (rclEventsIn.setup != 0) + { + startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus < RCL_CommandStatus_Finished) + { + if (ble5HandlerState.adv.isExtAdv && ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Calculate auxPtr offset and update Tx FIFO if needed */ + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, ble5HandlerState.adv.chanMap, ble5HandlerState.adv.switchPhy)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = + RCL_Handler_BLE5_initAdvScanInitStats(advCmd->stats, rclSchedulerState.actualStartTime); + ble5HandlerState.adv.gracefulStopObserved = false; + if (rclSchedulerState.gracefulStopInfo.cmdStopEnabled || rclSchedulerState.gracefulStopInfo.schedStopEnabled) + { + /* Enable interrupt to service graceful stop */ + hal_enable_graceful_stop_time_irq(); + } + } + } + else + { + if (advCmd->highDuty != 0) + { + startTimeStatus = RCL_Scheduler_setNewStartRelTime(HIGH_DUTY_CYCLE_INTERVAL); + } + else + { + if (ble5HandlerState.adv.isExtAdv && ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* + * All primary advertising packets must point to the same time at which the auxiliary packet will be sent. + * Achieve this by using a relative start time to previous LRF start where the packet duration is also expressed + * in terms of 30 [us] units. This facilitates the calculation of the auxOffset. + */ + uint32_t pktDurationInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(pktDuration, BLE_AUX_OFFSET_30_US); + uint32_t relStartTime = RCL_SCHEDULER_SYSTIM_US((pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US); + startTimeStatus = RCL_Scheduler_setNewStartRelTime(relStartTime); + + /* Calculate auxPtr offset and update Tx FIFO if needed */ + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, ble5HandlerState.adv.chanMap, ble5HandlerState.adv.switchPhy)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + else + { + startTimeStatus = RCL_Scheduler_setNewStartNow(); + } + } + } + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(curChannel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + /* Enable interrupts */ + if (ble5HandlerState.adv.runRx) + { + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + } + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting advertiser on channel %1d", curChannel); + + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + + if ((curChannel & BLE_CUSTOM_FREQ_BM) != 0) + { + /* Custom channel - run only once */ + ble5HandlerState.adv.chanMap = 0; + } + else + { + ble5HandlerState.adv.chanMap &= ~(1 << (curChannel - 37)); + if (advCmd->highDuty != 0 && ble5HandlerState.adv.chanMap == 0) + { + /* High duty cycle advertising: Reload channel map when one round is done */ + ble5HandlerState.adv.chanMap = advCmd->chanMap; + } + } + } + } + } + if (runExtAdv) + { + RCL_CommandStatus startTimeStatus; + RCL_Ble5Channel channel; + uint32_t startTimeDelta = 0; + + /* Switch to the channel indicated by the auxPtr */ + channel = ble5HandlerState.common.auxPtrInfo.chIndex; + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + RCL_Buffer_TxBuffer *nextTxBuffer = RCL_TxBuffer_head(&advCmd->ctx->txBuffers); + uint16_t advCfg = 0; + uint16_t aeCfg = PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + + if (nextTxBuffer != NULL) + { + /* + * Start time is calculated relative to the duration of the previous packet. If there was a PHY change, + * consider its duration with the previous PHY, before updating the timestamps associated with the new PHY. + */ + if (ble5HandlerState.adv.switchPhy) + { + startTimeDelta = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + /* Consider the time that it takes to handle the PHY switching */ + startTimeDelta += RCL_SCHEDULER_SYSTIM_US(EXT_ADV_PHY_SWITCHING_DELAY_US); + /* Adjust timestamps accordingly */ + RCL_Handler_BLE5_setPhy(rclSchedulerState.requestedPhyFeatures); + ble5HandlerState.adv.switchPhy = false; + } + else + { + startTimeDelta = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + } + + /* Check advertising type and mode */ + uint8_t header = nextTxBuffer->data[nextTxBuffer->numPad - 1]; + uint8_t extHeader = nextTxBuffer->data[nextTxBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + if ((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) + { + switch ((extHeader & BLE_ADV_MODE_BM) >> 6) + { + case BLE_ADV_MODE_NONCONN_NONSCAN: /* Non-connectable - Non-scannable */ + advCfg = 0; + /* Extract AuxPtr information if available */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(nextTxBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + ble5HandlerState.adv.runRx = false; + break; + + case BLE_ADV_MODE_CONN_NONSCAN: /* Connectable - Non-scannable */ + + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(nextTxBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + ble5HandlerState.adv.runRx = false; + /* Connectable PDUs must not have an AuxPtr */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + else + { + advCfg = PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M; + ble5HandlerState.adv.runRx = true; + } + break; + + case BLE_ADV_MODE_NONCONN_SCAN: /* Non-connectable - Scannable */ + /* Scannable PDUs must not have an AuxPtr in the AUX_ADV_IND, so perform a sanity check on it to be sure */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(nextTxBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + ble5HandlerState.adv.runRx = false; + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + else + { + advCfg = PBE_BLE5_RAM_ADVCFG_SCANNABLE_M; + ble5HandlerState.adv.runRx = true; + } + break; + + default: + advCfg = 0; + ble5HandlerState.adv.runRx = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + break; + } + } + else + { + /* Only extended PDUs are valid at this point */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_Param; + } + } + + /* Enter payload */ + uint32_t nBuffer = 0; + if ((advCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) + { + /* Scannable advertising requires the presence of an additional Tx Buffer with an AUX_SCAN_RSP in the Tx buffer list */ + RCL_Buffer_TxBuffer *auxScanRspTxBuffer; + auxScanRspTxBuffer = RCL_TxBuffer_next(nextTxBuffer); + + if (auxScanRspTxBuffer != NULL) + { + uint8_t header = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad - 1]; + uint8_t extHeader = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + /* AUX_SCAN_RSP PDUs may or may not point to a subsequent auxiliary packet. Check the Tx Buffer to see if there is one */ + if (((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) && ((extHeader & BLE_ADV_MODE_BM) >> 6) == 0) + { + /* + * Since both Tx buffers will be put in the PBE FIFO, consider the entry length of the AUX_ADV_IND to determine + * the location of the AuxPtr in the PBE FIFO. This needs to be known so that the AuxPtr fields can be updated + * later. + */ + uint8_t auxAdvEntryLength = RCL_Buffer_entryLen(BLE_NUM_PAD, BLE_HEADER_LENGTH, nextTxBuffer->data[nextTxBuffer->numPad]); + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(auxScanRspTxBuffer, &ble5HandlerState.common.auxPtrInfo, auxAdvEntryLength); + } + /* Enter the two Tx Buffers corresponding to the AUX_ADV_IND and the AUX_SCAN_RSP */ + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&advCmd->ctx->txBuffers, 2, + &ble5HandlerState.common.txBufferInfo, + false); + /* Keep track of the lengths of the AUX_ADV_IND and the AUX_SCAN_IND since they will be used if an AUX_CHAIN_IND is to be sent afterwards */ + ble5HandlerState.adv.auxScanRspLen = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad]; + ble5HandlerState.adv.auxAdvIndLen = nextTxBuffer->data[nextTxBuffer->numPad]; + } + } + else if ((advCfg & PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M) != 0) + { + /* Connectable advertising requires a Tx Buffer with an AUX_CONNECT_RSP */ + RCL_Buffer_TxBuffer *auxConnectRspTxBuffer; + auxConnectRspTxBuffer = RCL_TxBuffer_next(nextTxBuffer); + + if (auxConnectRspTxBuffer != NULL) + { + /* Enter the two Tx Buffers corresponding to the AUX_ADV_IND and the AUX_CONNECT_RSP */ + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&advCmd->ctx->txBuffers, 2, + &ble5HandlerState.common.txBufferInfo, + false); + } + } + else + { + /* Non-scannable advertising is handled one Tx buffer at a time */ + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&advCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + } + + if (nBuffer == 0 || (((advCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) && (nBuffer < 2)) || + (((advCfg & PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M) != 0) && (nBuffer < 2))) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + /* + * Express the startTimeDelta in terms of offset units so that the relative start time is rounded up + * to the closest offset unit. Add a delay of a couple of microseconds to avoid sending the packets right + * at the beginning of the offset window. + */ + startTimeDelta += RCL_SCHEDULER_SYSTIM_US(EXT_ADV_INTERVAL_US); + uint32_t startTimeDeltaInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(startTimeDelta, BLE_AUX_OFFSET_30_US); + uint32_t relStartTime = RCL_SCHEDULER_SYSTIM_US((startTimeDeltaInOffsetUnits * BLE_AUX_OFFSET_30_US)) + RCL_SCHEDULER_SYSTIM_US(2); + /* + * If an AUX_SCAN_REQ was received, the relative start time for the packet needs to consider the + * time spent sending the AUX_ADV_IND, receiving the AUX_SCAN_REQ and replying with the AUX_SCAN_RSP. + * In this particular case, the AUX_SCAN_RSP is the previously sent packet, so no need to include it here. + */ + if (ble5HandlerState.adv.auxScanReqReceived) + { + /* Time spent sending the AUX_ADV_IND */ + relStartTime += RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.adv.auxAdvIndLen, ble5HandlerState.common.phyFeatures); + /* Time spent receiving the AUX_SCAN_REQ */ + relStartTime += RCL_Handler_BLE5_findPacketDuration(BLE_ADV_AUX_SCAN_REQ_PKT_LEN, ble5HandlerState.common.phyFeatures); + /* Time spent switching from Tx to Rx to receive the AUX_SCAN_REQ, and then back from Rx to Tx to send the AUX_SCAN_RSP */ + relStartTime += (2 * BLE_T_IFS); + ble5HandlerState.adv.auxScanReqReceived = false; + } + startTimeStatus = RCL_Scheduler_setNewStartRelTime(relStartTime); + + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Consider the current packet duration when calculating the AuxOffset */ + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, ble5HandlerState.adv.chanMap, ble5HandlerState.adv.switchPhy)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = advCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = (advCmd->ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_ADV_S) & + PBE_BLE5_RAM_FILTPOLICY_ADV_M; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = (advCmd->ctx->rpaModePeer << PBE_BLE5_RAM_RPAMODE_PEERADR_S); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPACONNECT) = advCmd->ctx->acceptAllRpaConnectInd << PBE_BLE5_RAM_RPACONNECT_ENDADV_S; + + if ((advCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) + { + RCL_FilterList *filterList = advCmd->ctx->filterListScan; + uint32_t invertMask = 0; + if ((advCmd->ctx->filterPolicy & BLE_ADV_FILTER_POLICY_SCAN) != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M | + PBE_BLE5_RAM_FL1MASK_EN_M; + } + else + { + if (advCmd->ctx->privIgnMode != 0) + { + /* Set filter list masks for RPA filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider pribvIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M; + invertMask = PBE_BLE5_RAM_FL1MASK_PRIVIGN_M; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + filterList = NULL; + } + } + RCL_Handler_BLE5_InitializeFilterList(filterList, (uint32_t *) (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1INFO0), invertMask); + } + else + { + /* Filter list not applicable */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + } + if ((advCfg & PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M) != 0) + { + RCL_FilterList *filterList = advCmd->ctx->filterListConn; + uint32_t invertMask = 0; + if ((advCmd->ctx->filterPolicy & BLE_ADV_FILTER_POLICY_CONN) != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = PBE_BLE5_RAM_FL2MASK_MATCH_M | + PBE_BLE5_RAM_FL2MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL2MASK_TYPE_M | + PBE_BLE5_RAM_FL2MASK_EN_M; + } + else + { + if (advCmd->ctx->privIgnMode != 0) + { + /* Set filter list masks for RPA filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = PBE_BLE5_RAM_FL2MASK_MATCH_M | + PBE_BLE5_RAM_FL2MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL2MASK_TYPE_M; + invertMask = PBE_BLE5_RAM_FL2MASK_PRIVIGN_M; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + filterList = NULL; + } + } + RCL_Handler_BLE5_InitializeFilterList(filterList, (uint32_t *) (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2INFO0), invertMask); + } + else + { + /* Filter list not applicable */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + } + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + /* Enable interrupts */ + if (ble5HandlerState.adv.runRx) + { + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + } + + LRF_waitForTopsmReady(); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting extended advertiser on channel %1d", channel); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + + /* Free up finished Tx buffers from the Tx Buffer list and raise the appropriate RCL event */ + uint32_t numBuffers = nBuffer; + RCL_Buffer_TxBuffer *txBuffer; + do + { + txBuffer = RCL_TxBuffer_get(&advCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + numBuffers--; + } while (numBuffers > 0); + /* Raise RCL event indicating that the buffers have been consumed */ + rclEvents.txBufferFinished = 1; + } + } + } + } + if (rclEvents.lastCmdDone != 0) + { + RCL_Handler_BLE5_updateAdvScanInitStats(advCmd->stats, rclSchedulerState.actualStartTime); + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_aux_adv ======== + */ +RCL_Events RCL_Handler_BLE5_aux_adv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + uint32_t rfFreq; + RCL_CmdBle5AuxAdvertiser *auxAdvCmd = (RCL_CmdBle5AuxAdvertiser *) cmd; + bool runAuxAdv = false; + bool runAuxChain = false; + RCL_Events rclEvents = {.value = 0}; + uint32_t earliestStartTime = 0; + RCL_Ble5Channel channel; + + if (rclEventsIn.setup != 0) + { + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = ADV_CRC_INIT; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + + if (LRF_programTxPower(auxAdvCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&auxAdvCmd->ctx->rxBuffers); + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* Enter address */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRL) = auxAdvCmd->ctx->advA[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRM) = auxAdvCmd->ctx->advA[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRH) = auxAdvCmd->ctx->advA[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRTYPE) = auxAdvCmd->ctx->addrType.own; + + /* Find which type of advertising */ + RCL_Buffer_TxBuffer *txBuffer = RCL_TxBuffer_head(&auxAdvCmd->ctx->txBuffers); + uint16_t auxAdvCfg = 0; + uint16_t aeCfg = PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + channel = auxAdvCmd->channel; + + if (txBuffer != NULL) + { + uint8_t header = txBuffer->data[txBuffer->numPad - 1]; + uint8_t extHeader = txBuffer->data[txBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + /* Check advertising type */ + if ((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) + { + ble5HandlerState.common.auxPtrInfo.numPrimaryChPackets = 0; + + /* Check advertising mode */ + switch ((extHeader & BLE_ADV_MODE_BM) >> 6) + { + case BLE_ADV_MODE_NONCONN_NONSCAN: /* Non-connectable - Non-scannable */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(txBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + ble5HandlerState.auxAdv.runRx = false; + ble5HandlerState.auxAdv.sendAuxAdv = true; + ble5HandlerState.auxAdv.auxScanReqReceived = false; + break; + case BLE_ADV_MODE_CONN_NONSCAN: /* Connectable - Non-scannable */ + ble5HandlerState.auxAdv.runRx = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + ble5HandlerState.auxAdv.auxScanReqReceived = false; + auxAdvCfg = PBE_BLE5_RAM_ADVCFG_CONNECTABLE_M; + break; + case BLE_ADV_MODE_NONCONN_SCAN: /* Non-connectable - Scannable */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(txBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + ble5HandlerState.auxAdv.runRx = false; + ble5HandlerState.auxAdv.auxScanReqReceived = false; + /* Scannable PDUs must not have an AuxPtr */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + else + { + auxAdvCfg = PBE_BLE5_RAM_ADVCFG_SCANNABLE_M; + ble5HandlerState.auxAdv.runRx = true; + ble5HandlerState.auxAdv.auxScanReqReceived = false; + } + break; + default: + ble5HandlerState.auxAdv.runRx = false; + ble5HandlerState.common.auxPtrInfo.auxPtrPresent = false; + ble5HandlerState.auxAdv.auxScanReqReceived = false; + break; + } + } + else + { + /* Error. Tx Buffer does not correspond to an Extended Advertising PDU */ + status = RCL_CommandStatus_Error_TxBufferCorruption; + } + } + + /* Enter payload */ + uint32_t nBuffer = 0; + if ((auxAdvCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) + { + /* Scannable advertising requires a Tx Buffer with an AUX_SCAN_RSP */ + RCL_Buffer_TxBuffer *auxScanRspTxBuffer; + auxScanRspTxBuffer = RCL_TxBuffer_next(txBuffer); + if (auxScanRspTxBuffer != NULL) + { + uint8_t header = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad - 1]; + uint8_t extHeader = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + /* Perform a sanity check on the AUX_SCAN_RSP and extract its AuxPtr if needed */ + if (((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) && ((extHeader & BLE_ADV_MODE_BM) >> 6) == 0) + { + /* Consider the entry length of the AUX_ADV_IND to determine the pointer to the AuxPtr in the FIFO */ + uint8_t auxAdvEntryLength = RCL_Buffer_entryLen(BLE_NUM_PAD, BLE_HEADER_LENGTH, txBuffer->data[txBuffer->numPad]); + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(auxScanRspTxBuffer, &ble5HandlerState.common.auxPtrInfo, auxAdvEntryLength); + } + /* If it's scannable advertising, two Tx buffers are needed */ + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { 0 }; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&auxAdvCmd->ctx->txBuffers, 2, + &ble5HandlerState.common.txBufferInfo, + false); + /* Keep track of the lengths of the AUX_ADV_IND and the AUX_SCAN_IND since they will be used if an AUX_CHAIN_IND is to be sent afterwards */ + ble5HandlerState.auxAdv.auxScanRspLen = auxScanRspTxBuffer->data[auxScanRspTxBuffer->numPad]; + ble5HandlerState.auxAdv.auxAdvIndLen = txBuffer->data[txBuffer->numPad]; + } + } + else + { + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { 0 }; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&auxAdvCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + } + + if (nBuffer == 0 || (((auxAdvCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) && (nBuffer < 2))) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + /* Free up finished Tx buffers from the Tx Buffer list and raise the appropriate RCL event */ + uint32_t numBuffers = nBuffer; + RCL_Buffer_TxBuffer *txBuffer; + do + { + txBuffer = RCL_TxBuffer_get(&auxAdvCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + numBuffers--; + } while (numBuffers > 0); + /* Raise RCL event indicating that the buffers have been consumed */ + rclEvents.txBufferFinished = 1; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = auxAdvCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = (auxAdvCmd->ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_ADV_S) & + PBE_BLE5_RAM_FILTPOLICY_ADV_M; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = (auxAdvCmd->ctx->rpaModePeer << PBE_BLE5_RAM_RPAMODE_PEERADR_S); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPACONNECT) = auxAdvCmd->ctx->acceptAllRpaConnectInd << PBE_BLE5_RAM_RPACONNECT_ENDADV_S; + + if ((auxAdvCfg & PBE_BLE5_RAM_ADVCFG_SCANNABLE_M) != 0) + { + RCL_FilterList *filterList = auxAdvCmd->ctx->filterListScan; + uint32_t invertMask = 0; + if ((auxAdvCmd->ctx->filterPolicy & BLE_ADV_FILTER_POLICY_SCAN) != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M | + PBE_BLE5_RAM_FL1MASK_EN_M; + } + else + { + if (auxAdvCmd->ctx->privIgnMode != 0) + { + /* Set filter list masks for RPA filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider pribvIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M; + invertMask = PBE_BLE5_RAM_FL1MASK_PRIVIGN_M; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + filterList = NULL; + } + } + RCL_Handler_BLE5_InitializeFilterList(filterList, (uint32_t *) (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1INFO0), invertMask); + } + else + { + /* Filter list not applicable */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + } + if (status >= RCL_CommandStatus_Finished) + { + cmd->status = status; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = auxAdvCfg; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + /* Run advertiser next */ + runAuxAdv = true; + } + } + } + + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&auxAdvCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + ble5HandlerState.auxAdv.auxScanReqReceived = true; + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateAdvScanInitStats(auxAdvCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.auxAdv.gracefulStopObserved = true; + } + + if (lrfEvents.opDone != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_CONNECT) + { + /* 32-bit access to also read LASTTIMESTAMPH */ + auxAdvCmd->connectPktTime = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) - ble5HandlerState.common.timestampAdjust; + + ble5HandlerState.common.endStatus = RCL_CommandStatus_Connect; + runAuxAdv = false; + runAuxChain = false; + } + else if (rclEventsIn.hardStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + runAuxAdv = false; + runAuxChain = false; + + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP || + ble5HandlerState.auxAdv.gracefulStopObserved || + rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + runAuxAdv = false; + runAuxChain = false; + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC && ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* If no AUX_SCAN_REQ is received, no point in sending any subsequent AUX_CHAIN_IND PDUs */ + runAuxAdv = false; + runAuxChain = false; + } + else + { + if (!ble5HandlerState.auxAdv.sendAuxAdv) + { + if(ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + if (ble5HandlerState.common.auxPtrInfo.offsetUnits == 1 && ble5HandlerState.common.auxPtrInfo.auxOffset == 0) + { + /* Reset TX FIFO to handle auxPtr updates. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RESET >> LRFDPBE_FCMD_DATA_S) ; + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + runAuxChain = true; + } + else + { + runAuxChain = false; + } + } + else + { + runAuxChain = false; + } + runAuxAdv = false; + } + } + if (!runAuxAdv && !runAuxChain && cmd->status == RCL_CommandStatus_Active) + { + cmd->status = ble5HandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + runAuxAdv = false; + runAuxChain = false; + } + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + runAuxAdv = false; + runAuxChain = false; + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&auxAdvCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + + if (runAuxAdv) + { + RCL_CommandStatus startTimeStatus; + + /* Set up channel */ + channel = auxAdvCmd->channel; + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + + /* Consider the current packet duration when calculating the AuxOffset */ + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, 0, false)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + if (startTimeStatus < RCL_CommandStatus_Finished) + { + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = + RCL_Handler_BLE5_initAdvScanInitStats(auxAdvCmd->stats, rclSchedulerState.actualStartTime); + ble5HandlerState.auxAdv.gracefulStopObserved = false; + + if (rclSchedulerState.gracefulStopInfo.cmdStopEnabled || rclSchedulerState.gracefulStopInfo.schedStopEnabled) + { + /* Enable interrupt to service graceful stop */ + hal_enable_graceful_stop_time_irq(); + } + } + + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + /* Enable interrupts */ + if (ble5HandlerState.auxAdv.runRx) + { + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + } + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting extended advertiser on channel %1d", channel); + + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + ble5HandlerState.auxAdv.sendAuxAdv = false; + } + } + } + if (runAuxChain) + { + RCL_CommandStatus startTimeStatus; + + RCL_Ble5Channel channel = ble5HandlerState.common.auxPtrInfo.chIndex; + uint16_t auxAdvCfg = 0; + + uint32_t startTimeDelta = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + /* Check advertising type */ + RCL_Buffer_TxBuffer *nextTxBuffer = RCL_TxBuffer_head(&auxAdvCmd->ctx->txBuffers); + if(nextTxBuffer != NULL) + { + uint8_t header = nextTxBuffer->data[nextTxBuffer->numPad - 1]; + uint8_t extHeader = nextTxBuffer->data[nextTxBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + if (((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) && ((extHeader & BLE_ADV_MODE_BM) >> 6) == 0) + { + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(nextTxBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + ble5HandlerState.auxAdv.runRx = false; + } + } + + uint32_t nBuffer = 0; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&auxAdvCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + if (nBuffer == 0) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + /* + * Express the startTimeDelta in terms of offset units so that the relative start time is rounded up + * to the closest offset unit. Also add a couple of microseconds to avoid sending the packets right + * at the beginning of the offset window. + */ + startTimeDelta += RCL_SCHEDULER_SYSTIM_US(EXT_ADV_INTERVAL_US); + uint32_t startTimeDeltaInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(startTimeDelta, BLE_AUX_OFFSET_30_US); + uint32_t relStartTime = RCL_SCHEDULER_SYSTIM_US((startTimeDeltaInOffsetUnits * BLE_AUX_OFFSET_30_US)) + RCL_SCHEDULER_SYSTIM_US(2); + + /* + * If an AUX_SCAN_REQ was received, the relative start time for the packet needs to consider the + * time spent sending the AUX_ADV_IND, receiving the AUX_SCAN_REQ and replying with the AUX_SCAN_RSP. + * In this particular case, the AUX_SCAN_RSP is the previously sent packet, so no need to include it here. + */ + if (ble5HandlerState.auxAdv.auxScanReqReceived) + { + /* Time spent sending the AUX_ADV_IND */ + relStartTime += RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.auxAdv.auxAdvIndLen, ble5HandlerState.common.phyFeatures); + /* Time spent receiving the AUX_SCAN_REQ */ + relStartTime += RCL_Handler_BLE5_findPacketDuration(BLE_ADV_AUX_SCAN_REQ_PKT_LEN, ble5HandlerState.common.phyFeatures); + /* Time spent switching from Tx to Rx, and then back from Rx to Tx */ + relStartTime += (2 * BLE_T_IFS); + ble5HandlerState.auxAdv.auxScanReqReceived = false; + } + + /* Set new start time */ + startTimeStatus = RCL_Scheduler_setNewStartRelTime(relStartTime); + + /* Calculate auxPtr offset and update Tx FIFO if needed */ + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Consider the current packet duration when calculating the AuxOffset */ + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, 0, false)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = auxAdvCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + /* Enable interrupts */ + if (ble5HandlerState.auxAdv.runRx) + { + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + } + + LRF_waitForTopsmReady(); + + /* Deallocate TX FIFO. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_DEALLOC >> LRFDPBE_FCMD_DATA_S); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting extended advertiser on channel %1d", channel); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + + /* Free up the TxBuffer and notify caller with an RCL event */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&auxAdvCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + rclEvents.txBufferFinished = 1; + } + } + } + } + if (rclEvents.lastCmdDone != 0) + { + RCL_Handler_BLE5_updateAdvScanInitStats(auxAdvCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_periodicAdv ======== + */ +RCL_Events RCL_Handler_BLE5_periodicAdv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + uint32_t rfFreq; + RCL_CmdBle5PeriodicAdvertiser *perAdvCmd = (RCL_CmdBle5PeriodicAdvertiser *) cmd; + bool runAuxSync = false; + bool runAuxChain = false; + RCL_Ble5Channel channel; + RCL_Events rclEvents = {.value = 0}; + uint32_t earliestStartTime = 0; + + if (rclEventsIn.setup != 0) + { + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + RCL_CtxPeriodicAdvertiser *ctx = perAdvCmd->ctx; + uint32_t crcInit = ctx->crcInit; + uint32_t accessAddress = ctx->accessAddress; + + /* 32-bit access to set the Access Address for the periodic advertisement */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = crcInit << 8; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + if (LRF_programTxPower(perAdvCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Initialize RF FIFOs */ + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* This operation is always non-connectable/non-scannable */ + RCL_Buffer_TxBuffer *txBuffer = RCL_TxBuffer_head(&perAdvCmd->ctx->txBuffers); + uint16_t advCfg = 0; + uint16_t aeCfg = PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + channel = perAdvCmd->channel; + + if (txBuffer != NULL) + { + uint8_t header = txBuffer->data[txBuffer->numPad - 1]; + uint8_t extHeader = txBuffer->data[txBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + /* Check advertising type. Only extended PDUs with AdvMode set to 0 are allowed */ + if (((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) && (((extHeader & BLE_ADV_MODE_BM) >> 6) == BLE_ADV_MODE_NONCONN_NONSCAN)) + { + /* Extract AuxPtr information if available indicating that an AUX_CHAIN_IND will follow the AUX_SYNC_IND */ + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(txBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + } + else + { + status = RCL_CommandStatus_Error_TxBufferCorruption; + } + } + + /* Enter payload. Enter only one Tx Buffer corresponding to the AUX_SYNC_IND */ + uint32_t nBuffer; + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { 0 }; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&perAdvCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + if (nBuffer == 0) + { + status = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = advCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPACONNECT) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + + /* Once packets are copied to the TX FIFO, consume them from the Tx Buffer list and notify the caller */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&perAdvCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + rclEvents.txBufferFinished = 1; + + /* Run periodic advertising next */ + runAuxSync = true; + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.perAdv.gracefulStopObserved = true; + } + + if (lrfEvents.opDone != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + + if (rclEventsIn.hardStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + runAuxSync = false; + runAuxChain = false; + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP || + ble5HandlerState.adv.gracefulStopObserved || + rclEventsIn.gracefulStop != 0) + { + ble5HandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + runAuxSync = false; + runAuxChain = false; + } + else + { + if(ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + if (ble5HandlerState.common.auxPtrInfo.offsetUnits == 1 && ble5HandlerState.common.auxPtrInfo.auxOffset == 0) + { + /* Reset TX FIFO to handle auxPtr updates. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RESET >> LRFDPBE_FCMD_DATA_S) ; + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + runAuxChain = true; + } + else + { + runAuxChain = false; + } + } + else + { + runAuxChain = false; + } + runAuxSync = false; + } + if (!runAuxSync && !runAuxChain && cmd->status == RCL_CommandStatus_Active) + { + cmd->status = ble5HandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + runAuxSync = false; + runAuxChain = false; + } + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + runAuxSync = false; + runAuxChain = false; + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (runAuxSync) + { + RCL_CommandStatus startTimeStatus; + + /* Set up channel */ + channel = perAdvCmd->channel; + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + + /* Consider the current packet duration when calculating the AuxOffset */ + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, 0, false)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + if (startTimeStatus < RCL_CommandStatus_Finished) + { + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = + RCL_Handler_BLE5_initAdvScanInitStats(perAdvCmd->stats, rclSchedulerState.actualStartTime); + ble5HandlerState.perAdv.gracefulStopObserved = false; + + if (rclSchedulerState.gracefulStopInfo.cmdStopEnabled || rclSchedulerState.gracefulStopInfo.schedStopEnabled) + { + /* Enable interrupt to service graceful stop */ + hal_enable_graceful_stop_time_irq(); + } + } + + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = perAdvCmd->ctx->accessAddress ^ (whitenInit << 24); + } + + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting periodic advertising on channel %1d (access address %08X)", channel, perAdvCmd->ctx->accessAddress); + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + } + } + } + if (runAuxChain) + { + RCL_CommandStatus startTimeStatus; + + RCL_Ble5Channel channel = ble5HandlerState.common.auxPtrInfo.chIndex; + + /* Non-connectable/Non-scannable always*/ + uint16_t advCfg = 0; + uint32_t startTimeDelta = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, true); + LRF_enable(); + + /* Check advertising type */ + RCL_Buffer_TxBuffer *nextTxBuffer = RCL_TxBuffer_head(&perAdvCmd->ctx->txBuffers); + if(nextTxBuffer != NULL) + { + uint8_t header = nextTxBuffer->data[nextTxBuffer->numPad - 1]; + uint8_t extHeader = nextTxBuffer->data[nextTxBuffer->numPad - 1 + BLE_HEADER_LENGTH]; + + if (((header & BLE_PDU_TYPE_BM) == BLE_PDU_ADV_EXTENDED) && ((extHeader & BLE_ADV_MODE_BM) >> 6) == 0) + { + RCL_Handler_BLE5_getAuxPtrFromTxBuffer(nextTxBuffer, &ble5HandlerState.common.auxPtrInfo, 0); + } + } + uint32_t nBuffer = 0; + nBuffer = RCL_Handler_BLE5_updateTxBuffers(&perAdvCmd->ctx->txBuffers, 1, + &ble5HandlerState.common.txBufferInfo, + false); + if (nBuffer == 0) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + /* + * Express the startTimeDelta in terms of offset units so that the relative start time is rounded up + * to the closest offset unit. Also add a couple of microseconds to avoid sending the packets right + * at the beginning of the offset window. + */ + startTimeDelta += RCL_SCHEDULER_SYSTIM_US(EXT_ADV_INTERVAL_US); + uint32_t startTimeDeltaInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(startTimeDelta, BLE_AUX_OFFSET_30_US); + uint32_t relStartTime = RCL_SCHEDULER_SYSTIM_US((startTimeDeltaInOffsetUnits * BLE_AUX_OFFSET_30_US)) + RCL_SCHEDULER_SYSTIM_US(2); + + /* Set new start time */ + startTimeStatus = RCL_Scheduler_setNewStartRelTime(relStartTime); + + /* Calculate auxPtr offset and update Tx FIFO if needed */ + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Consider the current packet duration when calculating the AuxOffset */ + uint32_t pktDuration = RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.common.auxPtrInfo.pktLen, ble5HandlerState.common.phyFeatures); + + if(!RCL_Handler_BLE5_updateAuxPtr(&ble5HandlerState.common.auxPtrInfo, pktDuration, 0, false)) + { + startTimeStatus = RCL_CommandStatus_Error_Param; + } + } + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_ADVCFG) = advCfg; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = perAdvCmd->ctx->accessAddress ^ (whitenInit << 24); + } + + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + LRF_waitForTopsmReady(); + + /* Deallocate TX FIFO. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_DEALLOC >> LRFDPBE_FCMD_DATA_S); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Sending AuxChain on channel %1d (access address %08X)", channel, perAdvCmd->ctx->accessAddress); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_ADV; + + /* Free up the TxBuffer and notify caller with an RCL event */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&perAdvCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + } + txBuffer->state = RCL_BufferStateFinished; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + } + rclEvents.txBufferFinished = 1; + } + } + } + } + if (rclEvents.lastCmdDone != 0) + { + RCL_Handler_BLE5_updateAdvScanInitStats(perAdvCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_scan_init ======== + */ +RCL_Events RCL_Handler_BLE5_scan_init(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBle5Scanner *scanCmd = (RCL_CmdBle5Scanner *) cmd; + RCL_CmdBle5Initiator *initCmd = (RCL_CmdBle5Initiator *) cmd; + uint32_t rfFreq; + RCL_Events rclEvents = RCL_EventNone; + RCL_CtxScanInit *ctx; + RCL_StatsAdvScanInit *stats; + bool followAuxPtr = false; + RCL_ConnParams *connParams; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_Ble5Channel channel; + uint32_t interval = 0; + RCL_Command_TxPower txPower; + bool acceptLegacy; + bool acceptExtended; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = ADV_CRC_INIT; + + /* The initial First Rx Timeout depends on the relative gaceful stop time configured for the command */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTRXTIMEOUT) = 0; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + if (cmd->cmdId == RCL_CMDID_BLE5_INITIATOR) + { + ble5HandlerState.scanInit.initiator = true; + channel = initCmd->channel; + txPower = initCmd->txPower; + acceptLegacy = initCmd->acceptLegacy; + acceptExtended = initCmd->acceptExtended; + } + else + { + ble5HandlerState.scanInit.initiator = false; + channel = scanCmd->channel; + txPower = scanCmd->txPower; + acceptLegacy = scanCmd->acceptLegacy; + acceptExtended = scanCmd->acceptExtended; + } + ble5HandlerState.scanInit.dynamicWinOffset = false; /* Default */ + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + else if (!acceptLegacy && !acceptExtended) + { + cmd->status = RCL_CommandStatus_Error_Param; + } + else if (acceptLegacy && (cmd->phyFeatures != 0)) + { + cmd->status = RCL_CommandStatus_Error_Param; + } + else if (acceptLegacy && !acceptExtended) + { + if (channel != BLE_ADV_CHAN_LO && channel != BLE_ADV_CHAN_MID && channel != BLE_ADV_CHAN_HI) + { + cmd->status = RCL_CommandStatus_Error_Param; + } + } + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + if (ble5HandlerState.scanInit.initiator) + { + ctx = initCmd->ctx; + stats = initCmd->stats; + } + else + { + ctx = scanCmd->ctx; + stats = scanCmd->stats; + } + + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = RCL_Handler_BLE5_initAdvScanInitStats(stats, + rclSchedulerState.actualStartTime); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + /* Configure maximum packet length */ + if (acceptExtended) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MAXLEN) = BLE_ADV_EXTENDED_MAX_PKT_LEN; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MAXLEN) = BLE_ADV_LEGACY_MAX_PKT_LEN; + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRL) = ctx->ownA[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRM) = ctx->ownA[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRH) = ctx->ownA[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRTYPE) = ctx->addrType.own; + + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = (ctx->rpaModeOwn << PBE_BLE5_RAM_RPAMODE_OWNADR_S) | + (ctx->rpaModePeer << PBE_BLE5_RAM_RPAMODE_PEERADR_S); + + ble5HandlerState.common.filterListUpdateIndex = -1; + /* Make sure status is correctly initialized */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FLSTAT) = 0; + if (ble5HandlerState.scanInit.initiator) + { + if (ctx->filterPolicy != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = PBE_BLE5_RAM_FL2MASK_MATCH_M | + PBE_BLE5_RAM_FL2MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL2MASK_TYPE_M | + PBE_BLE5_RAM_FL2MASK_EN_M; + + /* Initialize filter list */ + RCL_Handler_BLE5_InitializeFilterList(ctx->filterList, (uint32_t *)(volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2INFO0), 0); + ble5HandlerState.common.updatableFilterList = ctx->filterList; + } + else + { + /* Filter list not used */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + RCL_Handler_BLE5_InitializeFilterList(NULL, (uint32_t *)(volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2INFO0), 0); + ble5HandlerState.common.updatableFilterList = NULL; + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0; + ble5HandlerState.scanInit.filterListInvertMask = 0; + + /* Set legacy/extended acceptance configuration */ + uint16_t aeCfg = (acceptLegacy << PBE_BLE5_RAM_AECFG_LEGACY_S) & PBE_BLE5_RAM_AECFG_LEGACY_M; + aeCfg |= (acceptExtended << PBE_BLE5_RAM_AECFG_EXTENDED_S) & PBE_BLE5_RAM_AECFG_EXTENDED_M; + if (acceptExtended) + { + /* Accept only connectable/non-scannable advertising modes */ + aeCfg |= PBE_BLE5_RAM_AECFG_ADVMODE1_ACCEPT; + + /* Inform the PBE about the type of channel that will be used for reception */ + if (channel != BLE_ADV_CHAN_LO && channel != BLE_ADV_CHAN_MID && channel != BLE_ADV_CHAN_HI) + { + aeCfg |= PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + } + /* Set backoff (only for connect requests on the secondary advertising physical channel) */ + if (ctx->initialBackoff > 0) + { + /* Backoff definition in PBE is one count less than in Bluetooth spec */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) = ctx->initialBackoff - 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) = 0; + } + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + + /* Set filter policy */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = (ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_INTOR_S) & + PBE_BLE5_RAM_FILTPOLICY_INTOR_M; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRL) = ctx->peerA[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRM) = ctx->peerA[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRH) = ctx->peerA[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PEERADRTYPE) = ctx->addrType.peer; + + RCL_Buffer_TxBuffer *txBuffer = RCL_TxBuffer_head(&ctx->txBuffers); + uint32_t numPad = txBuffer->numPad; + ble5HandlerState.scanInit.winOffsetFifoPtr = + (uint16_t *) LRF_getTxFifoWrAddr(offsetof(RCL_Buffer_DataEntry, pad0) + numPad + BLE_HEADER_LENGTH + BLE_WIN_OFFSET_POS); + ble5HandlerState.scanInit.intervalFifoPtr = + (uint16_t *) LRF_getTxFifoWrAddr(offsetof(RCL_Buffer_DataEntry, pad0) + numPad + BLE_HEADER_LENGTH + BLE_INTERVAL_POS); + + if (txBuffer != NULL) + { + if (txBuffer->length >= 34) + { + ble5HandlerState.scanInit.winOffsetBufferPtr = ((uint16_t *)(txBuffer_dataByte(txBuffer, BLE_HEADER_LENGTH + BLE_WIN_OFFSET_POS))); + ble5HandlerState.scanInit.transmitWindowOffset = HWREGH_READ_LRF(ble5HandlerState.scanInit.winOffsetBufferPtr); + + interval = *((uint16_t *)(txBuffer_dataByte(txBuffer, BLE_HEADER_LENGTH + BLE_INTERVAL_POS))); + } + else + { + ble5HandlerState.scanInit.transmitWindowOffset = 0; + } + if (initCmd->dynamicWinOffset) + { + if (interval == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else + { + ble5HandlerState.scanInit.dynamicWinOffset = true; + /* Set WinSize to 2 */ + *txBuffer_dataByte(txBuffer, BLE_HEADER_LENGTH + BLE_WIN_SIZE_POS) = 2; + + /* TODO: See RCL-346 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_TIMPER1) = RCL_BLE5_CONNECT_SUB_INT - 1; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINMOD) = RCL_BLE5_CONNECT_INT_SUB_DIV * interval + RCL_BLE5_CONNECT_INT_SUB_DIV - 1; + + ble5HandlerState.scanInit.connectInterval = interval; + } + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINMOD) = 0; + } + } + /* Enter CONNECT_IND or AUX_CONNECT_REQ */ + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { 0 }; + if (RCL_Handler_BLE5_updateTxBuffers(&ctx->txBuffers, 1, &ble5HandlerState.common.txBufferInfo, false) == 0) + { + status = RCL_CommandStatus_Error_MissingTxBuffer; + } + } + else + { + if (ctx->filterPolicy != 0) + { + /* Set filter list masks to normal accept list use: */ + /* Bit 0: Consider enable bit */ + /* Bit 1: Consider type bit */ + /* Bit 2: Consider duplicateIgn bit */ + /* Bit 3: Consider privIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = 0x800F; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_PRIVIGN_M | + PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M | + PBE_BLE5_RAM_FL1MASK_EN_M; + ble5HandlerState.scanInit.filterListInvertMask = 0; + } + else + { + /* Set filter list masks to duplicate address filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 2: Consider duplicateIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M; + ble5HandlerState.scanInit.filterListInvertMask = PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M; + } + RCL_Handler_BLE5_InitializeFilterList(ctx->filterList, (uint32_t *)(volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1INFO0), + ble5HandlerState.scanInit.filterListInvertMask); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + ble5HandlerState.common.updatableFilterList = ctx->filterList; + + /* Set active/passive scanner configuration */ + uint16_t scanCfg = (scanCmd->activeScan << PBE_BLE5_RAM_SCANCFG_ACTPASS_S) & PBE_BLE5_RAM_SCANCFG_ACTPASS_M; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_SCANCFG) = scanCfg; + + /* Set legacy/extended acceptance configuration */ + uint16_t aeCfg = (acceptLegacy << PBE_BLE5_RAM_AECFG_LEGACY_S) & PBE_BLE5_RAM_AECFG_LEGACY_M; + aeCfg |= (acceptExtended << PBE_BLE5_RAM_AECFG_EXTENDED_S) & PBE_BLE5_RAM_AECFG_EXTENDED_M; + if (acceptExtended) + { + /* Scanner should accept all packets but only respond to scannable advertisements */ + aeCfg |= PBE_BLE5_RAM_AECFG_ADVMODE0_ACCEPT; + aeCfg |= PBE_BLE5_RAM_AECFG_ADVMODE1_ACCEPT; + aeCfg |= PBE_BLE5_RAM_AECFG_ADVMODE2_ACCEPT; + + /* Inform the PBE about the type of channel that will be used for reception */ + if (channel != BLE_ADV_CHAN_LO && channel != BLE_ADV_CHAN_MID && channel != BLE_ADV_CHAN_HI) + { + aeCfg |= PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + } + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + + /* Set filter policy */ + // TODO: When available, enable SyncInfo filter policy + // HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = ((ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_SCANNER_S) | + // (ctx->scanExtFilterPolicy << PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_S) | + // (ctx->periodicSyncEstablishment << PBE_BLE5_RAM_FILTPOLICY_SYNCINFO_S)) & + // (PBE_BLE5_RAM_FILTPOLICY_SCANNER_M | PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_M | + // PBE_BLE5_RAM_FILTPOLICY_SYNCINFO_M); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = ((ctx->filterPolicy << PBE_BLE5_RAM_FILTPOLICY_SCANNER_S) | + (ctx->scanExtFilterPolicy << PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_S)) & + (PBE_BLE5_RAM_FILTPOLICY_SCANNER_M | PBE_BLE5_RAM_FILTPOLICY_EXTSCANNER_M); + + + /* Set backoff */ + if (ctx->initialBackoff > 0) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) = ctx->initialBackoff - 1; /* Backoff definition in PBE is one less than in Bluetooth spec */ + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) = 0; + } + } + + if (status == RCL_CommandStatus_Active) + { + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + + if (ble5HandlerState.scanInit.initiator) + { + Log_printf(RclCore, Log_VERBOSE, "Starting initiator"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_INITIATOR; + + if (ble5HandlerState.scanInit.dynamicWinOffset) + { + /* Calculate initial winOffset while radio is starting */ + if (acceptExtended && !acceptLegacy) + { + /* + * For extended advertising, a new referenceTime will be calculated once the initiator has moved to a + * secondary advertising channel. + */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINOFFSET) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINMOD) = 0; + } + else + { + /* + * Calculate initial winOffset while radio is starting. Use the actual start time of the command as initial reference, + * and consider that the transmit window starts after the end of the packet containing the AUX_CONNECT_REQ. + */ + uint32_t referenceTime = rclSchedulerState.actualStartTime + + RCL_Handler_BLE5_findPacketDuration(BLE_CONNECT_MSG_LEN, ble5HandlerState.common.phyFeatures) + + BLE_TRANSMIT_WINDOW_DELAY_LEGACY + 3 * RCL_BLE5_CONNECT_SUB_INT; + + /* + * Use the reference time and the requested connect time to calculate an appropriate value for the winOffset. + * The winOffset value is initially set to hit the next window start by considering the desired connect interval, + * but the PBE adjusts it based on the length of the window (WINMOD). + */ + uint32_t initialWinOffset = RCL_Handler_BLE5_prepareConnectTime(&initCmd->connectTime, referenceTime, interval); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINOFFSET) = initialWinOffset; + } + } + } + else + { + Log_printf(RclCore, Log_VERBOSE, "Starting scanner"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_SCAN; + } + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + else + { + bool updateStats = false; + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + if(lrfEvents.rxOk && wordLength > 1) + { + uint32_t header = data32[1] >> 16; + uint32_t type = (header & BLE_PDU_TYPE_BM); + + if (type == BLE_PDU_ADV_EXTENDED) + { + /* Attempt to extract an AuxPtr from the received packet */ + RCL_Handler_BLE5_readAuxPtrFromRxBuffer(data32, &ble5HandlerState.common.auxPtrInfo); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + /* Check auxPhy and request PHY change if needed */ + if (ble5HandlerState.common.channel == BLE_ADV_CHAN_LO || + ble5HandlerState.common.channel == BLE_ADV_CHAN_MID || + ble5HandlerState.common.channel == BLE_ADV_CHAN_HI) + { + if ((cmd->phyFeatures & 0x03) != ble5HandlerState.common.auxPtrInfo.auxPhy) + { + ble5HandlerState.scanInit.switchPhy = true; + } + } + else + { + ble5HandlerState.scanInit.switchPhy = false; + } + ble5HandlerState.scanInit.followAuxPtr = true; + } + else + { + ble5HandlerState.scanInit.followAuxPtr = false; + } + ble5HandlerState.scanInit.isExtAdv = true; + } + else if (type == BLE_PDU_AUX_CONNECT_RSP && ble5HandlerState.scanInit.initiator) + { + /* No auxiliary PDU is expected after receiving an AUX_CONNECT_RSP */ + ble5HandlerState.scanInit.followAuxPtr = false; + ble5HandlerState.scanInit.isExtAdv = true; + } + else + { + /* Handle all other legacy PDU types */ + if (ble5HandlerState.scanInit.initiator) + { + /* Store BLE packet length if this was an accepted connectable advertiser message */ + if (type == BLE_PDU_ADV_IND || type == BLE_PDU_ADV_DIRECT_IND) + { + ble5HandlerState.scanInit.advPktLen = header >> 8; + } + } + ble5HandlerState.scanInit.switchPhy = false; + ble5HandlerState.scanInit.isExtAdv = false; + ble5HandlerState.scanInit.followAuxPtr = false; + } + } + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + ctx = (ble5HandlerState.scanInit.initiator) ? initCmd->ctx : scanCmd->ctx; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + updateStats = true; + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + if (lrfEvents.opError == 0 && (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_RXERR || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC)) + { + /* Backoff updates are handled differently depending on whether it's a scanner or an initiator */ + ctx = (ble5HandlerState.scanInit.initiator) ? initCmd->ctx : scanCmd->ctx; + + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_RXERR || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC) + { + if (!ble5HandlerState.scanInit.initiator) + { + if (ble5HandlerState.scanInit.isExtAdv) + { + /* Only update backoff related variables for the extended usecase after an AUX_SCAN_REQ has been sent. */ + uint16_t chCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) & PBE_BLE5_RAM_AECFG_CHNL_M; + if (ble5HandlerState.scanInit.isExtAdv && (chCfg == PBE_BLE5_RAM_AECFG_CHNL_SECONDARY)) + { + // TODO: Ensure that the backoff procedure is only executed when receiving AUX_SCAN_RSP PDUs and not for subsequent AUX_CHAIN_IND PDUs. + RCL_Handler_BLE5_updateBackoffParams(ctx, endCause); + } + /* Follow AuxPtr if needed and schedule new listening window */ + if (ble5HandlerState.scanInit.followAuxPtr && (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK)) + { + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + if (ble5HandlerState.scanInit.switchPhy) + { + /* Update phyFeatures while keeping the code rate selection intact. Raise a partialSetup event to handle the PHY switch. */ + rclSchedulerState.requestedPhyFeatures = ble5HandlerState.common.auxPtrInfo.auxPhy | (cmd->phyFeatures & 0x04); + rclEvents.partialSetup = 1; + followAuxPtr = false; + } + else + { + /* No need to handle a PHY switch. Proceed with the operation. */ + rclSchedulerState.requestedPhyFeatures = cmd->phyFeatures; + followAuxPtr = true; + } + } + else + { + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = RCL_CommandStatus_Finished; + } + } + else + { + /* Always update the various variables associated with the backoff procedure for legacy advertising */ + RCL_Handler_BLE5_updateBackoffParams(ctx, endCause); + + /* Receiving on a primary channel. Restart scanner unless timed out */ + /* Set to start immediately */ + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setNewStartNow(); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + if (!(rclSchedulerState.hardStopInfo.apiStopEnabled || rclSchedulerState.gracefulStopInfo.apiStopEnabled)) + { + Log_printf(RclCore, Log_VERBOSE, "Restarting scanner"); + /* Reset TXFIFO - needed due to LPRF_PHY-511 */ + /* Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RESET >> LRFDPBE_FCMD_DATA_S); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_SCAN; + if (ble5HandlerState.common.activeUpdate) + { + updateStats = true; + } + } + } + } + } + else /* Initiator */ + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + if (ble5HandlerState.scanInit.isExtAdv && ble5HandlerState.scanInit.followAuxPtr) + { + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + /* Check if a PHY switch was requested */ + if (ble5HandlerState.scanInit.switchPhy) + { + /* Update phyFeatures while keeping the code rate selection intact. Raise a partialSetup event to handle the PHY switch. */ + rclSchedulerState.requestedPhyFeatures = ble5HandlerState.common.auxPtrInfo.auxPhy | (cmd->phyFeatures & 0x04); + rclEvents.partialSetup = 1; + followAuxPtr = false; + } + else + { + rclSchedulerState.requestedPhyFeatures = cmd->phyFeatures; + followAuxPtr = true; + } + } + else + { + endStatus = RCL_CommandStatus_Connect; + /* Find connect time */ + uint32_t transmitWindowOffset; + /* 32-bit acccess to also read LASTTIMESTAMPH */ + uint32_t eventTime = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) - ble5HandlerState.common.timestampAdjust; + uint32_t connectTime; + if (ble5HandlerState.scanInit.dynamicWinOffset) + { + transmitWindowOffset = HWREGH_READ_LRF(ble5HandlerState.scanInit.winOffsetFifoPtr); + /* Write back to transmit buffer */ + HWREGH_WRITE_LRF(ble5HandlerState.scanInit.winOffsetBufferPtr) = transmitWindowOffset; + } + else + { + transmitWindowOffset = ble5HandlerState.scanInit.transmitWindowOffset; + } + Log_printf(RclCore, Log_VERBOSE, "Connection formed, transmit window offset %1d", transmitWindowOffset); + + /* Find the connect time and report it to the caller */ + uint32_t referenceTime = eventTime; + if (ble5HandlerState.scanInit.isExtAdv && !ble5HandlerState.scanInit.followAuxPtr) + { + /* + * The transmit window starts after the end of the packet containing the AUX_CONNECT_REQ, but evenTime corresponds to the time at which + * the AUX_CONNECT_RSP was received. Account for this by substracting the T_IFS. + */ + referenceTime -= BLE_T_IFS; + referenceTime += transmitWindowOffset * BLE_CONNECT_INT_UNIT; + /* For extended advertising, PHY needs to be considered when calculating the transmit window delay */ + referenceTime += ((ble5HandlerState.common.phyFeatures & BLE_PHY_FEATURE_PHY_MASK) == BLE_PHY_FEATURE_PHY_CODED) ? + BLE_TRANSMIT_WINDOW_DELAY_EXT_CODED : BLE_TRANSMIT_WINDOW_DELAY_EXT_UNCODED; + } + else + { + referenceTime += RCL_Handler_BLE5_findPacketDuration(ble5HandlerState.scanInit.advPktLen, ble5HandlerState.common.phyFeatures) + + BLE_T_IFS + RCL_Handler_BLE5_findPacketDuration(BLE_CONNECT_MSG_LEN, ble5HandlerState.common.phyFeatures) + + BLE_TRANSMIT_WINDOW_DELAY_LEGACY + transmitWindowOffset * BLE_CONNECT_INT_UNIT; + } + + if (ble5HandlerState.scanInit.dynamicWinOffset) + { + connectTime = RCL_Handler_BLE5_findConnectTime(initCmd->connectTime, referenceTime, ble5HandlerState.scanInit.connectInterval); + /* Check that the connect time is within the bounds expected; if not (due to timer drift), report a different connect time */ + if (connectTime > referenceTime + 2 * BLE_CONNECT_INT_UNIT) + { + Log_printf(RclCore, Log_WARNING, "Transmitted window offset did not match requested transmit time. Reporting a different connect time"); + connectTime = referenceTime + BLE_CONNECT_INT_UNIT / 2; + } + else + { + Log_printf(RclCore, Log_DEBUG, "Margins: %1d us and %1d us", (connectTime - referenceTime + 2)/4, (referenceTime + 2 * BLE_CONNECT_INT_UNIT - connectTime + 2)/4); + } + } + else + { + connectTime = referenceTime + BLE_CONNECT_INT_UNIT / 2; + } + initCmd->connectTime = connectTime; + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + + /* Only update backOff related variables for the extended usecase after an AUX_CONNECT_REQ has been sent */ + uint16_t chCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) & PBE_BLE5_RAM_AECFG_CHNL_M; + if (ble5HandlerState.scanInit.isExtAdv && chCfg == PBE_BLE5_RAM_AECFG_CHNL_SECONDARY) + { + RCL_Handler_BLE5_updateBackoffParams(ctx, endCause); + } + } + } + } + } + else + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (lrfEvents.opError != 0 && endStatus == RCL_CommandStatus_Finished) + { + endStatus = RCL_Handler_BLE5_findPbeErrorEndStatus(endCause); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else if (rclSchedulerState.hardStopInfo.apiStopEnabled && endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else if (rclSchedulerState.gracefulStopInfo.apiStopEnabled && endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else + { + /* No change of status */ + } + } + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (rclEvents.lastCmdDone != 0) + { + /* Write back backoff count */ + if (!ble5HandlerState.scanInit.initiator) + { + scanCmd->ctx->initialBackoff = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) + 1; /* Backoff definition in PBE is one less than in Bluetooth spec */ + } + if (ble5HandlerState.scanInit.initiator && ble5HandlerState.scanInit.isExtAdv) + { + initCmd->ctx->initialBackoff = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) + 1; /* Backoff definition in PBE is one less than in Bluetooth spec */ + } + updateStats = true; + } + if (updateStats) + { + RCL_Handler_BLE5_updateAdvScanInitStats((ble5HandlerState.scanInit.initiator) ? initCmd->stats : scanCmd->stats, + rclSchedulerState.actualStartTime); + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.rxBufferUpdate != 0) + { + ctx = (ble5HandlerState.scanInit.initiator) ? initCmd->ctx : scanCmd->ctx; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + if (rclEventsIn.handlerCmdUpdate != 0) + { + if (ble5HandlerState.scanInit.followAuxPtr && ble5HandlerState.scanInit.switchPhy) + { + /* PHY change concluded successfully. Proceed with the scanner restart */ + followAuxPtr = true; + } + else + { + followAuxPtr = false; + } + if (ble5HandlerState.common.updatableFilterList != NULL && ble5HandlerState.common.filterListUpdateIndex >= 0) + { + uint32_t index = (uint32_t) ble5HandlerState.common.filterListUpdateIndex; + uint32_t *targetPtr = (uint32_t *) (ble5HandlerState.scanInit.initiator ? (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2INFO0) : (volatile unsigned short*) (LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1INFO0)); + + RCL_Handler_BLE5_updateFilterListEntry(ble5HandlerState.common.updatableFilterList, + targetPtr, + ble5HandlerState.scanInit.filterListInvertMask, index); + ble5HandlerState.common.filterListUpdateIndex = -1; + } + } + if (followAuxPtr) + { + uint32_t maxAuxPtrWaitTime = (ble5HandlerState.scanInit.initiator) ? initCmd->maxAuxPtrWaitTime : scanCmd->maxAuxPtrWaitTime; + uint32_t auxOffsetUs = ble5HandlerState.common.auxPtrInfo.offsetUnits ? (ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_300_US) : + (ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_30_US); + + /* Switch to the channel indicated by the auxPtr */ + RCL_Ble5Channel nextChannel = (RCL_Ble5Channel) ble5HandlerState.common.auxPtrInfo.chIndex; + rfFreq = RCL_Handler_BLE5_findRfFreq(nextChannel); + + if ((maxAuxPtrWaitTime != 0) && (maxAuxPtrWaitTime < auxOffsetUs)) + { + cmd->status = RCL_CommandStatus_MaxAuxWaitTimeExceeded; + rclEvents.lastCmdDone = 1; + } + else if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + if (ble5HandlerState.scanInit.initiator) + { + connParams = initCmd->ctx->connParams; + if (initCmd->ctx->connParams != NULL) + { + /* Check received AuxPhy to determine if connection parameters need to be updated */ + if (ble5HandlerState.common.auxPtrInfo.auxPhy == BLE_PHY_FEATURE_PHY_2MBPS) + { + /* Retry TX FIFO and point to the correct AUX_CONNECT_REQ. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RETRY >> LRFDPBE_FCMD_DATA_S); + + /* Update parameters. Use position of Interval field as reference for other connection parameters */ + HWREGH_WRITE_LRF(ble5HandlerState.scanInit.intervalFifoPtr) = connParams->ble2M.interval; + HWREGH_WRITE_LRF(((uintptr_t) ble5HandlerState.scanInit.intervalFifoPtr) + (BLE_LATENCY_POS - BLE_INTERVAL_POS)) = connParams->ble2M.latency; + HWREGH_WRITE_LRF(((uintptr_t) ble5HandlerState.scanInit.intervalFifoPtr) + (BLE_TIMEOUT_POS - BLE_INTERVAL_POS)) = connParams->ble2M.timeout; + } + else if (ble5HandlerState.common.auxPtrInfo.auxPhy == BLE_PHY_FEATURE_PHY_CODED) + { + /* Retry TX FIFO and point to the correct AUX_CONNECT_REQ. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = (LRFDPBE_FCMD_DATA_TXFIFO_RETRY >> LRFDPBE_FCMD_DATA_S); + + /* Update parameters. Use position of Interval field as reference for other connection parameters */ + HWREGH_WRITE_LRF(ble5HandlerState.scanInit.intervalFifoPtr) = connParams->bleCoded.interval; + HWREGH_WRITE_LRF(((uintptr_t) ble5HandlerState.scanInit.intervalFifoPtr) + (BLE_LATENCY_POS - BLE_INTERVAL_POS)) = connParams->bleCoded.latency; + HWREGH_WRITE_LRF(((uintptr_t) ble5HandlerState.scanInit.intervalFifoPtr) + (BLE_TIMEOUT_POS - BLE_INTERVAL_POS)) = connParams->bleCoded.timeout; + } + else + { + /* No need to update connection parameters for LE 1M PHY */ + } + } + else + { + /* No change of the connection parameters regardless of the PHY */ + } + } + + /* Begin the start time calculation of the receive window by getting the time of the last sync plus the aux offset given in the AuxPtr */ + /* 32-bit access to also read LASTTIMESTAMPH */ + uint32_t startTime = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) - ble5HandlerState.common.timestampAdjust; + + /* Update timestamps for the next packet if there was been a PHY change */ + if (ble5HandlerState.scanInit.switchPhy) + { + RCL_Handler_BLE5_setPhy(rclSchedulerState.requestedPhyFeatures); + ble5HandlerState.scanInit.switchPhy = false; + } + + uint32_t offset = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? + ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_300_US : + ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_30_US); + startTime += offset; + + /* Use the local and remote clock accuracies to find the clock error contribution */ + uint16_t localClkAccuracy = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.scanInit.initiator ? + initCmd->ctx->localClockAccuracy : + scanCmd->ctx->localClockAccuracy); + uint16_t remoteClkAccuracy = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? + BLE_SCALED_CLK_ACCURACY_500PPM : + BLE_SCALED_CLK_ACCURACY_50PPM); + + /* Find clock error contribution. Add 1 us (4 systim units) to correct for rounding down. Also consider the sleep/active clock adjustments */ + uint16_t remoteClkError = (uint16_t)((((offset * remoteClkAccuracy) >> BLE_CLK_ACCURACY_SCALE_FACTOR)) + 4 + RCL_SCHEDULER_SYSTIM_US(2)); + uint16_t localClkError = (uint16_t)((((offset * localClkAccuracy) >> BLE_CLK_ACCURACY_SCALE_FACTOR)) + 4 + RCL_SCHEDULER_SYSTIM_US(16)); + + /* Calculate the needed window widening. Consider the allowed deviations for active clock accuracy and sleep clock accuracy */ + uint16_t windowWidening = remoteClkError + localClkError; + + /* Add some additional time to the window widening due to missing constants describing the Rx Start Overhead. See RCL-513. */ + startTime -= (windowWidening + RX_START_OVERHEAD); + + /* Begin the timeout calculation by considering that the end of receive window occurs one offset unit after startTime */ + uint16_t endTime = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? BLE_AUX_OFFSET_300_US : BLE_AUX_OFFSET_30_US); + uint16_t timeout = windowWidening + endTime + windowWidening; + +#ifdef DeviceFamily_CC27XX + startTime -= RCL_SCHEDULER_SYSTIM_US(100); + timeout += RCL_SCHEDULER_SYSTIM_US(200); +#endif + /* Set timeout by writing to FIRSTRXTIMEOUT. Consider the necessary Rx sync Overhead. See RCL-513. */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTRXTIMEOUT) = timeout + RCL_Handler_BLE5_findRxSyncOverhead(ble5HandlerState.common.phyFeatures); + + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + /* Enable radio */ + LRF_enable(); + + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(nextChannel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + + /* Inform the PBE that we have moved to a secondary channel */ + uint16_t aeCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) | PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ADV_ACCESS_ADDRESS ^ (whitenInit << 24); + } + + if (ble5HandlerState.scanInit.dynamicWinOffset) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINMOD) = RCL_BLE5_CONNECT_INT_SUB_DIV * ble5HandlerState.scanInit.connectInterval + RCL_BLE5_CONNECT_INT_SUB_DIV - 1; + } + + /* Set new start time */ + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setNewStartAbsTime(startTime, true); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + cmd->status = RCL_CommandStatus_Active; + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + Log_printf(RclCore, Log_VERBOSE, "Following AuxPointer on channel: %d", nextChannel); + LRF_waitForTopsmReady(); + + if (!ble5HandlerState.scanInit.initiator) + { + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_SCAN; + } + else + { + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_INITIATOR; + + if (ble5HandlerState.scanInit.dynamicWinOffset) + { + /* + * Calculate initial winOffset while radio is starting. Use the actual start time of the command as initial reference, + * and consider that the transmit window starts after the end of the packet containing the AUX_CONNECT_REQ. + */ + uint32_t referenceTime = rclSchedulerState.actualStartTime + + RCL_Handler_BLE5_findPacketDuration(BLE_CONNECT_MSG_LEN, ble5HandlerState.common.phyFeatures) + + 3 * RCL_BLE5_CONNECT_SUB_INT; + /* The transmitWindowDelay needs to take into account the type of PHY in use */ + referenceTime += ((ble5HandlerState.common.phyFeatures & BLE_PHY_FEATURE_PHY_MASK) == BLE_PHY_FEATURE_PHY_CODED) ? + BLE_TRANSMIT_WINDOW_DELAY_EXT_CODED : BLE_TRANSMIT_WINDOW_DELAY_EXT_UNCODED; + + /* + * Use the reference time and the requested connect time to calculate an appropriate value for the winOffset. + * The winOffset value is initially set to hit the next window start by considering the desired connect interval, + * but the PBE adjusts it based on the length of the window (WINMOD). + */ + uint32_t initialWinOffset = RCL_Handler_BLE5_prepareConnectTime(&initCmd->connectTime, referenceTime, + ble5HandlerState.scanInit.connectInterval); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WINOFFSET) = initialWinOffset; + } + } + + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateAdvScanInitStats((ble5HandlerState.scanInit.initiator) ? initCmd->stats : scanCmd->stats, + rclSchedulerState.actualStartTime); + + } + } + } + } + } + + if (rclEvents.lastCmdDone != 0) + { + ble5HandlerState.common.updatableFilterList = NULL; + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_periodicScan ======== + */ +RCL_Events RCL_Handler_BLE5_periodicScan(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBle5PeriodicScanner *perScanCmd = (RCL_CmdBle5PeriodicScanner *) cmd; + uint32_t rfFreq; + RCL_Events rclEvents = RCL_EventNone; + bool followAuxPtr = false; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_Ble5Channel channel; + RCL_Command_TxPower txPower; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = perScanCmd->ctx->accessAddress; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = perScanCmd->ctx->crcInit << 8; + + /* The initial First Rx Timeout depends on the relative gaceful stop time configured for the command */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTRXTIMEOUT) = 0; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + channel = perScanCmd->channel; + txPower = perScanCmd->txPower; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + else if (channel != BLE_ADV_CHAN_LO && channel != BLE_ADV_CHAN_MID && channel != BLE_ADV_CHAN_HI) + { + cmd->status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = RCL_Handler_BLE5_initAdvScanInitStats(perScanCmd->stats, + rclSchedulerState.actualStartTime); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + + /* Only accept non-connectable/non-scannable extended PDUs coming on a secondary channel */ + uint16_t aeCfg = PBE_BLE5_RAM_AECFG_EXTENDED_EN | PBE_BLE5_RAM_AECFG_ADVMODE0_ACCEPT | PBE_BLE5_RAM_AECFG_CHNL_SECONDARY; + + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = perScanCmd->ctx->accessAddress ^ (whitenInit << 24); + } + + /* Configure maximum packet length */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MAXLEN) = BLE_ADV_EXTENDED_MAX_PKT_LEN; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRM) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRH) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OWNADRTYPE) = 0; + + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&perScanCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RPAMODE) = 0; + + ble5HandlerState.common.filterListUpdateIndex = -1; + /* Make sure status is correctly initialized */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FLSTAT) = 0; + + /* Set filter list masks to duplicate address filtering: */ + /* Bit 1: Consider type bit */ + /* Bit 2: Consider duplicateIgn bit */ + /* Bit 15: Consider match bit (found by PBE) */ + /* Other bits are not checked */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL1MASK) = PBE_BLE5_RAM_FL1MASK_MATCH_M | + PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M | + PBE_BLE5_RAM_FL1MASK_TYPE_M; + ble5HandlerState.scanInit.filterListInvertMask = PBE_BLE5_RAM_FL1MASK_DUPLICATEIGN_M; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FL2MASK) = 0; + + /* Set passive scanner configuration. No scan requests are sent */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_SCANCFG) = 0; + + /* Set acceptance configuration */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_AECFG) = aeCfg; + + /* Set filter policy */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FILTPOLICY) = 0; + + if (status == RCL_CommandStatus_Active) + { + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + + Log_printf(RclCore, Log_VERBOSE, "Starting periodic scanner"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_SCAN; + + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + else + { + bool updateStats = false; + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + if(lrfEvents.rxOk && wordLength > 1) + { + uint32_t header = data32[1] >> 16; + uint32_t type = (header & BLE_PDU_TYPE_BM); + + if (type == BLE_PDU_ADV_EXTENDED) + { + /* Attempt to extract an AuxPtr from the received packet */ + RCL_Handler_BLE5_readAuxPtrFromRxBuffer(data32, &ble5HandlerState.common.auxPtrInfo); + if (ble5HandlerState.common.auxPtrInfo.auxPtrPresent) + { + ble5HandlerState.perScan.followAuxPtr = true; + } + else + { + ble5HandlerState.perScan.followAuxPtr = false; + } + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&perScanCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + else + { + rclEvents.lastCmdDone = 1; + cmd->status = RCL_CommandStatus_Error_RxBufferCorruption; + } + } + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + updateStats = true; + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + if (lrfEvents.opError == 0 && (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_RXERR || + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC)) + { + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK && ble5HandlerState.perScan.followAuxPtr) + { + /* Turn off LRF to allow new synth programming */ + LRF_disable(); + followAuxPtr = true; + } + else + { + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = RCL_CommandStatus_Finished; + } + } + else + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (lrfEvents.opError != 0 && endStatus == RCL_CommandStatus_Finished) + { + endStatus = RCL_Handler_BLE5_findPbeErrorEndStatus(endCause); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else if (rclSchedulerState.hardStopInfo.apiStopEnabled && endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else if (rclSchedulerState.gracefulStopInfo.apiStopEnabled && endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + followAuxPtr = false; + rclEvents.lastCmdDone = 1; + cmd->status = endStatus; + } + else + { + /* No change of status */ + } + } + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (rclEvents.lastCmdDone != 0) + { + updateStats = true; + } + if (updateStats) + { + RCL_Handler_BLE5_updateAdvScanInitStats(perScanCmd->stats, rclSchedulerState.actualStartTime); + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&perScanCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + if (followAuxPtr) + { + uint32_t maxAuxPtrWaitTime = perScanCmd->maxAuxPtrWaitTime; + uint32_t auxOffsetUs = ble5HandlerState.common.auxPtrInfo.offsetUnits ? (ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_300_US) : + (ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_30_US); + + /* Switch to the channel indicated by the auxPtr */ + RCL_Ble5Channel nextChannel = (RCL_Ble5Channel) ble5HandlerState.common.auxPtrInfo.chIndex; + rfFreq = RCL_Handler_BLE5_findRfFreq(nextChannel); + + if (maxAuxPtrWaitTime < auxOffsetUs) + { + cmd->status = RCL_CommandStatus_MaxAuxWaitTimeExceeded; + rclEvents.lastCmdDone = 1; + } + else if (rfFreq == 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Begin the start time calculation of the receive window by getting the time of the last sync plus the aux offset given in the AuxPtr */ + /* 32-bit access to also read LASTTIMESTAMPH */ + uint32_t startTime = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) - ble5HandlerState.common.timestampAdjust; + uint32_t offset = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? + ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_300_US : + ble5HandlerState.common.auxPtrInfo.auxOffset * BLE_AUX_OFFSET_30_US); + startTime += offset; + + /* Use the local and remote clock accuracies to find the clock error contribution */ + uint16_t localClkAccuracy = RCL_SCHEDULER_SYSTIM_US(perScanCmd->ctx->localClockAccuracy); + uint16_t remoteClkAccuracy = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? + BLE_SCALED_CLK_ACCURACY_500PPM : + BLE_SCALED_CLK_ACCURACY_50PPM); + + /* Find clock error contribution. Add 1 us (4 systim units) to correct for rounding down. Also consider the sleep/active clock adjustments */ + uint16_t remoteClkError = (uint16_t)((((offset * remoteClkAccuracy) >> BLE_CLK_ACCURACY_SCALE_FACTOR)) + 4 + RCL_SCHEDULER_SYSTIM_US(2)); + uint16_t localClkError = (uint16_t)((((offset * localClkAccuracy) >> BLE_CLK_ACCURACY_SCALE_FACTOR)) + 4 + RCL_SCHEDULER_SYSTIM_US(16)); + + /* Calculate the needed window widening. Consider the allowed deviations for active clock accuracy and sleep clock accuracy */ + uint16_t windowWidening = remoteClkError + localClkError; + + /* Add some additional time to the window widening due to missing constants describing the Rx Start Overhead. See RCL-513. */ + startTime -= (windowWidening + RX_START_OVERHEAD); + + /* Begin the timeout calculation by considering that the end of receive window occurs one offset unit after startTime */ + uint16_t endTime = RCL_SCHEDULER_SYSTIM_US(ble5HandlerState.common.auxPtrInfo.offsetUnits ? BLE_AUX_OFFSET_300_US : BLE_AUX_OFFSET_30_US); + uint16_t timeout = windowWidening + endTime + windowWidening; + +#ifdef DeviceFamily_CC27XX + startTime -= RCL_SCHEDULER_SYSTIM_US(100); + timeout += RCL_SCHEDULER_SYSTIM_US(200); +#endif + /* Set timeout by writing to FIRSTRXTIMEOUT. Consider the necessary Rx sync Overhead. See RCL-513. */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTRXTIMEOUT) = timeout + RCL_Handler_BLE5_findRxSyncOverhead(ble5HandlerState.common.phyFeatures); + + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + /* Enable radio */ + LRF_enable(); + + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(nextChannel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = perScanCmd->ctx->accessAddress ^ (whitenInit << 24); + } + + /* Set new start time */ + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setNewStartAbsTime(startTime, true); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + cmd->status = RCL_CommandStatus_Active; + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + Log_printf(RclCore, Log_VERBOSE, "Following AuxPointer on channel: %d", nextChannel); + LRF_waitForTopsmReady(); + + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_SCAN; + + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateAdvScanInitStats(perScanCmd->stats, rclSchedulerState.actualStartTime); + } + } + } + } + } + + if (rclEvents.lastCmdDone != 0) + { + ble5HandlerState.common.updatableFilterList = NULL; + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_conn ======== + */ +RCL_Events RCL_Handler_BLE5_conn(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + uint32_t rfFreq; + RCL_CmdBle5Connection *connCmd = (RCL_CmdBle5Connection *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + uint32_t startDelay = 0; + RCL_CtxConnection *ctx = connCmd->ctx; + uint32_t crcInit = ctx->crcInit; + uint32_t accessAddress = ctx->accessAddress; + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress; + + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = crcInit << 8; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MDCFG) = 0; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_SEQSTAT) = ctx->seqStat; + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + rfFreq = RCL_Handler_BLE5_findRfFreq(connCmd->channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(connCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, !ctx->isPeripheral); + + /* Enable radio */ + LRF_enable(); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = 0; + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(connCmd->channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress ^ (whitenInit << 24); + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MAXLEN) = BLE_MAX_PKT_LEN; + /* Set up timers */ + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = RCL_Handler_BLE5_initConnStats(connCmd->stats, rclSchedulerState.actualStartTime); + if (cmd->scheduling == RCL_Schedule_AbsTime) + { + startDelay = rclSchedulerState.actualStartTime - cmd->timing.absStartTime; + } + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&connCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* Enter TX payload - maximum two packets in the beginning */ + bool retransPossible = ctx->isPeripheral && + ((ctx->seqStat & (PBE_BLE5_RAM_SEQSTAT_EMPTY_M | PBE_BLE5_RAM_SEQSTAT_FIRSTPKT_M)) == 0); + ble5HandlerState.common.txBufferInfo = (RCL_TxBufferInfo) { .isConnBuffer = true }; + RCL_Handler_BLE5_updateTxBuffers(&ctx->txBuffers, 2, + &ble5HandlerState.common.txBufferInfo, retransPossible); + + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxEmpty.value | + LRF_EventRxBufFull.value | LRF_EventTxDone.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + if (ctx->isPeripheral) + { + int32_t relRxTimeoutTime = connCmd->relRxTimeoutTime; + if (relRxTimeoutTime != 0) + { + relRxTimeoutTime -= startDelay; + + if (relRxTimeoutTime <= 0) + { + status = RCL_CommandStatus_RxTimeout; + } + } + + if (status == RCL_CommandStatus_Active) + { + /* Set timeout */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTRXTIMEOUT) = relRxTimeoutTime; + + Log_printf(RclCore, Log_VERBOSE, "Starting peripheral"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_PERIPHERAL; + } + } + else + { + Log_printf(RclCore, Log_VERBOSE, "Starting central"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_CENTRAL; + } + if (status == RCL_CommandStatus_Active) + { + /* Insert any more TX payload that can fit */ + RCL_Handler_BLE5_updateTxBuffers(&ctx->txBuffers, + UINT32_MAX, + &ble5HandlerState.common.txBufferInfo, + false); + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + else + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxEmpty != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&connCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateConnStats(connCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (lrfEvents.txDone != 0) + { + /* Free up finished tx buffers */ + uint32_t bytesWritten = ble5HandlerState.common.txFifoSz - LRF_getTxFifoWritable(); + uint32_t numBytes = ble5HandlerState.common.txBufferInfo.numBytes; + int32_t numBuffers = ble5HandlerState.common.txBufferInfo.numBuffers; + if (bytesWritten < numBytes) + { + RCL_Buffer_TxBuffer *txBuffer; + do + { + uint32_t entryBytes; + txBuffer = RCL_TxBuffer_get(&connCmd->ctx->txBuffers); + if (txBuffer == NULL) + { + /* Error */ + break; + } + txBuffer->state = RCL_BufferStateFinished; + numBuffers--; + entryBytes = RCL_Buffer_DataEntry_paddedLen(txBuffer->length); + numBytes -= entryBytes; + if (txBuffer == ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer) + { + ble5HandlerState.common.txBufferInfo.lastEnteredTxBuffer = NULL; + ble5HandlerState.common.txBufferInfo.lastTxHdr = NULL; + } + + } while (bytesWritten < numBytes); + + /* Check consistency */ + if (numBytes != bytesWritten || numBuffers < 0) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_TxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + } + else + { + ble5HandlerState.common.txBufferInfo.numBytes = numBytes; + ble5HandlerState.common.txBufferInfo.numBuffers = numBuffers; + rclEvents.txBufferFinished = 1; + } + /* Set flag to insert more data if possible */ + rclEventsIn.txBufferUpdate = 1; + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + RCL_CommandStatus endStatus; + connCmd->ctx->seqStat = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_SEQSTAT); + /* Disable radio */ + + rclEvents.lastCmdDone = 1; + endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + uint16_t pbeEndcause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + /* Check if we need to change status */ + if (lrfEvents.opError != 0) + { + endStatus = RCL_Handler_BLE5_findPbeErrorEndStatus(pbeEndcause); + } + else + { + if (pbeEndcause == PBE_COMMON_RAM_ENDCAUSE_STAT_RXTIMEOUT) + { + endStatus = RCL_CommandStatus_RxTimeout; + } + else if (pbeEndcause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + else if (pbeEndcause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC) + { + endStatus = RCL_CommandStatus_NoSync; + } + else if (pbeEndcause == PBE_COMMON_RAM_ENDCAUSE_STAT_RXERR) + { + endStatus = RCL_CommandStatus_RxErr; + } + else if (pbeEndcause == PBE_COMMON_RAM_ENDCAUSE_STAT_MAXNAK) + { + endStatus = RCL_CommandStatus_MaxNak; + } + else + { + /* No change of status */ + } + } + } + cmd->status = endStatus; + } + else + { + /* Other events need to be handled unconditionally */ + } + if (rclEvents.lastCmdDone != 0) + { + RCL_Handler_BLE5_updateConnStats(connCmd->stats, rclSchedulerState.actualStartTime); + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&connCmd->ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + if (rclEventsIn.txBufferUpdate != 0) + { + /* Insert any more TX payload that can fit */ + RCL_Handler_BLE5_updateTxBuffers(&connCmd->ctx->txBuffers, + UINT32_MAX, + &ble5HandlerState.common.txBufferInfo, + false); + rclEventsIn.txBufferUpdate = 0; + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_dtmTx ======== + */ +RCL_Events RCL_Handler_BLE5_dtmTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBle5DtmTx *txCmd = (RCL_CmdBle5DtmTx *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_Ble5Channel channel; + uint8_t byteVal; + uint32_t whitenPoly; + uint32_t whitenSeed; + uint32_t rfFreq; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = DTM_ACCESS_ADDRESS; + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = ADV_CRC_INIT; + /* Set PBE timer 1 prescaler to use 1 us ticks */ + uint16_t timPre = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TIMPRE); + ble5HandlerState.dtmTx.storedPbeTimPre = timPre; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_TIMPRE) = (timPre & ~LRFDPBE_TIMPRE_PRE1_M) | ((LRF_CLOCK_TICKS_PER_US - 1) << LRFDPBE_TIMPRE_PRE1_S); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_RFINTERVAL) = txCmd->periodUs; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXTARGET) = txCmd->numPackets; + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + channel = txCmd->channel; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enable radio */ + LRF_enable(); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = (PBE_BLE5_RAM_OPCFG_REPEAT_YES) | + (PBE_BLE5_RAM_OPCFG_TXPATTERN_NO) | + (PBE_BLE5_RAM_OPCFG_TXFCMD_RETRY) | + (PBE_BLE5_RAM_OPCFG_RFINTERVAL_EN); + + /* Initialize RF FIFOs */ + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* Prepare payload */ + switch (txCmd->pduHeader & 0x0F) + { + case BLE_DTM_PAYLOAD_TYPE_PRBS9: + byteVal = 0; + whitenPoly = RCL_HANDLER_BLE5_PRBS9_POLY; + whitenSeed = RCL_HANDLER_BLE5_PRBS9_INIT; + break; + case BLE_DTM_PAYLOAD_TYPE_11110000: + byteVal = 0x0F; /* 11110000... in transmission order */ + whitenPoly = 0; + whitenSeed = 0; + break; + case BLE_DTM_PAYLOAD_TYPE_10101010: + byteVal = 0x55; /* 10101010... in transmission order */ + whitenPoly = 0; + whitenSeed = 0; + break; + case BLE_DTM_PAYLOAD_TYPE_PRBS15: + byteVal = 0; + whitenPoly = RCL_HANDLER_BLE5_PRBS15_POLY; + whitenSeed = RCL_HANDLER_BLE5_PRBS15_INIT; + break; + case BLE_DTM_PAYLOAD_TYPE_11111111: + byteVal = 0xFF; /* All ones */ + whitenPoly = 0; + whitenSeed = 0; + break; + case BLE_DTM_PAYLOAD_TYPE_00000000: + byteVal = 0x00; /* All zeros */ + whitenPoly = 0; + whitenSeed = 0; + break; + case BLE_DTM_PAYLOAD_TYPE_00001111: + byteVal = 0xF0; /* 00001111... in transmission order */ + whitenPoly = 0; + whitenSeed = 0; + break; + case BLE_DTM_PAYLOAD_TYPE_01010101: + byteVal = 0xAA; /* 01010101... in transmission order */ + whitenPoly = 0; + whitenSeed = 0; + break; + default: + status = RCL_CommandStatus_Error_Param; + whitenSeed = 0; + whitenPoly = 0; + byteVal = 0; + break; + } + if (status == RCL_CommandStatus_Active) + { + /* Enter length field and padding length in FIFO */ + HWREG_WRITE_LRF(LRFDTXF_BASE + LRFDTXF_O_TXD) = (txCmd->pduLength + 6) | (3 << 16); + /* Enter header in FIFO */ + HWREG_WRITE_LRF(LRFDTXF_BASE + LRFDTXF_O_TXD) = (txCmd->pduLength << 24) | (txCmd->pduHeader << 16); + + if (whitenSeed == 0) + { + uint32_t txWord = byteVal | (byteVal << 8) | (byteVal << 16) | (byteVal << 24); + for (int i = 0; i < RCL_Buffer_bytesToWords(txCmd->pduLength); i++) + { + HWREG_WRITE_LRF(LRFDTXF_BASE + LRFDTXF_O_TXD) = txWord; + } + } + else + { + /* Re-use PBE whitener for generating PRBS payload */ + /* Save existing polynomial, which is part of the setup */ + uint32_t whitenPolySave = HWREG_READ_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0); + /* Configure stand-alone whitening in PRBS0 of the PHA */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_PHACFG) = (LRFDPBE_PHACFG_MODE0_WHITE) | + (LRFDPBE_PHACFG_MODE1_INDEP); + /* Set the polynomial of the configured PRBS sequence */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = whitenPoly; + /* Seed the PRBS */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_LFSR0BR) = whitenSeed; + /* Set byte accesses */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_LFSR0N) = 7; + /* Write the configured byte value into the whitener for the first byte */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_LFSR0INL) = byteVal; + for (int i = 0; i < RCL_Buffer_bytesToWords(txCmd->pduLength); i++) + { + /* Initialize combined 4-byte word */ + uint32_t txWord = 0; + for (int j = 0; j < 4; j++) + { + /* Wait for PHA to be done whiteneing the byte */ + while ((HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_PHASTA) & LRFDPBE_PHASTA_BUSY_M) != 0) + {} + /* Read whitened byte */ + uint8_t txByte = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_PHAOUT0); + /* Enter next byte */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_LFSR0INL) = byteVal; + /* Insert byte into word */ + txWord |= txByte << (j * 8); + } + /* Write word to TX FIFO. If the packet length does not divide 4, there will be some extra non-zero bytes, + but they will be ignored by the radio, making the transmitted packet correct */ + HWREG_WRITE_LRF(LRFDTXF_BASE + LRFDTXF_O_TXD) = txWord; + } + /* Restore whitener polynomial */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = whitenPolySave; + } + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = 0; + if (ble5HandlerState.common.accessAddressModification) + { + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = DTM_ACCESS_ADDRESS ^ (whitenInit << 24); + } + Log_printf(RclCore, Log_VERBOSE, "Starting DTM TX"); + LRF_waitForTopsmReady(); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_TXRAW; + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + Log_printf(RclCore, Log_VERBOSE, "DTM TX started"); + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + Log_printf(RclCore, Log_VERBOSE, "TX raw done"); + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished && lrfEvents.opError != 0) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE) == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + /* Restore PBE timer 1 prescaler */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_TIMPRE) = ble5HandlerState.dtmTx.storedPbeTimPre; + } + return rclEvents; +} + + +/* + * ======== RCL_Handler_BLE5_genericRx ======== + */ +RCL_Events RCL_Handler_BLE5_genericRx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBle5GenericRx *rxCmd = (RCL_CmdBle5GenericRx *) cmd; + uint32_t rfFreq; + RCL_Events rclEvents = RCL_EventNone; + RCL_CtxGenericRx *ctx = rxCmd->ctx; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_Ble5Channel channel; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + uint32_t crcInit = ctx->crcInit; + uint32_t accessAddress = ctx->accessAddress; + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress; + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = crcInit << 8; + + ble5HandlerState.common.fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_EXTRABYTES) = RCL_Handler_BLE5_findNumExtraBytes(ble5HandlerState.common.fifoCfg); + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + channel = rxCmd->channel; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + /* Initialize counters */ + ble5HandlerState.common.activeUpdate = RCL_Handler_BLE5_initGenericRxStats(rxCmd->stats, + rclSchedulerState.actualStartTime); + + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress ^ (whitenInit << 24); + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_MAXLEN) = ctx->maxPktLen; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = ctx->config.repeated << PBE_BLE5_RAM_OPCFG_REPEAT_S; + + if (ctx->config.disableSync != 0) + { + uint16_t demc1be0 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE0); + uint16_t demc1be1 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1); + uint16_t demc1be2 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2); +#ifdef DeviceFamily_CC27XX + uint16_t demc1be12 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12); +#endif + ble5HandlerState.genericRx.restoreThresh = true; + ble5HandlerState.genericRx.demc1be0 = demc1be0; + ble5HandlerState.genericRx.demc1be1 = demc1be1; + ble5HandlerState.genericRx.demc1be2 = demc1be2; +#ifdef DeviceFamily_CC27XX + ble5HandlerState.genericRx.demc1be12 = demc1be12; +#endif + demc1be0 |= LRFDMDM_DEMC1BE0_MASKA_M | LRFDMDM_DEMC1BE0_MASKB_M; + demc1be1 = (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDA_S) | (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDB_S); + demc1be2 = (demc1be2 & ~LRFDMDM_DEMC1BE2_THRESHOLDC_M) | (0x7F << LRFDMDM_DEMC1BE2_THRESHOLDC_S); +#ifdef DeviceFamily_CC27XX + demc1be12 = (demc1be12 & ~LRFDMDM_DEMC1BE12_THRESHOLDG_M) | (0x7F << LRFDMDM_DEMC1BE12_THRESHOLDG_S); +#endif + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE0) = demc1be0; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = demc1be2; +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12) = demc1be12; +#endif + } + else + { + ble5HandlerState.genericRx.restoreThresh = false; + } + + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + ble5HandlerState.common.rxFifoSz = LRF_prepareRxFifo(); + ble5HandlerState.common.curBuffer = NULL; + if (ctx->config.discardRxPackets == 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + else + { + /* Set FIFO size to maximum */ + LRF_setRxFifoEffSz(ble5HandlerState.common.rxFifoSz); + } + + if (status == RCL_CommandStatus_Active) + { + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_BLE5_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxIgnored.value | + LRF_EventRxNok.value | LRF_EventRxBufFull.value, + fifoCfg, ble5HandlerState.common.activeUpdate)); + + Log_printf(RclCore, Log_VERBOSE, "Starting generic RX"); + LRF_waitForTopsmReady(); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_RXRAW; + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + else + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + if (ctx->config.discardRxPackets == 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(ble5HandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ble5HandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + ble5HandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_Handler_BLE5_commitPacket(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + } + else + { + LRF_discardRxFifoWords(wordLength); + } + } + } + if (ble5HandlerState.common.activeUpdate) + { + RCL_Handler_BLE5_updateGenericRxStats(rxCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (rclEventsIn.timerStart != 0) + { + Log_printf(RclCore, Log_VERBOSE, "Generic RX started"); + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + /* Disable radio */ + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + if (lrfEvents.opError != 0 && endStatus == RCL_CommandStatus_Finished) + { + endStatus = RCL_Handler_BLE5_findPbeErrorEndStatus(endCause); + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + else + { + /* No change of status */ + } + cmd->status = endStatus; + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (rclEvents.lastCmdDone != 0) + { + RCL_Handler_BLE5_updateGenericRxStats(rxCmd->stats, rclSchedulerState.actualStartTime); + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if ( rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_BLE5_updateRxCurBufferAndFifo(&ctx->rxBuffers); + rclEventsIn.rxBufferUpdate = 0; + } + } + if (rclEvents.lastCmdDone != 0) + { + if (ble5HandlerState.genericRx.restoreThresh) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE0) = ble5HandlerState.genericRx.demc1be0; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = ble5HandlerState.genericRx.demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = ble5HandlerState.genericRx.demc1be2; +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12) = ble5HandlerState.genericRx.demc1be12; +#endif + } + + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_BLE5_genericTx ======== + */ +RCL_Events RCL_Handler_BLE5_genericTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + uint32_t rfFreq; + RCL_CmdBle5GenericTx *txCmd = (RCL_CmdBle5GenericTx *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + RCL_Ble5Channel channel; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + RCL_CtxGenericTx *ctx = txCmd->ctx; + uint32_t crcInit = ctx->crcInit; + uint32_t accessAddress = ctx->accessAddress; + + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress; + /* 32-bit access to also write CRCINITH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_CRCINITL) = crcInit << 8; + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + channel = txCmd->channel; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enable radio */ + LRF_enable(); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = PBE_BLE5_RAM_OPCFG_TXFCMD_DEALLOC; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXTARGET) = 0; + + /* Initialize RF FIFOs */ + ble5HandlerState.common.txFifoSz = LRF_prepareTxFifo(); + + /* Enter payload */ + uint32_t nBuffer = RCL_Handler_BLE5_updateTxBuffers(&txCmd->ctx->txBuffers, 1, NULL, false); + if (nBuffer == 0) + { + status = RCL_CommandStatus_Error_MissingTxBuffer; + } + else + { + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (ble5HandlerState.common.accessAddressModification) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = accessAddress ^ (whitenInit << 24); + } + Log_printf(RclCore, Log_VERBOSE, "Starting generic TX"); + LRF_waitForTopsmReady(); + /* Post cmd */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_TXRAW; + } + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + Log_printf(RclCore, Log_VERBOSE, "TX raw done"); + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished && lrfEvents.opError != 0) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + /* Pop transmitted packet */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&txCmd->ctx->txBuffers); + if (txBuffer != NULL) + { + txBuffer->state = RCL_BufferStateFinished; + } + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_Ble5_txTest ======== + */ +RCL_Events RCL_Handler_Ble5_txTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBle5TxTest *txCmd = (RCL_CmdBle5TxTest *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + ble5HandlerState.txTest.restoreSelector = RCL_HANDLER_BLE5_RESTORE_NONE; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_OPCFG) = PBE_BLE5_RAM_OPCFG_TXPATTERN_M; + + /* Default end status */ + ble5HandlerState.common.endStatus = RCL_CommandStatus_Finished; + + RCL_Ble5Channel channel = txCmd->channel; + + RCL_CommandStatus status = RCL_Handler_BLE5_setPhy(cmd->phyFeatures); + uint32_t rfFreq = RCL_Handler_BLE5_findRfFreq(channel); + if (rfFreq == 0) + { + status = RCL_CommandStatus_Error_Param; + } + else if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + status = RCL_CommandStatus_Error_Param; + } + + if (status == RCL_CommandStatus_Active) + { + /* Program frequency word */ + LRF_programFrequency(rfFreq, false); + + /* Enter configuration */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_PATTERN) = txCmd->txWord; + if (txCmd->config.sendCw != 0) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) | LRFDMDM_MODCTRL_TONEINSERT_M; + ble5HandlerState.txTest.restoreSelector = RCL_HANDLER_BLE5_RESTORE_MODCTRL; + } + else + { + uint32_t whitenMode = txCmd->config.whitenMode; + /* Configure whitening */ + /* Use pseudo-random sync word (not necessarily matching selected PRBS) */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_HANDLER_BLE5_PRBS_SYNC; + if (whitenMode == RCL_CMD_BLE5_WH_MODE_DEFAULT) + { + uint16_t whitenInit = RCL_Handler_BLE5_findWhitenInit(txCmd->channel); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = whitenInit; + if (whitenInit == 0) + { + /* Use pattern as sync word */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = txCmd->txWord | (txCmd->txWord << 16); + } + } + else + { + ble5HandlerState.txTest.restoreSelector = RCL_HANDLER_BLE5_RESTORE_WHITEN_POLY; + ble5HandlerState.txTest.storedWhitenPoly = HWREG_READ_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0); + if (whitenMode == RCL_CMD_BLE5_WH_MODE_PRBS9) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = RCL_HANDLER_BLE5_PRBS9_POLY; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = RCL_HANDLER_BLE5_PRBS9_INIT; + } + else if (whitenMode == RCL_CMD_BLE5_WH_MODE_PRBS15) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = RCL_HANDLER_BLE5_PRBS15_POLY; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = RCL_HANDLER_BLE5_PRBS15_INIT; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = RCL_HANDLER_BLE5_PRBS32_POLY; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_WHITEINIT) = RCL_HANDLER_BLE5_PRBS32_INIT; + } + } + } + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + status = startTimeStatus; + } + else + { + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting BLE5 infinite TX"); + + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE5_REGDEF_API_OP_TXRAW; + } + } + /* Set status */ + cmd->status = status; + if (status >= RCL_CommandStatus_Finished) + { + rclEvents.lastCmdDone = 1; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + cmd->status = ble5HandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = ble5HandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE5_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + if ((ble5HandlerState.txTest.restoreSelector & RCL_HANDLER_BLE5_RESTORE_MODCTRL) != 0) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) & (~LRFDMDM_MODCTRL_TONEINSERT_M); + } + if ((ble5HandlerState.txTest.restoreSelector & RCL_HANDLER_BLE5_RESTORE_WHITEN_POLY) != 0) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = ble5HandlerState.txTest.storedWhitenPoly; + } + LRF_disable(); + LRF_disableSynthRefsys(); + } + + return rclEvents; +} + +/* + * ======== RCL_BLE5_updateFilterList ======== + */ +RCL_BLE5_FilterListUpdateResult RCL_BLE5_updateFilterList(const RCL_FL_Entry *newEntry, RCL_FilterList *filterList, uint32_t index) +{ + if (filterList == NULL) + { + return RCL_BLE5_FilterListUpdateIndexError; + } + else if (index >= filterList->numEntries || index >= PBE_NUM_FILTER_ENTRIES) + { + return RCL_BLE5_FilterListUpdateIndexError; + } + else + { + /* Run in protected region to avoid race conditions */ + uintptr_t key = HwiP_disable(); + /* Insert updated entry */ + filterList->entries[index] = *newEntry; + /* Check if handler should be notified */ + if (ble5HandlerState.common.updatableFilterList == filterList) + { + /* Set index */ + ble5HandlerState.common.filterListUpdateIndex = index; + /* Send event to running command */ + RCL_Scheduler_postEvent(rclSchedulerState.currCmd, RCL_EventHandlerCmdUpdate); + } + HwiP_restore(key); + + return RCL_BLE5_FilterListUpdateOk; + } +} + +/* + * ======== RCL_BLE5_setDefaultRfFrequency ======== + */ +void RCL_BLE5_setDefaultRfFrequency(uint32_t rfFrequency) +{ + ble5HandlerState.common.defaultRfFrequency = rfFrequency; +} + +/* + * ======== RCL_BLE5_getRxStatus ======== + */ +RCL_Ble5_RxPktStatus RCL_BLE5_getRxStatus(const RCL_Buffer_DataEntry *rxEntry) +{ + uint16_t fifoCfg = ble5HandlerState.common.fifoCfg; + + if ((fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M) != 0) + { + /* Find number of bytes in status and the appended bytes after that */ + uint32_t positionFromEnd = RCL_Handler_BLE5_findNumExtraBytes(fifoCfg & + (PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M | + PBE_BLE5_RAM_FIFOCFG_APPENDLQI_M | + PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_M | + PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M | + PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M)); + int32_t offset = rxEntry->length - sizeof(rxEntry->numPad) - sizeof(rxEntry->pad0) - positionFromEnd; + + if (offset < 0) + { + return (RCL_Ble5_RxPktStatus) {.value = RCL_BLE5_RX_PKT_STATUS_INVALID}; + } + else + { + const RCL_Ble5_RxPktStatus *statusPtr = (const RCL_Ble5_RxPktStatus *) (rxEntry->data + offset); + + return *statusPtr; + } + } + else + { + return (RCL_Ble5_RxPktStatus) {.value = RCL_BLE5_RX_PKT_STATUS_INVALID}; + } +} + +/* + * ======== RCL_BLE5_getRxRssi ======== + */ +int8_t RCL_BLE5_getRxRssi(const RCL_Buffer_DataEntry *rxEntry) +{ + uint16_t fifoCfg = ble5HandlerState.common.fifoCfg; + + if ((fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M) != 0) + { + /* Find number of bytes in RSSI and the appended bytes after that */ + uint32_t positionFromEnd = RCL_Handler_BLE5_findNumExtraBytes(fifoCfg & + (PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M | + PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M)); + int32_t offset = rxEntry->length - sizeof(rxEntry->numPad) - sizeof(rxEntry->pad0) - positionFromEnd; + + if (offset < 0) + { + return LRF_RSSI_INVALID; + } + else + { + const int8_t *rssiPtr = (const int8_t *) (rxEntry->data + offset); + + return *rssiPtr; + } + } + else + { + return LRF_RSSI_INVALID; + } +} + +/* + * ======== RCL_BLE5_getRxTimestamp ======== + */ +uint32_t RCL_BLE5_getRxTimestamp(const RCL_Buffer_DataEntry *rxEntry) +{ + uint16_t fifoCfg = ble5HandlerState.common.fifoCfg; + + if ((fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M) != 0) + { + uint32_t timestamp; + /* If status not appended; assume 1 Mbps */ + uint32_t timestampAdjust = TIMESTAMP_ADJUST_1MBPS; + int32_t offset = (rxEntry->length - sizeof(rxEntry->numPad) - sizeof(rxEntry->pad0) - sizeof(timestamp)); + if (offset < 0) + { + return 0; + } + else + { + const uint8_t *dataPtr = rxEntry->data + offset; + timestamp = dataPtr[0] | (dataPtr[1] << 8) | (dataPtr[2] << 16) | (dataPtr[3] << 24); + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M) + { + /* Find number of bytes in status and the appended bytes between status and timesptamp */ + uint32_t positionFromTimestamp = RCL_Handler_BLE5_findNumExtraBytes(fifoCfg & + (PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M | + PBE_BLE5_RAM_FIFOCFG_APPENDLQI_M | + PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_M | + PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M)); + offset -= positionFromTimestamp; + if (offset < 0) + { + return 0; + } + else + { + const RCL_Ble5_RxPktStatus *statusPtr = (const RCL_Ble5_RxPktStatus *) (rxEntry->data + offset); + switch (statusPtr->phy) + { + case RCL_Ble5_RxPhy1Mbps: + default: + timestampAdjust = TIMESTAMP_ADJUST_1MBPS; + break; + case RCL_Ble5_RxPhy2Mbps: + timestampAdjust = TIMESTAMP_ADJUST_2MBPS; + break; + case RCL_Ble5_RxPhyCodedS8: + case RCL_Ble5_RxPhyCodedS2: + timestampAdjust = TIMESTAMP_ADJUST_CODED; + break; + } + } + } + } + return timestamp - timestampAdjust; + } + else + { + return 0; + } +} + +/* + * ======== RCL_BLE5_getAuxAdvStartTimeDelta ======== + */ +uint32_t RCL_BLE5_getAuxAdvStartTimeDelta(uint16_t phyFeatures, uint8_t chMap, uint8_t advPayloadLen) +{ + uint8_t numPrimaryChPackets = (chMap & 1) + ((chMap >> 1) & 1) + ((chMap >> 2) & 1); + uint32_t advPayloadLenInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(RCL_Handler_BLE5_findPacketDuration(advPayloadLen, phyFeatures), BLE_AUX_OFFSET_30_US); + + return (RCL_SCHEDULER_SYSTIM_US((advPayloadLenInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US) * numPrimaryChPackets); +} + +/* + * ======== RCL_BLE5_setAccessAddressModification ======== + */ +/* This function should be secret, so no prototype is given in the .h file */ +void RCL_BLE5_setAccessAddressModification(bool enable) +{ + ble5HandlerState.common.accessAddressModification = enable; +} + +/* + * ======== RCL_Handler_BLE5_random ======== + */ +__attribute__((weak)) uint32_t RCL_Handler_BLE5_getRandomNumber(void) +{ + return Random_getNumber(); +} + +/* + * ======== RCL_Handler_BLE5_updateRxCurBufferAndFifo ======== + */ +static void RCL_Handler_BLE5_updateRxCurBufferAndFifo(List_List *rxBuffers) +{ + RCL_MultiBuffer *curBuffer = ble5HandlerState.common.curBuffer; + + if (curBuffer == NULL) + { + curBuffer = RCL_MultiBuffer_findFirstWritableBuffer((RCL_MultiBuffer *)rxBuffers->head); + } + ble5HandlerState.common.curBuffer = curBuffer; + + uint32_t rxSpace = + RCL_MultiBuffer_findAvailableRxSpace(curBuffer); + + LRF_setRxFifoEffSz(rxSpace); +} + +/* + * ======== RCL_Handler_BLE5_findWhitenInit ======== + */ +static uint16_t RCL_Handler_BLE5_findWhitenInit(RCL_Ble5Channel channel) +{ + uint16_t whitenInit; + + if ((channel & BLE_CUSTOM_FREQ_BM) == 0) + { + if (channel < BLE_PHY_CHAN_MIN) + { + /* Standard channel - set bit as BLE standard requires */ + whitenInit = channel | 0x40; + } + else + { + /* PHY channel - no whitening */ + whitenInit = 0; + } + } + else + { + /* Custom channel - use remaining bits as whitening initialization */ + whitenInit = channel & ~BLE_CUSTOM_FREQ_BM; + } + return whitenInit; +} + +/* + * ======== RCL_Handler_BLE5_findRfFreq ======== + */ +static uint32_t RCL_Handler_BLE5_findRfFreq(RCL_Ble5Channel channel) +{ + uint32_t rfFreq; + + ble5HandlerState.common.channel = channel; + if (channel <= BLE_DATA_CHAN_MAX) + { + /* Data channel */ + rfFreq = channel * BLE_CHAN_SPACE + BLE_DATA_CHAN_BASE; + if (rfFreq >= BLE_ADV_CHAN_MID_FREQ) + { + rfFreq += BLE_CHAN_SPACE; + } + } + else if (channel == BLE_ADV_CHAN_LO) + { + rfFreq = BLE_ADV_CHAN_LO_FREQ; + } + else if (channel == BLE_ADV_CHAN_MID) + { + rfFreq = BLE_ADV_CHAN_MID_FREQ; + } + else if (channel == BLE_ADV_CHAN_HI) + { + rfFreq = BLE_ADV_CHAN_HI_FREQ; + } + else if (channel >= BLE_PHY_CHAN_MIN && channel <= BLE_PHY_CHAN_MAX) + { + rfFreq = BLE_ADV_CHAN_LO_FREQ + ((channel - BLE_PHY_CHAN_MIN) * BLE_CHAN_SPACE); + } + else if ((channel & BLE_CUSTOM_FREQ_BM) != 0) + { + rfFreq = ble5HandlerState.common.defaultRfFrequency; + } + else + { + /* error */ + rfFreq = 0; + } + + return rfFreq; +} + +/* + * ======== RCL_Handler_BLE5_findAdvChannel ======== + */ +static RCL_Ble5Channel RCL_Handler_BLE5_findAdvChannel(uint32_t advMap, uint32_t order) +{ + RCL_Ble5Channel channel; + if ((advMap & BLE_CUSTOM_FREQ_BM) != 0) + { + channel = advMap; + } + else + { + if (order >= 6) + { + /* Error, but handle */ + order = 0; + } + switch (advMap & 0x07) + { + case 1: + channel = 37; + break; + + case 2: + channel = 38; + break; + + case 3: + channel = ((order & 1) == 0) ? 37 : 38; + break; + + case 4: + channel = 39; + break; + + case 5: + channel = ((order & 1) == 0) ? 37 : 39; + break; + + case 6: + channel = ((order & 1) == 0) ? 38 : 39; + break; + + case 7: + channel = (order >> 1) + 37; + break; + + default: + channel = 37; /* Error, but handle */ + break; + } + } + + return channel; +} + +/* + * ======== RCL_Handler_BLE5_setPhy ======== + */ +static RCL_CommandStatus RCL_Handler_BLE5_setPhy(uint16_t phyFeatures) +{ + switch (phyFeatures & BLE_PHY_FEATURE_PHY_MASK) + { + case BLE_PHY_FEATURE_PHY_1MBPS: + ble5HandlerState.common.timestampAdjust = TIMESTAMP_ADJUST_1MBPS; + break; + + case BLE_PHY_FEATURE_PHY_2MBPS: + ble5HandlerState.common.timestampAdjust = TIMESTAMP_ADJUST_2MBPS; + break; + + case BLE_PHY_FEATURE_PHY_CODED: + ble5HandlerState.common.timestampAdjust = TIMESTAMP_ADJUST_CODED; + break; + + default: + return RCL_CommandStatus_Error_Param; + } + + ble5HandlerState.common.phyFeatures = phyFeatures; + + return RCL_CommandStatus_Active; +} + +/* + * ======== RCL_Handler_BLE5_findPbeErrorEndStatus ======== + */ +static RCL_CommandStatus RCL_Handler_BLE5_findPbeErrorEndStatus(uint16_t pbeEndStatus) +{ + RCL_CommandStatus status; + switch (pbeEndStatus) + { + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_RXF: + status = RCL_CommandStatus_Error_RxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_TXF: + status = RCL_CommandStatus_Error_TxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_SYNTH: + Log_printf(RclCore, Log_ERROR, "Synth error. RFEMSGBOX = %04X", HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_MSGBOX)); + status = RCL_CommandStatus_Error_Synth; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP: + status = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_PAR: + status = RCL_CommandStatus_Error_Param; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_BADOP: + status = RCL_CommandStatus_Error_UnknownOp; + break; + default: + Log_printf(RclCore, Log_ERROR, "Unexpected error 0x%04X from PBE", pbeEndStatus); + status = RCL_CommandStatus_Error; + break; + } + return status; +} + +/* + * ======== RCL_Handler_BLE5_updateTxBuffers ======== + */ +static uint32_t RCL_Handler_BLE5_updateTxBuffers(List_List *txBuffers, + uint32_t maxBuffers, + RCL_TxBufferInfo *txBufferInfo, + bool retransPossible) +{ + uint32_t nWords = 0; + uint32_t nBuffers = 0; + RCL_Buffer_TxBuffer *nextTxBuffer; + RCL_Buffer_TxBuffer *txBuffer = NULL; + uint8_t *lastTxHdr = NULL; + bool isConnBuffer = false; + + if (txBufferInfo != NULL) + { + txBuffer = txBufferInfo->lastEnteredTxBuffer; + lastTxHdr = txBufferInfo->lastTxHdr; + isConnBuffer = txBufferInfo->isConnBuffer; + } + + if (txBuffer == NULL) + { + nextTxBuffer = RCL_TxBuffer_head(txBuffers); + } + else + { + nextTxBuffer = RCL_TxBuffer_next(txBuffer); + } + + if (nextTxBuffer != NULL && lastTxHdr != NULL && isConnBuffer) + { + /* Set MD = 1 */ + HWREGB_WRITE_LRF(lastTxHdr) = HWREGB_READ_LRF(lastTxHdr) | 0x10; + lastTxHdr = NULL; + } + + while (nextTxBuffer != NULL && nBuffers < maxBuffers) + { + + uint32_t length = nextTxBuffer->length; + /* Number of words including length field and end padding */ + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(length) / 4; + if (wordLength > LRF_getTxFifoWritable() / 4) + { + /* Packet will not fit */ + break; + } + txBuffer = nextTxBuffer; + txBuffer->state = RCL_BufferStateInUse; + + uint32_t *data32 = (uint32_t *) &(txBuffer->length); + + if (txBufferInfo != NULL && isConnBuffer) + { + lastTxHdr = LRF_getTxFifoWrAddr(txBuffer->numPad + 3); + } + /* TODO: See RCL-347 */ + /* Copy packet into FIFO */ + LRF_writeTxFifoWords(data32, wordLength); + nextTxBuffer = RCL_TxBuffer_next(txBuffer); + if (nextTxBuffer != NULL && lastTxHdr != NULL && isConnBuffer) + { + /* Set MD = 1 */ + HWREGB_WRITE_LRF(lastTxHdr) = HWREGB_READ_LRF(lastTxHdr) | 0x10; + lastTxHdr = NULL; + } + + nBuffers++; + nWords += wordLength; + /* If the first packet is a possible retransmission, move the read pointer behind it */ + if (retransPossible) + { + LRF_skipTxFifoWords(wordLength); + retransPossible = false; + } + } + + if (txBufferInfo != NULL) + { + txBufferInfo->lastEnteredTxBuffer = txBuffer; + txBufferInfo->lastTxHdr = lastTxHdr; + txBufferInfo->numBytes += nWords * 4; + txBufferInfo->numBuffers += nBuffers; + } + + return nBuffers; +} + +/* + * ======== RCL_Handler_BLE5_commitPacket ======== + */ +static void RCL_Handler_BLE5_commitPacket(RCL_MultiBuffer *curBuffer, uint32_t numBytes) +{ + /* Write channel into receive buffer entry - pad0 field is always part of the padding in BLE */ + RCL_Buffer_DataEntry *entry = (RCL_Buffer_DataEntry *) RCL_MultiBuffer_getNextWritableByte(curBuffer); + entry->pad0 = ble5HandlerState.common.channel; + + /* Commit packet */ + RCL_MultiBuffer_commitBytes(curBuffer, numBytes); +} + + +/* + * ======== RCL_Handler_BLE5_maskEventsByFifoConf ======== + */ +static uint32_t RCL_Handler_BLE5_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate) +{ + /* Remove events that will not give an entry in the RX FIFO, based on FIFOCFG, unless active update is used */ + if (!activeUpdate) + { + mask &= ~(((fifoConfVal & PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHIGN_M) ? LRF_EventRxIgnored.value : 0) | + ((fifoConfVal & PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHCRC_M) ? LRF_EventRxNok.value : 0) | + ((fifoConfVal & PBE_BLE5_RAM_FIFOCFG_AUTOFLUSHEMPTY_M) ? LRF_EventRxEmpty.value : 0) | + LRF_EventRxBufFull.value); + } + + return mask; +} + +/* + * ======== RCL_Handler_BLE5_updateAdvScanInitStats ======== + */ +static void RCL_Handler_BLE5_updateAdvScanInitStats(RCL_StatsAdvScanInit *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* 32-bit access to also read LASTTIMESTAMPH */ + uint32_t lastTimestamp = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL); + /* Check if a new value is found in the first timestamp */ + if (lastTimestamp == startTime) + { + stats->timestampValid = false; + } + else + { + stats->timestampValid = true; + stats->lastTimestamp = lastTimestamp - ble5HandlerState.common.timestampAdjust; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTRSSI); + stats->nRxNok = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK); + stats->nRxIgnored = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED); + stats->nRxFifoFull = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL); + stats->nRxOk = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK); + stats->nTx = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX); + } +} + +/* + * ======== RCL_Handler_BLE5_initAdvScanInitStats ======== + */ +static bool RCL_Handler_BLE5_initAdvScanInitStats(RCL_StatsAdvScanInit *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + /* 32-bit access to also write LASTTIMESTAMPH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) = startTime; + + stats->timestampValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED) = stats->nRxIgnored; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = stats->nRxFifoFull; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = stats->nRxOk; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX) = stats->nTx; + } + else + { + /* Reset existing values in PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX) = 0; + + stats->nRxNok = 0; + stats->nRxIgnored = 0; + stats->nRxFifoFull = 0; + stats->nRxOk = 0; + stats->nTx = 0; + } + return stats->config.activeUpdate; + } + else + { + return false; + } +} + +/* + * ======== RCL_Handler_BLE5_initConnStats ======== + */ +static bool RCL_Handler_BLE5_initConnStats(RCL_StatsConnection *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + /* 32-bit access to also write FIRSTTIMESTAMPH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTTIMESTAMPL) = startTime; + + stats->anchorValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXDONE) = stats->nTxDone; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXACK) = stats->nTxAck; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTLACK) = stats->nTxCtlAck; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTL) = stats->nTxCtl; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXRETRANS) = stats->nTxRetrans; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED) = stats->nRxIgnored; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXEMPTY) = stats->nRxEmpty; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = stats->nRxFifoFull; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = stats->nRxOk; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX) = stats->nTx; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTL) = stats->nRxCtl; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTLACK) = stats->nRxCtlAck; + } + else + { + /* Reset existing values in PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXDONE) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXACK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTLACK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXRETRANS) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXEMPTY) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTLACK) = 0; + + stats->nTxDone = 0; + stats->nTxAck = 0; + stats->nTxCtlAck = 0; + stats->nTxCtl = 0; + stats->nTxRetrans = 0; + stats->nRxNok = 0; + stats->nRxIgnored = 0; + stats->nRxEmpty = 0; + stats->nRxFifoFull = 0; + stats->nRxOk = 0; + stats->nTx = 0; + stats->nRxCtl = 0; + stats->nRxCtlAck = 0; + } + return stats->config.activeUpdate; + } + else + { + return false; + } +} + +/* + * ======== RCL_Handler_BLE5_updateConnStats ======== + */ +static void RCL_Handler_BLE5_updateConnStats(RCL_StatsConnection *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* 32-bit access to also read FIRSTTIMESTAMPH */ + uint32_t anchorPoint = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FIRSTTIMESTAMPL); + + /* Check if a new value is found in the first timestamp */ + if (anchorPoint == startTime) + { + stats->anchorValid = false; + } + else + { + stats->anchorValid = true; + stats->anchorPoint = anchorPoint - ble5HandlerState.common.timestampAdjust; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTRSSI); + stats->nTxDone = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXDONE); + stats->nTxAck = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXACK); + stats->nTxCtlAck = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTLACK); + stats->nTxCtl = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXCTL); + stats->nTxRetrans = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTXRETRANS); + stats->nRxNok = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK); + stats->nRxIgnored = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXIGNORED); + stats->nRxEmpty = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXEMPTY); + stats->nRxFifoFull = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL); + stats->nRxOk = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK); + stats->nTx = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NTX); + stats->nRxCtl = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTL); + stats->nRxCtlAck = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXCTLACK); + } +} + +/* + * ======== RCL_Handler_BLE5_initGenericRxStats ======== + */ +static bool RCL_Handler_BLE5_initGenericRxStats(RCL_StatsGenericRx *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + /* 32-bit access to also write LASTIMESTAMPH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL) = startTime; + + stats->timestampValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = stats->nRxFifoFull; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = stats->nRxOk; + } + else + { + /* Reset existing values in PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK) = 0; + + stats->nRxNok = 0; + stats->nRxFifoFull = 0; + stats->nRxOk = 0; + } + return stats->config.activeUpdate; + } + else + { + return false; + } +} + +/* + * ======== RCL_Handler_BLE5_updateGenericRxStats ======== + */ +static void RCL_Handler_BLE5_updateGenericRxStats(RCL_StatsGenericRx *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* 32-bit access to also read LASTTIMESTAMPH */ + uint32_t lastTimestamp = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTTIMESTAMPL); + + /* Check if a new value is found in the first timestamp */ + if (lastTimestamp == startTime) + { + stats->timestampValid = false; + } + else + { + stats->timestampValid = true; + stats->lastTimestamp = lastTimestamp - ble5HandlerState.common.timestampAdjust; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_LASTRSSI); + stats->nRxNok = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXNOK); + stats->nRxFifoFull = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXFIFOFULL); + stats->nRxOk = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_NRXOK); + } +} + +/* + * ======== RCL_Handler_BLE5_InitializeFilterList ======== + */ +static void RCL_Handler_BLE5_InitializeFilterList(RCL_FilterList *filterList, uint32_t *pbeFilterList, uint32_t invertMask) +{ + uint32_t numEntries; + uint32_t *targetPtr = pbeFilterList; + + if (filterList == NULL) + { + numEntries = 0; + } + else + { + uint32_t *sourcePtr; + + numEntries = filterList->numEntries; + sourcePtr = (uint32_t *) filterList->entries; + if (numEntries > PBE_NUM_FILTER_ENTRIES) + { + numEntries = PBE_NUM_FILTER_ENTRIES; + } + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + + /* Set info of unused entries to be ignored */ + for (int i = 0; i < numEntries; i++) + { + uint32_t entry0 = *sourcePtr++; + uint32_t entry1 = *sourcePtr++; + entry0 ^= invertMask; + *targetPtr++ = entry0; + *targetPtr++ = entry1; + } + } + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + + /* Set info of unused entries to be ignored */ + for (int i = numEntries; i < PBE_NUM_FILTER_ENTRIES; i++) + { + *targetPtr = invertMask; + targetPtr += 2; + } +} + +/* + * ======== RCL_Handler_BLE5_updateFilterListEntry ======== + */ +static void RCL_Handler_BLE5_updateFilterListEntry(RCL_FilterList *filterList, uint32_t *pbeFilterList, uint32_t invertMask, uint32_t index) +{ + if (filterList != NULL) + { + uint32_t *sourcePtr; + sourcePtr = (uint32_t *) &filterList->entries[index]; + volatile uint32_t *targetPtr = pbeFilterList + 2 * index; + + /* [RCL-515 WORKAROUND]: Protect the first memory write on BLE High PG1.x due to the hardware bugs */ +#ifdef DeviceFamily_CC27XX + ASM_4_NOPS(); +#endif //DeviceFamily_CC27XX + + /* Disable given entry and remove any match if set up */ + targetPtr[0] = invertMask; + /* TOPsm uses read-modify-write on this entry. Write several times to ensure it is not overwritten */ + targetPtr[0] = invertMask; + targetPtr[0] = invertMask; + targetPtr[0] = invertMask; + targetPtr[0] = invertMask; + + /* Read updated entry */ + uint32_t entry0 = sourcePtr[0]; + uint32_t entry1 = sourcePtr[1]; + /* Apply invert mask */ + entry0 ^= invertMask; + + uint32_t flstat = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FLSTAT); + /* Check if matching algorithm is running */ + if (flstat == 0) + { + /* If not, set match bit */ + entry0 |= PBE_BLE5_RAM_FL1MASK_MATCH_M; + } + + /* Write back, making sure to write info last */ + targetPtr[1] = entry1; + targetPtr[0] = entry0; + /* TOPsm uses read-modify-write on this entry. Write several times to ensure it is not overwritten */ + targetPtr[0] = entry0; + targetPtr[0] = entry0; + targetPtr[0] = entry0; + targetPtr[0] = entry0; + + /* Check if matching algorithm has started during this operation */ + if (flstat == 0 && HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_FLSTAT) != 0) + { + /* If so, clear match bit */ + entry0 &= ~PBE_BLE5_RAM_FL1MASK_MATCH_M; + /* Update entry so no match is found by error */ + targetPtr[0] = entry0; + /* TOPsm uses read-modify-write on this entry. Write several times to ensure it is not overwritten */ + targetPtr[0] = entry0; + targetPtr[0] = entry0; + targetPtr[0] = entry0; + targetPtr[0] = entry0; + } + } +} + +/* + * ======== RCL_Handler_BLE5_prepareConnectTime ======== + */ +static uint32_t RCL_Handler_BLE5_prepareConnectTime(uint32_t *connectTime, uint32_t referenceTime, uint32_t interval) +{ + uint32_t initialConnectTime = *connectTime; + uint32_t newConnectTime; + + /* Always allow 2 sub-periods extra to ensure that subIntervalStart is in the range [2, (2 * interval)] */ + newConnectTime = RCL_Handler_BLE5_findConnectTime(initialConnectTime, referenceTime + BLE_CONNECT_INT_UNIT, interval); + *connectTime = newConnectTime; + + uint32_t subIntervalStart = ((newConnectTime - referenceTime) / RCL_BLE5_CONNECT_SUB_INT); + Log_printf(RclCore, Log_DEBUG, "subIntervalStart = %d", subIntervalStart); + return subIntervalStart; +} + +/* + * ======== RCL_Handler_BLE5_findConnectTime ======== + */ +static uint32_t RCL_Handler_BLE5_findConnectTime(uint32_t initialConnectTime, uint32_t referenceTime, uint32_t interval) +{ + uint32_t connectTime; + uint32_t timeDiff = initialConnectTime - referenceTime; + if (timeDiff < 0x80000000) + { + /* initialConnectTime >= referenceTime */ + uint32_t intervalAdjust = timeDiff / (interval * BLE_CONNECT_INT_UNIT); + connectTime = initialConnectTime - intervalAdjust * (interval * BLE_CONNECT_INT_UNIT); + } + else + { + /* Result was negative; turn it around */ + timeDiff = referenceTime - initialConnectTime; + uint32_t intervalAdjust = (timeDiff + (interval * BLE_CONNECT_INT_UNIT) - 1) / (interval * BLE_CONNECT_INT_UNIT); + connectTime = initialConnectTime + intervalAdjust * (interval * BLE_CONNECT_INT_UNIT); + } + Log_printf(RclCore, Log_DEBUG, "referenceTime = 0x%08X, connectTime = 0x%08X", referenceTime, connectTime); + + return connectTime; +} + +/* + * ======== RCL_Handler_BLE5_findPacketDuration ======== + */ +static uint32_t RCL_Handler_BLE5_findPacketDuration(uint32_t length, uint16_t phyFeatures) +{ + uint32_t duration; + switch (phyFeatures & BLE_PHY_FEATURE_PHY_MASK) + { + case BLE_PHY_FEATURE_PHY_1MBPS: + default: + duration = BLE_1MBPS_PACKET_BASE_TIME + BLE_1MBPS_TIME_PER_BYTE * length; + break; + + case BLE_PHY_FEATURE_PHY_2MBPS: + duration = BLE_2MBPS_PACKET_BASE_TIME + BLE_2MBPS_TIME_PER_BYTE * length; + break; + + case BLE_PHY_FEATURE_PHY_CODED: + if ((phyFeatures & 0x0004) == BLE_PHY_FEATURE_CODING_S8) + { + duration = BLE_CODED_S8_PACKET_BASE_TIME + BLE_CODED_S8_TIME_PER_BYTE * length; + } + else + { + duration = BLE_CODED_S2_PACKET_BASE_TIME + BLE_CODED_S2_TIME_PER_BYTE * length; + } + break; + } + return duration; +} + +/* + * ======== RCL_Handler_BLE5_findNumExtraBytes ======== + */ +static uint32_t RCL_Handler_BLE5_findNumExtraBytes(uint32_t fifoCfg) +{ + uint32_t numExtraBytes = 0; + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDCRC_M) + { + numExtraBytes += BLE_CRC_LENGTH; + } + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDSTATUS_M) + { + numExtraBytes += 1; + } + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDLQI_M) + { + numExtraBytes += 1; + } + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDFREQEST_M) + { + numExtraBytes += 1; + } + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDRSSI_M) + { + numExtraBytes += 1; + } + if (fifoCfg & PBE_BLE5_RAM_FIFOCFG_APPENDTIMESTAMP_M) + { + numExtraBytes += sizeof(uint32_t); + } + + return numExtraBytes; +} + +/* + * ======== RCL_Handler_BLE5_findRxSyncOverhead ======== + */ +static uint16_t RCL_Handler_BLE5_findRxSyncOverhead(uint16_t phyFeatures) +{ + uint16_t overhead; + switch (phyFeatures & BLE_PHY_FEATURE_PHY_MASK) + { + case BLE_PHY_FEATURE_PHY_1MBPS: + default: + overhead = RX_SYNC_OVERHEAD_1MBPS; + break; + + case BLE_PHY_FEATURE_PHY_2MBPS: + overhead = RX_SYNC_OVERHEAD_2MBPS; + break; + + case BLE_PHY_FEATURE_PHY_CODED: + overhead = RX_SYNC_OVERHEAD_CODED; + break; + } + return overhead; +} + +/* + * ======== RCL_Handler_BLE5_updateBackoffParams ======== + */ +static void RCL_Handler_BLE5_updateBackoffParams(RCL_CtxScanInit *ctx, uint16_t endCause) +{ + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + /* SCAN_RSP, AUX_SCAN_RSP, AUX_CONNECT_RSP received OK */ + ctx->backoffStatus.backOffLastFail = 0; + if (ctx->backoffStatus.backOffLastSucceed != 0) + { + /* Decrement backoffUpper */ + if (ctx->backoffUpper > 0) + { + ctx->backoffUpper--; + } + ctx->backoffStatus.backOffLastSucceed = 0; + } + else + { + ctx->backoffStatus.backOffLastSucceed = 1; + } + } + else + { + /* SCAN_RSP, AUX_SCAN_RSP or AUX_CONNECT_RSP not received OK */ + ctx->backoffStatus.backOffLastSucceed = 0; + if (ctx->backoffStatus.backOffLastFail != 0) + { + /* Increment backoffUpper */ + if (ctx->backoffUpper < BACKOFF_UPPER_MAX) + { + ctx->backoffUpper++; + } + ctx->backoffStatus.backOffLastFail = 0; + } + else + { + ctx->backoffStatus.backOffLastFail = 1; + } + } + /* Set new backoff count */ + /* Backoff definition in PBE is one less count than in Bluetooth spec */ + /* This gives value from 0 to (2^backoffUpper - 1) */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE5_RAM_O_BACKOFFCNT) = (RCL_Handler_BLE5_getRandomNumber() & ((1 << ctx->backoffUpper) - 1)); +} + +/* + * ======== RCL_Handler_BLE5_getAuxPtrFromTxBuffer ======== + */ +static void RCL_Handler_BLE5_getAuxPtrFromTxBuffer(RCL_Buffer_TxBuffer *curBuffer, RCL_AuxPtrInfo *auxPtrInfo, uint8_t offset) +{ + uint8_t payloadIndex = curBuffer->numPad - 1 + BLE_HEADER_LENGTH; + uint8_t pktLen = curBuffer->data[payloadIndex - 1]; + uint8_t extHdrFlags = curBuffer->data[payloadIndex + 1]; + + uint8_t auxPtrIndex = RCL_Handler_BLE5_checkExtHdrField(extHdrFlags, BLE_EXTENDED_HEADER_AUXPTR_BM); + + if (auxPtrIndex != 0) + { + /* + * Consider that the extended header takes 2 bytes, one for the extended header length + * and one for the header flags. + */ + auxPtrIndex += payloadIndex + 2; + + /* Determine Tx FIFO pointer to the auxOffset */ + auxPtrInfo->auxChCaOffsetUnitsFifoPtr = LRF_getTxFifoWrAddr(offset + payloadIndex + auxPtrIndex); + auxPtrInfo->auxOffsetLowFifoPtr = LRF_getTxFifoWrAddr(offset + payloadIndex + auxPtrIndex + 1); + auxPtrInfo->auxOffsetHighFifoPtr = LRF_getTxFifoWrAddr(offset + payloadIndex + auxPtrIndex + 2); + + /* Extract AuxPtr information from Tx Buffer */ + auxPtrInfo->pktLen = pktLen; + auxPtrInfo->ptrIndex = auxPtrIndex; + auxPtrInfo->chIndex = curBuffer->data[auxPtrIndex] & 0x3F; + auxPtrInfo->ca = ((curBuffer->data[auxPtrIndex] & 0x40) >> 6); + auxPtrInfo->offsetUnits = (curBuffer->data[auxPtrIndex] >> 7); + auxPtrInfo->auxOffset = ((uint16_t)(curBuffer->data[auxPtrIndex + 2] & 0x1F) << 8) | (uint16_t)(curBuffer->data[auxPtrIndex + 1]); + auxPtrInfo->auxPhy = curBuffer->data[auxPtrIndex + 2] >> 5; + auxPtrInfo->auxPtrPresent = true; + } + else + { + auxPtrInfo->pktLen = pktLen; + auxPtrInfo->ptrIndex = 0; + auxPtrInfo->chIndex = 0; + auxPtrInfo->offsetUnits = 0; + auxPtrInfo->auxOffset = 0; + auxPtrInfo->ca = 0; + auxPtrInfo->auxPhy = 0; + auxPtrInfo->auxChCaOffsetUnitsFifoPtr = NULL; + auxPtrInfo->auxOffsetLowFifoPtr = NULL; + auxPtrInfo->auxOffsetHighFifoPtr = NULL; + auxPtrInfo->auxPtrPresent = false; + } +} + +/* + * ======== RCL_Handler_BLE5_checkExtHdrField ======== + */ +static uint8_t RCL_Handler_BLE5_checkExtHdrField(uint8_t extHdrFlags, uint8_t fieldMask) +{ + uint8_t fieldIndex = 0; + + /* Check extended header flags to determine the index of the desired field (if present) */ + if (extHdrFlags & fieldMask) + { + if (extHdrFlags & BLE_EXTENDED_HEADER_ADVA_BM) + { + fieldIndex += BLE_EXTENDED_HEADER_ADVA_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_TARGETA_BM) + { + fieldIndex += BLE_EXTENDED_HEADER_TARGETA_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_CTEINFO_BM) + { + fieldIndex += BLE_EXTENDED_HEADER_CTEINFO_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_ADI_BM) + { + fieldIndex += BLE_EXTENDED_HEADER_ADI_LEN; + } + if ((extHdrFlags & BLE_EXTENDED_HEADER_AUXPTR_BM) && (fieldMask == BLE_EXTENDED_HEADER_SYNCINFO_BM)) + { + fieldIndex += BLE_EXTENDED_HEADER_AUXPTR_LEN; + } + } + + return fieldIndex; +} + +/* + * ======== RCL_Handler_BLE5_readAuxPtrFromRxBuffer ======== + */ +static void RCL_Handler_BLE5_readAuxPtrFromRxBuffer(uint32_t *data32, RCL_AuxPtrInfo *auxPtrInfo) +{ + uint8_t *data8; + data8 = (uint8_t*) data32; + uint8_t payloadIndex = 6 + BLE_HEADER_LENGTH; + uint8_t extHdrFlags = data8[payloadIndex + 1]; + + /* Check advertising type */ + if (extHdrFlags & BLE_EXTENDED_HEADER_AUXPTR_BM) + { + /* Extract AuxPtr information */ + uint8_t auxPtrIndex = payloadIndex + 2; + + if (extHdrFlags & BLE_EXTENDED_HEADER_ADVA_BM) + { + auxPtrIndex += BLE_EXTENDED_HEADER_ADVA_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_TARGETA_BM) + { + auxPtrIndex += BLE_EXTENDED_HEADER_TARGETA_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_CTEINFO_BM) + { + auxPtrIndex += BLE_EXTENDED_HEADER_CTEINFO_LEN; + } + if (extHdrFlags & BLE_EXTENDED_HEADER_ADI_BM) + { + auxPtrIndex += BLE_EXTENDED_HEADER_ADI_LEN; + } + + auxPtrInfo->auxOffset = ((uint16_t)(data8[auxPtrIndex + 2] & 0x1F) << 8) | (uint16_t)(data8[auxPtrIndex + 1]); + auxPtrInfo->ca = ((data8[auxPtrIndex] & 0x40) >> 6); + auxPtrInfo->offsetUnits = data8[auxPtrIndex] >> 7; + auxPtrInfo->chIndex = data8[auxPtrIndex] & 0x3F; + auxPtrInfo->auxPhy = data8[auxPtrIndex + 2] >> 5; + auxPtrInfo->ptrIndex = auxPtrIndex; + auxPtrInfo->pktLen = data8[payloadIndex - 1]; + + auxPtrInfo->auxChCaOffsetUnitsFifoPtr = NULL; + auxPtrInfo->auxOffsetHighFifoPtr = NULL; + auxPtrInfo->auxOffsetLowFifoPtr = NULL; + auxPtrInfo->auxPtrPresent = true; + } + else + { + auxPtrInfo->pktLen = 0; + auxPtrInfo->ptrIndex = 0; + auxPtrInfo->chIndex = 0; + auxPtrInfo->offsetUnits = 0; + auxPtrInfo->auxOffset = 0; + auxPtrInfo->ca = 0; + auxPtrInfo->auxPhy = 0; + auxPtrInfo->auxChCaOffsetUnitsFifoPtr = NULL; + auxPtrInfo->auxOffsetLowFifoPtr = NULL; + auxPtrInfo->auxOffsetHighFifoPtr = NULL; + auxPtrInfo->auxPtrPresent = false; + } +} + +/* + * ======== RCL_Handler_BLE5_updateAuxPtr ======== + */ +static bool RCL_Handler_BLE5_updateAuxPtr(RCL_AuxPtrInfo *auxPtr, uint32_t packetDuration, uint8_t chanMap, bool switchPhy) +{ + uint16_t auxOffsetUs; + uint16_t auxOffset; + uint8_t auxChCaOffsetUnits; + uint8_t auxOffsetLow; + uint8_t auxOffsetHigh; + bool status = true; + + uint8_t primaryChPacketsLeft = (chanMap & 1) + ((chanMap >> 1) & 1) + ((chanMap >> 2) & 1); + + /* + * First calculate the packet duration in terms of 30 us offset units. Then round up to avoid being too late. + * Note: Packet Duration is given in systim units [250 ns], so divide by 4 to get value in microseconds. + */ + uint32_t pktDurationInOffsetUnits = BLE_convertSystimUnitsToOffsetUnits(packetDuration, BLE_AUX_OFFSET_30_US); + /* + * Automatic calculation of the AuxPtr. + * All primary advertising channel packets must point to the same time. Since they have the same duration, + * the packet duration can be used to calculate the auxPtr. + */ + if ((auxPtr->offsetUnits == 1) && (auxPtr->auxOffset == 0)) + { + if (primaryChPacketsLeft == 0) + { + auxOffsetUs = (pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US; + } + else + { + auxOffsetUs = primaryChPacketsLeft * ((pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US); + } + + /* Consider the time that it takes to handle the PHY switching */ + if (switchPhy) + { + auxOffsetUs += EXT_ADV_PHY_SWITCHING_DELAY_US; + } + + /* Calculate the auxOffset in 30 us offset units */ + auxOffset = auxOffsetUs / BLE_AUX_OFFSET_30_US; + + /* Use 30 [us] offset units. Keep the rest of the AuxPtr information intact */ + auxChCaOffsetUnits = (auxPtr->chIndex | (auxPtr->ca << 6)); + } + /* + * If valid, use existing AuxPtr to send the first primary advertising channel packet, and derive the + * correct value for the rest of the primary advertising channel packets. + */ + else + { + uint32_t minReqOffsetUs; + auxOffsetUs = auxPtr->offsetUnits ? (auxPtr->auxOffset * BLE_AUX_OFFSET_300_US) : (auxPtr->auxOffset * BLE_AUX_OFFSET_30_US); + + if (primaryChPacketsLeft == 0) + { + /* No need to recalculate auxOffset. All primary advertising channel packets sent or start from secondary channel. */ + minReqOffsetUs = (pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US; + + if (auxOffsetUs < minReqOffsetUs) + { + /* Invalid initial auxOffset. Deadline can't be met. */ + status = false; + } + } + else + { + /* Derive correct auxOffset value based on the number of primary channel packets sent. */ + minReqOffsetUs = primaryChPacketsLeft * ((pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US); + + if (auxOffsetUs < minReqOffsetUs) + { + /* Invalid initial auxOffset. Deadline can't be met. */ + status = false; + } + else + { + auxOffsetUs -= (auxPtr->numPrimaryChPackets - primaryChPacketsLeft) * ((pktDurationInOffsetUnits * BLE_AUX_OFFSET_30_US) + EXT_ADV_INTERVAL_US); + } + } + + /* Consider the time that it takes to handle the PHY switching */ + if (switchPhy) + { + auxOffsetUs += EXT_ADV_PHY_SWITCHING_DELAY_US; + } + + /* Calculate the auxOffset in offset units (i.e. 30 us or 300 us) */ + auxOffset = auxPtr->offsetUnits ? (auxOffsetUs / BLE_AUX_OFFSET_300_US) : (auxOffsetUs / BLE_AUX_OFFSET_30_US); + + /* Keep the AuxPtr information intact */ + auxChCaOffsetUnits = (auxPtr->chIndex | (auxPtr->ca << 6) | (auxPtr->offsetUnits << 7)); + } + + auxOffsetLow = auxOffset & 0xFF; + auxOffsetHigh = (auxOffset >> 8) & 0x1F; + Log_printf(RclCore, Log_VERBOSE, "Start of next auxiliary packet in %d [us] or %d [offset units]", auxOffsetUs, auxOffset); + + /* Update Tx FIFO */ + *auxPtr->auxChCaOffsetUnitsFifoPtr = auxChCaOffsetUnits; + *auxPtr->auxOffsetLowFifoPtr = auxOffsetLow; + *auxPtr->auxOffsetHighFifoPtr = auxOffsetHigh | (auxPtr->auxPhy << 5); + + return status; +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.h b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.h new file mode 100644 index 00000000..da3bc0da --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble5.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_handlers_ble5_h__include +#define ti_drivers_RCL_handlers_ble5_h__include + +#include +#include +#include +#include +#include + +/* Handler functions */ +RCL_Events RCL_Handler_BLE5_adv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_scan_init(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_conn(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_dtmTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_genericRx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_genericTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Ble5_txTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_aux_adv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_periodicAdv(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE5_periodicScan(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); + +/** + * @brief Result of filter list update API + * + * Tells if RCL_BLE5_FilterListUpdateResult succeeded + */ +typedef enum +{ + RCL_BLE5_FilterListUpdateOk, /*!< Update was successful */ + RCL_BLE5_FilterListUpdateIndexError, /*!< Index was outside size of filter list or filter list was NULL */ +} RCL_BLE5_FilterListUpdateResult; + +/* API functions */ +/** + * @brief Update filter list + * + * Update the given filter list in a way that is safe even if a running command is using + * the filter list. The contents of %newEntry will be copied into %filterList->entries[%index]. + * + * If a scanner or initiator function is running, the filter list in use in the radio will also be + * updated in a way that ensures no match will be found on a non-existing entry. In a short time, + * neither the old nor new entry will give a match. + * + * If an advertiser command is running, the update will not apply until the next time the advertiser + * is started + * + * @param newEntry New filter list entry to apply + * @param filterList Filter accept list to update + * @param index Index into filter accept list to update + * + * @return Result telling if update was successful + * + */ +RCL_BLE5_FilterListUpdateResult RCL_BLE5_updateFilterList(const RCL_FL_Entry *newEntry, RCL_FilterList *filterList, uint32_t index); + +/** + * @brief Set RF frequency to use if custom frequency is specified + * + * If a command specifies to use a custom frequency, it will program the frequency last set using + * this function. + * + * @param rfFrequency RF frequency in Hz + * + */ +void RCL_BLE5_setDefaultRfFrequency(uint32_t rfFrequency); + +/** + * @brief Get channel field from packet + * + * Returns the channel that the packet was received on + * + * @param rxEntry Received data entry + * + * @return Channel for receiving packet + */ +static inline RCL_Ble5Channel RCL_BLE5_getRxChannel(const RCL_Buffer_DataEntry *rxEntry) +{ + return (RCL_Ble5Channel) rxEntry->pad0; +} + +/** + * @brief Get received status field from packet + * + * Returns the packet status field of a received packet, or {.value = RCL_BLE5_RX_PKT_STATUS_INVALID} if status is not enabled + * + * @param rxEntry Received data entry + * + * @return Receive packet status + */ +RCL_Ble5_RxPktStatus RCL_BLE5_getRxStatus(const RCL_Buffer_DataEntry *rxEntry); + +/** + * @brief Get received RSSI from packet + * + * Returns the RSSI field of a received packet, or LRF_RSSI_INVALID if RSSI is not enabled + * + * @param rxEntry Received data entry + * + * @return Reported RSSI of received packet + */ +int8_t RCL_BLE5_getRxRssi(const RCL_Buffer_DataEntry *rxEntry); + +/** + * @brief Get received timestamp from packet + * + * Returns the timestamp a received packet, adjusted according to the PHY it was received on + * (1 Mbps assumed if packet status is not available). If timestamp is not enabled, 0 is returned. + * Note that this is a valid value, so it can not be used for error checking. + * + * @param rxEntry Received data entry + * + * @return Timestamp of received packet + */ +uint32_t RCL_BLE5_getRxTimestamp(const RCL_Buffer_DataEntry *rxEntry); + +/** + * @brief Get the expected start time delta associated with sending an auxiliary advertising indication + * + * Returns the expected time delta between the start time of a non-connectable/non-scannable ADV_EXT_IND + * sent over a specific PHY on a defined channel map, and the start time of an AUX_ADV_IND that contains + * the SyncInfo field needed for periodic advertising establishment. + * + * @param phyFeatures PHY feature selector + * @param chMap Channel map. Bit positions 0-2 correspond to channels 37-39 + * @param advPayloadLen Payload length of ADV_EXT_IND + * + * @return Time delta in 250[ns] units between the start time of the ADV_EXT_IND and the start time of the AUX_ADV_IND + */ +uint32_t RCL_BLE5_getAuxAdvStartTimeDelta(uint16_t phyFeatures, uint8_t chMap, uint8_t advPayloadLen); + + +#endif /* ti_drivers_RCL_handlers_ble5_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.c b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.c new file mode 100644 index 00000000..83402717 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.c @@ -0,0 +1,2049 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ble_cs.c ======== + */ + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_lrfdtxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe32.h) +#include DeviceFamily_constructPath(inc/hw_lrfds2r.h) +#include DeviceFamily_constructPath(inc/rfe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_generic_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_ble5_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_ble_cs_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_ble_cs_regdef_regs.h) + +#ifndef OCTOPUS +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_gpio.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#endif + +#define BLE_CS_BASE_FREQ_MHZ 2402 +#define BLE_CS_MAX_CHANNEL 78 +#define BLE_CS_NUM_CHANNELS 90 +#define BLE_CS_NUM_INVALID_CHANNELS 7 +#define BLE_CS_SILENT_CHANNEL 100 +#define BLE_CS_NUM_PERMUTATION 24 +#define BLE_CS_S2R_OVERSAMPLE_RATE 4 +#define BLE_CS_S2R_MEMORY_OFFSET 0x0C00 +#define BLE_CS_TXFIFO_BASE_ADDR 128 +#define BLE_CS_TXFIFO_LEN 96 +#define BLE_CS_RXFIFO_BASE_ADDR 224 +#define BLE_CS_RXFIFO_LEN 160 +#define BLE_CS_FIRST_BATCH_SIZE 2 +#define BLE_CS_TONE_QUALITY_GOOD_THR 25 +#define BLE_CS_TONE_QUALITY_MEDIUM_THR 50 +#define BLE_CS_TONE_EXTENSION_INITIATOR_TX 0b01 +#define BLE_CS_TONE_EXTENSION_REFLECTOR_TX 0b10 +#define DECODE_ANTENNA(x, y) (((x) >> ((y)*2)) & 0x03) +#define ENCODE_ANTENNA(x, y) (((x) << ((y)*4))) +#define INT16_MSB(x) (((x) >> 8) & 0xFF) +#define INT16_LSB(x) ((x) & 0xFF) + +/* Prepare constant terms for step specific calculations */ +#define T1US 48 // Constant 1us at 48MHz +#define T3US 144 // Constant 3us at 48MHz +#define TRD 240 // Constant 5us at 48MHz +#define TGD 480 // Constant 10us at 48MHz +#define TPLT 960 // Constant 20us at 48MHz +#define TPYL 0 // Unknown at this point + +/* + * ======== Execution status ======== + */ +struct +{ + struct { + RCL_CommandStatus endStatus; + } common; + struct { + uint32_t startTime; + } ble_cs; +} bleCsHandlerState; + +/* Storage to decompress data */ +RCL_CmdBleCs_Step_Internal step; +RCL_CmdBleCs_StepResult_Internal result; + +/* Precalculated base terms */ +uint32_t tStepLut[RCL_CmdBleCs_StepMode_Length]; +uint16_t tAdjALut[RCL_CmdBleCs_StepMode_Length]; +uint16_t tAdjBLut[RCL_CmdBleCs_StepMode_Length]; +uint16_t tAntALut[RCL_CmdBleCs_StepMode_Length]; +uint16_t tAntBLut[RCL_CmdBleCs_StepMode_Length]; +uint16_t tRttAdjustLut[RCL_CmdBleCs_StepMode_Length]; + +/* + * ======== Type for indexing antenna sequence ======== + */ +typedef union { + struct { + uint8_t a0 : 2; + uint8_t a1 : 2; + uint8_t a2 : 2; + uint8_t a3 : 2; + } a; + uint8_t apn; +} RCL_AntennaPath_t; + +/* + * ======== Type for mapping antenna permutation to antenna sequence ======== + */ +typedef struct { + uint8_t numPath : 3; /*!< Total number of antenna path */ + uint8_t numPerm : 5; /*!< Total number of permutation possible with this configuration */ + uint8_t increment; /*!< How to index the permutation table */ + RCL_AntennaPath_t ap[2]; +} RCL_AntennaConfig_t; + +/* + * ======== Antenna permutation table ======== + */ +const RCL_AntennaPath_t antennaPermutation[BLE_CS_NUM_PERMUTATION] = { + /*[ 0:5 ]=*/{{0,1,2,3}}, {{0,1,3,2}}, {{0,2,3,1}}, {{0,2,1,3}}, {{0,3,1,2}}, {{0,3,2,1}}, + /*[ 6:11]=*/{{1,0,2,3}}, {{1,0,3,2}}, {{1,2,3,0}}, {{1,2,0,3}}, {{1,3,0,2}}, {{1,3,2,0}}, + /*[12:17]=*/{{2,0,1,3}}, {{2,0,3,1}}, {{2,1,3,0}}, {{2,1,0,3}}, {{2,3,0,1}}, {{2,3,1,0}}, + /*[18:24]=*/{{3,0,2,1}}, {{3,0,1,2}}, {{3,1,2,0}}, {{3,1,0,2}}, {{3,2,0,1}}, {{3,2,1,0}} +}; + +/* + * ======== Antenna permutation selection mapping ======== + */ +const RCL_AntennaConfig_t antennaConfig[RCL_CmdBleCs_AntennaConfig_Length] = { + /*1x1=*/{.numPath=1, .numPerm=1, .increment=0, .ap={/*initiator=*/{{0,0,0,0}}, /*reflector=*/{{0,0,0,0}}}}, + /*2x1=*/{.numPath=2, .numPerm=2, .increment=6, .ap={/*initiator=*/{{0,1,0,0}}, /*reflector=*/{{0,0,0,0}}}}, + /*3x1=*/{.numPath=3, .numPerm=6, .increment=3, .ap={/*initiator=*/{{0,1,2,0}}, /*reflector=*/{{0,0,0,0}}}}, + /*4x1=*/{.numPath=4, .numPerm=24, .increment=1, .ap={/*initiator=*/{{0,1,2,3}}, /*reflector=*/{{0,0,0,0}}}}, + /*1x2=*/{.numPath=2, .numPerm=2, .increment=6, .ap={/*initiator=*/{{0,0,0,0}}, /*reflector=*/{{0,1,0,0}}}}, + /*1x3=*/{.numPath=3, .numPerm=6, .increment=3, .ap={/*initiator=*/{{0,0,0,0}}, /*reflector=*/{{0,1,2,0}}}}, + /*1x4=*/{.numPath=4, .numPerm=24, .increment=1, .ap={/*initiator=*/{{0,0,0,0}}, /*reflector=*/{{0,1,2,3}}}}, + /*2x2=*/{.numPath=4, .numPerm=24, .increment=1, .ap={/*initiator=*/{{0,0,1,1}}, /*reflector=*/{{0,1,1,0}}}} +}; + +/* + * ======== Type of configuration of MCE and FIDC accumulator used for PCT measurement ======== + */ +typedef union { + struct { + uint8_t period : 2; /*!< Configures the accumulation period of DEMFIDC module */ + uint8_t numIteration : 2; /*!< Configures how many times to run the accumulator period */ + uint8_t fracWaitAdj : 4; + uint8_t fracWait; + }; + uint16_t val; +} RCL_PctConfig_t; + +typedef union { + struct { + uint8_t magnIteration; + uint8_t reserved; + }; + uint16_t val; +} RCL_MagnConfig_t; + +typedef struct { + int16_t mode0[2]; + int16_t mode1[2]; + int16_t mode2[2]; + int16_t mode3[2]; +} RCL_Tadjust_t; + +/* + * ======== Type of configuration for phy specific settings ======== + */ +typedef struct { + /* Modem specific registers */ + uint16_t baud; + uint16_t symmap; + uint16_t demmisc2; + uint16_t demmisc3; + uint16_t rssioffset; + + /* Timing parameters [48 MHz units unless specified otherwise] */ + uint16_t tPostProcessDiv1; /*!< Duration set aside for post processing */ + uint16_t tPostProcessDiv12; /*!< Duration set aside for post processing */ + uint16_t tRxTimeoutI0; /*!< Initiator must terminate packet reception before end of step */ + uint16_t tRxTimeoutI3; /*!< Initiator must terminate packet reception before end of step */ + int16_t tPilotAdjust; /*!< Pilot tone need to be adjusted with shaper delay */ + uint16_t tStartup; /*!< Duration set aside for starting up the topSMs and start to emit a tone on the antenna */ + uint16_t tPacket; /*!< Duration of packet [preamble + AA + Trailer] */ + uint16_t tRxTimeoutRn; /*!< Reception timeout on reflector side */ + uint16_t tInfiniteRx; /*!< Correction of step duration when packet reception is used as anchor point */ + uint16_t tTr; /*!< Duration of trailer bits */ + uint16_t tCorr; /*!< Time between signal on antenna and correlation event */ + uint16_t tDem; /*!< Time between signal on antenna and demodulation completed*/ + uint16_t tFidc; /*!< Time between signal on antenna and FIDC */ + uint16_t tTxModDelay; /*!< Time between modulator and signal on antenna (mostly shaper delay) */ + uint16_t tTimestampDelay1; /*!< Sum of delays between signal on antenna vs capture on timer by HW for mode-1 */ + uint16_t tTimestampDelay3; /*!< Sum of delays between signal on antenna vs capture on timer by HW for mode-3 */ + + /* Accumulator period and iteration number in order to fit into the same TPM period. */ + RCL_PctConfig_t pctConfig[RCL_CmdBleCs_Tpm_Length]; + + /* Magnitude accumulator configuration used by RFE for tone quality estimation */ + RCL_MagnConfig_t magnConfig[RCL_CmdBleCs_Tpm_Length]; + + /* Adjustment of TIP period per mode */ + RCL_Tadjust_t tAdj[RCL_CmdBleCs_Role_Length]; + + /* Adjustment of antenna timings for mode 2 & 3 */ + RCL_Tadjust_t tAnt[RCL_CmdBleCs_Role_Length]; +} RCL_PhyConfig_t; + +//#define FE_8MHZ 1 +/* + * ======== Configuration per PHY ======== + */ +const RCL_PhyConfig_t phyConfigLut[RCL_CmdBleCs_Phy_Length] = { + #ifdef FE_8MHZ + { /* Phy_1M @ 8MHZ*/ + .baud = 0x4000, + .symmap = 0x001F, + .demmisc2 = 0x15F8, + .demmisc3 = 0x10A1, + .rssioffset = 0x0049, + + /* Theory */ + .tPacket = 2112, // 8+32+4 bits = 44us + .tTr = 192, // 4us + + /* Tuned */ + .tStartup = 93, // 1.937us (pbe_timer_event -> mce_timer start) + .tTxModDelay = 245, // 5.109us (wait -> signal on shaper) + .tPilotAdjust = 264, // 5.5us + .tPostProcessDiv1 = 936, // 19.5us + .tPostProcessDiv12 = 78, // 19.5us + .tInfiniteRx = 60, // 1.25us + + .tFidc = 161, // 3.35us + .tCorr = 244, // 5.08us + .tDem = 783, // 16.31us + + .tRxTimeoutI0 = RCL_BLE_CS_US_TO_MCE_TIMER(70), + .tRxTimeoutI3 = RCL_BLE_CS_US_TO_MCE_TIMER(56), + .tRxTimeoutRn = RCL_BLE_CS_US_TO_MCE_TIMER(76), + + /* Sum of demodulation and modulation delay (HW only) */ + .tTimestampDelay1 = 477, + .tTimestampDelay3 = 481, + + .pctConfig = { + /*TPM = 10US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 2, .fracWait = 32, .fracWaitAdj = 9}, + /*TPM = 20US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 1, .fracWait = 128, .fracWaitAdj = 0}, + /*TPM = 40US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 2, .fracWait = 128, .fracWaitAdj = 0} + }, + + .magnConfig = { + /*TPM = 10US*/{.magnIteration = 5}, + /*TPM = 20US*/{.magnIteration = 14}, + /*TPM = 40US*/{.magnIteration = 30} + }, + + .tAdj = { /* { pkt-tn, tn-tn} */ + { + /* Initiator */ + .mode0 = {0, 0}, + .mode1 = {0, 0}, + .mode2 = {-147, +112}, + .mode3 = {0, +28} + }, + { + /* Reflector */ + .mode0 = {+11, 0}, + .mode1 = {+11, 0}, + .mode2 = {-66, -96}, + .mode3 = {-50, -54} + } + }, + + .tAnt = { + { + /* Initiator */ + .mode2 = {0, 0}, + .mode3 = {0, 0} + }, + { + /* Reflector */ + .mode2 = {0, 0}, + .mode3 = {0, 0} + } + } + }, + #else + { /* Phy_1M @ 4MHZ*/ + .baud = 0x4000, + .symmap = 0x001F, + .demmisc2 = 0x05F8, + .demmisc3 = 0x1082, + .rssioffset = 0x0049, + + /* Theory */ + .tPacket = 2112, // 8+32+4 bits = 44us + .tTr = 192, // 4us + + /* Tuned */ + .tStartup = 93, // 1.937us (pbe_timer_event -> mce_timer start) + .tTxModDelay = 245, // 5.109us (wait -> signal on shaper) + .tPilotAdjust = 259, // 5.39us + .tPostProcessDiv1 = 936, // 19.5us + .tPostProcessDiv12 = 78, // 19.5us + .tInfiniteRx = 60, // 1.25us + + .tFidc = 264, // 5.5us + .tCorr = 377, // 7.85us + .tDem = 914, // 19.05us + + .tRxTimeoutI0 = RCL_BLE_CS_US_TO_MCE_TIMER(70), + .tRxTimeoutI3 = RCL_BLE_CS_US_TO_MCE_TIMER(56), + .tRxTimeoutRn = RCL_BLE_CS_US_TO_MCE_TIMER(76), + + /* Sum of demodulation and modulation delay (HW only) */ + .tTimestampDelay1 = 603, + .tTimestampDelay3 = 601, + + .pctConfig = { + /*TPM = 10US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 1, .fracWait = 32, .fracWaitAdj = 0}, + /*TPM = 20US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 2, .fracWait = 32, .fracWaitAdj = 0}, + /*TPM = 40US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 1, .fracWait = 128, .fracWaitAdj = 0} + }, + + .magnConfig = { + /*TPM = 10US*/{.magnIteration = 3}, + /*TPM = 20US*/{.magnIteration = 6}, + /*TPM = 40US*/{.magnIteration = 14} + }, + + .tAdj = { /* { pkt-tn, tn-tn} */ + { + /* Initiator */ + .mode0 = {0, 0}, + .mode1 = {0, 0}, + .mode2 = {-147, +64}, + .mode3 = {0, -22} + }, + { + /* Reflector */ + .mode0 = {+27, 0}, + .mode1 = {+27, 0}, + .mode2 = {-94, -48}, + .mode3 = {-96, +16} + } + }, + + .tAnt = { + { + /* Initiator */ + .mode2 = {+60, 0}, + .mode3 = {+66, 0} + }, + { + /* Reflector */ + .mode2 = {+105, 0}, + .mode3 = {+105, 0} + } + } + }, + #endif + { /* Phy_2M */ + .baud = 0x8000, + .symmap = 0x002E, + .demmisc2 = 0x04F8, + .demmisc3 = 0x1081, + .rssioffset = 0x0049, + + /* Theory */ + .tPacket = 1248, // 16+32+4bit = 26us + .tTr = 96, // 2us + + /* Tuned */ + .tStartup = 95, // 1.979us (pbe_timer_event -> mce_timer start) + .tTxModDelay = 142, // 2.957us (wait -> signal on shaper) + .tPilotAdjust = 156, // 4.02us + .tPostProcessDiv1 = 720, // 15us + .tPostProcessDiv12 = 60, // 15us + .tInfiniteRx = 60, // 1.25us + + .tFidc = 146, // 3.05us + .tCorr = 204, // 4.25us + .tDem = 565, // 11.77us + + .tRxTimeoutI0 = 2448+24, // 51us MCE + .tRxTimeoutI3 = 1776, // 37us MCE + .tRxTimeoutRn = 3096, // 64.5us MCE + + /* Sum of demodulation and modulation delay (HW only) */ + .tTimestampDelay1 = 333, + .tTimestampDelay3 = 335, + + .pctConfig = { + /*TPM = 10US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 2, .fracWait = 32, .fracWaitAdj = 9}, + /*TPM = 20US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 1, .fracWait = 128, .fracWaitAdj = 0}, + /*TPM = 40US*/{.period = (LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 >> LRFDMDM_DEMFIDC0_ACCPERIOD_S), .numIteration = 2, .fracWait = 128, .fracWaitAdj = 0} + }, + + .magnConfig = { + /*TPM = 10US*/{.magnIteration = 5}, + /*TPM = 20US*/{.magnIteration = 14}, + /*TPM = 40US*/{.magnIteration = 30} + }, + + .tAdj = { + { + /* Initiator */ + .mode0 = {0, 0}, + .mode1 = {0, 0}, + .mode2 = {-48, +107}, + .mode3 = {0, 0} + }, + { + /* Reflector */ + .mode0 = {+32, 0}, + .mode1 = {+32, 0}, + .mode2 = {-38, -93}, + .mode3 = {-60, -20} + } + }, + + .tAnt = { + { + /* Initiator */ + .mode2 = {+63, 0}, + .mode3 = {+63, 0} + }, + { + /* Reflector */ + .mode2 = {+129, 0}, + .mode3 = {+129, 0} + } + } + } +}; + +/* Frequency compensation value due to the fixed CMIXN value use. Resolution is 4x FOFF unit. + Calculated based on the formula: + foffError = 4x ((((1<<21) * fif) / (BLE_CS_BASE_FREQ_MHZ + pStepI->channelIdx) / 1e3) + - ((1<<21) * (1024 - pStepI->cmixn) / 288 / 1024)); */ +const int8_t foffErrorLut[BLE_CS_NUM_CHANNELS] = { + /*2402 MHz =*/ 38, 34, 34, 34, 30, 30, 30, 26, + /*2410 MHz =*/ 26, 26, 26, 22, 22, 22, 18, 18, 18, 14, + /*2420 MHz =*/ 14, 14, 10, 10, 10, 10, 6, 6, 6, 2, + /*2430 MHz =*/ 2, 2, -2, -2, -2, -2, -6, -6, -6,-10, + /*2440 MHz =*/ -10,-10,-14,-14,-14,-14,-18,-18,-18,-22, + /*2450 MHz =*/ -22,-22,-26,-26,-26,-26,-30,-30,-30,-34, + /*2460 MHz =*/ -34,-34,-34,-38,-38,-38,-42,-42,-42,-46, + /*2470 MHz =*/ -46,-46,-46,-50,-50,-50,-54,-54,-54,-54, + /*2480 MHz =*/ -58,-58,-58,-62,-62,-62,-62,-66,-66,-66 +}; + +/* Look up table of payload length in units of MCE Timer at rate of [1M]. Scaling dynamically if needed. */ +const uint16_t payloadLut[RCL_CmdBleCs_Payload_Length] = { + /*0 bits =*/ RCL_BLE_CS_US_TO_MCE_TIMER(0), + /*32 bits =*/ RCL_BLE_CS_US_TO_MCE_TIMER(32), + /*64 bits =*/ RCL_BLE_CS_US_TO_MCE_TIMER(64), + /*96 bits =*/ RCL_BLE_CS_US_TO_MCE_TIMER(96), + /*128 bits =*/ RCL_BLE_CS_US_TO_MCE_TIMER(128) +}; + +/* Forward declarations */ +static RCL_MultiBuffer* RCL_Handler_BLE_CS_findBufferFitNumberOfBytes(List_List *pHead, uint16_t numBytes); +static void RCL_Handler_BLE_CS_configureTxRxFifo(RCL_CmdBleCs* pCmd); +static void RCL_Handler_BLE_CS_retrieveAndStoreNextResult(RCL_CmdBleCs* pCmd, bool forceBufferToFinishState); +static void RCL_Handler_BLE_CS_fetchAndforwardNextStep(RCL_CmdBleCs* pCmd); +static RCL_Events RCL_Handler_BLE_CS_preFillTxBuffer(RCL_CmdBleCs* pCmd); +static RCL_Events RCL_Handler_BLE_CS_readWriteBuffer(RCL_CmdBleCs* pCmd, bool forceBufferToFinishState); +static bool RCL_Handler_BLE_CS_transferFinishedBuffers(List_List *pSrc, List_List *pDst); +static void RCL_Handler_BLE_CS_configureS2R(RCL_CmdBleCs *pCmd); +static RCL_Events RCL_Handler_BLE_CS_readS2RSamples(RCL_CmdBleCs *pCmd); +static void RCL_Handler_BLE_CS_readStatistics(RCL_CmdBleCs *pCmd); +static void RCL_Handler_BLE_CS_preprocessCommand(RCL_CmdBleCs *pCmd); +static void RCL_Handler_BLE_CS_preprocessStep(RCL_CmdBleCs *pCmd, RCL_CmdBleCs_Step *pStep, RCL_CmdBleCs_Step_Internal *pStepI); +static RCL_CmdBleCs_StepResult_Internal* RCL_Handler_BLE_CS_fetchNextStepResult(RCL_CmdBleCs *pCmd); +static int16_t RCL_Handler_BLE_CS_convertFreqOffset(int16_t foffMeasured); +static int16_t RCL_Handler_BLE_CS_convertRtt(RCL_CmdBleCs *pCmd, uint8_t mode, int8_t channel, int16_t foff, uint8_t payload, bool secondToneExtensionSlot, float toAD, uint16_t corrBefore, uint16_t corrPeak, uint16_t corrAfter); +static uint32_t RCL_Handler_BLE_CS_convertPct(int16_t pct_i, int16_t pct_q, uint8_t channelIdx); +static uint8_t RCL_Handler_BLE_CS_convertPctQuality(uint16_t qMin, uint16_t qMax, uint16_t qAvg, bool toneExtensionSlot, bool toneExpected); +static uint16_t RCL_Handler_BLE_CS_estimateStepResultLength(RCL_CmdBleCs *pCmd,RCL_CmdBleCs_StepResult_Internal* src); +static uint16_t RCL_Handler_BLE_CS_convertStepResult(RCL_CmdBleCs* pCmd, uint8_t *dst, RCL_CmdBleCs_StepResult_Internal* src); +static RCL_CommandStatus RCL_Handler_BLE_CS_findPbeErrorEndStatus(uint16_t pbeEndStatus); + +/* + * ======== Traverse multibuffer list looking for space ======== + */ +static RCL_MultiBuffer* RCL_Handler_BLE_CS_findBufferFitNumberOfBytes(List_List *pHead, uint16_t numBytes) +{ + /* Start search from the head of list */ + RCL_MultiBuffer *pBuffer = RCL_MultiBuffer_head(pHead); + + /* Traverse the chain of buffers and find the first free one */ + do { + pBuffer = RCL_MultiBuffer_findFirstWritableBuffer(pBuffer); + + /* Avoid NULL pointer dereferencing */ + if (pBuffer) + { + /* Check for available space */ + if (pBuffer->length - pBuffer->tailIndex >= numBytes) + { + /* Mark the buffer to be written */ + pBuffer->state = RCL_BufferStateInUse; + + break; + } + else + { + /* The buffer will not fit the incoming number of bytes */ + pBuffer->state = RCL_BufferStateFinished; + } + } + } while (pBuffer); + + return (pBuffer); +} + +/* + * ======== Transfer all buffers marked as finished from one list to another ======== + */ +static bool RCL_Handler_BLE_CS_transferFinishedBuffers(List_List *pSrc, List_List *pDst) +{ + /* Initialize return value */ + bool callbackEvent = false; + RCL_MultiBuffer *pBuffer = NULL; + + /* Transfer the used buffers */ + do + { + pBuffer = RCL_MultiBuffer_head(pSrc); + + if (pBuffer && (pBuffer->state == RCL_BufferStateFinished)) + { + /* Pop from list and add to done list */ + RCL_MultiBuffer *pBuff = RCL_MultiBuffer_get(pSrc); + RCL_MultiBuffer_put(pDst, pBuff); + + /* Trigger callback side effect*/ + callbackEvent = true; + } + else + { + break; + } + } while (pBuffer); + + return (callbackEvent); +} + +/* + * ======== Configure the BUFRAM size and interrupts for BLE CS ======== + */ +static void RCL_Handler_BLE_CS_configureTxRxFifo(RCL_CmdBleCs* pCmd) +{ + /* Override the FIFO location and size */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG1) = BLE_CS_TXFIFO_BASE_ADDR; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG2) = BLE_CS_TXFIFO_LEN; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG3) = BLE_CS_RXFIFO_BASE_ADDR; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG4) = BLE_CS_RXFIFO_LEN; + + /* Reset FIFOs to have a clean start */ + /* Writing to FCMD is safe since the PBE is not running, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = LRFDPBE_FCMD_DATA_FIFO_RESET; + + /* Calculate how many entries can be stored simultaneous in given size of tx/rx fifos */ + uint16_t nStepsFit = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWRITABLE) / sizeof(RCL_CmdBleCs_Step_Internal); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWBTHRS) = (nStepsFit - 1) * sizeof(RCL_CmdBleCs_Step_Internal); + + uint16_t nResultsFit = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFWRITABLE) / sizeof(RCL_CmdBleCs_StepResult_Internal); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRBTHRS) = (nResultsFit - 1) * sizeof(RCL_CmdBleCs_StepResult_Internal); + + #ifndef PG2 + /* CDDS BUG00003 - Temporarily workaround */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRBTHRS) = sizeof(RCL_CmdBleCs_StepResult_Internal); + #endif + + /* FIFO pointers should auto-commit/auto-dealloc, enable threshold events */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) | (LRFDPBE_FCFG0_TXACOM_M | LRFDPBE_FCFG0_TXADEAL_M | LRFDPBE_FCFG0_RXACOM_M | LRFDPBE_FCFG0_RXADEAL_M); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_FCFG0) & (~(LRFDPBE_FCFG0_RXIRQMET_M | LRFDPBE_FCFG0_TXIRQMET_M)); + + /* Clear any interrupts left from uninitialized fifos */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_EVTCLR1) = (LRFDPBE_EVTCLR1_RXRDBTHR_M | LRFDPBE_EVTCLR1_RXWRBTHR_M | LRFDPBE_EVTCLR1_TXRDBTHR_M | LRFDPBE_EVTCLR1_TXWRBTHR_M); + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_ICLR0) | (LRFDDBELL_ICLR0_RXFIFO_M | LRFDDBELL_ICLR0_TXFIFO_M); +} + +/* + * ======== Fill the BLE CS step descriptors into the BUFRAM TX FIFO ======== + */ +static RCL_Events RCL_Handler_BLE_CS_preFillTxBuffer(RCL_CmdBleCs* pCmd) +{ + /* Initialize return value */ + RCL_Events events = {.value = 0}; + + /* Calculate how many additional step will fit (which might be all) */ + uint16_t nWritable = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_TXFWRITABLE) / sizeof(RCL_CmdBleCs_Step_Internal); + uint16_t nRemaining = (pCmd->mode.repeatSteps) ? (pCmd->mode.nSteps) : (pCmd->mode.nSteps - pCmd->stats->nStepsWritten); + uint16_t nBatch = (nWritable < nRemaining) ? nWritable : nRemaining; + + /* Limited time is available when we start the command (ABS_START_TIME_OFFSET), + so the first batch is reduced */ + if (pCmd->stats->nStepsWritten == 0) + { + nBatch = (nBatch < BLE_CS_FIRST_BATCH_SIZE) ? nBatch : BLE_CS_FIRST_BATCH_SIZE; + } + + /* Transfer the calculated number of steps into the fifo */ + for (uint16_t i=0; istepBuffers, &pCmd->stepBuffersDone); + + return (events); +} + +/* + * ======== Write the BLE CS Steps to the BUFRAM TX fifo ======== + */ +static void RCL_Handler_BLE_CS_fetchAndforwardNextStep(RCL_CmdBleCs* pCmd) +{ + /* Default return value */ + RCL_CmdBleCs_Step *pStep = NULL; + + /* Buffers are served on a FIFO basis */ + RCL_MultiBuffer *pStepBuffer = RCL_MultiBuffer_head(&pCmd->stepBuffers); + + /* Handle buffer boundaries within a batch */ + pStepBuffer = RCL_MultiBuffer_findFirstWritableBuffer(pStepBuffer); + if (pStepBuffer) + { + /* Flag the buffer */ + pStepBuffer->state = RCL_BufferStateInUse; + + /* Point to the beginning of step list */ + pStep = (RCL_CmdBleCs_Step *) &pStepBuffer->data[0]; + + /* Verify that there is enough bytes in the buffer */ + if ((pStepBuffer->headIndex + sizeof(RCL_CmdBleCs_Step)) <= pStepBuffer->tailIndex) + { + /* Point to the next entry */ + pStep += pStepBuffer->headIndex/sizeof(RCL_CmdBleCs_Step); + + /* Decompress and calculate internal parameters on step */ + RCL_Handler_BLE_CS_preprocessStep(pCmd, pStep, &step); + + /* Send it to PBE */ + uint32_t *ptr = (uint32_t *) &step; + for(uint8_t j=0; jstats->nStepsWritten++; + pStepBuffer->headIndex += sizeof(RCL_CmdBleCs_Step); + + /* This buffer is exhausted, or end of subevent */ + if (pStepBuffer->headIndex == pStepBuffer->tailIndex) + { + if (pCmd->mode.repeatSteps == false) + { + /* Update state and move the buffer */ + pStepBuffer->state = RCL_BufferStateFinished; + } + else + { + /* Pretend that this is the beginning of the sequence */ + pStepBuffer->headIndex = 0; + pCmd->stats->nStepsWritten = 0; + } + } + } + } +} + +/* + * ======== Read the BLE CS Step results from the BUFRAM RX fifo ======== + */ +static void RCL_Handler_BLE_CS_retrieveAndStoreNextResult(RCL_CmdBleCs* pCmd, bool forceBufferToFinishState) +{ + uint32_t *ptr = (uint32_t *) &result; + for(uint8_t j=0; jstats->nRxOk += 1; + } + else + { + pCmd->stats->nRxNok += 1; + } + + /* Pop and fill the next container */ + RCL_CmdBleCs_StepResult_Internal *pResult = RCL_Handler_BLE_CS_fetchNextStepResult(pCmd); + if (pResult) + { + memcpy(pResult, (RCL_CmdBleCs_StepResult_Internal *) &result, sizeof(RCL_CmdBleCs_StepResult_Internal)); + } + + /* Identify HCI compression size */ + uint16_t requiredSpaceInBytes = RCL_Handler_BLE_CS_estimateStepResultLength(pCmd, (RCL_CmdBleCs_StepResult_Internal *) &result); + + /* Alternative HCI destination */ + RCL_MultiBuffer *pResultBuffer = RCL_Handler_BLE_CS_findBufferFitNumberOfBytes(&pCmd->resultBuffers, requiredSpaceInBytes); + + /* Increment if either internal or HCI format is used */ + if (pResult || pResultBuffer) + { + pCmd->stats->nResultsRead++; + } + + /* Avoid NULL pointer dereferencing */ + if (pResultBuffer) + { + /* Decode the start of the segment */ + RCL_CmdBleCs_SubeventResults *pSubeventResults = (RCL_CmdBleCs_SubeventResults *) pResultBuffer->data; + + /* Initialize header in an empty buffer */ + if (pResultBuffer->tailIndex == 0) + { + /* No steps reported yet */ + pSubeventResults->numStepsReported = 0; + + /* Increment tail with header length */ + RCL_MultiBuffer_commitBytes(pResultBuffer, sizeof(RCL_CmdBleCs_SubeventResults)); + } + + /* Update the HCI header */ + pSubeventResults->numStepsReported += 1; + pSubeventResults->numAntennaPath = pCmd->stats->numAntennaPath + 1; + pSubeventResults->referencePowerLevel = result.gain; + pSubeventResults->frequencyCompensation = RCL_Handler_BLE_CS_convertFreqOffset(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFCOMP) << 2); + + if (pCmd->stats->nResultsRead == 1) + { + pCmd->stats->reserved0 = result.gain; + } + + /* Decode the offset of data field */ + uint8_t *pResult = RCL_MultiBuffer_getNextWritableByte(pResultBuffer); + + /* Compress and write the data */ + uint32_t nBytes = RCL_Handler_BLE_CS_convertStepResult(pCmd, pResult, (RCL_CmdBleCs_StepResult_Internal *) &result); + + /* Commit the pointers in the buffer */ + RCL_MultiBuffer_commitBytes(pResultBuffer, nBytes); + + /* Force close the multibuffer, even if there is more space left */ + if ( (pCmd->mode.repeatSteps == false) && (pCmd->mode.nSteps == pCmd->stats->nResultsRead) ) + { + pResultBuffer->state = RCL_BufferStateFinished; + } + else if (forceBufferToFinishState) + { + pResultBuffer->state = RCL_BufferStateFinished; + } + } +} + +/* + * ======== Read the BLE CS Step results from the BUFRAM RX fifo ======== + */ +static RCL_Events RCL_Handler_BLE_CS_readWriteBuffer(RCL_CmdBleCs* pCmd, bool forceBufferToFinishState) +{ + /* Initialize return value */ + RCL_Events events = {.value = 0}; + + /* Calculate how many result entries are available in rx fifo (might be all that has left) */ + uint16_t nBatch = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) / sizeof(RCL_CmdBleCs_StepResult_Internal); + + /* Read out the calculated number of entries */ + for (uint16_t i=0; iresultBuffers, &pCmd->resultBuffersDone); + events.txBufferFinished = (uint32_t) RCL_Handler_BLE_CS_transferFinishedBuffers(&pCmd->stepBuffers, &pCmd->stepBuffersDone); + + /* Reduce the batch size if there is only a few entries missing */ + int16_t nRemaining = pCmd->mode.nSteps - pCmd->stats->nResultsRead; + if (nRemaining <= 0) + { + if (pCmd->mode.repeatSteps == false) + { + /* No more results expected, set the threshold to the max */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRBTHRS) = 0x3FF; + } + } + else if (nRemaining < nBatch) + { + /* Reduce the Fifo threshold to number of remaining steps */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFRBTHRS) = (nRemaining * sizeof(RCL_CmdBleCs_StepResult_Internal)); + } + + return (events); +} + + +/* + * ======== Initialize the S2R engine ======== + */ +static void RCL_Handler_BLE_CS_configureS2R(RCL_CmdBleCs *pCmd) +{ + LRF_setRclClockEnable(LRFDDBELL_CLKCTL_S2RRAM_M | LRFDDBELL_CLKCTL_S2R_M); + + /* Access the list of multibuffers */ + RCL_MultiBuffer *pS2rBuffer = RCL_MultiBuffer_head(&pCmd->s2rBuffers); + + /* Only set up S2R, if there is buffer on the list */ + if (pS2rBuffer) + { + /* Store 32bit words in S2R (offset 3072) memory; don't arm yet */ + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_START) = BLE_CS_S2R_MEMORY_OFFSET; + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_STOP) = HWREG_READ_LRF(LRFDS2R_BASE + LRFDS2R_O_START) + (RCL_BLE_CS_MAX_S2R_LEN >> pCmd->mode.phy); + HWREG_WRITE_LRF(LRFDS2R_BASE + LRFDS2R_O_CFG) = LRFDS2R_CFG_CTL_EN + | LRFDS2R_CFG_SEL_FRONTEND + | LRFDS2R_CFG_TRIGMODE_ONESHOT + | LRFDS2R_CFG_LAST0_DIS; + } +} + +/* + * ======== Read the S2R memory ======== + */ +RCL_Events RCL_Handler_BLE_CS_readS2RSamples(RCL_CmdBleCs *pCmd) +{ + RCL_Events events = {.value = 0}; + + uint16_t s2rLength = sizeof(S2RSample) * HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTWORDSIZE); + uint16_t dataLength = sizeof(RCL_CmdBleCs_S2r) + s2rLength; + + /* Access the list of multibuffers */ + RCL_MultiBuffer *pS2rBuffer = RCL_Handler_BLE_CS_findBufferFitNumberOfBytes(&pCmd->s2rBuffers, dataLength); + + if (pS2rBuffer) + { + /* Decode the next free slot in the multibuffer */ + RCL_CmdBleCs_S2r *pS2rData = (RCL_CmdBleCs_S2r *) RCL_MultiBuffer_getNextWritableByte(pS2rBuffer); + + /* Store the step index */ + pS2rData->phy = pCmd->mode.phy; + pS2rData->idx = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTIDX); + pS2rData->channel = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTCHIDX); + pS2rData->payloadLen = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTPAYLOADLEN); + /* 32 bit access */ + pS2rData->payload0 = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD0L); + pS2rData->payload1 = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD1L); + pS2rData->payload2 = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD2L); + pS2rData->payload3 = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTPAYLOAD3L); + + /* Number of valid samples to be copied out with 32bit operation + Need to calculate with 0/32/64/96/128 bit @ 8MHz/4MHz front-end sampling */ + pS2rData->iqLength = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_S2ROUTWORDSIZE); + + /* Store the data, unwrap the loop for faster copying */ + uint32_t *src = (uint32_t *)S2R_RAM_BASE_ADDR; + uint32_t *dst = (uint32_t *)&pS2rData->data; + + #ifdef NO_INLINE_ASM + for(uint16_t i=0; i<(pS2rData->iqLength >> 3); i++) + { + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + } + #else + for(uint16_t i=0; i<(pS2rData->iqLength >> 2); i++) + { + __asm( + "LDMIA %0!, {r4, r5, r6, r7} \n" + "STMIA %1!, {r4, r5, r6, r7} \n" + : "+r" (src), "+r" (dst) : + : "r4", "r5", "r6", "r7"); + } + #endif + + /* Flag the entry */ + RCL_MultiBuffer_commitBytes(pS2rBuffer, dataLength); + pCmd->stats->nS2RDone++; + + /* Force close the buffer, even if there is more space left */ + pS2rBuffer->state = RCL_BufferStateFinished; + + /* Transfer the used buffers, should trigger a callback if any */ + events.swTriggered = (uint32_t) RCL_Handler_BLE_CS_transferFinishedBuffers(&pCmd->s2rBuffers, &pCmd->s2rBuffersDone); + } + + return (events); +} + +/* + * ======== Read the statistics from the PBE ======== + */ +static void RCL_Handler_BLE_CS_readStatistics(RCL_CmdBleCs *pCmd) +{ + if (pCmd->stats) + { + pCmd->stats->nStepsDone = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_NSTEPSDONE); + pCmd->stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_RSSILAST); + pCmd->stats->lastFoff = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFLAST); + pCmd->stats->foffComp = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFCOMP); + } +} + +/* + * ======== Load the command and step descriptors into LRF REGISTERS/BUFRAM ======== + */ +static void RCL_Handler_BLE_CS_preprocessCommand(RCL_CmdBleCs *pCmd) +{ + /* Force antenna switching time to zero for single antenna path per spec */ + if (pCmd->antennaConfig.select == 0) + { + pCmd->timing.tSw = 0; + } + + /* Decode mapping of configuration to antennas */ + const RCL_AntennaConfig_t *antennaEntry = &antennaConfig[pCmd->antennaConfig.select]; + + /* Decode the Phy specific settings */ + const RCL_PhyConfig_t *config = &phyConfigLut[pCmd->mode.phy]; + + /* Clear output statistics */ + if (pCmd->stats) + { + memset((void *)pCmd->stats, 0, sizeof(RCL_CmdBleCs_Stats)); + + pCmd->stats->lastRssi = LRF_RSSI_INVALID; + pCmd->stats->numAntennaPath = antennaEntry->numPath; + } + + /* Mode */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_MODE) = ((pCmd->mode.role << PBE_BLE_CS_RAM_MODE_ROLE_S) & PBE_BLE_CS_RAM_MODE_ROLE_M) | + ((pCmd->mode.phy << PBE_BLE_CS_RAM_MODE_PHY_S) & PBE_BLE_CS_RAM_MODE_PHY_M) | + ((pCmd->mode.repeatSteps << PBE_BLE_CS_RAM_MODE_INFINIT_S) & PBE_BLE_CS_RAM_MODE_INFINIT_M) | + ((pCmd->mode.nSteps << PBE_BLE_CS_RAM_MODE_NUM_STEPS_S) & PBE_BLE_CS_RAM_MODE_NUM_STEPS_M); + + /* Antenna */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANTN) = antennaEntry->numPath; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANTMSK) = pCmd->antennaConfig.gpoMask; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANT0) = pCmd->antennaConfig.gpoVal[0]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANT1) = pCmd->antennaConfig.gpoVal[1]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANT2) = pCmd->antennaConfig.gpoVal[2]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_ANT3) = pCmd->antennaConfig.gpoVal[3]; + + /* Timing */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TFCS) = pCmd->timing.tFcs - (TPLT + config->tStartup); // Pilot tone + startup time is included into the TFCS budget + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TFM) = pCmd->timing.tFm; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TPM) = pCmd->timing.tPm; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TIP1) = pCmd->timing.tIp1; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TIP2) = pCmd->timing.tIp2; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSW) = pCmd->timing.tSw; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSWADJA) = pCmd->timing.tSwAdjustA; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSWADJB) = pCmd->timing.tSwAdjustB; + + /* Timegrid adjustment shall be initialized with maximum unsigned value (ca. 536s @ 4MHz) */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPACCTHRH)= 0x7FFF; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPACCTHRL)= 0xFFFF; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPACCH) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPACCL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPCOMP) = 0; + + /* Initialize MOD.FOFF values. Usueful for sub-events without mode 0 steps */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFSUM) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFNUM) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_RSSILAST) = LRF_RSSI_INVALID; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_RSSISUM0) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_RSSINUM0) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_NSTEPSDONE) = 0; + + /* Apply override if configured */ + if (pCmd->frontend.foffOverrideEnable) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFSUM) = pCmd->frontend.foffOverride; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFNUM) = (1 << 15) | 1; // [15]=Enable, [1]=NUM hardcoded to 1 + } + + /* Program frequency dependent config: hardcode on 2440MHz, to be updated on the fly */ + HWREG_WRITE_LRF(LRFDMDM32_BASE + LRFDMDM32_O_DEMFRAC1_DEMFRAC0) = 0x0D800000; // P: Constant + HWREG_WRITE_LRF(LRFDMDM32_BASE + LRFDMDM32_O_DEMFRAC3_DEMFRAC2) = 0x0E4C0000; // Q: Being dynammically scaled by RFE per channel + + /* Shaper gain */ + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_MOD0) = 0x1824; + + /* Configure AGC with gain=15/7 or a static value=gain/gain */ + uint16_t rxGain = pCmd->frontend.rxGain; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE0) = (rxGain == 0) + ? (0x30F7) + : ((rxGain << 4) | rxGain); + + uint8_t lutIdx = RCL_CmdBleCs_Tpm_40us; + if (pCmd->timing.tPm <= RCL_BLE_CS_US_TO_MCE_TIMER(20)) + { + lutIdx = RCL_CmdBleCs_Tpm_20us; + } + if (pCmd->timing.tPm <= RCL_BLE_CS_US_TO_MCE_TIMER(10)) + { + lutIdx = RCL_CmdBleCs_Tpm_10us; + } + + /* MAFC gain */ + #ifdef DeviceFamily_CC27XX + /* Workaround for IQ swap */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC2) = config->demmisc2 | LRFDMDM_DEMMISC2_PDIFIQCONJEN; + #else + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC2) = config->demmisc2; + #endif + + /* Channel filter = 0.33 */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMMISC1) = 0x0001; + + /* Fife IIR adaptation rate = 64 (provides good mode-0 frequency tolerance for both PHYs) */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMFIFE0) = 0x0007; + + /* Use precalibration values or mode-0 estimates */ + if ((pCmd->precalTable) && (pCmd->precalTable->valid)) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_SPARE1) = (1<<8); + } + else + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_SPARE1) = 0; + } + + /* Baudrate specific settings */ + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_SPARE0) = config->pctConfig[lutIdx].val; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_BAUD) = config->baud; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODSYMMAP0) = config->symmap; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE3) = config->magnConfig[lutIdx].val; + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_RSSIOFFSET) = config->rssioffset; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_DEMMISC3) = config->demmisc3; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV1) = config->tPostProcessDiv1; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TPOSTPROCESSDIV12) = config->tPostProcessDiv12; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXTIMEOUTI0) = config->tRxTimeoutI0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXTIMEOUTI3) = config->tRxTimeoutI3; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TPILOTADJ) = config->tPilotAdjust; + + /* Alias for dynamic parameters for calculations */ + uint16_t tIp1 = pCmd->timing.tIp1; + uint16_t tIp2 = pCmd->timing.tIp2; + uint16_t tFm = pCmd->timing.tFm; + uint16_t tPm = pCmd->timing.tPm; + uint16_t tFcs = pCmd->timing.tFcs; + uint16_t tSw = pCmd->timing.tSw; + uint16_t nPath = antennaEntry->numPath; + + /* Phy specific delays */ + uint16_t tStartup = config->tStartup; + uint16_t tPkt = config->tPacket; + uint16_t tCorr = config->tCorr; + uint16_t tDem = config->tDem; + uint16_t tTr = config->tTr; + uint16_t tFidc = config->tFidc; + uint16_t tTxModDelay = config->tTxModDelay; + uint16_t tInfiniteRx = config->tInfiniteRx; + + /* Modulation + Demodulation delay for timestamp capturing */ + uint16_t tTimestampDelay1 = config->tTimestampDelay1; + uint16_t tTimestampDelay3 = config->tTimestampDelay3; + + /* Calculate base terms of step duration for each mode. + Later can be extended with optional payload per step before sending it over to the PBE. */ + tStepLut[RCL_CmdBleCs_StepMode_0] = (tFcs + ((tPkt + TRD) << 1) + TGD + tIp1 + tFm); + tStepLut[RCL_CmdBleCs_StepMode_1] = (tFcs + ((tPkt + TPYL + TRD) << 1) + tIp1); + tStepLut[RCL_CmdBleCs_StepMode_2] = (tFcs + ((((tPm + tSw) * (nPath + 1)) + TRD) << 1) + tIp2); + tStepLut[RCL_CmdBleCs_StepMode_3] = (tFcs + ((tPkt + TPYL + TGD + ((tPm + tSw) * (nPath + 1)) + TRD) << 1) + tIp2); + + /* Adjustment of MCE timegrid */ + const RCL_Tadjust_t *tAdj = &config->tAdj[pCmd->mode.role]; + + if (pCmd->mode.role == RCL_CmdBleCs_Role_Initiator) + { + /* Calculate base terms of interlude period. Later will scale with payload. */ + + /* TX */ + tAdjALut[RCL_CmdBleCs_StepMode_0] = tAdj->mode0[0] + 0xFFFF; + tAdjALut[RCL_CmdBleCs_StepMode_1] = tAdj->mode1[0] + 0xFFFF; + tAdjALut[RCL_CmdBleCs_StepMode_2] = tAdj->mode2[0] + 0x0000; // No packet, variable used for pilot adjustment + tAdjALut[RCL_CmdBleCs_StepMode_3] = tAdj->mode3[0] + 0xFFFF; + + /* RX */ + tAdjBLut[RCL_CmdBleCs_StepMode_0] = tAdj->mode0[1] + TRD + tIp1 - TPLT; + tAdjBLut[RCL_CmdBleCs_StepMode_1] = tAdj->mode1[1] + TRD + tIp1 - TPLT; + tAdjBLut[RCL_CmdBleCs_StepMode_2] = tAdj->mode2[1] + TRD + tIp2 + tSw + tFidc; + tAdjBLut[RCL_CmdBleCs_StepMode_3] = tAdj->mode3[1] + TRD + tIp2 + tSw + tFidc; + + /* ToAD common term */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_0] = 0; /* NA, no RTT defined */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_1] = TPYL + TRD + tIp1 + tPkt + tTimestampDelay1; + tRttAdjustLut[RCL_CmdBleCs_StepMode_2] = 0; /* NA, no RTT defined */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_3] = TPYL + (TGD << 1) + (((tPm + tSw) * ((nPath << 1) + 1))) + TRD + tIp2 + tPkt + tTimestampDelay3; + + /* Initiator: timeout is hardcoded in the MCE in order to comply with the static timegrid. + This parameter is therefor ignored. */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXTIMEOUTR013) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXWIDENINGR0) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPREMAININGR0) = 0; + } + else + { + /* RX */ + tAdjALut[RCL_CmdBleCs_StepMode_0] = tAdj->mode0[0] - tCorr + tTr + TRD + tIp1 - TPLT - tTxModDelay; + tAdjALut[RCL_CmdBleCs_StepMode_1] = tAdj->mode1[0] - tCorr + tTr + TRD + tIp1 - TPLT - tTxModDelay; + tAdjALut[RCL_CmdBleCs_StepMode_2] = tAdj->mode2[0] + tStartup + TPLT + tSw + tFidc; + tAdjALut[RCL_CmdBleCs_StepMode_3] = tAdj->mode3[0] - tCorr + tTr + TGD + tSw + tFidc; + + /* TX */ + tAdjBLut[RCL_CmdBleCs_StepMode_0] = tAdj->mode0[1]; + tAdjBLut[RCL_CmdBleCs_StepMode_1] = tAdj->mode1[1]; + tAdjBLut[RCL_CmdBleCs_StepMode_2] = tAdj->mode2[1] - tFidc - tSw /* + TRD */ + tIp2 - TPLT; // Ramp-down delay is added by the topSM + tAdjBLut[RCL_CmdBleCs_StepMode_3] = tAdj->mode3[1] - tFidc - tSw /* + TRD */ + tIp2 - TPLT - tTxModDelay; + + /* ToAD common term */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_0] = 0; /* NA, no RTT defined */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_1] = TPYL + TRD + tIp1 + tPkt - tTimestampDelay1; + tRttAdjustLut[RCL_CmdBleCs_StepMode_2] = 0; /* NA, no RTT defined */ + tRttAdjustLut[RCL_CmdBleCs_StepMode_3] = TPYL + (TGD << 1) + (((tPm + tSw) * ((nPath << 1) + 1))) + TRD + tIp2 + tPkt - tTimestampDelay3; + + /* The miminum value is defined by the static timegrid. Different for each datarate and implemented by the MCE. */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXTIMEOUTR013) = config->tRxTimeoutRn; + + /* Handle infinite/extended RX timeout implemented by PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TRXWIDENINGR0) + = (pCmd->timing.tRxWideningR0 == 0xFFFF) + ? (0xFFFF) + : RCL_BLE_CS_MCE_TIMER_TO_PBE_TIMER(tFcs + (tPkt - tTr) + tDem + T3US + pCmd->timing.tRxWideningR0); + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_TSTEPREMAININGR0) = + RCL_BLE_CS_MCE_TIMER_TO_PBE_TIMER(0 - tDem + tTr + TRD + tIp1 + tPkt + TGD + tFm + TRD - tInfiniteRx); + } + + /* Adjustment of antenna control per mode per phy */ + const RCL_Tadjust_t *tAnt = &config->tAnt[pCmd->mode.role & 1]; + + tAntALut[RCL_CmdBleCs_StepMode_0] = 0; /* NA - no antenna */ + tAntALut[RCL_CmdBleCs_StepMode_1] = 0; /* NA - no antenna */ + tAntALut[RCL_CmdBleCs_StepMode_2] = tAnt->mode2[0] + TPLT; + tAntALut[RCL_CmdBleCs_StepMode_3] = tAnt->mode3[0] + TPLT + tPkt + TGD; + + tAntBLut[RCL_CmdBleCs_StepMode_0] = 0; /* NA - no antenna */ + tAntBLut[RCL_CmdBleCs_StepMode_1] = 0; /* NA - no antenna */ + tAntBLut[RCL_CmdBleCs_StepMode_2] = tAnt->mode2[1]; + tAntBLut[RCL_CmdBleCs_StepMode_3] = tAnt->mode3[1]; + + /* Enforce modulator and demodulator clock. RTL bug with automatic control. */ + LRF_setRclClockEnable(LRFDDBELL_CLKCTL_DEM_M | LRFDDBELL_CLKCTL_MOD_M); +} + +/* + * ======== Preprocess the step ======== + */ +static void RCL_Handler_BLE_CS_preprocessStep(RCL_CmdBleCs *pCmd, RCL_CmdBleCs_Step *pStep, RCL_CmdBleCs_Step_Internal *pStepI) +{ + /* Decompress the HCI format into PBE internal format */ + pStepI->channelIdx = pStep->channelIdx; + pStepI->mode = pStep->mode; + pStepI->antennaPermIdx = pStep->antennaPermIdx; + pStepI->toneExtension = pStep->toneExtension; + pStepI->payloadLen = pStep->payloadLen; + pStepI->aaTx = pStep->aaTx; + pStepI->aaRx = pStep->aaRx; + + for (uint8_t i=0; ipayloadTx[i] = pStep->payloadTx[i]; + pStepI->payloadRx[i] = pStep->payloadRx[i]; + } + + /* Disable restricted channels if filtering is turned on */ + if (pCmd->mode.chFilterEnable == true) + { + uint16_t channelIdx = pStepI->channelIdx; + + if ( channelIdx > BLE_CS_MAX_CHANNEL + || channelIdx == 0 /* Advertisement frequency (channel 37)*/ + || channelIdx == 1 + || channelIdx == 23 + || channelIdx == 24 /* Advertisement frequency (channel 38)*/ + || channelIdx == 25 + || channelIdx == 77 + || channelIdx == 78 /* Advertisement frequency (channel 39)*/) + { + /* The user configured a channel outside the allowed domain or + a restricted channel. Guard channels also covered! + We still keep the timegrid but silence this step. */ + pStepI->channelIdx = BLE_CS_SILENT_CHANNEL; + } + } + + /* Decode the base term for the complete duration of the step */ + uint32_t tStep = tStepLut[pStepI->mode]; + uint16_t tAdjA = tAdjALut[pStepI->mode]; + uint16_t tAdjB = tAdjBLut[pStepI->mode]; + + /* Scale with bit length and 1M/2M rate */ + uint16_t tPyl = (payloadLut[pStepI->payloadLen]) >> pCmd->mode.phy; + + /* Extend with timing of optional payload */ + if (pStepI->payloadLen) + { + /* Adjustment only on Reflector */ + uint16_t tAdj = (pCmd->mode.role == RCL_CmdBleCs_Role_Reflector) + ? (tPyl) + : (0); + + /* Payload is only allowed for certain modes. */ + if (pStepI->mode == RCL_CmdBleCs_StepMode_1 || + pStepI->mode == RCL_CmdBleCs_StepMode_3) + { + /* Multiplied by two for combined effect of TX and RX */ + tStep += (tPyl << 1); + + /* The duration from AA sync until the next activity scales with payload on reflector only */ + tAdjA += tAdj; + } + else + { + /* Enforce no payload for mode 0 & 2 */ + pStepI->payloadLen = 0; + + /* No adjustment needed */ + tPyl = 0; + } + } + + /* Configure the PBE with the scaled step duration */ + pStepI->tStep = (uint16_t) RCL_BLE_CS_MCE_TIMER_TO_PBE_TIMER(tStep); + + /* Configure the MCE with the scaled intermediate timegrid parameters */ + pStepI->tAdjustA = tAdjA; + pStepI->tAdjustB = tAdjB; + + /* Antenna timing from beginning of step */ + pStepI->tAntennaA = tAntALut[pStepI->mode] + tPyl; + pStepI->tAntennaB = tAntBLut[pStepI->mode]; + + /* DC compensation */ + if ((pCmd->precalTable) && (pCmd->precalTable->valid)) + { + pCmd->precalTable->callback(pCmd->precalTable, pStepI->channelIdx, (uint32_t *)&pStepI->dcComp[0], (uint32_t *)&pStepI->dcComp[1]); + } + else + { + pStepI->dcComp[0].i = 0; + pStepI->dcComp[0].q = 0; + pStepI->dcComp[1].i = 0; + pStepI->dcComp[1].q = 0; + } + + /* Antenna calculations */ + pStepI->antennaSequence = 0; + + /* Decode mapping of configuration to antennas */ + const RCL_AntennaConfig_t *antennaEntry = &antennaConfig[pCmd->antennaConfig.select]; + + /* Avoid indexing out of range */ + if (pStepI->antennaPermIdx < antennaEntry->numPerm) + { + /* Find the proper permutation pattern based on generic config and random step related selection. + The same table is used, but we index the entries differently */ + uint8_t apn = antennaPermutation[pStepI->antennaPermIdx * antennaEntry->increment].apn; + + /* We reuse the same permutation table for 1:1, 1:N, N:1 and 2:2, + but only use the appropriate number of entries from each row */ + for(uint8_t k1=0; k1numPath; k1++) + { + uint8_t apm = antennaEntry->ap[pCmd->mode.role & 1].apn; + + /* Decode bitfields */ + uint8_t k2 = DECODE_ANTENNA(apn, k1); + uint8_t k3 = DECODE_ANTENNA(apm, k2); + + /* Antenna sequence is stored as [7:6]=A4, [5:4]=A3, [3:2]=A2, [1:0]=A1. + The PBE will decode it accordingly. */ + pStepI->antennaSequence |= ENCODE_ANTENNA(k3, k1); + } + } + + /* Look up the frequency offset actuation error (only used by mode 0) */ + pStepI->foffErr = (uint16_t) foffErrorLut[pStepI->channelIdx]; +} + +/* + * ======== Fetch the next available step result container in the list and return a pointer to it ======== + */ +static RCL_CmdBleCs_StepResult_Internal* RCL_Handler_BLE_CS_fetchNextStepResult(RCL_CmdBleCs *pCmd) +{ + RCL_CmdBleCs_StepResult_Internal *pResult = NULL; + + if ((pCmd->stats->nResultsRead < pCmd->mode.nSteps) && pCmd->results) + { + pResult = &pCmd->results[pCmd->stats->nResultsRead]; + } + + return (pResult); +} + +/* + * ======== RCL_Handler_BLE_CS_convertFreqOffset ======== + */ +static int16_t RCL_Handler_BLE_CS_convertFreqOffset(int16_t foffMeasured) +{ + /* Intermediate arithmetics on 32bit + freqOffset = foff * 100 * 1e6 / 2^23 + = foff * (100 * 1e6 / 2^7) / 2^16 + = foff * 0xBEBC2 / 2^16 [0.01 ppm] */ + int32_t freqOffset = (int32_t)foffMeasured; + freqOffset *= 0xBEBC2; + freqOffset >>= 16; + + return (int16_t)(freqOffset); +} + +/* + * ======== RCL_Handler_BLE_CS_convertRtt ======== + */ +static int16_t RCL_Handler_BLE_CS_convertRtt(RCL_CmdBleCs *pCmd, uint8_t mode, int8_t channel, int16_t foff, uint8_t payloadLen, bool secondToneExtensionSlot, + float toAD, uint16_t corrBefore, uint16_t corrPeak, uint16_t corrAfter) +{ + /* Raw RTT need to be compensated with: + - Correlator before/after fractional approximation + - Nominal tunr-around time T = TSY + TIP + TEXT + TPYL + ... + - Time drift due to XTAL offset (initiator only) + - CMIX (channel specific) and layout related errors */ + + /* Conversion from 4M/8M baudrate to 48M clock tick */ + uint8_t baud2tick = (pCmd->mode.phy) ? (6) : (12); + + /* Quadratic interpolation with correlator values */ + float corr = (float)(baud2tick * (corrBefore - corrAfter)) + / (float)((corrAfter << 1) + (corrBefore << 1) - (corrPeak << 2)); + + /* Compensation applies with different sign */ + toAD += (pCmd->mode.role == RCL_CmdBleCs_Role_Initiator) ? (+corr) : (-corr); + + /* Remove nominal turn-around time (adjust to the signal on the antenna) */ + toAD -= tRttAdjustLut[mode]; + + /* Adjust with optional payload duration */ + toAD -= (payloadLut[payloadLen] >> pCmd->mode.phy); + + /* Adjust with optional tone-extension slot for mode-3 */ + if (secondToneExtensionSlot == true) + { + toAD -= (pCmd->timing.tPm + pCmd->timing.tSw); + } + + /* Adjust initiator */ + if (pCmd->mode.role == RCL_CmdBleCs_Role_Initiator) + { + /* XTAL offset related drift */ + //toAD *= 100e6/(100e6 + foff); //TODO: This takes to much execution time + } + + /* Channel specific delays */ + #define CHANNEL_MID (float)(40.0) + #define CHANNEL_CAL (float)(0.0415) + float adj = CHANNEL_CAL * (channel - CHANNEL_MID); + toAD -= (pCmd->mode.role == RCL_CmdBleCs_Role_Initiator) ? (-adj) : (+adj); + + /* Convert to 0.5ns units as per HCI spec requires */ + toAD *= (float)41.6666; + + /* Round */ + toAD += (float)0.5; + + /* Return the adjusted timeticks */ + return ((int16_t) toAD); +} + +/* + * ======== RCL_Handler_BLE_CS_rotateVector ======== + */ +void RCL_Handler_BLE_CS_rotateVector(int16_t *pct_i, int16_t *pct_q, int16_t theta) +{ + /* Quickly return if nothing to do */ + if (theta != 0) + { + /* CORDIC implementation of rotating a vector with given angle + * + * theta = 16bit representation of the angle in [-pi = -32768, +pi = 32767] range to rotate the PCT with + * pct_i = I component of PCT + * pct_q = Q component of PCT + * */ + #define PI_div2 (1 << (16-2)) + + /* The LUT and normalization factor is generated by the following python expression: + * + * f = 1.0 + * for i in range(NBITS): + * x = np.arctan(1 / 2**i) / (np.pi/2) * (2**NBITS) + * atanLut += [ (np.floor)(x + 0.5) ] + * + * f = (f * (2**(2*i) + 1)) / 2**(2*i) + * + * f = 1/np.sqrt(f) * (2**NBITS) + * K = (np.floor) (f + 0.5) + * */ + #define NBITS (14) + #define K14 (9949) + const uint16_t atanLut[NBITS] = { 8192, 4836, 2555, 1297, 651, 326, 163, 81, 41, 20, 10, 5, 3, 1 }; + + /* Swap coordinates when angle is between [-pi,-pi/2] or [pi/2,pi] */ + int32_t x = ((int32_t) *pct_i); + int32_t y = ((int32_t) *pct_q); + if (theta > PI_div2) + { + theta -= PI_div2; + x = -((int32_t) *pct_q); + y = +((int32_t) *pct_i); + } + else if (theta < (-PI_div2)) + { + theta += PI_div2; + x = +((int32_t) *pct_q); + y = -((int32_t) *pct_i); + } + x *= K14; + y *= K14; + + /* Initialize local variables */ + int32_t x1 = 0; + int32_t y1 = 0; + + /* The direction follows the mathematical positive direction */ + int32_t phi = (int32_t)(-theta); + + /* Rotate iteratively */ + for (uint8_t i = 0; i < NBITS; i++) + { + if (phi < 0) + { /* Counter-clockwise */ + phi += atanLut[i]; + y1 = y + (x >> i); + x1 = x - (y >> i); + } + else + { /* Clockwise */ + phi -= atanLut[i]; + y1 = y - (x >> i); + x1 = x + (y >> i); + } + + x = x1; + y = y1; + } + + /* Scale according to LUT normalization weight */ + *pct_i = (x >> NBITS); + *pct_q = (y >> NBITS); + } +} + +/* + * ======== RCL_Handler_BLE_CS_convertPct ======== + */ +static uint32_t RCL_Handler_BLE_CS_convertPct(int16_t pct_i, int16_t pct_q, uint8_t channelIdx) +{ + /* Calibrate via the t_picosec parameter */ + #define t_picosec (uint64_t)(1000) + #define t_picosec_ (uint64_t)(t_picosec * 3/2) + #define t_const (uint64_t)((t_picosec_ << 31) / 1e6) + #define t_scaler (15) + #define CALC_ANGLE(ch) (-(int16_t)((((uint64_t)ch) * t_const) >> t_scaler)) + + /* Adjust the phase to the signal on the antenna (group delay and layout) */ + RCL_Handler_BLE_CS_rotateVector(&pct_i, &pct_q, CALC_ANGLE(channelIdx)); + + /* Compress PCTs to 24bit */ + uint32_t pct = (((pct_q >> 1) & 0x0FFF) << 12) + | ( (pct_i >> 1) & 0x0FFF); + + return (pct); +} + +/* + * ======== RCL_Handler_BLE_CS_convertPctQuality ======== + */ +static uint8_t RCL_Handler_BLE_CS_convertPctQuality(uint16_t qMin, uint16_t qMax, uint16_t qAvg, bool toneExtensionSlot, bool toneExpected) +{ + /* Initialize with unavailable */ + uint8_t tnQ = RCL_CmdBleCs_ToneQuality_Unavailable; + + /* Avoid zero-division. Metric is unavailable. Also for Initiator mode-3. */ + if (qAvg != 0) + { + /* Calculate Q3 scale */ + uint8_t Q3 = 100 * (qMax - qMin)/qAvg; + + /* Classify based on thresholds */ + if (Q3 < BLE_CS_TONE_QUALITY_GOOD_THR) tnQ = RCL_CmdBleCs_ToneQuality_Good; + else if (Q3 < BLE_CS_TONE_QUALITY_MEDIUM_THR) tnQ = RCL_CmdBleCs_ToneQuality_Medium; + else tnQ = RCL_CmdBleCs_ToneQuality_Low; + + /* Add additional flag for the tone extension slot */ + if (toneExtensionSlot) + { + /* Decode the appropriate flag */ + uint8_t toneExtensionFlag = (toneExpected) + ? (RCL_CmdBleCs_ToneExtensionSlot_Enabled_ToneExpected) + : (RCL_CmdBleCs_ToneExtensionSlot_Enabled_NoToneExpected); + + tnQ |= (toneExtensionFlag << 4); + } + } + + return (tnQ); +} + +/* + * ======== RCL_Handler_BLE_CS_estimateStepResultLength ======== + */ +static uint16_t RCL_Handler_BLE_CS_estimateStepResultLength(RCL_CmdBleCs *pCmd, RCL_CmdBleCs_StepResult_Internal* src) +{ + /* Information extracted from registers */ + uint8_t role = pCmd->mode.role; + uint8_t numAntennaPath = pCmd->stats->numAntennaPath + 1; // +1 = tone extension + + /* First two fields are mandatory */ + uint16_t length = 0; + + /* Dataformat varies based on the mode. Constants are known from the spec */ + switch (src->mode) + { + case (RCL_CmdBleCs_StepMode_0): + /* Initiator also contains the measured frequency offset */ + length = (role == RCL_CmdBleCs_Role_Initiator) ? sizeof(RCL_CmdBleCs_ResultI0) : sizeof(RCL_CmdBleCs_ResultR0); + break; + case (RCL_CmdBleCs_StepMode_1): + length = sizeof(RCL_CmdBleCs_ResultIR1); + break; + case (RCL_CmdBleCs_StepMode_2): + length = sizeof(RCL_CmdBleCs_ResultIR2) + numAntennaPath * sizeof(RCL_CmdBleCs_Tone); + break; + case (RCL_CmdBleCs_StepMode_3): + length = sizeof(RCL_CmdBleCs_ResultIR3) + numAntennaPath * sizeof(RCL_CmdBleCs_Tone); + break; + } + + return (length); +} + +/* + * ======== RCL_Handler_BLE_CS_convertStepResult ======== + */ +static uint16_t RCL_Handler_BLE_CS_convertStepResult(RCL_CmdBleCs* pCmd, uint8_t *dst, RCL_CmdBleCs_StepResult_Internal* src) +{ + #define NADM_NOT_SUPPORTED 0xFF + #define PACKET_ANTENNA 1 + + uint8_t numAntennaPath = pCmd->stats->numAntennaPath + 1; // +1 = tone extension + + /* Use register access to guarantee the latest-greatest value for the first burst */ + int16_t foff = RCL_Handler_BLE_CS_convertFreqOffset(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_FOFFCOMP) << 2); + + /* Dataformat varies based on the mode */ + uint8_t mode = src->mode; + uint8_t channel = src->channelIdx; + uint8_t payloadLen = src->payloadLen; + uint8_t toneExtension = src->toneExtension; + + /* Mode independent fields */ + *dst++ = mode; + *dst++ = channel; + + /* Remember the address of field 'datalength' and skip it for now, will be filled later */ + uint8_t *dataLength = dst++; + + if (mode == RCL_CmdBleCs_StepMode_0) + { + *dst++ = src->pktResult; /* Packet_AA_Quality */ + *dst++ = src->pktRssi; /* Packet_RSSI */ + *dst++ = PACKET_ANTENNA; /* Packet_Antenna */ + + if (pCmd->mode.role == RCL_CmdBleCs_Role_Initiator) + { + int16_t freqOffset = RCL_Handler_BLE_CS_convertFreqOffset(src->foffMeasured); + *dst++ = INT16_LSB(freqOffset); + *dst++ = INT16_MSB(freqOffset); + } + } + else if (mode == RCL_CmdBleCs_StepMode_1) + { + *dst++ = src->pktResult; /* Packet_AA_Quality */ + *dst++ = NADM_NOT_SUPPORTED; /* Packet_NADM */ + *dst++ = src->pktRssi; /* Packet_RSSI */ + *dst++ = PACKET_ANTENNA; /* Packet_Antenna */ + + /* RTT calculation using correlator values */ + int16_t toAD = RCL_Handler_BLE_CS_convertRtt(pCmd, + RCL_CmdBleCs_StepMode_1, + channel, + foff, + payloadLen, + false, // secondToneExtensionSlot=NA, there are no tones in mode-1 + src->rtt, src->corr[0], src->corr[1], src->corr[2]); + *dst++ = INT16_LSB(toAD); + *dst++ = INT16_MSB(toAD); + } + else if (mode == RCL_CmdBleCs_StepMode_2) + { + *dst++ = src->antennaPermIdx; + for (uint8_t j = 0; j < numAntennaPath; j++) + { + /* Compress PCT to 24bits */ + int16_t i = src->pct[j].i; + int16_t q = src->pct[j].q; + + uint32_t pct = RCL_Handler_BLE_CS_convertPct(i, q, channel); + *dst++ = (uint8_t)((pct) & 0xFF); + *dst++ = (uint8_t)((pct >> 8) & 0xFF); + *dst++ = (uint8_t)((pct >> 16) & 0xFF); + + /* Calculate PCT quality */ + bool toneExtensionSlot = (bool)(j == (numAntennaPath - 1)); + bool toneExpected = (bool)((pCmd->mode.role == RCL_CmdBleCs_Role_Reflector) + ? (toneExtension & BLE_CS_TONE_EXTENSION_INITIATOR_TX) + : (toneExtension & BLE_CS_TONE_EXTENSION_REFLECTOR_TX)); + + uint16_t min = src->magn[j].magnMin; + uint16_t max = src->magn[j].magnMax; + uint16_t avg = src->magn[j].magnAvg; + *dst++ = RCL_Handler_BLE_CS_convertPctQuality(min, max, avg, toneExtensionSlot, toneExpected); + } + } + else if (mode == RCL_CmdBleCs_StepMode_3) + { + /* Packet related data */ + *dst++ = src->pktResult; /* Packet_AA_Quality */ + *dst++ = NADM_NOT_SUPPORTED; /* Packet_NADM */ + *dst++ = src->pktRssi; /* Packet_RSSI */ + *dst++ = PACKET_ANTENNA; /* Packet_Antenna */ + + /* RTT calculation using correlator values */ + int16_t toAD = RCL_Handler_BLE_CS_convertRtt(pCmd, + RCL_CmdBleCs_StepMode_3, + channel, + foff, + payloadLen, + (bool)(toneExtension & 2), + src->rtt, src->corr[0], src->corr[1], src->corr[2]); + *dst++ = INT16_LSB(toAD); + *dst++ = INT16_MSB(toAD); + + /* Tone related data */ + *dst++ = src->antennaPermIdx; + for (uint8_t j = 0; j < numAntennaPath; j++) + { + /* Compress PCT to 24bits */ + int16_t i = src->pct[j].i; + int16_t q = src->pct[j].q; + + uint32_t pct = RCL_Handler_BLE_CS_convertPct(i, q, channel); + *dst++ = (uint8_t)((pct) & 0xFF); + *dst++ = (uint8_t)((pct >> 8) & 0xFF); + *dst++ = (uint8_t)((pct >> 16) & 0xFF); + + /* Calculate PCT quality */ + bool toneExtensionSlot = (bool)(j == (numAntennaPath - 1)); + + /* Mode-3 may or may not have the R->I tone extension present */ + bool toneExpected = (bool)((pCmd->mode.role == RCL_CmdBleCs_Role_Reflector) + ? (toneExtension & BLE_CS_TONE_EXTENSION_INITIATOR_TX) + : (toneExtension & BLE_CS_TONE_EXTENSION_REFLECTOR_TX)); + + uint16_t min = src->magn[j].magnMin; + uint16_t max = src->magn[j].magnMax; + uint16_t avg = src->magn[j].magnAvg; + *dst++ = RCL_Handler_BLE_CS_convertPctQuality(min, max, avg, toneExtensionSlot, toneExpected); + } + } + + /* Fill the Step_Data_Length based on difference of addresses */ + *dataLength = (dst - dataLength - 1); + + /* Return the number of bytes written (+3 = mode&channel&dataLength) */ + return (*dataLength + 3); +} + +/* + * ======== RCL_Handler_BLE_CS_findPbeErrorEndStatus ======== + */ +static RCL_CommandStatus RCL_Handler_BLE_CS_findPbeErrorEndStatus(uint16_t pbeEndStatus) +{ + RCL_CommandStatus status; + switch (pbeEndStatus) + { + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_RXF: + status = RCL_CommandStatus_Error_RxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_TXF: + status = RCL_CommandStatus_Error_TxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_SYNTH: + status = RCL_CommandStatus_Error_Synth; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP: + status = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_PAR: + status = RCL_CommandStatus_Error_Param; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_BADOP: + status = RCL_CommandStatus_Error_UnknownOp; + break; + default: + Log_printf(RclCore, Log_ERROR, "Unexpected error 0x%04X from PBE", pbeEndStatus); + status = RCL_CommandStatus_Error; + break; + } + return (status); +} + +/* + * ======== RCL_Handler_BLE_CS ======== + */ +RCL_Events RCL_Handler_BLE_CS(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBleCs *pCmd = (RCL_CmdBleCs *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + /* Check if valid PLLDIV0 synth setting is used. */ + /* BLE CS currently supports only either 3 => FREF0=16MHz or 12 => FREF0=4MHz */ + uint32_t plldiv0 = (HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_PRE0) & LRFDRFE_PRE0_PLLDIV0_M) >> LRFDRFE_PRE0_PLLDIV0_S; + if ((plldiv0 != 3U) && (plldiv0 != 12U)) + { + /* Override to use PLLDIV0=12, gives FREF0=4MHz */ + Log_printf(RclCore, Log_WARNING, "Unsupported RFE_PRE0_PLLDIV0 synth setting detected. Will override to use 12 (FREF=4MHz)"); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_PRE0) = ((12U << LRFDRFE_PRE0_PLLDIV0_S) & LRFDRFE_PRE0_PLLDIV0_M) | + ((12U << LRFDRFE_PRE0_PLLDIV1_S) & LRFDRFE_PRE0_PLLDIV1_M); + } + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + /* Default end status */ + bleCsHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Enable interrupts (LRF_EventMdmsoft0 => "S2R samples available") */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) = + HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) + | LRF_EventOpDone.value + | LRF_EventOpError.value + | LRF_EventMdmsoft0.value + | LRF_EventRxfifo.value; + + /* Initialize BLE CS specific registers and FIFO */ + RCL_Handler_BLE_CS_preprocessCommand(pCmd); + + /* Configure TX power*/ + if (LRF_programTxPower(pCmd->frontend.txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + /* Configure the BUFRAM fifo size and interrupts */ + RCL_Handler_BLE_CS_configureTxRxFifo(pCmd); + + /* Configure S2R size and mode */ + RCL_Handler_BLE_CS_configureS2R(pCmd); + + /* Fill the first batch of step descriptors into the BUFRAM TX fifo */ + RCL_Handler_BLE_CS_preFillTxBuffer(pCmd); + + /* Post command */ + LRF_waitForTopsmReady(); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_MSGBOX) = 0; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE_CS_REGDEF_API_OP_BLE_CS; + + /* Forward fill more steps */ + RCL_Handler_BLE_CS_preFillTxBuffer(pCmd); + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + /* Read the statistics */ + RCL_Handler_BLE_CS_readStatistics(pCmd); + + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + /* Drain the rx fifo of the final batch of results. Force close the buffer. */ + rclEvents.value |= RCL_Handler_BLE_CS_readWriteBuffer(pCmd, true).value; + } + else + { + if (lrfEvents.rxfifo != 0) + { + /* Read the available results, and issue event if multibuffer is exhausted */ + rclEvents.value |= RCL_Handler_BLE_CS_readWriteBuffer(pCmd, false).value; + } + } + + if (lrfEvents.mdmsoft0 != 0) + { + /* Read S2R samples upon MCE event */ + rclEvents.value |= RCL_Handler_BLE_CS_readS2RSamples(pCmd).value; + } + + if (lrfEvents.opDone != 0) + { + cmd->status = bleCsHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = bleCsHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE_CS_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return (rclEvents); +} + + + +/* + * ======== RCL_Handler_BLE_CS_Precal ======== + */ +RCL_Events RCL_Handler_BLE_CS_Precal(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdBleCs_Precal *pCmd = (RCL_CmdBleCs_Precal *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + /* Default end status */ + bleCsHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Enable interrupts */ + HWREG_WRITE_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) + = HWREG_READ_LRF(LRFDDBELL_BASE + LRFDDBELL_O_IMASK0) + | LRF_EventOpDone.value + | LRF_EventOpError.value; + + RCL_Handler_BLE_CS_configureTxRxFifo(NULL); + + /* Number of channels to calibrate on */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_BLE_CS_RAM_O_MODE) = ((pCmd->table->numEntries << PBE_BLE_CS_RAM_MODE_NUM_STEPS_S) & PBE_BLE_CS_RAM_MODE_NUM_STEPS_M); + HWREG_WRITE_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE0) = pCmd->table->rxGain; + + for (uint8_t j=0; jtable->numEntries; j++) + { + /* 32bit aperture */ + HWREG_WRITE_LRF(LRFDTXF_BASE + LRFDTXF_O_TXD) = pCmd->table->entries[j].channel; + } + + /* Post command */ + LRF_waitForTopsmReady(); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_MSGBOX) = 0; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_BLE_CS_REGDEF_API_OP_PRECAL; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (lrfEvents.opDone != 0) + { + for (uint8_t j=0; jtable->numEntries; j++) + { + /* uint32_t per read via the FIFO */ + uint32_t data = HWREG_READ_LRF(LRFDRXF_BASE + LRFDRXF_O_RXD); + pCmd->table->entries[j].hdc.i = ((data >> 0 ) & 0xFFFF); + pCmd->table->entries[j].hdc.q = ((data >> 16) & 0xFFFF); + + data = HWREG_READ_LRF(LRFDRXF_BASE + LRFDRXF_O_RXD); + pCmd->table->entries[j].ldc.i = ((data >> 0 ) & 0xFFFF); + pCmd->table->entries[j].ldc.q = ((data >> 16) & 0xFFFF); + } + + /* Validate the table */ + pCmd->table->valid = 1; + + cmd->status = bleCsHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + /* Invalidate the table */ + pCmd->table->valid = 0; + + RCL_CommandStatus endStatus = bleCsHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_BLE_CS_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + } + return (rclEvents); +} + +/* + * ======== RCL_Handler_BLE_CS_PrecalDefaultCallback ======== + */ +void RCL_Handler_BLE_CS_PrecalDefaultCallback(RCL_CmdBleCs_PrecalTable *table, uint8_t channel, uint32_t *hdc, uint32_t *ldc) +{ + *hdc = 0; + *ldc = 0; + + if (channel <= BLE_CS_MAX_CHANNEL) + { + /* Default channel blocks : 10-30-50-70 MHz */ + #define BLE_CS_PRECAL_BIN_WIDTH 20 + + uint8_t k = channel / BLE_CS_PRECAL_BIN_WIDTH; + + if (k < table->numEntries) + { + /* Populate the DC measured with high gain */ + uint32_t i = table->entries[k].hdc.i; + uint32_t q = table->entries[k].hdc.q; + *hdc = (q << 16 | i); + + i = table->entries[k].ldc.i; + q = table->entries[k].ldc.q; + *ldc = (q << 16 | i); + } + } +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.h b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.h new file mode 100644 index 00000000..cea0f3ad --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ble_cs.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_handlers_ble_cs_h__include +#define ti_drivers_RCL_handlers_ble_cs_h__include + +#include +#include +#include + +/* Handler functions */ +RCL_Events RCL_Handler_BLE_CS(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_BLE_CS_Precal(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); + +#endif /* ti_drivers_RCL_handlers_ble_cs_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.c b/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.c new file mode 100644 index 00000000..98d91614 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.c @@ -0,0 +1,2219 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== generic.c ======== + */ + +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_lrfdtxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/pbe_generic_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_generic_regdef_regs.h) + +/** Polynomial to use for PRBS15 data */ +#define RCL_HANDLER_GENERIC_PRBS15_POLY 0x80020000 +/** Polynomial to use for PRBS32 data */ +#define RCL_HANDLER_GENERIC_PRBS32_POLY 0x00400007 +#define RCL_HANDLER_GENERIC_PRBS_INIT 0x00005555 +#define RCL_HANDLER_GENERIC_PRBS_SYNC 0xAB05FA1C + +#define RCL_HANDLER_GENERIC_RESTORE_NONE 0x0000 +#define RCL_HANDLER_GENERIC_RESTORE_MODCTRL 0x0001 +#define RCL_HANDLER_GENERIC_RESTORE_WHITEN_INIT 0x0002 +#define RCL_HANDLER_GENERIC_RESTORE_WHITEN_POLY 0x0004 + + +struct +{ + struct { + uint16_t txFifoSize; + uint16_t rxFifoSize; + RCL_CommandStatus endStatus; + bool activeUpdate; + bool powerConstraintsSet; + RCL_MultiBuffer *curBuffer; + } common; + union { + struct { + bool gracefulStopObserved; + bool stopFs; + uint32_t txCount; + uint32_t period; + } tx; + struct { + uint16_t restoreOpt; + uint16_t storedWhitenInit; + uint32_t storedWhitenPoly; + } txTest; + struct { + uint32_t longOkCount; + uint32_t longNokCount; + uint16_t demc1be1; + uint16_t demc1be2; +#ifdef DeviceFamily_CC27XX + uint16_t demc1be12; +#endif + bool restoreThresh; + } rx; + struct { + uint32_t longTxCount; + uint32_t longOkCount; + uint32_t longNokCount; + uint32_t longRxIgnoredCount; + uint32_t longRxAddrMismatchCount; + uint32_t longRxBufFullCount; + } nesb; + }; +} genericHandlerState; + + +static void RCL_Handler_Generic_setSynthPowerState(bool fsOff); +static void RCL_Handler_Generic_updateRxCurBufferAndFifo(List_List *rxBuffers); +static RCL_CommandStatus RCL_Handler_Generic_findPbeErrorEndStatus(uint16_t pbeEndStatus); +static uint32_t RCL_Handler_Generic_updateTxBuffers(List_List *txBuffers, uint32_t maxBuffers); +static uint32_t RCL_Handler_Generic_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate); +static void RCL_Handler_Generic_updateRxStats(RCL_StatsGeneric *stats, uint32_t startTime); +static void RCL_Handler_Generic_updateLongStats(void); +static bool RCL_Handler_Generic_initRxStats(RCL_StatsGeneric *stats, uint32_t startTime); +static uint32_t RCL_Handler_Generic_updateSyncWord(uint32_t syncWord); +static void RCL_Handler_Nesb_updateHeader(List_List *txBuffers, uint8_t autoRetransmitMode, + uint8_t hdrConf, uint8_t seqNumber); +static void RCL_Handler_Nesb_updateStats(RCL_StatsNesb *stats, uint32_t startTime); +static void RCL_Handler_Nesb_updateLongStats(void); +static bool RCL_Handler_Nesb_initStats(RCL_StatsNesb *stats, uint32_t startTime); + +/* + * ======== RCL_Handler_Generic_Fs ======== + */ +RCL_Events RCL_Handler_Generic_Fs(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdGenericFs *fsCmd = (RCL_CmdGenericFs *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + /* Program frequency word */ + LRF_programFrequency(fsCmd->rfFrequency, fsCmd->fsType == RCL_FsType_Tx); + + /* Enable radio */ + LRF_enable(); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = 0 << PBE_GENERIC_RAM_OPCFG_START_S; + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting FS"); + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_FS; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + cmd->status = genericHandlerState.common.endStatus; + + RCL_Handler_Generic_setSynthPowerState(false); + + /* Set additional power constraints if necessary */ + if(!genericHandlerState.common.powerConstraintsSet) + { + genericHandlerState.common.powerConstraintsSet = true; + hal_power_set_constraint(); + } + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + RCL_Handler_Generic_setSynthPowerState(true); + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_FsOff ======== + */ +RCL_Events RCL_Handler_Generic_FsOff(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + /* Enable radio */ + LRF_enable(); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setCmdStopTimeNoStartTrigger(cmd); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = 0; + + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Turning off FS"); + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOPFS; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (lrfEvents.opDone != 0) + { + cmd->status = RCL_CommandStatus_Finished; + RCL_Handler_Generic_setSynthPowerState(true); + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_Tx ======== + */ +RCL_Events RCL_Handler_Generic_Tx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdGenericTx *txCmd = (RCL_CmdGenericTx *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if ((txCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(txCmd->syncWord); + uint32_t opCfgVal = + (0 << PBE_GENERIC_RAM_OPCFG_TXINFINITE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_TXPATTERN_S) | + (2 << PBE_GENERIC_RAM_OPCFG_TXFCMD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_START_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_S) | + (0 << PBE_GENERIC_RAM_OPCFG_NEXTOP_S) | + (1 << PBE_GENERIC_RAM_OPCFG_SINGLE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S); + + if (txCmd->config.fsOff != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + if (txCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = (PBE_GENERIC_RAM_NESB_NESBMODE_OFF); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + /* Program frequency word */ + if (txCmd->rfFrequency != 0) + { + LRF_programFrequency(txCmd->rfFrequency, true); + } + if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enable radio */ + LRF_enable(); + + /* Initialize RF FIFO */ + genericHandlerState.common.txFifoSize = LRF_prepareTxFifo(); + + /* Enter payload */ + uint32_t nBuffer = RCL_Handler_Generic_updateTxBuffers(&txCmd->txBuffers, 1); + if (nBuffer == 0) + { + cmd->status = RCL_CommandStatus_Error_MissingTxBuffer; + rclEvents.lastCmdDone = 1; + } + else + { + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting TX"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_TX; + } + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + /* Pop transmitted packet */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&txCmd->txBuffers); + if (txBuffer != NULL) + { + txBuffer->state = RCL_BufferStateFinished; + } + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(txCmd->config.fsOff); + } + return rclEvents; +} + +RCL_Events RCL_Handler_Generic_TxRepeat(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdGenericTxRepeat *txCmd = (RCL_CmdGenericTxRepeat *) cmd; + RCL_Events rclEvents = {.value = 0}; + bool runTx = false; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if ((txCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else if ((txCmd->rfFrequency == 0) && (txCmd->config.fsRecal != 0)) + { + /* Synth not to be programmed, recalibration for each packet requested */ + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(txCmd->syncWord); + /* Handle FS off in the end, so disable it in PBE */ + uint32_t opCfgVal = + (0 << PBE_GENERIC_RAM_OPCFG_TXINFINITE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_TXPATTERN_S) | + (1 << PBE_GENERIC_RAM_OPCFG_TXFCMD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_START_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S) | + (0 << PBE_GENERIC_RAM_OPCFG_NEXTOP_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S) | + (1 << PBE_GENERIC_RAM_OPCFG_SINGLE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S); + + if (txCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + if (txCmd->config.fsRecal != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = (PBE_GENERIC_RAM_NESB_NESBMODE_OFF); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + genericHandlerState.tx.stopFs = false; + genericHandlerState.tx.txCount = 0; + + /* Program frequency word */ + if (txCmd->rfFrequency != 0) + { + LRF_programFrequency(txCmd->rfFrequency, true); + } + if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enable radio */ + LRF_enable(); + + /* Initialize RF FIFO */ + genericHandlerState.common.txFifoSize = LRF_prepareTxFifo(); + + /* Enter payload */ + if (txCmd->txEntry == NULL) + { + cmd->status = RCL_CommandStatus_Error_MissingTxBuffer; + rclEvents.lastCmdDone = 1; + } + else + { + uint32_t length = txCmd->txEntry->length; + /* Number of words including length field and end padding */ + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(length) / 4; + if (wordLength > LRF_getTxFifoWritable() / 4) + { + /* Packet will not fit */ + /* TODO: See RCL-348 */ + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + else { + LRF_writeTxFifoWords((uint32_t *) txCmd->txEntry, wordLength); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + genericHandlerState.tx.period = txCmd->timePeriod; + + runTx = true; /* Go on */ + genericHandlerState.tx.gracefulStopObserved = false; + if (rclSchedulerState.gracefulStopInfo.cmdStopEnabled || rclSchedulerState.gracefulStopInfo.schedStopEnabled) + { + /* Enable interrupt to service graceful stop */ + hal_enable_graceful_stop_time_irq(); + } + } + } + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.systim1 != 0) + { + genericHandlerState.tx.gracefulStopObserved = true; + } + if (lrfEvents.opDone != 0) + { + if (genericHandlerState.tx.stopFs) + { + runTx = false; + } + else { + /* Retry TX FIFO. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = LRFDPBE_FCMD_DATA_TXFIFO_RETRY; + + if (txCmd->numPackets == 0 || genericHandlerState.tx.txCount < txCmd->numPackets) + { + /* Reset PBE */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_INIT) = 1 << LRFDPBE_INIT_TOPSM_S; + + runTx = true; + if (rclEventsIn.hardStop != 0) + { + genericHandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + runTx = false; + } + else if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE) == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP || + genericHandlerState.tx.gracefulStopObserved || + rclEventsIn.gracefulStop != 0) + { + genericHandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + runTx = false; + } + else { + RCL_CommandStatus startTimeStatus; + if (genericHandlerState.tx.period != 0) + { + startTimeStatus = RCL_Scheduler_setNewStartRelTime(genericHandlerState.tx.period); + } + else + { + startTimeStatus = RCL_Scheduler_setNewStartNow(); + } + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + genericHandlerState.common.endStatus = startTimeStatus; + runTx = false; + } + } + } + else + { + if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE) == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + genericHandlerState.common.endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + runTx = false; + } + } + if (!runTx && cmd->status == RCL_CommandStatus_Active) + { + if (!genericHandlerState.tx.stopFs && txCmd->config.fsRecal == 0 && txCmd->config.fsOff != 0) + { + /* Send stop FS */ + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOPFS; + genericHandlerState.tx.stopFs = true; + } + else { + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + } + } + else if (lrfEvents.opError != 0) + { + if (genericHandlerState.common.endStatus == RCL_CommandStatus_Finished) + { + genericHandlerState.common.endStatus = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + + if (!genericHandlerState.tx.stopFs && txCmd->config.fsRecal == 0 && txCmd->config.fsOff != 0 && + (HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x01) != 0) + { + /* Synth was turned on, but should be off. Send stop FS */ + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOPFS; + genericHandlerState.tx.stopFs = true; + } + else + { + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + } + else + { + /* Other events need to be handled unconditionally */ + } + + if (runTx) + { + uint32_t txCount = genericHandlerState.tx.txCount; + if (txCount != 0 && txCmd->config.fsRecal == 0) + { + /* Frequency programming only for the first packet */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) | PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M; + } + txCount++; + if (txCount != 0) + { + /* Avoid wraparound */ + genericHandlerState.tx.txCount = txCount; + } + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting TX"); + + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_TX; + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(txCmd->config.fsOff); + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_TxTest ======== + */ +RCL_Events RCL_Handler_Generic_TxTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdGenericTxTest *txCmd = (RCL_CmdGenericTxTest *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + genericHandlerState.txTest.restoreOpt = RCL_HANDLER_GENERIC_RESTORE_NONE; + if ((txCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + uint32_t opCfgVal = + (1 << PBE_GENERIC_RAM_OPCFG_TXINFINITE_S) | + (1 << PBE_GENERIC_RAM_OPCFG_TXPATTERN_S) | + (0 << PBE_GENERIC_RAM_OPCFG_TXFCMD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_START_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S) | + (0 << PBE_GENERIC_RAM_OPCFG_NEXTOP_S) | + (1 << PBE_GENERIC_RAM_OPCFG_SINGLE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S); + + if (txCmd->config.fsOff != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + if (txCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = (PBE_GENERIC_RAM_NESB_NESBMODE_OFF); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enter configuration */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PATTERN) = txCmd->config.txWord; + if (txCmd->config.sendCw != 0) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) | LRFDMDM_MODCTRL_TONEINSERT_M; + genericHandlerState.txTest.restoreOpt = RCL_HANDLER_GENERIC_RESTORE_MODCTRL; + } + else + { + uint32_t whitenMode = txCmd->config.whitenMode; + /* Configure whitening */ + if (whitenMode == RCL_CMD_GENERIC_WH_MODE_NONE) + { + genericHandlerState.txTest.restoreOpt = RCL_HANDLER_GENERIC_RESTORE_WHITEN_INIT; + genericHandlerState.txTest.storedWhitenInit = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_WHITEINIT); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_WHITEINIT) = 0; + /* Use pattern as sync word */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(txCmd->config.txWord | (txCmd->config.txWord << 16)); + } + else + { + if (whitenMode >= RCL_CMD_GENERIC_WH_MODE_PRBS15) + { + genericHandlerState.txTest.restoreOpt = RCL_HANDLER_GENERIC_RESTORE_WHITEN_POLY | RCL_HANDLER_GENERIC_RESTORE_WHITEN_INIT; + genericHandlerState.txTest.storedWhitenPoly = HWREG_READ_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0); + genericHandlerState.txTest.storedWhitenInit = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_WHITEINIT); + if (whitenMode > RCL_CMD_GENERIC_WH_MODE_PRBS15) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = RCL_HANDLER_GENERIC_PRBS15_POLY; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = RCL_HANDLER_GENERIC_PRBS32_POLY; + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_WHITEINIT) = RCL_HANDLER_GENERIC_PRBS_INIT; + } + /* Use pseudo-random sync word (not necessarily matching selected PRBS) */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_HANDLER_GENERIC_PRBS_SYNC; + } + } + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + if (txCmd->rfFrequency != 0) + { + /* Program frequency word */ + LRF_programFrequency(txCmd->rfFrequency, true); + } + + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting infinite TX"); + + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_TX; + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(txCmd->config.fsOff); + if ((genericHandlerState.txTest.restoreOpt & RCL_HANDLER_GENERIC_RESTORE_MODCTRL) != 0) { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) & (~LRFDMDM_MODCTRL_TONEINSERT_M); + } + if ((genericHandlerState.txTest.restoreOpt & RCL_HANDLER_GENERIC_RESTORE_WHITEN_INIT) != 0) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_WHITEINIT) = genericHandlerState.txTest.storedWhitenInit; + } + if ((genericHandlerState.txTest.restoreOpt & RCL_HANDLER_GENERIC_RESTORE_WHITEN_POLY) != 0) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = genericHandlerState.txTest.storedWhitenPoly; + } + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_Rx ======== + */ +RCL_Events RCL_Handler_Generic_Rx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdGenericRx *rxCmd = (RCL_CmdGenericRx *) cmd; + RCL_Events rclEvents = RCL_EventNone; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if ((rxCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(rxCmd->syncWordA); + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCB) = RCL_Handler_Generic_updateSyncWord(rxCmd->syncWordB); + uint32_t opCfgVal = + (0 << PBE_GENERIC_RAM_OPCFG_RXFILTEROP_S) | + (1 << PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_S) | + (1 << PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_S) | + (0 << PBE_GENERIC_RAM_OPCFG_START_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_NOCAL_S) | + (1 << PBE_GENERIC_RAM_OPCFG_FS_KEEPON_S) | + (1 << PBE_GENERIC_RAM_OPCFG_NEXTOP_S) | + (0 << PBE_GENERIC_RAM_OPCFG_SINGLE_S) | + (0 << PBE_GENERIC_RAM_OPCFG_IFSPERIOD_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RXREPEATOK_S) | + (0 << PBE_GENERIC_RAM_OPCFG_RFINTERVAL_S); + + if (rxCmd->config.fsOff != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + if (rxCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + if (rxCmd->config.repeated) + { + opCfgVal |= PBE_GENERIC_RAM_OPCFG_RFINTERVAL_M; + } + else + { + opCfgVal |= PBE_GENERIC_RAM_OPCFG_SINGLE_M; + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = (PBE_GENERIC_RAM_NESB_NESBMODE_OFF); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_MAXLEN) = rxCmd->maxPktLen; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_RXTIMEOUT) = 0; /* No timeout except from SYSTIM */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIRSTRXTIMEOUT) = 0; /* No timeout except from SYSTIM */ + + /* If needed, configure demodulator correlator engine for syncwordA and syncwordB */ + if (rxCmd->config.disableSyncA != 0 || rxCmd->config.disableSyncB != 0) + { + uint16_t demc1be1 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1); + uint16_t demc1be2 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2); +#ifdef DeviceFamily_CC27XX + uint16_t demc1be12 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12); +#endif + genericHandlerState.rx.restoreThresh = true; + genericHandlerState.rx.demc1be1 = demc1be1; + genericHandlerState.rx.demc1be2 = demc1be2; +#ifdef DeviceFamily_CC27XX + genericHandlerState.rx.demc1be12 = demc1be12; +#endif + if (rxCmd->config.disableSyncA != 0) + { + demc1be1 = (demc1be1 & ~LRFDMDM_DEMC1BE1_THRESHOLDA_M) | (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDA_S); + demc1be2 = (demc1be2 & ~LRFDMDM_DEMC1BE2_THRESHOLDC_M) | (0x7F << LRFDMDM_DEMC1BE2_THRESHOLDC_S); +#ifdef DeviceFamily_CC27XX + demc1be12 = (demc1be12 & ~LRFDMDM_DEMC1BE12_THRESHOLDG_M) | (0x7F << LRFDMDM_DEMC1BE12_THRESHOLDG_S); +#endif + } + if (rxCmd->config.disableSyncB != 0) + { + demc1be1 = (demc1be1 & ~LRFDMDM_DEMC1BE1_THRESHOLDB_M) | (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDB_S); + } + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = demc1be2; +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12) = demc1be12; +#endif + } + else + { + genericHandlerState.rx.restoreThresh = false; + } + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + /* Program frequency word */ + if (rxCmd->rfFrequency != 0) + { + LRF_programFrequency(rxCmd->rfFrequency, false); + } + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else { + genericHandlerState.common.activeUpdate = RCL_Handler_Generic_initRxStats(rxCmd->stats, + rclSchedulerState.actualStartTime); + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + genericHandlerState.common.rxFifoSize = LRF_prepareRxFifo(); + genericHandlerState.common.curBuffer = NULL; + if (rxCmd->config.discardRxPackets == 0) + { + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + } + else + { + /* Set FIFO size to maximum */ + LRF_setRxFifoEffSz(genericHandlerState.common.rxFifoSize); + } + + /* Enable interrupts */ + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_Generic_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxNok.value | + LRF_EventRxBufFull.value, + fifoCfg, genericHandlerState.common.activeUpdate)); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting Rx"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_RX; + } + } + } + else + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + if (rxCmd->config.discardRxPackets == 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(genericHandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != genericHandlerState.common.curBuffer) { + rclEvents.rxBufferFinished = 1; + genericHandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) { + /* Error */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_MultiBuffer_commitBytes(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + } + } + else + { + LRF_discardRxFifoWords(wordLength); + } + } + } + if (genericHandlerState.common.activeUpdate) + { + RCL_Handler_Generic_updateRxStats(rxCmd->stats, rclSchedulerState.actualStartTime); + } + else + { + RCL_Handler_Generic_updateLongStats(); + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + if (lrfEvents.opError != 0 && endStatus == RCL_CommandStatus_Finished) + { + endStatus = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE) == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + cmd->status = endStatus; + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(rxCmd->config.fsOff); + RCL_Handler_Generic_updateRxStats(rxCmd->stats, rclSchedulerState.actualStartTime); + /* Restore changed thresholds */ + if (genericHandlerState.rx.restoreThresh) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = genericHandlerState.rx.demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = genericHandlerState.rx.demc1be2; +#ifdef DeviceFamily_CC27XX + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE12) = genericHandlerState.rx.demc1be12; +#endif + } + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_PbeOperation ======== + */ +RCL_Events RCL_Handler_Generic_PbeOperation(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_Events rclEvents = {.value = 0}; + RCL_CmdGenericPbeOperation *pbeCmd = (RCL_CmdGenericPbeOperation *) cmd; + + if (cmd->status == RCL_CommandStatus_Scheduled) + { + /* Enable radio */ + LRF_enable(); + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setCmdStopTimeNoStartTrigger(cmd); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = pbeCmd->pbeOperation; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (lrfEvents.opDone != 0) + { + cmd->status = RCL_CommandStatus_Finished; + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + } + return rclEvents; +} + + +/* + * ======== RCL_Handler_Nesb_Ptx ======== + */ +RCL_Events RCL_Handler_Nesb_Ptx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdNesbPtx *txCmd = (RCL_CmdNesbPtx *) cmd; + RCL_Events rclEvents = {.value = 0}; + bool runTx = false; + bool listenAck = false; + uint32_t earliestStartTime = 0; + + if (rclEventsIn.setup != 0) + { + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if ((txCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(txCmd->syncWord); + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCB) = RCL_Handler_Generic_updateSyncWord(txCmd->syncWord); + + uint32_t opCfgVal = (PBE_GENERIC_RAM_OPCFG_NEXTOP_SWITCH) | + (PBE_GENERIC_RAM_OPCFG_TXFCMD_NONE) | + (PBE_GENERIC_RAM_OPCFG_FS_NOCAL_NOCAL) | + (PBE_GENERIC_RAM_OPCFG_FS_KEEPON_YES) | + (PBE_GENERIC_RAM_OPCFG_IFSPERIOD_EN) | + (PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_YES) | + (PBE_GENERIC_RAM_OPCFG_RXREPEATOK_YES) | + (PBE_GENERIC_RAM_OPCFG_RFINTERVAL_DIS) | + (PBE_GENERIC_RAM_OPCFG_SINGLE_DIS) | + (PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_YES); + + if (txCmd->config.fsOff != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + if (txCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + if (txCmd->config.autoRetransmitMode != 0) + { + opCfgVal |= (PBE_GENERIC_RAM_OPCFG_TXFCMD_RETRY); + } + else + { + opCfgVal |= (PBE_GENERIC_RAM_OPCFG_TXFCMD_DEALLOC); + } + + /* Enable NESB mode */ + uint32_t nesbVal = (PBE_GENERIC_RAM_NESB_NESBMODE_ON); + + uint32_t seqStat0Val = (txCmd->config.autoRetransmitMode << PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_S) + & PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_M; + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIRSTRXTIMEOUT) = 2500; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_RXTIMEOUT) = 800; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_MAXLEN) = 255; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = nesbVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_SEQSTAT0) = seqStat0Val; + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + genericHandlerState.tx.txCount = 0; + + /* Program frequency word */ + if (txCmd->rfFrequency != 0) + { + LRF_programFrequency(txCmd->rfFrequency, true); + } + if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enable radio */ + LRF_enable(); + + /* Initialize Tx FIFO */ + genericHandlerState.common.txFifoSize = LRF_prepareTxFifo(); + + /* Enter header and get ACK configuration */ + RCL_Handler_Nesb_updateHeader(&txCmd->txBuffers, + txCmd->config.autoRetransmitMode, + txCmd->config.hdrConf, + txCmd->seqNo); + + /* Configure Rx if necessary */ + if (txCmd->config.autoRetransmitMode != PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_ALWAYS) + { + /* Initialize Rx FIFO */ + genericHandlerState.common.rxFifoSize = LRF_prepareRxFifo(); + genericHandlerState.common.curBuffer = NULL; + + /* Request notification on RX buffer updates */ + RCL_Handler_Generic_updateRxCurBufferAndFifo(&txCmd->rxBuffers); + listenAck = true; + } + + /* Enter payload */ + uint32_t nBuffer = RCL_Handler_Generic_updateTxBuffers(&txCmd->txBuffers, 1); + if (nBuffer == 0) + { + cmd->status = RCL_CommandStatus_Error_MissingTxBuffer; + rclEvents.lastCmdDone = 1; + } + else + { + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + genericHandlerState.common.activeUpdate = RCL_Handler_Nesb_initStats(txCmd->stats, + rclSchedulerState.actualStartTime); + runTx = true; + } + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + /* We only get an Rx LRF event if an Acknowledge is expected */ + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t numWords = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / sizeof(uint32_t); + if (numWords > 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(genericHandlerState.common.curBuffer, + numWords * sizeof(uint32_t)); + + if (curBuffer != genericHandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + genericHandlerState.common.curBuffer = curBuffer; + } + + if (curBuffer == NULL) + { + /* Error */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *buffer32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(buffer32, numWords); + RCL_MultiBuffer_commitBytes(curBuffer, numWords * sizeof(uint32_t)); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_Generic_updateRxCurBufferAndFifo(&txCmd->rxBuffers); + } + } + } + if (genericHandlerState.common.activeUpdate) + { + RCL_Handler_Nesb_updateStats(txCmd->stats, rclSchedulerState.actualStartTime); + } + else + { + RCL_Handler_Nesb_updateLongStats(); + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + /* Retry TX FIFO. Writing to FCMD is safe because PBE is finished, ref. RCL-367 */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_FCMD) = LRFDPBE_FCMD_DATA_TXFIFO_RETRY; + + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + + if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ENDOK) + { + /* Increment the sequence number for next packet */ + txCmd->seqNo = (txCmd->seqNo + 1) % 4; + + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + + /* Pop transmitted packet */ + RCL_Buffer_TxBuffer *txBuffer; + txBuffer = RCL_TxBuffer_get(&txCmd->txBuffers); + if (txBuffer != NULL) + { + txBuffer->state = RCL_BufferStateFinished; + runTx = false; + } + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + /* Handle missed ACKs or ACKs with the wrong address */ + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_NOSYNC) + { + /* Reset PBE */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_INIT) = 1 << LRFDPBE_INIT_TOPSM_S; + + /* Attempt to retransmit the packet */ + if (genericHandlerState.tx.txCount <= txCmd->maxRetrans) + { + Log_printf(RclCore, Log_VERBOSE, "PTX needs to retransmit"); + + /* Set a new transmit time according to retransDelay. If unattainable, retransmit as soon as possible */ + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setNewStartRelTime(txCmd->retransDelay); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + Log_printf(RclCore, Log_VERBOSE, "Unattainable retranmission delay. Retransmitting as soon as possible"); + RCL_Scheduler_setNewStartNow(); + } + runTx = true; + } + else /* Finish the command without incrementing the sequence number */ + { + genericHandlerState.common.endStatus = RCL_CommandStatus_NoSync; + cmd->status = genericHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + runTx = false; + } + } + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + + if (endStatus == RCL_CommandStatus_Finished) + { + cmd->status = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + runTx = false; + } + else + { + /* Other events need to be handled unconditionally */ + } + if (runTx) + { + uint32_t txCount = genericHandlerState.tx.txCount; + txCount++; + if (txCount != 0) + { + /* Avoid wraparound */ + genericHandlerState.tx.txCount = txCount; + } + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Enable interrupts */ + if (listenAck) + { + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_Generic_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxNok.value | + LRF_EventRxIgnored.value | LRF_EventRxBufFull.value, + fifoCfg, genericHandlerState.common.activeUpdate)); + } + else + { + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + } + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Start of PTX operation"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_TX; + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(txCmd->config.fsOff); + RCL_Handler_Nesb_updateStats(txCmd->stats, rclSchedulerState.actualStartTime); + } + return rclEvents; +} + + +/* + * ======== RCL_Handler_Nesb_Prx ======== + */ +RCL_Events RCL_Handler_Nesb_Prx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdNesbPrx *rxCmd = (RCL_CmdNesbPrx *) cmd; + RCL_Events rclEvents = RCL_EventNone; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if ((rxCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = RCL_Handler_Generic_updateSyncWord(rxCmd->syncWordA); + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCB) = RCL_Handler_Generic_updateSyncWord(rxCmd->syncWordB); + + uint32_t opCfgVal = (PBE_GENERIC_RAM_OPCFG_NEXTOP_SWITCH) | + (PBE_GENERIC_RAM_OPCFG_TXFCMD_RETRY) | + (PBE_GENERIC_RAM_OPCFG_FS_NOCAL_NOCAL) | + (PBE_GENERIC_RAM_OPCFG_FS_KEEPON_YES) | + (PBE_GENERIC_RAM_OPCFG_IFSPERIOD_EN) | + (PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_NO) | + (PBE_GENERIC_RAM_OPCFG_RXREPEATOK_NO) | + (PBE_GENERIC_RAM_OPCFG_RFINTERVAL_DIS) | + (PBE_GENERIC_RAM_OPCFG_SINGLE_DIS) | + (PBE_GENERIC_RAM_OPCFG_RXINCLUDEHDR_YES); + + if (rxCmd->config.fsOff != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_KEEPON_M); + } + if (rxCmd->rfFrequency != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_FS_NOCAL_M); + } + if (rxCmd->config.repeatNok != 0) + { + opCfgVal |= PBE_GENERIC_RAM_OPCFG_RXREPEATNOK_M; + } + if (rxCmd->config.repeatOk != 0) + { + opCfgVal &= ~(PBE_GENERIC_RAM_OPCFG_RXREPEATOK_M); + } + + /* Enable NESB mode */ + uint32_t nesbVal = (PBE_GENERIC_RAM_NESB_NESBMODE_ON); + nesbVal |= (rxCmd->addrLen << PBE_GENERIC_RAM_NESB_PEERADRLEN_S) & PBE_GENERIC_RAM_NESB_PEERADRLEN_M; + + /* Configure AutoACK and Seq Status for syncword 0 */ + uint32_t seqStat0Val = (rxCmd->syncWord[0].seqValid << PBE_GENERIC_RAM_SEQSTAT0_VALID_S) + & PBE_GENERIC_RAM_SEQSTAT0_VALID_M; + + seqStat0Val |= (rxCmd->syncWord[0].autoAckMode << PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_S) + & PBE_GENERIC_RAM_SEQSTAT0_STOPAUTO_M; + + /* Configure AutoACK and Seq Status for syncword 1 */ + uint32_t seqStat1Val = (rxCmd->syncWord[1].seqValid << PBE_GENERIC_RAM_SEQSTAT1_VALID_S) + & PBE_GENERIC_RAM_SEQSTAT1_VALID_M; + + seqStat1Val |= (rxCmd->syncWord[1].autoAckMode << PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_S) + & PBE_GENERIC_RAM_SEQSTAT1_STOPAUTO_M; + + /* Set the addresses that will be used for address filtering */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PEERADR0AL) = (rxCmd->syncWord[0].address & PBE_GENERIC_RAM_PEERADR0AL_VAL_M); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PEERADR0AH) = (rxCmd->syncWord[0].address >> 0x10) & PBE_GENERIC_RAM_PEERADR0AH_VAL_M; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PEERADR0BL) = (rxCmd->syncWord[1].address & PBE_GENERIC_RAM_PEERADR0BL_VAL_M); + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PEERADR0BH) = (rxCmd->syncWord[1].address >> 0x10) & PBE_GENERIC_RAM_PEERADR0BH_VAL_M; + + /* Set timeouts for the Rx operation */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIRSTRXTIMEOUT) = 0; /* No timeout except from SYSTIM */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_RXTIMEOUT) = 0; /* No timeout except from SYSTIM */ + + /* Set remaining configuration registers */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_OPCFG) = opCfgVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NESB) = nesbVal; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_SEQSTAT0) = seqStat0Val; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_SEQSTAT1) = seqStat1Val; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_MAXLEN) = 255; + + /* If needed, configure demodulator correlator engine for syncwordA and syncwordB */ + if (rxCmd->config.disableSyncA != 0 || rxCmd->config.disableSyncB != 0) + { + uint16_t demc1be1 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1); + uint16_t demc1be2 = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2); + genericHandlerState.rx.restoreThresh = true; + genericHandlerState.rx.demc1be1 = demc1be1; + genericHandlerState.rx.demc1be2 = demc1be2; + if (rxCmd->config.disableSyncA != 0) + { + demc1be1 = (demc1be1 & ~LRFDMDM_DEMC1BE1_THRESHOLDA_M) | (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDA_S); + demc1be2 = (demc1be2 & ~LRFDMDM_DEMC1BE2_THRESHOLDC_M) | (0x7F << LRFDMDM_DEMC1BE2_THRESHOLDC_S); + } + if (rxCmd->config.disableSyncB != 0) + { + demc1be1 = (demc1be1 & ~LRFDMDM_DEMC1BE1_THRESHOLDB_M) | (0x7F << LRFDMDM_DEMC1BE1_THRESHOLDB_S); + } + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = demc1be2; + } + else + { + genericHandlerState.rx.restoreThresh = false; + } + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* Default end status */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Finished; + + /* Program frequency word */ + if (rxCmd->rfFrequency != 0) + { + LRF_programFrequency(rxCmd->rfFrequency, false); + } + if (LRF_programTxPower(rxCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + genericHandlerState.common.activeUpdate = RCL_Handler_Nesb_initStats(rxCmd->stats, + rclSchedulerState.actualStartTime); + + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize Rx FIFO */ + genericHandlerState.common.rxFifoSize = LRF_prepareRxFifo(); + genericHandlerState.common.curBuffer = NULL; + + if (rxCmd->config.discardRxPackets == 0) + { + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + } + else + { + /* Set FIFO size to maximum */ + LRF_setRxFifoEffSz(genericHandlerState.common.rxFifoSize); + } + + /* If an ACK is required, prepare Tx FIFOs */ + if ((rxCmd->syncWord[0].autoAckMode != 0) || (rxCmd->syncWord[1].autoAckMode != 0)) + { + genericHandlerState.common.txFifoSize = LRF_prepareTxFifo(); + } + + /* Enable interrupts */ + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_Generic_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxNok.value | + LRF_EventRxIgnored.value | LRF_EventRxBufFull.value, + fifoCfg, genericHandlerState.common.activeUpdate)); + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting of PRX operation"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_RX; + } + } + } + else + { + if (lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0 || lrfEvents.rxBufFull != 0) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + while (HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE) >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t numWords = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / sizeof(uint32_t); + if (numWords > 0) + { + if (rxCmd->config.discardRxPackets == 0) + { + RCL_MultiBuffer *curBuffer; + curBuffer = RCL_MultiBuffer_getBuffer(genericHandlerState.common.curBuffer, + numWords * 4); + if (curBuffer != genericHandlerState.common.curBuffer) + { + rclEvents.rxBufferFinished = 1; + genericHandlerState.common.curBuffer = curBuffer; + } + if (curBuffer == NULL) + { + /* Error */ + genericHandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_GENERIC_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else + { + uint32_t *buffer32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(buffer32, numWords); + RCL_MultiBuffer_commitBytes(curBuffer, numWords * sizeof(uint32_t)); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + + /* Update the sequence number to the one from to the last successfully received packet */ + rxCmd->syncWord[0].seq = (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_SEQSTAT0) & PBE_GENERIC_RAM_SEQSTAT0_PID_M) >> PBE_GENERIC_RAM_SEQSTAT0_PID_S; + rxCmd->syncWord[1].seq = (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_SEQSTAT1) & PBE_GENERIC_RAM_SEQSTAT1_PID_M) >> PBE_GENERIC_RAM_SEQSTAT1_PID_S; + + /* Update the CRC value to the one from the last successfully received packet */ + rxCmd->syncWord[0].crcVal = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_CRCVAL0); + rxCmd->syncWord[1].crcVal = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_CRCVAL1); + } + } + else + { + LRF_discardRxFifoWords(numWords); + } + } + } + if (genericHandlerState.common.activeUpdate) + { + RCL_Handler_Nesb_updateStats(rxCmd->stats, rclSchedulerState.actualStartTime); + } + else + { + RCL_Handler_Nesb_updateLongStats(); + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = genericHandlerState.common.endStatus; + + rclEvents.lastCmdDone = 1; + if (lrfEvents.opError != 0 && endStatus == RCL_CommandStatus_Finished) + { + endStatus = RCL_Handler_Generic_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE) == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + cmd->status = endStatus; + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + else + { + /* Other events need to be handled unconditionally */ + } + } + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_Handler_Generic_updateRxCurBufferAndFifo(&rxCmd->rxBuffers); + } + } + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + RCL_Handler_Generic_setSynthPowerState(rxCmd->config.fsOff); + RCL_Handler_Nesb_updateStats(rxCmd->stats, rclSchedulerState.actualStartTime); + /* Restore changed thresholds */ + if (genericHandlerState.rx.restoreThresh) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE1) = genericHandlerState.rx.demc1be1; + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMC1BE2) = genericHandlerState.rx.demc1be2; + } + } + + return rclEvents; +} + +/* + * ======== RCL_Handler_Generic_setSynthPowerState ======== + */ +static void RCL_Handler_Generic_setSynthPowerState(bool fsOff) +{ + /* Do power management for synth at the end of a command. + If synth is off, turn off refsys and remove constraint on standby. + If synth is on, keep refsys on and ensure constraint on standby is set */ + if (fsOff) + { + LRF_disableSynthRefsys(); + /* Release additional power constraints if necessary */ + if(genericHandlerState.common.powerConstraintsSet) + { + genericHandlerState.common.powerConstraintsSet = false; + hal_power_release_constraint(); + } + } + else + { + /* Set additional power constraints if necessary */ + if(!genericHandlerState.common.powerConstraintsSet) + { + genericHandlerState.common.powerConstraintsSet = true; + hal_power_set_constraint(); + } + } +} + +/* + * ======== RCL_Handler_Generic_updateRxCurBufferAndFifo ======== + */ +static void RCL_Handler_Generic_updateRxCurBufferAndFifo(List_List *rxBuffers) +{ + RCL_MultiBuffer *curBuffer = genericHandlerState.common.curBuffer; + + if (curBuffer == NULL) + { + curBuffer = RCL_MultiBuffer_findFirstWritableBuffer((RCL_MultiBuffer *)rxBuffers->head); + } + genericHandlerState.common.curBuffer = curBuffer; + + uint32_t rxSpace = RCL_MultiBuffer_findAvailableRxSpace(curBuffer); + + LRF_setRxFifoEffSz(rxSpace); +} + +/* + * ======== RCL_Handler_Generic_findPbeErrorEndStatus ======== + */ +static RCL_CommandStatus RCL_Handler_Generic_findPbeErrorEndStatus(uint16_t pbeEndStatus) +{ + RCL_CommandStatus status; + switch (pbeEndStatus) + { + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_RXF: + status = RCL_CommandStatus_Error_RxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_TXF: + status = RCL_CommandStatus_Error_TxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_SYNTH: + status = RCL_CommandStatus_Error_Synth; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_RXTIMEOUT: + status = RCL_CommandStatus_RxTimeout; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP: + status = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP: + status = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_BADOP: + status = RCL_CommandStatus_Error_UnknownOp; + break; + default: + Log_printf(RclCore, Log_ERROR, "Unexpected error 0x%04X from PBE", pbeEndStatus); + status = RCL_CommandStatus_Error; + break; + } + return status; +} + +/* + * ======== RCL_Handler_Generic_updateTxBuffers ======== + */ +static uint32_t RCL_Handler_Generic_updateTxBuffers(List_List *txBuffers, + uint32_t maxBuffers) +{ + uint32_t nBuffers = 0; + RCL_Buffer_TxBuffer *nextTxBuffer; + + nextTxBuffer = RCL_TxBuffer_head(txBuffers); + + while (nextTxBuffer != NULL && nBuffers < maxBuffers) + { + uint32_t length = nextTxBuffer->length; + /* Number of words including length field and end padding */ + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(length) / 4; + + if (wordLength > LRF_getTxFifoWritable() / 4) + { + /* Packet will not fit */ + /* TODO: See RCL-348 */ + break; + } + nextTxBuffer->state = RCL_BufferStateInUse; + uint32_t *data32 = (uint32_t *) &(nextTxBuffer->length); + + /* Copy packet into FIFO */ + LRF_writeTxFifoWords(data32, wordLength); + nextTxBuffer = RCL_TxBuffer_next(nextTxBuffer); + + nBuffers++; + } + + return nBuffers; +} + +/* + * ======== RCL_Handler_Generic_maskEventsByFifoConf ======== + */ +static uint32_t RCL_Handler_Generic_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate) +{ + /* Remove events that will not give an entry in the RX FIFO, based on FIFOCFG, unless active update is used + Note: never remove the CRC error event, as it is needed to update the long CRC error counter */ + if (!activeUpdate) + { + mask &= ~(((fifoConfVal & PBE_GENERIC_RAM_FIFOCFG_AUTOFLUSHIGN_M) ? LRF_EventRxIgnored.value : 0) | + LRF_EventRxBufFull.value); + } + return mask; +} + +/* + * ======== RCL_Handler_Generic_updateRxStats ======== + */ +static void RCL_Handler_Generic_updateRxStats(RCL_StatsGeneric *stats, uint32_t startTime) +{ + if (stats != NULL) + { + uint32_t lastTimestamp = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTTIMESTAMPL); + /* Check if a new value is found in the first timestamp */ + if (lastTimestamp == startTime) + { + stats->timestampValid = false; + } + else { + stats->timestampValid = true; + stats->lastTimestamp = lastTimestamp; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTRSSI); + RCL_Handler_Generic_updateLongStats(); + stats->nRxNok = genericHandlerState.rx.longNokCount; + stats->nRxOk = genericHandlerState.rx.longOkCount; + } +} + +/* + * ======== RCL_Handler_Generic_updateLongStats ======== + */ +static void RCL_Handler_Generic_updateLongStats(void) +{ + uint32_t oldRxOk = genericHandlerState.rx.longOkCount; + uint32_t oldRxNok = genericHandlerState.rx.longNokCount; + uint32_t newRxOk = (oldRxOk & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK); + uint32_t newRxNok = (oldRxNok & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK); + + if (newRxOk < oldRxOk) + { + newRxOk += 0x10000; + } + if (newRxNok < oldRxNok) + { + newRxNok += 0x10000; + } + genericHandlerState.rx.longOkCount = newRxOk; + genericHandlerState.rx.longNokCount = newRxNok; +} + +/* + * ======== RCL_Handler_Generic_initRxStats ======== + */ +static bool RCL_Handler_Generic_initRxStats(RCL_StatsGeneric *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTTIMESTAMPL) = startTime; + stats->timestampValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + genericHandlerState.rx.longNokCount = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = stats->nRxNok & 0xFFFF; + genericHandlerState.rx.longOkCount = stats->nRxOk; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = stats->nRxOk & 0xFFFF; + } + else + { + /* Reset existing values in PBE */ + genericHandlerState.rx.longNokCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = 0; + genericHandlerState.rx.longOkCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = 0; + + stats->nRxNok = 0; + stats->nRxOk = 0; + } + return stats->config.activeUpdate; + } + else + { + /* Reset existing values in PBE */ + genericHandlerState.rx.longNokCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = 0; + genericHandlerState.rx.longOkCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = 0; + + return false; + } +} + +/* + * ======== RCL_Handler_Generic_updateSyncWord ======== + */ +static uint32_t RCL_Handler_Generic_updateSyncWord(uint32_t syncWord) +{ + uint32_t syncWordOut; + /* Check bit ordering of header and follow that */ + if ((HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_PKTCFG) & PBE_GENERIC_RAM_PKTCFG_HDRORDER_M) != 0) + { + /* MSb first configured - bit reverse sync word */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_PHAOUT0) = syncWord & 0x0000FFFF; + syncWordOut = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_PHAOUT0BR) << 16; + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_PHAOUT0) = syncWord >> 16; + syncWordOut |= HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_PHAOUT0BR); + /* Check sync word length to see ensure that sync word ends up in least significant bits */ + uint32_t syncWordLen = (HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_DEMSWQU0) & LRFDMDM_DEMSWQU0_REFLEN_M) + 1; + syncWordOut >>= (32 - syncWordLen); + } + else + { + syncWordOut = syncWord; + } + + return syncWordOut; +} + +/* + * ======== RCL_Handler_Nesb_updateHeader ======== + */ +static void RCL_Handler_Nesb_updateHeader(List_List *txBuffers, uint8_t autoRetransmitMode, + uint8_t hdrConf, uint8_t seqNumber) +{ + uint8_t noAck; + uint8_t seqNo; + + RCL_Buffer_TxBuffer *nextTxBuffer; + nextTxBuffer = RCL_TxBuffer_head(txBuffers); + uint8_t indexHeader = nextTxBuffer->numPad - 1; + + if (hdrConf == 0) + { + /* Insert NO_ACK field from TX buffer. */ + noAck = nextTxBuffer->data[indexHeader] & 0x01; + seqNo = seqNumber; + } + else + { + /* Insert SEQ and NO_ACK field from TX buffer. */ + noAck = nextTxBuffer->data[indexHeader] & 0x01; + seqNo = (nextTxBuffer->data[indexHeader] >> 1) & 0x03; + } + + /* Update header */ + nextTxBuffer->data[indexHeader] = ((nextTxBuffer->data[indexHeader] & 0xF8) | ((seqNo & 0x03) << 1) | noAck); +} + +/* + * ======== RCL_Handler_Nesb_updateStats ======== + */ +static void RCL_Handler_Nesb_updateStats(RCL_StatsNesb *stats, uint32_t startTime) +{ + if (stats != NULL) + { + uint32_t lastTimestamp = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTTIMESTAMPL); + /* Check if a new value is found in the first timestamp */ + if (lastTimestamp == startTime) + { + stats->timestampValid = false; + } + else { + stats->timestampValid = true; + stats->lastTimestamp = lastTimestamp; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTRSSI); + RCL_Handler_Nesb_updateLongStats(); + stats->nTx = genericHandlerState.nesb.longTxCount; + stats->nRxOk = genericHandlerState.nesb.longOkCount; + stats->nRxNok = genericHandlerState.nesb.longNokCount; + stats->nRxIgnored = genericHandlerState.nesb.longRxIgnoredCount; + stats->nRxAddrMismatch = genericHandlerState.nesb.longRxAddrMismatchCount; + stats->nRxBufFull = genericHandlerState.nesb.longRxBufFullCount; + } +} + +/* + * ======== RCL_Handler_Nesb_updateLongStats ======== + */ +static void RCL_Handler_Nesb_updateLongStats(void) +{ + uint32_t oldTx = genericHandlerState.nesb.longTxCount; + uint32_t oldRxOk = genericHandlerState.nesb.longOkCount; + uint32_t oldRxNok = genericHandlerState.nesb.longNokCount; + /* TODO: RCL-308: Long counters should not be needed for anything except RX Ok and CRC error */ + uint32_t oldRxIgnored = genericHandlerState.nesb.longRxIgnoredCount; + uint32_t oldRxAddrMismatch = genericHandlerState.nesb.longRxAddrMismatchCount; + uint32_t oldRxBufFull = genericHandlerState.nesb.longRxBufFullCount; + + uint32_t newTx = (oldTx & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NTX); + uint32_t newRxOk = (oldRxOk & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK); + uint32_t newRxNok = (oldRxNok & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK); + uint32_t newRxIgnored = (oldRxIgnored & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED); + /* TODO: See RCL-343 */ + uint32_t newRxAddrMismatch = (oldRxAddrMismatch & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED); + uint32_t newRxBufFull = (oldRxBufFull & ~0xFFFF) | HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXFIFOFULL); + + if (newTx < oldTx) + { + newTx += 0x10000; + } + if (newRxOk < oldRxOk) + { + newRxOk += 0x10000; + } + if (newRxNok < oldRxNok) + { + newRxNok += 0x10000; + } + if (newRxIgnored < oldRxIgnored) + { + newRxIgnored += 0x10000; + } + if (newRxAddrMismatch < oldRxAddrMismatch) + { + newRxAddrMismatch += 0x10000; + } + if (newRxBufFull < oldRxBufFull) + { + newRxBufFull += 0x10000; + } + genericHandlerState.nesb.longTxCount = newTx; + genericHandlerState.nesb.longOkCount = newRxOk; + genericHandlerState.nesb.longNokCount = newRxNok; + genericHandlerState.nesb.longRxIgnoredCount = newRxIgnored; + genericHandlerState.nesb.longRxAddrMismatchCount = newRxAddrMismatch; + genericHandlerState.nesb.longRxBufFullCount = newRxBufFull; +} + +/* + * ======== RCL_Handler_Nesb_initStats ======== + */ +static bool RCL_Handler_Nesb_initStats(RCL_StatsNesb *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_LASTTIMESTAMPL) = startTime; + stats->timestampValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + genericHandlerState.nesb.longTxCount = stats->nTx; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NTX) = stats->nRxOk & 0xFFFF; + genericHandlerState.nesb.longOkCount = stats->nRxOk; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = stats->nRxOk & 0xFFFF; + genericHandlerState.nesb.longNokCount = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = stats->nRxNok & 0xFFFF; + genericHandlerState.nesb.longRxIgnoredCount = stats->nRxIgnored; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = stats->nRxIgnored & 0xFFFF; + genericHandlerState.nesb.longRxAddrMismatchCount = stats->nRxAddrMismatch; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = stats->nRxAddrMismatch & 0xFFFF; + genericHandlerState.nesb.longRxBufFullCount = stats->nRxBufFull; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXFIFOFULL) = stats->nRxBufFull & 0xFFFF; + } + else + { + /* Reset existing values in PBE */ + genericHandlerState.nesb.longTxCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NTX) = 0; + genericHandlerState.nesb.longOkCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = 0; + genericHandlerState.nesb.longNokCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = 0; + genericHandlerState.nesb.longRxIgnoredCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = 0; + genericHandlerState.nesb.longRxAddrMismatchCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = 0; + genericHandlerState.nesb.longRxBufFullCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXFIFOFULL) = 0; + + stats->nTx = 0; + stats->nRxOk = 0; + stats->nRxNok = 0; + stats->nRxIgnored = 0; + stats->nRxAddrMismatch = 0; + stats->nRxBufFull = 0; + } + return stats->config.activeUpdate; + } + else + { + /* Reset existing values in PBE */ + genericHandlerState.nesb.longTxCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NTX) = 0; + genericHandlerState.nesb.longOkCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXOK) = 0; + genericHandlerState.nesb.longNokCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXNOK) = 0; + genericHandlerState.nesb.longRxIgnoredCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = 0; + genericHandlerState.nesb.longRxAddrMismatchCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXIGNORED) = 0; + genericHandlerState.nesb.longRxBufFullCount = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_GENERIC_RAM_O_NRXFIFOFULL) = 0; + + return false; + } +} diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.h b/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.h new file mode 100644 index 00000000..3ef3f52a --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/generic.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_handlers_generic_h__include +#define ti_drivers_RCL_handlers_generic_h__include + +#include +#include +#include + +RCL_Events RCL_Handler_Generic_Fs(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_FsOff(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_Tx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_TxRepeat(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_TxTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_Rx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Generic_PbeOperation(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Nesb_Ptx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Nesb_Prx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); + +#endif // ti_drivers_RCL_handlers_ble5_h__include diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.c b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.c new file mode 100644 index 00000000..2e6b934b --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.c @@ -0,0 +1,1768 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ieee.c ======== + */ + +#ifndef DeviceFamily_CC27XX + +#include +#include + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_lrfdtxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrxf.h) +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe.h) +#include DeviceFamily_constructPath(inc/hw_lrfdpbe32.h) +#include DeviceFamily_constructPath(inc/hw_lrfdmdm.h) +#include DeviceFamily_constructPath(inc/hw_lrfdrfe.h) +#include DeviceFamily_constructPath(inc/pbe_ieee_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) +#include DeviceFamily_constructPath(inc/pbe_ieee_regdef_regs.h) + +/** Polynomial to use for PRBS9 data */ +#define RCL_HANDLER_IEEE_PRBS9_POLY 0x08800000 +/** Polynomial to use for PRBS15 data */ +#define RCL_HANDLER_IEEE_PRBS15_POLY 0x80020000 +/** Polynomial to use for PRBS32 data */ +#define RCL_HANDLER_IEEE_PRBS32_POLY 0x00400007 +#define RCL_HANDLER_IEEE_PRBS_INIT 0x0000001F + +#define RCL_HANDLER_IEEE_RESTORE_NONE 0x0000 +#define RCL_HANDLER_IEEE_RESTORE_MODCTRL 0x0001 +#define RCL_HANDLER_IEEE_RESTORE_WHITENING 0x0002 +#define RCL_HANDLER_IEEE_RESTORE_SFD 0x0004 + +/* Byte length of IEEE 802.15.4 frame fields */ +#define IEEE_PHY_HDR_LEN 1 +#define IEEE_MAC_FCF_LEN 2 + +/* Timing constants */ +/* Backoff period for the O-QPSK PHY per the 802.15.4 standard */ +#define IEEE_BACKOFF_PERIOD RCL_SCHEDULER_SYSTIM_US(320) +/* Necessary margin to start CCA */ +#define IEEE_CCA_START_TIME_MARGIN RCL_SCHEDULER_SYSTIM_US(192) + +typedef enum +{ + txStateNoTx, + txStateNewAction, + txStateSetupCca, + txStateWaitForCca, + txStateStopToSetTx, + txStateSetTxTime, + txStateWaitForTx, + txStateTx, + txStateTxRx, + txStateTxRxAck, + txStateCheckAck, + txStateWaitForCmdEnd, + txStateFinished, +} RCL_Handler_Ieee_TxState; + +typedef enum +{ + rxStateNoRx, + rxStateWaitForStart, + rxStateRunning +} RCL_Handler_Ieee_RxState; + +typedef enum +{ + noEvent, + customEvent, + customHardStop, +} RCL_Handler_Ieee_EventType; + +struct +{ + struct { + uint16_t txFifoSize; + uint16_t rxFifoSize; + RCL_CommandStatus endStatus; + bool activeUpdate; + bool apiHardStopPending; + RCL_MultiBuffer *curBuffer; + uint32_t nextEventTime; + RCL_Handler_Ieee_EventType eventTimeType; + } common; + union { + struct { + uint16_t restoreOpt; + uint16_t storedWhitenInit; + uint32_t storedWhitenPoly; + uint32_t storedMdmSyncA; + } txTest; + struct { + RCL_Handler_Ieee_TxState txState; + RCL_Handler_Ieee_RxState rxState; + uint8_t ccaContentionWindow; + bool waitingForValidRssi; + bool allowTxDelay; + bool alwaysStoreAck; + uint8_t expSeqNo; + uint32_t ccaTxStartTime; + RCL_StopType txActionStop; + } rxTx; + }; +} ieeeHandlerState; + +static void RCL_Handler_Ieee_updateRxCurBufferAndFifo(List_List *rxBuffers); +static RCL_CommandStatus RCL_Handler_Ieee_findPbeErrorEndStatus(uint16_t pbeEndStatus); +static uint32_t RCL_Handler_Ieee_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate); +static void RCL_Handler_Ieee_updateStats(RCL_StatsIeee *stats, uint32_t startTime); +static bool RCL_Handler_Ieee_initStats(RCL_StatsIeee *stats, uint32_t startTime); +static bool RCL_Handler_Ieee_setCustomEventTime(uint32_t eventTime, uint32_t timeMargin, bool hardStop); +static bool RCL_Handler_Ieee_restoreStopTime(void); + +/* + * ======== RCL_Handler_Ieee_RxTx ======== + */ +RCL_Events RCL_Handler_Ieee_RxTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdIeeeRxTx *ieeeCmd = (RCL_CmdIeeeRxTx *) cmd; + RCL_Events rclEvents = {.value = 0}; + bool startTx = false; + bool doCca = false; + bool restartRx = false; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + ieeeHandlerState.rxTx.rxState = rxStateNoRx; + ieeeHandlerState.rxTx.txState = txStateNoTx; + ieeeHandlerState.common.eventTimeType = noEvent; + ieeeHandlerState.common.apiHardStopPending = false; + ieeeHandlerState.rxTx.txActionStop = RCL_StopType_None; + + RCL_CmdIeee_RxAction *rxAction = ieeeCmd->rxAction; + RCL_CmdIeee_TxAction *txAction = ieeeCmd->txAction; + + RCL_CmdIeee_CcaMode ccaMode = RCL_CmdIeee_NoCca; + if (txAction != NULL) + { + ccaMode = txAction->ccaMode; + } + + if (rxAction == NULL) + { + if (txAction == NULL) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + return rclEvents; + } + else + { + /* Go straight to TX */ + /* CSMA or RX ACK not possible with pure TX */ + if (ccaMode != RCL_CmdIeee_NoCca || + txAction->expectImmAck != 0 || + txAction->expectEnhAck != 0) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + return rclEvents; + } + } + } + else + { + if (rxAction->numPan > RCL_CMD_IEEE_MAX_NUM_PAN) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + return rclEvents; + } + else if (rxAction->numPan == 0 && txAction != NULL && + (txAction->expectImmAck != 0 || txAction->expectEnhAck != 0)) + { + /* RX ACK not supported with promiscuous mode */ + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + return rclEvents; + } + } + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + + if (txAction != NULL) + { + uint32_t cmdTime = (cmd->scheduling == RCL_Schedule_AbsTime) ? cmd->timing.absStartTime : RCL_Scheduler_getCurrentTime(); + uint32_t txActionTime = (txAction->ccaScheduling == RCL_Schedule_AbsTime) ? txAction->absCcaStartTime : cmdTime; + /* Check that TX action start time is not before the command start time */ + if (!txAction->allowDelay && !RCL_Scheduler_isLater(cmdTime, txActionTime)) + { + txAction->txStatus = RCL_CommandStatus_Error_StartTooLate; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + if (ccaMode == RCL_CmdIeee_NoCca) + { + /* Check if the command should go directly to TX */ + uint32_t txTime = txActionTime + txAction->relativeTxStartTime; + ieeeHandlerState.rxTx.ccaTxStartTime = txTime; + ieeeHandlerState.rxTx.allowTxDelay = txAction->allowDelay || txAction->allowTxDelay; + if (rxAction == NULL || RCL_Scheduler_delta(cmdTime, txTime) < (2 * IEEE_CCA_START_TIME_MARGIN)) + { + /* TX starts after a short time; don't do RX first */ + startTx = true; + } + else + { + /* Set receiver to stop in time for TX */ + ieeeHandlerState.rxTx.txState = txStateStopToSetTx; + } + } + else + { + /* Schedule CCA evaluation */ + txAction->txStatus = RCL_CommandStatus_Scheduled; + ieeeHandlerState.rxTx.txState = txStateSetupCca; + } + } + } + + if (rclEvents.lastCmdDone == 0) + { + /* Program frequency word */ + LRF_programFrequency(ieeeCmd->rfFrequency, startTx); + + if (LRF_programTxPower(ieeeCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + } + + if (rclEvents.lastCmdDone == 0) + { + /* Enable radio */ + LRF_enable(); + + ieeeHandlerState.common.activeUpdate = RCL_Handler_Ieee_initStats(ieeeCmd->stats, + rclSchedulerState.actualStartTime); + + RCL_CommandStatus startTimeStatus; + if (startTx) + { + RCL_CommandTiming timing = cmd->timing; + timing.absStartTime = ieeeHandlerState.rxTx.ccaTxStartTime; + startTimeStatus = RCL_Scheduler_setCustomStartStopTimeEarliestStart(&timing, RCL_Schedule_AbsTime, + ieeeHandlerState.rxTx.allowTxDelay, earliestStartTime); + ieeeHandlerState.rxTx.txState = txStateWaitForTx; + } + else + { + startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + } + + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + } + + if (rclEvents.lastCmdDone == 0 && rxAction != NULL) + { + /* Prepare receiver */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXTIMEOUT) = 0; /* No timeout except from SYSTIM */ + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_PIB) = rxAction->numPan; + + uint32_t panRegOffset = 0; + uint32_t sourceMatchHeaderOffset = 0; + uint32_t sourceMatchTableOffset = 0; + for (int i = 0; i < rxAction->numPan; i++) + { + RCL_CmdIeee_PanConfig *panConfig = &rxAction->panConfig[i]; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + panRegOffset + PBE_IEEE_RAM_O_PANID0) = panConfig->localPanId; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + panRegOffset + PBE_IEEE_RAM_O_SHORTADDR0) = panConfig->localShortAddr; + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + panRegOffset + PBE_IEEE_RAM_O_EXTADDR00) = (uint32_t) panConfig->localExtAddr; + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + panRegOffset + PBE_IEEE_RAM_O_EXTADDR02) = (uint32_t) (panConfig->localExtAddr >> 32); + uint32_t frameFilteringOption = + (panConfig->maxFrameVersion << PBE_IEEE_RAM_FFOPT0_MAXFRAME_S) | + (panConfig->panCoord << PBE_IEEE_RAM_FFOPT0_PANCOORD_S) | + (panConfig->defaultPend << PBE_IEEE_RAM_FFOPT0_DEFPEND_S); + + switch (panConfig->autoAckMode) + { + case RCL_CmdIeee_AutoAck_Off: + default: + frameFilteringOption |= PBE_IEEE_RAM_FFOPT0_AUTOACK_DISABLE | + PBE_IEEE_RAM_FFOPT0_AUTOPEND_DISABLE | + PBE_IEEE_RAM_FFOPT0_PREQONLY_ANY; + break; + + case RCL_CmdIeee_AutoAck_ImmAckNoAutoPend: + frameFilteringOption |= PBE_IEEE_RAM_FFOPT0_AUTOACK_EN | + PBE_IEEE_RAM_FFOPT0_AUTOPEND_DISABLE | + PBE_IEEE_RAM_FFOPT0_PREQONLY_ANY; + break; + + case RCL_CmdIeee_AutoAck_ImmAckAutoPendAll: + frameFilteringOption |= PBE_IEEE_RAM_FFOPT0_AUTOACK_EN | + PBE_IEEE_RAM_FFOPT0_AUTOPEND_EN | + PBE_IEEE_RAM_FFOPT0_PREQONLY_ANY; + break; + + case RCL_CmdIeee_AutoAck_ImmAckAutoPendDataReq: + frameFilteringOption |= PBE_IEEE_RAM_FFOPT0_AUTOACK_EN | + PBE_IEEE_RAM_FFOPT0_AUTOPEND_EN | + PBE_IEEE_RAM_FFOPT0_PREQONLY_DATAREQ; + break; + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + panRegOffset + PBE_IEEE_RAM_O_FFOPT0) = frameFilteringOption; + + /* Set up source matching */ + if (panConfig->sourceMatchingTableExt != NULL) + { + /* Extended source matching: Not yet supported */ + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + break; + } + if (panConfig->sourceMatchingTableShort != NULL) + { + RCL_CmdIeee_SourceMatchingTableShort *sourceMatchingTable = panConfig->sourceMatchingTableShort; + uint32_t numEntries = sourceMatchingTable->numEntries; + if (numEntries > RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_MAX_LEN) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + break; + } + uint32_t entryNo = 0; + uint32_t index = 0; + while (entryNo < numEntries) + { + uint16_t mask = 0xFFFF; + if ((numEntries - entryNo) < 16) + { + mask >>= (16 - (numEntries - entryNo)); + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + sourceMatchHeaderOffset + PBE_IEEE_RAM_O_ENTRYENABLE00 + (index << 1)) = + sourceMatchingTable->entryEnable[index] & mask; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + sourceMatchHeaderOffset + PBE_IEEE_RAM_O_FRAMEPENDING00 + (index << 1)) = + sourceMatchingTable->framePending[index] & mask; + index++; + entryNo += 16; + } + while (index < RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_NUM_WORDS) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_ENTRYENABLE00 + (index << 1)) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_FRAMEPENDING00 + (index << 1)) = 0; + index++; + } + for (entryNo = 0; entryNo < numEntries; entryNo++) + { + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + sourceMatchTableOffset + PBE_IEEE_RAM_O_PAN0_SRC_MATCH_SHORT_START + (entryNo << 2)) = + sourceMatchingTable->shortEntry[entryNo].combined; + } + } + else + { + for (int i = 0; i < RCL_CMD_IEEE_SOURCE_MATCH_TABLE_SHORT_NUM_WORDS; i++) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + sourceMatchHeaderOffset + PBE_IEEE_RAM_O_ENTRYENABLE00 + (i << 1)) = 0; + } + } + + panRegOffset += PBE_IEEE_RAM_O_PANID1 - PBE_IEEE_RAM_O_PANID0; + sourceMatchHeaderOffset += PBE_IEEE_RAM_O_ENTRYENABLE10 - PBE_IEEE_RAM_O_ENTRYENABLE00; + sourceMatchTableOffset += PBE_IEEE_RAM_O_PAN1_SRC_MATCH_SHORT_START - PBE_IEEE_RAM_O_PAN0_SRC_MATCH_SHORT_START; + } + uint16_t ffType = + PBE_IEEE_RAM_FFTYPE_MACCMD1_M | + PBE_IEEE_RAM_FFTYPE_DATA1_M | + PBE_IEEE_RAM_FFTYPE_BEACON1_M | + PBE_IEEE_RAM_FFTYPE_MACCMD0_M | + PBE_IEEE_RAM_FFTYPE_DATA0_M | + PBE_IEEE_RAM_FFTYPE_BEACON0_M; + ieeeHandlerState.rxTx.alwaysStoreAck = rxAction->alwaysStoreAck; + if (ieeeHandlerState.rxTx.alwaysStoreAck) + { + ffType |= PBE_IEEE_RAM_FFTYPE_ACK1_M | PBE_IEEE_RAM_FFTYPE_ACK0_M; + } + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_FFTYPE) = ffType; + } + + if (rclEvents.lastCmdDone == 0) + { + if (rxAction != NULL) + { + /* Start receiver */ + /* Set up sync found capture */ + hal_setup_sync_found_cap(); + /* Initialize RF FIFOs */ + ieeeHandlerState.common.rxFifoSize = LRF_prepareRxFifo(); + ieeeHandlerState.common.curBuffer = NULL; + RCL_Handler_Ieee_updateRxCurBufferAndFifo(&rxAction->rxBuffers); + + /* Enable interrupts */ + uint16_t fifoCfg = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_FIFOCFG); + LRF_enableHwInterrupt(RCL_Handler_Ieee_maskEventsByFifoConf(LRF_EventOpDone.value | LRF_EventOpError.value | + LRF_EventRxOk.value | LRF_EventRxNok.value | + LRF_EventRxIgnored.value | LRF_EventRxBufFull.value | + (ieeeHandlerState.common.activeUpdate ? LRF_EventTxAck.value : 0), + fifoCfg, ieeeHandlerState.common.activeUpdate)); + if (!startTx) + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + PBE_IEEE_RAM_OPCFG_STOP_SOFTEND | + PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES | + PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES | + PBE_IEEE_RAM_OPCFG_TXINFINITE_NO | + PBE_IEEE_RAM_OPCFG_TXPATTERN_NO | + PBE_IEEE_RAM_OPCFG_TXFCMD_NONE | + PBE_IEEE_RAM_OPCFG_START_SYNC | + PBE_IEEE_RAM_OPCFG_SINGLE_DIS | + PBE_IEEE_RAM_OPCFG_IFSPERIOD_EN; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXTIMEOUT) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_CFGAUTOACK) = + PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_NOFILT | PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_DIS; + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting IEEE RX"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_IEEE_REGDEF_API_OP_RX; + /* Clear RSSI valid interrupt flag */ + LRF_clearHwInterrupt(LRF_EventRfesoft0.value); + ieeeHandlerState.rxTx.rxState = rxStateWaitForStart; + } + } + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + + /* End status not determined */ + ieeeHandlerState.common.endStatus = RCL_CommandStatus_Active; + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.stopTimesUpdated) + { + if (ieeeHandlerState.common.eventTimeType != noEvent) + { + bool hardStop = (ieeeHandlerState.common.eventTimeType == customHardStop); + /* Event has been turned off by stop time modification */ + ieeeHandlerState.common.eventTimeType = noEvent; + /* Turn back on if possible */ + RCL_Handler_Ieee_setCustomEventTime(ieeeHandlerState.common.nextEventTime, IEEE_CCA_START_TIME_MARGIN, hardStop); + } + } + if (rclEventsIn.handlerCmdUpdate) + { + RCL_CmdIeee_TxAction *txAction = ieeeCmd->txAction; + RCL_StopType txActionStop = ieeeHandlerState.rxTx.txActionStop; + if (txActionStop != RCL_StopType_None && txAction != NULL) + { + if (txAction->txStatus < RCL_CommandStatus_Active) + { + Log_printf(RclCore, Log_VERBOSE, "Descheduling pending TX action"); + /* TX action can be descheduled */ + txAction->txStatus = RCL_CommandStatus_DescheduledApi; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else if (ieeeHandlerState.rxTx.txState <= txStateWaitForTx) + { + /* Waiting for CCA or TX to start; hard or graceful stop possible */ + if (txActionStop == RCL_StopType_Graceful || txActionStop == RCL_StopType_Hard) + { + RCL_Handler_Ieee_restoreStopTime(); + Log_printf(RclCore, Log_VERBOSE, "Stopping pending CCA or TX"); + txAction->txStatus = (txActionStop == RCL_StopType_Graceful) ? RCL_CommandStatus_GracefulStopApi : RCL_CommandStatus_HardStopApi; + ieeeHandlerState.rxTx.txState = txStateFinished; + startTx = false; + } + } + else if ((ieeeHandlerState.rxTx.txState == txStateTx || + ieeeHandlerState.rxTx.txState == txStateTxRx || + ieeeHandlerState.rxTx.txState == txStateTxRxAck) && + (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXSTATUS) & PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS) != 0) + { + if (txActionStop == RCL_StopType_Hard) + { + Log_printf(RclCore, Log_VERBOSE, "Stopping TX due to hard stop"); + /* Send hard stop to PBE */ + LRF_sendHardStop(); + /* TX action will end when PBE is finished */ + ieeeHandlerState.common.apiHardStopPending = true; + } + } + else if (ieeeHandlerState.rxTx.txState == txStateTxRxAck) + { + if (txActionStop == RCL_StopType_Hard) + { + /* Hard stop - give up on TX action, but keep receiver alive */ + txAction->txStatus = RCL_CommandStatus_HardStopApi; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + else + { + /* No action needed, TX action should end very soon */ + } + /* Clear stop action */ + ieeeHandlerState.rxTx.txActionStop = RCL_StopType_None; + } + else if (ieeeHandlerState.rxTx.txState == txStateNewAction && txAction != NULL) + { + uint32_t currentTime = RCL_Scheduler_getCurrentTime(); + uint32_t txActionTime = (txAction->ccaScheduling == RCL_Schedule_AbsTime) ? txAction->absCcaStartTime : currentTime; + /* Check that TX action start time is not in the past */ + if (txAction->ccaScheduling == RCL_Schedule_AbsTime && !txAction->allowDelay && + !RCL_Scheduler_isLater(currentTime, txActionTime)) + { + txAction->txStatus = RCL_CommandStatus_Error_StartTooLate; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else if (ieeeCmd->rxAction->numPan == 0 && + (txAction->expectImmAck != 0 || txAction->expectEnhAck != 0)) + { + txAction->txStatus = RCL_CommandStatus_Error_Param; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + txAction->txStatus = RCL_CommandStatus_Scheduled; + if (txAction->ccaMode == RCL_CmdIeee_NoCca) + { + /* Check if the command should go directly to TX */ + uint32_t txTime = txActionTime + txAction->relativeTxStartTime; + ieeeHandlerState.rxTx.ccaTxStartTime = txTime; + ieeeHandlerState.rxTx.allowTxDelay = txAction->allowDelay || txAction->allowTxDelay; + + if (RCL_Scheduler_delta(currentTime, txTime) < IEEE_CCA_START_TIME_MARGIN) + { + /* TX starts after a short time; stop RX now */ + ieeeHandlerState.rxTx.txState = txStateSetTxTime; + /* Stop running RX */ + LRF_sendHardStop(); + } + else + { + /* Set receiver to stop in time for TX */ + ieeeHandlerState.rxTx.txState = txStateStopToSetTx; + } + } + else + { + /* Schedule CCA evaluation */ + ieeeHandlerState.rxTx.txState = txStateSetupCca; + } + } + } + } + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + if (ieeeHandlerState.rxTx.rxState == rxStateWaitForStart) + { + ieeeHandlerState.rxTx.rxState = rxStateRunning; + } + } + if (rclEventsIn.rxBufferUpdate != 0) + { + RCL_CmdIeee_RxAction *rxAction = ieeeCmd->rxAction; + if (rxAction != NULL) + { + RCL_Handler_Ieee_updateRxCurBufferAndFifo(&rxAction->rxBuffers); + } + } + + if (ieeeHandlerState.rxTx.txState == txStateStopToSetTx && ieeeHandlerState.rxTx.rxState == rxStateRunning) + { + /* Set receiver to stop in time for TX */ + bool timeSet = RCL_Handler_Ieee_setCustomEventTime(ieeeHandlerState.rxTx.ccaTxStartTime - IEEE_CCA_START_TIME_MARGIN, IEEE_CCA_START_TIME_MARGIN, true); + if (timeSet) + { + ieeeHandlerState.rxTx.txState = txStateSetTxTime; + } + else + { + /* Command will end soon - park TX action until then */ + ieeeHandlerState.rxTx.txState = txStateWaitForCmdEnd; + } + } + + if (ieeeHandlerState.rxTx.txState == txStateSetupCca && ieeeHandlerState.rxTx.rxState == rxStateRunning) + { + RCL_CmdIeee_TxAction *txAction = ieeeCmd->txAction; + uint32_t ccaTime = txAction->absCcaStartTime; + RCL_ScheduleType ccaScheduling = txAction->ccaScheduling; + bool allowDelay = (ccaScheduling == RCL_Schedule_Now) ? true : txAction->allowDelay; + + uint32_t currentTime = RCL_Scheduler_getCurrentTime(); + ieeeHandlerState.rxTx.waitingForValidRssi = false; + + uint8_t ccaContentionWindow = txAction->ccaContentionWindow; + if (ccaContentionWindow < 1) + { + ccaContentionWindow = 1; + } + ieeeHandlerState.rxTx.ccaContentionWindow = ccaContentionWindow; + uint32_t ccaDuration = (ccaContentionWindow - 1) * IEEE_BACKOFF_PERIOD; + if (ccaScheduling == RCL_Schedule_AbsTime && + RCL_Scheduler_isLater(currentTime + IEEE_CCA_START_TIME_MARGIN, ccaTime)) + { + bool timeSet = RCL_Handler_Ieee_setCustomEventTime(ccaTime, ccaDuration + IEEE_CCA_START_TIME_MARGIN, false); + ieeeHandlerState.rxTx.ccaTxStartTime = ccaTime; + if (timeSet) + { + ieeeHandlerState.rxTx.txState = txStateWaitForCca; + } + } + else if (allowDelay || ccaScheduling == RCL_Schedule_Now) + { + if (ccaScheduling == RCL_Schedule_Now) + { + ieeeHandlerState.rxTx.ccaTxStartTime = currentTime; + } + else + { + /* Use programmed CCA time for future calculations even if it was in the past */ + ieeeHandlerState.rxTx.ccaTxStartTime = ccaTime; + } + ieeeHandlerState.rxTx.txState = txStateWaitForCca; + /* Start immediately */ + doCca = true; + } + else + { + /* Requested too late */ + txAction->txStatus = RCL_CommandStatus_Error_StartTooLate; + /* Signal end of action */ + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + + if ((rclEventsIn.hardStop && ieeeHandlerState.common.eventTimeType == customEvent) || + (lrfEvents.rfesoft0 && LRF_readRssi() != LRF_RSSI_INVALID)) + { + if (ieeeHandlerState.rxTx.txState == txStateWaitForCca) + { + /* The hard stop event means "do CCA" and will not cause PBE to stop */ + doCca = true; + Log_printf(RclCore, Log_VERBOSE, "Perform CCA"); + /* Set back stop event */ + RCL_Handler_Ieee_restoreStopTime(); + } + } + + if (doCca) + { + RCL_CmdIeee_TxAction *txAction = ieeeCmd->txAction; + RCL_CmdIeee_CcaMode ccaMode = txAction->ccaMode; + txAction->txStatus = RCL_CommandStatus_Active; + + bool busy = false; + /* All CCA modes shall report busy if packet is in progress */ + if (HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXSTATUS) != 0) + { + busy = true; + Log_printf(RclCore, Log_VERBOSE, "CCA busy because packet is in progress"); + if (ieeeHandlerState.rxTx.waitingForValidRssi) + { + LRF_disableHwInterrupt(LRF_EventRfesoft0.value); + ieeeHandlerState.rxTx.waitingForValidRssi = false; + } + } + + if (!busy && (ccaMode != RCL_CmdIeee_CcaMode4Aloha)) + { + /* Check RSSI */ + int8_t rssi = LRF_readRssi(); + /* RSSI is checked even for CCA mode 2, as invalid RSSI means that correlation result is not yet ready */ + if (rssi == LRF_RSSI_INVALID && !ieeeHandlerState.rxTx.waitingForValidRssi) + { + /* Wait for RSSI valid */ + Log_printf(RclCore, Log_VERBOSE, "CCA invalid; check again"); + + ieeeHandlerState.rxTx.waitingForValidRssi = true; + /* Wait 1 backoff period for valid RSSI */ + uint32_t ccaTime = ieeeHandlerState.rxTx.ccaTxStartTime; + ccaTime += IEEE_BACKOFF_PERIOD; + if (txAction->ccaContentionWindow <= 1) + { + /* Non-slotted CSMA - wait only until the RSSI is ready, but use the backoff period as a timeout */ + /* Enable notification on RSSI available */ + LRF_enableHwInterrupt(LRF_EventRfesoft0.value); + } + else + { + /* Store updated CCA time only for slotted CCA */ + ieeeHandlerState.rxTx.ccaTxStartTime = ccaTime; + } + + /* Set new compare time */ + RCL_Handler_Ieee_setCustomEventTime(ccaTime, IEEE_CCA_START_TIME_MARGIN, false); + + /* If RSSI is not valid the second time around, treat as busy */ + } + else + { + bool busyRssi = false; + bool busySignal = false; + + LRF_disableHwInterrupt(LRF_EventRfesoft0.value); + ieeeHandlerState.rxTx.waitingForValidRssi = false; + if (rssi >= txAction->rssiLimit) + { + busyRssi = true; + } + + uint16_t corrCount = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_CORRCNT); + + if (corrCount > txAction->ccaCorrThresh || rssi == LRF_RSSI_INVALID) + { + busySignal = true; + } + + switch (ccaMode) + { + case RCL_CmdIeee_CcaMode1Energy: + busy = busyRssi; + break; + + case RCL_CmdIeee_CcaMode2Signal: + busy = busySignal; + break; + + case RCL_CmdIeee_CcaMode3EnergyOrSignal: + busy = busyRssi || busySignal; + break; + + case RCL_CmdIeee_CcaMode3EnergyAndSignal: + busy = busyRssi && busySignal; + break; + + default: + /* Other values are invalid or should not be processed here - treat as busy */ + busy = true; + break; + } + if (busy) + { + Log_printf(RclCore, Log_VERBOSE, "CCA busy; RSSI = %1d dBm, correlation top count = %1d", rssi, corrCount); + } + else + { + Log_printf(RclCore, Log_VERBOSE, "CCA idle; RSSI = %1d dBm, correlation top count = %1d", rssi, corrCount); + } + } + } + + if (!ieeeHandlerState.rxTx.waitingForValidRssi) + { + if (busy) + { + txAction->txStatus = RCL_CommandStatus_ChannelBusy; + /* Signal end of action */ + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + uint32_t ccaTime = ieeeHandlerState.rxTx.ccaTxStartTime; + ieeeHandlerState.rxTx.ccaContentionWindow -= 1; + if (ieeeHandlerState.rxTx.ccaContentionWindow == 0) + { + /* Channel idle - transmit */ + ieeeHandlerState.rxTx.txState = txStateSetTxTime; + ieeeHandlerState.rxTx.ccaTxStartTime = ccaTime + txAction->relativeTxStartTime; + ieeeHandlerState.rxTx.allowTxDelay = txAction->allowTxDelay; + Log_printf(RclCore, Log_VERBOSE, "Stop RX to go to TX"); + /* Stop running RX */ + LRF_sendHardStop(); + } + else + { + /* Slotted CCA - check again after 1 backoff period */ + ccaTime += IEEE_BACKOFF_PERIOD; + /* Set new compare time */ + RCL_Handler_Ieee_setCustomEventTime(ccaTime, IEEE_CCA_START_TIME_MARGIN, false); + ieeeHandlerState.rxTx.ccaTxStartTime = ccaTime; + } + } + } + } + + if (lrfEvents.rxEmpty != 0) + { + /* Timeout or ACK reception */ + LRF_disableHwInterrupt(LRF_EventRxEmpty.value); + if (ieeeHandlerState.rxTx.txState == txStateTxRxAck) + { + uint16_t ackStatus = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_ACKSTATUS); + + if (ackStatus & PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT_M) + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_NoSync; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else if (ackStatus & PBE_IEEE_RAM_ACKSTATUS_CRCOK_M) + { + if (ieeeHandlerState.rxTx.alwaysStoreAck) + { + /* Need to check sequence number below */ + ieeeHandlerState.rxTx.txState = txStateCheckAck; + } + else + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_Finished; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + else if (ackStatus & + (PBE_IEEE_RAM_ACKSTATUS_IGNORED_M | PBE_IEEE_RAM_ACKSTATUS_OTHERFRM_M | + PBE_IEEE_RAM_ACKSTATUS_CRCERR_M)) + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_RxErr; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + /* ERROR: ACK status gives no known status; should not happen */ + ieeeCmd->txAction->txStatus = RCL_CommandStatus_Error; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + } + if (lrfEvents.txDone != 0) + { + LRF_disableHwInterrupt(LRF_EventTxDone.value); + if (ieeeHandlerState.rxTx.txState == txStateTx || ieeeHandlerState.rxTx.txState == txStateTxRx) + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_Finished; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + if (lrfEvents.opDone != 0 || lrfEvents.opError != 0) + { + uint16_t endCause = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE); + ieeeHandlerState.rxTx.rxState = rxStateNoRx; + if (ieeeHandlerState.rxTx.txState == txStateSetTxTime) + { + /* Set up TX start time */ + RCL_CommandStatus status = RCL_Scheduler_setNewStartAbsTime(ieeeHandlerState.rxTx.ccaTxStartTime, ieeeHandlerState.rxTx.allowTxDelay); + if (status != RCL_CommandStatus_Active) + { + ieeeCmd->txAction->txStatus = status; + ieeeHandlerState.rxTx.txState = txStateFinished; + if (RCL_CommandStatus_isAnyStop(status)) + { + /* Entire command to stop */ + cmd->status = status; + rclEvents.lastCmdDone = 1; + } + } + else + { + LRF_enable(); + startTx = true; + ieeeHandlerState.rxTx.txState = txStateWaitForTx; + } + } + else if (ieeeHandlerState.rxTx.txState == txStateTx) + { + if (lrfEvents.opDone != 0) + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_Finished; + ieeeHandlerState.rxTx.txState = txStateFinished; + + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + else + { + RCL_CommandStatus endStatus = ieeeHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Active) + { + cmd->status = RCL_Handler_Ieee_findPbeErrorEndStatus(endCause); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + } + else if ((ieeeHandlerState.rxTx.txState >= txStateTxRx && ieeeHandlerState.rxTx.txState <= txStateCheckAck) && + endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP && ieeeHandlerState.common.apiHardStopPending) + { + /* Hard stop of ongoing TX action */ + ieeeCmd->txAction->txStatus = RCL_CommandStatus_HardStopApi; + ieeeHandlerState.rxTx.txState = txStateFinished; + /* Stop is now done */ + ieeeHandlerState.common.apiHardStopPending = false; + } + else + { + RCL_CommandStatus endStatus = ieeeHandlerState.common.endStatus; + rclEvents.lastCmdDone = 1; + if (endStatus == RCL_CommandStatus_Active) + { + if (lrfEvents.opError != 0) + { + endStatus = RCL_Handler_Ieee_findPbeErrorEndStatus(endCause); + } + else if (endCause == PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP) + { + endStatus = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + } + else + { + endStatus = RCL_CommandStatus_Finished; + } + } + cmd->status = endStatus; + RCL_Profiling_eventHook(RCL_ProfilingEvent_PostprocStart); + } + } + + if (startTx) + { + RCL_CmdIeee_TxAction *txAction = ieeeCmd->txAction; + txAction->txStatus = RCL_CommandStatus_Active; + + ieeeHandlerState.common.txFifoSize = LRF_prepareTxFifo(); + + if (ieeeCmd->rxAction != NULL && (txAction->expectImmAck || !txAction->endCmdWhenDone)) + { + /* Set TX to proceed with RX */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + PBE_IEEE_RAM_OPCFG_STOP_SOFTEND | + PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES | + PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES | + PBE_IEEE_RAM_OPCFG_TXINFINITE_NO | + PBE_IEEE_RAM_OPCFG_TXPATTERN_NO | + PBE_IEEE_RAM_OPCFG_TXFCMD_NONE | + PBE_IEEE_RAM_OPCFG_START_SYNC | + PBE_IEEE_RAM_OPCFG_SINGLE_DIS | + PBE_IEEE_RAM_OPCFG_IFSPERIOD_EN; + /* RX will be running when TX is done */ + ieeeHandlerState.rxTx.rxState = rxStateWaitForStart; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + PBE_IEEE_RAM_OPCFG_STOP_SOFTEND | + PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES | + PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES | + PBE_IEEE_RAM_OPCFG_TXINFINITE_NO | + PBE_IEEE_RAM_OPCFG_TXPATTERN_NO | + PBE_IEEE_RAM_OPCFG_TXFCMD_NONE | + PBE_IEEE_RAM_OPCFG_START_SYNC | + PBE_IEEE_RAM_OPCFG_SINGLE_EN | + PBE_IEEE_RAM_OPCFG_IFSPERIOD_DIS; + } + + /* Enter payload */ + RCL_Buffer_DataEntry *txEntry = txAction->txEntry; + if (txEntry == NULL) + { + txAction->txStatus = RCL_CommandStatus_Error_MissingTxBuffer; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(txEntry->length) / 4; + + if (wordLength > LRF_getTxFifoWritable() / 4) + { + /* Packet will not fit - probably an error in the packet structure */ + txAction->txStatus = RCL_CommandStatus_Error_TxBufferCorruption; + ieeeHandlerState.rxTx.txState = txStateFinished; + } + else + { + uint32_t *data32 = (uint32_t *) (txEntry); + + /* Copy packet into FIFO */ + LRF_writeTxFifoWords(data32, wordLength); + + /* Enable interrupts */ + LRF_Events interrupts = {.value = (LRF_EventOpDone.value | LRF_EventOpError.value)}; + + if (txAction->expectImmAck) + { + /* Find sequence number from transmitted frame */ + uint8_t seqNo = 0; + uint32_t pos = txEntry->numPad - sizeof(txEntry->pad0) + IEEE_PHY_HDR_LEN + IEEE_MAC_FCF_LEN; + if (txEntry->length >= sizeof(txEntry->numPad) + sizeof(txEntry->pad0) + pos) + { + seqNo = txEntry->data[pos]; + } + + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXTIMEOUT) = txAction->ackTimeout; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_CFGAUTOACK) = + (ieeeHandlerState.rxTx.alwaysStoreAck ? + PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_NOFILT : + PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_FILT) | + PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_EN | + (seqNo << PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_S); + /* Get informed on ACK result */ + interrupts.rxEmpty = 1; + ieeeHandlerState.rxTx.txState = txStateTxRxAck; + ieeeHandlerState.rxTx.expSeqNo = seqNo; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_RXTIMEOUT) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_CFGAUTOACK) = + PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_NOFILT | PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_DIS; + + if (ieeeCmd->rxAction != NULL && !txAction->endCmdWhenDone) + { + /* RX will go on, but TX action is finished at the end of TX */ + interrupts.txDone = 1; + ieeeHandlerState.rxTx.txState = txStateTxRx; + } + else + { + ieeeHandlerState.rxTx.txState = txStateTx; + } + } + /* Clear and enable interrupts */ + LRF_clearHwInterrupt(interrupts.value); + LRF_enableHwInterrupt(interrupts.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting IEEE TX"); + LRF_waitForTopsmReady(); + RCL_Profiling_eventHook(RCL_ProfilingEvent_PreprocStop); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_IEEE_REGDEF_API_OP_TX; + } + } + } + + if ((lrfEvents.rxOk != 0 || lrfEvents.rxNok != 0 || lrfEvents.rxIgnored != 0) && ieeeCmd->rxAction != NULL) + { + /* Copy received packet from PBE FIFO to buffer */ + /* First, check that there is actually a buffer available */ + uint32_t rxFifoReadable = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE); + while (rxFifoReadable >= 4) + { + /* Check length of received buffer by peeking */ + uint32_t fifoWord = LRF_peekRxFifo(0); + uint32_t wordLength = RCL_Buffer_DataEntry_paddedLen(fifoWord & 0xFFFF) / 4; + if (wordLength > 0) + { + RCL_MultiBuffer *curBuffer; + if (wordLength * 4 > rxFifoReadable) + { + /* Error */ + curBuffer = NULL; + } + else + { + curBuffer = RCL_MultiBuffer_getBuffer(ieeeHandlerState.common.curBuffer, + wordLength * 4); + if (curBuffer != ieeeHandlerState.common.curBuffer) { + rclEvents.rxBufferFinished = 1; + ieeeHandlerState.common.curBuffer = curBuffer; + } + } + if (curBuffer == NULL) { + /* Error */ + ieeeHandlerState.common.endStatus = RCL_CommandStatus_Error_RxBufferCorruption; + /* Send abort */ + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_IEEE_REGDEF_API_OP_STOP; + /* Do not check for more packets from the RX FIFO */ + break; + } + else { + uint32_t *data32; + data32 = (uint32_t *)RCL_MultiBuffer_getNextWritableByte(curBuffer); + LRF_readRxFifoWords(data32, wordLength); + RCL_MultiBuffer_commitBytes(curBuffer, wordLength * 4); + /* Raise event */ + rclEvents.rxEntryAvail = 1; + /* Adjust effective FIFO size */ + RCL_Handler_Ieee_updateRxCurBufferAndFifo(&ieeeCmd->rxAction->rxBuffers); + if (ieeeHandlerState.rxTx.txState == txStateCheckAck) + { + if (lrfEvents.rxOk && wordLength >= 2) + { + /* Read out sequence number; expect rest of the frame to be checked OK by PBE */ + RCL_Buffer_DataEntry *entry = (RCL_Buffer_DataEntry *) data32; + uint8_t seqNo = entry->data[entry->numPad - sizeof(entry->pad0) + IEEE_PHY_HDR_LEN + IEEE_MAC_FCF_LEN]; + if (seqNo == ieeeHandlerState.rxTx.expSeqNo) + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_Finished; + } + else + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_RxErr; + } + } + else + { + ieeeCmd->txAction->txStatus = RCL_CommandStatus_RxErr; + } + ieeeHandlerState.rxTx.txState = txStateFinished; + } + } + } + rxFifoReadable = HWREG_READ_LRF(LRFDPBE_BASE + LRFDPBE_O_RXFREADABLE); + } + if (ieeeHandlerState.common.activeUpdate) + { + RCL_Handler_Ieee_updateStats(ieeeCmd->stats, rclSchedulerState.actualStartTime); + } + } + if (lrfEvents.txAck != 0 && ieeeCmd->rxAction != NULL) + { + if (ieeeHandlerState.common.activeUpdate) + { + RCL_Handler_Ieee_updateStats(ieeeCmd->stats, rclSchedulerState.actualStartTime); + } + } + + if (ieeeHandlerState.rxTx.txState == txStateFinished && cmd->status == RCL_CommandStatus_Active) + { + rclEvents.cmdStepDone = 1; + LRF_disableHwInterrupt(LRF_EventRfesoft0.value); + + if (ieeeCmd->txAction->endCmdWhenDone || ieeeCmd->rxAction == NULL) + { + if (ieeeHandlerState.rxTx.rxState != rxStateNoRx) + { + /* Stop running RX and let it finish */ + ieeeHandlerState.common.endStatus = ieeeCmd->txAction->txStatus; + Log_printf(RclCore, Log_VERBOSE, "Stop RX as command should end"); + LRF_sendHardStop(); + ieeeHandlerState.rxTx.txState = txStateWaitForCmdEnd; + } + else + { + /* End now */ + cmd->status = ieeeCmd->txAction->txStatus; + rclEvents.lastCmdDone = 1; + ieeeHandlerState.rxTx.txState = txStateNoTx; + } + } + else + { + if (ieeeHandlerState.rxTx.rxState == rxStateNoRx) + { + LRF_enable(); + /* Restart RX */ + restartRx = true; + } + ieeeHandlerState.rxTx.txState = txStateNoTx; + } + if (ieeeHandlerState.common.activeUpdate) + { + RCL_Handler_Ieee_updateStats(ieeeCmd->stats, rclSchedulerState.actualStartTime); + } + } + } + if (restartRx) + { + RCL_CommandStatus status = RCL_Scheduler_setNewStartNow(); + if (status == RCL_CommandStatus_Active) + { + /* Set up for RX */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + PBE_IEEE_RAM_OPCFG_STOP_SOFTEND | + PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES | + PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES | + PBE_IEEE_RAM_OPCFG_TXINFINITE_NO | + PBE_IEEE_RAM_OPCFG_TXPATTERN_NO | + PBE_IEEE_RAM_OPCFG_TXFCMD_NONE | + PBE_IEEE_RAM_OPCFG_START_SYNC | + PBE_IEEE_RAM_OPCFG_SINGLE_DIS | + PBE_IEEE_RAM_OPCFG_IFSPERIOD_EN; + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Restarting IEEE RX"); + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_IEEE_REGDEF_API_OP_RX; + /* Clear RSSI valid interrupt flag */ + LRF_clearHwInterrupt(LRF_EventRfesoft0.value); + ieeeHandlerState.rxTx.rxState = rxStateRunning; + } + else + { + cmd->status = status; + rclEvents.lastCmdDone = 1; + } + } + + if (rclEvents.lastCmdDone != 0) + { + /* Check if TX action has finished */ + if (ieeeHandlerState.rxTx.txState != txStateNoTx) + { + Log_printf(RclCore, Log_VERBOSE, "TX action ending because command ended"); + if (ieeeCmd->txAction != NULL && ieeeCmd->txAction->txStatus < RCL_CommandStatus_Finished) + { + /* End status not set - use command end status to show it ended with command */ + ieeeCmd->txAction->txStatus = cmd->status; + } + rclEvents.cmdStepDone = 1; + } + LRF_disable(); + LRF_disableSynthRefsys(); + RCL_Handler_Ieee_updateStats(ieeeCmd->stats, rclSchedulerState.actualStartTime); + } + return rclEvents; +} + +/* + * ======== RCL_Handler_Ieee_TxTest ======== + */ +RCL_Events RCL_Handler_Ieee_TxTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn) +{ + RCL_CmdIeeeTxTest *txCmd = (RCL_CmdIeeeTxTest *) cmd; + RCL_Events rclEvents = {.value = 0}; + + if (rclEventsIn.setup != 0) + { + uint32_t earliestStartTime; + + /* Start by enabling refsys */ + earliestStartTime = LRF_enableSynthRefsys(); + ieeeHandlerState.txTest.restoreOpt = RCL_HANDLER_IEEE_RESTORE_NONE; + ieeeHandlerState.common.apiHardStopPending = false; + if ((txCmd->rfFrequency == 0) && ((HWREG_READ_LRF(LRFDRFE_BASE + LRFDRFE_O_SPARE4) & 0x0001) == 0)) + { + /* Synth not to be programmed, but not already locked */ + cmd->status = RCL_CommandStatus_Error_Synth; + rclEvents.lastCmdDone = 1; + } + else + { + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + PBE_IEEE_RAM_OPCFG_RXREPEATOK_NO | + PBE_IEEE_RAM_OPCFG_RXREPEATNOK_NO | + PBE_IEEE_RAM_OPCFG_TXINFINITE_YES | + PBE_IEEE_RAM_OPCFG_TXPATTERN_YES | + PBE_IEEE_RAM_OPCFG_TXFCMD_NONE | + PBE_IEEE_RAM_OPCFG_START_SYNC | + PBE_IEEE_RAM_OPCFG_SINGLE_EN | + PBE_IEEE_RAM_OPCFG_IFSPERIOD_DIS; + + /* Mark as active */ + cmd->status = RCL_CommandStatus_Active; + /* End status not determined */ + ieeeHandlerState.common.endStatus = RCL_CommandStatus_Active; + + if (LRF_programTxPower(txCmd->txPower) != TxPowerResult_Ok) + { + cmd->status = RCL_CommandStatus_Error_Param; + rclEvents.lastCmdDone = 1; + } + + /* Enter configuration */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_PATTERN) = txCmd->txWord; + if (txCmd->config.sendCw != 0) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) | LRFDMDM_MODCTRL_TONEINSERT_M; + ieeeHandlerState.txTest.restoreOpt = RCL_HANDLER_IEEE_RESTORE_MODCTRL; + } + else + { + uint32_t whitenMode = txCmd->config.whitenMode; + /* Configure whitening */ + if (whitenMode != RCL_CMD_IEEE_WH_MODE_OFF) + { + ieeeHandlerState.txTest.restoreOpt = RCL_HANDLER_IEEE_RESTORE_WHITENING; + ieeeHandlerState.txTest.storedWhitenPoly = HWREG_READ_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0); + ieeeHandlerState.txTest.storedWhitenInit = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_WHITEINIT); + uint32_t whitenPoly; + switch (whitenMode) + { + case RCL_CMD_IEEE_WH_MODE_PRBS9: + default: + whitenPoly = RCL_HANDLER_IEEE_PRBS9_POLY; + break; + case RCL_CMD_IEEE_WH_MODE_PRBS15: + whitenPoly = RCL_HANDLER_IEEE_PRBS15_POLY; + break; + case RCL_CMD_IEEE_WH_MODE_PRBS32: + whitenPoly = RCL_HANDLER_IEEE_PRBS32_POLY; + break; + } + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = whitenPoly; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_WHITEINIT) = RCL_HANDLER_IEEE_PRBS_INIT; + } + + ieeeHandlerState.txTest.restoreOpt |= RCL_HANDLER_IEEE_RESTORE_SFD; + ieeeHandlerState.txTest.storedMdmSyncA = HWREG_READ_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA); + /* Set non-standard SFD */ + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ieeeHandlerState.txTest.storedMdmSyncA ^ 0x00FF; + } + /* Enable radio */ + LRF_enable(); + + RCL_CommandStatus startTimeStatus = RCL_Scheduler_setStartStopTimeEarliestStart(cmd, earliestStartTime); + if (startTimeStatus >= RCL_CommandStatus_Finished) + { + cmd->status = startTimeStatus; + rclEvents.lastCmdDone = 1; + } + else + { + /* Program frequency word */ + LRF_programFrequency(txCmd->rfFrequency, true); + + /* Enable interrupts */ + LRF_enableHwInterrupt(LRF_EventOpDone.value | LRF_EventOpError.value); + + /* Post cmd */ + Log_printf(RclCore, Log_VERBOSE, "Starting infinite TX"); + + LRF_waitForTopsmReady(); + HWREG_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_API) = PBE_IEEE_REGDEF_API_OP_TX; + } + } + } + + if (cmd->status == RCL_CommandStatus_Active) + { + if (rclEventsIn.timerStart != 0) + { + rclEvents.cmdStarted = 1; + } + if (lrfEvents.opDone != 0) + { + RCL_CommandStatus endStatus = ieeeHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Active) + { + cmd->status = RCL_CommandStatus_Finished; + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else if (lrfEvents.opError != 0) + { + RCL_CommandStatus endStatus = ieeeHandlerState.common.endStatus; + if (endStatus == RCL_CommandStatus_Active) + { + cmd->status = RCL_Handler_Ieee_findPbeErrorEndStatus(HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_COMMON_RAM_O_ENDCAUSE)); + } + else + { + cmd->status = endStatus; + } + rclEvents.lastCmdDone = 1; + } + else + { + /* Other events need to be handled unconditionally */ + } + } + + if (rclEvents.lastCmdDone != 0) + { + LRF_disable(); + LRF_disableSynthRefsys(); + if ((ieeeHandlerState.txTest.restoreOpt & RCL_HANDLER_IEEE_RESTORE_MODCTRL) != 0) + { + HWREG_WRITE_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) = HWREG_READ_LRF(LRFDMDM_BASE + LRFDMDM_O_MODCTRL) & (~LRFDMDM_MODCTRL_TONEINSERT_M); + } + if ((ieeeHandlerState.txTest.restoreOpt & RCL_HANDLER_IEEE_RESTORE_WHITENING) != 0) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_POLY0) = ieeeHandlerState.txTest.storedWhitenPoly; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_WHITEINIT) = ieeeHandlerState.txTest.storedWhitenInit; + } + if ((ieeeHandlerState.txTest.restoreOpt & RCL_HANDLER_IEEE_RESTORE_SFD) != 0) + { + HWREG_WRITE_LRF(LRFDPBE32_BASE + LRFDPBE32_O_MDMSYNCA) = ieeeHandlerState.txTest.storedMdmSyncA; + } + } + + return rclEvents; +} + +/* + * ======== RCL_IEEE_Tx_submit ======== + */ +RCL_CommandStatus RCL_IEEE_Tx_submit(RCL_CmdIeeeRxTx *cmd, RCL_CmdIeee_TxAction *txAction) +{ + RCL_CommandStatus status = RCL_CommandStatus_Idle; + /* Can't submit action again if already submitted */ + if (txAction->txStatus != RCL_CommandStatus_Idle && txAction->txStatus < RCL_CommandStatus_Finished) + { + return RCL_CommandStatus_Error_AlreadySubmitted; + } + + uintptr_t key = HwiP_disable(); + /* Check if command is finished */ + if (cmd == NULL || cmd->common.status >= RCL_CommandStatus_Finished) + { + /* TODO: New status */ + Log_printf(RclCore, Log_ERROR, "Command ended before TX action was submitted"); + status = RCL_CommandStatus_Error; + } + else if (cmd->txAction != NULL && cmd->txAction->txStatus != RCL_CommandStatus_Idle && cmd->txAction->txStatus < RCL_CommandStatus_Finished) + { + /* Another TX action is already running */ + status = RCL_CommandStatus_Error_AlreadySubmitted; + } + /* Extra check in case user modified status field */ + else if (rclSchedulerState.currCmd == &cmd->common && ieeeHandlerState.rxTx.txState != txStateNoTx) + { + status = RCL_CommandStatus_Error_AlreadySubmitted; + } + + if (status != RCL_CommandStatus_Idle) + { + HwiP_restore(key); + + return status; + } + else + { + /* Insert TX action */ + txAction->txStatus = RCL_CommandStatus_Idle; + cmd->txAction = txAction; + + if (rclSchedulerState.currCmd == &cmd->common) + { + /* Trigger handler */ + ieeeHandlerState.rxTx.txState = txStateNewAction; + RCL_Scheduler_postEvent(&cmd->common, RCL_EventHandlerCmdUpdate); + } + HwiP_restore(key); + + return txAction->txStatus; + } +} + +/* + * ======== RCL_IEEE_Tx_stop ======== + */ +RCL_CommandStatus RCL_IEEE_Tx_stop(RCL_CmdIeeeRxTx *cmd, RCL_StopType stopType) +{ + if (cmd == NULL) + { + return RCL_CommandStatus_Error_Param; + } + uintptr_t key = HwiP_disable(); + RCL_CmdIeee_TxAction *txAction = cmd->txAction; + if (txAction == NULL) + { + /* No TX action at all */ + HwiP_restore(key); + return RCL_CommandStatus_Error_Param; + } + /* Check command state */ + else if (cmd->common.status < RCL_CommandStatus_Active) + { + /* TX action can be descheduled without any other action */ + txAction->txStatus = RCL_CommandStatus_DescheduledApi; + /* In this case, we have to set the TX action to NULL to avoid it starting */ + cmd->txAction = NULL; + } + else if (cmd->common.status < RCL_CommandStatus_Finished) + { + /* Inform handler about stop */ + ieeeHandlerState.rxTx.txActionStop = stopType; + RCL_Scheduler_postEvent(&cmd->common, RCL_EventHandlerCmdUpdate); + } + else + { + /* Command finished; nothing to do about TX action */ + } + HwiP_restore(key); + + return txAction->txStatus; +} + +/* + * ======== RCL_Handler_Ieee_updateRxCurBufferAndFifo ======== + */ +static void RCL_Handler_Ieee_updateRxCurBufferAndFifo(List_List *rxBuffers) +{ + RCL_MultiBuffer *curBuffer = ieeeHandlerState.common.curBuffer; + + if (curBuffer == NULL) + { + curBuffer = RCL_MultiBuffer_findFirstWritableBuffer((RCL_MultiBuffer *)rxBuffers->head); + } + ieeeHandlerState.common.curBuffer = curBuffer; + + uint32_t rxSpace = RCL_MultiBuffer_findAvailableRxSpace(curBuffer); + + LRF_setRxFifoEffSz(rxSpace); +} + +/* + * ======== RCL_Handler_Ieee_findPbeErrorEndStatus ======== + */ +static RCL_CommandStatus RCL_Handler_Ieee_findPbeErrorEndStatus(uint16_t pbeEndStatus) +{ + RCL_CommandStatus status; + switch (pbeEndStatus) + { + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_RXF: + status = RCL_CommandStatus_Error_RxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_TXF: + status = RCL_CommandStatus_Error_TxFifo; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_SYNTH: + status = RCL_CommandStatus_Error_Synth; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_RXTIMEOUT: + status = RCL_CommandStatus_RxTimeout; + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_EOPSTOP: + status = RCL_Scheduler_findStopStatus(RCL_StopType_Graceful); + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_STOP: + if (ieeeHandlerState.common.apiHardStopPending) + { + status = RCL_CommandStatus_HardStopApi; + } + else + { + status = RCL_Scheduler_findStopStatus(RCL_StopType_Hard); + } + break; + case PBE_COMMON_RAM_ENDCAUSE_STAT_ERR_BADOP: + status = RCL_CommandStatus_Error_UnknownOp; + break; + default: + Log_printf(RclCore, Log_ERROR, "Unexpected error 0x%04X from PBE", pbeEndStatus); + status = RCL_CommandStatus_Error; + break; + } + return status; +} + +/* + * ======== RCL_Handler_Ieee_maskEventsByFifoConf ======== + */ +static uint32_t RCL_Handler_Ieee_maskEventsByFifoConf(uint32_t mask, uint16_t fifoConfVal, bool activeUpdate) +{ + /* Remove events that will not give an entry in the RX FIFO, based on FIFOCFG, unless active update is used */ + if (!activeUpdate) + { + /* Remove events that will not give an entry in the RX FIFO, based on FIFOCFG. */ + mask &= ~(((fifoConfVal & PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_M) ? LRF_EventRxIgnored.value : 0) | + ((fifoConfVal & PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_M) ? LRF_EventRxNok.value : 0) | + LRF_EventRxBufFull.value); + } + return mask; +} + +/* + * ======== RCL_Handler_Ieee_updateRxStats ======== + */ +static void RCL_Handler_Ieee_updateStats(RCL_StatsIeee *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Read LASTTIMESTAMP andf LASTTIMESTAMPH as one unit */ + uint32_t lastTimestamp = HWREG_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_LASTTIMESTAMPL); + + /* Check if a new value is found in the first timestamp */ + if (lastTimestamp == startTime) + { + stats->timestampValid = false; + } + else { + stats->timestampValid = true; + stats->lastTimestamp = lastTimestamp; + } + stats->lastRssi = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_LASTRSSI); + stats->nRxNok = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXNOK); + stats->nRxFifoFull = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXFIFOFULL); + stats->nRxOk = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXOK); + stats->nRxIgnored = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXIGNORED); + stats->nTx = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTX); + stats->nTxAck = HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTXACK); + } +} + +/* + * ======== RCL_Handler_Ieee_initStats ======== + */ +static bool RCL_Handler_Ieee_initStats(RCL_StatsIeee *stats, uint32_t startTime) +{ + if (stats != NULL) + { + /* Set timestamp to start time of command (will not occur again) to know if a valid value has been found */ + /* This accesses PBE_IEEE_RAM_O_LASTTIMESTAMPL and PBE_IEEE_RAM_O_LASTTIMESTAMPH */ + HWREG_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_LASTTIMESTAMPL) = startTime; + stats->timestampValid = false; + stats->lastRssi = LRF_RSSI_INVALID; + if (stats->config.accumulate != 0) + { + /* Copy existing values into PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXNOK) = stats->nRxNok; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXFIFOFULL) = stats->nRxFifoFull; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXOK) = stats->nRxOk; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXIGNORED) = stats->nRxIgnored; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTX) = stats->nTx; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTXACK) = stats->nTxAck; + } + else + { + /* Reset existing values in PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXNOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXFIFOFULL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXIGNORED) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTX) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTXACK) = 0; + + stats->nRxNok = 0; + stats->nRxFifoFull = 0; + stats->nRxOk = 0; + stats->nRxIgnored = 0; + stats->nTx = 0; + stats->nTxAck = 0; + } + return stats->config.activeUpdate; + } + else + { + /* Reset existing values in PBE */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXNOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXFIFOFULL) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXOK) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NRXIGNORED) = 0; + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_NTX) = 0; + + return false; + } +} + +static bool RCL_Handler_Ieee_setCustomEventTime(uint32_t eventTime, uint32_t timeMargin, bool hardStop) +{ + uint32_t activeStopTime; + if (rclSchedulerState.hardStopInfo.stopReason != RCL_SchedulerStopReason_None) + { + if (rclSchedulerState.hardStopInfo.stopReason == RCL_SchedulerStopReason_Timeout) + { + activeStopTime = rclSchedulerState.hardStopInfo.cmdStopTime; + } + else if (rclSchedulerState.hardStopInfo.stopReason == RCL_SchedulerStopReason_Scheduling) + { + activeStopTime = rclSchedulerState.hardStopInfo.schedStopTime; + } + else + { + /* Otherwise API stop is active and command should stop shortly */ + activeStopTime = RCL_Scheduler_getCurrentTime(); + } + } + if (rclSchedulerState.hardStopInfo.stopReason == RCL_SchedulerStopReason_None || + RCL_Scheduler_isLater(eventTime + timeMargin, activeStopTime)) + { + if (hardStop) + { + /* Program hard stop time */ + hal_setup_hard_stop_time(eventTime); + /* Flag as custom time */ + ieeeHandlerState.common.nextEventTime = eventTime; + ieeeHandlerState.common.eventTimeType = customHardStop; + } + else + { + /* Change the stop time and set it to a soft timing */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) | PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_M; + hal_setup_hard_stop_time(eventTime); + hal_enable_hard_stop_time_irq(); + ieeeHandlerState.common.nextEventTime = eventTime; + ieeeHandlerState.common.eventTimeType = customEvent; + } + return true; + } + else + { + /* Command will stop very soon, so time not set */ + if (ieeeHandlerState.common.eventTimeType != noEvent) + { + RCL_Handler_Ieee_restoreStopTime(); + } + return false; + } +} + +static bool RCL_Handler_Ieee_restoreStopTime(void) +{ + if (ieeeHandlerState.common.eventTimeType != noEvent) + { + hal_cancel_hard_stop_time(); + /* Set back stop event */ + RCL_StopType stopType = RCL_Scheduler_setStopTimes(); + + /* Clear systimer event in TOPsm to avoid an old event stopping the RX */ + HWREGH_WRITE_LRF(LRFDPBE_BASE + LRFDPBE_O_EVTCLR0) = LRFDPBE_EVTCLR0_SYSTCMP0_M; + + /* Set stop time back to hard stop */ + HWREGH_WRITE_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) = + HWREGH_READ_LRF(LRFD_BUFRAM_BASE + PBE_IEEE_RAM_O_OPCFG) & ~PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_M; + + ieeeHandlerState.common.eventTimeType = noEvent; + /* If hard stop already occurred, it needs to be executed (unless already planned) */ + /* Other stop types returned should not need special handling */ + if (stopType == RCL_StopType_Hard) + { + if (rclSchedulerState.hardStopInfo.apiStopEnabled == 0) + { + LRF_sendHardStop(); + rclSchedulerState.hardStopInfo.apiStopEnabled = 1; + } + return true; + } + } + return false; +} +#endif diff --git a/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.h b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.h new file mode 100644 index 00000000..d9a50bc1 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/handlers/ieee.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_RCL_handlers_ieee_h__include +#define ti_drivers_RCL_handlers_ieee_h__include + +#include +#include +#include +#include +#include + +/* Handler functions */ +RCL_Events RCL_Handler_Ieee_RxTx(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); +RCL_Events RCL_Handler_Ieee_TxTest(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEventsIn); + +/** + * @brief Result of IEEE command update API + * + * Tells if update of IEEE command fields succeeded + */ +typedef enum +{ + RCL_IEEE_UpdateOk, /*!< Update was successful */ + RCL_IEEE_UpdateIndexError, /*!< Index was out of range or pointer was NULL */ +} RCL_IEEE_UpdateResult; + +/** + * @brief Result of entering ACK frame + * + * Tells if ACK frame was entered successfully + */ +typedef enum +{ + RCL_IEEE_AckOk, /*!< ACK was entered successfully */ + RCL_IEEE_AckNotExpected, /*!< Ack was not expected */ + RCL_IEEE_AckTooLate, /*!< Ack was provided too late */ + RCL_IEEE_AckError, /*!< Data entry or pointer was not correct */ +} RCL_IEEE_AckEntryResult; + + +/* API functions */ +/** + * @brief Update short source matching table + * + * Update the given source matching table filter list in a way that is safe even if a running command is using + * the filter table. + * + * @param newAddr New address and PAN ID to apply; NULL to leave unchanged + * @param framePending Value of frame pending bit + * @param table Source matching table to update + * @param index Index into source matching table to update + * + * @return Result telling if update was successful + * @note Not supported in this version + * + */ +RCL_IEEE_UpdateResult RCL_IEEE_updateSourceMatchingTableShort(RCL_CmdIeee_PanIdAddr *newAddr, uint8_t framePending, RCL_CmdIeee_SourceMatchingTableShort *table, uint32_t index); + +/** + * @brief Update frame filtering settings extended source matching table + * + * Update the given frame filtering settings in a way that is safe even if a running command is receiving a frame + * + * @param cmd Existing IEEE command to update + * @param newPanConfig New PAN configuration to apply + * @param panNumber Index of PAN to update + * + * @return Result telling if update was successful + * @note Not supported in this version + * + */ +RCL_IEEE_UpdateResult RCL_IEEE_updateSourceMatchingTableExt(RCL_CmdIeeeRxTx *cmd, RCL_CmdIeee_PanConfig *newPanConfig, uint32_t panNumber); + +/** + * @brief Provide ACK frame to be transmitted in response to received packet + * + * Provide an ACK frame, which will be transmitted if the frame was received successfully + * + * @param cmd Existing IEEE command for which to enter ACK + * @param ackEntry ACK to be transmitted over the air + * + * @return Result telling if update was successful + * @note Not supported in this version + * + */ +RCL_IEEE_AckEntryResult RCL_IEEE_enterAck(RCL_CmdIeeeRxTx *cmd, RCL_Buffer_DataEntry *ackEntry); + +/** + * @brief Update tx action + * + * @param cmd Existing IEEE command to submit the TX on top of + * @param txAction TX action to apply + * + * @return %RCL_CommandStatus result of the submission + * + */ +RCL_CommandStatus RCL_IEEE_Tx_submit(RCL_CmdIeeeRxTx *cmd, RCL_CmdIeee_TxAction *txAction); + +/** + * @brief Stop a Tx action in an IEEE command + * + * Sends the message to try to stop a TX action. When the function returns, the command may still be + * running. Depending on the stop type, the operation may stop after some time. + * + * @param cmd [in] IEEE command + * @param stopType [in] Stop type; telling which situations the operation will stop + * + * @return Status of the TX operation; if the operation is not finished, a wait is needed. + * + */ +RCL_CommandStatus RCL_IEEE_Tx_stop(RCL_CmdIeeeRxTx *cmd, RCL_StopType stopType); + +/** + * @brief Wait for a submitted TX operation to complete. + * + * Uses %SemaphoreP_pend to block in the callers context. + * + * @pre This function must be called from a task context, with interrupts enabled. + * + * @param[in] cmd IEEE command running + * + * @return Status of the TX operation + * @note Not supported in this version + * + */ +RCL_CommandStatus RCL_IEEE_Tx_pend(RCL_CmdIeeeRxTx *cmd); + +/** + * @brief Get received RSSI from packet + * + * Returns the RSSI field of a received packet, or LRF_RSSI_INVALID if RSSI is not enabled + * + * @param rxEntry Received data entry + * + * @return Reported RSSI of received packet + * @note Not supported in this version + * + */ +int8_t RCL_IEEE_getRxRssi(const RCL_Buffer_DataEntry *rxEntry); + +/** + * @brief Get received timestamp from packet + * + * Returns the timestamp a received packet, adjusted to point to the start of the preamble. + * If timestamp is not enabled, 0 is returned. + * Note that 0 is a valid value, so it cannot be used for error checking. + * + * @param rxEntry Received data entry + * + * @return Timestamp of received packet + * @note Not supported in this version + * + */ +uint32_t RCL_IEEE_getRxTimestamp(const RCL_Buffer_DataEntry *rxEntry); + +#endif /* ti_drivers_RCL_handlers_ble5_h__include */ diff --git a/simplelink_lpf3/source/ti/drivers/rcl/wrappers/RCL_AdcNoise.c b/simplelink_lpf3/source/ti/drivers/rcl/wrappers/RCL_AdcNoise.c new file mode 100644 index 00000000..c1112a73 --- /dev/null +++ b/simplelink_lpf3/source/ti/drivers/rcl/wrappers/RCL_AdcNoise.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include + +#include +#include + +#include + +#include DeviceFamily_constructPath(inc/hw_lrfddbell.h) +#include DeviceFamily_constructPath(inc/pbe_common_ram_regs.h) + +extern const LRF_Config LRF_configAdcNoise; + +/* Place necessary RCL structs in BUFRAM to avoid using static SYSRAM. This saves 148 B */ +/* Note that we need to skip the part of the BUFRAM used by common RAM variables, as they + may be written by the RCL */ +#define PBE_COMMON_RAM_REGISTER_END_OFFSET 32UL +/* We know that the PBE_COMMON_RAM_FIFOCMDADD register is used by the LRF setup, so at least make sure that this is covered */ +#if (PBE_COMMON_RAM_FIFOCMDADD_ADR >= (BUF_RAM_BASE_ADDR + PBE_COMMON_RAM_REGISTER_END_OFFSET)) +#error "BUFRAM memory used by ADC noise wrapper overlaps initialized RAM variable" +#endif + +#define RCL_CLIENT_ADDR (BUF_RAM_BASE_ADDR + PBE_COMMON_RAM_REGISTER_END_OFFSET) +#define RCL_ADC_NOISE_CMD_ADDR (RCL_CLIENT_ADDR + sizeof(RCL_Client)) +#define CALLBACK_ADDR (RCL_ADC_NOISE_CMD_ADDR + sizeof(RCL_CmdAdcNoiseGet)) + +#define RCL_CLIENT_PTR ((RCL_Client*)RCL_CLIENT_ADDR) +#define RCL_ADC_NOISE_CMD_PTR ((RCL_CmdAdcNoiseGet*)RCL_ADC_NOISE_CMD_ADDR) +#define CALLBACK_PTR ((applicationCallback_t*)CALLBACK_ADDR) + +#define STATUS_SUCCESS 0 +#define STATUS_ERROR -1 +#define RCL_STATUS_TO_WRAPPER_STATUS(x) ((x) == RCL_CommandStatus_Finished ? STATUS_SUCCESS : STATUS_ERROR) + +/* Callback function type */ +typedef void (*applicationCallback_t)(uint32_t* buffer, uint32_t numWords, int_fast16_t status); + +/****************************************************************************** + * Internal callback function + ******************************************************************************/ +static void adcNoiseCallback(RCL_Command *cmd, LRF_Events lrfEvents, RCL_Events rclEvents) +{ + RCL_CmdAdcNoiseGet *adcCmd = (RCL_CmdAdcNoiseGet *)cmd; + + applicationCallback_t callback = *CALLBACK_PTR; + + callback(adcCmd->output, adcCmd->numWords, RCL_STATUS_TO_WRAPPER_STATUS(cmd->status)); + + /* Close the RCL client */ + RCL_close(cmd->runtime.client); + + /* This must come after closing because command and client structs are in BUFRAM */ + Power_releaseDependency(PowerLPF3_PERIPH_LRFD_BUFRAM); + + /* Release power constraint to allow standby */ + hal_power_release_constraint(); +} + +/****************************************************************************** + * Public API + ******************************************************************************/ + + +/* + * ======== RCL_AdcNoise_get_samples_blocking ======== + */ +int_fast16_t RCL_AdcNoise_get_samples_blocking(uint32_t* buffer, uint32_t numWords) +{ + RCL_CommandStatus status; + RCL_CmdAdcNoiseGet *adcNoiseCmd = RCL_ADC_NOISE_CMD_PTR; + + /* Turn on BUFRAM before calling RCL_open, since the RCL_client resides in BUFRAM */ + Power_setDependency(PowerLPF3_PERIPH_LRFD_BUFRAM); + + /* Prevent the system from going to standby because BUFRAM doesn't have retention */ + hal_power_set_constraint(); + + RCL_init(); + + /* Open client and provide settings */ + RCL_Handle h = RCL_open(RCL_CLIENT_PTR, &LRF_configAdcNoise); + + *adcNoiseCmd = RCL_CmdAdcNoiseGet_Default(); + + /* Set number of sample words */ + adcNoiseCmd->numWords = numWords; + adcNoiseCmd->output = buffer; + + /* Submit the command */ + status = RCL_Command_submit(h, adcNoiseCmd); + + if (status <= RCL_CommandStatus_Finished) + { + /* Wait for the command to finish. The thread will yield and other threads can run. */ + status = RCL_Command_pend(adcNoiseCmd); + } + + /* Close the RCL client */ + RCL_close(h); + + /* This must come after closing because command and client structs are in BUFRAM */ + Power_releaseDependency(PowerLPF3_PERIPH_LRFD_BUFRAM); + + /* Release power constraint to allow standby */ + hal_power_release_constraint(); + + return RCL_STATUS_TO_WRAPPER_STATUS(status); +} + +/* + * ======== RCL_AdcNoise_get_samples_callback ======== + * + * NOTE: This function must be called from a task context, with interrupts enabled + */ +int_fast16_t RCL_AdcNoise_get_samples_callback(uint32_t* buffer, uint32_t numWords, applicationCallback_t callback) +{ + RCL_CommandStatus status; + RCL_CmdAdcNoiseGet *adcNoiseCmd = RCL_ADC_NOISE_CMD_PTR; + + /* Turn on BUFRAM before calling RCL_open, since the RCL_client resides in BUFRAM */ + Power_setDependency(PowerLPF3_PERIPH_LRFD_BUFRAM); + + /* Prevent the system from going to standby because BUFRAM doesn't have retention */ + hal_power_set_constraint(); + + RCL_init(); + + /* Open client and provide settings */ + RCL_Handle h = RCL_open(RCL_CLIENT_PTR, &LRF_configAdcNoise); + + *adcNoiseCmd = RCL_CmdAdcNoiseGet_Default(); + + /* Set number of sample words */ + adcNoiseCmd->numWords = numWords; + adcNoiseCmd->output = buffer; + + /* Set callback function to be run at the end of the command */ + adcNoiseCmd->common.runtime.callback = adcNoiseCallback; + + *CALLBACK_PTR = callback; + + /* Run callback at the end of the command only */ + adcNoiseCmd->common.runtime.rclCallbackMask.value = RCL_EventLastCmdDone.value; + + /* Submit the command */ + status = RCL_Command_submit(h, adcNoiseCmd); + + return RCL_STATUS_TO_WRAPPER_STATUS(status); +} From 68e86d93d3219435370d63e3a5984edc14c5620e Mon Sep 17 00:00:00 2001 From: Julien Panis Date: Tue, 14 Jan 2025 11:06:11 +0100 Subject: [PATCH 6/7] simplelink_lpf3: cc23x0r5: Add missing support for Zephyr - Add some driverlib files to CMakeLists. - Add CLKCTL driver. - Add VIMS functionality for flash. VIMS function API is needed to enable/disable buffers and check for activity before read/write/erase. - Extend GPIO functionality with GPIOSetConfigDio and GPIOGetConfigDio. - Add UARTEnable. - Add support for DMA mode in ADC driver. Add support to ADC API for DMA Trigger Event Publisher (INT_EVENT2). The ADC module provides four interrupt sources (one for each conversion result storage register) that can be configured to source the DMA trigger. Signed-off-by: Stoyan Bogdanov Signed-off-by: Julien Panis --- .../source/ti/devices/cc23x0r5/CMakeLists.txt | 5 + .../ti/devices/cc23x0r5/driverlib/adc.h | 120 ++++++ .../ti/devices/cc23x0r5/driverlib/clkctl.h | 197 ++++++++++ .../ti/devices/cc23x0r5/driverlib/gpio.h | 40 ++ .../ti/devices/cc23x0r5/driverlib/uart.c | 11 + .../ti/devices/cc23x0r5/driverlib/uart.h | 13 + .../ti/devices/cc23x0r5/driverlib/vims.c | 174 +++++++++ .../ti/devices/cc23x0r5/driverlib/vims.h | 369 ++++++++++++++++++ 8 files changed, 929 insertions(+) create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.c create mode 100644 simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.h diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt index 2b2db566..c93485e3 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt @@ -44,6 +44,11 @@ zephyr_library_sources( driverlib/lrfd.c driverlib/setup.c driverlib/uart.c + driverlib/spi.c + driverlib/vims.c + driverlib/adc.c + driverlib/cpu.c + driverlib/i2c.c ) # RF patches diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h index 0c0bfea5..76b2360a 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h @@ -587,6 +587,126 @@ __STATIC_INLINE void ADCClearInterrupt(uint32_t intFlags) HWREG(ADC_BASE + ADC_O_ICLR0) = intFlags; } +//***************************************************************************** +// +//! \brief Enable DMA trigger for data transfer. +//! +//! This function enables DMA trigger for data transfer. DMAEN bit is cleared by hardware +//! based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN +//! bit for ADC to generate DMA triggers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCEnableDMATrigger(void) +{ + HWREG(ADC_BASE + ADC_O_CTL2) |= ADC_CTL2_DMAEN; +} + +//***************************************************************************** +// +//! \brief Enables individual ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2). +//! +//! This function enables the indicated ADC interrupt sources (INT_EVENT2). +//! +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCEnableDMAInterrupt(uint32_t intFlags) +{ + // Enable the specified interrupts. + HWREG(ADC_BASE + ADC_O_IMASK2) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2). +//! +//! This function disables the indicated ADC interrupt sources (INT_EVENT2). +//! +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCDisableDMAInterrupt(uint32_t intFlags) +{ + // Disable the specified interrupts. + HWREG(ADC_BASE + ADC_O_IMASK2) &= ~(intFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current raw interrupt status for DMA Trigger Event Publisher (INT_EVENT2). +//! +//! This function returns the raw interrupt status for the ADC (INT_EVENT2). +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCRawDMAInterruptStatus(void) +{ + return (HWREG(ADC_BASE + ADC_O_RIS2)); +} + +//***************************************************************************** +// +//! \brief Gets the current masked interrupt status for DMA Trigger Event Publisher (INT_EVENT2). +//! +//! This function returns the masked interrupt status for the ADC (INT_EVENT2). +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +// +//***************************************************************************** +__STATIC_INLINE uint32_t ADCMaskedDMAInterruptStatus(void) +{ + return (HWREG(ADC_BASE + ADC_O_MIS2)); +} + +//***************************************************************************** +// +//! \brief Clears ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2). +//! +//! The specified ADC interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any +//! synchronizers) +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void ADCClearDMAInterrupt(uint32_t intFlags) +{ + // Clear the requested interrupt sources + HWREG(ADC_BASE + ADC_O_ICLR2) = intFlags; +} + //***************************************************************************** // //! \brief Returns ADC gain value for given reference diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h new file mode 100644 index 00000000..bca93ba2 --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * Filename: clkctl.h + * + * Description: Defines and prototypes for the Clock Control (CLKCTL). + * + * Copyright (c) 2024 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __CLKCTL_H__ +#define __CLKCTL_H__ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup clkctl_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_clkctl.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Values that can be passed to CLKCTLEnable() and CLKCTLDisable(). +// +//***************************************************************************** +#define CLKCTL_LGPT3 CLKCTL_CLKENSET0_LGPT3 //!< Configure LGPT3 clock enable +#define CLKCTL_LGPT2 CLKCTL_CLKENSET0_LGPT2 //!< Configure LGPT2 clock enable +#define CLKCTL_LGPT1 CLKCTL_CLKENSET0_LGPT1 //!< Configure LGPT1 clock enable +#define CLKCTL_LGPT0 CLKCTL_CLKENSET0_LGPT0 //!< Configure LGPT0 clock enable +#define CLKCTL_DMA CLKCTL_CLKENSET0_DMA //!< Configure DMA clock enable +#define CLKCTL_LAES CLKCTL_CLKENSET0_LAES //!< Configure LAES clock enable +#define CLKCTL_ADC0 CLKCTL_CLKENSET0_ADC0 //!< Configure ADC0 clock enable +#define CLKCTL_SPI0 CLKCTL_CLKENSET0_SPI0 //!< Configure SPI0 clock enable +#define CLKCTL_I2C0 CLKCTL_CLKENSET0_I2C0 //!< Configure I2C0 clock enable +#define CLKCTL_UART0 CLKCTL_CLKENSET0_UART0 //!< Configure UART0 clock enable +#define CLKCTL_LRFD CLKCTL_CLKENSET0_LRFD //!< Configure LRFD clock enable +#define CLKCTL_GPIO CLKCTL_CLKENSET0_GPIO //!< Configure GPIO clock enable + +//***************************************************************************** +// +// API Functions and prototypes. +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks clock control base address. +//! +//! This function determines if a clock controle base address is valid. +//! +//! \param base specifies the clock control base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool CLKCTLBaseValid(uint32_t base) +{ + return (base == CLKCTL_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the clock for a peripheral. +//! +//! This function enables the clock for a peripheral. +//! +//! \param base specifies the clock control base address. +//! \param peripheral specifies the peripheral. +//! The parameter can be one of the following values: +//! - \ref CLKCTL_LGPT3 +//! - \ref CLKCTL_LGPT2 +//! - \ref CLKCTL_LGPT1 +//! - \ref CLKCTL_LGPT0 +//! - \ref CLKCTL_DMA +//! - \ref CLKCTL_LAES +//! - \ref CLKCTL_ADC0 +//! - \ref CLKCTL_SPI0 +//! - \ref CLKCTL_I2C0 +//! - \ref CLKCTL_UART0 +//! - \ref CLKCTL_LRFD +//! - \ref CLKCTL_GPIO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CLKCTLEnable(uint32_t base, uint32_t peripheral) +{ + // Check the arguments + ASSERT(CLKCTLBaseValid(base)); + + // Read-modify-write the set bit + HWREG(base + CLKCTL_O_CLKENSET0) |= peripheral; +} + +//***************************************************************************** +// +//! \brief Disables the clock for a peripheral. +//! +//! This function disables the clock for a peripheral. +//! +//! \param base specifies the clock control base address. +//! \param peripheral specifies the peripheral. +//! The parameter can be one of the following values: +//! - \ref CLKCTL_LGPT3 +//! - \ref CLKCTL_LGPT2 +//! - \ref CLKCTL_LGPT1 +//! - \ref CLKCTL_LGPT0 +//! - \ref CLKCTL_DMA +//! - \ref CLKCTL_LAES +//! - \ref CLKCTL_ADC0 +//! - \ref CLKCTL_SPI0 +//! - \ref CLKCTL_I2C0 +//! - \ref CLKCTL_UART0 +//! - \ref CLKCTL_LRFD +//! - \ref CLKCTL_GPIO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void CLKCTLDisable(uint32_t base, uint32_t peripheral) +{ + // Check the arguments + ASSERT(CLKCTLBaseValid(base)); + + // Read-modify-write the clear bit + HWREG(base + CLKCTL_O_CLKENCLR0) |= peripheral; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** + +#endif // __CLKCTL_H__ diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h index 595c859e..44a8acb2 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h @@ -581,6 +581,46 @@ __STATIC_INLINE void GPIOClearEventMultiDio(uint32_t dioMask) HWREG( GPIO_BASE + GPIO_O_ICLR ) = dioMask; } +//***************************************************************************** +// +//! \brief Set configuration to DIO. +//! +//! \param iocfgRegAddr is address where config should be written +//! \param config is the configuration to be written +//! \return None +//! +//! \sa \ref GPIOGetConfigDio() +// +//***************************************************************************** +__STATIC_INLINE void GPIOSetConfigDio(uint32_t iocfgRegAddr, uint32_t config) +{ + // Check the arguments. + ASSERT(iocfgRegAddr); + + // Set the specified DIO config. + HWREG( iocfgRegAddr ) = config; +} + +//***************************************************************************** +// +//! \brief Get configuration for DIO. +//! +//! \param iocfgRegAddr is address from where config should be read +//! +//! \return Raw register value +//! +//! \sa \ref GPIOSetConfigDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t GPIOGetConfigDio(uint32_t iocfgRegAddr) +{ + // Check the arguments. + ASSERT(iocfgRegAddr); + + // Return Raw register value. + return HWREG( iocfgRegAddr ); +} + //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c index 5638a3a6..91586129 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.c @@ -78,6 +78,17 @@ void UARTDisable(uint32_t base) HWREG(base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE); } +//***************************************************************************** +// +// Enable UART +// +//***************************************************************************** +void UARTEnable(uint32_t base) +{ + // Enable the UART. + HWREG(base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE); +} + //***************************************************************************** // // Blocks until a character is available, and returns it diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h index 958d53f3..13b0ca66 100644 --- a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/uart.h @@ -225,6 +225,19 @@ extern void UARTConfigSetExpClk(uint32_t base, uint32_t UARTClkFreq, uint32_t ba //***************************************************************************** extern void UARTDisable(uint32_t base); +//***************************************************************************** +// +//! \brief Enable transmitting and receiving. +//! +//! This function enable UARTEN, TXE and RXE. +//! +//! \param base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTEnable(uint32_t base); + //***************************************************************************** // //! \brief Enables the transmit and receive FIFOs. diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.c b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.c new file mode 100644 index 00000000..a3c46c9a --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.c @@ -0,0 +1,174 @@ +/****************************************************************************** +* Filename: vims.c +* +* Description: Driver for the VIMS. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "vims.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef VIMSConfigure + #define VIMSConfigure NOROM_VIMSConfigure + #undef VIMSModeSet + #define VIMSModeSet NOROM_VIMSModeSet + #undef VIMSModeGet + #define VIMSModeGet NOROM_VIMSModeGet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +//***************************************************************************** +// +// Safe setting of new VIMS mode +// - Function might be blocking +// - Can be called for any mode change (also if actually not changing mode) +// +//***************************************************************************** +void +VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) +{ + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREG( VIMS_BASE + VIMS_O_STAT) & VIMS_STAT_MODE_CHANGING_BITN ) { + // Do nothing - wait for change to complete. + } + } + } +} diff --git a/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.h b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.h new file mode 100644 index 00000000..a01dcf9f --- /dev/null +++ b/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/vims.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* Filename: vims.h +* +* Description: Defines and prototypes for the VIMS. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup vims_api +//! @{ +// +//***************************************************************************** + +#ifndef __VIMS_H__ +#define __VIMS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif +#define DOXYGEN +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_vims.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define VIMSConfigure NOROM_VIMSConfigure + #define VIMSModeSet NOROM_VIMSModeSet + #define VIMSModeGet NOROM_VIMSModeGet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, +// and returned from VIMSModeGet(). +// +//***************************************************************************** +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE + // can not be changed at moment. +#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a VIMS base address. +//! +//! This function determines if the VIMS base address is valid. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +VIMSBaseValid(uint32_t ui32Base) +{ + return(ui32Base == VIMS_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the VIMS. +//! +//! This function sets general control settings of the VIMS system. +//! +//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param bRoundRobin specifies the arbitration method. +//! - \c true : Round Robin arbitration between the two available read/write interfaces +//! (i.e. Icode/Dcode and Sysbus) is to be used. +//! - \c false : Strict arbitration will be used, where Icode/Dcode +//! is preferred over the Sysbus. +//! \param bPrefetch specifies if prefetching is to be used. +//! - \c true : Cache is to prefetch tag data for the following address. +//! - \c false : No prefetch. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, + bool bPrefetch); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS. +//! +//! This function sets the operational mode of the VIMS. +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational. +//! Reads and writes to flash will be uncached. +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in \ref VIMSModeSafeSet() +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. Once \ref VIMSModeSet() is used to set the VIMS in +//! \ref VIMS_MODE_CHANGING mode, the user should check using +//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when +//! the mode has changed the cache has been completely invalidated. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32Mode is the operational mode. +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \return None +//! +//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() +// +//***************************************************************************** +extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Get the current operational mode of the VIMS. +//! +//! This function returns the operational mode of the VIMS. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns one of: +//! - \ref VIMS_MODE_CHANGING +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern uint32_t VIMSModeGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS in a safe sequence. +//! +//! This function sets the operational mode of the VIMS in a safe sequence +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational (read/write to flash will be uncached). +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in this function. +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32NewMode is the new operational mode: +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! \param blocking shall be set to TRUE if further code execution shall be +//! blocked (delayed) until mode change is completed. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() +// +//***************************************************************************** +extern void VIMSModeSafeSet( uint32_t ui32Base , + uint32_t ui32NewMode , + bool blocking ); + +//***************************************************************************** +// +//! \brief Disable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufDisable(uint32_t ui32Base) +{ + // Disable line buffers + HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M; +} + +//***************************************************************************** +// +//! \brief Enable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufEnable(uint32_t ui32Base) +{ + // Enable linebuffers + HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) +// #include "../driverlib/rom.h" + #ifdef ROM_VIMSConfigure + #undef VIMSConfigure + #define VIMSConfigure ROM_VIMSConfigure + #endif + #ifdef ROM_VIMSModeSet + #undef VIMSModeSet + #define VIMSModeSet ROM_VIMSModeSet + #endif + #ifdef ROM_VIMSModeGet + #undef VIMSModeGet + #define VIMSModeGet ROM_VIMSModeGet + #endif + #ifdef ROM_VIMSModeSafeSet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet ROM_VIMSModeSafeSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __VIMS_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** From d1e2ff8af16a0f7d6e7372b24a1aa7324bb160db Mon Sep 17 00:00:00 2001 From: Julien Panis Date: Fri, 6 Dec 2024 12:21:17 +0100 Subject: [PATCH 7/7] simplelink_lpf3: Add README.md Detail how this directory was generated and how someone can update to a newer SDK. Also add details on what upstream SDK version these sources were generated. Signed-off-by: Vebjorn Myklebust Signed-off-by: Julien Panis --- simplelink_lpf3/README.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 simplelink_lpf3/README.md diff --git a/simplelink_lpf3/README.md b/simplelink_lpf3/README.md new file mode 100644 index 00000000..c22ae90c --- /dev/null +++ b/simplelink_lpf3/README.md @@ -0,0 +1,23 @@ +# Simplelink LPF3 + +This folder contains the low-level support required from the +Simplelink LPF3 SDK. + +### Version + +The current version of simplelink_lpf3 is based on +[Simplelink LPF3 8.20.00](https://www.ti.com/tool/download/SIMPLELINK-LOWPOWER-F3-SDK/). + +Specifically, the following components have been used: +- Core SDK 8.10.01.04 +- RCL 8.20.01.04 + +## Contents + +The folder-structure herein reflects the folder-structure in the +Simplelink SDK. All files required to support Zephyr have been copied +manually from the Simplelink SDK, with the exception of DPL files under +`kernel/zephyr/dpl`, which are original and maintained in this repository. + +When updating to a new SDK, a comparison of the files in the 'devices' +and 'drivers' directories should be performed to pick up any new changes.